ADV7176A* [ADI]
High Quality. 10-Bit. Digital CCIR-601 to PAL/NTSC Video Encoder ; 高质量。 10位。数字CCIR -601至PAL / NTSC视频编码器
| 型号： | ADV7176A* |
| 厂家： | 
ADI |
| 描述： | High Quality. 10-Bit. Digital CCIR-601 to PAL/NTSC Video Encoder
|
| 文件： | 总52页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Quality, 10-Bit, Digital CCIR-601
to PAL/NTSC Video Encoder
a
ADV7175A/ADV7176A*
FEATURES
Program m able LUMA Delay
ITU-R BT601/ 656 YCrCb to PAL/ NTSC Video Encoder
High Quality 10-Bit Video DACs
Integral Nonlinearity <1 LSB at 10 Bits
NTSC-M, PAL-M/ N, PAL-B/ D/ G/ H/ I
Single 27 MHz Clock Required (
؋
2 Oversam pling) 80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Com posite (CVBS)
Com ponent S-Video (Y/ C)
Com ponent YUV and RGB
EuroSCART Output (RGB + CVBS/ LUMA)
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Form at
4:2:2 16-Bit Parallel Input Form at
Individual ON/ OFF Control of Each DAC
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
Color Signal Control/ Burst Signal Control
Interlaced/ Noninterlaced Operation
Com plete On-Chip Video Tim ing Generator
Program m able Multim ode Master/ Slave Operation
Macrovision Antitaping Rev 7.01 (ADV7175A Only)**
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
Onboard Color Bar Generation
Onboard Voltage Reference
2-Wire Serial MPU Interface (I2C Com patible)
Single Supply +5 V or + 3 V Operation
Sm all 44-Lead PQFP Therm ally Enhanced Package
SMPTE 170M NTSC Com patible Com posite Video
ITU-R BT.470 PAL Com patible Com posite Video
Full Video Output Drive or Low Signal Drive Capability
34.7 m A m ax into 37.5 ⍀ (Doubly-Term inated 75R)
5 m A m in w ith External Buffers
APPLICATIONS
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Cable System s (Set Top Boxes/ IRDs), Digital TVs,
CD Video/ Karaoke, Video Gam es, PC Video/ Multim edia
Program m able Sim ultaneous Com posite
GENERAL D ESCRIP TIO N
and S-Video Y/ C or RGB (SCART)/ YUV Video Outputs
Program m able Lum a Filters (Low -Pass/ Notch/ Extended)
Program m able VBI (Vertical Blanking Interval)
Program m able Subcarrier Frequency and Phase
T he ADV7175A/ADV7176A is an integrated digital video en-
coder that converts Digital CCIR-601 4:2:2 8 or 16-bit compo-
nent video data into a standard analog baseband television
(Continued on page 11)
FUNCTIO NAL BLO CK D IAGRAM
M
U
L
T
I
P
L
E
X
E
R
10
10
10
TELETEXT
INSERTION
BLOCK
TTX
10-BIT
DAC
DAC D (PIN 27)
DAC C (PIN 26)
DAC B (PIN 31)
TTXREQ
YUV TO
RBG
MATRIX
10-BIT
DAC
V
AA
10-BIT
DAC
Y
8
8
8
8
8
8
10
8
8
8
INTER-
POLATOR
ADD
SYNC
LOW-PASS
FILTER
COLOR
DATA
YCrCb
TO
YUV
P7–P0
4:2:2 TO
4:4:4
INTER-
U
10
10
8
INTER-
POLATOR
ADD
BURST
LOW-PASS
FILTER
10
P15–P8
10-BIT
DAC
MATRIX
POLATOR
DAC A (PIN 32)
V
8
8
INTER-
POLATOR
ADD
BURST
LOW-PASS
FILTER
ADV7175A/ADV7176A
10
10
HSYNC
FIELD/VSYNC
REAL-TIME
CONTROL
CIRCUIT
V
R
REF
VOLTAGE
REFERENCE
CIRCUIT
2
VIDEO TIMING
GENERATOR
I C MPU PORT
SIN/COS
DDS BLOCK
SET
BLANK
COMP
SCRESET/RTC
CLOCK
SCLOCK SDATA ALSB
GND
RESET
*Protected by U.S. patents numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**T his device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 and other intellectual property rights. T he Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOT E: IT U-R and CCIR are used interchangeably in this document (IT U-R has replaced CCIR recommendations).
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
ADV7175A/ADV7176A–SPECIFICATIONS
(V = +5 V ؎ 5%1, V = 1.235 V R = 150 ⍀. All specifications T to TMAX unless otherwise noted)
2
5 V SPECIFICATIONS
AA
REF
SET
MIN
P aram eter
Conditions1
Min
Typ
Max
Units
ST AT IC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
10
Bits
±1
±1
LSB
LSB
Differential Nonlinearity
Guaranteed Monotonic
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
2
V
V
µA
µA
pF
0.8
±1
±50
3
Input Current, IIN
Input Current, IIN
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
4
Input Capacitance, CIN
10
10
DIGIT AL OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
T hree-State Leakage Current
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
V
V
µA
pF
0.4
10
T hree-State Output Capacitance
ANALOG OUT PUT S
Output Current5
33
0
34.7
5
0.6
37
mA
mA
%
V
kΩ
pF
Output Current6
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
5
+1.4
15
IOUT = 0 mA
30
VOLT AGE REFERENCE
Reference Range, VREF
IVREFOUT = 20 µA
1.112
4.75
1.235
5.0
1.359
V
V
POWER REQUIREMENT S7
VAA
5.25
155
150
Normal Power Mode
IDAC (max)8
150
20
100
mA
mA
mA
IDAC (min)8
9
ICCT
Low Power Mode
IDAC (max)8
80
15
100
0.01
mA
mA
mA
%/%
IDAC (min)8
9
ICCT
150
0.5
Power Supply Rejection Ratio
COMP = 0.1 µF
NOT ES
1T he max/min specifications are guaranteed over this range. T he max/min values are typical over 4.75 V to 5.25 V.
2T emperature range T MIN to T MAX: 0°C to 70°C.
3All digital input pins except pins RESET and RT C/SCRESET .
4Excluding all digital input pins except pins RESET and RT C/SCRESET .
5Full drive into 37.5 Ω load.
6Minimum drive current (used with buffered/scaled output load).
7Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
8IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. T urning off individual
DACs reduces IDAC correspondingly.
9ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
–2–
REV. B
ADV7175A/ADV7176A
1
2
(V = +3.0 V – 3.6 V , V = 1.235 V R = 300 ⍀. All specifications T to TMAX unless otherwise noted)
3.3 V SPECIFICATIONS
AA
REF
SET
MIN
P aram eter
Conditions1
Min
Typ
Max
Units
ST AT IC PERFORMANCE3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
10
Bits
±1
±1
LSB
LSB
Differential Nonlinearity
Guaranteed Monotonic
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
2
0.8
V
V
µA
µA
pF
3, 4
Input Current, IIN
Input Current, IIN
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
±1
±50
3, 5
Input Capacitance, CIN
10
DIGIT AL OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
T hree-State Leakage Current3
T hree-State Output Capacitance3
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
0.4
V
V
µA
pF
10
10
ANALOG OUT PUT S3
Output Current6, 7
16.5
0
17.35
5
2.0
18.5
mA
mA
%
V
kΩ
pF
Output Current8
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
+1.4
30
15
IOUT = 0 mA
POWER REQUIREMENT S3, 9
VAA
3.0
3.3
3.6
V
Normal Power Mode
IDAC (max)10
150
20
45
155
mA
mA
mA
IDAC (min)10
9
ICCT
Low Power Mode
IDAC (max)10
75
15
45
0.01
mA
mA
mA
%/%
IDAC (min)10
11
ICCT
Power Supply Rejection Ratio
COMP = 0.1 µF
0.5
NOT ES
11T he max/min specifications are guaranteed over this range. T he max/min values are typical over 3.0 V to 3.6 V.
12T emperature range T MIN to T MAX: 0°C to 70°C.
13
Guaranteed by characterization.
14All digital input pins except pins RESET and RT C/SCRESET .
15Excluding all digital input pins except pins RESET and RT C/SCRESET .
16Full drive into 37.5 Ω load.
17DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (R SET = 300 Ω and RL = 150 Ω.
18Minimum drive current (used with buffered/scaled output load).
19Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
10
I
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. T urning off individual
DAC
DACs reduces IDAC correspondingly.
11
I
(Circuit Current) is the continuous current required to drive the device.
CCT
Specifications subject to change without notice.
REV. B
–3–
ADV7175A/ADV7176A–SPECIFICATIONS
1
2
(V = +4.75 V – 5.25 V , V = 1.235 V RSET = 150 ⍀. All specifications TMIN to T
MAX
AA
REF
1
5 V DYNAMIC SPECIFICATIONS
unless otherwise noted.)
P aram eter
Conditions1
Min
Typ
Max
Units
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
NT SC Mode
>54 dB Attenuation
>3 dB Attenuation
NT SC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Normal Power Mode
Normal Power Mode
Lower Power Mode
Lower Power Mode
RMS
7.0
4.2
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degree
%
Degree
dB rms
dB p-p
dB rms
dB p-p
Degree
%
Passband Cutoff F3 dB
Differential Gain4
0.4
0.4
2.0
1.0
80
70
60
58
0.5
1.0
0.6
0.2
0.4
0.1
0.1
0.6
2.0
1.0
66
Differential Phase4
Differential Gain4
Differential Phase4
SNR4 (Pedestal)
SNR4 (Pedestal)
Peak Periodic
RMS
Peak Periodic
SNR4 (Ramp)
SNR4 (Ramp)
Hue Accuracy4
Color Saturation Accuracy4
Chroma Nonlinear Gain4
Chroma Nonlinear Phase4
Chroma Nonlinear Phase4
Chroma/Luma Intermod4
Chroma/Luma Intermod4
Chroma/Luma Gain Ineq4
Chroma/Luma Delay Ineq4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
Referenced to 40 IRE
NT SC
PAL
Referenced to 714 mV (NT SC)
Referenced to 700 mV (PAL)
±%
±Degree
±Degree
±%
±%
±%
ns
±%
dB
dB
63
NOT ES
1T he max/min specifications are guaranteed over this range. T he max/min values are typical over 4.75 V to 5.25 V.
2T emperature range T MIN to T MAX: 0°C to +70°C.
3T hese specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
4Guaranteed by characterization.
Specifications subject to change without notice.
–4–
REV. B
ADV7175A/ADV7176A
1
2
(V = +3.0 V – 3.6 V , V = 1.235 V RSET = 300 ⍀. All specifications TMIN to T
AA
REF
MAX
1
unless otherwise noted.)
3.3 V DYNAMIC SPECIFICATIONS
P aram eter
Conditions1
Min
Typ
Max
Units
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
NT SC Mode
>54 dB Attenuation
>3 dB Attenuation
NT SC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Normal Power Mode
Normal Power Mode
RMS
7.0
4.2
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degree
dB rms
dB p-p
dB rms
dB p-p
Degree
%
Passband Cutoff F3 dB
Differential Gain4
0.7
0.5
75
68
58
Differential Phase4
SNR4 (Pedestal)
SNR4 (Pedestal)
Peak Periodic
RMS
Peak Periodic
SNR4 (Ramp)
SNR4 (Ramp)
56
Hue Accuracy4
1.0
1.2
1.1
67
63
64
Color Saturation Accuracy4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
Chroma AM Noise4
Chroma PM Noise4
±%
dB
dB
dB
NT SC
NT SC
PAL
PAL
63
dB
NOT ES
1T he max/min specifications are guaranteed over this range. T he max/min values are typical over 3.0 V to 3.6 V.
2T emperature range T MIN to T MAX: 0°C to +70°C.
3T hese specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
4Guaranteed by characterization.
Specifications subject to change without notice.
REV. B
–5–
ADV7175A/ADV7176A
(V = 4.75 V – 5.25 V , V = 1.235 V RSET = 150 ⍀. All specifications TMIN to T 2 unless
1
AA
REF
MAX
5 V TIMING SPECIFICATIONS
otherwise noted.)
P aram eter
Conditions
Min
Typ
Max
Units
MPU PORT3, 4
SCLOCK Frequency
0
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold T ime (Start Condition), t3
Setup T ime (Start Condition), t4
Data Setup T ime, t5
SDAT A, SCLOCK Rise T ime, t6
SDAT A, SCLOCK Fall T ime, t7
Setup T ime (Stop Condition), t8
4.0
4.7
4.0
4.7
250
After T his Period the First Clock Is Generated
Relevant for Repeated Start Condition
1
300
4.7
ANALOG OUT PUT S3, 5
Analog Output Delay
DAC Analog Output Skew
5
0
ns
ns
CLOCK CONT ROL
AND PIXEL PORT3, 6
FCLOCK
27
MHz
Clock High T ime, t9
Clock Low T ime, t10
Data Setup T ime, t11
Data Hold T ime, t12
Control Setup T ime, t11
Control Hold T ime, t12
Digital Output Access T ime, t13
Digital Output Hold T ime, t14
Pipeline Delay, t15
8
8
3.5
4
4
ns
ns
ns
ns
ns
ns
ns
ns
3
24
4
37
Clock Cycles
T ELET EXT PORT3, 7
Digital Output Access T ime, t16
Data Setup T ime, t17
20
1
2
ns
ns
ns
Data Hold T ime, t18
RESET CONT ROL3, 4
RESET Low T ime
6
ns
NOT ES
1T he max/min specifications are guaranteed over this range.
2T emperature range T MIN to T MAX: 0oC to +70oC.
3T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
Clock Input:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
7T eletext Port consists of the following:
T eletext Output:
T eletext Input:
T T XREQ
T T X
Specifications subject to change without notice.
–6–
REV. B
ADV7175A/ADV7176A
(V = 3.0 – 3.61, V = 1.235 V RSET = 300 ⍀. All specifications TMIN to T 2 unless
AA
REF
MAX
otherwise noted.)
3.3 V TIMING SPECIFICATIONS
P aram eter
Conditions
Min
Typ
Max
Units
MPU PORT3, 4
SCLOCK Frequency
0
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold T ime (Start Condition), t3
Setup T ime (Start Condition), t4
Data Setup T ime, t5
SDAT A, SCLOCK Rise T ime, t6
SDAT A, SCLOCK Fall T ime, t7
Setup T ime (Stop Condition), t8
4.0
4.7
4.0
4.7
250
After T his Period the First Clock Is Generated
for Repeated Start Condition
1
300
4.7
ANALOG OUT PUT S3, 5
Analog Output Delay
DAC Analog Output Skew
7
0
ns
ns
CLOCK CONT ROL
AND PIXEL PORT3, 4, 6, 7
FCLOCK
27
MHz
Clock High T ime, t9
Clock Low T ime, t10
Data Setup T ime, t11
Data Hold T ime, t12
Control Setup T ime, t11
Control Hold T ime, t12
Digital Output Access T ime, t13
Digital Output Hold T ime, t14
Pipeline Delay, t15
8
8
3.5
4
4
ns
ns
ns
ns
ns
ns
ns
ns
3
24
4
37
Clock Cycles
T ELET EXT PORT3, 6, 8
Digital Output Access T ime t16
Data Setup T ime, t17
23
2
2
ns
ns
ns
Data Hold T ime, t18
RESET CONT ROL3, 4
RESET Low T ime
6
ns
NOT ES
1T he max/min specifications are guaranteed over this range.
2T emperature range T MIN to T MAX: 0oC to +70oC.
3T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Characterized by design.
7Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
Clock Input:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
8T eletext Port consists of the following:
T eletext Output:
T eletext Input:
T T XREQ
T T X
Specifications subject to change without notice.
REV. B
–7–
ADV7175A/ADV7176A
t5
t3
t3
SDATA
t6
t1
SCLOCK
t2
t7
t4
t8
Figure 1. MPU Port Tim ing Diagram
CLOCK
t12
t9
t10
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
I/PS
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb
Y
t11
t13
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
O/PS
t14
Figure 2. Pixel and Control Data Tim ing Diagram
TXTREQ
CLOCK
t16
t17
t18
TXT
3 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 3. Teletext Tim ing Diagram
–8–
REV. B
ADV7175A/ADV7176A
P ACKAGE TH ERMAL P ERFO RMANCE
ABSO LUTE MAXIMUM RATINGS1
T he 44-PQFP package used for this device takes advantage of
an ADI patented thermal coastline lead frame construction.
T his maximizes heat transfer into the leads and reduces the
package thermal resistance.
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C
Analog Outputs to GND2 . . . . . . . . . . . . . GND – 0.5 to VAA
T he junction-to-ambient (θJA) thermal resistance in still air on a
four-layer PCB is 35.5°C/W. T he junction-to-case thermal
resistance (θJC) is 13.75°C/W.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Analog output short circuit to any power supply or common can be of an indefinite
duration.
O RD ERING GUID E
Tem perature P ackage
Range D escription
P ackage
O ption
Model
ADV7175AKS 0°C to +70°C Plastic Quad Flatpack S-44
ADV7176AKS 0°C to +70°C Plastic Quad Flatpack S-44
P IN CO NFIGURATIO N
44 43 42 41 40 39 38 37 36 35 34
1
2
33
V
V
AA
REF
PIN 1
IDENTIFIER
32 DAC A
31 DAC B
P5
P6
3
4
30
V
P7
AA
29 GND
5
P8
ADV7175A/ADV7176A
PQFP
6
28
27
P9
V
AA
TOP VIEW
(Not to Scale)
7
DAC D
P10
P11
P12
GND
8
26 DAC C
25 COMP
24 SDATA
9
10
11
V
23
SCLOCK
AA
13
12
14 15 16 17 18 19
21 22
20
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175A/ADV7176A feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, pr oper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–9–
ADV7175A/ADV7176A
P IN FUNCTIO N D ESCRIP TIO NS
Input/
P in
No.
Mnem onic
O utput
Function
1, 11, 20,
28, 30
VAA
P
Power Supply (+3 V to +5 V).
Ground Pin.
10, 19, 21,
29, 43
GND
G
15
HSYNC
I/O
HSYNC (Modes 1 and 2) Control Signal. T his pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
16
FIELD/VSYNC
I/O
I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. T his
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
17
BLANK
Video Blanking Control Signal. T he pixel inputs are ignored when this is
logic level “0.” T his signal is optional.
18
22
ALSB
I
I
T T L Address Input. T his signal sets up the LSB of the MPU address.
RESET
T he input resets the on chip timing generator and sets the ADV7175A/
ADV7176A into default mode. T his is NT SC operation, T iming Slave Mode
0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on.
23
24
25
SCLOCK
SDAT A
COMP
I
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
I/O
O
Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA. For
Optimum Dynamic Performance in Low Power Mode, the value of the
COMP capacitor can be lowered to as low as 2.2 nF.
26
27
31
32
DAC C
DAC D
DAC B
DAC A
O
O
O
O
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
PAL/NT SC Composite Video Output. Full-Scale Output is 180IRE (1286
mV) for NT SC and 1300 mV for PAL.
33
34
VREF
RSET
I/O
I
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the video signals.
35
SCRESET /RT C
I
T his pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a high
to low transition on this pin will reset the subcarrier to Field 0. Alternatively
it may be configured as a Real T ime Control (RT C) input.
36
37
T T XREQ/GND
T T X/VAA
P0–P15
O
I
T eletext Data Request Signal/Defaults to GND when T eletext not selected
(enables backward compatibility to ADV7175/ADV7176).
T eletext Data/Defaults to VAA when T eletext not selected (enables backward
compatibility to ADV7175/ADV7176).
38–42
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
2–9, 12–14
16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.
44
CLOCK
I
T T L Clock Input. Requires a stable 27 MHz reference Clock for standard
operation. Alternatively, a 24.52 MHz (NT SC) or 29.5 MHz (PAL) can be
used for square pixel operation.
–10–
REV. B
ADV7175A/ADV7176A
(Continued from page 1)
D ATA P ATH D ESCRIP TIO N
For PAL B, D, G, H, I, M, N and NT SC M modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz Data Rate. T he pixel data is demultiplexed to from
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. T he
ADV7175A/ADV7176A supports PAL (B, D, G, H, I, N, M)
and NT SC (with and without Pedestal) standards. T he ap-
propriate SYNC, BLANK and Burst levels are added to the
YCrCb data. Macrovision antitaping (ADV7175A only),
closed captioning and teletext levels are also added to Y, and
the resultant data is interpolated to a rate of 27 MHz. T he
interpolated data is filtered and scaled by three digital FIR
filters.
signal compatible with worldwide standards. T he 4:2:2 YUV
video data is interpolated to two times the pixel rate. T he
color-difference components (UV) are quadrature modulated
using a subcarrier frequency generated by an on-chip 32-bit
digital synthesizer (also running at two times the pixel rate).
T he two times pixel rate sampling allows for better signal-to-
noise-ratio. A 32-bit DDS with a 10-bit look-up table produces
a superior subcarrier in terms of both frequency and phase. In
addition to the composite output signal, there is the facility to
output S-Video (Y/C) video, YUV or RGB video. T he Y/C,
YUV or RGB format is simultaneously available at the analog
outputs with the composite video signal.
Each analog output is capable of driving the full video-level
(35 mA) signal into an unbuffered, doubly terminated 75 Ω
load. With external buffering, the user has the additional option
to scale back the DAC output current to 5 mA min, thereby signifi-
cantly reducing the power dissipation of the device.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi-
nance signal. T he luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
T he luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The ADV7175A/ADV7176A also supports both PAL and NTSC
square pixel operation.
T he output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing signals.
T hese timing signals can be adjusted to change pulsewidth and
position while the part is in the master mode. T he encoder
requires a single two times pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.54 MHz clock
for NT SC or 29.5 MH z clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
T he YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. T he RGB data is in
synchronization with the composite video output. Alternatively
analog YUV data can be generated instead of RGB.
T he four 10-bit DACs can be used to output:
1. Composite Video + RGB Video.
2. Composite Video + YUV Video
3. T wo Composite Video Signals + LUMA and CHROMA
3. (Y/C) Signals.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
Alternatively, each DAC can be individually powered off if not
required.
T he ADV7175A/ADV7176A modes are set up over a two-wire
serial bidirectional port (I2C Compatible) with two slave addresses.
Video output levels are illustrated in Appendix 4 and Appendix 5.
Functionally the ADV7175A and ADV7176A are the same with
the exception that the ADV7175A can output the Macrovision
anticopy algorithm.
INTERNAL FILTER RESP O NSE
T he Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low pass responses, PAL/
NT SC subcarrier notch responses and a PAL/NT SC extended
response. T he U and V filters have a 2/2.4 MHz low-pass
response for NT SC/PAL. T hese filter characteristics are illus-
trated in Figures 4 to 12.
T he ADV7175A/ADV7176A is packaged in a 44-lead thermally
enhanced PQFP package.
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
F
3dB
FILTER SELECTION
MR04
MR03
NTSC
PAL
NTSC
PAL
NTSC/PAL
NTSC
PAL
0
0
0
0
1
1
1
0
0
1
1
0
1
1
2.3
3.4
1.0
1.4
4.0
2.3
3.4
0.026
0.098
0.085
0.107
0.150
0.054
0.106
7.0
7.3
3.57
4.43
7.5
>
>
>
>
>
>
>
54
50
27.6
29.3
40
4.2
5.0
2.1
2.7
5.65
4.2
5.0
7.0
7.3
54
50.3
Figure 4. Lum inance Internal Filter Specifications
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
ATTENUATION @
1.3MHz (dB)
F
3dB
FILTER SELECTION
NTSC
PAL
1.0
1.3
0.085
0.04
3.2
4.0
>
40
40
0.3
0.02
2.05
2.45
>
Figure 5. Chrom inance Internal Filter Specifications
–11–
REV. B
ADV7175A/ADV7176A
0
–10
–20
0
–10
TYPE A
–20
–30
–40
–50
–60
–30
–40
–50
–60
TYPE B
10
0
2
4
6
8
10
12
0
2
4
6
8
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 9. PAL Notch Filter
Figure 6. NTSC Low-Pass Filter
0
–10
–20
–10
–20
–30
–40
–50
–60
–30
–40
–50
–60
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 10. NTSC/PAL Extended Mode Filter
Figure 7. NTSC Notch Filter
0
0
–10
–10
TYPE B
–20
–30
–40
–50
–60
–20
–30
–40
–50
–60
TYPE A
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 11. NTSC UV Filter
Figure 8. PAL Low-Pass Filter
–12–
REV. B
ADV7175A/ADV7176A
0
–10
–20
SUBCARRIER RESET
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used in subcarrier reset mode. T he subcarrier will reset to
Field 0 at the start of the following field when a low to high
transition occurs on this input pin.
–30
–40
–50
–60
REAL TIME CO NTRO L
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used to lock to an external video source. T he real time control
mode allows the ADV7175A/ADV7176A to automatically alter
the subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
datastream in the RT C format (such as an ADV7185 video
decoder [see Figure 13]), the part will automatically change to
the compensated subcarrier frequency on a line by line basis.
T his digital datastream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles long.
00HEX should be written to all four subcarrier frequency regis-
ters when using this mode.
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 12. PAL UV Filter
CO LO R BAR GENERATIO N
T he ADV7175A/ADV7176A can be configured to generate
75% amplitude, 75% saturation (75/7.5/75/7.5) for NT SC or
75% amplitude, 100% saturation (100/0/75/0) for PAL color
bars. T hese are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
VID EO TIMING D ESCRIP TIO N
T he ADV7175A/ADV7176A is intended to interface to off-
the-shelf MPEG1 and MPEG2 Decoders. Consequently, the
ADV7175A/ADV7176A accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. T he ADV7175A/ADV7176A generates all of the
required horizontal and vertical timing periods and levels for the
analog video outputs.
SQ UARE P IXEL MO D E
T he ADV7175A/ADV7176A can be used to operate in square
pixel mode. For NT SC operation an input clock of 24.5454
MHz is required. Alternatively an input clock of 29.5 MHz is
required for PAL operation. T he internal timing logic adjusts
accordingly for square pixel mode operation.
CO LO R SIGNAL CO NTRO L
T he color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
T he ADV7175A/ADV7176A calculates the width and place-
ment of analog sync pulses, blanking levels and color burst
envelopes. Color bursts are disabled on appropriate lines, and
serration and equalization pulses are inserted where required.
BURST SIGNAL CO NTRO L
T he burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
In addition the ADV7175A/ADV7176A supports a PAL or
NT SC square pixel operation in slave mode. T he part requires
an input pixel clock of 24.5454 MHz for NT SC and an input
pixel clock of 29.5 MHz for PAL. T he internal horizontal line
counters place the various video waveform sections in the cor-
rect location for the new clock frequencies.
NTSC P ED ESTAL CO NTRO L
T he pedestal on both odd and even fields can be controlled on a
line by line basis using the NT SC Pedestal Control Registers.
T his allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
T he ADV7175A/ADV7176A has four distinct master and four
distinct slave timing configurations. T iming Control is estab-
lished with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. T iming Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.
P IXEL TIMING D ESCRIP TIO N
The ADV7175A/ADV7176A can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCr Cb Mode
T his default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. T he inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. T he Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCr Cb Mode
T his mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. T he
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
REV. B
–13–
ADV7175A/ADV7176A
CLOCK
COMPOSITE
VIDEO
e.g., VCR
SCRESET/RTC
VIDEO
DECODER
(e.g., ADV7185)
GREEN/LUMA/Y
RED/CHROMA/V
M
U
X
OR CABLE
P7–P0
BLUE/COMPOSITE/U
COMPOSITE
MPEG
DECODER
HSYNC
FIELD/VSYNC
ADV7175A/ADV7176A
SEQUENCE
RESERVED
2
BIT
H/LTRANSITION
COUNT START
RESET
4 BITS
RESERVED
5 BITS
RESERVED
3
BIT
LOW
14 BITS
RESERVED
128
1
FSCPLL INCREMENT
0
0
13
21
RTC
TIME SLOT: 01
6768
14
19
NOT USED IN
ADV7175A/ADV7176A
VALID
SAMPLE SAMPLE
INVALID
8/LLC
NOTES:
1
F
PLL INCREMENT IS 22 BITS LONG, VALUED LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUB CARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
SC
F
SC
BE WRITTEN TO THE SUB CARRIER FREQUENCY REGISTERS OF THE ADV7175A/ADV7176A.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE.
3
RESET BIT
RESET ADV7175A/ADV7176A’s DDS.
Figure 13. RTC Tim ing and Connections
Ver tical Blanking D ata Inser tion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization
pulses (see Figures 15 to 26). T his mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. T his data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
T he complete VBI comprises of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
T he “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave O ption
(T iming Register 0 T R0 = X X X X X 0 0 0)
T he ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel
data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. T he HSYNC, FIELD/VSYNC and
BLANK (if not used) pins should be tied high during this mode.
–14–
REV. B
ADV7175A/ADV7176A
ANALOG
VIDEO
EAV CODE
SAV CODE
C
r
C
b
C
b
8
0
0
0
F
F
F A
F B
A
B
A
B
8
0
0
0
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
INPUT PIXELS
Y
Y
Y
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
268 CLOCK
1440 CLOCK
1440 CLCOK
PAL SYSTEM
(625 LINES/50Hz)
280 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 14. Tim ing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master O ption
(T iming Register 0 T R0 = X X X X X 0 0 1)
T he ADV7175A/ADV7176A generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
time codes in the CCIR-656 standard. T he H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NT SC) and Figure 16 (PAL). T he H, V and F transitions
relative to the video waveform are illustrated in Figure 17.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
7
10
11
20
21
22
5
9
8
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
H
V
F
ODD FIELD
EVEN FIELD
Figure 15. Tim ing Mode 0 (NTSC Master Mode)
REV. B
–15–
ADV7175A/ADV7176A
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
22
23
5
21
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
335
336
318
334
309
310
311
312
313
314
315
316
317
319
320
H
V
F
ODD FIELD EVEN FIELD
Figure 16. Tim ing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
V
Figure 17. Tim ing Mode 0 Data Transitions (Master Mode)
Mode 1: Slave O ption HSYNC, BLANK, FIELD
(T iming Register 0 T R0 = X X X X X 0 1 0)
In this mode the ADV7175A/ADV7176A accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame i.e., vertical retrace. T he BLANK signal is optional. When the BLANK input is disabled
the ADV7175A/ADV7176A automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NT SC) and Fig-
ure 19 (PAL).
–16–
REV. B
ADV7175A/ADV7176A
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 18. Tim ing Mode 1 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD EVEN FIELD
Figure 19. Tim ing Mode 1 (PAL)
Mode 1: Master O ption HSYNC, BLANK, FIELD
(T iming Register 0 T R0 = X X X X X 0 1 1)
In this mode the ADV7175A/ADV7176A can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. T he BLANK signal is optional. When the BLANK input is
disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge
following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NT SC) and Figure 19 (PAL). Figure 20 illustrates the
HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
REV. B
–17–
ADV7175A/ADV7176A
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 20. Tim ing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave O ption HSYNC, VSYNC, BLANK
(T iming Register 0 T R0 = X X X X X 1 0 0 )
In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. T he BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NT SC) and Figure 22 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 21. Tim ing Mode 2 (NTSC)
–18–
REV. B
ADV7175A/ADV7176A
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD EVEN FIELD
Figure 22. Tim ing Mode 2 (PAL)
Mode 2: Master O ption HSYNC, VSYNC, BLANK
(T iming Register 0 T R0 = X X X X X 1 0 1)
In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start
of an even field. T he BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NT SC) and Figure 22 (PAL). Figure 23
illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 * CLOCK/2
BLANK
NTSC = 16 * CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 23. Tim ing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 24. Tim ing Mode 2 Odd-to-Even Field Transition Master/Slave
–19–
REV. B
ADV7175A/ADV7176A
Mode 3: Master /Slave O ption HSYNC, BLANK, FIELD
(T iming Register 0 T R0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7175A/ADV7176A accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. T he BLANK signal is optional. When the BLANK
input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated
in Figure 25 (NT SC) and Figure 26 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
5
6
7
8
9
10
11
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 25. Tim ing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 26. Tim ing Mode 3 (PAL)
–20–
REV. B
ADV7175A/ADV7176A
O UTP UT VID EO TIMING
applied. In this configuration the SCH phase will never be reset,
which means that the output video will now track the unstable
input video. T he subcarrier phase reset, when applied, will reset
the SCH phase to Field 0 at the start of the next field (e.g.,
subcarrier phase reset applied in Field 5 [PAL] on the start of
the next field SCH phase will be reset to Field 0).
T he video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. T hese sequences are summarized below. In slave
modes, the following sequences are synchronized with the input
timing control signals. In master modes, the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
MP U P O RT D ESCRIP TIO N
T he ADV7175A and ADV7176A support a two-wire serial (I2C
Compatible) microprocessor bus driving multiple peripherals.
T wo inputs, serial data (SDAT A) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. T he
ADV7175A and ADV7176A each have four possible slave
addresses for both read and write operations. T hese are unique
addresses for each device and are illustrated in Figure 27 and
Figure 28. T he LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7175A/ADV7176A to Logic Level “0” or
Logic Level “1.”
NTSC–Inter laced: Scan Lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan Lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for closed captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
NTSC–Noninter laced: Scan Lines 1–9 are always blanked,
and vertical sync pulses are included. Scan Lines 10–21 are also
blanked and can be used for closed captioning data. Burst is
disabled on Lines 1–6, 261–262.
P AL–Inter laced: Scan Lines 1–6, 311–318 and 624–625 are
always blanked, and vertical sync pulses are included in Fields
1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are al-
ways blanked, and vertical sync pulses are included in Fields 3,
4, 7 and 8. T he remaining scan lines in the vertical blanking
interval are also blanked and can be used for teletext data.
Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields
1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and
623–625 in Fields 3, 4, 7 and 8.
1
1
1
0
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
P AL–Noninter laced: Scan Lines 1–6 and 311–312 are always
blanked, and vertical sync pulses are included. T he remaining
scan lines in the vertical blanking interval are also blanked and
can be used for teletext data. Burst is disabled on Lines 1–5,
310–312.
0
1
WRITE
READ
Figure 27. ADV7175A Slave Address
P O WER-O N RESET
1
1
0
0
1
A1
X
0
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. T his initializes the pixel port so that the
pixel inputs, P7–P0 are selected. After reset, the ADV7175A/
ADV7176A is automatically set up to operate in NT SC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the
exception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR02. Bit
MR02 of Mode Register 0 is set to Logic “1.” T his enables the
7.5 IRE pedestal.
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 28. ADV7176A Slave Address
T o control the various devices on the bus, the following proto-
col must be followed: First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDAT A while SCLOCK remains high. T his indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). T he bits transfer from MSB down to LSB. T he pe-
ripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. T his is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. T he idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the start condition and the correct transmitted
address. T he R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
SCH P hase Mode
T he SCH phase is configured in default mode to reset every
four (NT SC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. T his effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7175A/ADV7176A is
configured in RT C mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video) the subcarrier phase reset
should be enabled MR22 = 0 and MR21 = 1) but no reset
REV. B
–21–
ADV7175A/ADV7176A
T he ADV7175A/ADV7176A acts as a standard slave device on
the bus. T he data on the SDAT A pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. T he ADV7175A has 33
subaddresses and the ADV7176A has 19 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. T he subaddresses auto increment allow data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. T he user can
also access any unique subaddress register on a one by one basis
without having to update all the registers. T here is one excep-
tion. T he subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. T he
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
return to the idle condition. If, in auto-increment mode the user
exceeds the highest subaddress, the following action will be
taken:
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. T his indicates the end of a read. A no-ac-
knowledge condition is where the SDAT A line is not pulled
low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175A/ADV7176A and the part will
return to the idle condition.
SDATA
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high pe-
riod, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7175A/ADV7176A will not issue an acknowledge and will
SCLOCK
S
1-7
8
9
1-7
8
9
1-7
DATA
8
9
P
START ADDR
ACK SUBADDRESS ACK
ACK
STOP
R/W
Figure 29. Bus Data Transfer
Figure 29 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
Figure 30 shows bus write and read sequences.
WRITE
SEQUENCE
S
SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
DATA
A(S)
DATA
A(M)
A(S) P
LSB = 1
READ
SEQUENCE
S
SLAVE ADDR A(S)
SUB ADDR A(S)
S
SLAVE ADDR A(S)
DATA
DATA
P
A(M)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 30. Write and Read Sequences
SR1
SR7
SR6
SR5
SR4
SR3
SR2
SR0
SR7–SR6 (00)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7176A SUBADDRESS REGISTER
ADV7175A SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
MODE REGISTER 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 0
CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 1
CLOSED CAPTIONING DATA Ϸ BYTE 0
CLOSED CAPTIONING DATA Ϸ BYTE 1
TIMING REGISTER 1
CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 0
CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 1
CLOSED CAPTIONING DATA Ϸ BYTE 0
CLOSED CAPTIONING DATA Ϸ BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
MACROVISION REGISTER
TTXRQ CONTROL REGISTER 0
"
"
"
"
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
•
•
•
•
•
•
1
1
0
0
0
0
0
1
1
0
1
0
MACROVISION REGISTER
TTXRQ CONTROL REGISTER 0
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
Figure 31. Subaddress Register
–22–
REV. B
ADV7175A/ADV7176A
REGISTER ACCESSES
MO D E REGISTER 0 MR0 (MR07–MR00)
T he MPU can write to or read from all of the ADV7175A/
ADV7176A registers except the subaddress register, which is a
write-only register. T he subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
(Addr ess [SR4–SR0] = 00H )
Figure 32 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
MR0 BIT D ESCRIP TIO N
Encode Mode Contr ol (MR01–MR00)
These bits are used to set up the encode mode. The ADV7175A/
ADV7176A can be set up to output NT SC, PAL (B, D, G, H, I)
and PAL (M) standard video.
REGISTER P RO GRAMMING
P edestal Contr ol (MR02)
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NT SC pedestal
control registers in terms of its configuration.
This bit specifies whether a pedestal is to be generated on
the NT SC composite video signal. T his bit is invalid if the
ADV7175A/ADV7176A is configured in PAL mode.
Lum inance Filter Contr ol (MR04–MR03)
T he luminance filters are divided into two sets (NT SC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NT SC is selected, bits MR03
and MR04 select one of four NT SC luminance filters. T he fil-
ters are illustrated in Figures 4 to 12.
Subaddr ess Register (SR7–SR0)
T he communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. T he subaddress
register determines to/from which register the operation takes
place.
RGB Sync (MR05)
T his bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
O utput Contr ol (MR06)
Register Select (SR5–SR0)
T hese bits are set up to point to the required starting address.
T his bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still avail-
able in RGB/YUV mode.
MR01
MR06
MR05
MR04
MR03
MR02
MR00
MR07
OUTPUT SELECT
MR06
FILTER SELECT
MR04 MR03
OUTPUT VIDEO
STANDARD SELECTION
MR01
MR00
0
1
YC OUTPUT
RGB/YUV OUTPUT
0
0
1
1
0
1
0
1
LOW PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW PASS FILTER (B)
0
0
1
1
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
RGB SYNC
MR07
(0)
PEDESTAL CONTROL
MR02
MR05
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
0
1
PEDESTAL OFF
PEDESTAL ON
Figure 32. Mode Register 0 (MR0)
MR11
MR17
MR16
MR15
MR14
MR13
MR12
MR10
DAC A
CONTROL
DAC D
CONTROL
CLOSED CAPTIONING
FIELD SELECTION
MR16
MR14
MR12
MR11
0
1
NORMAL
POWER-DOWN
0
1
NORMAL
POWER-DOWN
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
COLOR BAR
CONTROL
DAC B
CONTROL
DAC C
CONTROL
INTERLACE
CONTROL
MR15
MR13
MR10
MR17
0
1
INTERLACED
NONINTERLACED
0
1
NORMAL
POWER-DOWN
0
1
NORMAL
POWER-DOWN
0
1
DISABLE
ENABLE
Figure 33. Mode Register 1 (MR1)
–23–
REV. B
ADV7175A/ADV7176A
SUBCARRIER
FREQUENCY
REG 3
MO D E REGISTER 1 MR1 (MR17–MR10)
(Addr ess (SR4–SR0) = 01H )
FSC30
FSC31
FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
SUBCARRIER
FREQUENCY
REG 2
Figure 33 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
SUBCARRIER
FREQUENCY
REG 1
FSC14
FSC6
FSC15
FSC7
FSC13 FSC12 FSC11 FSC10 FSC9
FSC8
FSC0
MR1 BIT D ESCRIP TIO N
Inter laced Mode Contr ol (MR10)
T his bit is used to set up the output to interlaced or noninter-
laced mode. T his mode is only relevant when the part is in
composite video mode.
SUBCARRIER
FREQUENCY
REG 0
FSC5
FSC4
FSC3 FSC2 FSC1
Figure 34. Subcarrier Frequency Register
Closed Captioning Field Contr ol (MR12–MR11)
T hese bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
SUBCARRIER P H ASE REGISTER (FP 7–FP 0)
(Addr ess [SR4–SR0] = 06H )
T his 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.
D AC Contr ol (MR16–MR13)
T hese bits can be used to power down the DACs. T his can
be used to reduce the power consumption of the ADV7175A/
ADV7176A if any of the DACs are not required in the application.
TIMING REGISTER 0 (TR07–TR00)
(Addr ess [SR4–SR0] = 07H )
Figure 35 shows the various operations under the control of
T iming Register 0. T his register can be read from as well as
written to. T his register can be used to adjust the width and
position of the master mode timing signals.
Color Bar Contr ol (MR17)
T his bit can be used to generate and output an internal color
bar test pattern. T he color bar configuration is 75/7.5/75/7.5
for NT SC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7175A/ADV7176A is
configured in a master timing mode as per the one selected by
bits T R01 and T R02.
TR0 BIT D ESCRIP TIO N
Master /Slave Contr ol (TR00)
T his bit controls whether the ADV7175A/ADV7176A is in
master or slave mode.
SUBCARRIER FREQ UENCY REGISTER 3-0
(FSC3–FSC0)
Tim ing Mode Contr ol (TR02–TR01)
T hese bits control the timing mode of the AD V7175A/
ADV7176A. T hese modes are described in the T iming and
Control section of the data sheet.
(Addr ess [SR4–SR0] = 05H –02H )
T hese 8-bit wide registers are used to set up the subcarrier fre-
quency. T he value of these registers are calculated by using the
following equation:
BLANK Contr ol (TR03)
T his bit controls whether the BLANK input is used when the
part is in slave mode.
232 –1
× FSCF
Subcarrier Frequency Register =
FCLK
Lum a D elay Contr ol (TR05–TR04)
T hese bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
i.e.: NT SC Mode,
FCLK = 27 MHz,
FSCF = 3.5795454 MHz
P ixel P or t Select (TR06)
232 –1
27 ×106
T his bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on Pins
P7–P0.
× 3.5795454 ×106
Subcarrier Frequency Value =
= 21F07C16 HEX
Tim ing Register Reset (TR07)
Figure 34 shows how the frequency is set up by the four registers.
T oggling T R07 from low to high and low again resets the inter-
nal timing counters. T his bit should be toggled after power-up,
reset or changing to a new timing mode.
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
BLACK INPUT
CONTROL
TIMING
REGISTER RESET
MASTER/SLAVE
CONTROL
TR03
TR00
TR07
0
1
ENABLE
DISABLE
0
1
SLAVE TIMING
MASTER TIMING
PIXEL PORT
CONTROL
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
TR06
TR02 TR01
0
0
1
1
0
1
0
1
0ns DELAY
0
8-BIT
0
0
1
1
0
1
0
1
MODE 0
74ns DELAY
148ns DELAY
222ns DELAY
1
16-BIT
MODE 1
MODE 2
MODE 3
Figure 35. Tim ing Register 0
–24–
REV. B
ADV7175A/ADV7176A
CLO SED CAP TIO NING EVEN FIELD
TR1 BIT D ESCRIP TIO N
D ATA REGISTER 1–0 (CED 15–CED 00)
H SYNC Width (TR11–TR10)
(Addr ess [SR4–SR0] = 09–08H )
T hese bits adjust the HSYNC pulsewidth.
These 8-bit wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
HSYNC to VSYNC/FIELD D elay Contr ol (TR13–TR12)
T hese bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD D elay Contr ol (TR15–TR14)
When the ADV7175A/ADV7176A is in T iming Mode 1, these
bits adjust the position of the HSYNC output relative to the
FIELD output rising edge.
CED15 CED14 CED13 CED12 CED11 CED10
CED9
CED8
BYTE 1
CED7
CED6
CED5
CED4
CED3
CED2
CED1
CED0
BYTE 0
Figure 36. Closed Captioning Extended Data Register
VSYNC Width (TR15–TR14)
When the ADV7175A/ADV7176A is in T iming Mode 2, these
bits adjust the VSYNC pulsewidth.
CLO SED CAP TIO NING O D D FIELD
D ATA REGISTER 1–0 (CCD 15–CCD 00)
(Subaddr ess [SR4–SR0] = 0B–0AH )
These 8-bit wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
HSYNC to P ixel D ata Adjust (TR17–TR16)
T his enables the HSYNC to be adjusted with respect to the
pixel data. T his allows the Cr and Cb components to be
swapped. T his adjustment is available in both master and slave
timing modes.
CCD15
CCD14 CCD13 CCD12 CCD11 CCD10
CCD9
CCD8
BYTE 1
MO D E REGISTER 2 MR2 (MR27–MR20)
(Addr ess [SR4-SR0] = 0D H )
Mode Register 2 is an 8-bit wide register.
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
BYTE 0
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
Figure 37. Closed Captioning Data Register
TIMING REGISTER 1 (TR17–TR10)
(AD D RESS [SR4–SR0] = 0CH )
T iming Register 1 is an 8-Bit Wide Register
MR2 BIT D ESCRIP TIO N
Squar e P ixel Mode Contr ol (MR20)
T his bit is used to set up square pixel mode. T his is available in
slave mode only. For NT SC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
Figure 38 shows the various operations under the control of
T iming Register 1. T his register can be read from as well as
written to. T his register can be used to adjust the width and
position of the master mode timing signals.
TR11
TR17
TR16
TR15
TR14
TR13
TR12
TR10
HSYNC TO PIXEL
DATA ADJUSTMENT
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
HSYNC WIDTH
HSYNC TO
FIELD/VSYNC DELAY
T
TR11 TR10
A
TR17 TR16
T
0
0
1
1
0
1
0
1
1 x T
4 x T
TR13 TR12
B
PCLK
T
TR15 TR14
C
0
0
1
1
0
1
0
1
0 x T
1 x T
2 x T
3 x T
0
0
1
1
0
1
0
1
0 x T
4 x T
8 x T
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
x
x
0
1
T
T
B
16 x T
PCLK
+ 32s
128 x T
B
PCLK
16 x T
PCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 x T
4 x T
PCLK
PCLK
16 x T
PCLK
128 x T
PCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
LINE 313
LINE 314
TA
TB
HSYNC
TC
FIELD/VSYNC
Figure 38. Tim ing Register 1
REV. B
–25–
ADV7175A/ADV7176A
MR21
MR27
MR26
MR25
MR24
MR23
MR22
MR20
CHROMINANCE
CONTROL
RGB/YUV
CONTROL
GENLOCK SELECTION
MR22 MR21
MR24
MR26
x
0
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
0
1
RGB OUTPUT
YUV OUTPUT
0
1
ENABLE COLOR
DISABLE COLOR
1
1
ENABLE RTC PIN
LOWER POWER
MODE
BURST
CONTROL
ACTIVE VIDEO LINE WIDTH
CONTROL
SQUARE PIXEL
CONTROL
MR27
MR25
MR23
MR20
0
1
DISABLE
ENABLE
0
1
ENABLE BURST
DISABLE BURST
0
1
DISABLE
ENABLE
0
1
720 PIXELS ACTIVE LINE
ITU-R/SMPTE ACTIVE LINE
Figure 39. Mode Register 2
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0
Genlock Contr ol (MR22–MR21)
FIELD 1/3
FIELD 1/3
T hese bits control the genlock feature of the ADV7175A/
AD V7176A. Setting M R21 to a Logic “1” configures the
SCRESET /RT C pin as an input. Setting MR22 to Logic Level
“0” configures the SCRESET /RT C pin as a subcarrier reset
input, therefore, the subcarrier will reset to Field 0, following a
high-to-low transition on the SCRESET /RT C pin. Setting
MR22 to Logic Level “1” configures the SCRESET /RT C pin as
a real-time control input.
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
FIELD 2/4
FIELD 2/4
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
Active Video Line Contr ol (MR23)
T his bit switches between two active video line durations. A
zero selects IT U-R BT .470 (720 pixels PAL/NT SC) and a one
selects IT U-R/SMPT E “analog” standard for active video dura-
tion (710 pixels NT SC 702 pixels PAL).
Figure 40. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0
FIELD 1/3
FIELD 1/3
Chr om inance Contr ol (MR24)
T his bit enables the color information to be switched on and off
the video output.
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
Bur st Contr ol (MR25)
T his bit enables the burst information to be switched on and off
the video output.
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0
FIELD 2/4
FIELD 2/4
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8
RGB/YUV Contr ol (MR26)
T his bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Figure 41. Teletext Control Registers
Lower P ower Contr ol (MR27)
T his bit enables the lower power mode of the ADV7175A/
ADV7176A. T his will reduce the DAC current by 50%.
MO D E REGISTER 3 MR3 (MR37–MR30)
(Addr ess [SR4–SR0] = 12H )
Mode Register 3 is an 8-bit wide register.
Figure 42 shows the various operations under the control of
Mode Register 3.
NTSC P ED ESTAL/P AL TELETEXT CO NTRO L
REGISTERS 3–0 (P CE15–0, P CO 15–0)/ (TXE15–0, TXO 15–0)
(Subaddr ess [SR4–SR0] = 11–0EH )
MR3 BIT D ESCRIP TIO N
T hese 8-bit wide registers are used to set up the NT SC pedes-
tal/PAL teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 40 and 41 show
the four control registers. A Logic “1” in any of the bits of these
registers has the effect of turning the pedestal OFF on the
equivalent line when used in NT SC. A Logic “1” in any of the
bits of these registers has the effect of turning teletext ON the
equivalent line when used in PAL.
Revision Code (MR30)
T his bit is read only and indicates the revision of the device.
VBI P ass-Thr ough Contr ol (MR31)
T his bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Reser ved (MR33–MR32)
T hese bits are reserved.
Teletext Enable (MR34)
T his bit must be set to “1” to enable teletext data insertion on
the T T X pin.
–26–
REV. B
ADV7175A/ADV7176A
D AC Switching Contr ol (MR37)
Input D efault Color (MR36)
T his bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown below.
T his bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
Table I. D AC O utput Configuration Matrix
D AC A D AC B D AC C
CVBS
MR06
MR26
MR37
D AC D
Sim ultaneous O utput
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CVBS
Y
C
Y
CVBS
Y
CVBS
G
CVBS
Y
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
RGB and Composite
RGB and Composite
YUV and Composite
YUV and Composite
CVBS
CVBS
CVBS
B
C
C
C
R
R
V
V
CVBS
Y
CVBS
G
B
CVBS
Y
U
U
CVBS
NOT E
CVBS: Composite Video Baseband Signal
Each DAC can be individually powered ON or OFF with the following control bits
(“0” = ON, “1” = OFF):
MR13 - DAC C
MR14 - DAC D
MR15 - DAC B
Y:
C:
U:
V:
R:
G:
B:
Luminance Component Signal (For YUV or Y/C Mode)
Chrominance Signal (For Y/C Mode)
Chrominance Component Signal (For YUV Mode)
Chrominance Component Signal (For YUV Mode)
RED Component Video (For RGB Mode)
MR16 - DAC A
GREEN Component Video (For RGB Mode)
BLUE Component Video (For RGB Mode)
MR31
MR36
MR35
MR34
MR33
MR32
MR30
MR30
MR37
RESERVED
MR35 = 0
ZERO SHOULD
BE WRITTEN TO
THIS BIT
REV CODE
(READ ONLY)
INPUT DEFAULT COLOR
MR36
TELETEXT ENABLE
VBI PASSTHROUGH
MR31
MR34
0
1
INPUT COLOR
BLACK
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
DAC OUTPUT
SWITCHING
MR37
DAC A
DAC B
DAC C
DAC D
0
1
COMPOSITE
GREEN/LUMA/Y
BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y
BLUE/COMP/U RED/CHROMA/V COMPOSITE
Figure 42. Mode Register 3
when bits T C07–T C04 are changed, the falling edge of T T REQ
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant)—see Figure 48.
TELETEXT CO NTRO L REGISTER TC07 (TC07–TC00)
(Addr ess [SR4–SR0] = 24H )
T eletext Control Register is an 8-bit wide register.
TTXREQ Rising Edge Contr ol (TC07–TC04)
T hese bits control the position of the rising edge of T T XREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles—see Figure 48.
TC06
TC05
TC04
TC03
TC02
TC01
TC00
TC07
TTXR EQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
TTXR EQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TTXREQ Falling Edge Contr ol (TC03–TC00)
1 PCLK
" PCLK
14 PCLK
15 PCLK
T hese bits control the position of the falling edge of T T XREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. T his controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If bits T C03–T C00 are unchanged
Figure 43. Teletext Control Register
REV. B
–27–
ADV7175A/ADV7176A
AP P END IX 1
BO ARD D ESIGN AND LAYO UT CO NSID ERATIO NS
The ADV7175A/ADV7176A is a highly integrated circuit contain-
ing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system level design so that high speed, accurate
performance is achieved. T he “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
Supply D ecoupling
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each
group of VAA pins on the ADV7175A/ADV7176A must have at
least one 0.1 µF decoupling capacitor to GND. T hese capaci-
tors should be placed as close to the device as possible.
It is important to note that while the ADV7175A/ADV7176A
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three terminal voltage
regulator for supplying power to the analog power plane.
The layout should be optimized for lowest noise on the ADV7175A/
ADV7176A power and ground lines by shielding the digital
inputs and providing good decoupling. T he lead length between
groups of VAA and GND pins should by minimized to minimize
inductive ringing.
Gr ound P lanes
D igital Signal Inter connect
T he ground plane should encompass all ADV7175A/ADV7176A
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7175A/ADV7176A, the analog output traces,
and all the digital signal traces leading up to the ADV7175A/
ADV7176A. T he ground plane is the board’s common ground
plane.
T he digital inputs to the ADV7175A/ADV7176A should be
isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay
the analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7175A/ADV7176A should be avoided to reduce noise
pickup.
T his should be as substantial as possible to maximize heat
spreading and power dissipation on the board.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not the
analog power plane.
P ower P lanes
T he ADV7175A/ADV7176A and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). T his power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. T his bead should be located within three inches of
the ADV7175A/ADV7176A.
Analog Signal Interconnect
T he ADV7175A/ADV7176A should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
T he video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
T he metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general
board.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7175A/ADV7176A power pins and voltage
reference circuitry.
For best performance, the outputs should each have a 75 Ω
load resistor connected to GND. T hese resistors should be
placed as close as possible to the ADV7175A/ADV7176A as to
minimize reflections.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
T he ADV7175A/ADV7176A should have no inputs left float-
ing. Any inputs that are not required should be tied to ground.
–28–
REV. B
ADV7175A/ADV7176A
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1F
0.01F
L1
(FERRITE BEAD)
+5V (V
)
AA
+5V (V
)
+5V (V
)
+5V
(V
AA
AA
)
1, 11, 20, 28, 30
33F
10F
CC
0.1F
GND
0.1F
V
AA
COMP
25
33
27
DAC D
V
REF
75⍀
75⍀
75⍀
75⍀
ADV7175A
ADV7176A
38–42,
2–9, 12–14
26
DAC C
+5V (V
)
P15–P0
AA
S VIDEO
4k⍀
35
DAC B 31
SCRESET/RTC
RESET
100nF
15 HSYNC
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
FIELD/VSYNC
16
17
22
+5V (V
)
32
DAC A
CC
+5V (V
)
+5V (V
)
CC
CC
BLANK
RESET
TTX
100k⍀
5k⍀
5k⍀
TTX
TTX REQ
100⍀
100⍀
37
36
44
SCLOCK 23
SDATA 24
MPU BUS
TTX REQ
CLOCK
100k⍀
34
R
SET
+5V (V
)
AA
ALSB
18
GND
150⍀
TELETEXT PULLUP &
10k⍀
10, 19, 21
29, 43
PULLDOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 44. Recom m ended Analog Circuit Layout
T he circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. T his waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. T his 13.5 MHz clock can be used if the
13.5 MHz clock is required by the MPEG decoder. T his will guarantee that the Cr and Cb pixel information is input to the
ADV7175A/ADV7176A in the correct sequence.
D
Q
13.5MHz
D
Q
CLOCK
CK
CK
HSYNC
Figure 45. Circuit to Generate 13.5 MHz
REV. B
–29–
ADV7175A/ADV7176A
AP P END IX 2
CLO SED CAP TIO NING
T he ADV7175A/ADV7176A supports closed captioning, conforming to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even
fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in
signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. 16 bits of data follow the start bit.
T hese consist of two 8-bit bytes, seven data bits and one odd parity bit. T he data for these bytes is stored in closed captioning Data
Registers 0 and 1.
T he ADV7175A/ADV7176A also supports the extended closed captioning operation, which is active during even fields, and is en-
coded on scan Line 284. T he data for this operation is stored in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7175A/
ADV7176A. All pixels inputs are ignored during Lines 21 and 284.
FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and
284.
T he ADV7175A/ADV7176A uses a single buffering method. T his means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. T he data
must be loaded at least one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of
this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. If no new
data is required for transmission you must insert zeros in both the data registers; this is called NULLING. It is also important to load
“control codes,” all of which are double bytes on Line 21, or a T V will not recognize them. If you have a message like “Hello World”
which has an odd number of characters, it is important to pad it out to an even number to get “end of caption” 2-byte control code to
land in the same field.
10.5 ؎ 0.25s
12.91s
7 CYCLES
OF 0.5035 MHz
(CLOCKRUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
S
T
A
R
T
P
A
R
I
T
Y
D0–D6
D0–D6
50 IRE
40 IRE
BYTE 1
BYTE 0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003s
33.764s
27.382s
Figure 46. Closed Captioning Waveform (NTSC)
–30–
REV. B
ADV7175A/ADV7176A
AP P END IX 3
TELETEXT INSERTIO N
Time TPD time needed by the ADV7175A/ADV7176A to interpolate input data on T T X and insert it onto the CVBS or Y outputs,
such that it appears T synT xtOut = 10.2 µs after the leading edge of the horizontal signal. T ime T xtDel is the pipeline delay time by the
source that is gated by the T T REQ signal in order to deliver T T X data.
With the programmability that is offered with T T XREQ signal on the Rising/Falling edges, the T T X data is always inserted at the
correct position of 10.2 µs after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline
delays.
T he width of the T T XREQ signal must always be maintained so it allows the insertion of 360 (to comply with the T eletext Standard
“PAL–WST ”) teletext bits at a text data rate of 6.9375 Mbits/s; this is achieved by setting T C03–T C00 to zero. T he insertion win-
dow is not open if the T eletext Enable bit (MR34) is set to zero.
Teletext P r otocol
T he relationship between the T T X bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:
27 MHz
= 6.75 MHz
4
6.9375 × 106
= 1.027777
6.75 × 106
Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. T he ADV7175A/ADV7176A
uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal
which can be outputted on the CVBS and Y outputs.
At the T T X input the bit duration scheme repeats after every 37 T T X bits or 144 clock cycles. T he protocol requires that T T X bits
10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 T T X bits, the next bits with three clock
cycles are 47, 56, 65 and 74. T his scheme holds for all following cycles of 37 T T X bits, until all 360 T T X bits are completed. All
teletext lines are implemented in the same way. Individual control of teletext lines are controlled by T eletext Setup Registers.
45 BYTES (360 BITS) – PAL
ADDRESS & DATA
TELETEXT VBI LINE
RUN-IN CLOCK
Figure 47. Teletext VBI Line
tSYNTXTOUT
CVBS/Y
tPD
tPD
HSYNC
10.2s
TXT
DATA
TXT
DEL
TXTREQ
TXT
ST
PROGRAMMABLE PULSE EDGES
tSYNTXTOUT = 10.2s
tPD = PIPELINE DELAY THROUGH ADV7175A/ADV7176A
TXT = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
DEL
Figure 48. Teletext Functionality Diagram
–31–
REV. B
ADV7175A/ADV7176A
AP P END IX 4
NTSC WAVEFO RMS (WITH P ED ESTAL)
1268.1mV
1048.4mV
130.8 IRE
100 IRE
PEAK COMPOSITE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
48.3mV
SYNC LEVEL
–40 IRE
Figure 49. NTSC Com posite Video Levels
1048.4mV
100 IRE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
48.3mV
SYNC LEVEL
–40 IRE
Figure 50. NTSC Lum a Video Levels
PEAK CHROMA
1067.7mV
835mV (pk-pk)
286mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
650mV
232.2mV
0mV
Figure 51. NTSC Chrom a Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.5mV
331.4mV
SYNC LEVEL
–40 IRE
45.9mV
Figure 52. NTSC RGB Video Levels
–32–
REV. B
ADV7175A/ADV7176A
NTSC WAVEFO RMS (WITH O UT P ED ESTAL)
130.8 IRE
100 IRE
1289.8mV
1052.2mV
PEAK COMPOSITE
REF WHITE
714.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
338mV
52.1mV
–40 IRE
Figure 53. NTSC Com posite Video Levels
1052.2mV
100 IRE
REF WHITE
714.2mV
338mV
52.1mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
Figure 54. NTSC Lum a Video Levels
PEAK CHROMA
1101.6mV
650mV
903.2mV (pk-pk)
307mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
198.4mV
0mV
Figure 55. NTSC Chrom a Video Levels
100 IRE
1052.2mV
REF WHITE
715.7mV
BLANK/BLACK LEVEL 336.5mV
51mV
0 IRE
SYNC LEVEL
–40 IRE
Figure 56. NTSC RGB Video Levels
REV. B
–33–
ADV7175A/ADV7176A
P AL WAVEFO RMS
PEAK COMPOSITE
REF WHITE
1284.2mV
1047.1mV
696.4mV
350.7mV
50.8mV
BLANK/BLACK LEVEL
SYNC LEVEL
Figure 57. PAL Com posite Video Levels
REF WHITE
1047mV
696.4mV
BLANK/BLACK LEVEL
SYNC LEVEL
350.7mV
50.8mV
Figure 58. PAL Lum a Video Levels
PEAK CHROMA
1092.5mV
885mV (pk-pk)
300mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
207.5mV
0mV
Figure 59. PAL Chrom a Video Levels
REF WHITE
1050.2mV
698.4mV
BLANK/BLACK LEVEL
SYNC LEVEL
351.8mV
51mV
Figure 60. PAL RGB Video Levels
–34–
REV. B
ADV7175A/ADV7176A
UV WAVEFO RMS
505mV
505mV
423mV
334mV
BETACAM LEVEL
171mV
82mV
BETACAM LEVEL
0mV
0mV
0mV
–82mV
0mV
؊171mV
–423mV
؊334mV
–505mV
؊505mV
Figure 61. NTSC 100% Color Bars No Pedestal U Levels
Figure 64. NTSC 100% Color Bars No Pedestal V Levels
467mV
467mV
391mV
309mV
BETACAM LEVEL
76mV
158mV
BETACAM LEVEL
0mV
0mV
–76mV
0mV
0mV
–158mV
–309mV
–391mV
–467mV
–467mV
Figure 62. NTSC 100% Color Bars with Pedestal U Levels
Figure 65. NTSC 100% Color Bars with Pedestal V Levels
350mV
350mV
293mV
232mV
SMPTE LEVEL
57mV
118mV
SMPTE LEVEL
0mV
0mV
–57mV
0mV
0mV
–118mV
–293mV
–350mV
–232mV
–350mV
Figure 63. PAL 1005 Color Bars U Levels
Figure 66. PAL 100% Color Bars V Levels
REV. B
–35–
ADV7175A/ADV7176A
AP P END IX 5
REGISTER VALUES
T he ADV7175A/ADV7176A registers can be set depending on
the user standard required.
Addr ess
D ata
10Hex Pedestal Control Register 2
11Hex Pedestal Control Register 3
12Hex Mode Register 3
24Hex T eletext Control Register
00Hex
00Hex
00Hex
00Hex
T he following examples give the various register formats for
several video standards.
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Addi-
tionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown, the timing mode is set to Mode 0 in slave
format. T R02–T R00 of the T iming Register 0 control the tim-
ing modes. For a detailed explanation of each bit in the com-
mand registers, please turn to the Register Programming section
of the data sheet. T R07 should be toggled after setting up a new
timing mode. T iming Register 1 provides additional control over
the position and duration of the timing signals. In the examples,
this register is programmed in default mode.
P AL M (FSC = 3.57561149 MH z)
Addr ess
00Hex Mode Register 0
D ata
06Hex
00Hex
A3Hex
EFHex
E6Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
01Hex Mode Register 1
02Hex Subcarrier Frequency Register 0
03Hex Subcarrier Frequency Register 1
04Hex Subcarrier Frequency Register 2
05Hex Subcarrier Frequency Register 3
06Hex Subcarrier Phase Register
07Hex T iming Register 0
08Hex Closed Captioning Ext Register 0
09Hex Closed Captioning Ext Register 1
0AHex Closed Captioning Register 0
0BHex Closed Captioning Register 1
0CHex T iming Register 1
NTSC (F SC = 3.5795454 MH z)
Addr ess
D ata
00Hex Mode Register 0
01Hex Mode Register 1
04Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
0DHex Mode Register 2
02Hex Subcarrier Frequency Register 0
03Hex Subcarrier Frequency Register 1
04Hex Subcarrier Frequency Register 2
05Hex Subcarrier Frequency Register 3
06Hex Subcarrier Phase Register
07Hex T iming Register 0
08Hex Closed Captioning Ext Register 0
09Hex Closed Captioning Ext Register 1
0AHex Closed Captioning Register 0
0BHex Closed Captioning Register 1
0CHex T iming Register 1
0EHex Pedestal Control Register 0
0FHex Pedestal Control Register 1
10Hex Pedestal Control Register 2
11Hex Pedestal Control Register 3
12Hex Mode Register 3
24Hex T eletext Control Register
0DHex Mode Register 2
0EHex Pedestal Control Register 0
0FHex Pedestal Control Register 1
10Hex Pedestal Control Register 2
11Hex Pedestal Control Register 3
12Hex Mode Register 3
24Hex T eletext Control Register
P AL B, D , G, H , I (F SC = 4.43361875 MH z)
Addr ess
00Hex Mode Register 0
01Hex Mode Register 1
01 Hex
00 Hex
CBHex
8A Hex
09 Hex
2AHex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
02Hex Subcarrier Frequency Register 0
03Hex Subcarrier Frequency Register 1
04Hex Subcarrier Frequency Register 2
05Hex Subcarrier Frequency Register 3
06Hex Subcarrier Phase Register
07Hex T iming Register 0
08Hex Closed Captioning Ext Register 0
09Hex Closed Captioning Ext Register 1
0AHex Closed Captioning Register 0
0BHex Closed Captioning Register 1
0CHex T iming Register 1
0DHex Mode Register 2
0EHex Pedestal Control Register 0
0FHex Pedestal Control Register 1
–36–
REV. B
ADV7175A/ADV7176A
AP P END IX 6
O P TIO NAL O UTP UT FILTER
If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7175A/ADV7176A, the following filter in
Figure 67 can be used. Plots of the filter characteristics are shown in Figures 68, 69 and 70. An output filter is not required if the
outputs of the ADV7175A/ADV7176A are connected to an analog monitor or an analog T V; however, if the output signals are ap-
plied to a system where sampling is used (e.g., digital T V), a filter is required to prevent aliasing.
L
1H
L
L
2.7H
0.68H
0
IN
OUT
C
C
C
56pF
R
75⍀
R
75⍀
V
– OP
–5
470pF
330pF
dB
–10
–15
–20
–25
–30
–35
Figure 67. Output Filter
0
–5
V
– OP
–10
dB
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
1
10
100
FREQUENCY – MHz
Figure 69. Output Filter Close Up
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
V
– OP
dB
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 68. Output Filter Plot
1
2
4
6
8
10
FREQUENCY – MHz
Figure 70. Output Filter Plot Close Up
REV. B
–37–
ADV7175A/ADV7176A
AP P END IX 7
O P TIO NAL D AC BUFFERING
For external buffering of the ADV7175A/ADV7176A DAC outputs, the configuration in Figure 71 is recommended. T his configu-
ration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7175A/ADV7176A
to dissipate less power, the analog current is reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω. This mode is recommended for
3.3 volt operation as optimum performance is obtained from the DAC outputs at 18 mA with a VAA of 3.3 volts. T his buffer also
adds extra isolation on the video outputs, see buffer circuit in Figure 72. When calculating absolute output full current and voltage,
use the following equation:
VOUT = IOUT × RLOAD
VREF × K
(
=
)
IOUT
RSET
K = 4.2146 constant , VREF = 1.235 V
V
AA
ADV7175A/ADV7176A
OUTPUT
BUFFER
V
REF
DAC A
75⍀
75⍀
75⍀
75⍀
OUTPUT
BUFFER
DAC B
PIXEL
PORT
DIGITAL
CORE
OUTPUT
BUFFER
DAC C
DAC D
R
SET
OUTPUT
BUFFER
300⍀
Figure 71. Output DAC Buffering Configuration
V
CC
36⍀
OUTPUT TO
TV/MONITOR
INPUT
2N2907
75⍀
75⍀
Figure 72. Recom m ended Output DAC Buffer
–38–
REV. B
ADV7175A/ADV7176A
AP P END IX 8
O UTP UT WAVEFO RMS
0.6
0.4
0.2
0.0
؊0.2
L608
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 0.00 dB
APL = 39.1%
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
SYNC = SOURCE
625 LINE PAL
NO FILTERING
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2 3 4
Figure 73. 100/75% PAL Color Bars
0.5
0.0
L575
0.0
10.0
20.0
30.0
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
40.0
50.0
60.0
70.0
APL NEEDS SYNC = SOURCE!
SOUND-IN-SYNC OFF
SYNC = A
625 LINE PAL
NO FILTERING
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1
Figure 74. 100/75% PAL Color Bars Lum inance
REV. B
–39–
ADV7175A/ADV7176A
0.5
0.0
–0.5
L575
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NO BRUCH SIGNAL
APL NEEDS SYNC = SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 V AT 6.72 s
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 75. 100/75% PAL Color Bars Chrom inance
100.0
0.5
50.0
0.0
0.0
F1
L76
–50.0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
APL = 44.6%
PRECISION MODE OFF
SYNCHRONOUS
525 LINE NTSC
NO FILTERING
SYNC = A
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 76. 100/75% NTSC Color Bars
–40–
REV. B
ADV7175A/ADV7176A
0.6
0.4
0.2
50.0
0.0
0.0
–0.2
F2
L238
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.7%
PRECISION MODE OFF
525 LINE NTSC
NO FILTERING
SYNCHRONOUS
SYNC = SOURCE
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 77. 100/75% NTSC Color Bars Chrom inance
0.4
50.0
0.2
0.0
–0.2
–0.4
–50.0
F1
L76
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC = SOURCE!
PRECISION MODE OFF
SYNCHRONOUS
525 LINE NTSC
NO FILTERING
SYNC = B
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 78. 100/75% NTSC Color Bars Chrom inance
REV. B
–41–
ADV7175A/ADV7176A
V
APL = 39.6%
SYSTEM LINE L608
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
625 LINE PAL
cy
BURST FROM SOURCE
DISPLAY +V & –V
R
g
M
g
75%
100%
YI
b
U
yl
B
G
Cy
m
g
r
SOUND IN SYNC OFF
Figure 79. PAL Vector Plot
R-Y
APL = 45.1%
SYSTEM LINE L76F1
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
525 LINE NTSC
cy
I
BURST FROM SOURCE
R
M
g
Q
YI
b
100%
B-Y
75%
B
G
Cy
–Q
–I
SETUP 7.5%
Figure 80. NTSC Vector Plot
–42–
REV. B
ADV7175A/ADV7176A
COLOR BAR (NTSC)
FIELD = 2 LINE = 28
WFM -->
FCC COLOR BAR
LUMINANCE LEVEL (IRE)
0.4
0.2
0.2
0.0
0.2
0.1
0.2
0.1
30.0
20.0
10.0
0.0
–10.0
CHROMINANCE LEVEL (IRE)
0.0 –0.2
1.0
–0.2
–0.3
–0.2
–0.3
0.0
0.0
0.0
–1.0
CHROMINANCE PHASE (DEG)
. . . . .
–0.1
–0.2
–0.2
–0.1
–0.3
–0.2
- - - - -
0.0
–1.0
–2.0
GRAY
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
AVERAGE: 32 --> 32
REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD
Figure 81. NTSC Color Bar Measurem ent
DGDP (NTSC)
WFM -->
MOD 5 STEP
BLOCK MODE START F2 L64, STEP = 32, END = 192
DIFFERENTIAL GAIN (%)
MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11
0.11 0.07
0.00
0.08
0.07
0.05
0.3
0.2
0.1
0.0
–0.1
DIFFERENTIAL PHASE (DEG)
0.00 0.03
MIN = –0.02 MAX = 0.14 pk-pk = 0.16
0.14 0.10
–0.02
0.10
0.20
0.15
0.10
0.05
–0.00
–0.05
–0.10
1ST
2ND
3RD
4TH
5TH
6TH
Figure 82. NTSC Differential Gain and Phase Measurem ent
REV. B
–43–
ADV7175A/ADV7176A
LUMINANCE NONLINEARITY (NTSC)
WFM -->
5 STEP
FIELD = 2 LINE = 21
LUMINANCE NONLINEARITY (%)
pk-pk = 0.2
99.9
99.9
100.0
99.9
99.8
100.4
100.3
100.2
100.1
100.0
99.9
99.8
99.7
99.6
99.5
99.4
99.3
99.2
99.1
99.0
98.9
98.8
98.7
98.6
1ST
2ND
3RD
4TH
5TH
Figure 83. NTSC Lum inance Nonlinearity Measurem ent
CHROMINANCE AM PM (NTSC)
FULL FIELD (BOTH FIELDS)
BANDWIDTH 100Hz TO 500kHz
WFM -->
APPROPRIATE
AM NOISE
–68.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
–50.0
–45.0
–40.0
dB RMS
PM NOISE
–64.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
–50.0
–45.0
–40.0
dB RMS
(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
Figure 84. NTSC AMPM Noise Measurem ent
–44–
REV. B
ADV7175A/ADV7176A
NOISE SPECTRUM (NTSC)
FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p)
BANDWIDTH 100kHz TO FULL
WFM -->
PEDESTAL
NOISE LEVEL = –80.1 dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
6.0
MHz
Figure 85. NTSC SNR Pedestal Measurem ent
NOISE SPECTRUM (NTSC)
WFM -->
RAMP SIGNAL
FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p)
BANDWIDTH 10kHz TO FULL (TILT NULL)
NOISE LEVEL = –61.7 dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
MHz
Figure 86. NTSC SNR Ram p Measurem ent
REV. B
–45–
ADV7175A/ADV7176A
PARADE SMPTE/EBU PAL
mV Y(A)
mV
250
Pb(B)
mV
Pr(C)
250
700
600
200
150
100
50
200
150
100
50
500
400
300
200
0
0
100
–50
–50
0
–100
–150
–200
–250
–100
–150
–200
–250
؊100
؊200
؊300
Figure 87. PAL YUV Parade Plot
VM700A DEV 3 WC TEMP = 90؇C V = 5.25V
DD
CHANNEL C SYSTEM DEFAULT
10-APR-97 09:23:07
LIGHTNING
L183
COLORBARS: 75% SMPTE/EBU (50Hz)
Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR Pk-Pk 525.0mV
AVERAGE 15 --> 32
YI
–274.82
0.93%
G
R
CY
88.31
0.28%
M
B
–173.24
0.19%
–88.36
0.19%
174.35
–0.65%
260.51
–0.14%
B-Y
W
YI
CY
864.78
–0.88%
462.80
–0.50%
YI
G
G
307.54
–0.21%
CY
M
216.12
–0.33%
R
M
R
156.63
–0.22%
B
B
61.00
1.92%
B
R
G
M
CY
YI
W
R-Y
CY
–262.17
–0.13%
G
B
YI
41.32
–0.76%
M
R
–218.70
–0.51%
–42.54
0.69%
212.28
–3.43%
252.74
–3.72%
COLOR Pk-Pk: B-Y 532.33mV
Pk-WHITE: 700.4mV (100%) SETUP –0.01%
1.40%
R-Y 514.90mV –1.92%
DELAY: B-Y –6ns R-Y –6ns
Figure 88. PAL YUV Lighting Plot
–46–
REV. B
ADV7175A/ADV7176A
COMPONENT NOISE
LINE = 202
AMPLITUDE (0dB = 700mV p-p)
BANDWIDTH 10kHz TO 5.0MHz
NOISE dB RMS
0.0
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
-->Y –82.1
Pb –82.3
Pr –83.3
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
5.0
MHz
Figure 89. PAL YUV SNR Plot
COMPONENT MULTIBURST
LINE = 202
AMPLITUDE (0dB = 100% OF 688.1mV
683.4mV
–0.05
668.9mV
–0.68
(dB)
0.04
–0.02
–2.58
4.79
–8.05
0.0
–5.0
Y
–10.0
0.49
0.99
2.00
3.99
5.79
0.21
0.23
–0.78
–2.59
–7.15
0.0
Pb –5.0
–10.0
0.49
0.25
0.99
0.25
1.99
2.39
2.89
–0.77
–2.59
–7.13
0.0
Pr –5.0
–10.0
0.49
0.99
1.99
2.39
2.89
(MHz)
Figure 90. PAL YUV Multiburst Response
REV. B
–47–
ADV7175A/ADV7176A
COMPONENT VECTOR SMPTE/EBU, 75%
R
M
g
YI
BK
B
G
CY
Figure 91. PAL YUV Vector Plot
RGB PARADE SMPTE/EBU
mV GREEN (A)
mV
BLUE (B)
mV
RED (C)
700
700
600
700
600
500
400
300
200
100
0
600
500
400
300
200
100
0
500
400
300
200
100
0
؊100
؊200
؊300
؊100
؊200
؊300
؊100
؊200
؊300
20 --> 32
Figure 92. PAL RGB Waveform s
–48–
REV. B
ADV7175A/ADV7176A
IND EX
Contents
Contents
P age No.
P age No.
MODE REGIST ER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MR1 BIT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 24
SUBCARRIER FREQUENCY REGIST ER . . . . . . . . . . . 24
SUBCARRIER PHASE REGIST ER . . . . . . . . . . . . . . . . . 24
T IMING REGIST ER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 24
T R0 BIT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 24
CLOSED CAPT IONING EVEN FIELD . . . . . . . . . . . . . 25
CLOSED CAPT IONING ODD FIELD . . . . . . . . . . . . . 25
T IMING REGIST ER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25
T R1 BIT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 25
MODE REGIST ER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MR2 BIT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 25
NT SC PEDEST AL/PAL T ELET EXT CONT ROL
REGIST ERS 3–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MODE REGIST ER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MR3 BIT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 26
T ELET EXT CONT ROL REGIST ER T C07 . . . . . . . . . . 27
APPENDIX 1. BOARD DESIGN AND LAYOUT
CONSIDERAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
APPENDIX 2. CLOSED CAPT IONING . . . . . . . . . . . . 30
APPENDIX 3. T ELET EXT INSERT ION . . . . . . . . . . . 31
APPENDIX 4. WAVEFORMS . . . . . . . . . . . . . . . . . . . . 32
APPENDIX 5. REGIST ER VALUES . . . . . . . . . . . . . . . 36
APPENDIX 6. OPT IONAL OUT PUT FILT ER . . . . . . . 37
APPENDIX 7. OPT IONAL DAC BUFFERING . . . . . . 38
APPENDIX 8. OUT PUT WAVEFORMS . . . . . . . . . . . . 39
OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 50
GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . .
ADV7175A/ADV7176A SPECIFICAT IONS . . . . . . . . . . .
T IMING SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . .
ABSOLUT E MAXIMUM RAT INGS . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURAT ION . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
6
9
9
9
PIN FUNCT ION DESCRIPT IONS . . . . . . . . . . . . . . . . 10
DAT A PAT H DESCRIPT ION . . . . . . . . . . . . . . . . . . . . 11
INT ERNAL FILT ER RESPONSE . . . . . . . . . . . . . . . . . . 11
COLOR BAR GENERAT ION . . . . . . . . . . . . . . . . . . . . . 13
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . 13
COLOR SIGNAL CONT ROL . . . . . . . . . . . . . . . . . . . . . 13
BURST SIGNAL CONT ROL . . . . . . . . . . . . . . . . . . . . . 13
NT SC PEDEST AL CONT ROL . . . . . . . . . . . . . . . . . . . . 13
PIXEL T IMING DESCRIPT ION . . . . . . . . . . . . . . . . . . 13
SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REAL T IME CONT ROL . . . . . . . . . . . . . . . . . . . . . . . . . 13
VIDEO T IMING DESCRIPT ION . . . . . . . . . . . . . . . . . . 13
T iming Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
T iming Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
T iming Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
T iming Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUT PUT VIDEO T IMING . . . . . . . . . . . . . . . . . . . . . . . 21
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MPU PORT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . 21
REGIST ER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REGIST ER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 23
MODE REGIST ER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MR0 BIT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 23
REV. B
–49–
ADV7175A/ADV7176A
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic Q uad Flatpack
(S-44)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
0.398 (10.11)
MAX
0.390 (9.91)
0.037 (0.94)
0.025 (0.64)
8°
0.8°
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
44
12
1
11
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.033 (0.84)
0.029 (0.74)
0.016 (0.41)
0.012 (0.30)
0.083 (2.11)
0.077 (1.96)
–50–
REV. B
–51–
–52–
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明