ADV7177 [ADI]
Integrated Digital CCIR-601 to PAL/NTSC Video Encoder; 集成数字CCIR -601至PAL / NTSC视频编码器型号: | ADV7177 |
厂家: | ADI |
描述: | Integrated Digital CCIR-601 to PAL/NTSC Video Encoder |
文件: | 总38页 (文件大小:282K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Integrated Digital CCIR-601
to PAL/NTSC Video Encoder
a
ADV7177/ADV7178
FEATURES
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 9-Bit Video DACs
Integral Nonlinearity <1 LSB at 9 Bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz Crystal/Clock Required (
؋
2 Oversampling) 75 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
OSD Support (AD7177 Only)
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.01 (ADV7178 Only)**
Closed Captioning Support
Component S-Video (Y/C)
Component YUV and RGB
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
Onboard Voltage Reference
2-Wire Serial MPU Interface (I2C® Compatible)
Single Supply +5 V or +3 V Operation
Small 44-Lead PQFP Package
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Full Video Output Drive or Low Signal Drive Capability
34.7 mA max into 37.5 ⍀ (Doubly-Terminated 75R)
5 mA min with External Buffers
Programmable Simultaneous Composite and S-VHS
(VHS) Y/C or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass/Notch/Extended)
Programmable VBI (Vertical Blanking Interval)
Synchronous 27 MHz/13.5 MHz Clock O/P
APPLICATIONS
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Cable Systems (Set Top Boxes/IRDs), Digital TVs,
CD Video/Karaoke, Video Games, PC Video/Multimedia
GENERAL DESCRIPTION
The ADV7177/ADV7178 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8- or 16-bit component
video data into a standard analog baseband television signal
(Continued on page 11)
FUNCTIONAL BLOCK DIAGRAM
V
AA
M
U
L
T
I
P
L
E
X
E
R
ADV7177/ADV7178
9
9-BIT
DAC
DAC A (PIN 31)
DAC B (PIN 27)
DAC C (PIN 26)
ADV7177
ONLY
YUV TO
RBG
MATRIX
9
9
9-BIT
DAC
OSD_EN
OSD_0
OSD_1
9-BIT
DAC
Y
OSD_2
9
8
8
8
8
8
8
8
8
8
8
8
8
ADD
SYNC
INTER-
POLATOR
LOW-PASS
FILTER
COLOR
DATA
4:2:2 TO
4:4:4
INTER-
YCrCb
TO
YUV
U
9
9
ADD
BURST
INTER-
POLATOR
LOW-PASS
FILTER
P7–P0
POLATOR
MATRIX
V
P15–P8
ADD
INTER-
POLATOR
LOW-PASS
FILTER
BURST
V
9
9
REF
HSYNC
FIELD/VSYNC
BLANK
VOLTAGE
REFERENCE
CIRCUIT
VIDEO TIMING
GENERATOR
2
R
I
C MPU PORT
SET
SIN/COS
DDS BLOCK
COMP
CLOCK/2
CLOCK CLOCK
RESET
SCLOCK SDATA ALSB
GND
*Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
I
2C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
ADV7177/ADV7178–SPECIFICATIONS
(V = +5 V ؎ 5%1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless otherwise noted.)
5 V SPECIFICATIONS
AA
Parameter
Conditions1
Min
Typ
Max
Units
STATIC PERFORMANCE3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
9
Bits
±1.0
±1.0
LSB
LSB
Differential Nonlinearity
Guaranteed Monotonic
DIGITAL INPUTS3
Input High Voltage, VINH
Input Low Voltage, VINL
2
V
V
µA
µA
pF
0.8
±1
±50
4
Input Current, IIN
Input Current, IIN
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
5
Input Capacitance, CIN
DIGITAL OUTPUTS3
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
10
10
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
V
V
µA
pF
0.4
10
Three-State Output Capacitance
ANALOG OUTPUTS3
Output Current6
RSET = 300 Ω, RL = 75 Ω
16.5
0
17.35
5
0.6
18.5
mA
mA
%
V
kΩ
Output Current7
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
5
+1.4
15
IOUT = 0 mA
30
pF
VOLTAGE REFERENCE3
Reference Range, VREF
POWER REQUIREMENTS3, 8
VAA
IVREFOUT = 20 µA
1.112
4.75
1.235
5.0
1.359
5.25
V
V
Low Power Mode
IDAC (max)9
62
25
100
0.01
mA
mA
mA
%/%
I
DAC (min)9
10
ICCT
150
0.5
Power Supply Rejection Ratio
COMP = 0.1 µF
NOTES
11The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
12Temperature range TMIN to TMAX: 0°C to +70°C.
13Guaranteed by characterization.
14All digital input pins except pins RESET, OSD0 and CLOCK.
15Excluding all digital input pins except pins RESET, OSD0 and CLOCK.
16Full drive into 75 Ω load.
17Minimum drive current (used with buffered/scaled output load).
18Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.
19
I
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 18.5 mA output per DAC) to drive all three DACs. Turning off individual
DAC
DACs reduces IDAC correspondingly.
10
I
(Circuit Current) is the continuous current required to drive the device.
CCT
Specifications subject to change without notice.
–2–
REV. 0
ADV7177/ADV7178
(V = +3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless otherwise noted.)
3.3 V SPECIFICATIONS
AA
Parameter
Conditions1
Min
Typ
Max
Units
STATIC PERFORMANCE3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
9
Bits
±0.5
±0.5
LSB
LSB
Differential Nonlinearity
Guaranteed Monotonic
DIGITAL INPUTS
Input High Voltage, VINH
2
0.8
V
V
µA
µA
pF
Input Low Voltage, VINL
3, 4
Input Current, IIN
Input Current, IIN
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
±1
±50
3, 5
Input Capacitance, CIN
10
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current3
Three-State Output Capacitance3
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
0.4
V
V
µA
pF
10
10
ANALOG OUTPUTS3
Output Current6, 7
RSET = 300 Ω, RL = 75 Ω
16.5
0
17.35
5
2.0
18.5
mA
mA
%
V
kΩ
Output Current8
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
+1.4
30
15
IOUT = 0 mA
pF
POWER REQUIREMENTS3, 9
VAA
3.0
3.3
3.6
V
Normal Power Mode
I
DAC (max)10
RSET = 300 Ω, RL = 150 Ω
113
15
45
116
mA
mA
mA
IDAC (min)10
9
ICCT
Low Power Mode
IDAC (max)10
60
25
45
0.01
mA
mA
mA
%/%
I
DAC (min)10
11
ICCT
Power Supply Rejection Ratio
COMP = 0.1 µF
0.5
NOTES
11The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
12Temperature range TMIN to TMAX: 0°C to +70°C.
13Guaranteed by characterization.
14All digital input pins except pins RESET, OSD0 and CLOCK.
15Excluding all digital input pins except pins RESET, OSD0 and CLOCK.
16Full drive into 75 Ω load.
17DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 150 Ω).
18Minimum drive current (used with buffered/scaled output load).
19Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.
10
I
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all three DACs. Turning off individual
DAC
DACs reduces IDAC correspondingly.
11
I
(Circuit Current) is the continuous current required to drive the device.
CCT
Specifications subject to change without notice.
REV. 0
–3–
ADV7177/ADV7178–SPECIFICATIONS
2
(VAA = +4.75 V – 5.25 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX
unless otherwise noted.)
5 V DYNAMIC SPECIFICATIONS1
Parameter
Conditions1
Min
Typ
Max
Units
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
NTSC Mode
>54 dB Attenuation
>3 dB Attenuation
NTSC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Lower Power Mode
Lower Power Mode
RMS
7.0
4.2
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
Passband Cutoff F3 dB
Differential Gain4
2.0
1.5
75
70
57
Differential Phase4
SNR4 (Pedestal)
Peak Periodic
RMS
Peak Periodic
SNR4 (Ramp)
56
Hue Accuracy4
1.2
1.4
1.0
0.4
0.6
0.2
0.2
0.6
2.0
1.2
64
Color Saturation Accuracy4
Chroma Nonlinear Gain4
Chroma Nonlinear Phase4
Referenced to 40 IRE
NTSC
PAL
Referenced to 714 mV (NTSC)
Referenced to 700 mV (PAL)
±%
±Degrees
±Degrees
±%
±%
±%
ns
±%
dB
dB
Chroma/Luma Intermod4
Chroma/Luma Gain Ineq4
Chroma/Luma Delay Ineq4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
62
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to +70°C.
3These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 5.
4Guaranteed by characterization.
Specifications subject to change without notice.
–4–
REV. 0
ADV7177/ADV7178
2
(VAA = +3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX
3.3 V DYNAMIC SPECIFICATIONS1
unless otherwise noted.)
Conditions1
Parameter
Min
Typ
Max
Units
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
NTSC Mode
>54 dB Attenuation
>3 dB Attenuation
NTSC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Normal Power Mode
Normal Power Mode
RMS
7.0
4.2
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
dB
dB
dB
Passband Cutoff F3 dB
Differential Gain4
1.0
1.0
70
64
56
Differential Phase4
SNR4 (Pedestal)
Peak Periodic
RMS
Peak Periodic
SNR4 (Ramp)
54
Hue Accuracy4
1.2
1.4
1.4
64
62
64
Color Saturation Accuracy4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
Chroma AM Noise4
Chroma PM Noise4
NTSC
NTSC
PAL
PAL
62
dB
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2Temperature range TMIN to TMAX: 0°C to +70°C.
3These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 5.
4Guaranteed by characterization.
Specifications subject to change without notice.
REV. 0
–5–
ADV7177/ADV7178
(VAA = 4.75 V – 5.25 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless
5 V TIMING SPECIFICATIONS otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Units
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
0
100
kHz
µs
µs
µs
µs
4.0
4.7
4.0
4.7
250
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
ns
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
1
300
µs
ns
µs
4.7
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
5
0
ns
ns
CLOCK CONTROL
AND PIXEL PORT3, 6
fCLOCK
27
MHz
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
8
8
3.5
4
4
ns
ns
ns
ns
ns
ns
ns
ns
3
24
4
37
Clock Cycles
RESET CONTROL3, 4
RESET Low Time
6
ns
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t16
Clock/2 Fall Time, t17
7
7
ns
ns
OSD TIMING4
OSD Setup Time, t18
OSD Hold Time, t19
6
2
ns
ns
NOTES
1The max/min specifications are guaranteed over this range.
2Temperature range TMIN to TMAX: 0°C to +70°C.
3TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
Clock Input:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
Specifications subject to change without notice.
–6–
REV. 0
ADV7177/ADV7178
(VAA = +3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless
otherwise noted.)
3.3 V TIMING SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Units
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
0
100
kHz
µs
µs
µs
µs
4.0
4.7
4.0
4.7
250
After This Period the First Clock Is Generated
Repeated for Start Condition
ns
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
1
300
µs
ns
µs
4.7
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
7
0
ns
ns
CLOCK CONTROL
AND PIXEL PORT3, 4, 6
fCLOCK
27
MHz
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
8
8
3.5
4
4
ns
ns
ns
ns
ns
ns
ns
ns
3
24
4
37
Clock Cycles
RESET CONTROL3, 4
RESET Low Time
6
ns
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t16
Clock/2 Fall Time, t17
10
10
ns
ns
OSD TIMING4
OSD Setup Time, t18
OSD Hold Time, t19
10
2
ns
ns
NOTES
1The max/min specifications are guaranteed over this range.
2Temperature range TMIN to TMAX: 0°C to +70°C.
3TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
Clock Input:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
Specifications subject to change without notice.
REV. 0
–7–
ADV7177/ADV7178
t5
t3
t3
SDATA
t6
t1
SCLOCK
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t12
t9
t10
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
I/PS
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb
Y
t11
t13
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
O/PS
t14
Figure 2. Pixel and Control Data Timing Diagram
t16
t17
CLOCK
CLOCK/2
t16
t17
CLOCK
CLOCK/2
Figure 3. Internal Timing Diagram
t18
t19
CLOCK
OSD EN
OSD0–2
Figure 4. OSD Timing Diagram
–8–
REV. 0
ADV7177/ADV7178
PACKAGE THERMAL PERFORMANCE
ABSOLUTE MAXIMUM RATINGS1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +260°C
Analog Outputs to GND2 . . . . . . . . . . . . . . GND – 0.5 to VAA
The 44-lead PQFP package used for this device has a junction-
to-ambient thermal resistance (θJA) in still air on a four-layer
PCB of 53.2°C/W. The junction-to-case thermal resistance (θJC)
is 18.8°C/W.
Care must be taken when operating the part in certain condi-
tions to prevent overheating. Table I illustrates what conditions
are to be used when using the part.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table I. Allowable Operating Conditions for ADV7177/
ADV7178 in 44-Lead PQFP Package
2Analog output short circuit to any power supply or common can be of an indefinite
duration.
Condition
5 V
3 V
3 DACs ON, Double 75R1
3 DACs ON, Low Power2
3 DACs ON, Buffered3
No
Yes
Yes
Yes
Yes
Yes
ORDERING GUIDE
Temperature Package
Range Description
Package
Option
2 DACs ON, Double 75R
2 DACs ON, Low Power
2 DACs ON, Buffered
No
Yes
Yes
Yes
Yes
Yes
Model
ADV7178KS 0°C to +70°C Plastic Quad Flatpack S-44
ADV7177KS 0°C to +70°C Plastic Quad Flatpack S-44
NOTES
1DAC ON, Double 75R refers to a condition where the DACs are terminated
into a double 75R load and low power mode is disabled.
2DAC ON, Low Power refers to a condition where the DACs are terminated in a
double 75R load and low power mode is enabled.
3DAC ON, Buffered refers to a condition where the DAC current is reduced to
5 mA and external buffers are used to drive the video loads.
PIN CONFIGURATION
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
1
2
V
R
AA
SET
PIN 1
IDENTIFIER
CLOCK/2
P5
V
REF
3
DAC A
4
V
P6
AA
5
P7
GND
ADV7177/ADV7178
PQFP
6
V
P8
AA
TOP VIEW
(Not to Scale)
7
P9
DAC B
DAC C
COMP
8
P10
9
P11
10
11
P12
SDATA
SCLOCK
OSD_EN
20
12 13 14 15 16 17 18 19
21 22
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7177/ADV7178 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–9–
ADV7177/ADV7178
PIN FUNCTION DESCRIPTIONS
Input/
Pin
No.
Mnemonic
Output
Function
1, 20, 28, 30
2
VAA
CLOCK/2
P
O
+5 V Supply.
Synchronous Clock output signal. Can be either 27 MHz or 13.5 MHz; this
can be controlled by MR32 and MR33 in Mode Register 3.
3–10, 12–14,
37–41
P15–P0
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb
Pixel Port (P15–P0). P0 represents the LSB.
11
15
OSD_EN
HSYNC
I
I/O
Enables OSD input data on the video outputs.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
16
17
FIELD/VSYNC
I/O
I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is
Logic Level “0.” This signal is optional.
BLANK
18
ALSB
GND
RESET
I
G
I
TTL Address Input. This signal sets up the LSB of the MPU address.
Ground Pin.
The input resets the on-chip timing generator and sets the ADV7177/ADV7178
into default mode. This is NTSC operation, Timing Slave Mode 0, 8-Bit
Operation, 2 × Composite and S VHS out.
19, 21, 29, 42
22
23
24
25
26
27
31
32
33
SCLOCK
SDATA
COMP
DAC C
DAC B
DAC A
VREF
I
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Compensation Pin. Connect a 0.1 µF Capacitor from COMP to VAA
DAC C Analog Output.
DAC B Analog Output.
DAC A Analog Output.
I/O
O
O
O
O
I/O
I
.
Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
A 300 Ω resistor connected from this pin to GND is used to control full-scale
RSET
amplitudes of the Video Signals.
34–36
43
44
OSD_0–2
CLOCK
CLOCK
I
O
I
On Screen Display Inputs.
Crystal Oscillator output (to crystal). Leave unconnected if no crystal is used.
Crystal Oscillator input. If no crystal is used this pin can be driven by an
external TTL Clock source; it requires a stable 27 MHz reference Clock for
standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL)
can be used for square pixel operation.
–10–
REV. 0
ADV7177/ADV7178
(Continued from page 1)
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The
ADV7177/ADV7178 supports PAL (B, D, G, H, I, N, M) and
NTSC (with and without Pedestal) standards. The appropri-
ate SYNC, BLANK and Burst levels are added to the YCrCb
data. Macrovision antitaping (ADV7178 only), closed captioning,
OSD (ADV7177 only), and teletext levels are also added to Y,
and the resultant data is interpolated to a rate of 27 MHz. The
interpolated data is filtered and scaled by three digital FIR
filters.
compatible with worldwide standards. The 4:2:2 YUV video
data is interpolated to two times the pixel rate. The color-
difference components (UV) are quadrature modulated using
a subcarrier frequency generated by an on-chip 32-bit digital
synthesizer (also running at two times the pixel rate). The two
times pixel rate sampling allows for better signal-to-noise ratio.
A 32-bit DDS with a 9-bit look-up table produces a superior
subcarrier in terms of both frequency and phase. In addition
to the composite output signal, there is the facility to output
S-Video (Y/C) video, YUV or RGB video.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi-
nance signal. The luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
Each analog output is capable of driving the full video-level
(34.7 mA) signal into an unbuffered, doubly terminated 75 Ω
load. With external buffering, the user has the additional option
to scale back the DAC output current to 5 mA min, thereby signifi-
cantly reducing the power dissipation of the device.
The ADV7177/ADV7178 also supports both PAL and NTSC
square pixel operation.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively
analog YUV data can be generated instead of RGB.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in the master mode. The encoder
requires a single two times pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.54 MHz clock
for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
The three 9-bit DACs can be used to output:
1. RGB Video.
2. YUV Video
3. One Composite Video Signal + LUMA and CHROMA
3. (S-Video).
Alternatively, each DAC can be individually powered off if not
required.
The ADV7177/ADV7178 modes are set up over a two-wire
serial bidirectional port (I2C-Compatible) with two slave addresses.
Video output levels are illustrated in Appendix 3, Appendix 4 and
Appendix 5.
Functionally the ADV7178 and ADV7177 are the same with
the exception that the ADV7178 can output the Macrovision
anticopy algorithm, and OSD is only supported on the ADV7177.
INTERNAL FILTER RESPONSE
The Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low-pass responses, PAL/
NTSC subcarrier notch responses and a PAL/NTSC extended
response. The U and V filters have a 2/2.4 MHz low-pass
response for NTSC/PAL. These filter characteristics are illus-
trated in Figures 7 to 13.
The ADV7177/ADV7178 is packaged in a 44-lead thermally
enhanced PQFP package.
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz data rate. The pixel data is demultiplexed to from
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
F
FILTER SELECTION
3 dB
MR04
MR03
NTSC
PAL
NTSC
PAL
NTSC/PAL
NTSC
PAL
0
0
0
0
1
1
1
0
0
1
1
0
1
1
2.3
3.4
1.0
1.4
4.0
2.3
3.4
0.026
0.098
0.085
0.107
0.150
0.054
0.106
7.0
7.3
3.57
4.43
7.5
>
>
>
>
>
>
>
54
50
27.6
29.3
40
4.2
5.0
2.1
2.7
5.35
4.2
5.0
7.0
7.3
54
50.3
Figure 5. Luminance Internal Filter Specifications
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
ATTENUATION @
1.3MHz (dB)
F
FILTER SELECTION
3 dB
NTSC
PAL
1.0
1.3
0.085
0.04
3.2
4.0
>
>
40
40
0.3
0.02
2.05
2.45
Figure 6. Chrominance Internal Filter Specifications
–11–
REV. 0
ADV7177/ADV7178
0
0
–10
–20
–10
TYPE A
–20
–30
–40
–50
–60
–30
–40
–50
–60
TYPE B
10
0
2
4
6
8
10
12
0
2
4
6
8
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 7. NTSC Low-Pass Filter
Figure 10. PAL Notch Filter
0
0
–10
–20
–10
–20
–30
–40
–50
–60
–30
–40
–50
–60
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 8. NTSC Notch Filter
Figure 11. NTSC/PAL Extended Mode Filter
0
0
–10
–10
TYPE A
–20
–30
–40
–50
–60
–20
–30
–40
–50
–60
TYPE B
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 9. PAL Low-Pass Filter
Figure 12. NTSC UV Filter
–12–
REV. 0
ADV7177/ADV7178
16-Bit YCrCb Mode
0
–10
–20
This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
OSD
The ADV7177 supports OSD. There are twelve 8-bit OSD
registers, loaded with data from the four most significant bits of
Y, Cb, Cr input pixel data bytes. A choice of eight colors can,
therefore, be selected via the OSD_0, OSD_1, OSD_2 pins,
each color being a combination of 12 bits of Y, Cb, Cr pixel
data. The display is under control of the OSD_EN pin. The
OSD window can be an entire screen or just one pixel, its size
may change by using the OSD_EN signal to control the width on a
line-by-line basis. Figure 4 illustrates OSD timing on the ADV7177.
–30
–40
–50
–60
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 13. PAL UV Filter
SUBCARRIER RESET
The ADV7177/ADV7178 can be used in subcarrier reset
mode. The subcarrier will reset to Field 0 at the start of the
following field when a low to high transition occurs on this
input pin.
COLOR BAR GENERATION
The ADV7177/ADV7178 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
VIDEO TIMING DESCRIPTION
The ADV7177/ADV7178 is intended to interface to off-
the-shelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7177/ADV7178 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port, and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7177/ADV7178 generates all of the re-
quired horizontal and vertical timing periods and levels for the
analog video outputs.
SQUARE PIXEL MODE
The ADV7177/ADV7178 can be used to operate in square pixel
mode. For NTSC operation an input clock of 24.5454 MHz is
required. Alternatively an input clock of 29.5 MHz is required
for PAL operation. The internal timing logic adjusts accordingly
for square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
The ADV7177/ADV7178 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
In addition, the ADV7177/ADV7178 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
The ADV7177/ADV7178 has four distinct master and four
distinct slave timing configurations. Timing Control is estab-
lished with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.
PIXEL TIMING DESCRIPTION
The ADV7177/ADV7178 can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
REV. 0
–13–
ADV7177/ADV7178
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see Figures 14 to 25). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
The complete VBI comprises of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
The “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7177/ADV7178 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high during this mode.
ANALOG
VIDEO
EAV CODE
SAV CODE
C
b
C
r
8
0
0
0
F
F
F A A
F B B
A
B
8
0
0
0
C
b
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
INPUT PIXELS
Y
Y
Y
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
268 CLOCK
1440 CLOCK
1440 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
280 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 14. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7177/ADV7178 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) time
codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 17.
–14–
REV. 0
ADV7177/ADV7178
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
7
10
11
20
21
22
5
9
8
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
H
V
F
ODD FIELD
EVEN FIELD
Figure 15. Timing Mode 0 (NTSC Master Mode)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
22
23
5
21
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
318
335
336
309
310
311
312
313
314
315
316
317
319
320
334
H
V
F
ODD FIELD EVEN FIELD
Figure 16. Timing Mode 0 (PAL Master Mode)
REV. 0
–15–
ADV7177/ADV7178
ANALOG
VIDEO
H
F
V
Figure 17. Timing Mode 0 Data Transitions (Master Mode)
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7177/ADV7178 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is dis-
abled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and
Figure 19 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 18. Timing Mode 1 (NTSC)
–16–
REV. 0
ADV7177/ADV7178
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD EVEN FIELD
Figure 19. Timing Mode 1 (PAL)
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge follow-
ing the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the HSYNC,
BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave
REV. 0
–17–
ADV7177/ADV7178
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7177/ADV7178 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all normally
blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 21. Timing Mode 2 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 22. Timing Mode 2 (PAL)
–18–
REV. 0
ADV7177/ADV7178
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7177/ADV7178 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illus-
trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 * CLOCK/2
BLANK
NTSC = 16 * CLOCK/2
PIXEL
DATA
Cb
Y
Cr
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
REV. 0
–19–
ADV7177/ADV7178
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7177/ADV7178 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 25 (NTSC) and Figure 26 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 25. Timing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 26. Timing Mode 3 (PAL)
–20–
REV. 0
ADV7177/ADV7178
OUTPUT VIDEO TIMING
this configuration the SCH phase will never be reset, which
means that the output video will now track the unstable input
video. The subcarrier phase reset, when applied, will reset the
SCH phase to Field 0 at the start of the next field (e.g., subcarrier
phase reset applied in Field 5 [PAL] on the start of the next
field SCH phase will be reset to Field 0).
The video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. These sequences are summarized below. In slave
modes, the following sequences are synchronized with the input
timing control signals. In master modes, the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
MPU PORT DESCRIPTION
The ADV7178 and ADV7177 support a two-wire serial (I2C-
Compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7178 and ADV7177 each have four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 27 and
Figure 28. The LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7177/ADV7178 to Logic Level “0” or
Logic Level “1.”
NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan Lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for closed captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
NTSC–Noninterlaced: Scan Lines 1–9 are always blanked,
and vertical sync pulses are included. Scan Lines 10–21 are also
blanked and can be used for closed captioning data. Burst is
disabled on Lines 1–6, 261–262.
PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are
always blanked, and vertical sync pulses are included in Fields
1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are al-
ways blanked, and vertical sync pulses are included in Fields 3,
4, 7 and 8. The remaining scan lines in the vertical blanking
interval are also blanked and can be used for teletext data.
Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields
1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and
623–625 in Fields 3, 4, 7 and 8.
0
0
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always
blanked, and vertical sync pulses are included. The remaining
scan lines in the vertical blanking interval are also blanked and
can be used for teletext data. Burst is disabled on Lines 1–5,
310–312.
0
1
WRITE
READ
Figure 27. ADV7178 Slave Address
1
1
1
1
0
1
A1
X
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the
pixel inputs, P7–P0 are selected. After reset, the ADV7177/
ADV7178 is automatically set up to operate in NTSC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the
exception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR02. Bit
MR02 of Mode Register 0 is set to Logic Level “1.” This en-
ables the 7.5 IRE pedestal.
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 28. ADV7177 Slave Address
To control the various devices on the bus, the following proto-
col must be followed: First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address
+ R/W bit). The bits transfer from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
SCH Phase Mode
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7177/ADV7178 is con-
figured in RTC mode (MR21 = 1 and MR22 = 1). Under these
conditions (unstable video) the subcarrier phase reset should be
enabled MR22 = 0 and MR21 = 1) but no reset applied. In
REV. 0
–21–
ADV7177/ADV7178
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7177/ADV7178 and the part will re-
turn to the idle condition.
The ADV7177/ADV7178 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7178 has 36
subaddresses and the ADV7177 has 31 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allows data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Figure 29 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
SDATA
SCLOCK
S
1-7
8
9
1-7
8
9
1-7
DATA
8
9
P
START ADDR
ACK SUBADDRESS ACK
ACK
STOP
R/W
Figure 29. Bus Data Transfer
Figure 30 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7177/
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high pe-
riod, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7177/ADV7178 will not issue an acknowledge and will
return to the idle condition. If, in auto-increment mode, the
user exceeds the highest subaddress, the following action will be
taken:
ADV7178 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration.
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
WRITE
SEQUENCE
S
S
SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
DATA
A(S)
DATA
A(M)
A(S) P
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S)
SUB ADDR A(S)
S
SLAVE ADDR A(S)
DATA
DATA
P
A(M)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 30. Write and Read Sequences
–22–
REV. 0
ADV7177/ADV7178
Subaddress Register (SR7–SR0)
MR0 BIT DESCRIPTION
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
Encode Mode Control (MR01–MR00)
These bits are used to set up the encode mode. The ADV7177/
ADV7178 can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
Pedestal Control (MR02)
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7177/ADV7178 is configured in PAL mode.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
Luminance Filter Control (MR04–MR03)
The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, bits MR03
and MR04 select one of four NTSC luminance filters. The
filters are illustrated in Figures 7 to 13.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 32 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
SR1
SR7
SR6
SR5
SR4
SR3
SR2
SR0
SR7–SR6 (00)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7178 SUBADDRESS REGISTER
ADV7177 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
MODE REGISTER 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 1
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
MACROVISION REGISTER
OSD REGISTER
"
"
"
"
"
"
"
"
•
•
•
•
•
•
•
•
•
•
•
•
1
0
0
0
1
1
MACROVISION REGISTER
0
1
1
1
1
0
OSD REGISTER
Figure 31. Subaddress Register
MR06
MR05
MR04
MR03
MR02
MR01
MR00
MR07
OUTPUT SELECT
FILTER SELECT
MR04 MR03
OUTPUT VIDEO
STANDARD SELECTION
MR06
MR01
MR00
0
1
YC OUTPUT
RGB/YUV OUTPUT
0
0
LOW-PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW-PASS FILTER (B)
0
0
1
1
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
0
1
1
1
0
1
RESERVED
RGB SYNC
MR07
(0)
PEDESTAL CONTROL
MR02
MR05
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
0
1
PEDESTAL OFF
PEDESTAL ON
Figure 32. Mode Register 0 (MR0)
–23–
REV. 0
ADV7177/ADV7178
MR11
MR17
MR16
MR15
MR14
MR13
MR12
MR10
MR16
(1)
LUMA
DAC CONTROL
CLOSED CAPTIONING
FIELD SELECTION
MR14
ONE SHOULD
MR12
MR11
BE WRITTEN TO
THIS BIT
0
1
NORMAL
POWER-DOWN
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
COLOR BAR
CONTROL
COMPOSITE
DAC CONTROL
CHROMA
DAC CONTROL
INTERLACE
CONTROL
MR17
MR15
MR13
MR10
0
1
INTERLACED
NONINTERLACED
0
1
NORMAL
POWER-DOWN
0
1
DISABLE
ENABLE
0
1
NORMAL
POWER-DOWN
Figure 33. Mode Register 1 (MR1)
i.e.: NTSC Mode,
RGB Sync (MR05)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
F
CLK = 27 MHz,
FSCF = 3.5795454 MHz
232 – 1
27 × 106
Output Control (MR06)
× 3.5795454 × 106
Subcarrier Frequency Value =
This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still avail-
able in RGB/YUV mode.
= 21F07C16 HEX
Figure 34 shows how the frequency is set up by the four registers.
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 33 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
SUBCARRIER
FREQUENCY
REG 3
FSC30
FSC31
FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
SUBCARRIER
FREQUENCY
REG 2
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
SUBCARRIER
FREQUENCY
REG 1
FSC14
FSC13 FSC12 FSC11 FSC10 FSC9
FSC15
FSC7
FSC8
FSC0
SUBCARRIER
FREQUENCY
REG 0
FSC6
FSC5
FSC4
FSC3 FSC2 FSC1
Figure 34. Subcarrier Frequency Register
Closed Captioning Field Control (MR12–MR11)
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 06H)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41 degrees.
DAC Control (MR15–MR13)
These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7177/
ADV7178 if any of the DACs are not required in the application.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)
Figure 35 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
Color Bar Control (MR17)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 75/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7177/ADV7178 is config-
ured in a master timing mode as per the one selected by bits
TR01 and TR02.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7177/ADV7178 is in master
or slave mode. This register can be used to adjust the width and
position of the master timing signals.
SUBCARRIER FREQUENCY REGISTER 3-0
(FSC3–FSC0)
(Address [SR4–SR0] = 05H–02H)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers are calculated by using
the following equation:
Timing Mode Control (TR02–TR01)
These bits control the timing mode of the ADV7177/ADV7178.
These modes are described in the Timing and Control section
of the data sheet.
232 –1
× FSCF
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode
Subcarrier Frequency Register =
FCLK
–24–
REV. 0
ADV7177/ADV7178
TR01
TR07
TR06
TR05
TR04
TR03
TR02
TR00
BLACK INPUT
CONTROL
TIMING
REGISTER RESET
MASTER/SLAVE
CONTROL
TR03
TR00
TR07
0
1
ENABLE
DISABLE
0
1
SLAVE TIMING
MASTER TIMING
PIXEL PORT
CONTROL
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
TR06
TR02 TR01
0
0
1
1
0
1
0
1
0ns DELAY
0
8-BIT
0
0
1
1
0
1
0
1
MODE 0
74ns DELAY
148ns DELAY
222ns DELAY
1
16-BIT
MODE 1
MODE 2
MODE 3
Figure 35. Timing Register 0
Luma Delay Control (TR05–TR04)
CED15 CED14 CED13 CED12 CED11 CED10
CED9
CED8
BYTE 1
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
CED7
CED6
CED5
CED4
CED3
CED2
CED1
CED0
BYTE 0
Pixel Port Select (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit data.
If an 8-bit input is selected the data will be set up on Pins P7–P0.
Figure 36. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 0B–0AH)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 09–08H)
CCD15
CCD14 CCD13 CCD12 CCD11 CCD10
CCD9
CCD8
BYTE 1
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
BYTE 0
Figure 37. Closed Captioning Data Register
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC TO PIXEL
DATA ADJUSTMENT
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
HSYNC WIDTH
HSYNC TO
FIELD/VSYNC DELAY
T
TR11 TR10
A
TR17 TR16
T
TR13 TR12
0
0
1
1
0
1
0
1
1 x T
4 x T
B
PCLK
PCLK
T
TR15 TR14
C
0
0
1
1
0
1
0
1
0 x T
1 x T
2 x T
3 x T
0
0
1
1
0
1
0
1
0 x T
4 x T
8 x T
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
x
x
0
1
T
T
B
16 x T
PCLK
+ 32s
B
128 x T
PCLK
16 x T
PCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 x T
4 x T
PCLK
PCLK
16 x T
PCLK
128 x T
PCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
LINE 313
LINE 314
TA
TB
HSYNC
TC
FIELD/VSYNC
Figure 38. Timing Register 1
REV. 0
–25–
ADV7177/ADV7178
TIMING REGISTER 1 (TR17–TR10)
(Address [SR4–SR0] = 0CH)
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
Timing Register 1 is an 8-bit-wide register.
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
Active Video Line Control (MR23)
This bit switches between two active video line durations. A
zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one
selects ITU-R/SMPTE “analog” standard for active video dura-
tion (710 pixels NTSC 702 pixels PAL).
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulsewidth.
Chrominance Control (MR24)
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
HSYNC to FIELD Delay Control (TR15–TR14)
When the ADV7177/ADV7178 is in Timing Mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
This bit enables the burst information to be switched on and off
the video output.
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
VSYNC Width (TR15–TR14)
When the ADV7177/ADV7178 is in Timing Mode 2, these bits
adjust the VSYNC pulsewidth.
Table II. DAC Output Configuration Matrix
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
MR06
MR26
DAC A
DAC B
DAC C
0
0
1
1
0
1
0
1
CVBS
CVBS
B
Y
Y
S
C
C
R
V
U
Y
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 0DH)
CVBS: Composite Video Baseband Signal
Mode Register 2 is an 8-bit-wide register.
Y:
C:
U:
V:
R:
G:
B:
Luminance Component Signal (For YUV or Y/C Mode)
Chrominance Signal (For Y/C Mode)
Chrominance Component Signal (For YUV Mode)
Chrominance Component Signal (For YUV Mode)
RED Component Video (For RGB Mode)
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
GREEN Component Video (For RGB Mode)
BLUE Component Video (For RGB Mode)
Low Power Control (MR27)
This bit enables the lower power mode of the ADV7177/
ADV7178. This will reduce DAC current by 50%.
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
CHROMINANCE
CONTROL
MR22–MR21
RGB/YUV
CONTROL
(00)
MR24
MR26
ZERO SHOULD
BE WRITTEN TO
THESE BITS
0
1
ENABLE COLOR
DISABLE COLOR
0
1
RGB OUTPUT
YUV OUTPUT
LOW POWER
MODE
BURST
CONTROL
CCIR624/CCIR601
SQUARE PIXEL
CONTROL
CONTROL
MR27
MR25
MR23
MR20
0
1
DISABLE
ENABLE
0
1
ENABLE BURST
DISABLE BURST
0
1
CCIR624 OUTPUT
CCIR601 OUTPUT
0
1
DISABLE
ENABLE
Figure 39. Mode Register 2
–26–
REV. 0
ADV7177/ADV7178
NTSC PEDESTAL REGISTERS 3–0 (PCE15–0, PCO15–0)
(Subaddress [SR4–SR0] = 11–0EH)
MR3 BIT DESCRIPTION
Revision Code (MR30)
These 8-bit-wide registers are used to set up the NTSC pedestal
on a line-by-line basis in the vertical blanking interval for both
odd and even fields. Figure 40 show the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal OFF on the equivalent line when used in
NTSC.
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Clock Output Select (MR33–MR32)
These bits control the synchronous clock output signal. The
clock can be 27 MHz, 13.5 MHz or disabled, depending on the
values of these bits.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO7
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
FIELD 1/3
FIELD 1/3
OSD Enable (MR35)
A logic one in MR35 will enable the OSD function on the
ADV7177.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
Reserved (MR36)
These bits are reserved.
FIELD 2/4
FIELD 2/4
Input Default Color (MR36)
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
Figure 40. Pedestal Control Registers
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
OSD REGISTER 0–11
(Address [SR4–SR0] = 12H–1DH)
There are 12 OSD registers as shown in Figure 42. There are
four bits for each Y, Cb and Cr value, there are four zero added
to give the complete byte for each value loaded internally.
(Y0 = [Y03, Y02, Y01, Y00, 0, 0, 0, 0], Cb = [Cb3, Cb2, Cb1,
Cb0, 0, 0, 0, 0,], Cr = [Cr3, Cr2, Cr1, Cr0, 0, 0, 0, 0].)
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR30
MR37
MR37
CLOCK CONTROL
MR33-32
OSD ENABLE
REV CODE
(READ ONLY)
0
0
1
1
0
1
0
1
CLOCK OUTPUT OFF
13.5MHz OUTPUT
27MHz OUTPUT
MR35
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
CLOCK OUTPUT OFF
INPUT DEFAULT COLOR
MR36
MR34
VBI PASSTHROUGH
MR31
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
0
1
INPUT COLOR
BLACK
Figure 41. Mode Register 3
OSD
REG 0
Y0
Cr0
OSD
REG 1
Cb0
Y1
OSD
REG 2
Cr1
Cb1
OSD
REG 11
Cr7
Cb7
Figure 42. OSD Registers
REV. 0
–27–
ADV7177/ADV7178
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
Supply Decoupling
The ADV7177/ADV7178 is a highly integrated circuit containing
both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system level design so that high speed, accurate
performance is achieved. The “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each
group of VAA pins on the ADV7177/ADV7178 must have at
least one 0.1 µF decoupling capacitor to GND. These capacitors
should be placed as close to the device as possible.
It is important to note that while the ADV7177/ADV7178 con-
tains circuitry to reject power supply noise, this rejection de-
creases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three terminal voltage
regulator for supplying power to the analog power plane.
The layout should be optimized for lowest noise on the ADV7177/
ADV7178 power and ground lines by shielding the digital inputs
and providing good decoupling. The lead length between groups
of VAA and GND pins should by minimized to minimize induc-
tive ringing.
Digital Signal Interconnect
Ground Planes
The digital inputs to the ADV7177/ADV7178 should be iso-
lated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
The ground plane should encompass all ADV7177/ADV7178
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7177/ADV7178, the analog output traces,
and all the digital signal traces leading up to the ADV7177/
ADV7178. The ground plane is the board’s common ground
plane.
Due to the high clock rates involved, long clock lines to the
ADV7177/ADV7178 should be avoided to reduce noise pickup.
This should be as substantial as possible to maximize heat
spreading and power dissipation on the board.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not the
analog power plane.
Power Planes
The ADV7177/ADV7178 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7177/ADV7178.
Analog Signal Interconnect
The ADV7177/ADV7178 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
The metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general
board.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7177/ADV7178 power pins and voltage refer-
ence circuitry.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7177/ADV7178 as to minimize
reflections.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
The ADV7177/ADV7178 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
–28–
REV. 0
ADV7177/ADV7178
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1F
0.01F
+5V (V
+5V (V
)
+5V (V
)
L1
AA
AA
(FERRITE BEAD)
)
AA
0.1F
0.1F
+5V
1, 20, 28, 30
(V
)
33F
10F
CC
31
COMP
32
GND
V
AA
V
REF
11
OSD_EN
34 OSD_0
LUMA 27
OSD
INPUTS
35
36
OSD_1
OSD_2
75⍀
ADV7177/
ADV7178
37–41,
3–10, 12–14
CHROMA 26
+5V (V
)
AA
75⍀
75⍀
PIXEL
DATA
P15–P0
4k⍀
25
CVBS
RESET
100nF
15 HSYNC
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
FIELD/VSYNC
16
17
22
44
43
+5V (V
)
+5V (V
)
CC
CC
BLANK
RESET
CLOCK
5k⍀
5k⍀
100⍀
100⍀
23
SCLOCK
33pF
27MHz
XTAL
MPU BUS
CLOCK
SDATA 24
33
CLOCK/2
2
33pF
R
27MHz OR 13.5MHz
CLOCK OUTPUT
SET
ALSB
18
GND
150⍀
19, 21
29, 42
+5V (V
)
AA
10k⍀
Figure 43. Recommended Analog Circuit Layout
REV. 0
–29–
ADV7177/ADV7178
APPENDIX 2
CLOSED CAPTIONING
The ADV7177/ADV7178 supports closed captioning, conform-
ing to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of even fields.
FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
The ADV7177/ADV7178 uses a single buffering method. This
means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed
captioning data unlike other 2-byte deep buffering systems. The
data must be loaded at least one line before (Line 20 or Line
283) it is outputted on Line 21 and Line 284. A typical imple-
mentation of this method is to use VSYNC to interrupt a micro-
processor, which will in turn load the new data (two bytes) every
field. If no new data is required for transmission you must
insert zeros in both the data registers; this is called NULLING.
It is also important to load “control codes,” all of which are
double bytes on Line 21, or a TV will not recognize them. If
you have a message like “Hello World,” which has an odd num-
ber of characters, it is important to pad it out to an even number
to get “end of caption” 2-byte control code to land in the same
field.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic Level “1” start bit. 16 bits of data follow
the start bit. These consist of two 8-bit bytes, seven data bits
and one odd parity bit. The data for these bytes is stored in
closed captioning Data Registers 0 and 1.
The ADV7177/ADV7178 also supports the extended closed
captioning operation, which is active during even fields, and is
encoded on scan Line 284. The data for this operation is stored
in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7177/
ADV7178. All pixels inputs are ignored during Lines 21 and
284.
10.5 ؎ 0.25s
12.91s
7 CYCLES
OF 0.5035 MHz
(CLOCK RUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
S
T
A
R
T
P
A
R
I
T
Y
D0–D6
D0–D6
50 IRE
40 IRE
BYTE 1
BYTE 0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003s
33.764s
27.382s
Figure 44. Closed Captioning Waveform (NTSC)
–30–
REV. 0
ADV7177/ADV7178
APPENDIX 3
NTSC WAVEFORMS (WITH PEDESTAL)
1268.1mV
130.8 IRE
100 IRE
PEAK COMPOSITE
1048.4mV
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
48.3mV
–40 IRE
Figure 45. NTSC Composite Video Levels
1048.4mV
100 IRE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
48.3mV
–40 IRE
Figure 46. NTSC Luma Video Levels
PEAK CHROMA
1067.7mV
835mV (pk-pk)
286mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
650mV
232.2mV
0mV
Figure 47. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.5mV
331.4mV
SYNC LEVEL
–40 IRE
45.9mV
Figure 48. NTSC RGB Video Levels
REV. 0
–31–
ADV7177/ADV7178
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
100 IRE
1289.8mV
1052.2mV
PEAK COMPOSITE
REF WHITE
714.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
338mV
52.1mV
–40 IRE
Figure 49. NTSC Composite Video Levels
1052.2mV
100 IRE
REF WHITE
714.2mV
338mV
52.1mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
Figure 50. NTSC Luma Video Levels
PEAK CHROMA
1101.6mV
650mV
903.2mV (pk-pk)
307mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
198.4mV
0mV
Figure 51. NTSC Chroma Video Levels
100 IRE
1052.2mV
REF WHITE
715.7mV
BLANK/BLACK LEVEL 336.5mV
51mV
0 IRE
SYNC LEVEL
–40 IRE
Figure 52. NTSC RGB Video Levels
–32–
REV. 0
ADV7177/ADV7178
PAL WAVEFORMS
PEAK COMPOSITE
1284.2mV
1047.1mV
REF WHITE
696.4mV
350.7mV
50.8mV
BLANK/BLACK LEVEL
SYNC LEVEL
Figure 53. PAL Composite Video Levels
REF WHITE
1047mV
696.4mV
BLANK/BLACK LEVEL
SYNC LEVEL
350.7mV
50.8mV
Figure 54. PAL Luma Video Levels
PEAK CHROMA
1092.5mV
885mV (pk-pk)
300mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
207.5mV
0mV
Figure 55. PAL Chroma Video Levels
REF WHITE
1050.2mV
698.4mV
BLANK/BLACK LEVEL
SYNC LEVEL
351.8mV
51mV
Figure 56. PAL RGB Video Levels
REV. 0
–33–
ADV7177/ADV7178
UV WAVEFORMS
505mV
334mV
505mV
423mV
171mV
BETACAM LEVEL
BETACAM LEVEL
82mV
0mV
0mV
0mV
0mV
–82mV
؊171mV
؊334mV
–423mV
–505mV
؊505mV
Figure 57. NTSC 100% Color Bars No Pedestal U Levels
Figure 60. NTSC 100% Color Bars No Pedestal V Levels
467mV
309mV
467mV
391mV
158mV
BETACAM LEVEL
76mV
BETACAM LEVEL
0mV
0mV
0mV
0mV
–76mV
–158mV
–309mV
–391mV
–467mV
–467mV
Figure 58. NTSC 100% Color Bars with Pedestal U Levels
Figure 61. NTSC 100% Color Bars with Pedestal V Levels
350mV
350mV
293mV
232mV
118mV
SMPTE LEVEL
57mV
SMPTE LEVEL
0mV
0mV
0mV
0mV
–57mV
–118mV
–232mV
–293mV
–350mV
–350mV
Figure 59. PAL 1005 Color Bars U Levels
Figure 62. PAL 100% Color Bars V Levels
–34–
REV. 0
ADV7177/ADV7178
APPENDIX 4
REGISTER VALUES
Address
Data
The ADV7177/ADV7178 registers can be set depending on the
user standard required.
0EHex Pedestal Control Register 0
0FHex Pedestal Control Register 1
10Hex Pedestal Control Register 2
11Hex Pedestal Control Register 3
12Hex Mode Register 3
00Hex
00Hex
00Hex
00Hex
00Hex
The following examples give the various register formats for
several video standards.
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Addi-
tionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown, the timing mode is set to Mode 0 in slave
format. TR02–TR00 of the Timing Register 0 control the tim-
ing modes. For a detailed explanation of each bit in the com-
mand registers, please turn to the Register Programming section
of the data sheet. TR07 should be toggled after setting up a new
timing mode. Timing Register 1 provides additional control over
the position and duration of the timing signals. In the examples,
this register is programmed in default mode.
PAL M (FSC = 3.57561149 MHz)
Address
00Hex Mode Register 0
Data
06Hex
00Hex
A3Hex
EFHex
E6Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
80Hex
00Hex
00Hex
00Hex
00Hex
00Hex
01Hex Mode Register 1
02Hex Subcarrier Frequency Register 0
03Hex Subcarrier Frequency Register 1
04Hex Subcarrier Frequency Register 2
05Hex Subcarrier Frequency Register 3
06Hex Subcarrier Phase Register
07Hex Timing Register 0
08Hex Closed Captioning Ext Register 0
09Hex Closed Captioning Ext Register 1
0AHex Closed Captioning Register 0
0BHex Closed Captioning Register 1
0CHex Timing Register 1
NTSC (FSC = 3.5795454 MHz)
Address
00Hex Mode Register 0
01Hex Mode Register 1
Data
04Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
80Hex
00Hex
00Hex
00Hex
00Hex
00Hex
02Hex Subcarrier Frequency Register 0
03Hex Subcarrier Frequency Register 1
04Hex Subcarrier Frequency Register 2
05Hex Subcarrier Frequency Register 3
06Hex Subcarrier Phase Register
07Hex Timing Register 0
08Hex Closed Captioning Ext Register 0
09Hex Closed Captioning Ext Register 1
0AHex Closed Captioning Register 0
0BHex Closed Captioning Register 1
0CHex Timing Register 1
0DHex Mode Register 2
0EHex Pedestal Control Register 0
0FHex Pedestal Control Register 1
10Hex Pedestal Control Register 2
11Hex Pedestal Control Register 3
12Hex Mode Register 3
0DHex Mode Register 2
0EHex Pedestal Control Register 0
0FHex Pedestal Control Register 1
10Hex Pedestal Control Register 2
11Hex Pedestal Control Register 3
12Hex Mode Register 3
PAL B, D, G, H, I (FSC = 4.43361875 MHz)
Address
Data
00Hex Mode Register 0
01Hex Mode Register 1
01Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
80Hex
02Hex Subcarrier Frequency Register 0
03Hex Subcarrier Frequency Register 1
04Hex Subcarrier Frequency Register 2
05Hex Subcarrier Frequency Register 3
06Hex Subcarrier Phase Register
07Hex Timing Register 0
08Hex Closed Captioning Ext Register 0
09Hex Closed Captioning Ext Register 1
0AHex Closed Captioning Register 0
0BHex Closed Captioning Register 1
0CHex Timing Register 1
0DHex Mode Register 2
REV. 0
–35–
ADV7177/ADV7178
APPENDIX 5
OPTIONAL OUTPUT FILTER
0
If an output filter is required for the CVBS, Y, UV, Chroma and
RGB outputs of the ADV7177/ADV7178, the following filter in
Figure 63 can be used. Plots of the filter characteristics are
shown in Figures 64, 65 and 66. An output filter is not required
if the outputs of the ADV7177/ADV7178 are connected to an
analog monitor or an analog TV; however, if the output signals
are applied to a system where sampling is used (e.g., digital
TV), a filter is required to prevent aliasing.
V
– OP
dB
–5
–10
–15
–20
–25
–30
–35
L
1H
L
L
2.7H
0.68H
IN
OUT
C
470pF
C
330pF
C
56pF
R
75⍀
R
75⍀
1
10
100
FREQUENCY – MHz
Figure 63. Output Filter
Figure 65. Output Filter Close Up
0
0.0
–5
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
V
– OP
–10
dB
V
– OP
dB
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
10k
100k
1M
10M
100M
1
2
4
6
8
10
FREQUENCY – Hz
FREQUENCY – MHz
Figure 64. Output Filter Plot
Figure 66. Output Filter Plot Close Up
–36–
REV. 0
ADV7177/ADV7178
APPENDIX 6
OPTIONAL DAC BUFFERING
For external buffering of the ADV7177/ADV7178 DAC out-
puts, the configuration in Figure 67 is recommended. This
configuration shows the DAC outputs running at half (18 mA)
their full current (34.7 mA) capability. This will allow the
ADV7177/ADV7178 to dissipate less power, the analog current is
reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω. This
mode is recommended for 3.3 volt operation as optimum perfor-
mance is obtained from the DAC outputs at 18 mA with a VAA of
3.3 volts. This buffer also adds extra isolation on the video out-
puts, see buffer circuit in Figure 68. When calculating absolute
output full current and voltage, use the following equation:
VOUT = IOUT × RLOAD
VREF × K
(
=
)
IOUT
RSET
K = 4.2146 constant ,VREF = 1.235 V
V
AA
V
CC
ADV7177/ADV7178
36⍀
OUTPUT
BUFFER
V
REF
DAC A
OUTPUT TO
TV/MONITOR
75⍀
75⍀
75⍀
INPUT
2N2907
OUTPUT
BUFFER
DAC B
75⍀
75⍀
PIXEL
PORT
DIGITAL
CORE
OUTPUT
BUFFER
DAC C
R
SET
300⍀
Figure 67. Output DAC Buffering Configuration
Figure 68. Recommended Output DAC Buffer
REV. 0
–37–
ADV7177/ADV7178
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Quad Flatpack
(S-44)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
0.398 (10.11)
MAX
0.390 (9.91)
0.037 (0.94)
0.025 (0.64)
8؇
0.8؇
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
44
12
1
11
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.033 (0.84)
0.029 (0.74)
0.016 (0.41)
0.012 (0.30)
0.083 (2.11)
0.077 (1.96)
–38–
REV. 0
相关型号:
ADV7177KS-REEL
IC COLOR SIGNAL ENCODER, PQFP44, PLASTIC, MO-112-AA-1, MQFP-44, Color Signal Converter
ADI
ADV7177KSZ
IC COLOR SIGNAL ENCODER, PQFP44, LEAD FREE, PLASTIC, MO-112-AA-1, MQFP-44, Color Signal Converter
ADI
ADV7177KSZ-REEL
IC COLOR SIGNAL ENCODER, PQFP44, LEAD FREE, PLASTIC, MO-112-AA-1, MQFP-44, Color Signal Converter
ADI
©2020 ICPDF网 联系我们和版权申明