ADV7178_15_技术文档

Integrated Digital CCIR-601

to PAL/NTSC Video Encoder

ADV7177/ADV7178

FEATURES

ITU-R BT601/656 YCrCb to PAL/NTSC video encoder

High quality, 9-bit video DACs

Integral nonlinearity <1 LSB at 9 bits

NTSC-M, PAL-M/N, PAL-B/D/G/H/I

Single 27 MHz crystal/clock required ( 2 oversampling)

75 dB video SNR

Color-signal control/burst-signal control

Interlaced/noninterlaced operation

Complete on-chip video timing generator

OSD support (ADV7177 only)

Programmable multimode master/slave operation

Macrovision AntiTaping Rev. 7.01 (ADV7178 only)¹

Closed captioning support

32-bit direct digital synthesizer for color subcarrier

Multistandard video output support:

Composite (CVBS)

Component S-video (Y/C)

Component YUV or RGB

Video input data port supports:

On-board voltage reference

2-wire serial MPU interface (I²C®-compatible)

Single-supply 5 V or 3 V operation

Small 44-lead MQFP package

Synchronous 27 MHz/13.5 MHz clock output

CCIR-656 4:2:2 8-bit parallel input format

4:2:2 16-bit parallel input format

APPLICATIONS

MPEG-1 and MPEG-2 video, DVD, digital satellite,

cable systems (set-top boxes/IRDs), digital TVs,

CD video/karaoke, video games, PC video/multimedia

Full video output drive or low signal drive capability

34.7 mA max into 37.5 Ω (doubly terminated 75 R)

5 mA min with external buffers

Programmable simultaneous composite and S-VHS

(VHS) Y/C or RGB (SCART)/YUV video outputs

Programmable luma filters (low-pass/notch/extended)

Programmable VBI (vertical blanking interval)

Programmable subcarrier frequency and phase

Programmable luma delay

¹The Macrovision anticopy process is licensed for noncommercial home use

only, which is its sole intended use in the device. Please contact sales office

for latest Macrovision version available. ITU-R and CCIR are used inter-

changeably in this document (ITU-R has replaced CCIR recommendations).

Individual on/off control of each DAC

CCIR and square pixel operation

FUNCTIONAL BLOCK DIAGRAM

V

AA

ADV7177/ADV7178

DAC A

(PIN 31)

9

9-BIT

DAC

ADV7177

ONLY

YUV TO

RBG

MATRIX

9-BIT

DAC

DAC B

(PIN 27)

OSD_EN

OSD_0

OSD_1

OSD_2

9-BIT

DAC

DAC C

(PIN 26)

Y

8

9

ADD

INTER-

LOW-PASS

FILTER

SYNC

POLATOR

COLOR

DATA

4:2:2 TO

4:4:4

INTER-

YCrCb

TO

YUV

U

8

9

ADD

BURST

INTER-

POLATOR

LOW-PASS

FILTER

P7–P0

POLATOR

MATRIX

ADD

INTER-

V

P15–P8

BURST

POLATOR

LOW-PASS

FILTER

HSYNC

FIELD/VSYNC

BLANK

V

REF

9

VOLTAGE

REFERENCE

CIRCUIT

VIDEO TIMING

GENERATOR

R

SIN/COS

DDS BLOCK

SET

COMP

2

I C MPU PORT

CLOCK CLOCK CLOCK/2 RESET

SCLOCK SDATA ALSB

GND

Figure 1.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7177/ADV7178

TABLE OF CONTENTS

General Description......................................................................... 4

Closed Captioning Even Field Data Register 1–0 (CED15–

CED0).......................................................................................... 29

Specifications..................................................................................... 5

5 V Specifications......................................................................... 5

3.3 V Specifications...................................................................... 6

5 V Dynamic Specifications........................................................ 7

3.3 V Dynamic Specifications..................................................... 8

5 V Timing Specifications........................................................... 9

3.3 V Timing Specifications...................................................... 10

Absolute Maximum Ratings.......................................................... 12

Stress Ratings .............................................................................. 12

Package Thermal Performance................................................. 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 16

Data Path Description ............................................................... 16

Pixel Timing Description .......................................................... 16

Video Timing Description ........................................................ 17

Timing and Control ................................................................... 18

Power-On Reset.......................................................................... 25

MPU Port Description............................................................... 25

Registers........................................................................................... 27

Register Access............................................................................ 27

Register Programming............................................................... 27

Mode Register 0 MR0 (MR07–MR00).................................... 27

MR0 Bit Description.................................................................. 27

Mode Register 1 MR1 (MR17–MR10).................................... 28

MR1 Bit Description.................................................................. 28

Subcarrier Frequency Register 3–0.......................................... 28

Subcarrier Phase Register (FP7–FP0)...................................... 29

Timing Register 0 (TR07–TR00) ............................................. 29

TR0 Bit Description ................................................................... 29

Closed Captioning Odd Field Data Register 1–0 (CCD15–

CCD0).......................................................................................... 29

Timing Register 1 (TR17–TR10) ............................................. 30

TR1 Bit Description................................................................... 30

Mode Register 2 MR2 (MR27–MR20).................................... 30

MR2 Bit Description.................................................................. 31

NTSC Pedestal Registers 3–0 PCE15–0, PCO15–0............... 31

Mode Register 3 MR3 (MR37–MR30).................................... 31

MR3 Bit Description.................................................................. 31

OSD Register 0–11..................................................................... 32

Board Design and Layout Considerations .................................. 33

Ground Planes ............................................................................ 33

Power Planes ............................................................................... 33

Supply Decoupling..................................................................... 33

Digital Signal Interconnect....................................................... 33

Analog Signal Interconnect ...................................................... 33

Closed Captioning.......................................................................... 35

Waveform Illustrations .................................................................. 36

NTSC Waveforms With Pedestal ............................................. 36

NTSC Waveforms Without Pedestal ....................................... 37

PAL Waveforms.......................................................................... 38

UV Waveforms ........................................................................... 39

Register Values................................................................................ 40

NTSC (FSC = 3.5795454 MHZ) ............................................... 40

PAL B, D, G, H, I (FSC = 4.43361875 MHZ).......................... 40

PAL M (FSC = 3.57561149 MHZ)............................................ 40

Optional Output Filter................................................................... 41

Optional DAC Buffering ............................................................... 42

Outline Dimensions....................................................................... 43

Ordering Guide .......................................................................... 43

Rev. C | Page 2 of 44

ADV7177/ADV7178

REVISION HISTORY

3/05—Rev. B to Rev. C

Updated Format.................................................................. Universal

Changes to Figure 6.........................................................................13

Changes to Subcarrier Frequency Register 3–0 Section ............28

Changes to Register Values Section ..............................................40

Updated Outline Dimensions........................................................43

Changes to Ordering Guide...........................................................43

3/02—Rev. A to Rev. B

Changed Figures 7–13 into TPC section .....................................10

Edits to Figures 20 and 21 ..............................................................21

Rev. C | Page 3 of 44

ADV7177/ADV7178

GENERAL DESCRIPTION

The ADV7177/AD7178 are integrated digital video encoders

that convert digital CCIR-601 4:2:2 8- or 16-component video

data into a standard analog baseband television signal

compatible with worldwide standards. The 4:2:2 YUV video

data is interpolated to 2× the pixel rate. The color-difference

components (UV) are quadrature modulated using a subcarrier

frequency generated by an on-chip, 32-bit digital synthesizer

(also running at 2× the pixel rate). The 2× pixel rate sampling

allows for better signal-to-noise ratio. A 32-bit DDS with a 9-bit

look-up table produces a superior subcarrier in terms of both

frequency and phase. In addition to the composite output

signal, there is the facility to output S-video (Y/C video), YUV

or RGB video.

The ADV7177/ADV7178 also support both PAL and NTSC

square pixel operation.

The output video frames are synchronized with the incoming

data timing reference codes. Optionally, the encoder accepts

(and can generate)

,

, and FIELD timing signals.

HSYNC VSYNC

These timing signals can be adjusted to change pulse width and

position while the parts are in master mode. The encoder

requires a single, 2× pixel rate (27 MHz) clock for standard

operation. Alternatively, the encoder requires a 24.5454 MHz

clock for NTSC or 29.5 MHz clock for PAL square pixel mode

operation. All internal timing is generated on-chip.

The ADV7177/ADV7178 modes are set up over a 2-wire serial

bidirectional port (I²C-compatible) with two slave addresses.

Each analog output is capable of driving the full video-level

(34.7 mA) signal into an unbuffered, doubly terminated 75 Ω

load. With external buffering, the user has the additional option

to scale back the DAC output current to 5 mA min, thereby

significantly reducing the power dissipation of the device.

Functionally, the ADV7178 and the ADV7177 are the same

except that the ADV7178 can output the Macrovision anticopy

algorithm, and OSD is only supported on the ADV7177.

The ADV7177/ADV7178 are packaged in a 44-lead, thermally

enhanced MQFP package.

Rev. C | Page 4 of 44

ADV7177/ADV7178

SPECIFICATIONS

5 V SPECIFICATIONS

V_AA= 5 V 5ꢀ,¹V_REF= 1.235 V, R_SET= 300 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 1.

1

Parameter

Conditions

Min

Typ

Max

Unit

STATIC PERFORMANCE³

Resolution (Each DAC)

Accuracy (Each DAC)

9

Bits

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUTS³

±±.ꢀ

LSB

Guaranteed monotonic

Input High Voltage, V_INH

Input Low Voltage, V_INL

2

V

µA

pF

ꢀ.8

±±

± 5ꢀ

4

Input Current, I_IN

V_IN= ꢀ.4 V or 2.4 V

5

Input Capacitance, C_IN

DIGITAL OUTPUTS³

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

ANALOG OUTPUTS³

Output Current⁶

±ꢀ

I_SOURCE= 4ꢀꢀ µA

I_SINK= 3.2 mA

2.4

V

µA

pF

ꢀ.4

±ꢀ

R_SET= 3ꢀꢀ Ω, R_L= 75 Ω

±6.5

ꢀ

±7.35

5

ꢀ.6

±8.5

mA

%

V

kΩ

pF

Output Current⁷

DAC-to-DAC Matching

Output Compliance, V_OC

Output Impedance, R_OUT

Output Capacitance, C_OUT

VOLTAGE REFERENCE³

Reference Range, V_REF

POWER REQUIREMENTS^{3, 8}

V_AA

5

±.4

±5

I_OUT= ꢀ mA

3ꢀ

I_VREFOUT= 2ꢀ µA

±.±±2

4.75

±.235

5.ꢀ

±.359

5.25

V

Low Power Mode

I_DAC(max)⁹

62

25

±ꢀꢀ

ꢀ.ꢀ±

mA

%/%

I_DAC(min)⁹

±ꢀ

I_CCT

±5ꢀ

ꢀ.5

Power-Supply Rejection Ratio

COMP = ꢀ.± µF

^±The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

²Temperature range T_MINto T_MAX: ꢀ°C to 7ꢀ°C.

³Guaranteed by characterization.

4

RESET

, OSDꢀ, and CLOCK.

All digital input pins except pins

5

RESET

, OSDꢀ, and CLOCK.

Excluding all digital input pins except pins

⁶Full drive into 75 Ω load.

⁷Minimum drive current (used with buffered/scaled output load).

⁸Power measurements are taken with clock frequency = 27 MHz. Max T_J= ±±ꢀ°C.

⁹I_DACis the total current (min corresponds to 5 mA output per DAC, max corresponds to ±8.5 mA output per DAC) to drive all three DACs. Turning off individual DACs

reduces I_DACcorrespondingly.

±ꢀ

I

(circuit current) is the continuous current required to drive the device.

CCT

Rev. C | Page 5 of 44

ADV7177/ADV7178

3.3 V SPECIFICATIONS

V_AA= 3.0 V to 3.6 V¹, V_REF= 1.235 V, R_SET= 300 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 2.

1

Parameter

Conditions

Min

Typ

Max

Unit

STATIC PERFORMANCE³

Resolution (Each DAC)

Accuracy (Each DAC)

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUTS

9

Bits

±ꢀ.5

LSB

Guaranteed monotonic

Input High Voltage, V_INH

Input Low Voltage, V_INL

2

ꢀ.8

V

µA

pF

3, 4

Input Current, I_IN

V_IN= ꢀ.4 V or 2.4 V

±±

±5ꢀ

3, 5

Input Capacitance, C_IN

DIGITAL OUTPUTS

±ꢀ

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current³

Three-State Output Capacitance³

ANALOG OUTPUTS³

Output Current^{6, 7}

I_SOURCE= 4ꢀꢀ µA

I_SINK= 3.2 mA

2.4

ꢀ.4

V

µA

pF

±ꢀ

±6.5

ꢀ

±7.35

5

2.ꢀ

±8.5

mA

%

V

kΩ

pF

R_SET= 3ꢀꢀ Ω, R_L= 75 Ω

Output Current⁸

DAC-to-DAC Matching

Output Compliance, V_OC

Output Impedance, R_OUT

Output Capacitance, C_OUT

POWER REQUIREMENTS^{3, 9}

V_AA

Normal Power Mode

I_DAC(max)^±ꢀ

I_DAC(min)³

±.4

3ꢀ

±5

I_OUT= ꢀ mA

3.ꢀ

3.3

3.6

±±6

V

R_SET= 3ꢀꢀ Ω, R_L= ±5ꢀ Ω

±±3

±5

45

mA

9

I_CCT

Low Power Mode

I_DAC(max)³

6ꢀ

25

45

ꢀ.ꢀ±

mA

%/%

I_DAC(min)³

±±

I_CCT

Power-Supply Rejection Ratio

COMP = ꢀ.± µF

ꢀ.5

^±The max/min specifications are guaranteed over this range. The max/min values are typical over 3.ꢀ V to 3.6 V.

²Temperature range T_MINto T_MAX: ꢀ°C to 7ꢀ°C.

³Guaranteed by characterization.

4

RESET

, OSDꢀ, and CLOCK.

All digital input pins except pins

5

RESET

, OSDꢀ, and CLOCK.

Excluding all digital input pins except pins

⁶Full drive into 75 Ω load.

⁷DACs can output 35 mA typically at 3.3 V (R_SET= ±5ꢀ Ω and R_L= 75 Ω), optimum performance obtained at ±8 mA DAC current (R_SET= 3ꢀꢀ Ω and R_L= ±5ꢀ Ω).

⁸Minimum drive current (used with buffered/scaled output load).

⁹Power measurements are taken with clock frequency = 27 MHz. Max T_J= ±±ꢀ°C.

±ꢀ

I

is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all three DACs. Turning off individual DACs

DAC

reduces IDAC correspondingly.

±±

I

(circuit current) is the continuous current required to drive the device.

CCT

Rev. C | Page 6 of 44

ADV7177/ADV7178

5 V DYNAMIC SPECIFICATIONS

V_AA= 4.75 V to 5.25 V,¹V_REF= 1.235 V, R_SET= 300 Ω. All specifications T_MINto T_MAX,²unless otherwise noted.

Table 3.

Parameter

Conditions¹

Min

Typ

Max

Unit

FILTER CHARACTERISTICS

Luma Bandwidth³(Low-Pass Filter)

Stop-Band Cutoff

Pass-Band Cutoff, F_{3 dB}

Chroma Bandwidth

Stop-Band Cutoff

Pass-Band Cutoff, F_{3 dB}

Luma Bandwidth³(Low-Pass Filter)

Stop-Band Cutoff

Pass-Band Cutoff, F_{3 dB}

Chroma Bandwidth

Stop-Band Cutoff

NTSC Mode

>54 dB Attenuation

>3 dB Attenuation

NTSC Mode

>4ꢀ dB Attenuation

>3 dB Attenuation

PAL Mode

>5ꢀ dB Attenuation

>3 dB Attenuation

PAL Mode

>4ꢀ dB Attenuation

>3 dB Attenuation

Lower Power Mode

RMS

7.ꢀ

4.2

MHz

3.2

2.ꢀ

MHz

7.4

5.ꢀ

MHz

4.ꢀ

2.4

MHz

%

Degrees

dB rms

dB p-p

dB rms

dB p-p

Degrees

%

Pass-Band Cutoff F_{3 dB}

Differential Gain⁴

Differential Phase⁴

SNR⁴(Pedestal)

2.ꢀ

±.5

75

7ꢀ

57

Peak Periodic

RMS

Peak Periodic

SNR⁴(Ramp)

56

Hue Accuracy⁴

±.2

±.4

±.ꢀ

ꢀ.4

ꢀ.6

ꢀ.2

ꢀ.6

2.ꢀ

±.2

64

Color Saturation Accuracy⁴

Chroma Nonlinear Gain⁴

Chroma Nonlinear Phase⁴

Referenced to 4ꢀ IRE

NTSC

PAL

Referenced to 7±4 mV (NTSC)

Referenced to 7ꢀꢀ mV (PAL)

± %

± Degrees

± %

ns

± %

dB

Chroma/Luma Intermod⁴

Chroma/Luma Gain Inequality⁴

Chroma/Luma Delay Inequality⁴

Luminance Nonlinearity⁴

Chroma AM Noise⁴

Chroma PM Noise⁴

62

^±The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

²Temperature range T_MINto T_MAX: ꢀ°C to 7ꢀ°C.

³These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table ±ꢀ.

⁴Guaranteed by characterization.

Rev. C | Page 7 of 44

ADV7177/ADV7178

3.3 V DYNAMIC SPECIFICATIONS

V_AA= 3.0 V to 3.6 V,¹V_REF= 1.235 V, R_SET= 300 Ω. All specifications T_MINto T_MAX,²unless otherwise noted.

Table 4.

Parameter

Conditions¹

Min

Typ

Max

Unit

FILTER CHARACTERISTICS

Luma Bandwidth³(Low-Pass Filter)

Stop-Band Cutoff

Pass-Band Cutoff, F_{3 dB}

Chroma Bandwidth

Stop-Band Cutoff

Pass-Band Cutoff, F_{3 dB}

Luma Bandwidth³(Low-Pass Filter)

Stop-Band Cutoff

Pass-Band Cutoff, F_{3 dB}

Chroma Bandwidth

Stop-Band Cutoff

NTSC mode

>54 dB attenuation

>3 dB attenuation

NTSC mode

>4ꢀ dB attenuation

>3 dB attenuation

PAL mode

>5ꢀ dB attenuation

>3 dB attenuation

PAL mode

>4ꢀ dB attenuation

>3 dB attenuation

Normal power mode

RMS

7.ꢀ

4.2

MHz

3.2

2.ꢀ

MHz

7.4

5.ꢀ

MHz

4.ꢀ

2.4

MHz

%

Degrees

dB rms

dB p-p

dB rms

dB p-p

Degrees

%

Pass-Band Cutoff, F_{3 dB}

Differential Gain⁴

Differential Phase⁴

SNR⁴(Pedestal)

±.ꢀ

7ꢀ

64

56

54

±.2

±.4

64

62

64

62

Peak periodic

RMS

Peak periodic

SNR⁴(Ramp)

Hue Accuracy⁴

Color Saturation Accuracy⁴

Luminance Nonlinearity⁴

Chroma AM Noise⁴

Chroma PM Noise⁴

Chroma AM Noise⁴

Chroma PM Noise⁴

± %

dB

NTSC

PAL

dB

^±The max/min specifications are guaranteed over this range. The max/min values are typical over 3.ꢀ V to 3.6 V.

²Temperature range T_MINto T_MAX: ꢀ°C to 7ꢀ°C.

³These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 7.

⁴Guaranteed by characterization.

Rev. C | Page 8 of 44

ADV7177/ADV7178

5 V TIMING SPECIFICATIONS

V_AA= 4.75 V to 5.25 V,¹V_REF= 1.235 V, R_SET= 300 Ω. All specifications T_MINto T_MAX,²unless otherwise noted.

Table 5.

Parameter

MPU PORT^{3, 4}

Conditions

Min

Typ

Max

Unit

SCLOCK Frequency

ꢀ

±ꢀꢀ

kHz

µs

ns

µs

ns

µs

SCLOCK High Pulse Width, t_±

SCLOCK Low Pulse Width, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

CLOCK CONTROL AND PIXEL PORT^{3, 4, 6}

f_CLOCK

4.ꢀ

4.7

4.ꢀ

4.7

25ꢀ

After this period, the first clock is generated

Relevant for repeated start condition

±

3ꢀꢀ

4.7

5

ꢀ

ns

27

MHz

Clock High Time, t₉

8

ns

Clock Low Time, t_±ꢀ

8

ns

Data Setup Time, t_±±

Data Hold Time, t_±2

3.5

4

ns

Control Setup Time, t_±±

Control Hold Time, t_±2

Digital Output Access Time, t_±3

Digital Output Hold Time, t_±4

Pipeline Delay, t_±5

4

3

ns

24

4

37

Clock Cycles

RESET CONTROL^{3, 4}

RESET Low Time

6

ns

INTERNAL CLOCK CONTROL

Clock/2 Rise Time, t_±6

Clock/2 Fall Time, t_±7

OSD TIMING⁴

7

ns

OSD Setup Time, t_±8

OSD Hold Time, t_±9

6

2

ns

^±The max/min specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX: ꢀ°C to 7ꢀ°C.

³TTL input values are ꢀ V to 3 V, with input rise/fall times ≤ 3 ns, measured between the ±ꢀ% and 9ꢀ% points. Timing reference points at 5ꢀ% for inputs and outputs.

Analog output load ≤ ±ꢀ pF.

⁴Guaranteed by characterization.

⁵Output delay measured from the 5ꢀ% point of the rising edge of CLOCK to the 5ꢀ% point of full-scale transition.

⁶Pixel port consists of the following:

Pixel inputs: P±5–Pꢀ

HSYNC

VSYNC BLANK

Pixel controls:

Clock input: CLOCK

, FIELD/

,

Rev. C | Page 9 of 44

ADV7177/ADV7178

3.3 V TIMING SPECIFICATIONS

V_AA= 3.0 V–3.6 V,¹V_REF= 1.235 V, R_SET= 300 Ω. All specifications T_MINto T_MAX,²unless otherwise noted.

Table 6.

Parameter

MPU PORT^{3, 4}

Conditions

Min

Typ

Max

Unit

SCLOCK Frequency

ꢀ

±ꢀꢀ

kHz

µs

ns

µs

ns

µs

SCLOCK High Pulse Width, t_±

SCLOCK Low Pulse Width, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

CLOCK CONTROL AND PIXEL PORT^{3, 4, 6}

f_CLOCK

4.ꢀ

4.7

4.ꢀ

4.7

25ꢀ

After this period the first clock is generated

Repeated for start condition

±

3ꢀꢀ

4.7

7

ꢀ

ns

27

MHz

Clock High Time, t₉

8

ns

Clock Low Time, t_±ꢀ

8

ns

Data Setup Time, t_±±

Data Hold Time, t_±2

3.5

4

ns

Control Setup Time, t_±±

Control Hold Time, t_±2

Digital Output Access Time, t_±3

Digital Output Hold Time, t_±4

Pipeline Delay, t_±5

4

3

ns

24

4

37

Clock cycles

RESET CONTROL^{3, 4}

RESET Low Time

6

ns

INTERNAL CLOCK CONTROL

Clock/2 Rise Time, t_±6

Clock/2 Fall Time, t_±7

OSD TIMING⁴

±ꢀ

ns

OSD Setup Time, t_±8

OSD Hold Time, t_±9

±ꢀ

2

ns

^±The max/min specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX: ꢀ°C to 7ꢀ°C.

³TTL input values are ꢀ V to 3 V, with input rise/fall times ≤ 3 ns, measured between the ±ꢀ% and 9ꢀ% points. Timing reference points at 5ꢀ% for inputs and outputs.

Analog output load ≤ ±ꢀ pF.

⁴Guaranteed by characterization.

⁵Output delay measured from the 5ꢀ% point of the rising edge of CLOCK to the 5ꢀ% point of full-scale transition.

⁶Pixel port consists of the following:

Pixel inputs: P±5–Pꢀ

HSYNC

VSYNC BLANK

Pixel controls:

Clock input: CLOCK

, FIELD/

,

Rev. C | Page ±ꢀ of 44

ADV7177/ADV7178

t₃

t₅

t₃

SDATA

t₆

t₁

SCLOCK

t₂

t₇

t₄

t₈

Figure 2. MPU Port Timing Diagram

CLOCK

HSYNC,

t₉

t₁₀

t₁₂

CONTROL

I/PS

FIELD/VSYNC,

BLANK

PIXEL INPUT

DATA

Cb

Y

Cr

Y

Cb

Y

t₁₁

t₁₃

HSYNC,

FIELD/VSYNC,

BLANK

CONTROL

O/PS

t₁₄

Figure 3. Pixel and Control Data Timing Diagram

t₁₆

t₁₇

CLOCK

CLOCK/2

t₁₆

t₁₇

CLOCK

CLOCK/2

Figure 4. Internal Timing Diagram

t₁₈

t₁₉

CLOCK

OSD_EN

OSD0–2

Figure 5. OSD Timing Diagram

Rev. C | Page ±± of 44

ADV7177/ADV7178

ABSOLUTE MAXIMUM RATINGS

STRESS RATINGS

PACKAGE THERMAL PERFORMANCE

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

The 44-lead MQFP package used for this device has a junction-

to-ambient thermal resistance (θ_JA) in still air on a 4-layer PCB

of 53.2°C/W. The junction-to-case thermal resistance (θ_JC) is

18.8°C/W. Care must be taken when operating the part in

certain conditions to prevent overheating. Table 8 lists the

conditions to use when using the part.

Table 7.

Table 8. Allowable Operating Conditions

Parameter

Rating

Condition

5 V

No

Yes

No

3 V

Yes

V_AAto GND

7 V

3 DACs on, double 75 R^±

3 DACs on, low power²

3 DACs on, buffered³

2 DACs on, double 75 R

2 DACs on, low power

2 DACs on, buffered

Voltage on Any Digital Input Pin

Storage Temperature (T_S)

Junction Temperature (T_J)

Lead Temperature

(Soldering, ±ꢀ sec)

Analog Outputs to GND^±

GND – ꢀ.5 V to V_AA+ ꢀ.5 V

–65°C to +±5ꢀ°C

±5ꢀ°C

Yes

26ꢀ°C

GND – ꢀ.5 V to V_AA

^±DAC on, double 75 R refers to a condition where the DACs are terminated

into a double 75 R load and low power mode is disabled.

^±Analog output short circuit to any power supply or common can be of an

indefinite duration.

²DAC on, low power refers to a condition where the DACs are terminated in

a double 75 R load and low power mode is enabled.

³DAC on, buffered refers to a condition where the DAC current is reduced to

5 mA and external buffers are used to drive the video loads.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4ꢀꢀꢀ V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page ±2 of 44

ADV7177/ADV7178

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

44 43 42 41 40 39 38 37 36 35 34

1

33

32

31

30

29

28

27

26

25

24

23

V

R

AA

SET

PIN 1

2

3

CLOCK/2

P5

V

REF

DAC A

4

P6

V

AA

5

P7

GND

AD7177/ADV7178

6

P8

V

MQFP

AA

7

P9

TOP VIEW

(Not to Scale)

DAC B

DAC C

COMP

8

P10

9

P11

10

11

P12

SDATA

SCLOCK

OSD_EN

12 13 14 15 16 17 18 19 20 21 22

Figure 6. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

±, 2ꢀ, 28, 3ꢀ

2

Mnemonic I/O

Function

V_AA

P

Power Supply.

CLOCK/2

O

Synchronous Clock Output Signal. Can be either 27 MHz or ±3.5 MHz; this can be controlled by MR32

and MR33 in Mode Register 3.

3 to ±ꢀ,

±2 to ±4,

37 to 4±

P5 to P±2,

P±3 to ±4,

Pꢀ to P4

I

8-Bit, 4:2:2 Multiplexed YCrCb Pixel Port (P7–Pꢀ) or ±6-Bit YCrCb Pixel Port (P±5–Pꢀ). Pꢀ represents the

LSB.

±±

±5

OSD_EN

HSYNC

I

Enables OSD input data on the video outputs.

HSYNC (Modes ± and 2) Control Signal. This pin can be configured to output (master mode) or accept

(slave mode) Sync signals.

I/O

±6

FIELD/

VSYNC

I/O

Dual Function Field (Mode ±) and VSYNC (Mode 2) Control Signal. This pin can be configured to

output (master mode) or accept (slave mode) these control signals.

Video Blanking Control Signal. The pixel inputs are ignored when this is Logic ꢀ. This signal is optional.

±7

±8

BLANK

ALSB

I/O

I

G

I

TTL Address Input. This signal sets up the LSB of the MPU address.

Ground Pin.

The input resets the on-chip timing generator and sets the ADV7±77/ADV7±78 into default mode. This

is NTSC operation, Timing Slave Mode ꢀ, 8-bit operation, 2× composite and S VHS out.

±9, 2±, 29, 42 GND

22

RESET

23

24

25

26

27

3±

32

33

SCLOCK

SDATA

COMP

DAC C

DAC B

DAC A

V_REF

I

MPU Port Serial Interface Clock Input.

MPU Port Serial Data Input/Output.

Compensation Pin. Connect a ꢀ.± µF capacitor from COMP to V_AA

DAC C Analog Output.

DAC B Analog Output.

DAC A Analog Output.

Voltage Reference Input for DACs or Voltage Reference Output (±.235 V).

A 3ꢀꢀ Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video

signals.

I/O

O

I/O

I

.

R_SET

34–36

OSD_ꢀ to

OSD_2

I

On Screen Display Inputs.

43

44

CLOCK

O

I

Crystal Oscillator Output (to crystal). Leave unconnected if no crystal is used.

Crystal Oscillator Input. If no crystal is used, this pin can be driven by an external TTL clock source; it

requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC)

or 29.5 MHz (PAL) can be used for square pixel operation.

Rev. C | Page ±3 of 44

ADV7177/ADV7178

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–10

TYPE A

–20

–30

–40

–50

TYPE B

–60

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 7. NTSC Low-Pass Filter

Figure 10. PAL Notch Filter

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

0

2

4

6

8

10

12

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 11. NTSC/PAL Extended Mode Filter

Figure 8. NTSC Notch Filter

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

TYPE A

TYPE B

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 12. NTSC UV Filter

Figure 9. PAL Low-Pass Filter

Rev. C | Page ±4 of 44

ADV7177/ADV7178

0

–10

–20

–30

–40

–50

–60

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 13 . PAL UV Filter

Rev. C | Page ±5 of 44

ADV7177/ADV7178

THEORY OF OPERATION

DATA PATH DESCRIPTION

Color-Bar Generation

For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb

4:2:2 data is input via the CCIR-656-compatible pixel port at

a 27 MHz data rate. The pixel data is demultiplexed to form

three data paths. Y typically has a range of 16 to 235, Cr and

Cb typically have a range of 128 112; however, it is possible

to input data from 1 to 254 on both Y, Cb and Cr. The

The devices can be configured to generate 100/7.5/75/7.5 color

bars for NTSC or 100/0/75/0 for PAL color bars. These are

enabled by setting MR17 of Mode Register 1 to Logic 1.

Square Pixel Mode

The ADV7177/ADV7178 can be used to operate in square pixel

mode. For NTSC operation, an input clock of 24.5454 MHz is

required. Alternatively, an input clock of 29.5 MHz is required

for PAL operation. The internal timing logic adjusts accordingly

for square pixel mode operation.

ADV7177/ADV7178 support PAL (B, D, G, H, I, N, M) and

NTSC (with and without pedestal) standards. The appropriate

SYNC,

, and burst levels are added to the YCrCb data.

BLANK

Macrovision AntiTaping (ADV7178 only), closed captioning,

OSD (ADV7177 only), and teletext levels are also added to Y,

and the resulting data is interpolated to a rate of 27 MHz. The

interpolated data is filtered and scaled by three digital FIR

filters.

Color Signal Control

The color information can be switched on and off the video

output by using Bit MR24 of Mode Register 2.

The U and V signals are modulated by the appropriate

subcarrier sine/cosine phases and added together to make up

the chrominance signal. The luma (Y) signal can be delayed

1 to 3 luma cycles (each cycle is 74 ns) with respect to the

chroma signal. The luma and chroma signals are then added

together to make up the composite video signal. All edges are

slew-rate limited.

Burst Signal Control

The burst information can be switched on and off the video

output using Bit MR25 of Mode Register 2.

NTSC Pedestal Control

The pedestal on both odd and even fields can be controlled on a

line-by-line basis by using the NTSC pedestal control registers.

This allows the pedestals to be controlled during the vertical

blanking interval.

The YCrCb data is also used to generate RGB data with

appropriate SYNC and

levels. The RGB data is in

BLANK

PIXEL TIMING DESCRIPTION

synchronization with the composite video output. Alternatively,

analog YUV data can be generated instead of RGB.

The ADV7177/ADV7178 can operate in either 8-bit or 16-bit

YCrCb mode.

The three 9-bit DACs can be used to output:

8-Bit YCrCb Mode

•

RGB video

YUV video

This default mode accepts multiplexed YCrCb inputs through

the P7 to P0 pixel inputs. The inputs follow the sequence Cb0,

Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a

rising clock edge.

One composite video signal + LUMA and CHROMA

(S-video).

Alternatively, each DAC can be individually powered off if not

required.

16-Bit YCrCb Mode

This mode accepts Y inputs through the P7 to P0 pixel inputs

and multiplexed CrCb inputs through the P15 to P8 pixel

inputs. The data is loaded on every second rising edge of

CLOCK. The inputs follow the sequence Cb0, Y0 Cr0,

Y1 Cb1, Y2, etc.

Video output levels are illustrated in the section NTSC

Waveforms With Pedestal.

Internal Filter Response

The Y filter supports several different frequency responses,

including two 4.5 MHz/5.0 MHz low-pass responses, PAL/

NTSC subcarrier notch responses, and a PAL/NTSC extended

response. The U and V filters have a 1.0 MHz/1.3 MHz low-

pass response for NTSC/PAL. These filter characteristics are

illustrated in the Typical Performance Characteristics section.

OSD

The ADV7177 supports OSD. There are twelve, 8-bit OSD

registers loaded with data from the four most significant bits of

Y, Cb, Cr input pixel data bytes. A choice of eight colors can,

therefore, be selected via the OSD_0, OSD_1, OSD_2 pins, each

color being a combination of 12 bits of Y, Cb, Cr pixel data. The

display is under control of the OSD_EN pin. The OSD window

can be an entire screen or just one pixel, and its size may change

by using the OSD_EN signal to control the width on a line-by-

line basis. Figure 5 illustrates OSD timing on the ADV7177.

Rev. C | Page ±6 of 44

ADV7177/ADV7178

VIDEO TIMING DESCRIPTION

of 29.5 MHz for PAL. The internal horizontal line counters

place the various video waveform sections in the correct

location for the new clock frequencies.

The ADV7177/ADV7178 are intended to interface to off-the-

shelf MPEG1 and MPEG2 decoders. Consequently, the

ADV7177/ADV7178 accept 4:2:2 YCrCb pixel data via a

CCIR-656 pixel port, and have several video timing modes

allowing them to be configured as either a system master

video timing generator or a slave to the system video timing

generator. The ADV7177/ADV7178 generate all of the required

horizontal and vertical timing periods and levels for the analog

video outputs. It is important to note that the CCIR-656 data

stream should not contain ancillary data packets as per the

BT1364 specification. This data can corrupt the internal

synchronization circuitry of the devices, resulting in loss of

synchronization on the output.

The ADV7177/ADV7178 have four distinct master and four

distinct slave timing configurations. Timing control is

established with the bidirectional

,

, and

SYNC BLANK

FIELD/

pins. Timing Mode Register 1 can also be used

VSYNC

to vary the timing pulse widths and where they occur in

relation to each other.

Vertical Blanking Data Insertion (VBI)

It is possible to allow encoding of incoming YCbCr data on

those lines of VBI that do not bear line sync or pre- and post-

equalization pulses (see the Typical Performance Characteristics

section). This mode of operation is called partial blanking and

is selected by setting MR31 to 1. It allows the insertion of any

VBI data (opened VBI) into the encoded output waveform. This

data is present in the digitized incoming YCbCr data stream

(for example, WSS data, CGMS, and VPS). Alternatively, the

entire VBI can be blanked (no VBI data inserted) on these lines

by setting MR31 to 0.

The ADV7177/ADV7178 calculate the width and placement of

analog sync pulses, blanking levels, and color burst envelopes.

Color bursts are disabled on appropriate lines, and serration

and equalization pulses are inserted where required.

In addition, the ADV7177/ADV7178 support a PAL or NTSC

square pixel operation in slave mode. The parts require an input

pixel clock of 24.5454 MHz for NTSC and an input pixel clock

Table 10. Luminance Internal Filter Specifications

Pass-Band

Cutoff (MHz)

Pass-Band

Ripple (dB)

Stop-Band

Cutoff (MHz)

Stop-Band

Attenuation (dB) F_{3 dB}

Filter Selection MR04

MR03

NTSC

PAL

NTSC

PAL

NTSC/PAL

NTSC

PAL

ꢀ

±

ꢀ

±

ꢀ

±

2.3

3.4

±.ꢀ

±.4

4.ꢀ

2.3

3.4

ꢀ.ꢀ26

ꢀ.ꢀ98

ꢀ.ꢀ85

ꢀ.±ꢀ7

ꢀ.±5ꢀ

ꢀ.ꢀ54

ꢀ.±ꢀ6

7.ꢀ

7.3

3.57

4.43

7.5

>54

>5ꢀ

>27.6

>29.3

>4ꢀ

4.2

5.ꢀ

2.±

2.7

5.35

4.2

5.ꢀ

7.ꢀ

7.3

>54

>5ꢀ.3

Table 11. Chrominance Internal Filter Specifications

Pass-Band

Cutoff (MHz)

Pass-Band

Ripple (dB)

Stop-Band

Cutoff (MHz)

Stop-Band

Attenuation (dB)

Attenuation

@ 1.3 MHz (dB)

Filter Selection

NTSC

PAL

F_{3 dB}

2.ꢀ5

2.45

±.ꢀ

±.3

ꢀ.ꢀ85

ꢀ.ꢀ4

3.2

4.ꢀ

>4ꢀ

ꢀ.3

ꢀ.ꢀ2

Rev. C | Page ±7 of 44

ADV7177/ADV7178

TIMING AND CONTROL

Mode 0 (CCIR-656): Slave Option

Timing Register 0 TR0 = X X X X X 0 0 0

The ADV7177/ADV7178 are controlled by the start active video (SAV) and end active video (EAV) time codes in the pixel data. All

timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after

each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The

, FIELD/

, and

(if not used)

HSYNC

VSYNC

BLANK

pins should be tied high during this mode.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

r

F

0

X

Y

8

0

1

0

8

0

1

0

F

A

B

A

B

A

B

8

0

1

0

8

0

1

0

F

0

X

Y

C

r

C

b

C

Y

INPUT PIXELS

b

r

b

ANCILLARY DATA

(HANC)

4 CLOCK

NTSC/PAL M SYSTEM

(525 LlNES/60Hz)

1440 CLOCK

268 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

280 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

Figure 14. Timing Mode 0 (Slave Mode)

Mode 0 (Ccir-656): Master Option

Timing Register 0 TR0 = X X X X X 0 0 1

The ADV7177/ADV7178 generate H, V, and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is

output on the pin, the V bit is output on the pin, and the F bit is output on the FIELD/ pin. Mode 0 is illustrated

HSYNC

BLANK

VSYNC

in Figure 15 (NTSC) and Figure 16 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 17.

DISPLAY

VERTICAL BLANK

522

523

524

525

1

2

3

4

6

7

10

11

20

21

22

5

9

8

H

V

F

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

H

V

F

ODD FIELD

EVEN FIELD

Figure 15. Timing Mode 0 (NTSC Master Mode)

Rev. C | Page ±8 of 44

ADV7177/ADV7178

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

22

23

5

21

H

V

F

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

318

334

335

336

309

310

311

312

313

314

315

316

317

319

320

H

V

F

ODD FIELD

EVEN FIELD

Figure 16. Timing Mode 0 (PAL Master Mode)

ANALOG

VIDEO

H

F

V

Figure 17. Timing Mode 0 Data Transitions (Master Mode)

Rev. C | Page ±9 of 44

ADV7177/ADV7178

Mode 1: Slave Option

,

, FIELD

HSYNC BLANK

Timing Register 0 TR0 = X X X X X 0 1 0

In this mode, the ADV7177/ADV7178 accepts horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when

HSYNC is low indicates a new frame, that is, vertical retrace. The signal is optional. When the input is disabled, the

BLANK

ADV7177/ADV7178 automatically blank all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 18. Timing Mode 1 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

5

21

22

23

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 19. Timing Mode 1 (PAL)

Rev. C | Page 2ꢀ of 44

ADV7177/ADV7178

Mode 1: Master Option

,

, FIELD

HSYNC BLANK

Timing Register 0 TR0 = X X X X X 0 1 1

In this mode, the ADV7177/ADV7178 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when

is low indicates a new frame, that is, vertical retrace. The signal is optional. When the input is disabled, the

HSYNC

BLANK

ADV7177/ADV7178 automatically blank all normally blank lines. Pixel data is latched on the rising clock edge following the timing

signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the

for an odd or even field transition relative to the pixel data.

,

, and FIELD

HSYNC BLANK

HSYNC

FIELD

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Rev. C | Page 2± of 44

ADV7177/ADV7178

Mode 2: Slave Option

,

HSYNC VSYNC BLANK

Timing Register 0 TR0 = X X X X X 1 0 0

In this mode, the ADV7177/ADV7178 accept horizontal and vertical SYNC signals. A coincident low transition of both

and

HSYNC

inputs indicates the start of an odd field. A

low transition when

is high indicates the start of an even field. The

HSYNC

VSYNC

BLANK

VSYNC

signal is optional. When the

input is disabled, the ADV7177/ADV7178 automatically blank all normally blank lines as

BLANK

per the BT-470 specification. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

Figure 21. Timing Mode 2 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

5

6

7

21

22

23

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

317

318

319

320

334

335

336

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

Figure 22. Timing Mode 2 (PAL)

Rev. C | Page 22 of 44

ADV7177/ADV7178

Mode 2: Master Option

,

HSYNC VSYNC BLANK

Timing Register 0 TR0 = X X X X X 1 0 1

In this mode, the ADV7177/ADV7178 can generate horizontal and vertical SYNC signals. A coincident low transition of both

HSYNC

is high indicates the start of an even field.

and

The

inputs indicates the start of an odd field. A

signal is optional. When the

low transition when

HSYNC

VSYNC

BLANK

VSYNC

input is disabled, the ADV7177/ADV7178 automatically blank all normally blank lines

BLANK

as per the BT-470 specification. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illustrates the

,

HSYNC BLANK

, and for an

HSYNC BLANK VSYNC

and

for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the

,

VSYNC

odd-to-even field transition relative to the pixel data.

HSYNC

VSYNC

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

DATA

Cb

Y

Cr

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 23. Timing Mode 2, Even-to-Odd Field Transition, Master/Slave

HSYNC

VSYNC

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

DATA

Cb

Y

Cr

Y

Cb

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 24. Timing Mode 2, Odd-to-Even Field Transition, Master/Slave

Rev. C | Page 23 of 44

ADV7177/ADV7178

Mode 3: Master/Slave Option

,

, FIELD

HSYNC BLANK

Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1

In this mode, the ADV7177/ADV7178 accept or generate horizontal SYNC and odd/even field signals. A transition of the field input

when

is high indicates a new frame, that is, vertical retrace. The

signal is optional. When the

input is disabled,

HSYNC

BLANK

the ADV7177/ADV7178 automatically blank all normally blank lines as per the BT-470 specification. Mode 3 is illustrated in Figure 25

(NTSC) and Figure 26 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

1

2

3

4

5

6

7

8

9

10

11

20

21

22

HSYNC

BLANK

EVEN FIELD ODD FIELD

FIELD

DISPLAY

VERTICAL BLANK

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

HSYNC

BLANK

ODD FIELD EVEN FIELD

FIELD

Figure 25. Timing Mode 3 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

5

6

7

21

22

23

HSYNC

BLANK

EVEN FIELD ODD FIELD

FIELD

DISPLAY

VERTICAL BLANK

318

334

335

336

309

310

311

312

313

314

315

316

317

319

320

HSYNC

BLANK

ODD FIELD EVEN FIELD

FIELD

Figure 26. Timing Mode 3 (PAL)

Rev. C | Page 24 of 44

ADV7177/ADV7178

POWER-ON RESET

After power-up, it is necessary to execute a reset operation. A

reset occurs on the falling edge of a high-to-low transition on

respond to the start condition and shift the next eight bits (7-bit

address + R/ bit). The bits transfer from MSB down to LSB.

W

the

pin. This initializes the pixel port so that the pixel

RESET

The peripheral that recognizes the transmitted address

responds by pulling the data line low during the ninth clock

pulse. This is known as an acknowledge bit. All other devices

withdraw from the bus at this point and maintain an idle

condition. The idle condition is where the device monitors the

SDATA and SCLOCK lines waiting for the start condition and

inputs, P7 to P0, are selected. After reset, the devices are

automatically set up to operate in NTSC mode. Subcarrier

frequency code 21F07C16HEX is loaded into the subcarrier

frequency registers. All other registers, except Mode Register 0,

are set to 00HEX. All bits in Mode Register 0 are set to Logic 0

except Bit MR02. Bit MR02 of Mode Register 0 is set to Logic 1.

This enables the 7.5 IRE pedestal.

the correct transmitted address. The R/ bit determines the

W

direction of the data. A Logic 0 on the LSB of the first byte

means that the master writes information to the peripheral. A

Logic 1 on the LSB of the first byte means that the master reads

information from the peripheral.

MPU PORT DESCRIPTION

The ADV7178 and ADV7177 support a 2-wire serial (I²C-

compatible) microprocessor bus driving multiple peripherals.

Two inputs, serial data (SDATA) and serial clock (SCLOCK),

carry information between any device connected to the bus.

Each slave device is recognized by a unique address. The

ADV7178 and ADV7177 each have four possible slave

addresses for both read and write operations. These are

unique addresses for each device and are illustrated in

Figure 27 and Figure 28. The LSB sets either a read or write

operation. Logic 1 corresponds to a read operation, while Logic

0 corresponds to a write operation. A1 is set by setting the

ALSB pin of the ADV7177/ ADV7178 to Logic 0 or Logic 1.

The ADV7177/ADV7178 act as standard slave devices on the

bus. The data on the SDATA pin is 8 bits long, supporting the

7-bit addresses, plus the R/ bit. The ADV7178 has 36 sub-

W

addresses and the ADV7177 has 31 subaddresses to enable

access to the internal registers. It therefore interprets the first

byte as the device address and the second byte as the starting

subaddress. The auto-increment of the subaddresses allows

data to be written to or read from the starting subaddress. A

data transfer is always terminated by a stop condition. The

user can also access any unique subaddress register on a one-

by-one basis without having to update all the registers, with one

exception. The subcarrier frequency registers should be updated

in sequence, starting with Subcarrier Frequency Register 0. The

auto-increment function should then be used to increment and

access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier

frequency registers should not be accessed independently.

To control the various devices on the bus, the following

protocol must be followed. First, the master initiates a data

transfer by establishing a start condition, defined by a high-to-

low transition on SDATA while SCLOCK remains high. This

indicates that an address/data stream follows. All peripherals

1

0

1

A1

X

0

1

0

1

A1

X

ADDRESS

CONTROL

ADDRESS

CONTROL

SET UP BY

ALSB

SET UP BY

ALSB

READ/WRITE

CONTROL

READ/WRITE

CONTROL

0

1

WRITE

READ

0

1

WRITE

READ

Figure 27. ADV7177 Slave Address

Figure 28. ADV7178 Slave Address

Rev. C | Page 25 of 44

ADV7177/ADV7178

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, they cause an

immediate jump to the idle condition. During a given SCLOCK

high period, the user should issue only one start condition, one

stop condition, or a single stop condition followed by a single

start condition. If an invalid subaddress is issued by the user,

the devices do not issue an acknowledge and return to the idle

condition. If, in auto-increment mode, the user exceeds the

highest subaddress, the following actions are taken.

In write mode, the data for the invalid byte is not loaded into

any subaddress register, a no acknowledge is issued by the

ADV7177/ADV7178, and the parts return to the idle condition.

Figure 29 illustrates an example of data transfer for a read

sequence and the start and stop conditions. Figure 30 shows

bus write and read sequences.

SDATA

In read mode, the highest subaddress register contents continue

to be output until the master device issues a no acknowledge.

This indicates the end of a read. A no-acknowledge condition is

where the SDATA line is not pulled low on the ninth pulse.

SCLOCK

S

1–7

8

9

1–7

8

9

1–7

8

9

P

START ADDR R/W ACK SUBADDRESS ACK

DATA

ACK

STOP

Figure 29. Bus Data Transfer

WRITE

SEQUENCE

S

SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 0

DATA

A(S)

DATA

A(M)

A(S) P

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S) SUB ADDR A(S)

S

SLAVE ADDR A(S)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO ACKNOWLEDGE BY SLAVE

A(M) = NO ACKNOWLEDGE BY MASTER

Figure 30. Write and Read Sequences

Rev. C | Page 26 of 44

ADV7177/ADV7178

REGISTERS

REGISTER ACCESS

MODE REGISTER 0 MR0 (MR07–MR00)

Address [SR4–SR0] = 00H

The MPU can write to or read from all of the ADV7177 and

ADV7178 registers except the subaddress register, which is a

write-only register. The subaddress register determines which

register the next read or write operation accesses. All commun-

ications with the part through the bus start with an access to

the subaddress register. A read/write operation is performed

from/to the target address, which then increments to the next

address until a stop command on the bus is performed.

Figure 32 shows the various operations under the control of

Mode Register 0. This register can be read from as well as

written to.

MR0 BIT DESCRIPTION

Output Video Standard Selection (MR01–MR00)

These bits are used to set up the encode mode. The ADV7177/

ADV7178 can be set up to output NTSC, PAL (B, D, G, H, I),

and PAL (M) standard video.

REGISTER PROGRAMMING

This section describes each register, including the subaddress

register, mode registers, subcarrier frequency registers, sub-

carrier phase register, timing registers, closed captioning

extended data registers, closed captioning data registers, and

the NTSC pedestal control registers in terms of configuration.

Pedestal Control (MR02)

This bit specifies whether a pedestal is to be generated on

the NTSC composite video signal. This bit is invalid if the

ADV7177/ADV7178 is configured in PAL mode.

Luminance Filter Control (MR04–MR03)

Subaddress Register (SR7–SR0)

The luminance filters are divided into two sets (NTSC/PAL) of

four filters, low-pass A, low-pass B, notch, and extended. When

PAL is selected, Bits MR03 and MR04 select one of four PAL

luminance filters; likewise, when NTSC is selected, Bits MR03

and MR04 select one of four NTSC luminance filters. The

Typical Performance Characteristics section shows the filters.

The communications register is an 8-bit, write-only register.

After the parts have been accessed over the bus and a read/write

operation is selected, the subaddress is set up. The subaddress

register determines to/from which register the operation takes

place.

Figure 31 shows the various operations under the control of the

subaddress register. Zero should always be written to SR7–SR6.

RGB Sync (MR05)

This bit is used to set up the RGB outputs with the sync

information encoded on all RGB outputs.

Register Select (SR5–SR0)

These bits are set up to point to the required starting address.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

SR7–SR6 (00)

ZERO SHOULD BE WRITTEN

TO THESE BITS

ADV7178 SUBADDRESS REGISTER

SR5 SR4 SR3 SR2 SR1 SR0

ADV7177 SUBADDRESS REGISTER

SR5 SR4 SR3 SR2 SR1 SR0

0

•

0

1

•

0

1

0

•

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

MODE REGISTER 0

MODE REGISTER 1

0

•

0

1

•

0

1

0

•

0

1

0

1

0

•

0

1

0

1

0

1

0

1

0

1

•

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

MODE REGISTER 0

MODE REGISTER 1

SUBCARRIER FREQ REGISTER 0

SUBCARRIER FREQ REGISTER 1

SUBCARRIER FREQ REGISTER 2

SUBCARRIER FREQ REGISTER 3

SUBCARRIER PHASE REGISTER

TIMING REGISTER 0

CLOSED CAPTIONING EXTENDED DATA– BYTE 0

CLOSED CAPTIONING EXTENDED DATA– BYTE 1

CLOSED CAPTIONING DATA– BYTE 0

CLOSED CAPTIONING DATA– BYTE 1

TIMING REGISTER 1

SUBCARRIER FREQ REGISTER 0

SUBCARRIER FREQ REGISTER 1

SUBCARRIER FREQ REGISTER 2

SUBCARRIER FREQ REGISTER 3

SUBCARRIER PHASE REGISTER

TIMING REGISTER 0

CLOSED CAPTIONING EXTENDED DATA– BYTE 0

CLOSED CAPTIONING EXTENDED DATA– BYTE 1

CLOSED CAPTIONING DATA– BYTE 0

CLOSED CAPTIONING DATA– BYTE 1

TIMING REGISTER 1

MODE REGISTER 2

NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)

NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)

MODE REGISTER 3

NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)

NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)

MODE REGISTER 3

0

•

MACROVISION REGISTER

OSD REGISTER

"

•

1

0

1

MACROVISION REGISTER

0

1

0

OSD REGISTER

Figure 31. Subaddress Register

Rev. C | Page 27 of 44

ADV7177/ADV7178

MR07

MR06

MR05

MR04

MR03

MR02

MR01

MR00

OUTPUT SELECT

MR06

LUMINANCE FILTER CONTROL

MR04 MR03

OUTPUT VIDEO

STANDARD SELECTION

MR01

MR00

0

1

YC OUTPUT

RGB/YUV OUTPUT

0

1

0

1

0

1

LOW-PASS FILTER (A)

NOTCH FILTER

EXTENDED MODE

LOW-PASS FILTER (B)

NTSC

PAL (B, D, G, H, I)

PAL (M)

0

1

0

1

0

1

RESERVED

MR07

RGB SYNC

PEDESTAL CONTROL

MR02

ZERO SHOULD

BE WRITTEN TO

THIS BIT

MR05

0

1

PEDESTAL OFF

PEDESTAL ON

0

1

DISABLE

ENABLE

Figure 32. Mode Register 0 (MR0)

MR17

MR16

MR15

MR14

MR13

MR12

MR11

MR10

MR16

LUMA

DAC CONTROL

CLOSED CAPTIONING

FIELD SELECTION

ONE SHOULD

BE WRITTEN TO

THIS BIT

MR14

MR12 MR11

0

1

NORMAL

POWER-DOWN

0

1

0

1

0

1

NO DATA OUT

ODD FIELD ONLY

EVEN FIELD ONLY

DATA OUT

(BOTH FIELDS)

COLOR BAR

CONTROL

COMPOSITE

DAC CONTROL

CHROMA

DAC CONTROL

INTERLACED MODE

CONTROL

MR17

MR15

MR13

MR10

0

1

DISABLE

ENABLE

NORMAL

POWER-DOWN

NORMAL

POWER-DOWN

INTERLACED

NONINTERLACED

0

1

0

1

0

1

Figure 33. Mode Register 1 (MR1)

Output Select (MR06)

Color Bar Control (MR17)

This bit specifies if the part is in composite video or RGB/YUV

mode. Note that the main composite signal is still available in

RGB/YUV mode.

This bit can be used to generate and output an internal color-

bar test pattern. The color-bar configuration is 100/7.5/75/7.5

for NTSC and 100/0/75/0 for PAL. Note that when color bars

are enabled, the ADV7177/ADV7178 are configured in a master

timing mode as per the one selected by bits TR01 and TR02.

MODE REGISTER 1 MR1 (MR17–MR10)

Address (SR4–SR0) = 01H

SUBCARRIER FREQUENCY REGISTER 3–0

FSC3–FSC0

Address [SR4–SR0] = 05H–02H

Figure 33 shows the various operations under the control of

Mode Register 1. This register can be read from as well as

written to.

These 8-bit-wide registers are used to set up the subcarrier

frequency. The value of these registers is calculated by using the

following equation, in which the asterisk (*) means rounded to

the nearest integer:

MR1 BIT DESCRIPTION

Interlaced Mode Control (MR10)

This bit is used to set up the output to interlaced or noninter-

laced mode. This mode is relevant only when the part is in

composite video mode.

No.of Subcarrier FrequencyValues in OneLineof VideoLine

× 2³²

*

No.of 27MHzClock CyclesinOne VideoLine

For example, in NTSC mode

Closed Captioning Field Selection (MR12–MR11)

These bits control the fields on which closed captioning data is

displayed; closed captioning information can be displayed on an

odd field, even field, or both fields.

227.5

1716

Subcarrier Frequency Value =

× 2³²= 569408542 d = 21F07C1Fh

DAC Control (MR15–MR13)

Note that on power-up, FSC Register 0 is set to 16h. A value of

1F as derived above is recommended.

These bits can be used to power down the DACs to reduce the

power consumption of the ADV7177/ADV7178 if any of the

DACs are not required in the application.

Rev. C | Page 28 of 44

ADV7177/ADV7178

Program as

Input Control (TR03)

FSC Register 0: 1Fh

FSC Register 2: 7Ch

FSC Register 3: F0h

FSC Register 4: 21h

This bit controls whether the

part is in slave mode.

input is used when the

BLANK

Luma Delay (TR05–TR04)

These bits control the addition of a luminance delay. Each bit

represents a delay of 74 ns.

Figure 34 shows how the frequency is set up by the four

registers.

Pixel Port Control (TR06)

SUBCARRIER

FREQUENCY

REG 3

FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24

This bit is used to set the pixel port to accept 8-bit or 16-bit

data. If an 8-bit input is selected, the data is set up on

Pins P7–P0.

SUBCARRIER

FREQUENCY

REG 2

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

SUBCARRIER

FREQUENCY

REG 1

Timing Register Reset (TR07)

FSC14

FSC6

FSC15

FSC7

FSC13 FSC12 FSC11 FSC10 FSC9

FSC8

FSC0

Toggling TR07 from low to high and low again resets the

internal timing counters. This bit should be toggled after

power-up, reset, or after changing to a new timing mode.

SUBCARRIER

FREQUENCY

REG 0

FSC5

FSC4

FSC3 FSC2 FSC1

Figure 34. Subcarrier Frequency Register

CLOSED CAPTIONING EVEN FIELD

DATA REGISTER 1–0 (CED15–CED0)

SUBCARRIER PHASE REGISTER (FP7–FP0)

Address [SR4–SR0] = 06H

Address [SR4–SR0] = 09H–08H

This 8-bit-wide register is used to set up the subcarrier phase.

Each bit represents 1.41 degrees.

These 8-bit-wide registers are used to set up the closed

captioning extended data bytes on even fields. Figure 35

shows how the high and low bytes are set up in the registers.

TIMING REGISTER 0 (TR07–TR00)

Address [SR4–SR0] = 07H

BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8

BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0

Figure 35. Closed Captioning Extended Data Register

Figure 37 shows the various operations under the control of

Timing Register 0. This register can be read from as well as

written to. This register can be used to adjust the width and

position of the master mode timing signals.

CLOSED CAPTIONING ODD FIELD

DATA REGISTER 1–0 (CCD15–CCD0)

TR0 BIT DESCRIPTION

Master/Slave Control (TR00)

Subaddress [SR4–SR0] = 0BH–0AH

This bit controls whether the ADV7177/ADV7178 are in master

or slave mode. This register can be used to adjust the width and

position of the master timing signals.

These 8-bit-wide registers are used to set up the closed

captioning data bytes on odd fields. Figure 36 shows how

the high and low bytes are set up in the registers.

Timing Mode Selection (TR02–TR01)

These bits control the timing mode of the ADV7177/ADV7178.

These modes are described in the Timing and Control section.

BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8

BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0

Figure 36. Closed Captioning Data Register

TR07

TR06

TR05

TR04

TR03

TR02

TR01

TR00

TIMING

REGISTER RESET

BLANK INPUT

CONTROL

MASTER/SLAVE

CONTROL

TR03

TR00

TR07

0

1

ENABLE

DISABLE

0

1

SLAVE TIMING

MASTER TIMING

LUMA DELAY

TIMING MODE

SELECTION

PIXEL PORT

CONTROL

TR05 TR04

TR02TR01

TR06

0

1

0

1

0

1

0ns DELAY

74ns DELAY

148ns DELAY

222ns DELAY

0

1

0

1

0

1

MODE 0

MODE 1

MODE 2

MODE 3

0

1

8-BIT

16-BIT

Figure 37. Timing Register 0

Rev. C | Page 29 of 44

ADV7177/ADV7178

Width (TR15–TR14)

VSYNC

When the ADV7177/ADV7178 are in Timing Mode 2, these

bits adjust the pulse width.

TIMING REGISTER 1 (TR17–TR10)

Address [SR4–SR0] = 0CH

VSYNC

to Pixel Data Adjust (TR17–TR16)

Timing Register 1 is an 8-bit-wide register. Figure 38 shows the

various operations under the control of Timing Register 1. This

register can be read from as well as written to. This register can

be used to adjust the width and position of the master mode

timing signals.

HSYNC

This enables the

to be adjusted with respect to the pixel

HSYNC

data and allows the Cr and Cb components to be swapped. This

adjustment is available in both master and slave timing modes.

TR1 BIT DESCRIPTION

MODE REGISTER 2 MR2 (MR27–MR20)

Address [SR4-SR0] = 0DH

Width (TR11–TR10)

HSYNC

These bits adjust the

pulse width.

HSYNC

Mode Register 2 is an 8-bit-wide register. Figure 39 shows the

various operations under the control of Mode Register 2. This

register can be read from as well as written to.

to FIELD/

VSYNC

Delay (TR13–TR12)

HSYNC

These bits adjust the position of the

output relative to

HSYNC

the FIELD/

output.

VSYNC

to FIELD Rising Edge Delay (TR15–TR14)

HSYNC

When the device is in Timing Mode 1, these bits adjust the

position of the

output relative to the FIELD output

HSYNC

rising edge.

TR17

TR16

TR15

TR14

TR13

TR12

TR11

TR10

HSYNC TO PIXEL

DATA ADJUST

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

HSYNC TO

FIELD/VSYNC DELAY

HSYNC WIDTH

T

TR11 TR10

A

TR17 TR16

TR13 TR12

T

B

1 × T

4 × T

0

1

0

1

0

1

PCLK

TR15 TR14

T

C

0

1

0

1

0

1

0 3 T

1 3 T

2 3 T

3 3 T

0

1

0

1

0

1

0 × T

4 × T

8 × T

PCLK

X

x

0

1

T

16 × T

B

PCLK

128 × T

+ 32µs

PCLK

16 × T

PCLK

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

0

1

0

1

0

1

1 × T

4 × T

PCLK

16 × T

PCLK

128 × T

PCLK

TIMING MODE 1 (MASTER/PAL)

LINE 1

LINE 313

LINE 314

HSYNC

T

A

T

C

B

FIELD/VSYNC

Figure 38. Timing Register 1

MR27

MR26

MR25

MR24

MR23

MR22

MR21

MR20

RGB/YUV

CONTROL

CHROMINANCE

CONTROL

MR22–MR21

(00)

MR26

MR24

ZERO SHOULD

BE WRITTEN TO

THESE BITS

0

1

RGB OUTPUT

YUV OUTPUT

0

1

ENABLE COLOR

DISABLE COLOR

LOW POWER

MODE

BURST

CONTROL

ACTIVE VIDEO

LINE DURATION

SQUARE PIXEL

CONTROL

MR27

MR25

MR23

MR20

0

1

DISABLE

ENABLE

0

1

ENABLE BURST

DISABLE BURST

0

1

720 PIXELS

710 PIXELS/702 PIXELS

0

1

DISABLE

ENABLE

Figure 39. Mode Register 2

Rev. C | Page 3ꢀ of 44

ADV7177/ADV7178

MR2 BIT DESCRIPTION

NTSC PEDESTAL REGISTERS 3–0

PCE15–0, PCO15–0

(Subaddress [SR4–SR0] = 11–0EH)

Square Pixel Control (MR20)

This bit is used to set up square pixel mode. This is available in

slave mode only. For NTSC, a 24.5454 MHz clock must be

supplied. For PAL, a 29.5 MHz clock must be supplied.

These 8-bit-wide registers set up the NTSC pedestal on a line-

by-line basis in the vertical blanking interval for both odd and

even fields. Figure 40 show the four control registers. A Logic 1

in any of the bits of these registers has the effect of turning the

pedestal off on the equivalent line when used in NTSC.

Active Video Line Duration (MR23)

This bit switches between two active video line durations. A 0

selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a 1 selects

ITU-R.BT470 “analog” standard for active video duration

(710 pixels NTSC, 702 pixels PAL).

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

Chrominance Control (MR24)

FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8

This bit enables the color information to be switched on and off

the video output.

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0

Burst Control (MR25)

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

This bit enables the burst information to be switched on and off

the video output.

FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8

Figure 40. Pedestal Control Registers

RGB/YUV Control (MR26)

This bit enables the output from the RGB DACs to be set to

YUV output video standard. Bit MR06 of Mode Register 0 must

be set to Logic 1 before MR26 is set.

MODE REGISTER 3 MR3 (MR37–MR30)

Address [SR4–SR0] = 12H

Mode Register 3 is an 8-bit-wide register. Figure 41shows the

various operations under the control of Mode Register 3.

Table 12. DAC Output Configuration Matrix

MR06

MR26

DAC A

CVBS

B

DAC B

DAC C

MR3 BIT DESCRIPTION

Revision Code (MR30)

ꢀ

±

ꢀ

±

ꢀ

±

Y

G

Y

C

R

V

This bit is read only and indicates the revision of the device.

U

VBI_Pass-Through (MR31)

This bit determines whether or not data in the vertical blanking

interval (VBI) is output to the analog outputs or blanked. VBI

In Table 12,

data insertion is not available in Slave Mode 0. Also, if

BLANK

CVBS: Composite video baseband signal

input control (TR03) is enabled, and VBI_Pass-Through is

enabled, TR03 has priority, that is, VBI data insertion does

not work.

Y:

Luminance component signal, YUV or Y/C mode

Chrominance signal, for Y/C mode

C:

U:

V:

R:

G:

B:

Clock Output (MR33–MR32)

Chrominance component signal, for YUV mode

Red component video, for RGB mode

These bits control the synchronous clock output signal. The

clock can be 27 MHz, 13.5 MHz, or disabled, depending on the

values of these bit.

OSD Enable (MR35)

A Logic 1 in MR35 enables the OSD function on the ADV7177.

Input Default Color (MR36)

Green component video, for RGB mode

Blue component video, for RGB mode

This bit determines the default output color from the DACs for

zero input data (or disconnected). A Logic 0 means that the

color corresponding to 00000000 is displayed. A Logic 1 forces

the output color to black for 00000000 input video data.

Low Power Control (MR27)

This bit enables the lower power mode of the ADV7177 and the

ADV7178. This reduces DAC current by 50ꢀ.

Reserved (MR37)

Zero should be written to this bit.

Rev. C | Page 3± of 44

ADV7177/ADV7178

OSD REGISTER 0–11

Address [SR4–SR0] = 13H–1EH

There are 12 OSD registers as shown in Figure 42. There are

four bits for each Y, Cb, and Cr value, and there are four zeros

added to give the complete byte for each value loaded internally.

(Y0 = [Y0₃, Y0₂, Y0₁, Y0₀, 0, 0, 0, 0], Cb = [Cb₃, Cb₂, Cb₁, Cb0, 0,

0, 0, 0,], Cr = [Cr₃, Cr₂, Cr₁, Cr₀, 0, 0, 0, 0].)

MR36

MR35

MR34

MR33

MR32

MR31

MR30

MR37

CLOCK OUTPUT

MR33-32

OSD ENABLE

MR35

MR37

0

1

0

1

0

1

CLOCK OUTPUT OFF

13.5MHz OUTPUT

27MHz OUTPUT

REV CODE

(READ ONLY)

ZERO SHOULD

BE WRITTEN TO

THIS BIT

0

1

DISABLE

ENABLE

CLOCK OUTPUT OFF

INPUT DEFAULT COLOR

MR36

MR34

VBI PASSTHROUGH

MR31

ZERO SHOULD

BE WRITTEN TO

THIS BIT

0

1

INPUT COLOR

BLACK

0

1

DISABLE

ENABLE

Figure 41. Mode Register 3

Y0

Cr0

Y1

Cb0

Cr1

Cb1

Cr7

Cb7

Figure 42. OSD Registers

Rev. C | Page 32 of 44

ADV7177/ADV7178

BOARD DESIGN AND LAYOUT CONSIDERATIONS

The ADV7177/ADV7178 are highly integrated circuits

containing both precision analog circuitry and high speed

digital circuitry. The parts have been designed to minimize

interference effects on the integrity of the analog circuitry by

the high speed digital circuitry. It is imperative that the same

design and layout techniques be applied to the system-level

design so that high speed and accurate performance is achieved.

Figure 43 shows the analog interface between the device and

monitor. The layout should be optimized for lowest noise on the

ADV7177/ADV7178 power and ground lines by shielding the

digital inputs and providing good decoupling. The lead length

between groups of V_AAand GND pins should by minimized to

minimize inductive ringing.

SUPPLY DECOUPLING

For optimum performance, bypass capacitors should be

installed using the shortest leads possible, consistent with

reliable operation, to reduce the lead inductance. Best

performance is obtained with 0.1 µF ceramic capacitor

decoupling. Each group of V_AApins on the ADV7177/ADV7178

must have at least one 0.1 µF decoupling capacitor to GND.

These capacitors should be placed as close to the device as

possible. Note that while the ADV7177/ADV7178 contains

circuitry to reject power-supply noise, this rejection decreases

with frequency. If a high frequency switching power supply is

used, the designer should pay close attention to reducing power

supply noise and consider using a 3-terminal voltage regulator

for supplying power to the analog power plane.

GROUND PLANES

The ground plane should encompass all ADV7177/ADV7178

ground pins, voltage reference circuitry, power supply bypass

circuitry for the ADV7177/ADV7178, the analog output traces,

and all digital signal traces leading up to the ADV7177/

ADV7178. The ground plane is the board’s common ground

plane.

DIGITAL SIGNAL INTERCONNECT

The digital inputs to the ADV7177/ADV7178 should be

isolated as much as possible from the analog outputs and other

analog circuitry. Also, these input signals should not overlay the

analog power plane.

Due to the high clock rates involved, long clock lines to the

ADV7177/ADV7178 should be avoided to reduce noise pickup.

Any active termination resistors for the digital inputs should be

connected to the regular PCB power plane (V_CC) and not to the

analog power plane.

POWER PLANES

The ADV7177/ADV7178 and any associated analog circuitry

should have their own power plane, referred to as the analog

power plane (V_AA). This power plane should be connected to

the regular PCB power plane (V_CC) at a single point through a

ferrite bead. This bead should be located within three inches of

the ADV7177/ADV7178.

ANALOG SIGNAL INTERCONNECT

The ADV7177/ADV7178 should be located as close to the

output connectors as possible to minimize noise pickup and

reflections due to impedance mismatch.

The metallization gap separating the device power plane and

board power plane should be as narrow as possible to minimize

the obstruction to the flow of heat from the device into the

general board.

The video output signals should overlay the ground plane, not

the analog power plane, to maximize the high frequency power-

supply rejection. Digital inputs, especially pixel data inputs and

clocking signals, should never overlay any of the analog signal

circuitry and should be kept as far away as possible.

The PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7177/ADV7178 power pins and voltage

reference circuitry.

For best performance, the outputs should each have a 75 Ω load

resistor connected to GND. These resistors should be placed as

close as possible to the ADV7177/ADV7178 to minimize

reflections.

Plane-to-plane noise coupling can be reduced by ensuring that

portions of the regular PCB power and ground planes do not

overlay portions of the analog power plane, unless they can be

arranged so that the plane-to-plane noise is common mode.

The ADV7177/ADV7178 should have no floating inputs. Any

inputs that are not required should be tied to ground.

Rev. C | Page 33 of 44

ADV7177/ADV7178

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

0.1µF

0.01µF

5V (V

L1

5V (V

)

5V (V )

AA

(FERRITE BEAD)

)

5V (V

)

AA

5V

(V

GND

0.1µF

)

10µF

33µF

CC

1, 20, 28, 30

32

25

V

COMP

V

REF

AA

11

34

35

36

27

26

31

OSD_EN

OSD_0

OSD_1

OSD_2

LUMA

75Ω

OSD

INPUTS

ADV7177/

ADV7178

CHROMA

37–41,

3–10, 12–14

PIXEL DATA

P15–P0

5V (V

)

CVBS

AA

15

16

17

22

44

43

2

HSYNC

UNUSED

INPUTS

SHOULD BE

GROUNDED

4kΩ

FIELD/VSYNC

BLANK

RESET

100nF

5V (V

)

5V (V

)

CC

RESET

5kΩ

CLOCK

100Ω

27MHz

XTAL

33pF

23

24

SCLOCK

SDATA

CLOCK

MPU BUS

CLOCK/2

33pF

27MHz OR 13.5MHz

CLOCK OUTPUT

R

SET

ALSB

18

GND

100Ω

19, 21

29, 42

5V (V

)

AA

10kΩ

Figure 43. Recommended Analog Circuit Layout

Rev. C | Page 34 of 44

ADV7177/ADV7178

CLOSED CAPTIONING

The ADV7177/ADV7178 support closed captioning, which

conforms to the standard television synchronizing waveform

for color transmission. Closed captioning is transmitted during

the blanked active line time of Line 21 of the odd fields and

Line 284 of even fields.

FCC Code of Federal Regulations (CFR) 47 Section 15.119 and

EIA608 describe the closed captioning information for Line 21

and Line 284.

The ADV7177/ADV7178 uses a single buffering method.

This means that the closed captioning buffer is only 1 byte

deep, therefore there is no frame delay in outputting the closed

captioning data unlike other 2-byte-deep buffering systems.

The data must be loaded at least one line before (Line 20 or

Line 283) it is outputted on Line 21 and Line 284. A typical

Closed captioning consists of a 7-cycle sinusoidal burst that is

frequency and phase locked to the caption data. After the clock

run-in signal, the blanking level is held for 2 data bits and is

followed by a Logic 1 start bit. The start bit is followed by16 bits

of data. These consist of two, 8-bit bytes, seven data bits and one

odd parity bit. The data for these bytes is stored in closed

captioning Data Registers 0 and 1.

implementation of this method is to use

to interrupt

VSYNC

a microprocessor, which in turn loads the new data (2 bytes)

every field. If no new data is required for transmission, zeros

must be inserted in both data registers; this is called nulling.

The ADV7177/ADV7178 also supports the extended closed

captioning operation, which is active during even fields, and is

encoded on Scan Line 284. The data for this operation is stored

in closed captioning extended Data Registers 0 and 1. All clock

run-in signals and timing to support closed captioning on

Line 21 and Line 284 are generated automatically by the

ADV7177/ ADV7178. All pixels inputs are ignored during

Line 21 and Line 284.

It is also important to load control codes, all of which are

double bytes on Line 21, or a TV does not recognize them. If

you have a message such as “Hello World,” which has an odd

number of characters, it is important to pad it out to an even

number to include the end-of-caption, 2-byte control code in

the same field.

10.5 ± 0.25µs

12.91µs

D0–D6

50 IRE

40 IRE

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003µs

27.382µs

33.764µs

Figure 44. Closed Captioning Waveform (NTSC)

Rev. C | Page 35 of 44

ADV7177/ADV7178

WAVEFORM ILLUSTRATIONS

NTSC WAVEFORMS WITH PEDESTAL

PEAK COMPOSITE

REF WHITE

1268.1mV

1048.4mV

130.8 IRE

100 IRE

714.2mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

387.6mV

334.2mV

SYNC LEVEL

48.3mV

–40 IRE

Figure 45. NTSC Composite Video Levels

100 IRE

REF WHITE

1048.4mV

714.2mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

387.6mV

334.2mV

–40 IRE

SYNC LEVEL

48.3mV

Figure 46. NTSC Luma Video Levels

963.8mV

PEAK CHROMA

629.7mVp-p

286mVp-p

650mV

BLANK/BLACK LEVEL

PEAK CHROMA

335.2mV

0mV

Figure 47. NTSC Chroma Video Levels

100 IRE

REF WHITE

1052.2mV

720.8mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

387.5mV

331.4mV

–40 IRE

SYNC LEVEL

45.9mV

Figure 48. NTSC RGB Video Levels

Rev. C | Page 36 of 44

ADV7177/ADV7178

NTSC WAVEFORMS WITHOUT PEDESTAL

130.8 IRE

100 IRE

PEAK COMPOSITE

REF WHITE

1289.8mV

1052.2mV

714.2mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

338mV

52.1mV

–40 IRE

Figure 49. NTSC Composite Video Levels

100 IRE

REF WHITE

1052.2mV

714.2mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

338mV

52.1mV

–40 IRE

Figure 50. NTSC Luma Video Levels

PEAK CHROMA

694.9mVp-p

286mVp-p

BLANK/BLACK LEVEL

PEAK CHROMA

0mV

Figure 51. NTSC Chroma Video Levels

100 IRE

REF WHITE

1052.2mV

715.7mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

336.5mV

51mV

–40 IRE

Figure 52. NTSC RGB Video Levels

Rev. C | Page 37 of 44

ADV7177/ADV7178

PAL WAVEFORMS

PEAK COMPOSITE

REF WHITE

1284.2mV

1047.1mV

696.4mV

350.7mV

50.8mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 53. PAL Composite Video Levels

REF WHITE

1047mV

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

350.7mV

50.8mV

Figure 54. PAL Luma Video Levels

989.7mV

650mV

PEAK CHROMA

672mVp-p

300mVp-p

BLANK/BLACK LEVEL

PEAK CHROMA

317.7mV

0mV

Figure 55. PAL Chroma Video Levels

REF WHITE

1050.2mV

698.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

351.8mV

51mV

Figure 56. PAL RGB Video Levels

Rev. C | Page 38 of 44

ADV7177/ADV7178

UV WAVEFORMS

505mV

423mV

334mV

BETACAM LEVEL

0mV

82mV

171mV

0mV

BETACAM LEVEL

0mV

–82mV

0mV

–171mV

–423mV

–505mV

–334mV

–505mV

Figure 57. NTSC 100% Color Bars Without Pedestal, U Levels

Figure 60. NTSC 100% Color Bars Without Pedestal, V Levels

467mV

391mV

309mV

BETACAM LEVEL

76mV

158mV

0mV

BETACAM LEVEL

0mV

–76mV

0mV

–158mV

–391mV

–467mV

–309mV

–467mV

Figure 58. NTSC 100% Color Bars With Pedestal, U Levels

Figure 61. NTSC 100% Color Bars With Pedestal, V Levels

350mV

293mV

232mV

SMPTE LEVEL

57mV

118mV

0mV

SMPTE LEVEL

–57mV

0mV

–118mV

–293mV

–350mV

–232mV

–350mV

Figure 59. PAL 1005 Color Bars, U Levels

Figure 62. PAL 100% Color Bars, V Levels

Rev. C | Page 39 of 44

ADV7177/ADV7178

REGISTER VALUES

The ADV7177/ADV7178 registers can be set depending on the

user standard required.

PAL B, D, G, H, I (FSC = 4.43361875 MHZ)

Address Data

Table 14.

The following examples give the various register formats for

several video standards. In each case the output is set to com-

posite output with all DACs powered up and with the

Address

Value

(Hex)

ꢀꢀ

ꢀ±

ꢀ2

ꢀ3

ꢀ4

ꢀ5

ꢀ6

ꢀ7

ꢀ8

ꢀ9

ꢀA

ꢀB

ꢀC

ꢀD

ꢀE

Register Name

BLANK

Mode Register ꢀ

Mode Register ±

ꢀ±

ꢀꢀ

CB

8A

ꢀ9

2A

ꢀ

ꢀ8

ꢀꢀ

8ꢀ

ꢀꢀ

input control disabled. Also, the burst and color information are

enabled on the output and the internal color bar generator is

switched off. In the examples shown, the timing mode is set to

Mode 0 in slave format. TR02–TR00 of the Timing Register 0

control the timing modes. For a detailed explanation of each bit

in the command registers, see the Register Programming

section. TR07 should be toggled after setting up a new timing

mode. Timing Register 1 provides added control over the

position and duration of the timing signals. In the examples,

this register is programmed in default mode.

Subcarrier Frequency Register ꢀ

Subcarrier Frequency Register ±

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register ꢀ

Timing Register ꢀ

Closed Captioning Ext. Register ꢀ

Closed Captioning Ext. Register ±

Closed Captioning Register ꢀ

Closed Captioning Register ±

Timing Register ±

NTSC (FSC = 3.5795454 MHZ)

Address Data

Table 13.

Mode Register 2

Pedestal Control Register ꢀ

Pedestal Control Register ±

Pedestal Control Register 2

Pedestal Control Register 3

Mode Register 3

Address

(Hex)

Value

(Hex)

ꢀF

Register Name

±ꢀ

±±

±2

ꢀꢀ

ꢀ±

ꢀ2

ꢀ3

ꢀ4

ꢀ5

ꢀ6

ꢀ7

ꢀ8

ꢀ9

ꢀA

ꢀB

ꢀC

ꢀD

ꢀE

ꢀF

±ꢀ

±±

±2

Mode Register ꢀ

Mode Register ±

ꢀ4

ꢀꢀ

±F^±

7C

Fꢀ

2±

ꢀꢀ

ꢀ8

ꢀꢀ

8ꢀ

ꢀꢀ

Subcarrier Frequency Register ꢀ

Subcarrier Frequency Register ±

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Timing Register ꢀ

Closed Captioning Register ꢀ

Closed Captioning Ext. Register ±

Closed Captioning Register ꢀ

Closed Captioning Register ±

Timing Register ±

PAL M (FSC = 3.57561149 MHZ)

Address Data

Table 15.

Address

Value

(Hex)

ꢀꢀ

ꢀ±

ꢀ2

ꢀ3

ꢀ4

ꢀ5

ꢀ6

ꢀ7

ꢀ8

ꢀ9

ꢀA

ꢀB

ꢀC

ꢀD

ꢀE

Register Name

Mode Register ꢀ

Mode Register ±

ꢀ6

ꢀꢀ

A3

EF

E6

2±

ꢀ

ꢀ8

ꢀꢀ

8ꢀ

ꢀꢀ

Subcarrier Frequency Register ꢀ

Subcarrier Frequency Register ±

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register ꢀ

Timing Register ꢀ

Closed Captioning Ext. Register ꢀ

Closed Captioning Ext. Register ±

Closed Captioning Register ꢀ

Closed Captioning Register ±

Timing Register ±

Mode Register 2

Pedestal Control Register ꢀ

Pedestal Control Register ±

Pedestal Control Register 2

Pedestal Control Register 3

Mode Register 3

^±Fscꢀ = ±6h on default/power-up. This should be set to ±Fh.

Mode Register 2

Pedestal Control Register ꢀ

Pedestal Control Register ±

Pedestal Control Register 2

Pedestal Control Register 3

Mode Register 3

ꢀF

±ꢀ

±±

±2

Rev. C | Page 4ꢀ of 44

ADV7177/ADV7178

OPTIONAL OUTPUT FILTER

0

–16.7

–33.3

–50.0

–66.7

–83.3

–100

If an output filter is required for the CVBS, Y, UV, Chroma, and

RGB outputs of the ADV7177/ADV7178, the filter in Figure 63

can be used. Plots of the filter characteristics are shown in

Figure 64. An output filter is not required if the outputs of the

ADV7177/ADV7178 are connected to an analog monitor or an

analog TV; however, if the output signals are applied to a system

where sampling is used (for example, digital TV), a filter is

required to prevent aliasing.

L

1µH

2.7µH

0.68µH

IN

OUT

C

56pF

R

75Ω

R

470pF

330pF

75Ω

100k

1M

10M

FREQUENCY (Hz)

100M

Figure 63. Output Filter

Figure 64. Output Filter Plot

Rev. C | Page 4± of 44

ADV7177/ADV7178

OPTIONAL DAC BUFFERING

V

AA

For external buffering of the ADV7177/ADV7178 DAC

outputs, the configuration in Figure 65 is recommended. This

configuration shows the DAC outputs running at half (18 mA)

their full-current (34.7 mA) capability. This allows the devices

to dissipate less power; the analog current is reduced by 50ꢀ

with a RSET of 300 Ω and a RLOAD of 75 Ω. This mode is

recommended for 3.3 V operation as optimum performance is

obtained from the DAC outputs at 18 mA with a V_AAof 3.3 V.

This buffer also adds extra isolation on the video outputs, as the

buffer circuit in Figure 66 shows. When calculating absolute

output full current and voltage, use the following equation:

ADV7177/ADV7178

OUTPUT

BUFFER

V

REF

DAC A

DAC B

DAC C

75Ω

OUTPUT

BUFFER

PIXEL

PORT

DIGITAL

CORE

OUTPUT

BUFFER

R

SET

300Ω

V

_OUT= I_OUT× R_LOAD

Figure 65. Output DAC Buffering Configuration

(

V_REF× K

R_SET

)

I_OUT

=

V

+

CC

where K = 4.2146 constant, V_REF= 1.235 V

5

4

3

OUTPUT TO

TV MONITOR

1

AD8051

INPUT/

OPTIONAL

FILTER O/P

2

V

–

CC

Figure 66. Recommended Output DAC Buffer

Rev. C | Page 42 of 44

ADV7177/ADV7178

OUTLINE DIMENSIONS

1.03

0.88

0.73

2.45

MAX

13.90

BSC SQ

33

23

34

22

SEATING

PLANE

10.00

BSC SQ

TOP VIEW

(PINS DOWN)

10°

6°

2°

2.10

2.00

1.95

0.23

0.11

VIEW A

PIN 1

44

12

7°

0°

1

11

0.25 MIN

0.10

COPLANARITY

0.45

0.30

0.80 BSC

LEAD PITCH

VIEW A

LEAD WIDTH

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MO-112-AA-1

Figure 67. Metric Quad Flat Package [MQFP]

(S-44-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADV7±77KS

ADV7±77KS-REEL

ADV7±77KSZ^±

ADV7±77KSZ-REEL^±

ADV7±78KS

Temperature Range

ꢀ°C to 7ꢀ°C

Package Description

Package Option

S-44-2

44-Lead Metric Quad Flat Package (MQFP)

ꢀ°C to 7ꢀ°C

S-44-2

ADV7±78KS-REEL

^±Z = Pb-free part.

Rev. C | Page 43 of 44

ADV7177/ADV7178

NOTES

registered trademarks are the property of their respective owners.

C00228–0-3/05(C)

Rev. C | Page 44 of 44


型号：	ADV7178_15
厂家：	ADI
描述：	Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
文件：	总44页 (文件大小：697K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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