ADV7180BSTZ [ADI]
10-Bit, 4 x Oversampling SDTV Video Decoder; 10位， 4倍过采样SDTV视频解码器
| 型号： | ADV7180BSTZ |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| 文件： | 总112页 (文件大小：2178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 4× Oversampling
SDTV Video Decoder
ADV7180
FEATURES
APPLICATIONS
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling
for Y/C mode, and 2× oversampling for YPrPb (per channel)
Three video input channels with on-chip antialiasing filter
CVBS (composite), Y/C (S-video), and YPrPb (component)
video input support
5-line adaptive comb filters and CTI/DNR video
enhancement
Adaptive Digital Line Length Tracking (ADLLT™),
signal processing, and enhanced FIFO management give
mini-TBC functionality
Digital camcorders and PDAs
Low-cost SDTV PIP decoder for digital TVs
Multichannel DVRs for video security
AV receivers and video transcoding
PCI-/USB-based video capture and TV tuner cards
Personal media players and recorders
Smartphone/multimedia handsets
In-car/automotive infotainment units
Rearview camera/vehicle safety systems
FUNCTIONAL BLOCK DIAGRAM
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
NTSC/PAL/SECAM autodetection
CLOCK PROCESSING BLOCK
XTAL1
LLC
PLL
ADLLT PROCESSING
XTAL
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, FIELD1
1.0 V analog input signal range
1
ANALOG
VIDEO
8-BIT/16 -BIT
PIXEL DATA
DIGITAL
PROCESSING
BLOCK
10-BIT, 86MHz
ADC
INPUTS
P7 TO P0
A
A
A
1
2
IN
IN
IN
AA
Four general-purpose outputs (GPO)2
FILTER
2D COMB
VS
HS
3
1
AA
FILTER
Full feature VBI data slicer with teletext support (WST)
Power-down mode and ultralow sleep mode current
2-wire serial MPU interface (I2C® compatible)
1.8 V analog, 1.8 V PLL, 1.8 V digital, 3.3 V I/O supply
−40°C to +85°C temperature grade
SHA
A/D
VBI SLICER
A
4
5
6
IN
IN
IN
2
FIELD
1
1
A
A
AA
FILTER
1
COLOR
DEMOD
GPO
SFL
INTRQ
2
REFERENCE
I C/CONTROL
ADV7180
Two package types:
SCLK SDATA ALSB RESET PWRDWN
40-lead, 6 mm × 6 mm, Pb-free LFCSP
64-lead, 10 mm × 10 mm, Pb-free LQFP
1
2
ONLY AVAILABLE ON 64-LEAD PACKAGE.
40-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.
Figure 1.
GENERAL DESCRIPTION
AGC and clamp-restore circuitry allow an input video signal
peak-to-peak range up to 1.0 V. Alternatively, these can be
bypassed for manual settings.
The ADV7180 automatically detects and converts standard
analog baseband television signals compatible with worldwide
NTSC, PAL, and SECAM standards into 4:2:2 component video
data compatible with the 8-bit ITU-R BT.656 interface standard.
The line-locked clock output allows the output data rate, timing
signals, and output clock signals to be synchronous,
asynchronous, or line locked even with 5% line length
variation. Output control signals allow glueless interface
connections in many applications. The ADV7180 is programmed
via a 2-wire, serial, bidirectional port (I2C compatible).
The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devices, Inc., digital video encoders, such as the
ADV7179. External HS, VS, and FIELD signals provide timing
references for LCD controllers and other video ASICs, if
required
The ADV7180 is fabricated in a 1.8 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. A chip-scale, 40-lead, Pb-free
LFCSP package option makes the decoder ideal for space-
constrained portable applications. A 64-lead LQFP package is
also available (pin compatible with ADV7181B).
The accurate 10-bit analog-to-digital conversion provides
professional quality video performance for consumer applications
with true 8-bit data resolution. Three analog video input channels
accept standard composite, S-video, or component video
signals, supporting a wide range of consumer video sources.
1 The ADV7180 LFCSP-40 uses one pin to output VS or FIELD.
2 ADV7180 LQFP-64 only.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADV7180
TABLE OF CONTENTS
Features .............................................................................................. 1
SD Chroma Path......................................................................... 22
Sync Processing .......................................................................... 23
VBI Data Recovery..................................................................... 23
General Setup.............................................................................. 23
Color Controls............................................................................ 25
Clamp Operation........................................................................ 27
Luma Filter .................................................................................. 28
Chroma Filter.............................................................................. 31
Gain Operation........................................................................... 32
Chroma Transient Improvement (CTI) .................................. 36
Digital Noise Reduction (DNR) and Luma Peaking Filter... 37
Comb Filters................................................................................ 38
IF Filter Compensation ............................................................. 40
AV Code Insertion and Controls ............................................. 41
Synchronization Output Signals............................................... 43
Sync Processing .......................................................................... 50
VBI Data Decode ....................................................................... 50
I2C Readback Registers.............................................................. 59
Pixel Port Configuration ............................................................... 72
GPO Control................................................................................... 73
MPU Port Description................................................................... 74
Register Access............................................................................ 75
Register Programming............................................................... 75
I2C Sequencer.............................................................................. 75
I2C Register Maps ........................................................................... 76
I2C Programming Examples........................................................ 106
ADV7180 LQFP-64.................................................................. 106
ADV7180 LFCSP-40................................................................ 107
PCB Layout Recommendations.................................................. 108
Analog Interface Inputs........................................................... 108
Power Supply Decoupling ....................................................... 108
PLL ............................................................................................. 108
VREFN and VREFP................................................................. 108
Digital Outputs (Both Data and Clocks) .............................. 108
Digital Inputs ............................................................................ 108
Typical Circuit Connection......................................................... 109
Outline Dimensions..................................................................... 111
Ordering Guide ........................................................................ 111
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Introduction ...................................................................................... 4
Analog Front End......................................................................... 4
Standard Definition Processor ................................................... 4
Comparison with the ADV7181B.............................................. 5
Functional Block Diagrams............................................................. 6
Specifications..................................................................................... 7
Electrical Characteristics............................................................. 7
Video Specifications..................................................................... 8
Timing Specifications .................................................................. 9
Analog Specifications................................................................... 9
Thermal Specifications ................................................................ 9
Timing Diagrams........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
40-Lead LFCSP ........................................................................... 12
64-Lead LQFP............................................................................. 13
Analog Front End ........................................................................... 15
Input Configuration................................................................... 16
INSEL[3:0], Input Selection, Address 0x00 [3:0] ................... 16
Analog Input Muxing ................................................................ 17
Antialiasing Filters ..................................................................... 18
Global Control Registers ............................................................... 19
Power-Saving Modes.................................................................. 19
Reset Control .............................................................................. 19
Global Pin Control ..................................................................... 19
Global Status Register .................................................................... 21
Identification............................................................................... 21
Status 1 ......................................................................................... 21
Autodetection Result.................................................................. 21
Status 2 ......................................................................................... 21
Status 3 ......................................................................................... 21
Video Processor .............................................................................. 22
SD Luma Path ............................................................................. 22
Rev. A | Page 2 of 112
ADV7180
REVISION HISTORY
11/06—Rev. 0 to Rev. A
Changes to Table 10 and Table 11.................................................16
Changes to Table 30 ........................................................................28
Changes to Gain Operation Section .............................................33
Changes to Table 43 ........................................................................35
Changes to Table 97 ........................................................................72
Changes to Table 99 ........................................................................73
Changes to Table 103 ......................................................................80
Changes to Figure 54 ....................................................................110
1/06—Revision 0: Initial Version
Rev. A | Page 3 of 112
ADV7180
INTRODUCTION
The ADV7180 is a versatile one-chip multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-video, and
component video into a digital ITU-R BT.656 format.
STANDARD DEFINITION PROCESSOR
The ADV7180 is capable of decoding a large selection of
baseband video signals in composite, S-video, and component
formats. The video standards supported by the video processor
include PAL B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc,
NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The
ADV7180 can automatically detect the video standard and
process it accordingly.
The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devides digital video encoders, such as the ADV7179.
External HS, VS, and FIELD signals provide timing references
for LCD controllers and other video ASICs that do not support
the ITU-R BT.656 interface standard.
The ADV7180 has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the
video standard and signal quality without requiring user
intervention. Video user controls such as brightness, contrast,
saturation, and hue are also available with the ADV7180.
ANALOG FRONT END
The ADV7180 analog front end comprises a single high speed,
10-bit, analog-to-digital converter (ADC) that digitizes the
analog video signal before applying it to the standard definition
processor. The analog front end employs differential channels
to the ADC to ensure high performance in mixed-signal
applications.
The ADV7180 implements a patented Adaptive Digital Line
Length Tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7180 to track and decode poor quality video sources such
as VCRs and noisy sources from tuner outputs, VCD players,
and camcorders. The ADV7180 contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The front end also includes a 3-channel input mux that enables
multiple composite video signals to be applied to the ADV7180.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see Figure 24). Fine clamping of the video signal
is performed downstream by digital fine clamping within
the ADV7180.
The video processor can process a variety of VBI data services,
such as closed captioning (CCAP), wide-screen signaling
(WSS), copy generation management system (CGMS), EDTV,
Gemstar® 1×/2×, and extended data service (XDS). Teletext data
slicing for world standard teletext (WST), along with program
delivery control (PDC) and video programming service (VPS),
are provided. Data is transmitted via the 8-bit video output port
as ancillary data packets (ANC). The ADV7180 is fully
Macrovision certified; detection circuitry enables Type I,
Type II, and Type III protection levels to be identified and
reported to the user. The decoder is also fully robust to all
Macrovision signal inputs.
Table 1 shows the three ADC clocking rates, which are determined
by the video input format to be processed—that is, INSEL[3:0].
These clock rates ensure 4× oversampling per channel for CVBS
mode and 2× oversampling per channel for Y/C and YPrPb modes.
Table 1. ADC Clock Rates
Oversampling
Rate per Channel
Input Format
CVBS
Y/C (S-Video) 2
ADC Clock Rate1
57.27 MHz
86 MHz
4×
2×
2×
YPrPb
86 MHz
1 Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins.
2 Refer to INSEL[3:0] in Table 103 for the mandatory write for Y/C (S-video) mode.
Rev. A | Page 4 of 112
ADV7180
Pin Compatibility with the ADV7181B
COMPARISON WITH THE ADV7181B
The ADV7180 LQFP-64 is pin compatible with the ADV7181B.
In comparison with the ADV7181B, the ADV7180 LQFP-64 has
the following additional features:
A complete ADV7181B-to-ADV7180 change over document is
available on request that specifies software changes required to
make the transition. Contact Analog Devices local field
engineers for more information.
•
•
•
•
•
•
Improved VCR and weak tuner locking capabilities
Three on-chip antialiasing filters
Four general-purpose outputs (GPOs)
1.8 V analog supply voltage
Please note that the ADV7180 has a different ADC reference
decoupling circuit (shown in Figure 2) than the ADV7181B.
40-lead LFCSP option
0.1µF
Automatic power-down of unused channels when using
INSEL[3:0]
VREFN
0.1µF
VREFP
0.1µF
Figure 2. ADV7180 ADC Reference Decoupling Circuit
Rev. A | Page 5 of 112
ADV7180
FUNCTIONAL BLOCK DIAGRAMS
CLOCK PROCESSING BLOCK
XTAL1
XTAL
LLC
PLL
ADLLT PROCESSING
16-BIT
PIXEL DATA
DIGITAL
PROCESSING
BLOCK
10-BIT, 86MHz
ADC
P15 TO P0
A
A
A
A
A
A
1
2
3
4
5
6
IN
IN
IN
IN
IN
IN
AA
FILTER
2D COMB
HS
ANALOG
VIDEO
INPUTS
AA
FILTER
SHA
A/D
VS
VBI SLICER
FIELD
AA
FILTER
COLOR
DEMOD
GPO0 TO GPO3
SFL
INTRQ
2
REFERENCE
I C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
Figure 3. Functional Block Diagram (64-Lead LQFP)
CLOCK PROCESSING BLOCK
XTAL1
XTAL
LLC
PLL
ADLLT PROCESSING
8-BIT
PIXEL DATA
DIGITAL
PROCESSING
BLOCK
10-BIT, 86MHz
ADC
P7 TO P0
AA
FILTER
A
A
A
1
2
3
IN
IN
IN
2D COMB
ANALOG
VIDEO
INPUTS
HS
AA
FILTER
SHA
A/D
VBI SLICER
VS/FIELD
SFL
AA
FILTER
COLOR
DEMOD
INTRQ
2
REFERENCE
I C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
Figure 4. Functional Block Diagram (40-Lead LFCSP)
Rev. A | Page 6 of 112
ADV7180
SPECIFICATIONS
Temperature range: TMIN to TMAX is −40°C to +85°C. The min/max specifications are guaranteed over this range.
ELECTRICAL CHARACTERISTICS
At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature
range, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
N
INL
DNL
10
Bits
LSB
LSB
BSL in CVBS mode
CVBS mode
2
−0.6/+0.6
Input High Voltage
Input Low Voltage
Crystal Inputs
Crystal Inputs
Input Current
VIH
VIL
VIH
VIL
IIN
2
V
V
V
V
μA
pF
0.8
1.2
–10
0.4
+10
10
Input Capacitance
CIN
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS1
Digital Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
VOH
VOL
ILEAK
COUT
ISOURCE = 0.4 mA
ISINK = 3.2 mA
2.4
V
V
μA
pF
0.4
10
20
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
1.65
3.0
1.65
1.71
1.8
3.3
1.8
1.8
77
3
12
33
59
77
6
0.1
1
1
15
20
2
V
V
V
V
3.6
2.0
1.89
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μW
ms
IAVDD
CVBS input
Y/C input
YPrPb input
Power-Down Current
IDVDD
IDVDDIO
IPVDD
IAVDD
Total Power Dissipation in Power-Down Mode2
Power-Up Time
tPWRUP
1 Guaranteed by characterization.
2 ADV7180 clocked.
Rev. A | Page 7 of 112
ADV7180
VIDEO SPECIFICATIONS
Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V,
specified at operating temperature range, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions
Min Typ
Max
Unit
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
DP
DG
LNL
CVBS input, modulate 5-step [NTSC]
CVBS input, modulate 5-step [NTSC]
CVBS input, 5-step [NTSC]
0.6
0.5
2.0
Degrees
%
%
Luma ramp
57.1
58
60
dB
dB
dB
Luma flat field
Analog Front-End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
FSC Subcarrier Lock Range
Color Lock-In Time
–5
40
1.3
60
20
5
+5
70
%
Hz
kHz
Lines
%
Sync Depth Range
Color Burst Range
200
200
%
Vertical Lock Time
Autodetection Switch Speed
Chroma Lima Gain Delay
2
Fields
Lines
ns
ns
ns
100
2.9
5.6
−3.0
CVBS
Y/C
YPrPb
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
CVBS, 1 V input
CVBS, 1 V input
1
1
%
%
Rev. A | Page 8 of 112
ADV7180
TIMING SPECIFICATIONS
Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V,
specified at operating temperature range, unless otherwise noted.
Table 4.
Parameter
Symbol Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
28.6363
MHz
ppm
50
I2C PORT
SCLK Frequency
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Times
SCLK and SDA Fall Times
Setup Time for Stop Condition
RESET FEATURE
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
t9:t10
45:55
55:45 % duty cycle
t11
t12
Negative clock edge to start of valid data
(tACCESS = t10 – t11)
End of valid data to negative clock edge
(tHOLD = t9 + t12)
3.6
2.4
ns
ns
Data Output Transitional Time
ANALOG SPECIFICATIONS
Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V,
specified at operating temperature range, unless otherwise noted.
Table 5.
Parameter
Test Conditions
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large-Clamp Source Current
Large-Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
0.1
10
0.4
0.4
10
μF
Clamps switched off
MΩ
mA
mA
μA
10
μA
THERMAL SPECIFICATIONS
Table 6.
Parameter
Symbol Test Conditions
Min
Typ
Max
Unit
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
θJA
θJC
θJA
θJC
4-layer PCB with solid ground plane,
40-lead LFCSP
4-layer PCB with solid ground plane,
40-lead LFCSP
4-layer PCB with solid ground plane,
64-lead LQFP
30
3
°C/W
°C/W
°C/W
°C/W
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
47
11.1
4-layer PCB with solid ground plane,
64-lead LQFP
Rev. A | Page 9 of 112
ADV7180
TIMING DIAGRAMS
t5
t3
t3
SDATA
t1
t6
SCLK
t4
t7
t8
t2
Figure 5. I2C Timing
t9
t10
OUTPUT LLC
t11
t12
OUTPUTS P0–P15, VS,
HS, FIELD,
SFL
Figure 6. Pixel Port and Control Output Timing
Rev. A | Page 10 of 112
ADV7180
ABSOLUTE MAXIMUM RATINGS
Table 7.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD to AGND
DVDD to DGND
PVDD to AGND
2.2 V
2.2 V
2.2 V
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
AVDD to DVDD
Digital Inputs Voltage
Digital Output Voltage
Analog Inputs to AGND
4 V
−0.3 V to +2 V
−0.3 V to +0.9 V
–0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +0.3 V
−0.3 V to +0.9 V
DGND − 0.3 V to DVDDIO + 0.3 V
DGND − 0.3 V to DVDDIO + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
This device is a high performance integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Maximum Junction Temperature 125°C
(TJ max)
Storage Temperature Range
−65°C to +150°C
Infrared Reflow Soldering (20 sec) 260°C
Rev. A | Page 11 of 112
ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
40-LEAD LFCSP
PIN 1
DVDDIO
SFL
DGND
DVDDIO
P7
1
2
3
4
5
6
7
8
9
30
29
A
A
3
2
IN
IN
INDICATOR
28 AGND
27 AVDD
26 VREFN
25 VREFP
24 AGND
23 A 1
22 TEST_0
21 AGND
ADV7180
LFCSP
P6
P5
P4
P3
TOP VIEW
(Not to Scale)
IN
P2 10
Figure 7. 40-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40
Pin No.
3, 15, 35, 40
21, 24, 28
1, 4
14, 36
27
Mnemonic
Type
Function
DGND
AGND
DVDDIO
DVDD
AVDD
G
G
P
P
P
P
I
O
O
O
Ground for Digital Supply.
Ground for Analog Supply.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
20
PVDD
23, 29, 30
5 to 10, 16, 17
39
AIN1 to AIN3
P7 to P2, P1, P0
HS
38
INTRQ
37
33
34
32
VS/FIELD
SDATA
SCLK
O
I/O
I
I
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
ALSB
Selects the I2C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a
write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC.
31
11
RESET
LLC
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or
down according to video line length.
O
13
12
XTAL
I
Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal, or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
XTAL1
O
18
19
PWRDWN
ELPF
I
I
A logic low on this pin places the ADV7180 into power-down mode.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 53.
2
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video
encoder.
26
25
22
VREFN
VREFP
TEST_0
O
O
I
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
This pin must be tied to DGND.
Rev. A | Page 12 of 112
ADV7180
64-LEAD LQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INTRQ
HS
A
A
A
5
4
3
IN
IN
IN
PIN 1
3
DGND
DVDDIO
P11
4
NC
NC
5
6
P10
AGND
NC
ADV7180
7
P9
LQFP
TOP VIEW
(Not to Scale)
8
P8
NC
9
SFL
AVDD
VREFN
VREFP
AGND
10
11
12
13
14
15
16
DGND
DVDDIO
GPO1
GPO0
P7
A
A
2
1
IN
IN
P6
TEST_0
NC
P5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Figure 8. 64-Lead LQFP Pin Configuration
Table 9. Pin Function Description for the ADV7180 LQFP-64
Pin No.
Mnemonic
Type Function
3, 10, 24, 57
32, 37, 43
4, 11
23, 58
40
31
38
39
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
VREFP
VREFN
AIN1 to AIN6
G
G
P
P
P
P
O
O
I
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Analog Video Input Channels.
35, 36, 46 to 49
27, 28, 33, 41, 42,
44, 45, 50
NC
No Connect Pins. These pins are not connected internally.
5 to 8, 14 to 19,
25, 26, 59 to 62
P11 to P8,
P7 to P2, P1,
O
Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes.
P0, P15 to P12
2
HS
VS
FIELD
INTRQ
O
O
O
O
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address
selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42.
64
63
1
53
54
52
SDATA
SCLK
ALSB
I/O
I
I
29
30
PWRDWN
ELPF
I
I
A logic low on this pin places the ADV7180 in power-down mode.
The recommended external loop filter must be connected to the ELPF pin, as shown in
Figure 54.
51
RESET
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
Rev. A | Page 13 of 113
ADV7180
Pin No.
Mnemonic
Type Function
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
9
SFL
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.
20
21
LLC
O
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz, but varies up or down according to video line length.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an
external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal
mode, the crystal must be a fundamental crystal.
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external
1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a
fundamental crystal.
XTAL1
O
I
22
XTAL
12, 13, 55, 56
34
GPO0 to GPO3
TEST_0
O
I
General-Purpose Outputs. These pins can be configured via I2C to allow control of external
devices.
This pin must be tied to DGND.
Rev. A | Page 14 of 113
ADV7180
ANALOG FRONT END
MAN_MUX_EN
A
A
A
A
A
A
2
IN
1
MUX_0[3:0]
IN
IN
IN
IN
IN
4
3
6
5
A
A
A
A
4
3
6
5
IN
IN
IN
IN
MUX_1[3:0]
MUX_2[3:0]
ADC
A
A
6
5
IN
IN
Figure 9. Internal Pin Connections LQFP-64
MAN_MUX_EN
A
A
A
1
2
3
MUX_0[3:0]
IN
IN
IN
A
A
2
3
IN
IN
MUX_1[3:0]
MUX_2[3:0]
ADC
A
3
IN
Figure 10. Internal Pin Connections LFCSP-40
Rev. A | Page 15 of 112
ADV7180
INPUT CONFIGURATION
Table 10. ADV7180 LQFP-64 INSEL[3:0]
There are two key steps for configuring the ADV7180 to
correctly decode the input video.
INSEL[3:0]
Video Format
Composite
Composite
Composite
Composite
Composite
Composite
Y/C (S-video)
Analog Input
CVBS → AIN1
CVBS → AIN2
CVBS → AIN3
CVBS → AIN4
CVBS → AIN5
CVBS → AIN6
Y → AIN1
0000
0001
1. Use INSEL[3:0] to configure routing and format decoding
(CVBS, Y/C, or YPrPb). For the ADV7180 LQFP-64, see
Table 10. For ADV7180 LFCSP-40, see Table 11.
0010
0011
0100
2. If the input requirements are not met using the INSEL[3:0]
options, the analog input muxing section must be
0101
0110
configured manually to correctly route the video from the
analog input pins to the ADC. The standard definition
processor block, which decodes the digital data, should be
configured to process either CVBS, Y/C, or YPrPb format.
This is performed by INSEL[3:0] selection.
C → AIN4
0111
1000
1001
Y/C (S-video)
Y/C (S-video)
YPrPb
Y → AIN2
C → AIN5
Y → AIN3
C → AIN6
CONNECT ANALOG VIDEO
SIGNALS TO ADV7180.
Y → AIN1
Pb → AIN4
Pr → AIN5
SET INSEL[3:0] TO CONFIGURE
VIDEO FORMAT. USE PREDEFINED
FORMAT/ROUTING.
1010
YPrPb
Y → AIN2
Pr → AIN6
Pb → AIN3
Not used
NO
1011 to 1111
Not used
YES
LQFP-64
LFCSP-40
CONFIGURE ADC INPUTS USING
MANUAL MUXING CONTROL BITS:
MUX_0[3:0], MUX_1[3:0], MUX_2[3:0].
SEE TABLE 12.
Table 11. ADV7180 LFCSP-40 INSEL[3:0]
REFER TO
TABLE 10
REFER TO
TABLE 11
INSEL[3:0]
Video Format
Composite
Not used
Composite
Composite
Not used
Analog Input
CVBS → AIN1
Not used
Figure 11. Signal Routing Options
0000
0001 to 0010
0011
INSEL[3:0], INPUT SELECTION, ADDRESS 0x00
[3:0]
CVBS → AIN2
CVBS → AIN3
Not used
0100
The INSEL bits allow the user to select the input format. They
also configure the standard definition processor core to process
composite (CVBS), S-video (Y/C), or component (YPrPb)
format.
0101
0110
Y/C (S-video)
Y → AIN1
C → AIN2
Not used
0111 to 1000
1001
Not used
YPrPb
INSEL[3:0] has predefined analog input routing schemes that
do not require manual mux programming (see Table 10 and
Table 11). This allows the user to route the various video signal
types to the decoder and select them using INSEL[3:0] only.
The added benefit is that if, for example, CVBS input is selected,
the remaining channels are powered down.
Y → AIN1
Pr → AIN3
Pb → AIN2
Not used
1010 to 1111
Not used
Rev. A | Page 16 of 112
ADV7180
MAN_MUX_EN, Manual Input Muxing Enable,
ANALOG INPUT MUXING
Address 0xC4 [7]
The ADV7180 has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder. Figure 9 and Figure 10 outline the overall structure
of the input muxing provided in the ADV7180.
To configure the ADV7180 analog muxing section, the user
must select the analog input AIN1 to AIN6 (ADV7180BSTZ) or
AIN1 to AIN3 (ADV7180BCPZ) that is to be processed by the
ADC. MAN_MUX_EN must be set to 1 to enable the following
muxing blocks:
A maximum of six CVBS inputs can be connected to and
decoded by the ADV7180BSTZ (64-lead LQFP) and a
maximum of three for ADV7180BCPZ (40-lead LFCSP). As
shown in the Pin Configurations and Function Description
section, these analog input pins lie in close proximity to one
another. This calls for a careful design of the PCB layout; for
example, ground shielding between all signals should be routed
through tracks that are physically close together. It is strongly
recommended to connect any unused analog input pins to
AGND to act as a shield.
•
•
•
MUX_0[3:0], ADC Mux Configuration, Address 0xC3 [3:0]
MUX_1[3:0], ADC Mux Configuration, Address 0xC3 [7:4]
MUX_2[3:0], ADC Mux Configuration, Address 0xC4 [3:0]
The three mux sections are controlled by the signal buses
SW_0/1/2[3:0]. Table 12 explains the control words used.
The input signal that contains the timing information (HS and
VS) must be processed by MUX_0. For example, in a Y/C input
configuration, MUX0 should be connected to the Y channel
and MUX1 to the C channel. When one or more muxes are not
used to process video, such as CVBS input, the idle mux and
associated channel clamps and buffers should be powered down
(see the description of Register 0x3A in Table 103).
Table 12. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)
ADC Connected to ADC Connected to
ADC Connected to
MUX_0[3:0]
000
001
010
011
LQFP-64
LFCSP-40
No connect
AIN1
No connect
No connect
AIN2
MUX_1[3:0]
000
001
010
011
LQFP-64
LFCSP-40
No connect
No connect
No connect
No connect
AIN2
MUX_2[3:0]
000
001
010
011
LQFP-64
LFCSP-40
No connect
No connect
No connect
No connect
No connect
AIN3
No connect
AIN1
AIN2
AIN3
AIN4
No connect
No connect
No connect
AIN3
AIN4
AIN5
No connect
No connect
AIN2
No connect
No connect
AIN5
100
101
100
101
100
101
AIN5
AIN3
AIN3
110
111
AIN6
No connect
No connect
No connect
110
111
AIN6
No connect
No connect
No connect
110
111
AIN6
No connect
No connect
No connect
Note the following:
•
•
•
CVBS can only be processed by MUX_0.
Y/C can only be processed by MUX_0 and MUX_1, respectively.
YPrPb can only be processed by MUX_0, MUX_1, and MUX_2, respectively.
Rev. A | Page 17 of 112
ADV7180
ANTIALIASING FILTERS
The ADV7180 has optional on-chip antialiasing filters on each
of the three channels that are multiplexed to the ADC (see
Figure 12). The filters are designed for standard definition video
up to 10 MHz bandwidth. Figure 13 and Figure 14 show the
filter magnitude and phase characteristics.
AA_FILT_EN, Address 0xF3 [1]
When AA_FILT_EN[1] is 0, AA Filter 2 is bypassed.
When AA_FILT_EN[1] is 1, AA Filter 2 is enabled.
AA_FILT_EN, Address 0xF3 [2]
The antialiasing filters are enabled by default and the selection
of INSEL[3:0] determines which filters are powered up at any
given time. For example, if CVBS mode is selected, the filter
circuits for the remaining input channels are powered down to
conserve power. However, the antialiasing filters can be disabled
or bypassed using the AA_FILT_MAN_OVR control.
When AA_FILT_EN[2] is 0, AA Filter 3 is bypassed.
When AA_FILT_EN[2] is 1, AA Filter 3 is enabled.
0
–4
–8
–12
–16
–20
–24
–28
–32
–36
10-BIT, 86MHz
ADC
A
A
A
1
2
IN
IN
IN
AA
FILTER 1
3
1
AA
FILTER 2
SHA
A/D
A
4
5
6
IN
IN
IN
1
1
A
A
AA
FILTER 3
1k
10k
100k
1M
10M
100M
1
ONLY AVAILABLE IN 64-LEAD PACKAGE
FREQUENCY (Hz)
Figure 12. Antialias Filter Configuration
Figure 13. Antialiasing Filter Magnitude Response
AA_FILT_MAN_OVR, Antialiasing Filter Override,
Address 0xF3 [3]
0
–10
–20
This feature allows the user to override the antialiasing filters
on/off settings, which are automatically selected by INSEL[3:0].
–30
–40
AA_FILT_EN, Antialiasing Filter Enable, Address 0xF3 [2:0]
–50
–60
These bits allow the user to enable or disable the antialiasing
filters on each of the three input channels multiplexed to the
ADC. When disabled, the analog signal bypasses the AA filter
and is routed directly to the ADC.
–70
–80
–90
–100
–110
–120
–130
–140
–150
AA_FILT_EN, Address 0xF3 [0]
When AA_FILT_EN[0] is 0, AA Filter 1 is bypassed.
When AA_FILT_EN[0] is 1, AA Filter 1 is enabled.
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 14. Antialiasing Filter Phase Response
Rev. A | Page 18 of 112
ADV7180
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
RESET
pin),
After setting the RESET bit (or initiating a reset via the
the part returns to the default for its primary mode of operation.
All I2C bits are loaded with their default values, making this bit
self-clearing.
POWER-SAVING MODES
Power-Down
PDBP, Address 0x0F [2]
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I2C writes are
performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented. See
the MPU Port Description section.
The digital supply of the ADV7180 can be shut down by using
the (
) pin or via I2C (PWRDWN, see below). PDBP
PWRDWN
controls whether the I2C control or the pin has the higher
priority. The default is to give the pin ( ) priority.
PWRDWN
This allows the user to have the ADV7180 powered down by
default at power-up without the need for an I2C write.
When RESET is 0 (default), operation is normal.
When RESET is 1, the reset sequence starts.
When PDBD is 0 (default), the digital supply power is controlled
by the
pin (the PWRDWN bit is disregarded).
PWRDWN
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03 [6]
When PDBD is 1, the PWRDWN bit, 0x0F[5], has priority
(the pin is disregarded).
PWRDWN, Address 0x0F [5]
This bit allows the user to three-state the output drivers of the
ADV7180.
When PDBP is set to 1, setting the PWRDWN bit switches the
ADV7180 to a chip-wide power-down mode. The power-down
stops the clock from entering the digital section of the chip,
thereby freezing its operation. No I2C bits are lost during
power-down. The PWRDWN bit also affects the analog blocks
and switches them into low current modes. The I2C interface is
unaffected and remains operational in power-down mode.
Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the
ADV7180 LFCSP-40), HS, VS, FIELD (VS/FIELD pin for the
ADV7180 LFCSP-40), and SFL pins are three-stated.
The timing pins (HS, VS, FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the Three-State LLC Driver and the Timing Signals Output
Enable sections.
The ADV7180 leaves the power-down state if the PWRDWN bit is
2
RESET
set to 0 (via I C) or if the ADV7180 is reset using the
pin.
Individual drive strength controls are provided via the
DR_STR_XX bits.
PDBP must be set to 1 for the PWRDWN bit to power down
the ADV7180.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
When PWRDWN is 0 (default), the chip is operational.
When PWRDWN is 1, the ADV7180 is in a chip-wide
power-down mode.
Three-State LLC Driver
RESET CONTROL
RESET, Chip Reset, Address 0x0F [7]
TRI_LLC, Address 0x1D [7]
This bit allows the output drivers for the LLC pin of the
ADV7180 to be three-stated. For more information on three-
state control, refer to the Three-State Output Drivers and the
Timing Signals Output Enable sections.
RESET
Setting this bit, which is equivalent to controlling the
pin on the ADV7180, issues a full chip reset. All I2C registers
are reset to their default/power-up values. Note that some
register bits do not have a reset value specified. They keep their
last written value. Those bits are marked as having a reset value
of x in the register tables (Table 103 and Table 104). After the
reset sequence, the part immediately starts to acquire the
incoming video signal.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
Rev. A | Page 19 of 112
ADV7180
Timing Signals Output Enable
Table 14. DR_STR_C Function
TIM_OE, Address 0x04 [3]
DR_STR_C[1:0]
Description
00
Low drive strength (1×)
Medium-low drive strength (2×)
Medium-high drive strength (3×)
High drive strength (4×)
The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active state (that is, driving state) even if the
TOD bit is set. If TIM_OE is set to low, the HS, VS, and FIELD
pins are three-stated depending on the TOD bit. This
functionality is beneficial if the decoder is to be used as a
timing generator only. This may be the case if only the timing
signals are to be extracted from an incoming signal, or if the
part is in free-run mode, where a separate chip can output a
company logo, for example.
01 (default)
10
11
Drive Strength Selection (Sync)
DR_STR_S[1:0], Address 0xF4 [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and FIELD are
driven. For more information, refer to the Drive Strength
Selection (Data) section.
For more information on three-state control, refer to the
Three-State Output Drivers section and the Three-State LLC
Driver section.
Table 15. DR_STR_S Function
DR_STR_S[1:0]
Description
Individual drive strength controls are provided via the
DR_STR_XX bits.
00
Low drive strength (1×)
Medium-low drive strength (2×)
Medium-high drive strength (3×)
High drive strength (4×)
01 (default)
10
11
When TIM_OE is 0 (default), HS, VS, and FIELD are three-
stated according to the TOD bit.
Enable Subcarrier Frequency Lock Pin
When TIM_OE is 1, HS, VS, and FIELD are forced active all the
time.
EN_SFL_PIN, Address 0x04 [1]
Drive Strength Selection (Data)
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as Genlock) from the ADV7180 core
to an encoder in a decoder/encoder back-to-back arrangement.
DR_STR[1:0], Address 0xF4 [5:4]
For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.
When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.
When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.
For more information on three-state control, refer to the Drive
Strength Selection (Clock) and the Drive Strength Selection
(Sync) sections.
Polarity LLC Pin
PCLK, Address 0x37 [0]
Table 13. DR_STR Function
DR_STR[1:0]
Description
The polarity of the clock that leaves the ADV7180 via the LLC
pin can be inverted using the PCLK bit.
00
Low drive strength (1×)
Medium-low drive strength (2×)
Medium-high drive strength (3×)
High drive strength (4×)
01 (default)
10
11
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
Drive Strength Selection (Clock)
When PCLK is 0, the LLC output polarity is inverted.
DR_STR_C[1:0], Address 0xF4 [3:2]
When PCLK is 1 (default), the LLC output polarity is normal
(see the Timing Specifications section).
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the Drive Strength Selection (Sync) and the Drive
Strength Selection (Data) sections.
Rev. A | Page 20 of 112
ADV7180
GLOBAL STATUS REGISTER
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7180. The other three registers contain
status bits from the ADV7180.
Table 17. Status_1 Function
STATUS_1
[7:0]
Bit Name
IN_LOCK
Description
0
1
In lock (now)
Lost lock (since last read of this
register)
LOST_LOCK
IDENTIFICATION
IDENT[7:0], Address 0x11 [7:0]
2
3
FSC_LOCK
FOLLOW_PW
FSC locked (now)
AGC follows peak white
algorithm
Result of autodetection
Result of autodetection
Result of autodetection
Color kill active
The register identification of the revision of the ADV7180. An
identification value of 0x18 indicates the ADV7180.
4
5
6
7
AD_RESULT[0]
AD_RESULT[1]
AD_RESULT[2]
COL_KILL
STATUS 1
STATUS_1[7:0], Address 0x10 [7:0]
This read-only register provides information about the internal
status of the ADV7180.
STATUS 2
See the CIL[2:0], Count Into Lock, Address 0x51 [2:0] section
and the COL[2:0], Count Out of Lock, Address 0x51 [5:3]
section for details on timing.
STATUS_2[7:0], Address 0x12 [7:0]
Table 18. STATUS_2 Function
STATUS_2
[7:0]
Depending on the setting of the FSCLE bit, the Status Register 0
and Status Register 1 are based solely on horizontal timing infor-
mation or on the horizontal timing and lock status of the color
subcarrier. See the FSCLE, FSC Lock Enable, Address 0x51 [7]
section.
Bit Name
MVCS DET
MVCS T3
Description
0
1
Detected Macrovision color striping
Macrovision color striping
protection; conforms to Type 3 if
high, Type 2 if low
2
MV PS DET
Detected Macrovision pseudo
sync pulses
AUTODETECTION RESULT
AD_RESULT[2:0], Address 0x10 [6:4]
3
4
5
6
7
MV AGC DET
LL NSTD
FSC NSTD
Reserved
Reserved
Detected Macrovision AGC pulses
Line length is nonstandard
FSC frequency is nonstandard
The AD_RESULT[2:0] bits report back on the findings from the
ADV7180 autodetection block. Consult the General Setup
section for more information on enabling the autodetection
block and the Autodetection of SD Modes section for more
information on how to configure it.
STATUS 3
STATUS_3[7:0], Address 0x13 [7:0]
Table 16. AD_RESULT Function
AD_RESULT[2:0]
Description
NTSM M/J
NTSC 4.43
PAL M
PAL 60
PAL B/G/H/I/D
SECAM
Table 19. STATUS_3 Function
STATUS_3
[7:0]
000
001
010
011
100
101
110
111
Bit Name
Description
0
INST_HLOCK
Horizontal lock indicator
(instantaneous)
Gemstar detect
Flags whether 50 Hz or 60 Hz is
present at output
Reserved for future use
ADV7180 outputs a blue screen
(see the DEF_VAL_EN, Default
Value Enable, Address 0x0C [0]
section)
1
2
GEMD
SD_OP_50Hz
PAL Combination N
SECAM 525
3
4
FREE_RUN_ACT
5
6
7
STD FLD LEN
INTERLACED
PAL_SW_LOCK
Field length is correct for
currently selected video standard
Interlaced video detected (field
sequence found)
Reliable sequence of swinging
bursts detected
Rev. A | Page 21 of 112
ADV7180
VIDEO PROCESSOR
STANDARD DEFINITION PROCESSOR
MACROVISION
DETECTION
STANDARD
AUTODETECTION
SLLC
CONTROL
VBI DATA
RECOVERY
DIGITIZED CVBS
DIGITIZED Y (YC)
LUMA
DIGITAL
FINE
LUMA
GAIN
CONTROL
LUMA
FILTER
LUMA
RESAMPLE
LUMA
2D COMB
CLAMP
LINE
AV
SYNC
EXTRACT
RESAMPLE
CONTROL
VIDEO DATA
OUTPUT
LENGTH
CODE
PREDICTOR
INSERTION
DIGITIZED CVBS
DIGITIZED C (YC)
CHROMA
DIGITAL
FINE
CHROMA
GAIN
CONTROL
MEASUREMENT
BLOCK (≥ I C)
CHROMA
DEMOD
CHROMA
FILTER
CHROMA
RESAMPLE
CHROMA
2D COMB
2
CLAMP
VIDEO DATA
PROCESSING
BLOCK
F
SC
RECOVERY
Figure 15. Block Diagram of the Video Processor
Figure 15 shows a block diagram of the ADV7180 video processor.
The ADV7180 can handle standard definition video in CVBS,
Y/C, and YPrPb formats. It can be divided into a luminance and
chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input.
SD CHROMA PATH
The input signal is processed by the following blocks:
•
Chroma Digital Fine Clamp.
This block uses a high precision algorithm to clamp the
video signal.
SD LUMA PATH
•
Chroma Demodulation.
The input signal is processed by the following blocks:
This block employs a color subcarrier (FSC) recovery unit to
regenerate the color subcarrier for any modulated chroma
scheme. The demodulation block then performs an AM
demodulation for PAL and NTSC, and an FM demodulation
for SECAM.
•
Luma Digital Fine Clamp.
This block uses a high precision algorithm to clamp the
video signal.
•
Luma Filter.
•
•
Chroma Filter.
This block contains a luma decimation filter (YAA) with a
fixed response and some shaping filters (YSH) that have
selectable responses.
This block contains a chroma decimation filter (CAA) with
a fixed response and some shaping filters (CSH) that have
selectable responses.
•
•
Luma Gain Control.
Chroma Gain Control.
The automatic gain control (AGC) can operate on a variety
of different modes, including gain based on the depth of
the horizontal sync pulse, peak white mode, and fixed
manual gain.
Automatic gain control (AGC) can operate on several
different modes, including gain based on the color subcarrier
amplitude, gain based on the depth of the horizontal sync
pulse on the luma channel, or fixed manual gain.
Luma Resample.
•
•
Chroma Resample.
To correct for line-length errors as well as dynamic line-
length changes, the data is digitally resampled.
The chroma data is digitally resampled to keep it perfectly
aligned with the luma data. The resampling is done to
correct for static and dynamic line-length errors of the
incoming video signal.
•
•
Luma 2D Comb.
The two-dimensional comb filter provides Y/C separation.
AV Code Insertion.
Chroma 2D Comb.
At this point, the decoded luma (Y) signal is merged with
the retrieved chroma values. AV codes can be inserted
(as per ITU-R BT.656).
The 2D, 5-line, superadaptive comb filter provides high
quality Y/C separation in case the input signal is CVBS.
Rev. A | Page 22 of 112
ADV7180
GENERAL SETUP
•
AV Code Insertion.
At this point, the demodulated chroma (Cr and Cb) signal
is merged with the retrieved luma values. AV codes can be
inserted (as per ITU-R BT.656).
Video Standard Selection
The VID_SEL[3:0] register allows the user to force the digital
core into a specific video standard. Under normal circumstances,
this is not necessary. The VID_SEL[3:0] bits default to an auto-
detection mode that supports PAL, NTSC, SECAM, and variants
thereof. The following section provides more information on
the autodetection system.
SYNC PROCESSING
The ADV7180 extracts syncs embedded in the analog input
video signal. There is currently no support for external HS/VS
inputs. The sync extraction is optimized to support imperfect
video sources, such as videocassette recorders with head
switches. The actual algorithm used employs a coarse detection
based on a threshold crossing, followed by a more detailed
detection using an adaptive interpolation algorithm. The raw
sync information is sent to a line-length measurement and
prediction block. The output of this is then used to drive the
digital resampling section to ensure that the ADV7180 outputs
720 active pixels per line.
Autodetection of SD Modes
To guide the autodetect system of the ADV7180, individual
enable bits are provided for each of the supported video standards.
Setting the relevant bit to 0 inhibits the standard from being
detected automatically. Instead, the system picks the closest of
the remaining enabled standards. The results of the autodetection
block can be read back via the status registers. See the Global
Status Register section for more information.
The sync processing on the ADV7180 also includes the
following specialized postprocessing blocks that filter and
condition the raw sync information retrieved from the digitized
analog video:
VID_SEL[3:0], Address 0x00 [7:4]
Table 20. VID_SEL Function
VID_SEL[3:0]
Description
0000 (default)
Autodetect (PAL B/G/H/I/D) <–> NTSC J
(no pedestal), SECAM
•
VSYNC Processor.
This block provides extra filtering of the detected VSYNCs
to improve vertical lock.
0001
0010
0011
Autodetect (PAL B/G/H/I/D) <–> NTSC M
(pedestal), SECAM
Autodetect (PAL N) (pedestal) <–> NTSC J
(no pedestal), SECAM
Autodetect (PAL N) (pedestal) <–> NTSC M
(pedestal), SECAM
•
HSYNC Processor.
The HSYNC processor is designed to filter incoming
HSYNCs that have been corrupted by noise, providing
much improved performance for video signals with a
stable time base but poor SNR.
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
NTSC J (1)
NTSC M (1)
PAL 60
NTSC 4.43 (1)
VBI DATA RECOVERY
The ADV7180 can retrieve the following information from the
input video:
PAL B/G/H/I/D
PAL N = PAL B/G/H/I/D (with pedestal)
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with pedestal)
SECAM
•
•
•
•
•
•
•
•
Wide-screen signaling (WSS)
Copy generation management system (CGMS)
Closed captioning (CCAP)
Macrovision protection presence
EDTV data
SECAM (with pedestal)
AD_SEC525_EN, Enable Autodetection of SECAM 525
Line Video, Address 0x07 [7]
Gemstar-compatible data slicing
Teletext
Setting AD_SEC525_EN to 0 (default) disables the
autodetection of a 525-line system with a SECAM-style, FM-
modulated color component.
VITC/VPS
The ADV7180 is also capable of automatically detecting the
incoming video standard with respect to
Setting AD_SEC525_EN to 1 enables the detection of a
SECAM-style, FM-modulated color component.
•
•
•
Color subcarrier frequency
Field rate
Line rate
The ADV7180 can configure itself to support PAL B/G/H/I/D,
PAL M/N, PAL Combination N, NTSC M, NTSC J, SECAM
50 Hz/60 Hz, NTSC 4.43, and PAL 60.
Rev. A | Page 23 of 112
ADV7180
AD_PAL_EN, Enable Autodetection of PAL,
Address 0x07 [0]
AD_SECAM_EN, Enable Autodetection of SECAM,
Address 0x07 [6]
Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.
Setting AD_SECAM_EN to 0 (default) disables the
autodetection of SECAM.
Setting AD_PAL_EN to 1 enables the detection of standard PAL.
Setting AD_SECAM_EN to 1 enables the detection of SECAM.
SFL_INV, Subcarrier Frequency Lock Inversion
AD_N443_EN, Enable Autodetection of NTSC 4.43,
Address 0x07 [5]
This bit controls the behavior of the PAL switch bit in the SFL
(Genlock Telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
AD_P60_EN, Enable Autodetection of PAL 60,
Address 0x07 [4]
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(Genlock Telegram) bit directly, whereas the later ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one-line delay of an SFL (Genlock
Telegram) transmission.
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.
AD_PALN_EN, Enable Autodetection of PAL N,
Address 0x07 [3]
As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work. Also,
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC. If the state of the PAL
switch bit is wrong, a 180° phase shift occurs.
Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.
Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
AD_PALM_EN, Enable Autodetection of PAL M,
Address 0x07 [2]
SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41 [6]
Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.
Setting SFL_INV to 0 (default) makes the part SFL-compatible
with ADV7190/ADV7191/ADV7194 encoders.
Setting AD_PALM_EN to 1 enables the detection of PAL M.
AD_NTSC_EN, Enable Autodetection of NTSC,
Address 0x07 [1]
Setting SFL_INV to 1 makes the part SFL-compatible with
ADV717x and ADV7173x encoders.
Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.
Lock Related Controls
Lock information is presented to the user through Bits[1:0] of
the Status Register 1. See the STATUS_1[7:0], Address 0x10 [7:0]
section. Figure 16 outlines the signal flow and the controls
available to influence the way the lock status information is
generated.
Setting AD_NTSC_EN to 1 enables the detection of standard
NTSC.
SELECT THE RAW LOCK SIGNAL
SRLS
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TIME_WIN
FREE_RUN
1
0
0
1
COUNTER INTO LOCK
COUNTER OUT OF LOCK
STATUS_1 [0]
STATUS_1 [1]
F
LOCK
SC
MEMORY
TAKE F LOCK INTO ACCOUNT
SC
FSCLE
Figure 16. Lock Related Signal Path
Rev. A | Page 24 of 112
ADV7180
SRLS, Select Raw Lock Signal, Address 0x51 [6]
COL[2:0], Count Out of Lock, Address 0x51 [5:3]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status Register 1).
Refer to Figure 16.
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 0 [1:0]. It counts
the value in lines of video.
•
The TIME_WIN signal is based on a line-to-line evaluation
of the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.
Table 22. COL Function
COL[2:0]
Number of Video Lines
•
The FREE_RUN signal evaluates the properties of the
incoming video over several fields, taking vertical
synchronization information into account.
000
001
010
1
2
5
011
100 (default)
101
110
111
10
Setting SRLS to 0 (default) selects the FREE_RUN signal.
Setting SRLS to 1 selects the TIME_WIN signal.
FSCLE, FSC Lock Enable, Address 0x51 [7]
100
500
1000
100,000
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in Status
Register 1. This bit must be set to 0 when operating the
ADV7180 in YPrPb component mode in order to generate a
reliable HLOCK status bit.
COLOR CONTROLS
These registers allow the user to control picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture clamping,
although both controls affect the dc level of the signal.
When FSCLE is set to 0 (default), only the overall lock status is
dependent on horizontal sync lock.
CON[7:0], Contrast Adjust, Address 0x08 [7:0]
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and FSC lock.
This register allows the user to control contrast adjustment of
the picture.
CIL[2:0], Count Into Lock, Address 0x51 [2:0]
Table 23. CON Function
CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state and reports this via Status 0 [1:0]. The bit
counts the value in lines of video.
CON[7:0]
0x80 (default)
0x00
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
0xFF
Table 21. CIL Function
SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3 [7:0]
CIL[2:0]
Number of Video Lines
000
1
001
010
011
100 (default)
101
2
5
10
100
500
1000
100,000
This register allows the user to control the gain of the Cb
channel only, which in turn adjusts the saturation of the picture.
Table 24. SD_SAT_Cb Function
SD_SAT_Cb[7:0] Description
0x80 (default)
0x00
0xFF
Gain on Cb channel = 0 dB
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
110
111
Rev. A | Page 25 of 112
ADV7180
Table 29. HUE Function
SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4 [7:0]
HUE[7:0]
0x00 (default)
0x7F
Description (Adjust Hue of the Picture)
Phase of the chroma signal = 0°
Phase of the chroma signal = −90°
Phase of the chroma signal = +90°
This register allows the user to control the gain of the Cr
channel only, which in turn adjusts the saturation of the picture.
0x80
Table 25. SD_SAT_Cr Function
SD_SAT_Cr[7:0] Description
DEF_Y[5:0], Default Value Y, Address 0x0C [7:2]
When the ADV7180 loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
0x80 (default)
0x00
0xFF
Gain on Cr channel = 0 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = +6 dB
SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1 [7:0]
•
If DEF_VAL_AUTO_EN bit is set to high and the ADV7180
has lost lock to the input video signal, this is the intended
mode of operation (automatic mode).
This register allows the user to select an offset for the Cb
channel only and to adjust the hue of the picture. There is a
functional overlap with the HUE[7:0] register.
•
The DEF_VAL_EN bit is set, regardless of the lock status of
the video decoder. This is a forced mode that may be
useful during configuration.
Table 26. SD_OFF_Cb Function
SD_OFF_Cb[7:0] Description
0x80 (default)
0x00
0xFF
0 offset applied to the Cb channel
−312 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
For DEF_Y[5:0], 0x0D (blue) is the default value for Y.
Register 0x0C has a default value of 0x36.
SD_OFF_Cr [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]
This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
DEF_C[7:0], Default Value C, Address 0x0D [7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if
Table 27. SD_OFF_Cr Function
SD_OFF_Cr[7:0]
0x80 (default)
0x00
Description
•
The DEF_VAL_AUTO_EN bit is set to high and the
ADV7180 cannot lock to the input video (automatic mode).
0 offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
•
DEF_VAL_EN bit is set to high (forced output).
0xFF
The data that is finally output from the ADV7180 for the
chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
{DEF_C[3:0], 0, 0, 0, 0}.
BRI[7:0], Brightness Adjust, Address 0x0A [7:0]
This register controls the brightness of the video signal. It
allows the user to adjust the brightness of the picture.
For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.
DEF_VAL_EN, Default Value Enable, Address 0x0C [0]
Table 28. BRI Function
BRI[7:0]
0x00 (default)
0x7F
Description
This bit forces the use of the default values for Y, Cr, and Cb.
Refer to the descriptions in the DEF_Y[5:0], Default Value Y,
Address 0x0C [7:2] and DEF_C[7:0], Default Value C, Address
0x0D [7:0] sections for additional information. In this mode,
the decoder also outputs a stable 27 MHz clock, HS, and VS.
Offset of the luma channel = 0IRE
Offset of the luma channel = +100IRE
Offset of the luma channel = –100IRE
0x80
HUE[7:0], Hue Adjust, Address 0x0B [7:0]
Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user-programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by
the DEF_VAL_AUTO_EN bit.
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
HUE[7:0] has a range of 90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user-programmable Y, Cr, and Cb values. This
overrides picture data even if the decoder is locked.
The hue adjustment value is fed into the AM color demodula-
tion block. Therefore, it only applies to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM and
does not work on component video inputs (YPrPb).
Rev. A | Page 26 of 112
ADV7180
After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Because the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur. Further-
more, dynamic changes in the dc level almost certainly lead to
visually objectionable artifacts, and must therefore be prohibited.
DEF_VAL_AUTO_EN, Default Value Automatic Enable,
Address 0x0C [1]
This bit enables the automatic use of the default values for Y, Cr,
and Cb when the ADV7180 cannot lock to the video signal.
Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If
the decoder is unlocked, it outputs noise.
Setting DEF_VAL_EN to 1 (default) enables free-run mode and
a colored screen set by user-programmable Y, Cr, and Cb values
is displayed when the decoder loses lock.
The clamping scheme has to complete two tasks. It must acquire
a newly connected video signal with a completely unknown dc
level, and it must maintain the dc level during normal operation.
CLAMP OPERATION
To acquire an unknown video signal quickly, the large current
clamps should be activated. It is assumed that the amplitude of
the video signal at this point is of a nominal value. Control of
the coarse and fine current clamp parameters is performed
automatically by the decoder.
The input video is ac-coupled into the ADV7180. Therefore, its
dc value needs to be restored. This process is referred to as
clamping the video. This section explains the general process of
clamping on the ADV7180 and shows the different ways in
which a user can configure its behavior.
Standard definition video signals may have excessive noise on
them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp would be
unsuitable for this type of video signal. Instead, the ADV7180
employs a set of four current sources that can cause coarse
(>0.5 mA) and fine (<0.1 mA) currents to flow into and away
from the high impedance node that carries the video signal
(see Figure 17).
The ADV7180 uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 17.
The analog processing channel shown is replicated three times
inside the IC. While only one single channel is needed for a
CVBS signal, two independent channels are needed for Y/C
(S-VHS) type signals, and three independent channels are
needed to allow component signals (YPrPb) to be processed.
The clamping can be divided into two sections:
The following sections describe the I2C signals that can be used
to influence the behavior of the clamping block.
•
Clamping before the ADC (analog domain): current
sources.
CCLEN, Current Clamp Enable, Address 0x14 [4]
•
Clamping after the ADC (digital domain): digital
processing block.
The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.
The ADC can digitize an input signal only if it resides within
the ADC 1.0 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.
When CCLEN is 0, the current sources are switched off.
When CCLEN is 1 (default), the current sources are enabled.
The primary task of the analog clamping circuits is to ensure that
the video signal stays within the valid ADC input window so that
the analog-to-digital conversion can take place. It is not necessary
to clamp the input signal with a very high accuracy in the analog
domain as long as the video signal fits within the ADC range.
FINE CURRENT SOURCES
COARSE CURRENT SOURCES
DATA
ANALOG
VIDEO
INPUT
VIDEO PROCESSOR
PRE-
ADC
WITH DIGITAL
PROCESSOR
FINE CLAMP
(DPP)
CLAMP CONTROL
Figure 17. Clamping Overview
Rev. A | Page 27 of 112
ADV7180
DCT[1:0], Digital Clamp Timing, Address 0x15 [6:5]
•
Luma Shaping Filters (YSH).
The clamp timing register determines the time constant of the
digital fine clamp circuitry. It is important to note that the
digital fine clamp reacts very quickly because it is supposed to
immediately correct any residual dc level error for the active
line. The time constant from the digital fine clamp must be
much quicker than the one from the analog blocks.
The shaping filter block is a programmable low-pass filter
with a wide variety of responses. It can be used to
selectively reduce the luma video signal bandwidth
(needed prior to scaling, for example). For some video
sources that contain high frequency noise, reducing the
bandwidth of the luma signal improves visual picture
quality. A follow-on video compression stage may work
more efficiently if the video is low-pass filtered.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
The ADV7180 has two responses for the shaping filter:
one that is used for good quality composite, component,
and S-VHS type sources, and a second for nonstandard
CVBS signals.
Table 30. DCT Function
DCT[1:0]
Description
00 (default)
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
Determined by ADV7180, depending on the
input video parameters
01
10
11
The YSH filter responses also include a set of notches for
PAL and NTSC. However, using the comb filters for Y/C
separation is recommended.
•
Digital Resampling Filter.
This block allows dynamic resampling of the video signal
to alter parameters such as the time base of a line of video.
Fundamentally, the resampler is a set of low-pass filters.
The actual response is chosen by the system with no
requirement for user intervention.
DCFE, Digital Clamp Freeze Enable, Address 0x15 [4]
This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their
own clamping. Users should disable the current sources for
analog clamping via the appropriate register bits, wait until the
digital clamp loop settles, and then freeze it via the DCFE bit.
Figure 19 through Figure 22 show the overall response of all
filters together. Unless otherwise noted, the filters are set into a
typical wideband mode.
When DCFE to 0 (default), the digital clamp is operational.
When DCFE is 1, the digital clamp loop is frozen.
LUMA FILTER
Y Shaping Filter
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. Y/C separation must aim for best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
Y/C separation can be achieved by using the internal comb
filters of the ADV7180. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of
the video line rate) and the color subcarrier (FSC). For good
quality CVBS signals, this relationship is known; the comb filter
algorithms can be used to separate luma and chroma with high
accuracy.
Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS input or luma only for Y/C and YPrPb input formats.
•
Luma Antialias Filter (YAA).
The ADV7180 receives video at a rate of 27 MHz. (In the case
of 4× oversampled video, the ADC samples at 57.27 MHz,
and the first decimation is performed inside the DPP filters.
Therefore, the data rate into the ADV7180 is always 27 MHz.)
The ITU-R BT.601 recommends a sampling frequency of
13.5 MHz. The luma antialias filter decimates the oversampled
video using a high quality linear phase, low-pass filter that
preserves the luma signal while at the same time attenuating
out-of-band components. The luma antialias filter (YAA)
has a fixed response.
In the case of nonstandard video signals, the frequency
relationship may be disturbed and the comb filters may not be
able to remove all crosstalk artifacts in the best fashion without
the assistance of the shaping filter block.
Rev. A | Page 28 of 112
ADV7180
An automatic mode is provided that allows the ADV7180 to
evaluate the quality of the incoming video signal and select the
filter responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
YSFM[4:0], Y Shaping Filter Mode, Address 0x17 [4:0]
The Y shaping filter mode bits allow the user to select from a
wide range of low-pass and notch filters. When switched in
automatic mode, the filter selection is based on other register
selections, such as detected video standard, as well as properties
extracted from the incoming video itself, such as quality and
time base stability. The automatic selection always selects the
widest possible bandwidth for the video input encountered.
The luma shaping filter has three control registers:
•
YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (depending on video quality and video
standard).
•
If the YSFM settings specify a filter (that is, YSFM is set to
values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.
•
•
WYSFMOVR allows the user to manually override the
WYSFM decision.
•
In automatic selection mode, the notch filters are only used
for bad quality video signals. For all other video signals,
wideband filters are used.
WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality composite (CVBS), component
(YPrPb), and S-VHS (Y/C) input signals.
WYSFMOVR, Wideband Y Shaping Filter Override,
Address 0x18 [7]
In automatic mode, the system preserves the maximum
possible bandwidth for good CVBS sources (because they can
be successfully combed) as well as for luma components of
YPrPb and Y/C sources (because they need not be combed).
For poor quality signals, the system selects from a set of
proprietary shaping filter responses that complements comb
filter operation in order to reduce visual artifacts.
Setting the WYSFMOVR bit enables the use of the
WYSFM[4:0] settings for good quality video signals. For more
information, refer to the general discussion of the luma shaping
filters in the Y Shaping Filter section and the flowchart shown
in Figure 18.
When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.
The decisions of the control logic are shown in Figure 18.
Setting WYSFMOVR to 1 (default) enables manual override via
WYSFM[4:0].
SET YSFM
YSFM IN AUTO MODE?
00000 OR 00001
YES
NO
VIDEO
QUALITY
BAD
GOOD
USE YSFM SELECTED
FILTER REGARDLESS OF
VIDEO QUALITY
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
WYSFMOVR
1
0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
SELECT AUTOMATIC
WIDEBAND FILTER
Figure 18. YSFM and WYSFM Control Flowchart
Rev. A | Page 29 of 112
ADV7180
Table 31. YSFM Function
YSFM[4:0] Description
Table 32. WYSFM Function
WYSFM[4:0]
0'0000
Description
Do not use
Do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
0'0000
Automatic selection including a wide-notch
response (PAL/NTSC/SECAM)
Automatic selection including a narrow-notch
response (PAL/NTSC/SECAM)
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
0'0001
0'0010
0'0011
0'0100
0'0101
0'0110
0'0111
0'1000
0'1001
0'1010
0'1011
0'1100
0'1101
0'1110
0'1111
1'0000
0'0001
(default)
0'0010
0'0011
0'0100
0'0101
0'0110
0'0111
0'1000
0'1001
0'1010
0'1011
0'1100
0'1101
0'1110
0'1111
1'0000
1'0001
1'0010
1'0011
1'0100
1'0101
1'0110
1'0111
1'1000
1'1001
1'1010
1'1011
1'1100
1'1101
1'1110
1'1111
SVHS 8
SVHS 9
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Do not use
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
1'0001
1'0010
1'0011 (default)
1'0100 to 1’1111
The filter plots in Figure 19 show the S-VHS 1 (narrowest) to
S-VHS 18 (widest) shaping filter settings. Figure 21 shows the
PAL notch filter responses. The NTSC-compatible notches are
shown in Figure 22.
COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,
Y RESAMPLE
0
–10
–20
–30
–40
–50
–60
–70
WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18 [4:0]
The WYSFM[4:0] bits allow the user to manually select a
shaping filter for good quality video signals, for example, CVBS
with stable time base, luma component of YPrPb, and luma
component of Y/C. The WYSFM bits are only active if the
WYSFMOVR bit is set to 1. See the general discussion of the
shaping filter settings in the Y Shaping Filter section.
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 19. Y S-VHS Combined Responses
Rev. A | Page 30 of 112
ADV7180
•
•
Chroma Shaping Filters (CSH).
CHROMA FILTER
The shaping filter block (CSH) can be programmed to
perform a variety of low-pass responses. It can be used to
selectively reduce the bandwidth of the chroma signal for
scaling or compression.
Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS inputs, chroma only for Y/C, or U/V interleaved for
YPrPb input formats.
Digital Resampling Filter.
•
Chroma Antialias Filter (CAA).
This block allows dynamic resampling of the video signal
to alter parameters such as the time base of a line of video.
Fundamentally, the resampler is a set of low-pass filters.
The actual response is chosen by the system without user
intervention.
The ADV7180 oversamples the CVBS by a factor of 4 and
the chroma/YPrPb by a factor of 2. A decimating filter (CAA)
is used to preserve the active video band and to remove any
out-of-band components. The CAA filter has a fixed response.
Figure 23 shows the overall response of all filters together.
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE
0
–20
0
–10
–20
–30
–40
–50
–60
–70
–40
–60
–80
–100
–120
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
Figure 20. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER
COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
Y RESAMPLE
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
–70
0
1
2
3
4
5
6
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. Chroma Shaping Filter Responses
Figure 21. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
Rev. A | Page 31 of 112
ADV7180
of the ADC, 0 V to 1 V. This circuit should be placed before all
analog inputs to the ADV7180.
CSFM[2:0], C Shaping Filter Mode, Address 0x17 [7:5]
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see Settings 000
and 001 in Table 33).
ANALOG VIDEO
INPUT
100nF
AIN_OF_ADV7180
36Ω
39Ω
Figure 24. Input Voltage Divider Network
Table 33. CSFM Function
The minimum supported amplitude of the input video is
determined by the ability of the ADV7180 to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
CSFM[2:0]
000 (default)
001
Description
Autoselect 1.5 MHz bandwidth
Autoselect 2.17 MHz bandwidth
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
010
011
100
SH1
SH2
SH3
101
110
111
SH4
SH5
The possible AGC modes are shown in Table 34.
Table 34. AGC Modes
Input
Wideband mode
Figure 23 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (shown in red).
Video Type Luma Gain
Chroma Gain
Any
Manual gain luma
Manual gain chroma
CVBS
Dependent on
horizontal sync depth
Dependent on color-
burst amplitude
GAIN OPERATION
The gain control within the ADV7180 is done on a purely
digital basis. The input ADC supports a 10-bit range mapped
into a 1.0 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.
taken from luma path
Dependent on color-
burst amplitude
taken from luma path
Dependent on color-
burst amplitude
taken from luma path
Dependent on color-
burst amplitude
Peak white
Y/C
Dependent on
horizontal sync depth
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
Peak white
YPrPb
Dependent on
horizontal sync depth
Taken from luma path
As shown in Figure 25, the ADV7180 can decode a video signal
as long as it fits into the ADC window. The components to this
are the amplitude of the input signal and the dc level it resides
on. The dc level is set by the clamping circuitry (see the Clamp
Operation section).
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating and the AGC determined gain
at the time of the freeze to stay active until the loop is either
unfrozen or the gain mode of operation is changed.
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
Luma Gain and Chroma Gain sections.
Figure 24 shows a typical voltage divider network that is
required to keep the input video signal within the allowed range
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1V RANGE FOR ADV7180)
MAXIMUM
VOLTAGE
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
DATA PRE-
PROCESSOR
(DPP)
ADC
GAIN
CONTROL
MINIMUM
VOLTAGE
CLAMP
LEVEL
Figure 25. Gain Control Overview
Rev. A | Page 32 of 112
ADV7180
Luma Gain
LG[11:0], Luma Gain, Address 0x2F [3:0],
Address 0x30 [7:0]; LMG[11:0], Luma Manual Gain,
Address 0x2F [3:0], Address 0x30 [7:0]
LAGC[2:0], Luma Automatic Gain Control,
Address 0x2C [6:4]
Luma gain [11:0] is a dual-function register. If all of these
registers are written to, a desired manual luma gain can be
programmed. This gain becomes active if the LAGC[2:0] mode
is switched to manual fixed gain. Equation 1 shows how to
calculate a desired gain.
The luma automatic gain control mode bits select the operating
mode for the gain control in the luma path.
There are internal parameters (Analog Devices proprietary
algorithms) to customize the peak white gain control. Contact
local Analog Devices field applications engineers or local
Analog Devices distributor for more information.
If read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, the value is
one of the following:
Table 35. LAGC Function
LAGC[2:0]
Description
•
Luma manual gain value (LAGC[2:0] set to luma manual
gain mode)
000
001
Manual fixed gain (use LMG[11:0])
Reserved
•
Luma automatic gain value (LAGC[2:0] set to any of the
automatic modes)
010 (default) AGC (blank level to sync tip), peak white
algorithm on
011
100
Reserved
Table 37. LG/LMG Function
LG[11:0]/LMG[11:0] Read/Write Description
AGC (blank level to sync tip), peak white
algorithm off
LMG[11:0] = X
Write
Manual gain for luma
path
Actual used gain
101
110
111
Reserved
Reserved
Freeze gain
LG[11:0]
Read
(1024 < LMG[11:0] ≤ 4095)
LAGT[1:0], Luma Automatic Gain Timing,
Address 0x2F [7:6]
Luma Gain(525i) ≅
≅ 0.72K2.9
≅ 0.7K2.78
1410
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. Note that this register only has an effect if the
LAGC[2:0] register is set to 001, 010, 011, or 100 (automatic
gain control modes).
(1024 < LMG[11:0] ≤ 4095)
Luma Gain(NTSC) ≅
1470
(1024< LMG[11:0] ≤ 4095)
Luma Gain(PAL/625i) ≅
1535
If peak white AGC is enabled and active (see the STATUS_1[7:0],
Address 0x10 [7:0] section), the actual gain update speed is
dictated by the peak white AGC loop and, as a result, the LAGT
settings have no effect. As soon as the part leaves peak white
AGC, LAGT becomes relevant again.
≅ 0.66K2.66
(1)
For example, with a 525i input applied, program the ADV7180
into manual fixed gain mode with a desired gain of 0.89 as
follows:
The update speed for the peak white algorithm can be
customized by the use of internal parameters. Contact Analog
Devices local field engineers for more information.
1. Use Equation 1 to convert the gain:
0.89 × 1410 = 1254.9
2. Truncate to integer value:
= 1255d
Table 36. LAGT Function
LAGT[1:0]
Description
3. Convert to hexadecimal:
1255d = 0x04E7
00
01
10
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
4. Split into two registers and program:
Luma Gain Control 1 [3:0] = 0x4
Luma Gain Control 2 [7:0] = 0xE7
11 (default)
5. Enable manual fixed gain mode:
Set LAGC[2:0] to 000
Rev. A | Page 33 of 112
ADV7180
BETACAM, Enable Betacam Levels, Address 0x01 [5]
PW_UPD, Peak White Update, Address 0x2B [0]
If YPrPb data is routed through the ADV7180, the automatic
gain control modes can target different video input levels, as
outlined in Table 40. Note that the BETACAM bit is valid only if
the input mode is YPrPb (component). The BETACAM bit sets
the target value for AGC operation.
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0]
must be set to the appropriate mode to enable the peak white or
average video mode in the first place. For more information,
refer to the LAGC[2:0], Luma Automatic Gain Control,
Address 0x2C [6:4] section.
A review of the following sections is useful:
•
MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4 [7] for how component video (YPrPb)
can be routed through the ADV7180.
Setting PW_UPD to 0 updates the gain once per video line.
Setting PW_UPD to 1 (default) updates the gain once per field.
Chroma Gain
•
Video Standard Selection to select the various standards,
for example, with and without pedestal.
CAGC[1:0], Chroma Automatic Gain Control,
Address 0x2C [1:0]
The automatic gain control (AGC) algorithms adjust the levels
based on the setting of the BETACAM bit (see Table 38).
The two bits of color automatic gain control mode select the
basic mode of operation for automatic gain control in the
chroma path.
Table 38. BETACAM Function
BETACAM
Description
0 (default)
Assuming YPrPb is selected as input format
Selecting PAL with pedestal selects MII
Selecting PAL without pedestal selects SMPTE
Selecting NTSC with pedestal selects MII
Selecting NTSC without pedestal selects SMPTE
Assuming YPrPb is selected as input format
Selecting PAL with pedestal selects BETACAM
1
Selecting PAL without pedestal selects BETACAM variant
Selecting NTSC with pedestal selects BETACAM
Selecting NTSC without pedestal selects BETACAM variant
Table 39. CAGC Function
CAGC[1:0]
Description
00
01
Manual fixed gain (use CMG[11:0])
Use luma gain for chroma
10 (default)
11
Automatic gain (based on color burst)
Freeze chroma gain
Table 40. Betacam Levels
Name
Betacam (mV)
Betacam Variant (mV)
0 to 714
SMPTE (mV)
0 to 700
MII (mV)
Y
0 to 714 (incl. 7.5% pedestal)
0 to 700 (incl. 7.5% pedestal)
Pb and Pr
Sync Depth
–467 to +467
286
–505 to +505
286
–350 to +350
300
–324 to +324
300
Rev. A | Page 34 of 112
ADV7180
CAGT[1:0], Chroma Automatic Gain Timing,
Address 0x2D [7:6]
CKE, Color Kill Enable, Address 0x2B [6]
The color kill enable bit allows the optional color kill function
to be switched on or off.
The chroma automatic gain timing register allows the user to
influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0]
register is set to 10 (automatic gain).
For QAM-based video standards (PAL and NTSC) as well as
FM-based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.
If color kill is enabled and the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.
Table 41. CAGT Function
CAGT[1:0]
Description
00
01
10
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
11 (default)
The color kill option only works for input signals with a
modulated chroma part. For component input (YPrPb), there is
no color kill.
CG[11:0], Chroma Gain, Address 0x2D [3:0],
Address 0x2E [7:0]; CMG[11:0], Chroma Manual Gain,
Address 0x2D [3:0], Address 0x2E [7:0]
Setting CKE to 0 disables color kill.
Chroma gain [11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] mode is switched to manual
fixed gain. Refer to Equation 2 for calculating a desired gain.
Setting CKE to 1 (default) enables color kill.
CKILLTHR[2:0], Color Kill Threshold, Address 0x3D
[6:4]
The CKILLTHR[2:0] bits allow the user to select a threshold for
the color kill function. The threshold applies to only QAM-
based (NTSC and PAL) or FM-modulated (SECAM) video
standards.
If read back, this register returns the current gain value.
Depending on the setting in the CAGC[1:0] bits, this is either:
•
•
The chroma manual gain value (CAGC[1:0] set to chroma
manual gain mode).
To enable the color kill function, the CKE bit must be set. For
Settings 000, 001, 010, and 011, chroma demodulation inside
the ADV7180 may not work satisfactorily for poor input video
signals.
The chroma automatic gain value (CAGC[1:0] set to any of
the automatic modes).
Table 42. CG/CMG Function
Table 43. CKILLTHR Function
CG[11:0]/CMG[11:0] Read/Write Description
Description
CMG[11:0]
Write
Manual gain for chroma
path
CKILLTHR[2:0] SECAM
NTSC, PAL
CG[11:0]
Read
Currently active gain
000
001
010
011 (default)
100
No color kill
Kill at <0.5%
Kill at <1.5%
Kill at <2.5%
Kill at <4.0%
Kill at <8.5%
Kill at <16.0%
Kill at <32.0%
Kill at <5%
Kill at <7%
Kill at <8%
Kill at <9.5%
Kill at <15%
Kill at <32%
(0 < CG ≤ 4095)
Chroma_Gain ≅
≅ 0 . . . 6.29
(2)
650
For example, freezing the automatic gain loop and reading back
the CG[11:0] register results in a value of 0x47A as follows:
101
110
1. Convert the readback value to decimal:
0x47A = 1146d
111
Reserved for Analog Devices internal use only.
Do not select.
2. Apply Equation 2 to convert the readback value:
1146/1024 = 1.12
Rev. A | Page 35 of 112
ADV7180
CHROMA TRANSIENT IMPROVEMENT (CTI)
The signal bandwidth allocated for chroma is typically much
smaller than that of luminance. In the past, this was a valid way
to fit a color video signal into a given overall bandwidth because
the human eye is less sensitive to chrominance than to luminance.
CTI_AB_EN, Chroma Transient Improvement
Alpha Blend Enable, Address 0x4D [1]
The CTI_AB_EN bit enables an alpha blend function within the
CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.
The uneven bandwidth, however, may lead to visual artifacts in
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see
Figure 26). Due to the higher bandwidth, the signal transition
of the luma component is usually much sharper than that of the
chroma component. The color edge is not sharp and can be
blurred, in the worst case, over several pixels.
For the alpha blender to be active, the CTI block must be
enabled via the CTI_EN bit.
Setting CTI_AB_EN to 0 disables the CTI alpha blender.
Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend
mixing function.
CTI_AB[1:0], Chroma Transient Improvement Alpha
Blend, Address 0x4D [3:2]
LUMA SIGNAL WITH A
TRANSITION, ACCOMPANIED
LUMA SIGNAL
BY A CHROMA TRANSITION
The CTI_AB[1:0] controls the behavior of alpha blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.
ORIGINAL, SLOW CHROMA
TRANSITION PRIOR TO CTI
DEMODULATED
CHROMA SIGNAL
For CTI_AB[1:0] to become active, the CTI block must be
enabled via the CTI_EN bit and the alpha blender must be
switched on via CTI_AB_EN.
SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI
Figure 26. CTI Luma/Chroma Transition
Sharp blending maximizes the effect of CTI on the picture, but
may also increase the visual impact of small amplitude, high
frequency chroma noise.
The chroma transient improvement block examines the input
video data. It detects transitions of chroma and can be
programmed to create steeper chroma edges in an attempt to
artificially restore lost color bandwidth. The CTI block,
however, operates only on edges above a certain threshold to
ensure that noise is not emphasized. Care has also been taken to
ensure that edge ringing and undesirable saturation or hue
distortion are avoided.
Table 44. CTI_AB Function
CTI_AB[1:0] Description
00
Sharpest mixing between sharpened and original
chroma signal
01
Sharp mixing
10
Smooth mixing
Chroma transient improvements are needed primarily for
signals that have severe chroma bandwidth limitations. For
those types of signals, it is strongly recommended to enable the
CTI block via CTI_EN.
11 (default)
Smoothest alpha blend function
CTI_C_TH[7:0], CTI Chroma Threshold,
Address 0x4E [7:0]
CTI_EN, Chroma Transient Improvement Enable,
Address 0x4D [0]
The CTI_C_TH[7:0] value is an unsigned, 8-bit number speci-
fying how big the amplitude step in a chroma transition has to
be in order to be steepened by the CTI block. Programming a
small value into this register causes even smaller edges to be
steepened by the CTI block. Making CTI_C_TH[7:0] a large
value causes the block to improve large transitions only.
Setting CTI_EN to 0 disables the CTI block.
Setting CTI_EN to 1 (default) enables the CTI block.
The default value for CTI_C_TH[7:0] is 0x08, indicating the
threshold for the chroma edges prior to CTI.
Rev. A | Page 36 of 112
ADV7180
PEAKING_GAIN[7:0], Luma Peaking Gain,
Address 0xFB [7:0]
DIGITAL NOISE REDUCTION (DNR) AND LUMA
PEAKING FILTER
Digital noise reduction is based on the assumption that high
frequency signals with low amplitude are probably noise and
that their removal, therefore, improves picture quality. There are
two DNR blocks in the ADV7180: the DNR1 block before the
luma peaking filter and the DNR2 block after the luma peaking
filter, as shown in Figure 27.
This filter can be manually enabled. The user can select to boost
or attenuate the mid region of the Y spectrum around 3 MHz.
The peaking filter can visually improve the picture by showing
more definition on the picture details that contain frequency
components around 3 MHz. The default value on this register
passes through the luma data unaltered. A lower value
attenuates the signal, and a higher value gains the luma signal.
A plot of the filter’s responses is shown in Figure 28.
Table 47. PEAKING_GAIN[7:0] Function
LUMA
SIGNAL
LUMA
OUTPUT
LUMA PEAKING
FILTER
DNR2
DNR1
Setting
Description
0x40 (Default)
0 dB response
PEAKING GAIN USING BP FILTER
15
10
5
Figure 27. DNR and Peaking Block Diagram
DNR_EN, Digital Noise Reduction Enable,
Address 0x4D [5]
The DNR_EN bit enables the DNR block or bypasses it.
0
Table 45. DNR_EN Function
Setting
Description
–5
–10
–15
0
Bypasses DNR (disable)
Enables digital noise reduction on the luma data
1 (Default)
DNR_TH[7:0], DNR Noise Threshold, Address 0x50 [7:0]
–20
0
The DNR1 block is positioned before the luma peaking block.
The DNR_TH[7:0] value is an unsigned, 8-bit number used to
determine the maximum edge that is interpreted as noise and
therefore blanked from the luma data. Programming a large
value into DNR_TH[7:0] causes the DNR block to interpret
even large transients as noise and remove them. As a result, the
effect on the video data is more visible. Programming a small
value causes only small transients to be seen as noise and to be
removed.
1
2
3
4
5
6
7
FREQUENCY (MHz)
Figure 28. Peaking Filter Responses
DNR_TH2[7:0], DNR Noise Threshold 2,
Address 0xFC [7:0]
The DNR2 block is positioned after the luma peaking block
and, therefore, affects the gained luma signal. It operates in the
same way as the DNR1 block, but there is an independent
threshold control, DNR_TH2[7:0], for this block. This value is
an unsigned, 8-bit number used to determine the maximum
edge that is interpreted as noise and therefore blanked from the
luma data. Programming a large value into DNR_TH2[7:0]
causes the DNR block to interpret even large transients as noise
and remove them. As a result, the effect on the video data is
more visible. Programming a small value causes only small
transients to be seen as noise and to be removed.
Table 46. DNR_TH[7:0] Function
Setting
Description
0x08 (Default)
Threshold for maximum luma edges to be
interpreted as noise
Table 48. DNR_TH2[7:0] Function
Setting
Description
0x04 (Default)
Threshold for maximum luma edges to be
interpreted as noise
Rev. A | Page 37 of 112
ADV7180
NTSC Comb Filter Settings
COMB FILTERS
Used for NTSC M/J CVBS inputs.
The comb filters of the ADV7180 have been greatly improved to
automatically handle video of all types, standards, and levels of
quality. The NTSC and PAL configuration registers allow the
user to customize comb filter operation, depending on which
video standard is detected (by autodetection) or selected (by
manual programming). In addition to the bits listed in this
section, there are some further internal controls (based on
Analog Devices proprietary algorithms); contact local Analog
Devices field engineers for more information.
NSFSEL[1:0], Split Filter Selection NTSC, Address 0x19
[3:2]
The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A narrow split filter selection
results in better performance on diagonal lines, but more dot
crawl in the final output image. The opposite is true for selecting
a wide bandwidth split filter.
Table 49. NSFSEL Function
NSFSEL[1:0]
Description
Narrow
00 (default)
01
10
11
Medium
Medium
Wide
CTAPSN[1:0] Chroma Comb Taps NTSC, Address 0x38 [7:6]
Table 50. CTAPSN Function
CTAPSN[1:0]
Description
00
Do not use
01
NTSC chroma comb adapts three lines (three taps) to two lines (two taps)
NTSC chroma comb adapts five lines (five taps) to three lines (three taps)
NTSC chroma comb adapts five lines (five taps) to four lines (four taps)
10 (default)
11
CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38 [5:3]
Table 51. CCMN Function
CCMN[2:0]
Description
Configuration
0xx (default)
Adaptive comb mode
Adaptive 3-line chroma comb for CTAPSN = 01
Adaptive 4-line chroma comb for CTAPSN = 10
Adaptive 5-line chroma comb for CTAPSN = 11
100
101
Disable chroma comb
Fixed chroma comb (top lines of line memory)
Fixed 2-line chroma comb for CTAPSN = 01
Fixed 3-line chroma comb for CTAPSN = 10
Fixed 4-line chroma comb for CTAPSN = 11
Fixed 3-line chroma comb for CTAPSN = 01
Fixed 4-line chroma comb for CTAPSN = 10
Fixed 5-line chroma comb for CTAPSN = 11
Fixed 2-line chroma comb for CTAPSN = 01
Fixed 3-line chroma comb for CTAPSN = 10
Fixed 4-line chroma comb for CTAPSN = 11
110
111
Fixed chroma comb (all lines of line memory)
Fixed chroma comb (bottom lines of line memory)
Rev. A | Page 38 of 112
ADV7180
YCMN[2:0], Luma Comb Mode NTSC, Address 0x38 [2:0]
Table 52. YCMN Function
CCMP[2:0], Chroma Comb Mode PAL, Address 0x39 [5:3]
Table 55. CCMP Function
YCMN[2:0] Description
Configuration
CCMP[2:0] Description
Configuration
0xx
(default)
Adaptive comb mode
Adaptive 3-line (three
taps) luma comb
0xx
(default)
Adaptive comb
mode
Adaptive 3-line chroma
comb for CTAPSP = 01
100
Disable luma comb
Use low-pass/notch
filter; see the Y Shaping
Filter section
Fixed 2-line (two taps)
luma comb
Fixed 3-line (three taps)
luma comb
Fixed 2-line (two taps)
luma comb
Adaptive 4-line chroma
comb for CTAPSP = 10
Adaptive 5-line chroma
comb for CTAPSP = 11
101
110
111
Fixed luma comb (top
lines of line memory)
Fixed luma comb (all
lines of line memory)
Fixed luma comb
(bottom lines of line
memory)
100
101
Disable chroma
comb
Fixed chroma comb
(top lines of line
memory)
Fixed 2-line chroma
comb for CTAPSP = 01
Fixed 3-line chroma
comb for CTAPSP = 10
Fixed 4-line chroma
comb for CTAPSP = 11
Fixed 3-line chroma
comb for CTAPSP = 01
Fixed 4-line chroma
comb for CTAPSP = 10
Fixed 5-line chroma
comb for CTAPSP = 11
Fixed 2-line chroma
comb for CTAPSP = 01
Fixed 3-line chroma
comb for CTAPSP = 10
PAL Comb Filter Settings
Used for PAL B/G/H/I/D, PAL M, PAL Combinational N,
PAL 60, and NTSC 4.43 CVBS inputs.
110
111
Fixed chroma comb
(all lines of line
memory)
PSFSEL[1:0], Split Filter Selection PAL, Address 0x19 [1:0]
The PSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
eliminates dot crawl, but shows imperfections on diagonal lines.
The opposite is true for selecting a narrow bandwidth split filter.
Fixed chroma comb
(bottom lines of line
memory)
Table 53. PSFSEL Function
PSFSEL[1:0] Description
Fixed 4-line chroma
comb for CTAPSP = 11
00
Narrow
Medium
Wide
01 (default)
10
11
YCMP[2:0], Luma Comb Mode PAL, Address 0x39 [2:0]
Table 56. YCMP Function
Widest
YCMP[2:0] Description
Configuration
CTAPSP[1:0], Chroma Comb Taps PAL, Address 0x39 [7:6]
0xx
(default)
Adaptive comb mode Adaptive five lines (three
taps) luma comb
Table 54. CTAPSP Function
CTAPSP[1:0] Description
100
101
110
111
Disable luma comb
Use low-pass/notch filter;
see the Y Shaping Filter
section.
Fixed three lines (two taps)
luma comb
00
01
Do not use
PAL chroma comb adapts five lines (three taps)
to three lines (two taps); cancels cross luma only
Fixed luma comb
(top lines of line
memory)
Fixed luma comb
(all lines of line
memory)
Fixed luma comb
(bottom lines of line
memory)
10
PAL chroma comb adapts five lines (five taps) to
three lines (three taps); cancels cross luma and
hue error less well
Fixed five lines (three taps)
luma comb
11 (default)
PAL chroma comb adapts five lines (five taps) to
four lines (four taps); cancels cross luma and hue
error well
Fixed three lines (two taps)
luma comb
Rev. A | Page 39 of 112
ADV7180
IF COMP FILTERS NTSC ZOOMED AROUND FSC
IF FILTER COMPENSATION
IFFILTSEL[2:0], IF Filter Select, Address 0xF8 [2:0]
6
4
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input, as would be
observed on tuner outputs. Figure 29 and Figure 30 show IF
filter compensation for NTSC and PAL, respectively.
2
0
–2
–4
–6
–8
–10
–12
The options for this feature are as follows:
•
•
•
Bypass mode
NTSC—consists of three filter characteristics
PAL—consists of three filter characteristics
2.0
2.5
3.0
3.5
4.0
4.5
5.0
See Table 103 for programming details.
FREQUENCY (MHz)
Figure 29. NTSC IF Filter Compensation
IF COMP FILTERS PAL ZOOMED AROUND FSC
6
4
2
0
–2
–4
–6
–8
3.0
3.5
4.0
4.5
5.0
5.5
6.0
FREQUENCY (MHz)
Figure 30. PAL IF Filter Compensation
Rev. A | Page 40 of 112
ADV7180
AV CODE INSERTION AND CONTROLS
This section describes the I2C-based controls that affect
In this output interface mode, the following assignment takes
place: Cb = FF, Y = 00, Cr = 00, and Y = AV.
•
•
•
Insertion of AV codes into the data stream
In a 16-bit output interface (ADV7180 LQFP-64 only) where Y
and Cr/Cb are delivered via separate data buses, the AV code is
spread over the whole 16 bits. The SD_DUP_AV bit allows the
user to replicate the AV codes on both buses, so the full AV
sequence can be found on the Y bus as well as on the Cr/Cb bus
(see Figure 31).
Data blanking during the vertical blank interval (VBI)
The range of data values permitted in the output data
stream
•
The relative delay of luma vs. chroma signals
Note that some of the decoded VBI data is inserted during the
horizontal blanking interval. See the Gemstar Data Recovery
section for more information.
When SD_DUP_AV is 0 (default), the AV codes are in single
fashion (to suit 8-bit interleaved data output).
When SD_DUP_AV is 1, the AV codes are duplicated (for
16-bit interfaces).
BT.656-4, ITU-R BT.656-4 Enable, Address 0x04 [7]
Between Revision 3 and Revision 4 of the ITU-R BT.656 standards,
the ITU has changed the toggling position for the V bit within
the SAV EAV codes for NTSC. The ITU-R BT.656-4 standard
bit allows the user to select an output mode that is compliant
with either the previous or new standard. For further information,
visit the International Telecommunication Union’s website.
VBI_EN, Vertical Blanking Interval Data Enable,
Address 0x03 [7]
The VBI enable bit allows data such as intercast and closed
caption data to be passed through the luma channel of the
decoder with a minimal amount of filtering. All data for Line 1
to Line 21 is passed through and available at the output port.
The ADV7180 does not blank the luma data and automatically
switches all filters along the luma data path into their widest
bandwidth. For active video, the filter settings for YSH and YPK
are restored.
Note that the standard change only affects NTSC and has no
bearing on PAL.
When ITU-R BT.656-4 is 0 (default), the ITU-R BT.656-3
specification is used. The V bit goes low at EAV of Line 10
and Line 273.
See the BL_C_VBI, Blank Chroma During VBI, Address 0x04
[2] section for information on the chroma path.
When ITU-R BT.656-4 is 1, the ITU-R BT.656-4 specification is
used. The V bit goes low at EAV of Line 20 and Line 283.
When VBI_EN is 0 (default), all video lines are filtered/scaled.
SD_DUP_AV, Duplicate AV Codes, Address 0x03 [0]
When VBI_EN is 1, only the active video region is
filtered/scaled.
Depending on the output interface width, it may be necessary to
duplicate the AV codes from the luma path into the chroma path.
In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data),
the AV codes are defined as FF/00/00/AV, with AV being the
transmitted word that contains information about H/V/F.
SD_DUP_AV = 1
SD_DUP_AV = 0
16-BIT INTERFACE
16-BIT INTERFACE
8-BIT INTERFACE
Y DATA BUS
FF
FF
00
00
AV
AV
Y
00
AV
Y
Cb/Y/Cr/Y
INTERLEAVED
FF
00
00 AV Cb
Cr/Cb DATA BUS
00
00
Cb
FF
00
Cb
AV CODE SECTION
AV CODE SECTION
AV CODE SECTION
Figure 31. AV Code Duplication Control (ADV7180 LQFP-64 Only)
Rev. A | Page 41 of 112
ADV7180
When AUTO_PDC_EN is 1 (default), the ADV7180 automati-
cally determines the LTA and CTA values to have luma and
chroma aligned at the output.
BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2]
Setting BL_C_VBI high, blanks the Cr and Cb values of all VBI
lines. This is done so any data that may arrive during VBI is not
decoded as color and is output through Cr and Cb. As a result,
it is possible to send VBI lines into the decoder, and then output
them through an encoder again, undistorted. Without this
blanking, any color that is incorrectly decoded would be
encoded by the video encoder, thus distorting the VBI lines.
LTA[1:0], Luma Timing Adjust, Address 0x27 [1:0]
The luma timing adjust register allows the user to specify a
timing difference between chroma and luma samples.
Note that there is a certain functionality overlap with the
CTA[2:0] register. For manual programming, use the
following defaults:
Setting BL_C_VBI to 0 decodes and outputs color during VBI.
Setting BL_C_VBI to 1 (default) blanks Cr and Cb values
during VBI.
•
•
•
CVBS input LTA[1:0] = 00
Y/C input LTA[1:0] = 01
YPrPb input LTA[1:0] = 01
RANGE, Range Selection, Address 0x04 [0]
AV codes (as per ITU-R BT.656, formerly known as CCIR-656)
consist of a fixed header made up of 0xFF and 0x00 values.
These two values are reserved and therefore are not to be used
for active video. Additionally, the ITU specifies that the
nominal range for video should be restricted to values between
16 to 235 for luma and 16 to 240 for chroma.
Table 58. LTA Function
LTA[1:0]
Description
00 (default)
No delay
01
10
11
Luma 1 clock (37 ns) late
Luma 2 clock (74 ns) early
Luma 1 clock (37 ns) early
The RANGE bit allows the user to limit the range of values
output by the ADV7180 to the recommended value range. In
any case, it ensures that the reserved values of 255d (0xFF) and
00d (0x00) are not presented on the output pins unless they are
part of an AV code header.
CTA[2:0], Chroma Timing Adjust, Address 0x27 [5:3]
The chroma timing adjust register allows the user to specify a
timing difference between chroma and luma samples. This may
be used to compensate for external filter group delay differences
in the luma vs. chroma path and to allow a different number of
pipeline delays while processing the video downstream. Review
this functionality together with the LTA[1:0] register.
Table 57. RANGE Function
RANGE
Description
16 ≤ Y ≤ 235
1 ≤ Y ≤ 254
0
16 ≤ C/P ≤ 240
1 ≤ C/P ≤ 254
1 (default)
The chroma can be delayed or advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where one can
no longer delay by luma pixel steps.
AUTO_PDC_EN, Automatic Programmed Delay Control,
Address 0x27 [6]
Enabling AUTO_PDC_EN activates a function within the
ADV7180 that automatically programs the LTA[1:0] and
CTA[2:0] to have the chroma and luma data match delays for
all modes of operation. If set, manual registers LTA[1:0] and
CTA[2:0] are not used. If the automatic mode is disabled (by
setting the AUTO_PDC_EN bit to 0), the values programmed
into LTA[1:0] and CTA[2:0] registers become active.
For manual programming, use the following defaults:
•
•
•
CVBS input CTA[2:0] = 011
Y/C input CTA[2:0] = 101
YPrPb input CTA[2:0] = 110
Table 59. CTA Function
When AUTO_PDC_EN is 0, the ADV7180 uses the LTA[1:0] and
CTA[2:0] values for delaying luma and chroma samples. Refer to
the LTA[1:0], Luma Timing Adjust, Address 0x27 [1:0] section
and the CTA[2:0], Chroma Timing Adjust, Address 0x27 [5:3]
section.
CTA[2:0]
Description
000
001
010
011 (default)
100
101
110
111
Not used
Chroma + 2 chroma pixel (early)
Chroma + 1 chroma pixel (early)
No delay
Chroma – 1 chroma pixel (late)
Chroma – 2 chroma pixel (late)
Chroma – 3 chroma pixel (late)
Not used
Rev. A | Page 42 of 112
ADV7180
HSE[10:0], HS End, Address 0x34 [2:0], Address 0x36 [7:0]
SYNCHRONIZATION OUTPUT SIGNALS
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 32). HSE is set to
00000000000b, which is 0 LLC1 clock cycles from count [0].
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
•
•
•
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
The default value of HSE[10:0] is 000, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.
The HS begin (HSB) and HS end (HSE) registers allow the user
to freely position the HS output (pin) within the video line. The
values in HSB[10:0] and HSE[10:0] are measured in pixel units
from the falling edge of HS. Using both values, the user can
program both the position and length of the HS output signal.
For example,
•
To shift the HS toward active video by 20 LLC1s, add
20 LLC1s to both HSB and HSE—that is,
HSB[10:0] = [00000010110], HSE[10:0] = [00000010100].
•
To shift the HS away from active video by 20 LLC1s, add
1696 LLC1s to both HSB and HSE (for NTSC)—that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
Therefore, 1696 is derived from the NTSC total number of
pixels, 1716.
HSB[10:0], HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 32). HSB is set to
00000000010b, which is two LLC1 clock cycles from count [0].
•
To move 20 LLC1s away from active video, subtract 20 from
1716 and add the result in binary to both HSB[10:0] and
HSE[10:0].
The default value of HSB[10:0] is 0x002, indicating that the HS
pulse starts two pixels after the falling edge of HS.
PHS, Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active high.
When PHS is 1, HS is active low.
Table 60. HS Timing Parameters (See Figure 32)
Characteristic
HS to Active Video
LLC1 Clock Cycles,
C in Figure 32 (Default)
Active Video
Samples/Line,
D in Figure 32
Total LLC1
Clock Cycles,
E in Figure 32
HS Begin Adjust
HSB[10:0] (Default)
HS End Adjust
HSE[10:0] (Default)
Standard
NTSC
00000000010b
00000000000b
00000000000b
00000000000b
272
276
284
720Y + 720C = 1440
640Y + 640C = 1280
720Y + 720C = 1440
1716
1560
1728
NTSC Square Pixel 00000000010b
PAL 00000000010b
Figure 32. HS Timing
Rev. A | Page 43 of 112
ADV7180
VS and FIELD Configuration
HVSTIM, Horizontal VS Timing, Address 0x31 [3]
The following controls allow the user to configure the behavior
of the VS and FIELD output pins, as well as the generation of
embedded AV codes.
The HVSTIM bit allows the user to select where the VS signal is
asserted within a line of video. Some interface circuitry may
require VS to go low while HS is low.
Note that the ADV7180 LQFP-64 has separate VS and FIELD pins.
The ADV7180 LFCSP-40 does not have separate VS and FIELD
pins, but can output either one on Pin 37, the VS/FIELD pin.
When HVSTIM is 0 (default), the start of the line is relative to
HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
VSYNC/FIELD SELECT, Address 0x58 [0]
VSBHO, VS Begin Horizontal Position Odd, Address 0x32 [7]
This feature is used for the ADV7180 LFCSP-40 (ADV7180BCPZ)
only. The polarity of this bit determines what signal appears on
the VS/FIELD pin.
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When this bit is set to 0 (default), the FIELD signal is output.
When this bit is set to 1, the VSYNC signal is output.
When VSBHO is 0 (default), the VS pin goes high at the middle
of a line of video (odd field).
The ADV7180 LQFP-64 (ADV7180BSTZ) has dedicated FIELD
and VSYNC pins.
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
ADV encoder-compatible signals via NEWAVMODE are
VSBHE, VS Begin Horizontal Position Even, Address 0x32 [6]
•
•
•
•
PVS, PF
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
When VSBHE is 0 (default), the VS pin goes high at the middle
of a line of video (even field).
For NTSC control,
•
•
NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0]
When VSBHE is 1, the VS pin changes state at the start of a line
(even field).
NVENDDELO, NVENDDELE, NVENDSIGN,
NVEND[4:0]
VSEHO, VS End Horizontal Position Odd, Address 0x33 [7]
•
NFTOGDELO, NFTOGDELE, NFTOGSIGN,
NFTOG[4:0]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
For PAL control,
•
•
•
PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0]
When VSEHO is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (odd field).
PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]
When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).
NEWAVMODE, New AV Mode, Address 0x31 [4]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit Analog Devices encoders. No adjustments are possible.
VSEHE, VS End Horizontal Position Even, Address 0x33 [6]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
Setting NEWAVMODE to 1 (default) enables the manual position
of the VSYNC, FIELD, and AV codes using Register 0x34 to
Register 0x37 and Register 0xE5 to Register 0xEA. Default register
settings are CCIR656 compliant; see Figure 33 for NTSC and
Figure 38 for PAL. For recommended manual user settings,
see Table 61 and Figure 34 for NTSC and Table 62 and Figure 39
for PAL.
When VSEHE is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (even field).
When VSEHE is 1, the VS pin changes state at the start of a line
(even field).
Rev. A | Page 44 of 112
ADV7180
PVS, Polarity VS, Address 0x37 [5]
Table 61. User Settings for NTSC (See Figure 34)
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high.
When PVS is 1, VS is active low.
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE5
0xE6
0xE7
Register Name
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
VS/FIELD Control 1
VS/FIELD Control 2
VS/FIELD Control 3
HS Position Control 1
HS Position Control 2
HS Position Control 3
Polarity
PF, Polarity FIELD, Address 0x37 [3]
The polarity of the FIELD pin can be inverted using the PF bit.
The FIELD pin can be inverted using the PF bit.
When PF is 0 (default), FIELD is active high.
When PF is 1, FIELD is active low.
NTSV V Bit Begin
NTSC V Bit End
NTSC F Bit Toggle
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
19
20
21
22
OUTPUT
VIDEO
H
V
1
NVBEG[4:0] = 0x5
NVEND[4:0] = 0x4
BT.656-4
REG 0x04, BIT 7 = 1
F
NFTOG[4:0] = 0x3
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275 276
283
284
285
OUTPUT
VIDEO
H
V
1
BT.656-4
REG 0x04, BIT 7 = 1
NVBEG[4:0] = 0x5
NVEND[4:0] = 0x4
F
NFTOG[4:0] = 0x3
APPLIES IF NEWAVMODE = 0:
1
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 33. NTSC Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
NVBEG[4:0] = 0x0
NVEND[4:0] = 0x3
OUTPUT
NFTOG[4:0] = 0x5
FIELD 2
267
262
263
264
265
266
268
269
270
271
272
273
274
275
276 277
284
285
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVBEG[4:0] = 0x0
NVEND[4:0] = 0x3
FIELD
OUTPUT
NFTOG[4:0] = 0x5
Figure 34. NTSC Typical VSYNC/FIELD Positions Using Register Writes in Table 61
Rev. A | Page 45 of 112
ADV7180
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC on the VS pin are modified.
NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field,
Address 0xE5 [7]
When NVBEGDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1 delays VSYNC going high on an odd
field by a line relative to NVBEG.
1
NVENDSIGN
0
ADVANCE END OF
VSYNC BY NVEND[4:0]
DELAY END OF VSYNC
BY NVEND[4:0]
1
NVBEGSIGN
0
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
YES
NO
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
YES
NO
NVENDDELO
1
NVENDDELE
1
0
0
NVBEGDELO
1
NVBEGDELE
1
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
0
0
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
VSEHO
1
VSEHE
1
0
0
VSBHO
1
VSBHE
1
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
0
0
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
VSYNC END
Figure 36. NTSC Vsync End
VSYNC BEGIN
NVENDDELO, NTSC Vsync End Delay on Odd Field,
Address 0xE6 [7]
Figure 35. NTSC Vsync Begin
When NVENDDELO is 0 (default), there is no delay.
NVBEGDELE, NTSC Vsync Begin Delay on Even Field,
Address 0xE5 [6]
Setting NVENDDELO to 1 delays vsync from going low on an
odd field by a line relative to NVEND.
When NVBEGDELE is 0 (default), there is no delay.
NVENDDELE, NTSC Vsync End Delay on Even Field,
Address 0xE6 [6]
Setting NVBEGDELE to 1 delays vsync going high on an even
field by a line relative to NVBEG.
When NVENDDELE is set to 0 (default), there is no delay.
NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]
Setting NVENDDELE to 1 delays vsync from going low on an
even field by a line relative to NVEND.
Setting NVBEGSIGN to 0 delays the start of vsync. Set for user
manual programming.
NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]
Setting NVBEGSIGN to 1 (default) advances the start of vsync.
Not recommended for user programming.
Setting NVENDSIGN to 0 (default) delays the end of vsync.
Set for user manual programming.
NVBEG[4:0], NTSC Vsync Begin, Address 0xE5 [4:0]
Setting NVENDSIGN to 1 advances the end of vsync. Not
recommended for user programming.
The default value of NVBEG is 00101, indicating the NTSC
vsync begin position.
Rev. A | Page 46 of 112
ADV7180
NVEND[4:0], NTSC Vsync End, Address 0xE6 [4:0]
NFTOG[4:0], NTSC Field Toggle, Address 0xE7 [4:0]
The default value of NVEND is 00100, indicating the NTSC
vsync end position.
The default value of NFTOG is 00011, indicating the NTSC
field toggle position.
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
For all NTSC/PAL field timing controls, both the F bit in the
AV code and the field signal on the FIELD/DE pin are modified.
NFTOGDELO, NTSC FIELD Toggle Delay on Odd Field,
Address 0xE7 [7]
1
NFTOGSIGN
0
When NFTOGDELO is 0 (default), there is no delay.
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
Setting NFTOGDELO to 1 delays the field toggle/transition on
an odd field by a line relative to NFTOG.
NOT VALID FOR USER
PROGRAMMING
NFTOGDELE, NTSC Field Toggle Delay on Even Field,
Address 0xE7 [6]
ODD FIELD?
YES
NO
When NFTOGDELE is 0, there is no delay.
Setting NFTOGDELE to 1 (default) delays the field toggle/
transition on an even field by a line relative to NFTOG.
NFTOGDELO
1
NFTOGDELE
1
NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]
0
0
Setting NFTOGSIGN to 0 delays the field transition. Set for
user manual programming.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
Setting NFTOGSIGN to 1 (default) advances the field
transition. Not recommended for user programming.
FIELD
TOGGLE
Figure 37. NTSC FIELD Toggle
FIELD 1
622
623
624
625
1
2
3
4
5
6
7
8
9
10
22
23
24
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
PVEND[4:0] = 0x4
F
PFTOG[4:0] = 0x3
FIELD 2
314
310
311
312
313
315
316
317
318
319
320
321 322
335
336
337
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
PVEND[4:0] = 0x4
F
PFTOG[4:0] = 0x3
Figure 38. PAL Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)
Rev. A | Page 47 of 112
ADV7180
FIELD 1
1
622
623 624
2
3
4
5
6
7
8
9
10
11
23
24
625
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
FIELD
OUTPUT
PFTOG[4:0] = 0x6
FIELD 2
314
310
311
312
315
316
317
318
319
320
321
322
323
336
337
313
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
FIELD
OUTPUT
PFTOG[4:0] = 0x6
Figure 39. PAL Typical VS/FIELD Positions Using Register Writes Shown in Table 62
PVBEG[4:0], PAL Vsync Begin, Address 0xE8 [4:0]
Table 62. User Settings for PAL
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
Register Name
VS/FIELD Control 1
VS/FIELD Control 2
VS/FIELD Control 3
HS Position Control 1
HS Position Control 2
HS Position Control 3
Polarity
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
The default value of PVBEG is 00101, indicating the PAL vsync
begin position. For all NTSC/PAL vsync timing controls, the
V bit in the AV code and the vsync on the VS pin are modified.
1
PVBEGSIGN
0
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
PAL V Bit Begin
NOT VALID FOR USER
PROGRAMMING
PAL V Bit End
ODD FIELD?
PAL F Bit Toggle
YES
NO
PVBEGDELO, PAL Vsync Begin Delay on Odd Field,
Address 0xE8 [7]
PVBEGDELO
1
PVBEGDELE
1
When PVBEGDELO is 0 (default), there is no delay.
0
0
Setting PVBEGDELO to 1 delays vsync going high on an odd
field by a line relative to PVBEG.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
PVBEGDELE PAL, Vsync Begin Delay on Even Field,
Address 0xE8 [6]
When PVBEGDELE is 0, there is no delay.
VSBHO
1
VSBHE
1
Setting PVBEGDELE to 1 (default) delays vsync going high on
an even field by a line relative to PVBEG.
0
0
PVBEGSIGN PAL, Vsync Begin Sign, Address 0xE8 [5]
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
Setting PVBEGSIGN to 0 delays the beginning of vsync. Set for
user manual programming.
Setting PVBEGSIGN to 1(default) advances the beginning of
vsync. Not recommended for user programming.
VSYNC BEGIN
Figure 40. PAL Vsync Begin
Rev. A | Page 48 of 112
ADV7180
PFTOGDELO, PAL Field Toggle Delay on Odd Field,
Address 0xEA [7]
1
PVENDSIGN
0
When PFTOGDELO is 0 (default), there is no delay.
ADVANCE END OF
DELAY END OF VSYNC
BY PVEND[4:0]
VSYNC BY PVEND[4:0]
Setting PFTOGDELO to 1 delays the F toggle/transition on an
odd field by a line relative to PFTOG.
NOT VALID FOR USER
PROGRAMMING
PFTOGDELE, PAL Field Toggle Delay on Even Field,
Address 0xEA [6]
ODD FIELD?
YES
NO
When PFTOGDELE is 0, there is no delay.
Setting PFTOGDELE to 1 (default) delays the F toggle/transition
on an even field by a line relative to PFTOG.
PVENDDELO
1
PVENDDELE
1
PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]
0
0
Setting PFTOGSIGN to 0 delays the field transition. Set for user
manual programming.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
Setting PFTOGSIGN to 1 (default) advances the field transition.
Not recommended for user programming.
PFTOG, PAL Field Toggle, Address 0xEA [4:0]
VSEHO
1
VSEHE
1
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
0
0
For all NTSC/PAL field timing controls, the F bit in the AV
code and the field signal on the FIELD/DE pin are modified.
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
1
PFTOGSIGN
0
VSYNC END
ADVANCE TOGGLE OF
FIELD BY PFTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
Figure 41. PAL Vsync End
PVENDDELO, PAL Vsync End Delay on Odd Field,
Address 0xE9 [7]
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
When PVENDDELO is 0 (default), there is no delay.
YES
NO
Setting PVENDDELO to 1 delays vsync going low on an odd
field by a line relative to PVEND.
PFTOGDELO
1
PFTOGDELE
1
PVENDDELE, PAL Vsync End Delay on Even Field,
Address 0xE9 [6]
0
0
When PVENDDELE is 0 (default), there is no delay.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
Setting PVENDDELE to 1 delays vsync going low on an even
field by a line relative to PVEND.
PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]
Setting PVENDSIGN to 0 (default) delays the end of vsync. Set
for user manual programming.
FIELD
TOGGLE
Figure 42. PAL F Toggle
Setting PVENDSIGN to 1 advances the end of vsync. Not
recommended for user programming.
PVEND[4:0], PAL Vsync End, Address 0xE9 [4:0]
The default value of PVEND is 10100, indicating the PAL vsync
end position.
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
Rev. A | Page 49 of 112
ADV7180
SYNC PROCESSING
Table 64. NTSC
The ADV7180 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits.
Feature
Standard
Teletext System B and D
Teletext System C/NABTS
Vertical Interval Time Codes (VITC )
ITU-R BT.653
ITU-R BT.653/EIA-516
–
Copy Generation Management
System (CGMS)
EIA-J CPR-1204/IEC 61880
ENHSPLL, Enable Hsync Processor, Address 0x01 [6]
The HSYNC processor is designed to filter incoming hsyncs
that have been corrupted by noise, providing improved per-
formance for video signals with stable time bases but poor SNR.
Gemstar
Closed Captioning (CCAP)
–
EIA-608
Setting ENHSPLL to 0 disables the hsync processor.
The VBI data standard that the VDP decodes on a particular
line of incoming video has been set by default as described in
Table 65. This can be overridden manually and any VBI data
can be decoded on any line. The details of manual
programming are described in Table 66.
Setting ENHSPLL to 1 (default) enables the hsync processor.
ENVSPROC, Enable Vsync Processor, Address 0x01 [3]
This block provides extra filtering of the detected vsyncs to
improve vertical lock.
VDP Default Configuration
Setting ENVSPROC to 0 disables the vsync processor.
Setting ENVSPROC to 1(default) enables the vsync processor.
VBI DATA DECODE
The VDP can decode different VBI data standards on a line-to-
line basis. The various standards supported by default on
different lines of VBI are explained in Table 65.
VDP Manual Configuration
There are two VBI data slicers on the ADV7180. The first is
called the VBI data processor (VDP), and the second is called
VBI System 2.
MAN_LINE_PGM, Enable Manual Line Programming of
VBI Standards, Address 0x64 [7], User Sub Map
The user can configure the VDP to decode different standards on
a line-to-line basis through manual line programming. For this,
the user has to set the MAN_LINE_PGM bit. The user needs to
write into all the line programming registers VBI_DATA_Px_Ny
(see Register 0x64 to Register 0x77 in Table 104).
The VDP can slice both low bandwidth standards and high
bandwidth standards such as teletext. VBI System 2 can slice
low data rate VBI standards only.
The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in output 656 data stream. For low data rate VBI standards
like CC/WSS/CGMS, users can read the decoded data bytes
from I2C registers.
0 (default)—The VDP decodes default standards on lines, as
shown in Table 65.
1—VBI standards to be decoded are manually programmed.
VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on
Line X for PAL, Line Y for NTSC, Addresses 0x64 to 0x77,
User Sub Map
The VBI data standards that can be decoded by the VDP are
listed in Table 63 and Table 64.
Table 63. PAL
Feature
These are related 4-bit clusters in Register 0x64 to Register 0x77
of the User Sub Map. These 4-bit, line programming registers,
named VBI_DATA_Px_Ny, identify the VBI data standard that
would be decoded on Line X in PAL or on Line Y in NTSC
mode. The different types of VBI standards decoded by
Standard
Teletext System A, C, or D
Teletext System B/WST
Video Programming System (VPS)
Vertical Interval Time Codes ( VITC)
Wide Screen Signaling (WSS)
ITU-R BT.653
ITU-R BT.653
ETSI EN 300 231 V 1.3.1
–
ITU-R BT.1119-1/
ETSI EN.300294
VBI_DATA_Px_Ny are shown in Table 66. Note that the X or Y
value depends on whether the ADV7180 is in PAL or NTSC mode.
Closed Captioning (CCAP)
–
Rev. A | Page 50 of 112
ADV7180
Table 65. Default Standards on Lines for PAL and NTSC
PAL—625/50
NTSC—525/60
Default VBI
Default VBI
DATA Decoded Line No.
Default VBI
DATA Decoded Line No.
Default VBI
DATA Decoded
Line No.
6
DATA Decoded
Gemstar_1×
Gemstar_1×
Gemstar_1×
–
Line No.
WST
WST
WST
WST
WST
WST
WST
WST
WST
WST
VPS
-
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
VPS
WST
WST
WST
WST
WST
WST
WST
WST
WST
WST
VPS
-
23
24
25
–
–
–
10
11
12
13
14
15
16
17
18
19
20
21
–
–
7
8
9
286
287
288
–
Gemstar_1×
Gemstar_1×
Gemstar_1×
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
–
–
–
–
NABTS
NABTS
NABTS
NABTS
VITC
NABTS
VITC
NABTS
NABTS
NABTS
CGMS
272
273
274
275
276
277
278
279
280
281
282
283
284
NABTS
NABTS
NABTS
NABTS
NABTS
VITC
-
NABTS
VITC
VITC
WST
WST
CCAP
WSS
WST
-
VITC
WST
WST
CCAP
WST
NABTS
NABTS
NABTS
CGMS
CCAP
CCAP
NABTS
24 + full
22 + full
odd field
odd field
337 + full
even field
WST
285 + full
even field
NABTS
Table 66. VBI Data Standards for Manual Configuration
VBI_DATA_Px_Ny
625/50—PAL
525/60—NTSC
0000
Disable VDP
Disable VDP
0001
Teletext system identified by VDP_TTXT_TYPE
Teletext system identified by VDP_TTXT_TYPE
0010
VPS – ETSI EN 300 231 V 1.3.1
Reserved
0011
VITC
VITC
0100
0101
0110
0111
WSS ITU-R BT.1119-1/ETSI.EN.300294
CGMS EIA-J CPR-1204/IEC 61880
Gemstar_1×
Gemstar_2×
CCAP EIA-608
Reserved
Reserved
Reserved
CCAP
1000 to 1111
Reserved
Rev. A | Page 51 of 112
ADV7180
Table 67.VBI Data Standards to be Decoded on Line Px (PAL) or Line Ny (NTSC)
Signal Name
Register Location
VDP_LINE_00F[7:4]
VDP_LINE_010[7:4]
VDP_LINE_011[7:4]
VDP_LINE_012[7:4]
VDP_LINE_013[7:4]
VDP_LINE_014[7:4]
VDP_LINE_015[7:4]
VDP_LINE_016[7:4]
VDP_LINE_017[7:4]
VDP_LINE_018[7:4]
VDP_LINE_019[7:4]
VDP_LINE_01A[7:4]
VDP_LINE_01B[7:4]
VDP_LINE_01C[7:4]
VDP_LINE_01D[7:4]
VDP_LINE_01E[7:4]
VDP_LINE_01F[7:4]
VDP_LINE_020[7:4]
VDP_LINE_021[7:4]
VDP_LINE_00E[3:0]
VDP_LINE_00F[3:0]
VDP_LINE_010[3:0]
VDP_LINE_011[3:0]
VDP_LINE_012[3:0]
VDP_LINE_013[3:0]
VDP_LINE_014[3:0]
VDP_LINE_015[3:0]
VDP_LINE_016[3:0]
VDP_LINE_017[3:0]
VDP_LINE_018[3:0]
VDP_LINE_019[3:0]
VDP_LINE_01A[3:0]
VDP_LINE_01B[3:0]
VDP_LINE_01C[3:0]
VDP_LINE_01D[3:0]
VDP_LINE_01E[3:0]
VDP_LINE_01F[3:0]
VDP_LINE_020[3:0]
VDP_LINE_021[3:0]
Dec Address
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
Hex Address
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
VBI_DATA_P6_N23
VBI_DATA_P7_N24
VBI_DATA_P8_N25
VBI_DATA_P9
VBI_DATA_P10
VBI_DATA_P11
VBI_DATA_P12_N10
VBI_DATA_P13_N11
VBI_DATA_P14_N12
VBI_DATA_P15_N13
VBI_DATA_P16_N14
VBI_DATA_P17_N15
VBI_DATA_P18_N16
VBI_DATA_P19_N17
VBI_DATA_P20_N18
VBI_DATA_P21_N19
VBI_DATA_P22_N20
VBI_DATA_P23_N21
VBI_DATA_P24_N22
VBI_DATA_P318
VBI_DATA_P319_N286
VBI_DATA_P320_N287
VBI_DATA_P321_N288
VBI_DATA_P322
VBI_DATA_P323
VBI_DATA_P324_N272
VBI_DATA_P325_N273
VBI_DATA_P326_N274
VBI_DATA_P327_N275
VBI_DATA_P328_N276
VBI_DATA_P329_N277
VBI_DATA_P330_N278
VBI_DATA_P331_N279
VBI_DATA_P332_N280
VBI_DATA_P333_N281
VBI_DATA_P334_N282
VBI_DATA_P335_N283
VBI_DATA_P336_N284
VBI_DATA_P337_N285
Note that full field detection (lines other than VBI lines) of any standard can also be enabled by writing into the registers
VBI_DATA_P24_N22[3:0] and VBI_DATA_P337_N285[3:0]. So, if VBI_DATA_P24_N22[3:0] is programmed with any teletext
standard, then teletext is decoded off for the entire odd field. The corresponding register for the even field is VBI_DATA_P337_N285[3:0].
For teletext system identification, VDP assumes that if teletext is present in a video channel, all the teletext lines comply with a single
standard system. Thus, the line programming using VBI_DATA_Px_Ny registers identifies whether the data in line is teletext; the actual
standard is identified by the VDP_TTXT_TYPE_MAN bit. To program the VDP_TTXT_TYPE_MAN bit, the
VDP_TTXT_TYPE_MAN_ENABLE bit must be set to 1.
Rev. A | Page 52 of 112
ADV7180
The user may select the data identification word (DID) and the
secondary data identification word (SDID) through
programming the ADF_DID[4:0] and ADF_SDID[5:0] bits,
respectively, as explained in the following sections.
VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual
Selection of Teletext Type, Address 0x60 [2], User Sub Map
0 (default)—Manual programming of the teletext type is
disabled.
ADF_DID[4:0], User-Specified Data ID Word in Ancillary
Data, Address 0x62 [4:0], User Sub Map
1—Manual programming of the teletext type is enabled.
VDP_TTXT_TYPE_MAN[1:0], Specify the Teletext Type,
Address 0x60 [1:0], User Sub Map
This bit selects the data ID word to be inserted into the
ancillary data stream with the data decoded by the VDP.
These bits specify the teletext type to be decoded. These bits are
functional only if VDP_TTXT_TYPE_MAN_ENABLE is set to 1.
The default value of ADF_DID[4:0] is 10101.
ADF_SDID[5:0], User-Specified Secondary Data ID Word
in Ancillary Data, Address 0x63 [5:0], User Sub Map
Table 68. VDP_TTXT_TYPE_MAN Function
VDP_TTXT_
TYPE_MAN[1:0]
These bits select the secondary data ID word to be inserted in
the ancillary data stream with the data decoded by the VDP.
625/50 (PAL)
525/60 (NTSC)
00 (default)
Teletext-ITU-BT.653-
625/50-A
Reserved
The default value of ADF_SDID[5:0] is 101010.
01
10
Teletext-ITU-BT.653-
625/50-B (WST)
Teletext-ITU-BT.653-
625/50-C
Teletext-ITU-BT.653-
525/60-B
Teletext-ITU-BT.653-
525/60-C or EIA516
(NABTS)
DUPLICATE_ADF, Enable Duplication/Spreading of
Ancillary Data over Y and C Buses, Address 0x63 [7], User
Sub Map
This bit determines whether the ancillary data is duplicated
over both Y and C buses or if the data packets are spread
between the two channels.
11
Teletext-ITU-BT.653-
625/50-D
Teletext-ITU-BT.653-
525/60-D
VDP Ancillary Data Output
0 (default)—The ancillary data packet is spread across the Y and
C data streams.
Reading the data back via I2C may not be feasible for VBI data
standards with high data rates (for example, teletext). An
alternative is to place the sliced data in a packet in the line
blanking of the digital output CCIR656 stream. This is available
for all standards sliced by the VDP module.
1—The ancillary data packet is duplicated on the Y and C data
streams.
ADF_MODE[1:0], Determine the Ancillary Data Output
Mode, Address 0x62 [6:5], User Sub Map
When data has been sliced on a given line, the corresponding
ancillary data packet is placed immediately after the next EAV
code that occurs at the output (that is, data sliced from multiple
lines are not buffered up and then emitted in a burst). Note that,
due to the vertical delay through the comb filters, the line
number on which the packet is placed differs from the line
number on which the data was sliced.
These bits determine if the ancillary data output mode is in byte
mode or nibble mode.
Table 69.
ADF_MODE[1:0]
Description
00 (default)
Nibble mode
01
10
Byte mode, no code restrictions
The user can enable or disable the insertion of VDP decoded
results into the 656 ancillary streams by using the
ADF_ENABLE bit.
Byte mode, but 0x00 and 0xFF prevented
(0x00 replaced by 0x01, 0xFF replaced by
0xFE)
11
Reserved
ADF_ENABLE, Enable Ancillary Data Output Through
656 Stream, Address 0x62 [7], User Sub Map
0 (default)—Disables insertion of VBI decoded data into
ancillary 656 stream.
1—Enables insertion of VBI decoded data into ancillary 656
stream.
Rev. A | Page 53 of 112
ADV7180
The ancillary data packet sequence is explained in Table 70 and
Table 71. The nibble output mode is the default mode of output
from the ancillary stream when ancillary stream output is
enabled. This format is in compliance with ITU-R BT.1364.
EP
•
•
—The MSB, B9, is the inverse of EP. This ensures that
restricted Codes 0x00 and 0xFF do not occur.
Line_number[9:0]—The line number of the line that
immediately precedes the ancillary data packet. The line
number is from the numbering system in ITU-R BT.470.
The line number runs from 1 to 625 in a 625-line system
and from 1 to 263 in a 525-line system. Note that, due to
the vertical delay through the comb filters, the line number
on which the packet is output differs from the line number
on which the VBI data was sliced.
Data Count—The data count specifies the number of
UDWs in the ancillary stream for the standard. The total
number of user data-words is four times the data count.
Padding words may be introduced to make the total
number of UDWs divisible by 4.
These abbreviations are used in Table 70 and Table 71:
•
•
EP—Even parity for Bit B8 to Bit B2. This means that the
parity bit’s EP is set so that an even number of 1s are in
Bit B8 to Bit B2, including the parity bit, D8.
CS—Checksum word. The CS word is used to increase
confidence of the integrity of the ancillary data packet
from the DID, SDID, and DC through user data-words
(UDWs). It consists of 10 bits: a 9-bit calculated value and
B9 as the inverse of B8. The checksum value B8 to B0 is
equal to the nine LSBs of the sum of the nine LSBs of the
DID, SDID, and DC and all UDWs in the packet. Prior to
the start of the checksum count cycle, all checksum and
carry bits are preset to 0. Any carry resulting from the
checksum count cycle is ignored.
•
Table 70. Ancillary Data in Nibble Output Format
Byte
B9
B8
B7
B6
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
Description
0
1
2
0
0
0
0
Ancillary data preamble.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DID (data identification
word).
EP
EP
3
4
EP
EP
0
I2C_DID6_2[4:0]
0
0
0
0
SDID (secondary data
identification word).
I2C_SDID7_2[5:0]
DC[4:0]
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
.
5
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
.
0
0
0
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
0
0
0
0
0
.
Data count.
6
padding[1:0]
VBI_DATA_STD[3:0]
Line_number[9:5]
ID0 (User Data-Word 1).
ID1 (User Data-Word 2).
ID2 (User Data-Word 3).
ID3 (User Data-Word 4).
ID4 (User Data-Word 5).
ID5 (User Data-Word 6).
ID6 (User Data-Word 7).
ID7 (User Data-Word 8).
ID8 (User Data-Word 9).
7
8
Even_Field
Line_number[4:0]
9
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
VDP_TTXT_TYPE[1:0]
VBI_WORD_1[7:4]
10
11
12
13
14
.
VBI_WORD_1[3:0]
VBI_WORD_2[7:4]
VBI_WORD_2[3:0]
VBI_WORD_3[7:4]
.
.
.
.
Pad 0x200. These
.
.
.
.
.
.
.
.
.
.
.
padding words may be
present depending on
ancillary data type. User
data-word xx.
.
.
.
.
.
.
.
.
.
.
.
n − 3
n − 2
n − 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
B8
Checksum
CS (checksum word).
Rev. A | Page 54 of 112
ADV7180
Table 71. Ancillary Data in Byte Output Format1
Byte
B9
B8
B7
B6
B5
0
B4
0
B3
0
B2
0
B1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
B0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
Description
0
0
0
0
0
Ancillary data preamble.
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
3
EP
EP
EP
EP
EP
EP
EP
0
I2C_DID6_2[4:0]
I2C_SDID7_2[5:0]
DC[4:0]
DID.
EP
EP
EP
EP
EP
EP
EP
4
SDID.
5
0
Data count.
6
padding[1:0]
VBI_DATA_STD[3:0]
Line_number[9:5]
ID0 (User Data-Word 1).
ID1 (User Data-Word 2).
ID2 (User Data-Word 3).
ID3 (User Data-Word 4).
ID4 (User Data-Word 5).
ID5 (User Data-Word 6).
ID6 (User Data-Word 7).
ID7 (User Data-Word 8).
ID8 (User Data-Word 9).
7
0
8
Even_Field
0
Line_number[4:0]
9
0
0
0
VDP_TTXT_TYPE[1:0]
10
11
12
13
14
.
VBI_WORD_1[7:0]
VBI_WORD_2[7:0]
VBI_WORD_3[7:0]
VBI_WORD_4[7:0]
VBI_WORD_5[7:0]
.
.
.
.
.
.
.
.
Pad 0x200. These
.
.
.
.
.
.
.
.
.
.
.
padding words may be
present depending on
ancillary data type. User
data-word xx.
.
.
.
.
.
.
.
.
.
.
.
n − 3
n − 2
n − 1
1
1
B8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Checksum
CS (checksum word).
1 This mode does not fully comply with ITU-R BT.1364.
Table 73 shows the framing code and its valid length for VBI
data standards supported by VDP.
Structure of VBI Words in Ancillary Data Stream
Each VBI data standard has been split into a clock-run-in
(CRI), a framing code (FC), and a number of data bytes (n).
The data packet in the ancillary stream includes only the FC
and data bytes. Table 72 shows the format of the VBI_WORD_x
in the ancillary data stream.
Example
For teletext (B-WST), the framing code byte is 11100100
(0xE4), with bits shown in the order of transmission. For
VBI_WORD_1 = 0x27, VBI_WORD_2 = 0x00, and
VBI_WORD_3 = 0x00 translated into UDWs in the ancillary
data stream for nibble mode is as follows:
Table 72. Structure of VBI Data-Words in Ancillary Stream
Ancillary Data
UDW5 [5:2] = 0010
Byte Number
VBI_WORD_1
VBI_WORD_2
VBI_WORD_3
VBI_WORD_4
…
Byte Type
FC0
FC1
FC2
DB1
Description
UDW6 [5:2] = 0111
Framing code [23:16]
Framing code [15:8]
Framing code [7:0]
1st data byte
UDW7 [5:2] = 0000 (undefined bits set to 0)
UDW8 [5:2] = 0000 (undefined bits set to 0)
UDW9 [5:2] = 0000 (undefined bits set to 0)
UDW10 [5:2] = 0000 (undefined bits set to 0)
…
DBn
…
VBI_WORD_N + 3
Last (nth) data byte
VDP Framing Code
For byte mode:
UDW5 [9:2] = 0010_0111
The length of the actual framing code depends on the VBI data
standard. For uniformity, the length of the framing code
reported in the ancillary data stream is always 24 bits. For
standards with a smaller framing code length, the extra LSB bits
are set to 0. The valid length of the framing code can be
decoded from the VBI_DATA_STD bit available in ID0
(UDW 1). The framing code is always reported in the inverse-
transmission order.
UDW6 [9:2] = 0000_0000 (undefined bits set to 0)
UDW7 [9:2] = 0000_0000 (undefined bits set to 0)
Rev. A | Page 55 of 112
ADV7180
The data bytes in the ancillary data stream are as follows:
VBI_WORD_4 = Byte 1 [7:0]
Data Bytes
The VBI_WORD_4 to VBI_WORD_N + 3 contains the data-
words that were decoded by the VDP in the transmission order.
The position of bits in bytes is in the inverse transmission order.
VBI_WORD_5 = Byte 2 [7:0]
The number of VBI_WORDS for each VBI data standard and
the total number of UDWs in the ancillary data stream is shown
in Table 74.
For example, closed captioning has two user data bytes, as
shown in Table 78.
Table 73. Framing Code Sequence for Different VBI Standards
Error-Free Framing Code Bits
(In Order of Transmission)
Error-Free Framing Code Reported by VDP
(In Reverse Order of Transmission)
VBI Standard
Length in Bits
TTXT_SYSTEM_A (PAL)
TTXT_SYSTEM_B (PAL)
TTXT_SYSTEM_B (NTSC)
TTXT_SYSTEM_C (PAL and NTSC)
TTXT_SYSTEM_D (PAL and NTSC)
VPS (PAL)
VITC (NTSC and PAL)
WSS (PAL)
GEMSTAR_1× (NTSC)
GEMSTAR_2× (NTSC)
CCAP (NTSC and PAL)
CGMS (NTSC)
8
8
8
8
8
16
1
24
3
11
3
11100111
11100100
11100100
11100111
11100101
10001010100011001
0
000111100011110000011111
001
1001_1011_101
001
0
11100111
00100111
00100111
11100111
10100111
1001100101010001
0
111110000011110001111000
100
101_1101_1001
100
0
1
Table 74. Total User Data-Words for Different VBI Standards1
VBI Standard
ADF Mode
Framing Code UDWs VBI Data-Words No. of Padding Words Total UDWs
TTXT_SYSTEM_A (PAL)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
74
37
84
42
68
34
66
33
68
34
26
13
18
9
4
2
4
2
8
4
4
2
0
0
2
3
2
3
0
2
2
3
0
0
0
0
2
3
2
3
2
1
2
3
0
2
84
44
96
52
80
44
76
42
80
44
36
20
28
16
16
12
16
12
20
12
16
12
16
12
TTXT_SYSTEM_B (PAL)
TTXT_SYSTEM_B (NTSC)
TTXT_SYSTEM_C (PAL and NTSC) 00 (nibble mode)
01,10 (byte mode)
TTXT_SYSTEM_D (PAL and NTSC) 00 (nibble mode)
01,10 (byte mode)
VPS (PAL)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
00 (nibble mode)
01,10 (byte mode)
VITC (NTSC and PAL)
WSS (PAL)
GEMSTAR_1× (NTSC)
GEMSTAR_2× (NTSC)
CCAP (NTSC and PAL)
CGMS (NTSC)
6
3 + 3
1 The first four UDWs are always the ID.
Rev. A | Page 56 of 112
ADV7180
I2C Interface
to be notified only when there is a change in the information
content or loss of the information content. The user needs to
enable content-based updating for the required standard
through the GS_VPS_PDC_UTC_CB_CHANGE and
WSS_CGMS_CB_CHANGE bits. Therefore, the AVAILABLE
bit shows the availability of that standard only when its content
has changed.
Dedicated I2C readback registers are available for CCAP,
CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. Because
teletext is a high data rate standard, data extraction is supported
only through the ancillary data packet. The details of these
registers and their access procedure are described next.
User Interface for I2C Readback Registers
Content-based updating also applies to lines with lost data.
Therefore, for standards like VPS, Gemstar, CGMS, and WSS, if no
data arrives in the next four lines programmed, the corresponding
AVAILABLE bit in the VDP_STATUS register is set high and
the content in the I2C registers for that standard is set to 0. The
user has to write high to the corresponding CLEAR bit so that
when a valid line is decoded after some time, the decoded results
are available in the I2C registers, with the AVAILABLE status
bit set high.
The VDP decodes all enabled VBI data standards in real time.
Because the I2C access speed is much lower than the decoded
rate, when the registers are accessed, they may be updated with
data from the next line. To avoid this, VDP has a self-clearing
CLEAR bit and an AVAILABLE status bit accompanying all
I2C readback registers.
The user has to clear the I2C readback register by writing a high
to the CLEAR bit. This resets the state of the AVAILABLE bit to
low and indicates that the data in the associated readback
registers is not valid. After the VDP decodes the next line of the
corresponding VBI data, the decoded data is placed into the I2C
readback register and the AVAILABLE bit is set to high to
indicate that valid data is now available.
If content-based updating is enabled, the AVAILABLE bit is set
high (assuming the CLEAR bit was written) in the following cases:
•
•
The data contents have changed.
Data was being decoded and four lines with no data have
been detected.
Though the VDP decodes this VBI data in subsequent lines if
present, the decoded data is not updated to the readback
registers until the CLEAR bit is set high again. However, this
data is available through the 656 ancillary data packets.
•
No data was being decoded and new data is now being
decoded.
GS_VPS_PDC_UTC_CB_CHANGE, Enable Content-
Based Updating for Gemstar/VPS/PDC/UTC,
Address 0x9C [5], User Sub Map
The CLEAR and AVAILABLE bits are in the VDP_CLEAR
(0x78, User Sub Map, write only) and VDP_STATUS (0x78,
User Sub Map, read only) registers.
Example I2C Readback Procedure
The following tasks have to be performed to read one packet
(line) of PDC data from the decoder:
1. Write 10 to I2C_GS_VPS_PDC_UTC[1:0] (0x9C, User Sub
Map) to specify that PDC data has to be updated to I2C
registers.
0—Disables content-based updating.
1 (default)—Enables content-based updating.
WSS_CGMS_CB_CHANGE, Enable Content-Based
Updating for WSS/CGMS, Address 0x9C [4],
User Sub Map
0—Disables content-based updating.
1 (default)—Enables content-based updating.
VDP—Interrupt-Based Reading of VDP I2C Registers
2. Write high to the GS_PDC_VPS_UTC_CLEAR bit (0x78,
User Sub Map) to enable I2C register updating.
Some VDP status bits are also linked to the interrupt request
controller so that the user does not have to poll the AVAILABLE
status bit. The user can configure the video decoder to trigger
an interrupt request on the INTRQ pin in response to the valid
data available in I2C registers. This function is available for the
following data types:
3. Poll the GS_PDC_VPS_UTC_AVL bit (0x78, User Sub
Map) going high to check the availability of the PDC
packets.
4. Read the data bytes from the PDC I2C registers. Repeat
Step 1 to Step 3 to read another line or packet of data.
To read a packet of CCAP, CGMS, or WSS data, only Step 1 to
Step 3 are required because they have dedicated registers.
•
CGMS or WSS: The user can select either triggering
an interrupt request each time sliced data is available
or triggering an interrupt request only when the
sliced data has changed. Selection is made via the
WSS_CGMS_CB_CHANGE bit.
VDP—Content-Based Data Update
For certain standards like WSS, CGMS, Gemstar, PDC, UTC,
and VPS, the information content in the signal transmitted
remains the same over numerous lines, and the user may want
Rev. A | Page 57 of 112
ADV7180
VDP_VITC_MSKB, Address 0x50 [6], User Sub Map
0 (default)—Disables interrupt on VDP_VITC_Q signal.
1—Enables interrupt on VDP_VITC_Q signal.
Interrupt Status Register Details
•
Gemstar, PDC, VPS, or UTC: The user can select to
trigger an interrupt request each time sliced data is
available or to trigger an interrupt request only when
the sliced data has changed. Selection is made via the
GS_VPS_PDC_UTC_CB_ CHANGE bit.
The sequence for the interrupt-based reading of the VDP I2C
data registers is as follows for the CCAP standard:
The following read-only bits contain data detection information
from the VDP module since the status bit was last cleared or
unmasked.
1. User unmasks CCAP interrupt mask bit (0x50 Bit 0, User
Sub Map = 1). CCAP data occurs on the incoming video.
VDP slices CCAP data and places it into the VDP readback
registers.
2. The VDP CCAP AVAILABLE bit goes high, and the VDP
module signals to the interrupt controller to stimulate an
interrupt request (for CCAP in this case).
VDP_CCAPD_Q, Address 0x4E [0], User Sub Map
0 (default)—CCAP data has not been detected.
1—CCAP data has been detected.
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E [2],
User Sub Map
3. The user reads the interrupt status bits (User Sub Map) and
sees that new CCAP data is available (0x4E Bit 0, User Sub
Map = 1).
0 (default)—CGMS or WSS data has not been detected.
1—CGM or WSS data has been detected.
4. The user writes 1 to the CCAP interrupt clear bit (0x4F
Bit 0, User Sub Map = 1) in the interrupt I2C space (this is a
self-clearing bit). This clears the interrupt on the INTRQ
pin but does not have an effect in the VDP I2C area.
5. The user reads the CCAP data from the VDP I2C area.
6. The user writes to Bit CC_CLEAR in the VDP_STATUS[0]
register, (0x78 Bit 0, User Sub Map = 1) to signify the CCAP
data has been read (therefore the VDP CCAP can be
updated at the next occurrence of CCAP).
VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E [4],
User Sub Map
0 (default)—Gemstar, PDC, UTC, or VPS data has not been
detected.
1—Gemstar, PDC, UTC, or VPS data has been detected.
VDP_VITC_Q, Address 0x4E [6], User Sub Map,
Read Only
0 (default)—VITC data has not been detected.
1—VITC data has been detected.
7. Back to Step 2.
Interrupt Mask Register Details
Interrupt Status Clear Register Details
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
It is not necessary to write 0 to these write-only bits because
they automatically reset after they have been set to 1 (self-
clearing).
VDP_CCAPD_MSKB, Address 0x50 [0], User Sub Map
0 (default)—Disables interrupt on VDP_CCAPD_Q signal.
1—Enables interrupt on VDP_CCAPD_Q signal.
VDP_CCAPD_CLR, Address 0x4F [0], User Sub Map
1—Clears VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_MSKB, Address 0x50 [2],
User Sub Map
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2],
User Sub Map
0 (default)—Disables interrupt on VDP_CGMS_WSS_
CHNGD_Q signal.
1—Clears VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F [4], User Sub Map
1—Enables interrupt on VDP_CGMS_WSS_CHNGD_Q
signal.
1—Clears VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_VITC_CLR, Address 0x4F [6], User Sub Map
1—Clears VDP_VITC_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_MSKB,
Address 0x50 [4], User Sub Map
0 (default)—Disables interrupt on
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
1—Enables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q
signal.
Rev. A | Page 58 of 112
ADV7180
I2C READBACK REGISTERS
WST_PKT_DECODE_DISABLE, Disable Hamming
Decoding of Bytes in WST, Address 0x60 [3], User Sub
Map
Teletext
Because teletext is a high data rate standard, the decoded bytes
are available only as ancillary data. However, a TTXT_AVL bit
has been provided in I2C so that the user can check whether the
VDP has detected teletext or not. Note that the TTXT_AVL bit
is a plain status bit and does not use the protocol identified in
the I2C Interface section.
0—Enables hamming decoding of WST packets.
1 (default)—Disables hamming decoding of WST packets.
For hamming-coded bytes, the dehammed nibbles are output
along with some error information from the hamming decoder
as follows:
TTXT_AVL, Teletext Detected Status, Address 0x78 [7],
User Sub Map, Read Only
•
Input hamming coded byte: {D3, P3, D2, P2, D1, P1, D0,
P0} (bits in decoded order)
0—Teletext was not detected.
1—Teletext was detected.
WST Packet Decoding
•
Output dehammed byte: {E1, E0, 0, 0, D3', D2', D1', D0'}
(Di' – corrected bits, Ei error information).
Table 75. Error Bits in the Dehammed Output Byte
Output Data Bits
in Nibble
For WST only, the VDP decodes the magazine and row address
of teletext packets and further decodes the packet’s 8 × 4
hamming coded words. This feature can be disabled using the
WST_PKT_ DECODE_ DISABLE bit (Bit 3, Register 0x60, User
Sub Map). This feature is valid for WST only.
E[1:0] Error Information
00
01
10
11
No errors detected
Error in P4
Double error
Okay
Okay
Bad
Single error found and corrected
Okay
Table 76 describes the WST packets that are decoded.
Table 76. WST Packet Description
Packet
Byte
Description
Header Packet
(X/00)
1st
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Page number—Dehammed Byte 6
Page number—Dehammed Byte 7
Control Bytes—Dehammed Byte 8 to Byte 13
Raw data bytes
2nd
3rd
4th
5th to 10th
11th to 42nd
1st
Text Packets
(X/01 to X/25)
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Raw data bytes
2nd
3rd to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
2nd
3rd
4th to 42nd
8/30 (Format 1) Packet
Design Code = 0000 or 0001
UTC
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design Code—Dehammed Byte 6
Dehammed initial teletext page, Byte 7 to Byte 12
UTC bytes—Dehammed Bytes 13 to Byte 25
Raw status bytes
8/30 (Format 2) Packet
Design Code = 0010 or 0011
PDC
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design Code—Dehammed Byte 6
Dehammed initial teletext page, Byte 7 to Byte 12
PDC bytes—Dehammed Byte 13 to Byte 25
Raw status bytes
X/26, X/27, X/28, X/29, X/30, X/311
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design Code—Dehammed Byte 6
Raw data bytes
1 For X/26, X/28, and X/29 further decoding needs 24 × 18 hamming decoding. Not supported at present.
Rev. A | Page 59 of 112
ADV7180
CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78 [2],
User Sub Map, Read Only
CGMS and WSS
The CGMS and WSS data packets convey the same type of
information for different video standards. WSS is for PAL and
CGMS is for NTSC, so the CGMS and WSS readback registers
are shared. WSS is biphase coded; the VDP does a biphase
decoding to produce the 14 raw WSS bits in the CGMS/WSS
readback I2C registers and to set the CGMS_WSS_AVL bit.
0—CGMS/WSS was not detected.
1—CGMS/WSS was detected.
CGMS_WSS_DATA_0[3:0], Address 0x7D [3:0];
CGMS_WSS_DATA_1[7:0], Address 0x7E [7:0];
CGMS_WSS_DATA_2[7:0], Address 0x7F [7:0];
User Sub Map, Read Only
CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78 [2],
User Sub Map, Write Only, Self-Clearing
These bits hold the decoded CGMS or WSS data.
1—Reinitializes the CGMS/WSS readback registers.
Refer to Figure 43 and Figure 44 for the I2C to WSS and CGMS
bit mapping.
VDP_CGMS_WSS_
VDP_CGMS_WSS_DATA_2 DATA_1[5:0]
0
1
2
3
4
5
6
7
0
1
2
3
4
5
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
11.0µs
38.4µs
42.5µs
Figure 43. WSS Waveform
+100 IRE
+70 IRE
VDP_CGMS_WSS_
DATA_0[3:0]
REF
VDP_CGMS_WSS_DATA_2
VDP_CGMS_WSS_DATA_1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0 IRE
49.1µs ± 0.5µs
–40 IRE
11.2µs
CRC SEQUENCE
2.235µs ± 20ns
Figure 44. CGMS Waveform
Table 77. CGMS Readback Registers1
Signal Name
Register Location
Address (User Sub Map)
CGMS_WSS_DATA_0[3:0]
CGMS_WSS_DATA_1[7:0]
CGMS_WSS_DATA_2[7:0]
VDP_CGMS_WSS_DATA_0[3:0]
VDP_CGMS_WSS_DATA_1[7:0]
VDP_CGMS_WSS_DATA_2[7:0]
125
126
127
0x7D
0x7E
0x7F
1 The register is a readback register; default value does not apply.
Rev. A | Page 60 of 112
ADV7180
CCAP
CC_EVEN_FIELD, Address 0x78 [1], User Sub Map,
Read Only
Two bytes of decoded closed caption data are available in the
I2C registers. The field information of the decoded CCAP data
can be obtained from the CC_EVEN_FIELD bit (Register 0x78).
Identifies the field from which the CCAP data was decoded.
0—Closed captioning was detected on an odd field.
1—Closed captioning was detected on an even field.
CC_CLEAR, Closed Caption Clear, Address 0x78 [0],
User Sub Map, Write Only, Self-Clearing
VDP_CCAP_DATA_0, Address 0x79 [7:0], User Sub Map,
Read Only
1—Reinitializes the CCAP readback registers.
CC_AVL, Closed Caption Available, Address 0x78 [0],
User Sub Map, Read Only
Decoded Byte 1 of CCAP data.
VDP_CCAP_DATA_1, Address 0x7A [7:0], User Sub Map,
Read Only
0—Closed captioning was not detected.
1—Closed captioning was detected.
Decoded Byte 2 of CCAP data.
10.5 ± 0.25µs
12.91µs
7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN)
0 1 2 3 4 5 6 7 0 1 2 3 4 5
6
7
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
50 IRE
40 IRE
VDP_CCAP_D ATA_0 VDP_CCAP_D ATA_1
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003µs
27.382µs
33.764µs
Figure 45. CCAP Waveform and Decoded Data Correlation
Table 78. CCAP Readback Registers1
Signal Name
Register Location
VDP_CCAP_DATA_0[7:0]
VDP_CCAP_DATA_1[7:0]
Address (User Sub Map)
CCAP_BYTE_1[7:0]
CCAP_BYTE_2[7:0]
121
122
0x79
0x7A
1 The register is a readback register; default value does not apply.
Rev. A | Page 61 of 112
ADV7180
VITC
VITC_CLEAR, VITC Clear, Address 0x78 [6],
User Sub Map, Write Only, Self-Clearing
VITC has a sequence of 10 syncs in between each data byte.
The VDP strips these syncs from the data stream to output
only the data bytes. The VITC results are available in Register
VDP_VITC_DATA_0 to Register VDP_VITC_DATA_8
(Register 0x92 to Register 0x9A, User Sub Map).
1—Reinitializes the VITC readback registers.
VITC_AVL, VITC Available, Address 0x78 [6],
User Sub Map
0—VITC data was not detected.
1—VITC data was detected.
The VITC has a CRC byte at the end; the syncs in between each
data byte are also used in this CRC calculation. Because the
syncs in between each data byte are not output, the CRC is
calculated internally. The calculated CRC is available for the
user in the VITC_CALC_CRC register (Resister 0x9B, User Sub
Map). Once the VDP completes decoding the VITC line, the
VITC_DATA and VITC_CALC_CRC registers are updated and
the VITC_AVL bit is set.
VITC Readback Registers
See Figure 46 for the I2C to VITC bit mapping.
TO
VITC WAVEFORM
BIT0, BIT1
BIT88, BIT89
Figure 46. VITC Waveform and Decoded Data Correlation
Table 79. VITC Readback Registers1
Signal Name
Register Location
Address (User Sub Map)
VITC_DATA_0[7:0]
VITC_DATA_1[7:0]
VITC_DATA_2[7:0]
VITC_DATA_3[7:0]
VITC_DATA_4[7:0]
VITC_DATA_5[7:0]
VITC_DATA_6[7:0]
VITC_DATA_7[7:0]
VITC_DATA_8[7:0]
VITC_CALC_CRC[7:0]
VDP_VITC_DATA_0[7:0] (VITC Bits [9:2])
146
147
148
149
150
151
152
153
154
155
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
VDP_VITC_DATA_1[7:0] (VITC Bits [19:12])
VDP_VITC_DATA_2[7:0] (VITC Bits [29:22])
VDP_VITC_DATA_3[7:0] (VITC Bits [39:32])
VDP_VITC_DATA_4[7:0] (VITC Bits [49:42])
VDP_VITC_DATA_5[7:0] (VITC Bits [59:52])
VDP_VITC_DATA_6[7:0] (VITC Bits [69:62])
VDP_VITC_DATA_7[7:0] (VITC Bits [79:72])
VDP_VITC_DATA_8[7:0] (VITC Bits [89:82])
VDP_VITC_CALC_CRC[7:0]
1 The register is a readback register; default value does not apply.
Rev. A | Page 62 of 112
ADV7180
VDP supports autodetection of the Gemstar standard, either
VPS/PDC/UTC/GEMSTAR
Gemstar 1× or Gemstar 2×, and decodes accordingly. For the
autodetection mode to work, the user must set the
The readback registers for VPS, PDC, and UTC are shared.
Gemstar is a high data rate standard and is available only
through the ancillary stream. However, for evaluation purposes,
any one line of Gemstar is available through the I2C registers
sharing the same register space as PDC, UTC, and VPS.
Therefore, only VPS, PDC, UTC, or Gemstar can be read
through the I2C at a time.
AUTO_DETECT_GS_TYPE I2C bit (Register 0x61, User
Sub Map) and program the decoder to decode Gemstar 2× on
the required lines through line programming. The type of
Gemstar decoded can be determined by observing the
GS_DATA_TYPE bit (Register 0x78, User Sub Map).
To identify the data that should be made available in the I2C
registers, the user must program I2C_GS_VPS_PDC_UTC[1:0]
(Register Address 0x9C, User Sub Map).
I2C_GS_VPS_PDC_UTC [1:0] (VDP), Address 0x9C [6:5],
User Sub Map
AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map
0 (default)—Disables autodetection of Gemstar type.
1—Enables autodetection of Gemstar type.
GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only
Identifies the decoded Gemstar data type.
Specifies which standard result is available for I2C readback.
0—Gemstar 1× mode is detected. Read 2 data bytes from 0x84.
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear,
Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
1—Gemstar 2× mode is detected. Read 4 data bytes from 0x84.
The Gemstar data that is available in the I2C register could be
from any line of the input video on which Gemstar was
decoded. To read the Gemstar data on a particular video line,
the user should use the manual configuration described in
Table 66 and Table 67 and enable Gemstar decoding only on the
required line.
1—Reinitializes the GS/PDC/VPS/UTC data readback registers.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available,
Address 0x78 [4], User Sub Map, Read Only
0—One of GS, PDC, VPS, or UTC data was not detected.
1—One of GS, PDC, VPS, or UTC data was detected.
PDC/UTC
VDP_GS_VPS_PDC_UTC, Readback Registers,
Addresses 0x84 to 0x87
PDC and UTC are data transmitted through Teletext Packet 8/30
Format 2 (Magazine 8, Row 30, Design Code 2 or 3), and Packet
8/30 Format 1 (Magazine 8, Row 30, Design Code 0 or 1). Thus,
if PDC or UTC data is to be read through I2C, the corresponding
teletext standard (WST or PAL System B) should be decoded by
VDP. The whole teletext decoded packet is output on the ancillary
data stream. The user can look for the magazine number, row
number, and design code and qualify the data as PDC, UTC, or
neither of these.
See Table 81.
VPS
The VPS data bits are biphase decoded by the VDP. The
decoded data is available in both the ancillary stream and in the
I2C readback registers. VPS decoded data is available in the
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (Address 0x84 to Address 0x90, User Sub Map). The
GS_VPS_ PDC_UTC_AVL bit is set if the user programmed
I2C_GS_VPS_PDC_UTC to 01, as explained in Table 80.
If PDC/UTC packets have been identified, Byte 0 to Byte 12 are
updated to the GS_VPS_PDC_UTC_0 to VPS_PDC_UTC_12
registers, and the GS_VPS_PDC_UTC_AVL bit is set. The full
packet data is also available in the ancillary data format.
Note that the data available in the I2C register depends on the
status of the WST_PKT_DECODE_DISABLE bit (Bit 3,
Subaddress 0x60, User Sub Map).
GEMSTAR
The Gemstar-decoded data is made available in the ancillary
stream, and any one line of Gemstar is also available in the I2C
registers for evaluation purposes. To read Gemstar results
through the I2C registers, the user must program
I2C_GS_VPS_PDC_UTC to 00, as explained in Table 80.
Table 80. I2C_GS_VPS_PDC_UTC[1:0] Function
I2C_GS_VPS_PDC_UTC[1:0]
Description
Gemstar 1×/2×
VPS
PDC
UTC
00 (default)
01
10
11
Rev. A | Page 63 of 112
ADV7180
Table 81. GS/VPS/PDC/UTC Readback Registers1
Signal Name
Register Location
Dec Address (User Sub Map)
Hex Address (User Sub Map)
GS_VPS_PDC_UTC_BYTE_0[7:0]
GS_VPS_PDC_UTC_BYTE_1[7:0]
GS_VPS_PDC_UTC_BYTE_2[7:0]
GS_VPS_PDC_UTC_BYTE_3[7:0]
VPS_PDC_UTC_BYTE_4[7:0]
VPS_PDC_UTC_BYTE_5[7:0]
VPS_PDC_UTC_BYTE_6[7:0]
VPS_PDC_UTC_BYTE_7[7:0]
VPS_PDC_UTC_BYTE_8[7:0]
VPS_PDC_UTC_BYTE_9[7:0]
VPS_PDC_UTC_BYTE_10[7:0]
VPS_PDC_UTC_BYTE_11[7:0]
VPS_PDC_UTC_BYTE_12[7:0]
VDP_GS_VPS_PDC_UTC_0[7:0]
VDP_GS_VPS_PDC_UTC_1[7:0]
VDP_GS_VPS_PDC_UTC_2[7:0]
VDP_GS_VPS_PDC_UTC_3[7:0]
VDP_VPS_PDC_UTC_4[7:0]
VDP_VPS_PDC_UTC_5[7:0]
VDP_VPS_PDC_UTC_6[7:0]
VDP_VPS_PDC_UTC_7[7:0]
VDP_VPS_PDC_UTC_8[7:0]
VDP_VPS_PDC_UTC_9[7:0]
VDP_VPS_PDC_UTC_10[7:0]
VDP_VPS_PDC_UTC_11[7:0]
VDP_VPS_PDC_UTC_12[7:0]
132d
133d
134d
135d
136d
137d
138d
139d
140d
141d
142d
143d
144d
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
1 The default value does not apply to readback registers.
VBI System 2
GDE_SEL_OLD_ADF, Address 0x4C [3], User Sub Map
The user has an option of using a different VBI data slicer called
VBI System 2. This data slicer is used to decode Gemstar and
closed caption VBI signals only.
The ADV7180 has a new ancillary data output block that can be
used by the VDP data slicer and the VBI System 2 data slicer.
The new ancillary data formatter is used by setting
GDE_SEL_OLD_ADF to 0 (default). If this bit is set low, refer
to Table 70 and Table 71 for information about how the data is
packaged in the ancillary data stream.
Using this system, the Gemstar data is only available in the
ancillary data stream. A special mode enables one line of data to
be read back through I2C. For details about using I2C readback
with the VBI System 2 data slicer, contact local Analog Devices
field applications engineers or local Analog Devices distributor.
To use the old ancillary data formatter (to be backward compatible
with the ADV7183B), set GDE_SEL_OLD_ADF to 1. The ancillary
data format in this section refers to the ADV7183B-compatible
ancillary data formatter.
Gemstar Data Recovery
The Gemstar-compatible data recovery block (GSCD) supports
1× and 2× data transmissions. In addition, it can serve as a
closed caption decoder. Gemstar-compatible data transmissions
can occur only in NTSC. Closed caption data can be decoded in
both PAL and NTSC.
0 (default)—Enables new ancillary data system for use with
VDP and VBI System 2.
1—Enables old ancillary data system for use with VBI System 2
only (ADV7183B compatible).
The block can be configured via I2C as follows:
The format of the data packet depends on the following criteria:
•
•
•
GDECEL[15:0] allows data recovery on selected video lines
on even fields to be enabled or disabled.
GDECOL[15:0] enables the data recovery on selected lines
for odd fields.
GDECAD configures the way in which data is embedded
in the video data stream.
•
•
Transmission is 1× or 2×.
Data is output in 8-bit or 4-bit format (see the description
of the bit).
•
Data is closed caption (CCAP) or Gemstar compatible.
Data packets are output if the corresponding enable bit is set
(see the GDECEL[15:0] and GDECOL[15:0] descriptions) the
decoder detects the presence of data. This means that for video
lines where no data has been decoded, no data packet is output
even if the corresponding line enable bit is set.
The recovered data is not available through I2C, but is inserted into
the horizontal blanking period of an ITU-R BT.656-compatible
data stream. The data format is intended to comply with the
recommendation by the International Telecommunications
Union, ITU-R BT.1364. For more information, visit the
International Telecommunication Union website. See Figure 47.
Rev. A | Page 64 of 112
ADV7180
Each data packet starts immediately after the EAV code of the
preceding line. Figure 47 and Table 82 show the overall
structure of the data packet.
•
Data count byte, giving the number of user data-words that
follow.
•
•
User data section.
Entries within the packet are as follows:
Optional padding to ensure that the length of the user
data-word section of a packet is a multiple of 4 bytes
(requirement as set in ITU-R BT.1364).
•
•
Fixed preamble sequence of 0x00, 0xFF, and 0xFF.
Data identification word (DID). The value for the DID
marking a Gemstar or CCAP data packet is 0x140 (10-bit
value).
•
Checksum byte.
Table 82 lists the values within a generic data packet that is
output by the ADV7180 in 8-bit format.
•
Secondary data identification word (SDID), which contains
information about the video line from which data was
retrieved, whether the Gemstar transmission was of 1× or
2× format, and whether it was retrieved from an even or
odd field.
DATA IDENTIFICATION
SECONDARY DATA IDENTIFICATION
DATA
COUNT
OPTIONAL PADDING CHECK
00
FF
FF
DID
SDID
USER DATA
BYTES
SUM
PREAMBLE FOR ANCILLARY DATA
USER DATA (4 OR 8 WORDS)
Figure 47. Gemstar and CCAP Embedded Data Packet (Generic)
Table 82. Generic Data Output Packet
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
1
0
4
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
2X
0
0
SDID
line[3:0]
5
0
0
DC[1]
word1[7:4]
word1[3:0]
word2[7:4]
word2[3:0]
word3[7:4]
word3[3:0]
word4[7:4]
word4[3:0]
DC[0]
0
Data count (DC)
6
0
0
0
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
0
8
0
0
0
9
0
0
0
10
11
12
13
14
0
0
0
0
0
0
0
0
0
0
0
0
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
0
Table 83. Data Byte Allocation
Raw Information Bytes
Retrieved from the Video Line
User Data-Words
(Including Padding)
2×
1
1
0
0
GDECAD
Padding Bytes
DC[1:0]
10
01
01
01
4
4
2
2
0
1
0
1
8
4
4
4
0
0
0
2
Rev. A | Page 65 of 112
ADV7180
Gemstar Bit Names
•
•
DC[1:0]—Data count value. The number of UDWs in the
packet divided by 4. The number of UDWs in any packet
must be an integral number of 4. Padding may be required
at the end, as set in ITU-R BT.1364. See Table 83.
•
DID—The data identification value is 0x140 (10-bit value).
Care has been taken so that in 8-bit systems, the two LSBs
do not carry vital information.
CS[8:2]—The checksum is provided to determine the
integrity of the ancillary data packet. It is calculated by
summing up D[8:2] of DID, SDID, the data count byte, and
all UDWs, and ignoring any overflow during the
summation. Because all data bytes that are used to
calculate the checksum have their 2 LSBs set to 0, the
CS[1:0] bits are also always 0.
EP
•
EP and —The EP bit is set to ensure even parity on
data-word D[8:0]. Even parity means there is always an
even number of 1s within the D[8:0] bit arrangement. This
includes the EP bit.
and is output on D[9]. The
reserved codes of 00 and FF do not occur.
EP
describes the logic inverse of EP
EP
is output to ensure that the
•
•
EF—Even field identifier. EF = 1 indicates that the data was
recovered from a video line on an even field.
CS
CS
[8]—describes the logic inversion of CS[8]. The value [8]
is included in the checksum entry of the data packet to ensure
that the reserved values of 0x00 and 0xFF do not occur.
2×—This bit indicates whether the data sliced was in
Gemstar 1× or 2× format. A high indicates 2× format.
The 2× bit determines whether the raw information
retrieved from the video line was two bytes or four bytes.
The state of the GDECAD bit affects whether the bytes are
transmitted straight (that is, two bytes transmitted as two
bytes) or whether they are split into nibbles (that is, two
bytes transmitted as four half bytes). Padding bytes are
then added where necessary.
Table 84 to Table 89 outline the possible data packages.
Gemstar_2× Format, Half-Byte Output Mode
Half-byte output mode is selected by setting CDECAD to 0;
full-byte output mode is selected by setting CDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0] section.
Gemstar_1× Format
•
line[3:0]—This entry provides a code that is unique for
each of the possible 16 source lines of video from which
Gemstar data may have been retrieved. Refer to Table 92
and Table 93.
Half-byte output mode is selected by setting CDECAD to 0,
full-byte output mode is selected by setting CDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0] section.
Table 84. Gemstar_2× Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
1
0
0
4
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
1
0
0
SDID
line[3:0]
5
0
0
0
1
0
0
0
Data count
6
0
0
0
0
Gemstar word1[7:4]
Gemstar word1[3:0]
Gemstar word2[7:4]
Gemstar word2[3:0]
Gemstar word3[7:4]
Gemstar word3[3:0]
Gemstar word4[7:4]
Gemstar word4[3:0]
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
11
12
13
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Rev. A | Page 66 of 112
ADV7180
Table 85. Gemstar_2× Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
0
0
4
EP
EP
EP
EP
EF
0
0
0
SDID
line[3:0]
5
0
0
0
1
0
0
Data count
6
Gemstar word1[7:0]
Gemstar word2[7:0]
Gemstar word3[7:0]
Gemstar word4[7:0]
0
0
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
8
0
0
9
0
0
10
CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 86. Gemstar_1× Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
3
0
1
0
1
0
line[3:0]
0
0
0
4
EP
EP
EP
EP
EP
EP
CS[8]
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
0
0
SDID
5
0
0
0
0
1
0
0
Data count
6
0
0
0
0
Gemstar word1[7:4]
Gemstar word1[3:0]
Gemstar word2[7:4]
Gemstar word2[3:0]
User data-words
User data-words
User data-words
User data-words
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Checksum
Table 87. Gemstar_1× Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
0
line[3:0]
0
0
4
EP
EP
EP
EP
EF
0
0
SDID
5
0
0
1
0
Data count
6
Gemstar word1[7:0]
Gemstar word2[7:0]
0
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
7
0
8
1
0
0
0
0
0
0
0
0
0
0
9
1
0
0
0
0
0
0
10
CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Rev. A | Page 67 of 112
ADV7180
Table 88. NTSC CCAP Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
1
0
0
4
EP
EP
EP
EP
EP
EP
CS[8]
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
0
0
SDID
5
0
0
0
0
Data count
6
0
0
0
0
CCAP word1[7:4]
CCAP word1[3:0]
CCAP word2[7:4]
CCAP word2[3:0]
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 89. NTSC CCAP Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
0
0
4
EP
EP
EP
EP
EF
0
0
0
SDID
5
0
0
Data count
6
CCAP word1[7:0]
CCAP word2[7:0]
0
0
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
7
0
0
8
1
0
0
0
0
0
0
0
0
0
9
1
0
0
0
0
0
0
0
0
0
10
CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Rev. A | Page 68 of 112
ADV7180
Table 90. PAL CCAP Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
0
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
1
0
0
4
EP
EP
EP
EP
EP
EP
CS[8]
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
0
0
SDID
5
0
0
0
0
Data count
6
0
0
0
0
CCAP word1[7:4]
CCAP word1[3:0]
CCAP word2[7:4]
CCAP word2[3:0]
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 91. PAL CCAP Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
0
D[0]
Description
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
0
0
4
EP
EP
EP
EP
EF
0
0
0
SDID
5
0
0
Data count
6
CCAP word1[7:0]
CCAP word2[7:0]
0
0
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
7
0
0
8
1
0
0
0
0
0
0
0
0
0
9
1
0
0
0
0
0
0
0
0
0
10
CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
See the GDECEL[15:0], Gemstar Decoding Even Lines,
Address 0x48 [7:0], Address 0x49 [7:0] section and the
GDECOL[15:0], Gemstar Decoding Odd Lines, Address 0x4A
[7:0], Address 0x4B [7:0] section.
NTSC CCAP Data
Half-byte output mode is selected by setting CDECAD to 0, and
the full-byte mode is enabled by setting CDECAD to 1. See the
GDECAD, Gemstar Decode Ancillary Data Format, Address
0x4C [0] section. The data packet formats are shown in Table 88
and Table 89. Only closed caption data can be embedded in the
output data stream.
GDECEL[15:0], Gemstar Decoding Even Lines,
Address 0x48 [7:0], Address 0x49 [7:0]
The 16 bits of GDECEL[15:0] are interpreted as a collection of
16 individual line decode enable signals. Each bit refers to a line
of video in an even field. Setting the bit enables the decoder
block trying to find Gemstar or closed caption-compatible data
on that particular line. Setting the bit to 0 prevents the decoder
from trying to retrieve data. See Table 92 and Table 93.
NTSC closed caption data is sliced on Line 21d of even and odd
fields. The corresponding enable bit has to be set high. See the
GDECAD, Gemstar Decode Ancillary Data Format, Address
0x4C [0] section and the GDECOL[15:0], Gemstar Decoding
Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0] section.
To retrieve closed caption data services on NTSC (Line 284),
GDECEL[11] must be set.
PAL CCAP Data
Half-byte output mode is selected by setting CDECAD to 0, and
full-byte output mode is selected by setting CDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0] section. Table 90 and Table 91 list the bytes of
the data packet.
To retrieve closed caption data services on PAL (Line 335),
GDECEL[14] must be set.
The default value of GDECEL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the even field. The user should only
enable Gemstar slicing on lines where VBI data is expected.
Only closed caption data can be embedded in the output data
stream. PAL closed caption data is sliced from Line 22 and
Line 335. The corresponding enable bits must be set.
Rev. A | Page 69 of 112
ADV7180
Table 92. NTSC Line Enable Bits and Corresponding
Line Numbering
GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0]
Line Number
(ITU-R BT.470)
The decoded data from Gemstar-compatible transmissions or
closed caption-compatible transmission is inserted into the
horizontal blanking period of the respective line of video. A
potential problem can arise if the retrieved data bytes have a
value of 0x00 or 0xFF. In an ITU-R BT.656-compatible data
stream, these values are reserved and used only to form a fixed
preamble. The GDECAD bit allows the data to be inserted into
the horizontal blanking period in two ways:
line[3:0]
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
Comment
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
0
1
2
3
4
5
6
7
8
9
10
11
10
11
12
13
14
15
16
17
18
19
20
21
•
Insert all data straight into the data stream, even the
reserved values of 0x00 and 0xFF, if they occur. This may
violate output data format specification ITU-R BT.1364.
•
Split all data into nibbles and insert the half-bytes over
double the number of cycles in a 4-bit format.
Gemstar or
closed caption
0 (default)—The data is split into half-bytes and inserted.
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
22
23
24
25
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
1—The data is output straight into the data stream in 8-bit format.
Table 93. PAL Line Enable Bits and Line Numbering
Line Number
line[3:0] (ITU-R BT.470)
273 (10)
274 (11)
275 (12)
276 (13)
277 (14)
278 (15)
279 (16)
280 (17)
281 (18)
282 (19)
283 (20)
284 (21)
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
Comment
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
12
13
14
15
0
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
321 (8)
322 (9)
323 (10)
324 (11)
325 (12)
326 (13)
327 (14)
328 (15)
329 (16)
330 (17)
331 (18)
332 (19)
333 (20)
334 (21)
335 (22)
336 (23)
Gemstar or
closed caption
12
13
14
15
285 (22)
286 (23)
287 (24)
288 (25)
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
Gemstar
Gemstar
Gemstar
Gemstar
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
GDECOL[15:0], Gemstar Decoding Odd Lines,
Address 0x4A [7:0], Address 0x4B [7:0]
The 16 bits of GDECOL[15:0] form a collection of 16 individual
line decode enable signals. See Table 92 and Table 93.
To retrieve closed caption data services on NTSC (Line 21),
GDECOL[11] must be set.
To retrieve closed caption data services on PAL (Line 22),
GDECOL[14] must be set.
The default value of GDECOL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the odd field. The user should only
enable Gemstar slicing on lines where VBI data is expected.
Rev. A | Page 70 of 112
ADV7180
Letterbox Detection
There is no letterbox detected bit. Read the LB_LCT[7:0] and
LB_LCB[7:0] register values to determine whether or not the
letterbox-type video is present in software.
Incoming video signals may conform to different aspect ratios
(16:9 wide screen or 4:3 standard). For certain transmissions in
the wide-screen format, a digital sequence (WSS) is transmitted
with the video signal. If a WSS sequence is provided, the aspect
ratio of the video can be derived from the digitally decoded bits
that WSS contains.
LB_LCT[7:0], Letterbox Line Count Top, Address 0x9B
[7:0]; LB_LCM[7:0], Letterbox Line Count Mid,
Address 0x9C [7:0]; LB_LCB[7:0], Letterbox Line Count
Bottom, Address 0x9D [7:0]
In the absence of a WSS sequence, letterbox detection can be
used to find wide-screen signals. The detection algorithm
examines the active video content of lines at the start and end of
a field. If black lines are detected, this may indicate that the
currently shown picture is in wide-screen format.
Table 94. LB_LCx Access Information
Signal Name
LB_LCT[7:0]
LB_LCM[7:0]
LB_LCB[7:0]
Address
0x9B
0x9C
0x9D
The active video content (luminance magnitude) over a line of
video is summed together. At the end of a line, this accumulated
value is compared with a threshold, and a decision is made as to
whether or not a particular line is black. The threshold value
needed may depend on the type of input signal; some control is
provided via LB_TH[4:0].
LB_TH[4:0], Letterbox Threshold Control,
Address 0xDC [4:0]
Table 95. LB_TH Function
LB_TH[4:0]
Description
01100 (default)
01101 to 10000
Default threshold for detection of black lines.
Increase threshold (need larger active video
content before identifying nonblack lines).
Decrease threshold (even small noise levels
can cause the detection of nonblack lines).
Detection at the Start of a Field
The ADV7180 expects a section of at least six consecutive black
lines of video at the top of a field. Once those lines are detected,
Register LB_LCT[7:0] reports the number of black lines that
were actually found. By default, the ADV7180 starts looking for
those black lines in sync with the beginning of active video, for
example, immediately after the last VBI video line. LB_SL[3:0]
allows the user to set the start of letterbox detection from the
beginning of a frame on a line-by-line basis. The detection
window closes in the middle of the field.
00000 to 01011
LB_SL[3:0], Letterbox Start Line, Address 0xDD [7:4]
The LB_SL[3:0] bits are set at 0100 by default. For an NTSC
signal, this window is from Line 23 to Line 286.
By changing the bits to 0101, the detection window starts on
Line 24 and ends on Line 287.
Detection at the End of a Field
LB_EL[3:0], Letterbox End Line, Address 0xDD [3:0]
The ADV7180 expects at least six continuous lines of black video
at the bottom of a field before reporting the number of lines
actually found via the LB_LCB[7:0] value. The activity window
for letterbox detection (end of field) starts in the middle of an
active field. Its end is programmable via LB_EL[3:0].
The LB_EL[3:0] bits are set at 1101 by default. This means that the
letterbox detection window ends with the last active video line.
For an NTSC signal, this window is from Line 262 to Line 525.
By changing the bits to 1100, the detection window starts on
Line 261 and ends on Line 254.
Detection at the Midrange
Some transmissions of wide-screen video include subtitles
within the lower black box. If the ADV7180 finds at least two
black lines followed by some more nonblack video, for example,
the subtitle followed by the remainder of the bottom black
block, it reports a midcount via LB_LCM[7:0]. If no subtitles are
found, LB_LCM[7:0] reports the same number as LB_LCB[7:0].
There is a 2-field delay in reporting any line count parameter.
Rev. A | Page 71 of 112
ADV7180
PIXEL PORT CONFIGURATION
The ADV7180 has a very flexible pixel port that can be
configured in a variety of formats to accommodate downstream
ICs. Table 96, Table 97, and Table 98 summarize the various
functions that the ADV7180 pins can have in different modes of
operation.
SWPC, Swap Pixel Cr/Cb, Address 0x27 [7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
The ordering of components, for example, Cr vs. Cb for
Channels A, B, and C can be changed. Refer to the SWPC, Swap
Pixel Cr/Cb, Address 0x27 [7] section. Table 96 indicates the
default positions for the Cr/Cb components.
LLC_PAD_SEL[2:0], LLC1 Output Selection,
Address 0x8F [6:4]
The following I2C write allows the user to select between LLC1
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
OF_SEL[3:0], Output Format Selection, Address 0x03 [5:2]
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See the OF_SEL[3:0], Output Format
Selection, Address 0x03 [5:2] section for additional information.
The LLC2 signal and data on the data bus are synchronized.
By default, the rising edge of LLC1/LLC2 is aligned with the
Y data; the falling edge occurs when the data bus holds C data.
The polarity of the clock, and therefore the Y/C assignments to
the clock edges, can be altered by using the polarity LLC pin.
The modes in which the ADV7180 pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 98 for details.
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data rate
of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin
stays at the higher rate of 27 MHz. For information on outputting
the nominal 13.5 MHz clock on the LLC1 pin, see the section
LLC_PAD_SEL[2:0], LLC1 Output Selection,
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC1 pin (default).
Address 0x8F [6:4].
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC2 pin.
Table 96. ADV7180 LQFP-64 P15 to P0 Output/Input Pin Mapping
Data Port Pins P[15:0]
Format and Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
YCrCb[7:0]OUT
Y[7:0]OUT
CrCb[7:0]OUT
Table 97. ADV7180 LFCSP-40 P7 to P0 Output/Input Pin Mapping
Data Port Pins P[7:0]
Format and Mode
7
6
5
4
3
2
1
0
Video Out, 8-Bit, 4:2:2
YCrCb[7:0]OUT
Table 98. ADV7180 Standard Definition Pixel Port Modes
ADV7180 LQFP-64 P[15: 0]
P[15:8] P[7: 0]
ADV7180 LFCSP-40
P[7: 0]
OF_SEL[3:0]
0000 to 0001
0010
0011 (Default)
0100 to 1111
Format
Reserved
Reserved, do not use
16-bit @ LLC2 4:2:2
8-bit @ LLC1 4:2:2 (default)
Reserved
Y[7:0]
CrCb[7:0]
Not valid
YCrCb[7:0]
YCrCb[7:0]
Three-state
Reserved, do not use
Rev. A | Page 72 of 112
ADV7180
GPO CONTROL
The ADV7180 LQFP-64 has four general-purpose outputs
(GPO). These outputs allow the user to control other devices in
a system via the I2C port of the ADV7180 LQFP-64.
Table 99. General-Purpose Output Truth Table
GPO_Enable GPO[3:0] GPO3 GPO2 GPO1
GPO0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XXXX
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Z
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Z
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The ADV7180 LFCSP-40 does not have GPO pins.
GPO_Enable, General Purpose Output Enable,
Address 0x59[4]
When GPO_Enable is set to 0, all four GPO pins are three-stated.
When GPO_Enable is set to 1, all four GPO pins are in a driven
state. The polarity output from each GPO is controlled by
GPO[3:0].
GPO[3:0], General Purpose Outputs, Address 0x59 [3:0]
Individual control of the four GPO ports is achieved using
GPO[3:0].
GPO_Enable must be set to 1 for the GPO pins to become
active.
GPO[0]
When GPO[0] is set to 0, a Logic Level 0 is output from the
GPO0 pin [Pin 13]
When GPO[0] is set to 1, a Logic Level 1 is output from the
GPO0 pin.
GPO[1]
When GPO[1] is set to 0, a Logic Level 0 is output from the
GPO1 pin [Pin 12].
When GPO[1] is set to 1, a Logic Level 1 is output from the
GPO1 pin.
GPO[2]
When GPO[2] is set to 0, a Logic Level 0 is output from the
GPO2 pin [Pin 56].
When GPO[2] is set to 1, a Logic Level 1 is output from the
GPO2 pin.
GPO[3]
When GPO[3] is set to 0, a Logic Level 0 is output from the
GPO3 pin [Pin 55].
When GPO[3] is set to 1, a Logic Level 1 is output from the
GPO3 pin.
Rev. A | Page 73 of 112
ADV7180
MPU PORT DESCRIPTION
The ADV7180 supports a 2-wire (I2C-compatible) serial inter-
face. Two inputs, serial data (SDA) and serial clock (SCLK),
carry information between the ADV7180 and the system I2C
master controller. Each slave device is recognized by a unique
address. The ADV7180 I2C port allows the user to set up and
configure the decoder and to read back captured VBI data. The
ADV7180 has four possible slave addresses for both read and
write operations, depending on the logic level of the ALSB pin.
The four unique addresses are shown in Table 100. The ADV7180
ALSB pin controls Bit 1 of the slave address. By altering the ALSB,
it is possible to control two ADV7180s in an application without
having the conflict of using the same slave address. The LSB (Bit 0)
sets either a read or write operation. Logic 1 corresponds to a
read operation; Logic 0 corresponds to a write operation.
first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADV7180 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
W
address plus the R/ bit. The device has 249 subaddresses to
enable access to the internal registers. It therefore interprets the
first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A
data transfer is always terminated by a stop condition. The user
can also access any unique subaddress register on a one-by-one
basis without updating all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLK high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7180 does
not issue an acknowledge and returns to the idle condition.
Table 100. I2C Address for ADV7180
R/W
ALSB
Slave Address
0x40
0x41
0x42
0x43
0
0
1
1
0
1
0
1
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing
a start condition, which is defined by a high-to-low transition
on SDA while SCLK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
In auto-increment mode, if the user exceeds the highest
subaddress, the following action is taken:
•
In read mode, the highest subaddress register contents
continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. A no
acknowledge condition is when the SDA line is not pulled
low on the ninth pulse.
and shift the next eight bits (the 7-bit address plus the R/ bit).
W
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCLK lines for the start
•
In write mode, the data for the invalid byte is not loaded
into any subaddress register. A no acknowledge is issued by
the ADV7180, and the part returns to the idle condition.
condition and the correct transmitted address. The R/ bit
W
determines the direction of the data. Logic 0 on the LSB of the
SDATA
SCLOCK
S
P
1–7
8
9
1–7
8
9
1–7
DATA
8
9
START ADDR R/W ACK SUBADDRESS ACK
ACK
STOP
Figure 48. Bus Data Transfer
WRITE
S
S
SLAVE ADDR A(S) SUB ADDR
LSB = 0
A(S)
DATA
A(S)
DATA
A(M)
A(S) P
SEQUENCE
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S) SUB ADDR
A(S)
S
SLAVE ADDR A(S)
DATA
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 49. Read and Write Sequence
Rev. A | Page 74 of 112
ADV7180
Register Select (SR7 to SR0)
REGISTER ACCESS
The MPU can write to or read from all of the ADV7180
registers except the subaddress register, which is write only. The
subaddress register determines which register the next read or
write operation accesses. All communications with the part
through the bus start with an access to the subaddress register.
Then a read/write operation is performed from or to the target
address, which increments to the next address until a stop
command on the bus is performed.
These bits are set up to point to the required starting address.
I2C SEQUENCER
An I2C sequencer is used when a parameter exceeds eight bits
and is therefore distributed over two or more I2C registers, for
example, HSB [11:0].
When such a parameter is changed using two or more I2C write
operations, the parameter may hold an invalid value for the
time between the first I2C being completed and the last I2C
being completed. In other words, the top bits of the parameter
may hold the new value while the remaining bits of the parameter
still hold the previous value.
To avoid this problem, the I2C sequencer holds the updated bits
of the parameter in local memory, and all bits of the parameter
are updated together once the last register write operation has
completed.
The correct operation of the I2C sequencer relies on the
following:
REGISTER PROGRAMMING
The following sections describe the configuration for each
register. The communication register is an 8-bit, write-only
register. After the part has been accessed over the bus and a
read/write operation is selected, the subaddress is set up. The
subaddress register determines to or from which register the
operation takes place. Table 101 lists the various operations
under the control of the subaddress register for the control port.
SUB_USR_EN, Address 0x0E [5]
This bit splits the register map at Register 0x40.
•
All I2C registers for the parameter in question must be
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35,
and so on.
USER MAP
USER SUB MAP
2
COMMON I C SPACE
ADDRESS 0x00 ≥ 0x3F
•
No other I2C can take place between the two (or more) I2C
writes for the sequence. For example, for HSB[10:0], write
to Address 0x34 first, immediately followed by 0x35, and
so on.
ADDRESS 0x0E BIT 5 = 0b
ADDRESS 0x0E BIT 5 = 1b
2
2
I C SPACE
I C SPACE
ADDRESS 0x40 ≥ 0xFF
ADDRESS 0x40 ≥ 0x9C
NORMAL REGISTER SPACE
INTERRUPT AND VDP REGISTER SPACE
Figure 50. Register Access—User Map and User Sub Map
Rev. A | Page 75 of 112
ADV7180
I2C REGISTER MAPS
Table 101. Main Register Map Details
Address
Reset
Value
Dec Hex Register Name
RW 7
6
5
4
3
2
1
0
(Hex)
0
1
3
4
5
6
7
8
9
00 Input Control
01 Video Selection
03 Output Control
RW VID_SEL[3]
RW
VID_SEL[2]
ENHSPLL
TOD
VID_SEL[1]
BETACAM
OF_SEL[3]
VID_SEL[0]
INSEL[3]
ENVSPROC
OF_SEL[1]
TIM_OE
INSEL[2]
INSEL[1]
INSEL[0]
00000000 00
11001000 C8
00001100 0C
01xx0101 45
RW VBI_EN
OF_SEL[2]
OF_SEL[0]
BL_C_VBI
SD_DUP_AV
RANGE
04 Extended Output Control RW BT.656-4
05 Reserved
EN_SFL_PIN
06 Reserved
07 Autodetect Enable
08 Contrast
RW AD_SEC525_EN AD_SECAM_EN AD_N443_EN AD_P60_EN
AD_PALN_EN AD_PALM_EN
AD_NTSC_EN AD_PAL_EN
01111111 7F
10000000 80
RW CON[7]
CON[6]
CON[5]
CON[4]
CON[3]
CON[2]
CON[1]
CON[0]
09 Reserved
10 0A Brightness
11 0B Hue
RW BRI[7]
BRI[6]
BRI[5]
BRI[4]
BRI[3]
BRI[2]
BRI[1]
BRI[0]
00000000 00
00000000 00
00110110 36
RW HUE[7]
RW DEF_Y[5]
HUE[6]
DEF_Y[4]
HUE[5]
DEF_Y[3]
HUE[4]
DEF_Y[2]
HUE[3]
DEF_Y[1]
HUE[2]
DEF_Y[0]
HUE[1]
HUE[0]
12 0C Default Value Y
DEF_VAL_
AUTO_EN
DEF_VAL_EN
13 0D Default Value C
14 0E ADI Control 1
15 0F Power Management
16 10 Status 1
RW DEF_C[7]
DEF_C[6]
DEF_C[5]
DEF_C[4]
DEF_C[3]
DEF_C[2]
PDBP
DEF_C[1]
DEF_C[0]
01111100 7C
00000000 00
00000000 00
SUB_USR_EN
PWRDWN
RW RESET
R
COL_KILL
IDENT[7]
AD_RESULT[2] AD_RESULT[1] AD_RESULT[0] FOLLOW_PW FSC_LOCK
LOST_LOCK
IDENT[1]
MVCS T3
GEMD
IN_LOCK
---
---
17 11 IDENT
R
IDENT[6]
IDENT[5]
IDENT[4]
LL NSTD
IDENT[3]
IDENT[2]
IDENT[0]
00011011 1B
18 12 Status 2
R
FSC NSTD
MV AGC DET MV PS DET
MVCS DET
INST_HLOCK
---
---
---
---
19 13 Status 3
R
PAL_SW_LOCK INTERLACED
DCT[1]
STD FLD LEN FREE_RUN_ACT CVBS
SD_OP_50Hz
20 14 Analog Clamp Control
21 15 Digital Clamp Control
22 16 Reserved
RW
RW
CCLEN
DCT[0]
00010010 12
0000xxxx 00
23 17 Shaping Filter Control 1 RW CSFM[2]
24 18 Shaping Filter Control 2 RW WYSFMOVR
CSFM[1]
CSFM[0]
YSFM[4]
YSFM[3]
YSFM[2]
YSFM[1]
YSFM[0]
00000001 01
10010011 93
11110001 F1
01000xxx 40
01011000 58
11100001 E1
10101110 AE
11110100 F4
00000000 00
1111xxxx F0
xxxxxxxx 00
00010010 12
01000001 41
10000100 84
00000000 00
00000010 02
00000000 00
00000001 01
10000000 80
11000000 C0
00010000 10
WYSFM[4]
WYSFM[3]
NSFSEL[1]
WYSFM[2]
NSFSEL[0]
WYSFM[1]
PSFSEL[1]
WYSFM[0]
PSFSEL[0]
25 19 Comb Filter Control
29 1D ADI Control 2
RW
RW TRI_LLC
RW SWPC
RW
EN28XTAL
39 27 Pixel Delay Control
43 2B Misc Gain Control
44 2C AGC Mode Control
45 2D Chroma Gain Control 1
46 2E Chroma Gain Control 2
47 2F Luma Gain Control 1
48 30 Luma Gain Control 2
49 31 VSYNC Field Control 1
50 32 VSYNC Field Control 2
51 33 VSYNC Field Control 3
AUTO_PDC_EN CTA[2]
CKE
CTA[1]
CTA[0]
LTA[1]
LTA[0]
PW_UPD
CAGC[0]
CMG[8]
CMG[0]
LMG[8]
LMG[0]
RW
LAGC[2]
CAGT[0]
CMG[6]
LAGT[0]
LMG[6]
LAGC[1]
CMG[5]
LMG[5]
LAGC[0]
CMG[4]
LMG[4]
CAGC[1]
CMG[9]
CMG[1]
LMG[9]
LMG[1]
W
CAGT[1]
CMG[7]
LAGT[1]
LMG.7
CMG[11]
CMG[3]
LMG[11]
LMG[3]
CMG[10]
CMG[2]
LMG[10]
LMG[2]
W
W
W
RW
NEWAVMODE HVSTIM
RW VSBHO
RW VSEHO
VSBHE
VSEHE
HSB[10]
HSB[6]
HSE[6]
52 34 HSYNC Position Control 1 RW
HSB[9]
HSB[5]
HSE[5]
PVS
HSB[8]
HSE[10]
HSB[2]
HSE[2]
HSE[9]
HSB[1]
HSE[1]
HSE[8]
HSB[0]
HSE[0]
PCLK
53 35 HSYNC Position Control 2 RW HSB.7
54 36 HSYNC Position Control 3 RW HSE.7
HSB[4]
HSE[4]
HSB[3]
HSE[3]
55 37 Polarity
RW PHS
PF
56 38 NTSC Comb Control
57 39 PAL Comb Control
58 3A ADC Control
RW CTAPSN[1]
RW CTAPSP[1]
RW
CTAPSN[0]
CTAPSP[0]
CCMN[2]
CCMP[2]
CCMN[1]
CCMP[1]
CCMN[0]
CCMP[0]
MUX_0_PD
YCMN[2]
YCMP[2]
YCMN[1]
YCMP[1]
YCMN[0]
YCMP[0]
MUX_1_PD
MUX_2_PD
MUX PDN
Override
61 3D Manual Window Control RW
CKILLTHR[2]
SFL_INV
CKILLTHR[1] CKILLTHR[0]
GDECEL[13] GDECEL[12]
01110010 B2
00000001 01
00000000 00
00000000 00
00000000 00
00000000 00
xxxx0000 00
11101111 EF
00001000 08
00001000 08
00100100 24
00000000 00
65 41 Resample Control
72 48 Gemstar Control 1
73 49 Gemstar Control 2
74 4A Gemstar Control 3
75 4B Gemstar Control 4
76 4C Gemstar Control 5
77 4D CTI DNR Control 1
78 4E CTI DNR Control 2
80 50 CTI DNR Control 4
81 51 Lock Count
RW
RW GDECEL[15]
RW GDECEL[7]
RW GDECOL[15]
RW GDECOL[7]
RW
GDECEL[14]
GDECEL[6]
GDECOL[14]
GDECOL[6]
GDECEL[11]
GDECEL[3]
GDECOL[11]
GDECOL[3]
GDECEL[10]
GDECEL[2]
GDECOL[10]
GDECOL[2]
GDECEL[9]
GDECEL[1]
GDECOL[9]
GDECOL[1]
GDECEL[8]
GDECEL[0]
GDECOL[8]
GDECOL[0]
GDECAD
GDECEL[5]
GDECEL[4]
GDECOL[13] GDECOL[12]
GDECOL[5]
DNR_EN
GDECOL[4]
RW
CTI_AB.1
CTI_C_TH[3]
DNR_TH[3]
COL[0]
CTI_AB.0
CTI_AB_EN
CTI_EN
RW CTI_C_TH[7]
RW DNR_TH[7]
RW FSCLE
RW
CTI_C_TH[6]
DNR_TH[6]
SRLS
CTI_C_TH[5] CTI_C_TH[4]
CTI_C_TH[2]
DNR_TH[2]
CIL[2]
CTI_C_TH[1] CTI_C_TH[0]
DNR_TH[5]
COL[2]
DNR_TH[4]
COL[1]
DNR_TH[1]
CIL[1]
DNR_TH[0]
CIL[0]
88 58 VS/FIELD Pin Control1
ADC sampling control
VS/FIELD
89 59 General-Purpose O/P2
143 8F Free-Run Line Length 1
RW
W
GPO_Enable
GPO[3]
GPO[2]
GPO[1]
GPO[0]
00000000 00
00000000 00
LLC_PAD_
SEL_MAN
LLC_PAD_
SEL[1]
LLC_PAD_
SEL[0]
144 90 VBI INFO
153 99 CCAP 1
R
CCAPD
R
CCAP1[7]
CCAP1[6]
CCAP1[5]
CCAP1[4]
CCAP1[3]
CCAP1[2]
CCAP1[1]
CCAP1[0]
–
–
Rev. A | Page 76 of 112
ADV7180
Address
Reset
Dec Hex Register Name
154 9A CCAP 2
RW 7
6
5
4
3
2
1
0
Value
(Hex)
R
CCAP2[7]
CCAP2[6]
LB_LCT[6]
LB_LCM[6]
LB_LCB[6]
CCAP2[5]
LB_LCT[5]
LB_LCM[5]
LB_LCB[5]
CCAP2[4]
LB_LCT[4]
LB_LCM[4]
LB_LCB[4]
CCAP2[3]
LB_LCT[3]
LB_LCM[3]
LB_LCB[3]
CCAP2[2]
LB_LCT[2]
LB_LCM[2]
LB_LCB[2]
CRC_ENABLE
MUX0[2]
MUX2[2]
LB_TH[2]
LB_EL[2]
CCAP2[1]
LB_LCT[1]
LB_LCM[1]
LB_LCB[1]
CCAP2[0]
LB_LCT[0]
LB_LCM[0]
LB_LCB[0]
–
–
–
–
–
–
–
–
155 9B Letterbox 1
R
LB_LCT[7]
LB_LCM[7]
LB_LCB[7]
156 9C Letterbox 2
R
157 9D Letterbox 3
R
178 B2 CRC
W
00011100 1C
xxxxxxxx 00
0xxxxxxx 00
10101100 AC
01001100 4C
195 C3 ADC Switch 1
196 C4 ADC Switch 2
220 DC Letterbox Control 1
221 DD Letterbox Control 2
222 DE ST Noise Readback 1
223 DF ST Noise Readback 2
224 E0 Reserved
RW MUX1[3]
MUX1[2]
MUX1[1]
LB_SL[1]
MUX1[0]
MUX0[3]
MUX2[3]
LB_TH[3]
LB_EL[3]
MUX0[1]
MUX2[1]
LB_TH[1]
LB_EL[1]
MUX0[0]
MUX2[0]
LB_TH[0]
LB_EL[0]
RW MAN_MUX_EN
RW
LB_TH[4]
LB_SL[0]
RW LB_SL[3]
R
LB_SL.2
ST_NOISE_VLD ST_NOISE[10]
ST_NOISE[3] ST_NOISE[2]
ST_NOISE[9] ST_NOISE[8]
ST_NOISE[1] ST_NOISE[0]
–
–
–
–
R
ST_NOISE[7]
ST_NOISE.6
ST_NOISE[5] ST_NOISE[4]
225 E1 SD Offset Cb
226 E2 SD Offset Cr
227 E3 SD Saturation Cb
228 E4 SD Saturation Cr
229 E5 NTSC V Bit Begin
230 E6 NTSC V Bit End
231 E7 NTSC F Bit Toggle
232 E8 PAL V Bit Begin
233 E9 PAL V Bit End
234 EA PAL F Bit Toggle
235 EB Vblank Control 1
236 EC Vblank Control 2
243 F3 AFE_CONTROL 1
RW SD_OFF_CB[7] SD_OFF_CB[6] SD_OFF_CB[5] SD_OFF_CB[4] SD_OFF_CB[3] SD_OFF_CB[2]
RW SD_OFF_CR[7] SD_OFF_CR[6] SD_OFF_CR[5] SD_OFF_CR[4] SD_OFF_CR[3] SD_OFF_CR[2]
RW SD_SAT_CB[7] SD_SAT_CB[6] SD_SAT_CB[5] SD_SAT_CB[4] SD_SAT_CB[3] SD_SAT_CB[2]
RW SD_SAT_CR[7] SD_SAT_CR[6] SD_SAT_CR[5] SD_SAT_CR[4] SD_SAT_CR[3] SD_SAT_CR[2]
SD_OFF_CB[1] SD_OFF_CB[0]
SD_OFF_CR[1] SD_OFF_CR[0]
SD_SAT_CB[1] SD_SAT_CB[0]
SD_SAT_CR[1] SD_SAT_CR[0]
10000000 80
10000000 80
10000000 80
10000000 80
00100101 25
00000100 04
01100011 63
01100101 65
00010100 14
01100011 63
01010101 55
01010101 55
00000000 00
RW NVBEGDELO
RW NVENDDELO
RW NFTOGDELO
RW PVBEGDELO
RW PVENDDELO
RW PFTOGDELO
NVBEGDELE
NVENDDELE
NFTOGDELE
PVBEGDELE
PVENDDELE
PFTOGDELE
NVBEGSIGN NVBEG[4]
NVENDSIGN NVEND[4]
NFTOGSIGN NFTOG[4]
NVBEG[3]
NVEND[3]
NFTOG[3]
PVBEG[3]
PVEND[3]
PFTOG[3]
PVBIOLCM.1
NVBEG[2]
NVEND[2]
NFTOG[2]
PVBEG[2]
PVEND[2]
PFTOG[2]
PVBIOLCM.0
NVBEG[1]
NVEND[1]
NFTOG[1]
PVBEG[1]
PVEND[1]
PFTOG[1]
PVBIELCM.1
NVBEG[0]
NVEND[0]
NFTOG[0]
PVBEG[0]
PVEND[0]
PFTOG[0]
PVBIELCM.0
PVBEGSIGN
PVENDSIGN PVEND[4]
PFTOGSIGN PFTOG[4]
PVBEG[4]
RW NVBIOLCM[1] NVBIOLCM[0] NVBIELCM[1] NVBIELCM[0]
RW NVBIOCCM[1] NVBIOCCM[0] NVBIECCM[1] NVBIECCM[0] PVBIOCCM.1 PVBIOCCM.0
PVBIECCM.1 PVBIECCM.0
AA_FILT_EN[1] AA_FILT_EN[0]
RW
AA_FILT_
AA_FILT_EN[2]
MAN_OVR
244 F4 Drive Strength
248 F8 IF Comp Control
249 F9 VS Mode Control
RW
RW
RW
DR_STR[1]
DR_STR[0]
DR_STR_C[1] DR_STR_C[0]
IFFILTSEL[2]
DR_STR_S[1] DR_STR_S[0]
xx010101 15
00000000 00
00000011 03
IFFILTSEL[1]
IFFILTSEL[0]
VS_COAST_
MODE[1]
VS_COAST_
MODE[0]
EXTEND_VS_ EXTEND_VS_
MIN_FREQ
MAX_FREQ
251 FB Peaking Control
252 FC Coring Threshold
RW PEAKING_
GAIN[7]
PEAKING_
GAIN[6]
PEAKING_
GAIN[5]
PEAKING_
GAIN[4]
PEAKING_
GAIN[3]
PEAKING_
GAIN[2]
PEAKING_
GAIN[1]
PEAKING_
GAIN[0]
01000000 40
00000100 04
RW DNR_TH2[7]
DNR_TH2[6]
DNR_TH2[5] DNR_TH2[4]
DNR_TH2[3]
DNR_TH2[2]
DNR_TH2[1] DNR_TH2[0]
1 This feature applies to the ADV7180BCPZ 40-lead only because VS or field are shared on a single pin (Pin 37).
2 This feature applies to the ADV7180BSTZ 64-lead only.
Table 102. Interrupt System Register Map Details1
Address
Reset
Dec
Hex
Register Name
R/W
7
6
5
4
3
2
1
0
Value
(Hex)
64
40
Interrupt
Config. 1
RW
INTRQ_DUR_
SEL[1]
INTRQ_DUR_
SEL[0]
MV_INTRQ_
SEL[1]
MV_INTRQ_
SEL[0]
MPU_STIM_
INTRQ
INTRQ_OP_
SEL[1]
INTRQ_OP_SE
L[0]
0001x000
10
66
67
68
69
70
71
72
42
43
44
45
46
47
48
Interrupt
Status 1
R
MV_PS_CS_Q
SD_FR_
CHNG_Q
SD_UNLOCK
_Q
SD_LOCK_Q
–
–
Interrupt Clear 1
W
RW
R
MV_PS_CS_
CLR
SD_FR_
CHNG_CLR
SD_UNLOCK_
CLR
SD_LOCK_
CLR
x0000000
x0000000
–
00
00
–
Interrupt
Mask 1
MV_PS_CS_
MSKB
SD_FR_
CHNG_MSKB
SD_UNLOCK_
MSKB
SD_LOCK_
MSKB
Raw
Status 1
MPU_STIM_I
NTRQ
EVEN_FIELD
CCAPD
Interrupt
Status 2
R
MPU_STIM_
INTRQ_Q
SD_FIELD_
CHNGD_Q
GEMD_Q
CCAPD_Q
CCAPD_CLR
–
–
Interrupt Clear 2
W
RW
MPU_STIM_
INTRQ_CLR
SD_FIELD_
CHNGD_CLR
GEMD_CLR
GEMD_MSKB
0xx00000
0xx00000
00
00
Interrupt
Mask 2
MPU_STIM_
INTRQ_MSKB
SD_FIELD_
CHNGD_MSK
B
CCAPD_
MSKB
73
74
75
76
78
49
4A
4B
4C
4E
Raw
Status 2
R
SCM_LOCK
SD_H_LOCK
SD_V_LOCK
SD_OP_50Hz
–
–
Interrupt
Status 3
R
PAL_SW_LK_
CHNG_Q
SCM_LOCK_
CHNG_Q
SD_AD_
CHNG_Q
SD_H_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_Q
SD_OP_
CHNG_Q
–
–
Interrupt Clear 3
W
RW
R
PAL_SW_LK_
CHNG_CLR
SCM_LOCK_
CHNG_CLR
SD_AD_
CHNG_CLR
SD_H_LOCK_
CHNG_CLR
SD_V_LOCK_
CHNG_CLR
SD_OP_
CHNG_CLR
xx000000
xx000000
–
00
00
–
Interrupt
Mask 3
PAL_SW_LK_
CHNG_MSKB
SCM_LOCK_
CHNG_MSKB
SD_AD_
CHNG_MSKB
SD_H_LOCK_
CHNG_MSKB
SD_V_LOCK_
CHNG_MSKB
SD_OP_
CHNG_MSKB
Interrupt
Status 4
VDP_VITC_Q
VDP_GS_
VPS_PDC_
UTC_CHNG_
Q
VDP_CGMS_
WSS_
CHNGD_Q
VDP_CCAPD_
Q
79
4F
Interrupt Clear 4
W
VDP_VITC_
CLR
VDP_GS_
VPS_PDC_
UTC_CHNG_
CLR
VDP_CGMS_
WSS_CHNGD
_CLR
VDP_CCAPD_
CLR
00x0x0x0
00
Rev. A | Page 77 of 112
ADV7180
Address
Reset
Dec
Hex
Register Name
R/W
7
6
5
4
3
2
1
0
Value
(Hex)
80
50
Interrupt
Mask 4
RW
VDP_VITC_
MSKB
VDP_GS_
VPS_PDC_
UTC_CHNG_
MSKB
VDP_CGMS_
WSS_CHNGD_
MSKB
VDP_CCAPD_
MSKB
00x0x0x0
00
96
97
60
61
VDP_Config_1
VDP_Config_2
RW
RW
WST_PKT_
DECODE_
DISABLE
VDP_TTXT_
TYPE_MAN_
ENABLE
VDP_TTXT_
TYPE_MAN[1]
VDP_TTXT_
TYPE_MAN[0]
10001000
0001xx00
88
10
AUTO_
DETECT_GS_
TYPE
98
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
VDP_ADF_
Config_1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
ADF_ENABLE
ADF_MODE[1]
ADF_MODE[0]
ADF_SDID[5]
ADF_DID[4]
ADF_SDID[4]
ADF_DID[3]
ADF_DID[2]
ADF_DID[1]
ADF_DID[0]
00010101
0x101010
0xxx0000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
15
2A
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
99
VDP_ADF_
Config_2
DUPLICATE_
ADF
ADF_SDID[3]
ADF_SDID[2]
ADF_SDID[1]
ADF_SDID[0]
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VDP_LINE_00E
VDP_LINE_00F
VDP_LINE_010
VDP_LINE_011
VDP_LINE_012
VDP_LINE_013
VDP_LINE_014
VDP_LINE_015
VDP_LINE_016
VDP_LINE_017
VDP_LINE_018
VDP_LINE_019
VDP_LINE_01A
VDP_LINE_01B
VDP_LINE_01C
VDP_LINE_01D
VDP_LINE_01E
VDP_LINE_01F
VDP_LINE_020
VDP_LINE_021
MAN_LINE_
PGM
VBI_DATA_
P318[3]
VBI_DATA_
P318[2]
VBI_DATA_
P318[1]
VBI_DATA_
P318[0]
VBI_DATA_
P6_N23[3]
VBI_DATA_
P6_N23[2]
VBI_DATA_
P6_N23[1]
VBI_DATA_
P6_N23[0]
VBI_DATA_
P319_N286[3]
VBI_DATA_
P319_N286[2]
VBI_DATA_
P319_N286[1]
VBI_DATA_
P319_N286[0]
VBI_DATA_
P7_N24[3]
VBI_DATA_
P7_N24[2]
VBI_DATA_
P7_N24[1]
VBI_DATA_
P7_N24[0]
VBI_DATA_
P320_N287[3]
VBI_DATA_
P320_N287[2]
VBI_DATA_
P320_N287[1]
VBI_DATA_
P320_N287[0]
VBI_DATA_
P8_N25[3]
VBI_DATA_
P8_N25[2]
VBI_DATA_
P8_N25[1]
VBI_DATA_
P8_N25[0]
VBI_DATA_
P321_N288[3]
VBI_DATA_
P321_N288[2]
VBI_DATA_
P321_N288[1]
VBI_DATA_
P321_N288[0]
VBI_DATA_
P9[3]
VBI_DATA_
P9[2]
VBI_DATA_
P9[1]
VBI_DATA_
P9[0]
VBI_DATA_
P322[3]
VBI_DATA_
P322[2]
VBI_DATA_
P322[1]
VBI_DATA_
P322[0]
VBI_DATA_
P10[3]
VBI_DATA_
P10[2]
VBI_DATA_
P10.1
VBI_DATA_
P10[0]
VBI_DATA_
P323[3]
VBI_DATA_
P323[2]
VBI_DATA_
P323[1]
VBI_DATA_
P323[0]
VBI_DATA_
P11[3]
VBI_DATA_
P11[2]
VBI_DATA_
P11[1]
VBI_DATA_
P11[0]
VBI_DATA_
P324_N272[3]
VBI_DATA_
P324_N272[2]
VBI_DATA_
P324_N272[1]
VBI_DATA_
P324_N272[0]
VBI_DATA_
P12_N10[3]
VBI_DATA_
P12_N10[2]
VBI_DATA_
P12_N10[1]
VBI_DATA_
P12_N10[0]
VBI_DATA_
P325_N273[3]
VBI_DATA_
P325_N273[2]
VBI_DATA_
P325_N273[1]
VBI_DATA_
P325_N273[0]
VBI_DATA_
P13_N11[3]
VBI_DATA_
P13_N11[2]
VBI_DATA_
P13_N11[1]
VBI_DATA_
P13_N11[0]
VBI_DATA_
P326_N274[3]
VBI_DATA_
P326_N274[2]
VBI_DATA_
P326_N274[1]
VBI_DATA_
P326_N274[0]
VBI_DATA_
P14_N12[3]
VBI_DATA_
P14_N12[2]
VBI_DATA_
P14_N12[1]
VBI_DATA_
P14_N12[0]
VBI_DATA_
P327_N275[3]
VBI_DATA_
P327_N275[2]
VBI_DATA_
P327_N275[1]
VBI_DATA_
P327_N275[0]
VBI_DATA_
P15_N13[3]
VBI_DATA_
P15_N13[2]
VBI_DATA_
P15_N13[1]
VBI_DATA_
P15_N13[0]
VBI_DATA_
P328_N276[3]
VBI_DATA_
P328_N276[2]
VBI_DATA_
P328_N276[1]
VBI_DATA_
P328_N276[0]
VBI_DATA_
P16_N14[3]
VBI_DATA_
P16_N14[2]
VBI_DATA_
P16_N14[1]
VBI_DATA_
P16_N14[0]
VBI_DATA_
P329_N277[3]
VBI_DATA_
P329_N277[2]
VBI_DATA_
P329_N277[1]
VBI_DATA_
P329_N277[0]
VBI_DATA_
P17_N15[3]
VBI_DATA_
P17_N15[2]
VBI_DATA_
P17_N15[1]
VBI_DATA_
P17_N15[0]
VBI_DATA_
P330_N278[3]
VBI_DATA_
P330_N278[2]
VBI_DATA_
P330_N278[1]
VBI_DATA_
P330_N278[0]
VBI_DATA_
P18_N16[3]
VBI_DATA_
P18_N16[2]
VBI_DATA_
P18_N16[1]
VBI_DATA_
P18_N16[0]
VBI_DATA_
P331_N279[3]
VBI_DATA_
P331_N279[2]
VBI_DATA_
P331_N279[1]
VBI_DATA_
P331_N279[0]
VBI_DATA_
P19_N17[3]
VBI_DATA_
P19_N17[2]
VBI_DATA_
P19_N17[1]
VBI_DATA_
P19_N17[0]
VBI_DATA_
P332_N280[3]
VBI_DATA_
P332_N280[2]
VBI_DATA_
P332_N280[1]
VBI_DATA_
P332_N280[0]
VBI_DATA_
P20_N18[3]
VBI_DATA_
P20_N18[2]
VBI_DATA_
P20_N18[1]
VBI_DATA_
P20_N18[0]
VBI_DATA_
P333_N281[3]
VBI_DATA_
P333_N281[2]
VBI_DATA_
P333_N281[1]
VBI_DATA_
P333_N281[0]
VBI_DATA_
P21_N19[3]
VBI_DATA_
P21_N19[2]
VBI_DATA_
P21_N19[1]
VBI_DATA_
P21_N19[0]
VBI_DATA_
P334_N282[3]
VBI_DATA_
P334_N282[2]
VBI_DATA_
P334_N282[1]
VBI_DATA_
P334_N282[0]
VBI_DATA_
P22_N20[3]
VBI_DATA_
P22_N20[2]
VBI_DATA_
P22_N20[1]
VBI_DATA_
P22_N20[0]
VBI_DATA_
P335_N283[3]
VBI_DATA_
P335_N283[2]
VBI_DATA_P
335_N283[1]
VBI_DATA_
P335_N283[0]
VBI_DATA_
P23_N21[3]
VBI_DATA_
P23_N21[2]
VBI_DATA_
P23_N21[1]
VBI_DATA_
P23_N21[0]
VBI_DATA_
P336_N284[3]
VBI_DATA_
P336_N284[2]
VBI_DATA_
P336_N284[1]
VBI_DATA_
P336_N284[0]
VBI_DATA_
P24_N22[3]
VBI_DATA_
P24_N22[2]
VBI_DATA_
P24_N22[1]
VBI_DATA_
P24_N22[0]
VBI_DATA_
P337_N285[3]
VBI_DATA_
P337_N285[2]
VBI_DATA_
P337_N285[1]
VBI_DATA_
P337_N285[0]
VDP_STATUS_
CLEAR
VITC_CLEAR
GS_PDC_
VPS_UTC_
CLEAR
CGMS_WSS_
CLEAR
CC_CLEAR
120
78
VDP_STATUS
R
TTXT_AVL
VITC_AVL
GS_DATA_
TYPE
GS_PDC_
VPS_UTC_
AVL
CGMS_WSS_
AVL
CC_EVEN_
FIELD
CC_AVL
–
–
121
122
125
126
127
132
79
7A
7D
7E
7F
84
VDP_CCAP_
DATA_0
R
R
R
R
R
R
CCAP_
BYTE_1[7]
CCAP_
BYTE_1[6]
CCAP_
BYTE_1[5]
CCAP_
BYTE_1[4]
CCAP_
BYTE_1[3]
CCAP_
BYTE_1[2]
CCAP_
BYTE_1[1]
CCAP_
BYTE_1[0]
–
–
–
–
–
–
–
–
–
–
–
–
VDP_CCAP_
DATA_1
CCAP_
BYTE_2[7]
CCAP_
BYTE_2[6]
CCAP_
BYTE_2[5]
CCAP_
BYTE_2[4]
CCAP_
BYTE_2[3]
CCAP_
BYTE_2[2]
CCAP_
BYTE_2[1]
CCAP_
BYTE_2[0]
VDP_CGMS_
WSS_DATA_0
CGMS_
CRC[5]
CGMS_
CRC[4]
CGMS_
CRC[3]
CGMS_
CRC[2]
VDP_CGMS_
WSS_DATA_1
CGMS_
CRC[1]
CGMS_
CRC[0]
CGMS_
WSS[13]
CGMS_
WSS[12]
CGMS_
WSS[11]
CGMS_
WSS[10]
CGMS_
WSS[9]
CGMS_
WSS[8]
VDP_CGMS_
WSS_ DATA_2
CGMS_
WSS[7]
CGMS_
WSS[6]
CGMS_
WSS[5]
CGMS_
WSS[4]
CGMS_
WSS[3]
CGMS_
WSS[2]
CGMS_
WSS[1]
CGMS_
WSS[0]
VDP_GS_VPS_
PDC_UTC_0
GS_VPS_
PDC_UTC_
BYTE_0[7]
GS_VPS_
PDC_UTC_
BYTE_0[6]
GS_VPS_
PDC_UTC_
BYTE_0[5]
GS_VPS_
PDC_UTC_
BYTE_0[4]
GS_VPS_
PDC_UTC_
BYTE_0[3]
GS_VPS_
PDC_UTC_
BYTE_0[2]
GS_VPS_
PDC_UTC_
BYTE_0[1]
GS_VPS_
PDC_UTC_
BYTE_0[0]
133
134
85
86
VDP_GS_VPS_
PDC_UTC_1
R
R
GS_VPS_
PDC_UTC_
BYTE_1[7]
GS_VPS_
PDC_UTC_
BYTE_1[6]
GS_VPS_
PDC_UTC_
BYTE_1[5]
GS_VPS_
PDC_UTC_
BYTE_1[4]
GS_VPS_
PDC_UTC_
BYTE_1[3]
GS_VPS_
PDC_UTC_
BYTE_1[2]
GS_VPS_
PDC_UTC_
BYTE_1[1]
GS_VPS_
PDC_UTC_
BYTE_1[0]
–
–
–
–
VDP_GS_VPS_
PDC_UTC_2
GS_VPS_
PDC_UTC_
BYTE_2[7]
GS_VPS_
PDC_UTC_
BYTE_2[6]
GS_VPS_
PDC_UTC_
BYTE_2[5]
GS_VPS_
PDC_UTC_
BYTE_2[4]
GS_VPS_
PDC_UTC_
BYTE_2[3]
GS_VPS_
PDC_UTC_
BYTE_2[2]
GS_VPS_
PDC_UTC_
BYTE_2[1]
GS_VPS_
PDC_UTC_
BYTE_2[0]
Rev. A | Page 78 of 112
ADV7180
Address
Dec Hex
Reset
Register Name
R/W
7
6
5
4
3
2
1
0
Value
(Hex)
135
136
137
138
139
140
141
142
143
144
87
88
89
8A
8B
8C
8D
8E
8F
90
VDP_GS_VPS_
PDC_UTC_3
R
GS_VPS_
PDC_UTC_
BYTE_3[7]
GS_VPS_
PDC_UTC_
BYTE_3.6
GS_VPS_
PDC_UTC_
BYTE_3.5
GS_VPS_
PDC_UTC_
BYTE_3.4
GS_VPS_
PDC_UTC_
BYTE_3[3]
GS_VPS_
PDC_UTC_
BYTE_3[2]
GS_VPS_
PDC_UTC_
BYTE_3[1]
GS_VPS_
PDC_UTC_
BYTE_3[0]
–
–
VDP_VPS_
PDC_UTC_4
R
R
R
R
R
R
R
R
R
VPS_
PDC_UTC_
BYTE_4[7]
VPS_
PDC_UTC_
BYTE_4[6]
VPS_
PDC_UTC_
BYTE_4[5]
VPS_
PDC_UTC_
BYTE_4[4]
VPS_
PDC_UTC_
BYTE_4[3]
VPS_
PDC_UTC_
BYTE_4[2]
VPS_
PDC_UTC_
BYTE_4[1]
VPS_
PDC_UTC_
BYTE_4[0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VDP_VPS_
PDC_UTC_5
VPS_
PDC_UTC_
BYTE_5[7]
VPS_
PDC_UTC_
BYTE_5[6]
VPS_
PDC_UTC_
BYTE_5[5]
VPS_
PDC_UTC_
BYTE_5[4]
VPS_
PDC_UTC_
BYTE_5[3]
VPS_
PDC_UTC_
BYTE_5[2]
VPS_
PDC_UTC_
BYTE_5[1]
VPS_
PDC_UTC_
BYTE_5[0]
VDP_VPS_
PDC_UTC_6
VPS_
PDC_UTC_
BYTE_6[7]
VPS_
PDC_UTC_
BYTE_6[6]
VPS_
PDC_UTC_
BYTE_6[5]
VPS_
PDC_UTC_
BYTE_6[4]
VPS_
PDC_UTC_
BYTE_6[3]
VPS_
PDC_UTC_
BYTE_6[2]
VPS_
PDC_UTC_
BYTE_6[1]
VPS_
PDC_UTC_
BYTE_6[0]
VDP_VPS_
PDC_UTC_7
VPS_
PDC_UTC_
BYTE_7[7]
VPS_
PDC_UTC_
BYTE_7[6]
VPS_
PDC_UTC_
BYTE_7[5]
VPS_
PDC_UTC_
BYTE_7[4]
VPS_
PDC_UTC_
BYTE_7[3]
VPS_
PDC_UTC_
BYTE_7[2]
VPS_
PDC_UTC_
BYTE_7[1]
VPS_
PDC_UTC_
BYTE_7[0]
VDP_VPS_
PDC_UTC_8
VPS_
PDC_UTC_
BYTE_8[7]
VPS_
PDC_UTC_
BYTE_8[6]
VPS_
PDC_UTC_
BYTE_8[5]
VPS_
PDC_UTC_
BYTE_8[4]
VPS_
PDC_UTC_
BYTE_8[3]
VPS_
PDC_UTC_
BYTE_8[2]
VPS_
PDC_UTC_
BYTE_8[1]
VPS_
PDC_UTC_
BYTE_8[0]
VDP_VPS_
PDC_UTC_9
VPS_
PDC_UTC_
BYTE_9[7]
VPS_
PDC_UTC_
BYTE_9[6]
VPS_
PDC_UTC_
BYTE_9[5]
VPS_
PDC_UTC_
BYTE_9[4]
VPS_
PDC_UTC_
BYTE_9[3]
VPS_
PDC_UTC_
BYTE_9[2]
VPS_
PDC_UTC_
BYTE_9[1]
VPS_
PDC_UTC_
BYTE_9[0]
VDP_VPS_
PDC_UTC_10
VPS_
PDC_UTC_
BYTE_10[7]
VPS_
PDC_UTC_
BYTE_10[6]
VPS_
PDC_UTC_
BYTE_10[5]
VPS_
PDC_UTC_
BYTE_10[4]
VPS_
PDC_UTC_
BYTE_10[3]
VPS_
PDC_UTC_
BYTE_10[2]
VPS_
PDC_UTC_
BYTE_10[1]
VPS_
PDC_UTC_
BYTE_10[0]
VDP_VPS_
PDC_UTC_11
VPS_
PDC_UTC_
BYTE_11[7]
VPS_
PDC_UTC_
BYTE_11[6]
VPS_
PDC_UTC_
BYTE_11[5]
VPS_
PDC_UTC_
BYTE_11[4]
VPS_
PDC_UTC_
BYTE_11[3]
VPS_
PDC_UTC_
BYTE_11[2]
VPS_
PDC_UTC_
BYTE_11[1]
VPS_
PDC_UTC_
BYTE_11[0]
VDP_VPS_
PDC_UTC_12
VPS_
PDC_UTC_
BYTE_12[7]
VPS_
PDC_UTC_
BYTE_12[6]
VPS_
PDC_UTC_
BYTE_12[5]
VPS_
PDC_UTC_
BYTE_12[4]
VPS_
PDC_UTC_
BYTE_12[3]
VPS_
PDC_UTC_
BYTE_12[2]
VPS_
PDC_UTC_
BYTE_12[1]
VPS_
PDC_UTC_
BYTE_12[0]
146
147
148
149
150
151
152
153
154
155
156
92
93
94
95
96
97
98
99
9A
9B
9C
VDP_VITC_
DATA_0
R
VITC_
DATA_0[7]
VITC_
DATA_0[6]
VITC_
DATA_0[5]
VITC_
DATA_0[4]
VITC_
DATA_0[3]
VITC_
DATA_0[2]
VITC_
DATA_0[1]
VITC_
DATA_0[0]
–
–
–
–
–
–
–
–
–
–
–
30
VDP_VITC_
DATA_1
R
VITC_
DATA_1[7]
VITC_
DATA_1[6]
VITC_
DATA_1[5]
VITC_
DATA_1[4]
VITC_
DATA_1[3]
VITC_
DATA_1[2]
VITC_
DATA_1[1]
VITC_
DATA_1[0]
–
VDP_VITC_
DATA_2
R
VITC_
DATA_2[7]
VITC_
DATA_2[6]
VITC_
DATA_2[5]
VITC_
DATA_2[4]
VITC_
DATA_2[3]
VITC_
DATA_2[2]
VITC_
DATA_2[1]
VITC_
DATA_2[0]
–
VDP_VITC_
DATA_3
R
VITC_
DATA_3[7]
VITC_
DATA_3[6]
VITC_
DATA_3[5]
VITC_
DATA_3[4]
VITC_
DATA_3[3]
VITC_
DATA_3[2]
VITC_
DATA_3[1]
VITC_
DATA_3[0]
–
VDP_VITC_
DATA_4
R
VITC_
DATA_4[7]
VITC_
DATA_4[6]
VITC_
DATA_4[5]
VITC_
DATA_4[4]
VITC_
DATA_4[3]
VITC_
DATA_4[2]
VITC_
DATA_4[1]
VITC_
DATA_4[0]
–
VDP_VITC_
DATA_5
R
VITC_
DATA_5[7]
VITC_
DATA_5[6]
VITC_
DATA_5[5]
VITC_
DATA_5[4]
VITC_
DATA_5[3]
VITC_
DATA_5[2]
VITC_
DATA_5[1]
VITC_
DATA_5[0]
–
VDP_VITC_
DATA_6
R
VITC_
DATA_6[7]
VITC_
DATA_6[6]
VITC_
DATA_6[5]
VITC_
DATA_6[4]
VITC_
DATA_6[3]
VITC_
DATA_6[2]
VITC_
DATA_6[1]
VITC_
DATA_6[0]
–
VDP_VITC_
DATA_7
R
VITC_
DATA_7[7]
VITC_
DATA_7[6]
VITC_
DATA_7[5]
VITC_
DATA_7[4]
VITC_
DATA_7[3]
VITC_
DATA_7[2]
VITC_DATA_
7[1]
VITC_
DATA_7[0]
–
VDP_VITC_
DATA_8
R
VITC_
DATA_8[7]
VITC_
DATA_8[6]
VITC_
DATA_8[5]
VITC_
DATA_8[4]
VITC_
DATA_8[3]
VITC_
DATA_8[2]
VITC_
DATA_8[1]
VITC_
DATA_8[0]
–
VDP_VITC_
CALC_CRC
R
VITC_CRC[7]
VITC_CRC[6]
VITC_CRC.5
VITC_CRC[4]
VITC_CRC[3]
VITC_CRC[2]
VITC_CRC[1]
VITC_CRC[0]
–
VDP_OUTPUT_
SEL
RW
I2C_GS_
VPS_PDC_
UTC[1]
I2C_GS_
VPS_PDC_
UTC[0]
GS_VPS_
PDC_UTC_
CB_CHANGE
WSS_CGMS_
CB_CHANGE
00110000
1 To access the registers listed in Table 102, SUB_USR_EN in Register Address 0x0E must be programmed to 1.
Rev. A | Page 79 of 112
ADV7180
Table 103. Register Map Descriptions (Normal Operation)
Bits (Shading Indicates Default
State)
Comments
LQFP-64
Subaddress Register
0x00 Input Control
Bit Description
Notes
7
6
5
4
3
0
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
LFCSP-40
Composite
Reserved
Reserved
Composite
Composite
Reserved
S-Video
INSEL [3:0]. The INSEL
bits allow the user to
select an input channel
and the input format.
Composite
Composite
Composite
Composite
Composite
Composite
S-Video
Refer to Table 9 and
Table 8 for full routing
details.
Mandatory write required
for Y/C (S-video mode)
Reg 0x58 = 0x04; see
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
S-Video
S-Video
YPrPb
Reserved
Reserved
YPrPb
Reg 0x58 for bit description
YPrPb
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VID_SEL [3:0]. The
0
0
0
0
0
0
0
1
Autodetect PAL B/G/H/I/D,
NTSC (without pedestal),
SECAM
VID_SEL bits allow the
user to select the input
video standard.
Autodetect PAL B/G/H/I/D,
NTSC M (with pedestal),
SECAM
0
0
0
0
1
1
0
1
Autodetect PAL N, NTSC M
(without pedestal), SECAM
Autodetect PAL N, NTSC M
(with pedestal), SECAM
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/G/H/I/D
PAL N (B/G/H/I/D without
pedestal)
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N
(with pedestal)
1
1
1
1
1
1
0
1
SECAM
SECAM (with pedestal)
Set to default
0x01
Video Selection
Reserved.
0
0
0
ENVSPROC.
0
1
Disable vsync processor
Enable vsync processor
Set to default
Reserved.
BETACAM.
0
0
1
Standard video input
Betacam input enable
Disable hsync processor
Enable hsync processor
Set to default
ENHSPLL.
Reserved.
0
1
1
Rev. A | Page 80 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
0x03 Output Control
Bit Description
Notes
7
6
5
4
3
2
1
0
SD_DUP_AV.
0
AV codes to suit 8-bit
Duplicates the AV
codes from the luma
into the chroma path.
interleaved data output
1
AV codes duplicated
(for 16-bit interfaces)
Reserved.
0
Set as default
Reserved
OF_SEL [3:0]. Allows
the user to choose
from a set of output
formats.
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Reserved
16-bit @ LLC1 4:2:2
Options apply to
ADV7180 LQFP-64 only
8-bit @ LLC1 4:2:2
ITU-R BT.656
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Output pins enabled
TOD. Three-state
output drivers. This bit
allows the user to
three-state the output
drivers: P[19:0], HS, VS,
FIELD, and SFL.
0
1
See also TIM_OE
and TRI_LLC
Drivers three-stated
VBI_EN. Allows VBI data
(Lines 1 to 21) to be
passed through with
only a minimum
0
1
All lines filtered and scaled
Only active video region
filtered
amount of filtering
performed.
0x04
Extended Output
Control
RANGE. Allows the user
to select the range of
output values. Can be
ITU-R BT.656 compliant,
or can fill the whole
accessible number
range.
0
1
16 < Y < 235, 16 < C < 240
1 < Y < 254, 1 < C < 254
ITU-R BT.656
Extended range
EN_SFL_PIN.
0
1
SFL output is disabled
SFL output enables
encoder and decoder
to be connected directly
SFL information output on
the SFL pin
BL_C_VBI. Blank
0
1
Decode and output color
Blank Cr and Cb
During VBI
chroma during VBI. If
set, it enables data in
the VBI region to be
passed through the
decoder undistorted.
TIM_OE. Timing signals
output enable.
0
1
HS, VS, F three-stated
HS, VS, F forced active
Controlled by TOD
Reserved.
Reserved.
x
x
1
BT.656-4. Allows the
user to select an
output mode
0
1
ITU-R BT.656-3 compatible
ITU-R BT.656-4 compatible
compatible with
ITU-R BT.656-3/4.
0x05
0x06
Reserved
Reserved
Rev. A | Page 81 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0
1
0x07
Autodetect Enable
AD_PAL_EN. PAL B/G/I/H
autodetect enable.
Disable
Enable
Disable
AD_NTSC_EN. NTSC
autodetect enable.
0
1
Enable
Disable
AD_PALM_EN. PAL M
autodetect enable.
0
1
Enable
Disable
AD_PALN_EN. PAL N
autodetect enable.
0
1
Enable
Disable
AD_P60_EN. PAL 60
autodetect enable.
0
1
Enable
Disable
AD_N443_EN.
NTSC 4.43 autodetect
enable.
0
1
Enable
Disable
AD_SECAM_EN. SECAM
autodetect enable.
0
1
Enable
Disable
AD_SEC525_EN.
SECAM 525 autodetect
enable.
0
1
1
Enable
0x08
Contrast Register
CON[7:0]. Contrast
adjust. This is the user
control for contrast
adjustment.
0
0
0
0
0
0
0
Luma gain = 1
0x00 gain = 0,
0x80 gain = 1,
0xFF gain = 2
0x09
0x0A
Reserved
Reserved.
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Brightness Register
BRI[7:0]. This register
controls the brightness
of the video signal.
0x00 = 0IRE,
0x7F = +100IRE,
0x80 = –100IRE
0x0B
0x0C
Hue Register
HUE[7:0].
0
0
0
0
0
0
0
0
Hue range = −90° to +90°
This register contains
the value for the color
hue adjustment.
Default Value Y
DEF_VAL_EN. Default
value enable.
0
1
Free-run mode dependent
on DEF_VAL_AUTO_EN
Force free-run mode on
and output blue screen
DEF_VAL_AUTO_EN.
Default value.
0
1
Disable free-run mode
When lock is lost, free-run
mode can be enabled to
output stable timing, clock,
and a set color
Enable automatic free-run
mode (blue screen)
DEF_Y[5:0]. Default
value Y. This register
holds the Y default
value.
0
0
0
1
1
1
1
1
0
0
1
0
1
1
0
Y[7:0] = {DEF_Y[5:0], 0, 0}
Default Y value output in
free-run mode
0x0D
0x0E
Default Value C
ADI Control
DEF_C[7:0]. Default
value C. The Cr and Cb
default values are
0
0
0
0
Cr[7:0] = DEF_C[7:4], 0, 0, 0, 0}
Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0}
Default Cb/Cr value output
in free-run mode; default
values give blue screen
output
defined in this register.
Reserved.
Set as default
SUB_USR_EN. Enables
user to access the
interrupt/VDP register
map.
0
1
Access main register space
See Figure 50
Access interrupt/VDP register
space
Reserved.
0
0
Set as default
Rev. A | Page 82 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Set to default
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0x0F
Power
Reserved.
0
0
Management
PDBP. Power-down
bit priority selects
between PWRDWN bit
or pin control.
0
1
Chip power-down
controlled by pin
Bit has priority
(pin disregarded)
Reserved.
0
0
Set to default
PWRDWN. Power-
down places the
decoder into a full
power-down mode.
0
1
System functional
Powered down
See PDBP, 0x0F Bit 2
Reserved.
0
Set to default
RESET. Chip reset, loads
all I2C bits with default
values.
0
1
Normal operation
Start reset sequence
Executing reset takes
approx. 2 ms; this bit is
self-clearing
0x10
Status Register 1
(Read Only)
IN_LOCK.
x
1 = in lock (now)
Provides information
about the internal status
of the decoder
LOST_LOCK.
FSC_LOCK.
FOLLOW_PW.
x
1 = lost lock (since last read)
1 = FSC lock (now)
x
x
1 = peak white
AGC mode active
AD_RESULT[2:0].
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NTSM M/J
Detected standard
Autodetection result
reports the standard of
the input video.
NTSC 4.43
PAL M
PAL 60
PAL B/G/H/I/D
SECAM
PAL Combination N
SECAM 525
1 = color kill is active
COL_KILL.
x
Color kill
0x11
0x12
IDENT (Read Only)
IDENT[7:0]. Provides
identification on the
revision of the part.
0
0
0
1
1
x
0
x
1
x
1
x
Power-up value = 0x1B
Status Register 2
(Read Only)
MVCS DET.
MVCS T3.
MV color striping detected
MV color striping type
1 = detected
0 = Type 2
1 = Type 3
MV PS DET.
MV AGC DET.
LL NSTD.
MV pseudosync detected
MV AGC pulses detected
Nonstandard line length
FSC frequency nonstandard
1 = detected
1 = detected
1 = detected
1 = detected
x
FSC NSTD.
Reserved.
x
x
x
0x13
Status Register 3
(Read Only)
INST_HLOCK.
x
1 = horizontal lock
achieved
Unfiltered
GEMD.
x
1 = Gemstar data detected
SD 60 Hz detected
SD_OP_50Hz.
0
1
SD field rate detect
SD 50 Hz detected
CVBS.
0
1
Y/C signal detected
Result of CVBS and
Y/C autodetection
CVBS signal detected
1 = free-run mode active
1 = field length standard
1 = interlaced video detected
1 = swinging burst detected
FREE_RUN_ACT.
STD FLD LEN.
INTERLACED.
x
Blue screen output
x
Correct field length found
Field sequence found
x
PAL_SW_LOCK.
x
Reliable swinging burst
sequence
0x14
Analog Clamp
Control
Reserved.
0
0
1
0
Set to default
CCLEN. Current clamp
enable allows the user
to switch off the
0
1
Current sources switched off
Current sources enabled
current sources in the
analog front.
Reserved.
0
0
0
Set to default
Rev. A | Page 83 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Set to default
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0x15
Digital Clamp
Reserved.
x
x
x
x
Control 1
Digital clamp freeze
(DCFE)
0
1
Digital clamp on
Digital clamp off
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
TC dependent on video
Set to default
DCT[1:0]. Digital clamp
timing determines the
time constant of the
digital fine clamp
circuitry.
0
0
1
1
0
1
0
1
Reserved.
0
0x17
Shaping Filter
Control
YSFM[4:0]. Selects Y
shaping filter mode in
CVBS-only mode.
0
0
0
0
0
0
0
0
0
1
Auto wide notch for poor
quality sources or wide-
band filter with comb for
good quality input
Auto narrow notch for poor
quality sources or wideband
filter with comb for good
quality input
Decoder selects optimum
Y shaping filter depending
on CVBS quality
Allows the user to
select a wide range of
low-pass and notch
filters.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
Auto selection 15.0 MHz
Auto selection 2.17 MHz
If one of these modes is
selected, the decoder does
not change filter modes;
depending on video
quality, a fixed filter
response (the one
If either auto mode is
selected, the decoder
selects the optimum Y
filter depending on the
CVBS video source
quality (good vs. bad).
selected) is used for good
and bad quality video
CSFM[2:0]. C shaping
filter mode allows
selection from a range
of low-pass chrominance
filters. If either auto
mode is selected, the
decoder selects the
optimum C filter
depending on the
CVBS video source
quality (good vs. bad).
Nonauto settings force
a C filter for all standards
and quality of CVBS
video.
0
0
0
0
0
1
Automatically selects a
C filter based on video
standard and quality
Selects a C filter for all
video standards and for
good and bad video
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
SH1
SH2
SH3
SH4
SH5
Wideband mode
Rev. A | Page 84 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
~
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
~
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
~
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
~
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
~
1
0x18
Shaping Filter
WYSFM[4:0]. Wideband
Y shaping filter mode
allows the user to
select which Y shaping
filter is used for the Y
component of Y/C,
YPrPb, B/W input
signals. It is also used
when a good quality
input CVBS signal is
detected. For all other
inputs, the Y shaping
filter chosen is
Reserved, do not use
Reserved, do not use
SVHS 1
Control 2
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
controlled by
YSFM[4:0].
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved, Do not use
Reserved, Do not use
Reserved, Do not use
Reserved.
0
0
Set to default
WYSFMOVR. Enables
the use of automatic
WYSFM filter.
0
1
Autoselection of best filter
Manual select filter using
WYSFM[4:0]
0x19
Comb Filter Control
PSFSEL[1:0]. Controls
the signal bandwidth
that is fed to the comb
filters (PAL).
0
0
1
1
0
1
0
1
Narrow
Medium
Wide
Widest
NSFSEL[1:0]. Controls
the signal bandwidth
that is fed to the comb
filters (NTSC).
0
0
1
1
0
1
0
1
Narrow
Medium
Medium
Wide
Reserved.
Reserved.
1
1
1
0
1
0
Set as default
Set to default
0x1D
ADI Control 2
0
x
x
x
EN28XTAL.
TRI_LLC.
0
1
Use 27 MHz crystal
Use 28 MHz crystal
LLC pin active
0
1
LLC pin three-stated
Rev. A | Page 85 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
No delay
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0x27
Pixel Delay Control
LTA[1:0]. Luma timing
adjust allows the user
to specify a timing
difference between
chroma and luma
samples.
0
0
CVBS mode LTA[1:0] = 00b,
S-video mode LTA[1:0] = 01b,
YPrPb mode LTA[1:0] = 01b
1
1
0
0
Luma 1 clock (37 ns) late
Luma 2 clock (74 ns) early
1
1
Luma 1 clock (37 ns) early
Reserved.
0
Set to 0
CTA[2:0]. Chroma
timing adjust allows
a specified timing
difference between
the luma and chroma
samples.
0
0
0
Not valid setting
CVBS mode CTA[2:0] = 011b,
S-Video mode CTA[2:0] = 101b,
YPrPb mode CTA[2:0] = 110b
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Chroma + 2 pixels (early)
Chroma + 1 pixel (early)
No delay
Chroma − 1 pixel (late)
Chroma − 2 pixels (late)
Chroma − 3 pixels (late)
Not valid setting
AUTO_PDC_EN.
Automatically
0
1
Use values in LTA[1:0] and
CTA[2:0] for delaying
luma/chroma
programs the LTA/CTA
values so that luma
and chroma are
aligned at the output
for all modes of
operation.
LTA and CTA values
determined automatically
SWPC. Allows the Cr
and Cb samples to be
swapped.
0
1
No swapping
See Swap_CR_CB_WB,
Addr 0x89
Swap the Cr and Cb O/P
samples
0x2B
Misc Gain Control
PW_UPD. Peak white
update determines the
rate of gain.
0
1
Update once per video line
Update once per field
Peak white must be
enabled; see LAGC[2:0]
Reserved.
1
0
0
0
0
Set to default
CKE. Color kill enable
allows the color kill
function to be
0
1
Color kill disabled
Color kill enabled
For SECAM color kill,
threshold is set at 8%;
see CKILLTHR[2:0]
switched on and off.
Reserved.
1
Set to default
0x2C
AGC Mode Control
CAGC[1:0]. Chroma
0
0
1
1
0
1
0
1
Manual fixed gain
Use luma gain for chroma
Automatic gain
Freeze chroma gain
Set to 1
Use CMG[11:0]
automatic gain control
selects the basic mode
of operation for the
AGC in the chroma path.
Based on color burst
Reserved.
1
1
LAGC[2:0]. Luma
automatic gain control
selects the mode of
operation for the gain
control in the luma
path.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Manual fixed gain
Reserved
Use LMG[11:0]
Peak white algorithm on
Reserved
Blank level to sync tip
Blank level to sync tip
Peak white algorithm off
Reserved
Reserved
Freeze gain
Reserved.
1
Set to 1
Rev. A | Page 86 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0x2D
Chroma Gain
Control 1
CMG[11:8]/CG[11:8]. In
manual mode, the
0
1
0
0
CAGC[1:0] settings decide
in which mode CMG[11:0]
operates
chroma gain control can
be used to program a
desired manual chroma
gain. In auto mode, it can
be used to read back the
current gain value.
Reserved.
1
0
1
0
Set to 1
CAGT[1:0]. Chroma
automatic gain timing
allows adjustment of
the chroma AGC
0
0
1
1
0
0
1
0
1
0
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
Has an effect only if
CAGC[1:0] is set to
autogain (10)
tracking speed.
0x2E
0x2F
Chroma Gain
Control 2
CMG[7:0]/CG[7:0].
Chroma manual gain
lower eight bits. See
CMG[11:8]/CG[11:8] for
description.
0
x
0
x
0
x
0
x
CMG[11:0] = 750d; gain is 1
in NTSC. CMG[11:0] = 741d;
gain is 1 in PAL
Min value is 0 dec
(G = 1/1000)
Max value is 3750 dec
(Gain = 5)
Luma Gain Control 1
LMG[11:8]/LG[11:8]. In
manual mode, luma gain
control can be used to
program a desired
LAGC[1:0] settings decide
in which mode LMG[11:0]
operates
manual chroma gain. In
auto mode, it can be
used to read back the
actual gain value used.
Reserved.
1
x
1
x
Set to 1
LAGT[1:0]. Luma
automatic gain timing
allows adjustment of
the luma AGC tracking
speed.
0
0
1
1
x
0
1
0
1
x
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
Only has an effect if
LAGC[1:0] is set to auto
gain (001, 010, 011,or 100)
0x30
0x31
Luma Gain Control 2
VS/FIELD Control 1
LMG[7:0]/LG[7:0]. Luma
manual gain lower eight
bits. See LMG[11:8]/
x
x
x
x
LMG[11:0] = 1600d;
gain is 1 in NTSC
LMG[11:0] = 1630d;
gain is 1 in PAL
Minimum value
NTSC 2048 (G = 0.5)
PAL 2048 (G = 0.5)
Maximum value
NTSC 4095 (G = 2)
PAL 4095 (G = 2)
LG[11:8] for description.
Reserved.
0
1
0
Set to default
HVSTIM. Selects where
within a line of video
the VS signal is asserted.
0
1
Start of line relative to HSE
Start of line relative to HSB
HSE = Hsync end
HSB = Hsync begin
NEWAVMODE. Sets the
EAV/SAV mode.
0
1
EAV/SAV codes generated
to suit Analog Devices
encoders
Manual VS/FIELD position
controlled by the 0x32, 0x33,
and 0xE5 to 0xEA registers
Reserved.
Reserved.
VSBHE.
0
0
0
0
Set to default
Set to default
0x32
VS/FIELD Control 2
0
0
0
0
1
NEWAVMODE bit must be
set high
0
1
VS goes high in the middle
of the line (even field)
VS changes state at the
start of the line (even field)
VSBHO.
0
1
VS goes high in the middle
of the line (odd field)
VS changes state at the
start of the line (odd field)
0x33
VS/FIELD Control 3
Reserved.
VSEHE.
0
0
0
1
0
0
Set to default
0
1
VS goes low in the middle
of the line (even field)
NEWAVMODE bit must be
set high
VS changes state at the
start of the line (even field)
VSEHO.
0
1
VS goes low in the middle
of the line (odd field)
VS changes state at the
start of the line odd field
Rev. A | Page 87 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0x34
HS Position Control 1
HSE[10:8]. HS end
allows positioning of
the HS output within
the video line.
0
0
0
HS output ends HSE[10:0]
pixels after the falling edge
of hsync
Using HSB and HSE the
user can program the
position and length of
the output hsync
Reserved.
0
Set to 0
HSB[10:8]. HS begin
allows positioning of
the HS output within
the video line.
0
0
0
0
0
0
HS output starts HSB[10:0]
pixels after the falling edge
of hsync
Reserved.
0
0
Set to 0
0x35
HS Position Control 2
HSB[7:0] See above,
using HSB[10:0] and
HSE[10:0], users can
program the position
and length of HS output
signal.
0
0
0
1
0
0x36
0x37
HS Position Control 3
Polarity
HSE[7:0] See above.
0
0
0
0
0
0
0
0
0
0
0
1
PCLK. Sets polarity of
LLC1.
Invert polarity
Normal polarity as per the
timing diagrams
Reserved.
Set to 0
PF. Sets the FIELD
polarity.
0
1
Active high
Active low
Reserved.
Set to 0
PVS. Sets the VS
polarity.
0
1
Active high
Active low
Reserved.
0
Set to 0
PHS. Sets HS polarity.
0
1
Active high
Active low
0x38
NTSC Comb Control
YCMN[2:0]. Luma
comb mode, NTSC.
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
Adaptive 3-line, 3-tap luma
Use low-pass notch
Fixed luma comb (2-line)
Fixed luma comb (3-line)
Fixed luma comb (2-line)
Top lines of memory
All lines of memory
Bottom lines of memory
CCMN[2:0]. Chroma
comb mode, NTSC.
0
0
0
3-line adaptive for
CTAPSN = 01
4-line adaptive for
CTAPSN = 10
5-line adaptive for
CTAPSN = 11
1
1
0
0
0
1
Disable chroma comb
Fixed 2-line for
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
Top lines of memory
All lines of memory
1
1
1
1
0
1
Fixed 3-line for
CTAPSN = 01
Fixed 4-line for
CTAPSN = 10
Fixed 5-line for
CTAPSN = 11
Fixed 2-line for
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
Bottom lines of memory
CTAPSN[1:0]. Chroma
comb taps, NTSC.
0
0
1
1
0
1
0
1
Adapts three to two lines
Not used
Adapts five to three lines
Adapts five to four lines
Rev. A | Page 88 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
0x39 PAL Comb Control
Bit Description
Notes
7
6
5
4
3
2
1
0
YCMP[2:0]. Luma
comb mode, PAL.
0
0
0
Adaptive 5-line, 3-tap luma
comb
1
1
1
1
0
1
1
1
0
0
0
1
Use low-pass notch
Fixed luma comb
Top lines of memory
All lines of memory
Fixed luma comb (5-line)
Fixed luma comb (3-line)
Bottom lines of memory
CCMP[2:0]. Chroma
comb mode, PAL.
0
0
0
3-line adaptive
for CTAPSN = 01
4-line adaptive
for CTAPSN = 10
5-line adaptive
for CTAPSN = 11
1
1
0
0
0
1
Disable chroma comb
Fixed 2-line for CTAPSN = 01 Top lines of memory
Fixed 3-line for CTAPSN = 10
Fixed 4-line for CTAPSN = 11
1
1
1
1
0
1
Fixed 3-line for CTAPSN = 01
Fixed 4-line for CTAPSN = 10
Fixed 5-line for CTAPSN = 11
Fixed 2-line for CTAPSN = 01
Fixed 3-line for CTAPSN = 10
Fixed 4-line for CTAPSN = 11
All lines of memory
Bottom lines of memory
CTAPSP[1:0]. Chroma
comb taps, PAL.
0
0
Adapts five to two lines
(two taps)
0
1
1
0
Not used
Adapts five to three lines
(three taps)
1
1
Adapts five to four lines
(four taps)
0x3A
ADC Control
MUX PDN override.
MUX power-down
override.
0
1
No control over power-
down for muxes and
associated channel circuit
When INSEL[3:0] is
used, unused channels
are automatically
powered down.
Allows power-down of
MUX_0/1/2 and associated
channel circuit
PWRDWN_MUX_2.
Enables power-down
of MUX_2 and
associated channel
clamp and buffer.
0
1
MUX_2 and associated
channel in normal operation
Power down MUX_2 and
associated channel operation
MUX PDN override =1
MUX PDN override =1
MUX PDN override =1
PWRDWN_MUX_1.
Enables power-down
of MUX_1 and
associated channel
clamp and buffer.
0
1
MUX_1 and associated
channel in normal operation
Power down MUX_1 and
associated channel operation
PWRDWN_MUX_0.
Enables power-down
of MUX_0 and
associated channel
clamp and buffer.
0
1
MUX_0 and associated
channel in normal operation
Power down MUX_0 and
associated channel operation
Reserved.
0
0
0
1
Set as default
Rev. A | Page 89 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Reserved.
Notes
7
6
5
4
3
2
1
0
0x3D
Manual Window
0
0
1
0
Set to default
Kill at 0.5%
Kill at 1.5%
Kill at 2.5%
Kill at 4%
Control
CKILLTHR[2:0].
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CKE = 1 enables the color
kill function and must be
enabled for CKILLTHR[2:0]
to take effect
Kill at 8.5%
Kill at 16%
Kill at 32%
Reserved
Reserved.
Reserved.
1
Set to default
Set to default
0x41
Resample Control
0
0
0
0
0
1
SFL_INV. Controls the
behavior of the PAL
switch bit.
0
1
SFL compatible with
ADV7190/ADV7191/
ADV7194 encoders
SFL compatible with
ADV717x/ADV7173x
encoders
Reserved.
0
0
Set to default
0x48
0x49
Gemstar Control 1
Gemstar Control 2
GDECEL[15:8]. See the
Comments column.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GDECEL[15:0]: sixteen
LSB = Line 10
MSB = Line 25
Default = Do not check for
Gemstar-compatible data
on any lines [10 to 25] in
even fields
individual enable bits that
select the lines of video
(even field Line 10 to Line 25)
that the decoder checks for
Gemstar-compatible data
GDECEL[7:0].
0
0x4A
0x4B
Gemstar Control 3
Gemstar Control 4
GDECOL[15:8]. See the
Comments column.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GDECOL[15:0]: sixteen
LSB = Line 10
MSB = Line 25
Default = Do not check for
Gemstar-compatible data
on any lines [10 to 25] in
odd fields
individual enable bits that
select the lines of video
(odd field Line 10 to Line 25)
that the decoder checks for
Gemstar-compatible data
GDECOL[7:0].
0x4C
Gemstar Control 5
GDECAD. Controls the
manner in which
decoded Gemstar data
is inserted into the
horizontal blanking
period.
0
1
Split data into half-byte
To avoid 00/FF code
Output in straight 8-bit
format
Reserved.
x
x
x
x
x
x
x
Undefined
0x4D
CTI DNR Control 1
CTI_EN. CTI enable.
0
1
Disable CTI
Enable CTI
CTI_AB_EN. Enables
the mixing of the
transient improved
chroma with the
original signal.
0
1
Disable CTI alpha blender
Enable CTI alpha blender
CTI_AB[1:0]. Controls
the behavior of the
alpha-blend circuitry.
0
0
1
1
0
1
0
1
Sharpest mixing
Sharp mixing
Smooth
Smoothest
Reserved.
0
0
0
Set to default
DNR_EN. Enable or
bypass the DNR block.
0
1
Bypass the DNR block
Enable the DNR block
Set to default
Reserved.
1
0
1
0
0x4E
0x50
CTI DNR Control 2
CTI DNR Control 4
CTI_C_TH[7:0].
0
1
1
0
0
0
0
0
0
Set to 0x04 for AV input;
set to 0x0A for tuner input
Specifies how big the
amplitude step must
be to be steepened by
the CTI block.
DNR_TH[7:0]. Specifies
the maximum edge
that is interpreted as
noise and is therefore
blanked.
0
0
0
Rev. A | Page 90 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0x51
Lock Count
CIL[2:0]. Count into
lock determines the
number of lines the
system must remain in
lock before showing a
locked status.
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
1 line of video
COL[2:0]. Count out of
lock determines the
number of lines the
system must remain
out-of-lock before
showing a lost-locked
status.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
Over field with vertical info
Line-to-line evaluation
SRLS. Select raw lock
signal. Selects the
determination of the
lock status.
0
1
FSCLE. FSC lock enable.
0
1
Lock status set only by
horizontal lock
Lock status set by
horizontal lock and
subcarrier lock
0x58
VSYNC/FIELD Pin
Control
VS/FIELD.
Vsync or field output.
ADV7180 LFCSP-40 only.
0
1
FIELD
Pin 37 on LFCSP-40
Mandatory write
VSYNC
Reserved.
0
Set to default
ADC Sampling Control.
0
1
CVBS/YPrPb modes only
Y/C mode only
Reserved.
0
0
0
0
0
Set to default
0x59
General-Purpose
Outputs
GPO[3:0].
ADV7180 LQFP-64 only.
0
1
Outputs 0 to GPO0, Pin 13
Outputs 1 to GPO0, Pin 13
Outputs 0 to GPO1, Pin 12
Outputs 1 to GPO1, Pin 12
Outputs 0 to GPO2, Pin 56
Outputs 1 to GPO2, Pin 56
Outputs 0 to GPO3, Pin 55
Outputs 1 to GPO3, Pin 55
GPO[3:0] three-stated
GPO[3:0] enabled
GPO_Enable must be set to
1 for these bits to take
effect
0
1
0
1
0
1
GPO_Enable.
0
1
Reserved.
Reserved.
0
0
0
0x8F
Free-Run Line
Length 1
0
0
0
0
Set to default
LLC_PAD_SEL[2:0].
Enables manual
selection of clock
for LLC1 pin.
0
1
0
0
0
1
LLC1 (nominal 27 MHz)
selected out on LLC1 pin
LLC2 (nominal 13.5 MHz)
selected out on LLC1 pin
For 16-bit 4:2:2 out,
OF_SEL[3:0] = 0010
Reserved.
0
x
Set to default
0x99
0x9A
CCAP1
(Read Only)
CCAP1[7:0] Closed
caption data register.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CCAP1[7] contains parity
bit for Byte 0
CCAP2
CCAP2[7:0] Closed
caption data register.
x
CCAP2[7] contains parity
bit for Byte 0
(Read Only)
Rev. A | Page 91 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0x9B
Letterbox 1
(Read Only)
LB_LCT[7:0]. Letterbox
data register.
x
x
x
x
x
x
x
x
Reports the number of
black lines detected at the
top of active video
This feature examines the
active video at the start
and end of each field; it
enables format detection
even if the video is not
accompanied by a CGMS
or WSS sequence
0x9C
Letterbox 2
(Read Only)
LB_LCM[7:0]. Letterbox
data register.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Reports the number of
black lines detected in the
bottom half of active video
if subtitles are detected
0x9D
0xB2
Letterbox 3
(Read Only)
LB_LCB[7:0]. Letterbox
data register.
x
x
Reports the number of
black lines detected at the
bottom of active video
CRC Enable
(Write Only)
Reserved.
0
0
Set as default
CRC_ENABLE. Enable
CRC checksum
decoded from CGMS
packet to validate
CGMSD.
0
1
Turn off CRC check
CGMSD goes high with
valid checksum
Reserved.
0
0
0
1
1
Set as default
0xC3
ADC SWITCH 1
MUX_0[3:0]. Manual
muxing control for
MUX0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No connect
AIN1
No connect
AIN1
MAN_MUX_EN = 1
MAN_MUX_EN = 1
MAN_MUX_EN = 1
AIN2
No connect
No connect
AIN2
AIN3
This setting controls
which input is routed
to the ADC for
AIN4
AIN5
AIN3
processing.
AIN6
No connect
No connect
No connect
Reserved.
0
MUX_1[3:0]. Manual
muxing control for
MUX1.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No connect
No connect
No connect
AIN3
No connect
No connect
No connect
No connect
AIN2
This setting controls
which input is routed
to the ADC for
AIN4
AIN5
AIN3
processing.
AIN6
No connect
No connect
No connect
Reserved.
0
0xC4
ADC Switch 2
MUX_2[3:0]. Manual
muxing control for
MUX2.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
AIN3
No connect
No connect
AIN5
This setting controls
which input is routed
to the ADC for
processing.
AIN6
No connect
No connect
No connect
Reserved.
0
0
0
0
0
1
MAN_MUX_EN. Enable
manual setting of the
input signal muxing.
0
1
Disable
Enable
This bit must be set to 1 for
manual muxing
0xDC
0xDD
Letterbox Control 1
Letterbox Control 2
LB_TH [4:0]. Sets the
threshold value that
determines if a line is
black.
1
1
0
0
0
0
Default threshold for the
detection of black lines
Reserved.
1
0
0
1
1
0
Set as default
LB_EL[3:0]. Programs
the end line of the
activity window for LB
detection (end of field).
1
LB detection ends with the
last line of active video on a
field, 1100b: 262/525
LB_SL[3:0]. Program
the start line of the
activity window for LB
detection (start of
field).
0
Letterbox detection aligned
with the start of active video,
0100b: 23/286 NTSC
Rev. A | Page 92 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
x
x
1
x
x
0
x
x
0xDE
ST_Noise Readback 1
(Read Only)
ST NOISE[10:0]. Noise
measurement.
ST_NOISE[10:8].
ST_Noise_Valid.
x
x
When = 1, ST_Noise[10:0] is
valid
0xDF
ST_Noise Readback 2
(Read Only)
ST_NOISE[7:0].
x
x
x
x
0xE0
0xE1
Reserved.
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
SD Offset Cb
SD_OFF_CB [7:0].
Adjusts the hue by
selecting the offset for
the Cb channel.
0xE2
0xE3
0xE4
0xE5
SD Offset Cr
SD_OFF_CR [7:0].
Adjusts the hue by
selecting the offset for
the Cr channel.
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
SD Saturation Cb
SD Saturation Cr
NTSC V Bit Begin
SD_SAT_CB [7:0].
Adjusts the saturation
by affecting gain on
the Cb channel.
Chroma gain = 0 dB
SD_SAT_CR [7:0].
Adjusts the saturation
by affecting gain on
the Cr channel.
Chroma gain = 0 dB
NVBEG[4:0]. Number of
lines after lCOUNT rollover
to set V high.
NTSC default (ITU-R BT.656)
NVBEGSIGN.
0
1
Set to low when manual
programming
Not suitable for user
programming
NVBEGDELE. Delay
V bit going high by one
line relative to NVBEG
(even field).
0
1
No delay
Additional delay by one line
NVBEGDELO. Delay
V bit going high by one
line relative to NVBEG
(odd field).
0
1
No delay
Additional delay by one line
0xE6
NTSC V Bit End
NVEND[4:0]. Number of
lines after lCOUNT rollover
to set V low.
0
0
1
0
0
NTSC default (ITU-R BT.656)
NVENDSIGN.
0
1
Set to low when manual
programming
Not suitable for user
programming
NVENDDELE. Delay
V bit going low by one
line relative to NVEND
(even field).
0
1
No delay
Additional delay by one line
NVENDDELO. Delay
V bit going low by one
line relative to NVEND
(odd field).
0
1
No delay
Additional delay by one line
Rev. A | Page 93 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
NTSC default
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0xE7
0xE8
0xE9
0xEA
NTSC F Bit Toggle
NFTOG[4:0]. Number of
lines after lCOUNT rollover
to toggle F signal.
0
0
0
1
1
NFTOGSIGN.
0
1
Set to low when manual
programming
Not suitable for user
programming
NFTOGDELE. Delay
F transition by one line
relative to NFTOG
(even field).
0
1
No delay
Additional delay by one line
NFTOGDELO. Delay
F transition by one line
relative to NFTOG
(odd field).
0
1
No delay
Additional delay by one line
PAL V Bit Begin
PVBEG[4:0]. Number of
lines after lCOUNT rollover
to set V high.
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
PAL default (ITU-R BT.656)
PVBEGSIGN.
0
1
Set to low when manual
programming
Not suitable for user
programming
PVBEGDELE. Delay V bit
going high by one line
relative to PVBEG (even
field).
0
1
No delay
Additional delay by one line
PVBEGDELO. Delay V bit
going high by one line
relative to PVBEG (odd
field).
0
1
No delay
Additional delay by one line
PAL V Bit End
PVEND[4:0]. Number of
lines after lCOUNT rollover
to set V low.
PAL default (ITU-R BT.656)
PVENDSIGN.
0
1
Set to low when manual
programming
Not suitable for user
programming
PVENDDELE. Delay V bit
going low by one line
relative to PVEND (even
field).
0
1
No delay
Additional delay by one line
PVENDDELO. Delay V bit
going low by one line
relative to PVEND (odd
field).
0
1
No delay
Additional delay by one line
PAL F Bit Toggle
PFTOG[4:0]. Number of
lines after lCOUNT rollover
to toggle F signal.
PAL default (ITU-R BT.656)
PFTOGSIGN.
0
1
Set to low when manual
programming
Not suitable for user
programming
PFTOGDELE. Delay
F transition by one line
relative to PFTOG
(even field).
0
1
No delay
Additional delay by one line
PFTOGDELO. Delay
F transition by one line
relative to PFTOG
(odd field).
0
1
No delay
Additional delay by one line
Rev. A | Page 94 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
0xEB V Blank Control 1
Bit Description
Notes
7
6
5
4
3
2
1
0
PVBIELCM[1:0]. PAL VBI
even field line control.
0
0
VBI ends one line earlier
(Line 335)
Controls position of first
active (comb filtered) line
after VBI on even field in PAL
0
1
1
1
0
1
ITU-R BT.470 compliant
(Line 336)
VBI ends one line later
(Line 337)
VBI ends two lines later
(Line 338)
PVBIOLCM[1:0]. PAL VBI
odd field line control.
0
0
VBI ends one line earlier
(Line 22)
Controls position of first
active (comb filtered) line
after VBI on odd field in PAL
0
1
1
1
0
1
ITU-R BT.470 compliant
(Line 23)
VBI ends one line later
(Line 24)
VBI ends two lines later
(Line 25)
NVBIELCM[1:0]. NTSC VBI
even field line control.
0
0
VBI ends one line earlier
(Line 282)
Controls position of first
active (comb filtered) line
after VBI on even field in NTSC
0
1
1
1
0
1
ITU-R BT.470-compliant
(Line 283)
VBI ends one line later
(Line 284)
VBI ends two lines later
(Line 285)
PVBIOLCM[1:0]. NTSC VBI
odd field line control.
0
0
VBI ends one line earlier
(Line 20)
Controls position of first
active (comb filtered) line
after VBI on odd field in NTSC
0
1
ITU-R BT.470-compliant
(Line 21)
1
1
0
1
VBI ends one line later (Line 22)
VBI ends two lines later
(Line 23)
0xEC
V Blank Control 2
PVBIECCM[1:0]. PAL VBI
even field color control.
0
0
1
1
0
1
0
1
Color output beginning
Line 335
Controls the position of first
line that outputs color after
VBI on even field in PAL
ITU-R BT.470-compliant color
output beginning Line 336
Color output beginning
Line 337
Color output beginning
Line 338
PVBIOCCM[1:0]. PAL VBI
odd field color control.
0
0
1
1
0
1
0
1
Color output beginning
Line 22
Controls the position of first
line that outputs color after
VBI on odd field in PAL
ITU-R BT.470-compliant color
output beginning Line 23
Color output beginning
Line 24
Color output beginning
Line 25
NVBIECCM[1:0]. NTSC VBI
even field color control.
0
0
1
1
0
1
0
1
Color output beginning
Line 282
Controls the position of first
line that outputs color after
VBI on even field in NTSC
ITU-R BT.470-compliant color
output beginning Line 283
VBI ends one line later
(Line 284)
Color output beginning
Line 285
NVBIOCCM[1:0]. NTSC VBI
odd field color control.
0
0
0
1
Color output beginning
Line 20
Controls the position of first
line which outputs color after
VBI on odd field in NTSC
ITU-R BT.470 compliant color
output beginning
Line 21
1
1
0
1
Color output beginning
Line 22
Color output beginning
Line 23
Rev. A | Page 95 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0xF3
AFE Control 1
AA_FILT_EN[2:0].
Antialiasing filter enable.
0
Antialiasing Filter 1 disabled
AA_FILT_MAN_OVR must
be enabled to change
settings defined by
INSEL[3:0]
1
Antialiasing Filter 1 enabled
Antialiasing Filter 2 disabled
Antialiasing Filter 2 enabled
Antialiasing Filter 3 disabled
0
1
0
1
Antialiasing Filter 3
enabled
AA_FILT_MAN_OVR.
Antialiasing filter
override.
0
1
Override disabled
Override enabled
Reserved.
0
0
0
0
0xF4
Drive Strength
DR_STR_S[1:0]. Selects
the drive strength for
the sync output signals.
0
0
0
1
Low drive strength (1×)
Medium-low drive
strength (2×)
1
1
0
1
Medium-high drive
strength (3×)
High drive strength (4×)
Low drive strength (1×)
DR_STR_C[1:0]. Selects
the drive strength for
the clock output signal.
0
0
0
1
Medium-low drive
strength (2×)
1
1
0
1
Medium-high drive
strength (3×)
High drive strength (4×)
Low drive strength (1×)
DR_STR[1:0]. Selects the
drive strength for the
data output signals.
Can be increased or
decreased for EMC or
crosstalk reasons.
0
0
0
1
Medium-low drive
strength (2×)
1
1
0
1
Medium-high drive
strength (3×)
High drive strength (4×)
Reserved.
x
x
0xF8
IF Comp Control
IFFILTSEL[2:0]. IF filter
selection for PAL and
NTSC.
0
0
0
Bypass mode
0 dB
2 MHz
−3 dB
5 MHz
−2 dB
NTSC filters
0
0
0
1
0
1
1
0
1
0
1
0
−6 dB
+3.5 dB
+5 dB
−10 dB
Reserved
3 MHz
−2 dB
6 MHz
+2 dB
+3 dB
+5 dB
PAL filters
1
1
1
0
1
1
1
0
1
−5 dB
−7 dB
Reserved.
0
0
0
0
0
Rev. A | Page 96 of 112
ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0xF9
VS Mode Control
EXTEND_VS_MAX_FREQ.
0
Limits maximum vsync
frequency to 66.25 Hz
(475 lines/frame)
1
Limits maximum vsync
frequency to 70.09 Hz
(449 lines/frame)
EXTEND_VS_MIN_FREQ.
VS_COAST_MODE[1:0].
0
1
Limits minimum vsync
frequency to 42.75 Hz
(731 lines/frame)
Limits minimum vsync
frequency to 39.51 Hz
(791 lines/frame)
0
0
1
1
0
1
0
1
Autocoast mode
50 Hz coast mode
60 Hz coast mode
Reserved
This value sets up the
output coast frequency
Reserved.
0
0
0
1
0
0
0
0
0xFB
0xFC
Peaking Control
PEAKING_GAIN[7:0].
0
0
0
1
0
0
0
0
Increases/decreases the
gain for high frequency
portions of the video signal.
Coring Threshold 2
DNR_TH2[7:0].
0
0
0
0
Specifies the maximum
edge that is interpreted as
noise and therefore blanked.
Rev. A | Page 97 of 112
ADV7180
Table 104. Register Map Descriptions (Interrupt Operation)
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
0x40 Interrupt Configuration 1
Bit Description
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Comments
Notes
INTRQ_OP_SEL[1:0]. Interrupt drive
level select.
Open drain
Drive low when active
Drive high when active
Reserved
MPU_STIM_INTRQ. Manual interrupt
set mode.
0
1
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
x
MV_INTRQ_SEL[1:0]. Macrovision
interrupt select.
0
0
1
1
0
1
0
1
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
3 XTAL periods
INTRQ_DUR_SEL[1:0]. Interrupt
duration select.
0
0
1
1
0
1
0
1
15 XTAL periods
63 XTAL periods
Active until cleared
No change
0x42
Interrupt Status 1
(Read Only)
SD_LOCK_Q.
0
1
These bits can be cleared
or masked in Registers
0x43 and 0x44,
SD input has caused the decoder to go
from an unlocked state to a locked state
respectively
SD_UNLOCK_Q.
0
1
No change
SD input has caused the decoder to go
from a locked state to an unlocked state
Reserved.
x
Reserved.
x
Reserved.
x
SD_FR_CHNG_Q.
0
1
No Change
Denotes a change in the free-run status
No Change
MV_PS_CS_Q.
0
1
Pseudo sync/color striping detected. See
Reg. 0x40 MV_INTRQ_SEL[1:0] for
selection
Reserved.
x
x
x
0x43
Interrupt Clear 1
(Write Only)
SD_LOCK_CLR.
0
1
Do not clear
Clears SD_LOCK_Q bit
Do not clear
SD_UNLOCK_CLR.
0
1
Clears SD_UNLOCK_Q bit
Not used
Reserved.
0
Reserved.
0
Not used
Reserved.
0
Not used
SD_FR_CHNG_CLR.
0
1
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
MV_PS_CS_CLR.
Reserved.
0
1
Clears MV_PS_CS_Q bit
Not used
0x44
Interrupt Mask 1
(Read/Write)
SD_LOCK_MSK
0
1
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
.
SD_UNLOCK_MSK
0
1
.
Reserved.
Reserved.
Reserved.
0
0
Not used
0
Not used
SD_FR_CHNG_MSK
0
1
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
.
MV_PS_CS_MSK
0
1
.
Reserved.
Rev. A | Page 98 of 112
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x45
Raw Status 2
(Read Only)
CCAPD.
0
No CCAPD data detected—
VBI System 2
These bits are status bits
only; they cannot be
cleared or masked;
Register 0x46 is used for
this purpose
1
CCAPD data detected—VBI System 2
Reserved.
x
x
x
EVEN_FIELD.
0
1
Current SD field is odd numbered
Current SD field is even numbered
Reserved.
x
x
MPU_STIM_INTRQ.
0
1
MPU_STIM_INT = 0
MPU_STIM_INT = 1
0x46
Interrupt Status 2
(Read Only)
CCAPD_Q.
GEMD_Q.
0
1
Closed captioning not detected in the
input video signal—VBI System 2
These bits can be cleared
or masked by Registers
0x47 and 0x48,
Closed captioning data detected in the
video input signal—VBI System 2
respectively
0
1
Gemstar data not detected in the input
video signal—VBI System 2
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer
Gemstar data detected in the input
video signal—VBI System 2
Reserved.
x
x
SD_FIELD_CHNGD_Q.
0
1
SD signal has not changed field from
odd to even or vice versa
SD signal has changed Field from odd to
even or vice versa
Reserved.
x
Not used
Reserved.
x
Not used
MPU_STIM_INTRQ_Q.
0
1
Manual interrupt not set
Manual interrupt set
Do not clear—VBI System 2
Clears CCAPD_Q bit – VBI System 2
Do not clear
0x47
Interrupt Clear 2
(Write Only)
CCAPD_CLR.
GEMD_CLR.
0
1
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer
0
1
Clears GEMD_Q bit
Reserved.
0 0
SD_FIELD_CHNGD_CLR.
0
1
Do not clear
Clears SD_FIELD_CHNGD_Q bit
Not used
Reserved.
x
Reserved.
x
Not used
MPU_STIM_INTRQ_CLR.
0
1
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Masks CCAPD_Q bit—VBI System 2
0x48
Interrupt Mask 2
(Read/Write)
CCAPD_MSK
0
1
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer.
.
Unmasks CCAPD_Q bit—
VBI System 2
GEMD_MSK
0
1
Masks GEMD_Q bit—VBI System 2
Unmasks GEMD_Q bit—VBI System 2
Not used
.
Reserved.
SD_FIELD_CHNGD_MSK
0 0
0
1
Masks SD_FIELD_CHNGD_Q bit
Unmasks SD_FIELD_CHNGD_Q bit
Not used
.
Reserved.
0
0
MPU_STIM_INTRQ_MSK
0
1
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not established
SD vertical sync lock established
SD horizontal sync lock not established
SD horizontal sync lock established
Not used
.
0x49
Raw Status 3
(Read Only)
SD_OP_50Hz. SD 60 Hz/50 Hz
frame rate at output.
0
1
These bits are status bits
only; they cannot be
cleared or masked;
Register 0x4A is used for
this purpose
SD_V_LOCK.
0
1
SD_H_LOCK.
0
1
Reserved.
x
SCM_LOCK.
0
1
SECAM lock not established
SECAM lock established
Not used
Reserved.
Reserved.
Reserved.
x
x
Not used
x
Not used
Rev. A | Page 99 of 112
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x4A
Interrupt Status 3
(Read Only)
SD_OP_CHNG_Q. SD 60 Hz/50 Hz
frame rate at output.
0
No change in SD signal standard
detected at the output
These bits can be cleared
and masked by Registers
0x4B and 0x4C,
1
A change in SD signal standard is
detected at the output
respectively
SD_V_LOCK_CHNG_Q.
SD_H_LOCK_CHNG_Q.
0
1
No change in SD vsync lock status
SD vsync lock status has changed
No change in SD hsync lock status
SD hsync lock status has changed
0
1
SD_AD_CHNG_Q. SD autodetect
changed.
0
1
No change in AD_RESULT[2:0] bits in
Status Register 1
AD_RESULT[2:0] bits in Status Register 1
have changed
SCM_LOCK_CHNG_Q. SECAM lock.
PAL_SW_LK_CHNG_Q.
0
1
No change in SECAM lock status
SECAM lock status has changed
0
1
No change in PAL swinging burst
lock status
PAL swinging burst lock status has
changed
Reserved.
x
x
x
Not used
Reserved.
x
x
x
Not used
0x4B
Interrupt Clear 3
(Write only)
SD_OP_CHNG_CLR.
0
1
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
SD_V_LOCK_CHNG_CLR.
SD_H_LOCK_CHNG_CLR.
SD_AD_CHNG_CLR.
0
1
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
0
1
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
0
1
Clears SD_AD_CHNG_Q bit
Do not clear
SCM_LOCK_CHNG_CLR.
PAL_SW_LK_CHNG_CLR.
0
1
Clears SCM_LOCK_CHNG_Q bit
Do not clear
0
1
Clears PAL_SW_LK_CHNG_Q bit
Not used
Reserved.
Reserved.
Not used
0x4C
Interrupt Mask 3
(Read/Write)
SD_OP_CHNG_MSK
0
1
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q bit
Not used
.
SD_V_LOCK_CHNG_ MSK
0
1
.
SD_H_LOCK_CHNG_ MSK
0
1
.
SD_AD_CHNG_ MSK
0
1
.
SCM_LOCK_CHNG_ MSK
0
1
.
PAL_SW_LK_CHNG_ MSK
0
1
.
Reserved.
Reserved.
Not used
Rev. A | Page 100 of 112
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Comments
Notes
0x4E
Interrupt Status 4
VDP_CCAPD_Q.
Closed captioning not detected
Closed captioning detected
These bits can be cleared
and masked by Register
0x4F and Register 0x50,
respectively
Reserved.
x
VDP_CGMS_WSS_CHNGD_Q. See 0x9C
Bit 4 of user sub map to determine
whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content.
0
1
CGMS/WSS data is not changed/not
available
Note that an interrupt in
Register 0x4E for the
CCAP, Gemstar, CGMS,
WSS, VPS, PDC, UTC, and
VITC data is using the VDP
data slicer
CGMS/WSS data is changed/available
Reserved.
x
VDP_GS_VPS_PDC_UTC_CHNG_Q.
See 0x9C Bit 5 of User Sub Map to
determine whether interrupt is issued
for a change in detected data or for
when data is detected regardless of
content.
0
1
Gemstar/PDC/VPS/UTC data is not
changed/available
Gemstar/PDC/VPS/UTC data is
changed/available
Reserved.
x
VDP_VITC_Q.
0
1
VITC data is not available in the VDP
VITC data is available in the VDP
Reserved.
x
0x4F
Interrupt Clear 4
(Write Only)
VDP_CCAPD_CLR.
0
1
Do not clear
Note that an interrupt in
Register 0x4E for the
CCAP, Gemstar, CGMS,
WSS, VPS, PDC, UTC, and
VITC data is using the VDP
data slicer
Clears VDP_CCAPD_Q
Reserved.
0
VDP_CGMS_WSS_CHNGD_CLR.
0
1
Do not clear
Clears VDP_CGMS_WSS_CHNGD_Q
Reserved.
0
VDP_GS_VPS_PDC_UTC_CHNG_CLR.
0
1
Do not clear
Clears VDP_GS_VPS_PDC_UTC_
CHNG_Q
Reserved.
0
VDP_VITC_CLR.
0
1
Do not clear
Clears VDP_VITC_Q
Reserved.
0
0x50
Interrupt Mask 4
VDP_CCAPD_MSKB.
0
1
Masks VDP_CCAPD_Q
Note that an interrupt in
Register 0x4E for the
CCAP, Gemstar, CGMS,
WSS, VPS, PDC, UTC, and
VITC data is using the VDP
data slicer
Unmasks VDP_CCAPD_Q
Reserved.
0
VDP_CGMS_WSS_CHNGD_MSKB.
0
1
Masks VDP_CGMS_WSS_CHNGD_Q
Unmasks VDP_CGMS_WSS_
CHNGD_Q
Reserved.
0
VDP_GS_VPS_PDC_UTC_CHNG_MSKB.
0
1
Masks VDP_GS_VPS_PDC_UTC_
CHNG_Q
Unmasks VDP_GS_VPS_PDC_UTC_
CHNG_Q
Reserved.
0
VDP_VITC_MSKB.
0
1
Masks VDP_VITC_Q
Unmasks VDP_VITC_Q
Reserved.
0
0x60
VDP_Config_1
VDP_TTXT_TYPE_MAN[1:0].
0
0
1
0
1
0
PAL: Teletext-ITU-BT.653-625/50-A
NTSC: Reserved
PAL: Teletext-ITU-BT.653-625/50-B (WST)
NTSC: Teletext-ITU-BT.653-525/60-B
PAL: Teletext-ITU-BT.653-625/50-C
NTSC: Teletext-ITU-BT.653-525/60-C OR
EIA516 (NABTS)
1
1
PAL: Teletext-ITU-BT.653-625/50-D
NTSC: Teletext-ITU-BT.653-525/60-D
VDP_TTXT_TYPE_MAN_ENABLE.
WST_PKT_DECODE_DISABLE.
Reserved.
0
1
User programming of teletext type
disabled
User programming of teletext type
enabled
0
1
Enable hamming decoding of WST
packets
Disable hamming decoding of WST
packets
1
0
0
0
Rev. A | Page 101 of 112
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
Reserved.
7
6
5
4
3
2
1
0
Comments
Notes
0x61
VDP_Config_2
x
x
0
0
AUTO_DETECT_GS_TYPE.
0
1
Disable autodetection of Gemstar type
Enable autodetection of Gemstar type
Reserved.
0
0
0
0x62
VDP_ADF_Config_1
ADF_DID[4:0].
1
0
1
0
1
User-specified DID sent in the ancillary
data stream with VDP decoded data
ADF_MODE[1:0].
0
0
1
0
1
0
Nibble mode
Byte mode, no code restrictions
Byte mode with 0x00 and 0xFF
prevented
1
x
0
1
Reserved
ADF_ENABLE.
0
1
Disable insertion of VBI decoded data
into ancillary 656 stream
Enable insertion of VBI decoded data
into ancillary 656 stream
0x63
0x64
VDP_ADF_Config_2
ADF_SDID[5:0].
1
0
1
0
0
0
1
0
0
0
User-specified SDID sent in the ancillary
data stream with VDP decoded data
Reserved.
DUPLICATE_ADF.
0
1
Ancillary data packet is spread across the
Y and C data streams
Ancillary data packet is duplicated on
the Y and C data streams
VDP_LINE_00E
VBI_DATA_P318[3:0].
Sets VBI standard to be decoded from
Line 318 (PAL); NTSC—N/A
Reserved.
0
0
MAN_LINE_PGM.
0
1
Decode default standards on the lines
indicated in Table 65
Manually program the VBI standard
to be decoded on each line; see
Table 66
If set to 1, all VBI_DATA_
Px_Ny bits can be set as
desired
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
VDP_LINE_00F
VDP_LINE_010
VDP_LINE_011
VDP_LINE_012
VDP_LINE_013
VDP_LINE_014
VDP_LINE_015
VDP_LINE_016
VDP_LINE_017
VBI_DATA_P319_N286[3:0].
VBI_DATA_P6_N23[3:0].
VBI_DATA_P320_N287[3:0].
VBI_DATA_P7_N24[3:0].
VBI_DATA_P321_N288[3:0].
VBI_DATA_P8_N25[3:0].
VBI_DATA_P322[3:0].
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be decoded from
Line 319 (PAL), Line 286 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be decoded from
Line 6 (PAL), Line 23 (NTSC)
Sets VBI standard to be decoded from
Line 320 (PAL), Line 287 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 7 (PAL), Line 24 (NTSC)
Sets VBI standard to be decoded from
Line 321 (PAL), Line 288 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 8 (PAL), Line 25 (NTSC)
Sets VBI standard to be decoded from
Line 322 (PAL); NTSC—N/A
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
VBI_DATA_P9[3:0].
Sets VBI standard to be decoded from
Line 9 (PAL); NTSC—N/A
VBI_DATA_P323[3:0].
Sets VBI standard to be decoded from
Line 323 (PAL); NTSC—N/A
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
VBI_DATA_P10[3:0].
Sets VBI standard to be decoded from
Line 10 (PAL); NTSC—N/A
VBI_DATA_P324_N272[3:0].
VBI_DATA_P11[3:0].
Sets VBI standard to be decoded from
Line 324 (PAL), Line272 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 11 (PAL); NTSC—N/A
VBI_DATA_P325_N273[3:0].
VBI_DATA_P12_N10[3:0].
VBI_DATA_P326_N274[3:0].
VBI_DATA_P13_N11[3:0].
VBI_DATA_P327_N275[3:0].
VBI_DATA_P14_N12[3:0].
Sets VBI standard to be decoded from
Line 325 (PAL), Line 273(NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 12 (PAL), Line 10 (NTSC)
Sets VBI standard to be decoded from
Line 326 (PAL), Line 274 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 13 (PAL), Line 11 (NTSC)
Sets VBI standard to be decoded from
Line 327 (PAL), Line 275 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 14 (PAL), Line 12 (NTSC)
Rev. A | Page 102 of 112
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
VDP_LINE_018
VBI_DATA_P328_N276[3:0].
0
0
0
0
Sets VBI standard to be decoded from
Line 328 (PAL), Line 276 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
VBI_DATA_P15_N13[3:0].
VBI_DATA_P329_N277[3:0].
VBI_DATA_P16_N14[3:0].
VBI_DATA_P330_N278[3:0].
VBI_DATA_P17_N15[3:0].
VBI_DATA_P331_N279[3:0].
VBI_DATA_P18_N16[3:0].
VBI_DATA_P332_N280[3:0].
VBI_DATA_P19_N17[3:0].
VBI_DATA_P333_N281[3:0].
VBI_DATA_P20_N18[3:0].
VBI_DATA_P334_N282[3:0].
VBI_DATA_P21_N19[3:0].
VBI_DATA_P335_N283[3:0].
VBI_DATA_P22_N20[3:0].
VBI_DATA_P336_N284[3:0].
VBI_DATA_P23_N21[3:0].
VBI_DATA_P337_N285[3:0].
VBI_DATA_P24_N22[3:0].
0
0
0
0
Sets VBI standard to be decoded from
Line 15 (PAL), Line 13 (NTSC)
VDP_LINE_019
VDP_LINE_01A
VDP_LINE_01B
VDP_LINE_01C
VDP_LINE_01D
VDP_LINE_01E
VDP_LINE_01F
VDP_LINE_020
VDP_LINE_021
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be decoded from
Line 329 (PAL), Line 277 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be decoded from
Line 16 (PAL), Line14 (NTSC)
Sets VBI standard to be decoded from
Line 330 (PAL), Line 278 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 17 (PAL), Line 15 (NTSC)
Sets VBI standard to be decoded from
Line 331 (PAL), Line 279 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 18 (PAL), Line 16 (NTSC)
Sets VBI standard to be decoded from
Line 332 (PAL), Line 280 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 19 (PAL), Line 17 (NTSC)
Sets VBI standard to be decoded from
Line 333 (PAL), Line 281 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 20 (PAL), Line 18 (NTSC)
Sets VBI standard to be decoded from
Line 334 (PAL), Line 282 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 21 (PAL), Line 19 (NTSC)
Sets VBI standard to be decoded from
Line 335 (PAL), Line 283 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 22 (PAL), Line 20 (NTSC)
Sets VBI standard to be decoded from
Line 336 (PAL), Line 284 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 23 (PAL), Line 21 (NTSC)
Sets VBI standard to be decoded from
Line 337 (PAL), Line 285 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to be
effective
Sets VBI standard to be decoded from
Line 24 (PAL), Line 22 (NTSC)
Rev. A | Page 103 of 112
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Comments
Notes
0x78
VDP_STATUS
(Read Only)
CC_AVL.
Closed captioning not detected
Closed captioning detected
CC_CLEAR resets the
CC_AVL bit
CC_EVEN_FIELD.
CGMS_WSS_AVL.
0
1
Closed captioning decoded from
odd field
Closed captioning decoded from
even field
0
1
CGMS/WSS not detected
CGMS/WSS detected
CGMS_WSS_CLEAR resets
the CGMS_WSS_AVL bit
Reserved.
0
GS_PDC_VPS_UTC_AVL.
0
1
VPS not detected
VPS detected
GS_PDC_VPS_UTC_CLEAR
resets the
GS_PDC_VPS_UTC_AVL
bit
GS_DATA_TYPE.
VITC_AVL.
0
1
Gemstar_1× detected
Gemstar_2× detected
VITC not detected
0
1
VITC_CLEAR resets the
VITC_AVL bit
VITC detected
TTXT_AVL.
0
1
Teletext not detected
Teletext detected
VDP_STATUS_CLEAR
(Write Only)
CC_CLEAR.
0
1
Does not reinitialize the CCAP registers
Reinitializes the CCAP readback registers
This is a self-clearing bit
This is a self-clearing bit
Reserved.
0
CGMS_WSS_CLEAR.
0
1
Does not reinitialize the CGMS/WSS
registers
Reinitializes the CGMS/WSS readback
registers
Reserved.
0
GS_PDC_VPS_UTC_CLEAR.
0
1
Does not reinitialize the GS/PDC/VPS/
UTC registers
This is a self-clearing bit
This is a self-clearing bit
Refreshes the GS/PDC/VPS/UTC
readback registers
Reserved.
0
VITC_CLEAR.
0
1
Does not reinitialize the VITC registers
Reinitializes the VITC readback registers
Reserved.
0
x
0x79
0x7A
0x7D
VDP_CCAP_DATA_0
(Read Only)
VDP_CCAP_DATA_1
(Read Only)
VDP_CGMS_WSS_DATA_0
(Read Only)
CCAP_BYTE_1[7:0].
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Decoded Byte 1 of CCAP
CCAP_BYTE_2[7:0].
x
Decoded Byte 2 of CCAP
CGMS_CRC[5:2].
Reserved.
CGMS_WSS[13:8].
CGMS_CRC[1:0].
CGMS_WSS[7:0].
Decoded CRC sequence for CGMS
0
0
0
x
0
x
0x7E
VDP_CGMS_WSS_DATA_1
(Read Only)
x
x
x
x
Decoded CGMS/WSS data
Decoded CRC sequence for CGMS
Decoded CGMS/WSS data
x
x
x
x
0x7F
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
VDP_CGMS_WSS_DATA_2
(Read Only)
VDP_GS_VPS_PDC_UTC_0
(Read Only)
VDP_GS_VPS_PDC_UTC_1
(Read Only)
VDP_GS_VPS_PDC_UTC_2
(Read Only)
VDP_GS_VPS_PDC_UTC_3
(Read Only)
VDP_VPS_PDC_UTC_4
(Read Only)
VDP_VPS_PDC_UTC_5
(Read Only)
VDP_VPS_PDC_UTC_6
(Read Only)
VDP_VPS_PDC_UTC_7
(Read only)
VDP_VPS_PDC_UTC_8
(Read Only)
VDP_VPS_PDC_UTC_9
(Read Only)
VDP_VPS_PDC_UTC_10
(Read Only)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
GS_VPS_PDC_UTC_BYTE_0[7:0].
GS_VPS_PDC_UTC_BYTE_1[7:0].
GS_VPS_PDC_UTC_BYTE_2[7:0].
GS_VPS_PDC_UTC_BYTE_3[7:0].
VPS_PDC_UTC_BYTE_4[7:0].
VPS_PDC_UTC_BYTE_5[7:0].
VPS_PDC_UTC_BYTE_6[7:0].
VPS_PDC_UTC_BYTE_7[7:0].
VPS_PDC_UTC_BYTE_8[7:0].
VPS_PDC_UTC_BYTE_9[7:0].
VPS_PDC_UTC_BYTE_10[7:0].
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Decoded Gemstar/VPS/PDC/UTC data
Decoded Gemstar/VPS/PDC/UTC data
Decoded Gemstar/VPS/PDC/UTC data
Decoded Gemstar/VPS/PDC/UTC data
Decoded VPS/PDC/UTC data
Decoded VPS/PDC/UTC data
Decoded VPS/PDC/UTC data
Decoded VPS/PDC/UTC data
Decoded VPS/PDC/UTC data
Decoded VPS/PDC/UTC data
Decoded VPS/PDC/UTC data
Rev. A | Page 104 of 112
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Address Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x8F
0x90
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
VDP_VPS_PDC_UTC_11
(Read Only)
VDP_VPS_PDC_UTC_12
(Read Only)
VDP_VITC_DATA_0
(Read Only)
VDP_VITC_DATA_1
(Read Only)
VDP_VITC_DATA_2
(Read Only)
VDP_VITC_DATA_3
(Read only)
VDP_VITC_DATA_4
(Read Only)
VDP_VITC_DATA_5
(Read Only)
VDP_VITC_DATA_6
(Read Only)
VDP_VITC_DATA_7
(Read Only)
VDP_VITC_DATA_8
(Read Only)
VPS_PDC_UTC_BYTE_11[7:0].
x
x
x
x
x
x
x
x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_12[7:0].
VITC_DATA_0[7:0].
VITC_DATA_1[7:0].
VITC_DATA_2[7:0].
VITC_DATA_3[7:0].
VITC_DATA_4[7:0].
VITC_DATA_5[7:0].
VITC_DATA_6[7:0].
VITC_DATA_7[7:0].
VITC_DATA_8[7:0].
VITC_CRC[7:0].
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
0
Decoded VPS/PDC/UTC data
Decoded VITC data
Decoded VITC data
Decoded VITC data
Decoded VITC data
Decoded VITC data
Decoded VITC data
Decoded VITC data
Decoded VITC data
Decoded VITC data
Decoded VITC CRC data
VDP_VITC_CALC_CRC
(Read Only)
VDP_OUTPUT_SEL
Reserved.
WSS_CGMS_CB_CHANGE.
0
1
Disable content-based updating of
CGMS and WSS data
Enable content-based updating of CGMS
and WSS data
The AVAILABLE bit shows
the availability of data
only when its content has
changed
GS_VPS_PDC_UTC_CB_CHANGE.
I2C_GS_VPS_PDC_UTC[1:0].
0
1
Disable content-based updating of
Gemstar, VPS, PDC, and UTC data
Enable content-based updating of
Gemstar, VPS, PDC, and UTC data
0
0
1
1
0
1
0
1
Gemstar_1×/Gemstar_2×
Standard expected to be
decoded
VPS
PDC
UTC
Rev. A | Page 105 of 112
ADV7180
I2C PROGRAMMING EXAMPLES
ADV7180 LQFP-64
Mode 1 CVBS Input (Composite Video on AIN2)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
Table 105. Mode 1 CVBS Input
Register Address (Hex)
Register Value (Hex) Notes
00
04
17
31
3D
3E
3F
0E
55
0E
01
57
41
02
A2
6A
A0
80
81
00
INSEL = CVBS in on AIN2
Enable SFL
Select SH1
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
MWE enable manual window, color kill threshold to 2
BLM optimization
BGB optimization
Hidden space
ADC configuration
User space
Mode 2 S-Video Input (Y on AIN3 and C on AIN6)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 106. Mode 2 S-Video Input
Register Address (Hex)
Register Value (Hex) Notes
00
04
31
3D
3E
3F
58
0E
55
0E
08
57
02
A2
6A
A0
04
80
81
00
Insel = Y/C, Y = AIN3, C = AIN6
Enable SFL
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
MWE enable manual window, color kill threshold to 2
BLM optimization
BGB optimization
Mandatory write. This must be performed for correct operation.
Hidden space
ADC configuration
User space
Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN4, and Pb on AIN5)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 107. Mode 3 YPrPb Input
Register Address (Hex)
Register Value (Hex) Notes
00
31
3D
3E
3F
0E
55
0E
09
02
A2
6A
A0
80
81
00
INSEL = YPrPb, Y = AIN1, Pr = AIN4, Pb = AIN5
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
MWE enable manual window
BLM optimization
ADI recommended
Hidden space
ADC configuration
User space
Rev. A | Page 106 of 112
ADV7180
ADV7180 LFCSP-40
Mode 1 CVBS Input (Composite Video on AIN1)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P0 to P7
Table 108. Mode 1 CVBS Input
Register Address (Hex)
Register Value (Hex)
Notes
00
04
17
31
3D
3E
3F
0E
55
0E
00
57
41
02
A2
6A
A0
80
81
00
INSEL = CVBS in on AIN1
Enable SFL
Select SH1
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
MWE enable manual window, color kill threshold to 2
BLM optimization
BGB optimization
Hidden space
ADC configuration
User space
Mode 2 S-Video Input (Y on AIN1 and C on AIN2)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P0 to P7.
Table 109. Mode 2 S-Video Input
Register Address (Hex)
Register Value (Hex)
Notes
00
04
31
3D
3E
3F
58
0E
55
0E
06
57
02
A2
6A
A0
04
80
81
00
Insel = Y/C, Y = AIN1, C = AIN2
Enable SFL
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
MWE enable manual window, color kill threshold to 2
BLM optimization
BGB optimization
Mandatory write. This must be performed for correct operation.
Hidden space
ADC configuration
User space
Mode 3 525i/625i YPrPb Input (Y on AIN1, Pb on AIN2, and Pr on AIN3)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P0 to P7.
Table 110. Mode 3 YPrPb Input
Register Address (Hex)
Register Value (Hex)
Notes
00
31
3D
3E
3F
0E
55
0E
09
02
A2
6A
A0
80
81
00
INSEL = YPrPb, Y = AIN1, Pb = AIN2, Pr = AIN3
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
MWE enable manual window
BLM optimization
ADI recommended
Hidden space
ADC configuration
User space
Rev. A | Page 107 of 112
ADV7180
PCB LAYOUT RECOMMENDATIONS
Experience has repeatedly shown that the noise performance is
the same or better with a single ground plane. Using multiple
ground planes can be detrimental because each separate ground
plane is smaller, and long ground loops can result.
The ADV7180 is a high precision, high speed, mixed-signal
device. To achieve the maximum performance from the part, it
is important to have a well laid out PCB. The following is a
guide for designing a board using the ADV7180.
When using separate ground planes is unavoidable, placing a single
ground plane under the ADV7180 is recommended. The location
of the split should be under the ADV7180. In this case, it is even
more important to place components wisely because the current
loops are much longer, and current takes the path of least
resistance. An example of a current loop is a power plane to the
ADV7180 to the digital output trace to the digital data receiver to
the digital ground plane to the analog ground plane.
ANALOG INTERFACE INPUTS
Care should be taken when routing the inputs on the PCB.
Track lengths should be kept to a minimum, and 75 Ω trace
impedances should be used when possible. In addition, trace
impedances other than 75 Ω increase the chance of reflections.
POWER SUPPLY DECOUPLING
It is recommended to decouple each power supply pin with
0.1 μF and 10 nF capacitors. The fundamental idea is to have a
decoupling capacitor within about 0.5 cm of each power pin.
Also avoid placing the capacitor on the opposite side of the PCB
from the ADV7180, because doing so interposes resistive vias in
the path. The decoupling capacitors should be located between
the power plane and the power pin. Current should flow from
the power plane to the capacitor and then to the power pin. Do
not make the power connection between the capacitor and the
power pin. Placing a via underneath the 100 nF capacitor pads,
down to the power plane, is generally the best approach (see
Figure 51).
PLL
Place the PLL loop filter components as close as possible to the
ELPF pin. It should also be placed on the same side of the PCB
as the ADV7180. Do not place any digital or other high
frequency traces near these components. Use the values
suggested in the data sheet with tolerances of 10% or less.
VREFN AND VREFP
The circuit associated with these pins should be placed as close
as possible and on the same side of the PCB as the ADV7180.
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
VDD
VIA TO SUPPLY
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, requiring more
current and in turn causing more internal digital noise. Shorter
traces reduce the possibility of reflections.
10nF
100nF
GND
VIA TO GND
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7180.
If series resistors are used, place them as close as possible to the
ADV7180 pins. However, try not to add vias or extra length to
the output trace to make the resistors closer.
Figure 51. Recommended Power Supply Decoupling
It is particularly important to maintain low noise and good
stability of PVDD. Careful attention must be paid to regulation,
filtering, and decoupling. It is highly desirable to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD, DVDD, DVDDIO, and PVDD).
If possible, limit the capacitance that each of the digital outputs
drives to less than 15 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the ADV7180, creating more
digital noise on its power supplies.
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVDD, from a different,
cleaner power source, for example, from a 12 V supply.
The ADV7180 LFCSP-40 has an exposed metal paddle on the
bottom of the LFCSP package. This paddle must be soldered to
PCB ground for proper heat dissipation and also for noise and
mechanical strength benefits.
Using a single ground plane for the entire board is also
recommended. This ground plane should have a space between
the analog and digital sections of the PCB (see Figure 52).
DIGITAL INPUTS
The digital inputs on the ADV7180 are designed to work with
3.3 V signals and are not tolerant of 5 V signals. Extra
components are needed if 5 V logic signals are required to be
applied to the decoder.
ADV7180
ANALOG
SECTION
DIGITAL
SECTION
Figure 52. PCB Ground Layout
Rev. A | Page 108 of 112
ADV7180
TYPICAL CIRCUIT CONNECTION
Examples of how to connect the ADV7180 LQFP-64 and ADV7180 LFCSP-40 video decoder are shown in Figure 53 and Figure 54. For a
detailed schematic diagram for the ADV7180 evaluation boards, contact local Analog Devices field applications engineers or local Analog
Devices distributor.
D
_1.8V
D
A
_1.8V
ANALOG_INPUT_1
VDD
VDDIO
VDD
0.1µF
A
A
A
1
2
3
IN
IN
IN
36ꢀ
0.1µF
0.1µF
0.1µF
0.1µF
39ꢀ
10nF
10nF
10nF
10nF
ANALOG_INPUT_2
0.1µF
P
_1.8V
VDD
36ꢀ
D
_3.3V
VDDIO
39ꢀ
D
_1.8V
VDD
0.1µF
A
_1.8V
10nF
VDD
ANALOG_INPUT_3
0.1µF
P[0:7]
36ꢀ
39ꢀ
23
29
30
A
1
2
3
A
A
A
1
2
3
IN
IN
IN
IN
IN
IN
A
A
17
16
10
9
8
7
P0
P1
P2
P3
P4
P5
P6
P7
P0
P1
P2
P3
P4
P5
P6
P7
YCrCb
8-BIT
656 DATA
31
RESET
RESET
6
5
KEEP C14 AND C15 AS CLOSE AS POSSIBLE
TO THE ADV7180 AND ON THE SAME SIDE OF
THE PCB AS THE ADV7180.
ADV7180BCPZ
LFCSP–40
26
25
VREFN
VREFP
0.1µF
0.1µF
0.1µF
11
38
2
LLC
LLC
INTRQ
SFL
INTRQ
SFL
LOCATE CLOSE TO, AND ON THE
SAME SIDE AS, THE ADV7180.
13
12
XTAL
37
39
47pF
VS/FIELD
HS
VS/FIELD
HS
*
28.63636MHz
1Mꢀ
XTAL1
47pF
D
VDDIO
4kꢀ
32
ALSB
P
_1.8V
VDD
2
2
ALSB TIED HI ≥ I C ADDRESS = 42h
EXTERNAL
LOOP FILTER
ALSB TIED LOW ≥ I C ADDRESS = 40h
10nF
19
ELPF
18
PWRDWN
POWER_DOWN
82nF
34
33
SCLK
SCLK
SDA
1.69kꢀ
SDATA
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
*REFER TO ANALOG DEVICES
CRYSTAL APPLICATION NOTE
FOR PROPER CAPACITOR LOADING.
Figure 53. ADV7180 LFCSP-40 Typical Connection Diagram
Rev. A | Page 109 of 112
ADV7180
ANALOG_INPUT_1
Y
THE SUGGESTED INPUT ARRANGEMENT
IS AS SEEN ON THE EVAL BOARD AND IS
DIRECTLY SUPPORTED BY INSEL.
0.1µF
A
A
A
A
A
A
1
2
3
4
5
6
IN
IN
IN
IN
IN
IN
36ꢀ
39ꢀ
D
_1.8V
D
_1.8V
VDD
VDD
ANALOG_INPUT_2
CVBS
0.1µF
10nF
0.1µF
0.1µF
10nF
36ꢀ
39ꢀ
D
_3.3V
0.1µF
ANALOG_INPUT_3
YC_Y
A
_1.8V
10nF
VDDIO
VDD
0.1µF
0.1µF
36ꢀ
D
_3.3V
P
_1.8V
39ꢀ
VDDIO
VDD
10nF
ANALOG_INPUT_4
Cr
10nF
0.1µF
0.1µF
0.1µF
10nF
36ꢀ
39ꢀ
P[0:7]
ANALOG_INPUT_5
Cb
0.1µF
8-BIT
OUTPUT MODE
16-BIT
OUTPUT MODE
35
36
46
47
48
49
DATA BUS
P[0:7]
A
A
A
A
A
A
1
A
1
2
3
4
5
6
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
26
25
19
18
17
16
15
14
P0
P1
P2
P3
P4
P5
P6
P7
P0
P1
P2
P3
P4
P5
P6
P7
36ꢀ
---
Y
39ꢀ
2
3
4
5
6
A
A
A
A
A
P[8:15]
656/601 YCbCr
CbCr
ANALOG_INPUT_6
YC_C
0.1µF
P[8:15]
36ꢀ
39ꢀ
ADV7180BSTZ
8
7
6
5
62
61
60
59
P8
P9
LQFP–64
P8
P9
P10
P11
P12
P13
P14
P15
P10
P11
P12
P13
P14
P15
KEEP VREFN AND VREFP CAPS AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME
SIDE OF THE PCB AS THE ADV7180.
39
38
VREFN
VREFP
0.1µF
0.1µF
1
INTRQ
INT
55
56
12
13
GPO3
GPO2
GPO1
GPO0
GPO3
GPO2
GPO1
GPO0
DO NOT STUFF C19
0.1µF
22
21
XTAL
63
64
2
47pF
FIELD
VS
FIELD
*
28.63636MHz
1Mꢀ
VSYNC
HS
HS
XTAL1
RESET
47pF
9
SFL
SFL
P
_1.8V
VDD
27, 28, 33,
41, 42, 44,
45, 50
51
29
EXTERNAL
LOOP FILTER
RESET
NC
PWRDWN
POWER_DOWN
10nF
30
ELPF
D
_3.3V
VDDIO
82nF
4kꢀ
52
1.69kꢀ
ALSB
2
2
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
TIE HI: I C ADDRESS = 42
TIE LOW: I C ADDRESS = 40
20
LLC
LLC
33ꢀ
54
53
SCLK
SCLK
SDA
SDATA
33ꢀ
*REFER TO ANALOG DEVICES
CRYSTAL APPLICATION NOTE
FOR PROPER CAPACITOR LOADING.
NC = NO CONNECT
Figure 54. ADV7180 LQFP-64 Typical Connection Diagram
Rev. A | Page 110 of 112
ADV7180
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
4.25
4.10 SQ
3.95
5.75
BCS SQ
EXPOSED
PAD
(BOT TOM VIEW)
0.50
0.40
0.30
21
10
20
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
EXPOSED PADDLE MUST BE SOLDERED
TO PCB GROUND FOR PROPER
HEAT DISSIPATION, NOISE IMMUNITY AND
MECHANICAL STRENGTH BENEFITS.
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 55. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40)
Dimensions shown in millimeters
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
PLANE
17
32
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 56. 64-Lead Low Profile Quad Flat Package [LQFP]
10 mm × 10 mm Body
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADV7180BCPZ1
ADV7180BSTZ1
EVAL-ADV7180LQEB
EVAL-ADV7180LFEB
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board for the LQFP
CP-40
ST-64-2
Evaluation Board for LFCSP
1 Z = Pb-free part.
Note: The ADV7180 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes.
The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand
surface-mount soldering at up to 255°C ( 5°C).
In addition, it is backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be
soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C.
Rev. A | Page 111 of 112
ADV7180
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05700-0-11/06(A)
Rev. A | Page 112 of 112
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