ADV7342BSTZ_技术文档

Multiformat Video Encoder

Six, 11-Bit, 297 MHz DACs

ADV7342/ADV7343

EIA/CEA-861B compliance support

FEATURES

Programmable features

Luma and chroma filter responses

Vertical blanking interval (VBI)

Subcarrier frequency (F_SC) and phase

Luma delay

Copy generation management system (CGMS)

Closed captioning and wide screen signaling (WSS)

Integrated subcarrier locking to external video source

Complete on-chip video timing generator

On-chip test pattern generation

On-board voltage reference (optional external input)

Serial MPU interface with dual I²C® and SPI® compatibility

3.3 V analog operation

74.25 MHz 20-/30-bit high definition input support

Compliant with SMPTE 274M (1080i), 296M (720p),

and 240M (1035i)

6, 11-bit, 297 MHz video DACs

16× (216 MHz) DAC oversampling for SD

8× (216 MHz) DAC oversampling for ED

4× (297 MHz) DAC oversampling for HD

37 mA maximum DAC output current

NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support

NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)

Multiformat video input support

4:2:2 YCrCb (SD, ED, and HD)

4:4:4 YCrCb (ED and HD)

4:4:4 RGB (SD, ED, and HD)

Multiformat video output support

Composite (CVBS) and S-Video (Y/C)

Component YPrPb (SD, ED, and HD)

Component RGB (SD, ED, and HD)

Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant

Simultaneous SD and ED/HD operation

1.8 V digital operation

3.3 V I/O operation

Temperature range: −40°C to +85°C

APPLICATIONS

DVD recorders and players

High definition Blu-ray DVD players

HD-DVD players

FUNCTIONAL BLOCK DIAGRAM

ALSB/

SPI_SS

SCL/ SDA/

MOSI SCLK

SFL/

MISO

V

DGND (2)

V

(2)

AGND

AA

DD

ADV7342/ADV7343

GND_IO

VDD_IO

VBI DATA SERVICE

INSERTION

SUBCARRIER FREQUENCY

LOCK (SFL)

MPU PORT

11-BIT

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

YUV

16×

PROGRAMMABLE

LUMINANCE

FILTER

TO

ADD

FILTER

11-BIT

DAC 2

10-BIT

SD

YCrCb/

RGB

SYNC

RGB/YCrCb

TO

4:2:2 TO 4:4:4

YUV

HD DDR

DEINTERLEAVE

MATRIX

PROGRAMMABLE

CHROMINANCE

FILTER

11-BIT

DAC 3

16×

FILTER

VIDEO

DATA

ADD

BURST

SIN/COS DDS

BLOCK

R

11-BIT

DAC 4

RGB

ASYNC

BYPASS

RGB

G/B

11-BIT

DAC 5

YCbCr

TO

20-BIT

ED/HD

PROGRAMMABLE

HDTV FILTERS

RGB MATRIX

4×

FILTER

ED/HD INPUT

HDTV

TEST

PATTERN

GENERATOR

11-BIT

DAC 6

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

DEINTERLEAVE

VIDEO

DATA

POWER

MANAGEMENT

CONTROL

REFERENCE

AND CABLE

DETECT

16x/4x OVERSAMPLING

DAC PLL

VIDEO TIMING GENERATOR

R

(2)

SET

P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC CLKIN (2) PV

PGND EXT_LF (2)

V

COMP (2)

DD

REF

Figure 1.

Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.

Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7342/ADV7343

TABLE OF CONTENTS

Features .............................................................................................. 1

SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and

Timing Reset............................................................................... 49

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Detailed Features .............................................................................. 4

General Description......................................................................... 4

Specifications..................................................................................... 5

Power Supply and Voltage Specifications.................................. 5

Voltage Reference Specifications................................................ 5

Input Clock Specifications .......................................................... 5

Analog Output Specifications..................................................... 6

Digital Input/Output Specifications........................................... 6

Digital Timing Specifications ..................................................... 7

MPU Port Timing Specifications ............................................... 8

Power Specifications .................................................................... 8

Video Performance Specifications ............................................. 9

Timing Diagrams............................................................................ 10

Absolute Maximum Ratings.......................................................... 17

Thermal Resistance .................................................................... 17

ESD Caution................................................................................ 17

Pin Configuration and Function Descriptions........................... 18

Typical Performance Characteristics ........................................... 20

MPU Port Description................................................................... 25

I²C Operation.............................................................................. 25

SPI Operation.............................................................................. 26

Register Map Access....................................................................... 27

Register Programming............................................................... 27

Subaddress Register (SR7 to SR0) ............................................ 27

Input Configuration ....................................................................... 44

Standard Definition Only.......................................................... 44

Enhanced Definition/High Definition Only .......................... 45

SD VCR FF/RW Sync ................................................................ 50

Vertical Blanking Interval ......................................................... 50

SD Subcarrier Frequency Registers.......................................... 50

SD Noninterlaced Mode............................................................ 51

SD Square Pixel Mode ............................................................... 51

Filters............................................................................................ 52

ED/HD Test Pattern Color Controls ....................................... 53

Color Space Conversion Matrix ............................................... 53

SD Luma and Color Control..................................................... 54

SD Hue Adjust Control.............................................................. 55

SD Brightness Detect ................................................................. 55

SD Brightness Control............................................................... 55

SD Input Standard Auto Detection.......................................... 55

Double Buffering........................................................................ 56

Programmable DAC Gain Control.......................................... 56

Gamma Correction.................................................................... 56

ED/HD Sharpness Filter and Adaptive Filter Controls......... 58

ED/HD Sharpness Filter and Adaptive Filter Application

Examples...................................................................................... 59

SD Digital Noise Reduction...................................................... 60

SD Active Video Edge Control................................................. 61

External Horizontal and Vertical

Synchronization Control........................................................... 63

Low Power Mode........................................................................ 64

Cable Detection .......................................................................... 64

DAC Auto Power-Down............................................................ 64

Pixel and Control Port Readback............................................. 64

Reset Mechanism........................................................................ 64

Printed Circuit Board Layout and Design .................................. 65

DAC Configurations.................................................................. 65

Voltage Reference ....................................................................... 65

Video Output Buffer and Optional Output Filter.................. 65

Printed Circuit Board (PCB) Layout ....................................... 66

Typical Application Circuit....................................................... 68

Appendix 1—Copy Generation Management System .............. 69

SD CGMS .................................................................................... 69

ED CGMS.................................................................................... 69

HD CGMS................................................................................... 69

CGMS CRC Functionality ........................................................ 69

Simultaneous Standard Definition and Enhanced

Definition/High Definition....................................................... 45

Enhanced Definition Only (at 54 MHz) ................................. 46

Output Configuration.................................................................... 47

Features ............................................................................................ 48

Output Oversampling................................................................ 48

ED/HD Nonstandard Timing Mode........................................ 48

ED/HD Timing Reset ................................................................ 49

Rev. 0 | Page 2 of 88

ADV7342/ADV7343

Appendix 2—SD Wide Screen Signaling .....................................72

Appendix 3—SD Closed Captioning............................................73

Appendix 4—Internal Test Pattern Generation ..........................74

SD Test Patterns...........................................................................74

ED/HD Test Patterns ..................................................................74

Appendix 5—SD Timing................................................................75

Appendix 6—HD Timing ..............................................................80

Appendix 7—Video Output Levels...............................................81

SD YPrPb Output Levels—SMPTE/EBU N10........................81

ED/HD YPrPb Output Levels ...................................................82

SD/ED/HD RGB Output Levels................................................83

SD Output Plots ..........................................................................84

Appendix 8—Video Standards......................................................85

Outline Dimensions........................................................................87

Ordering Guide ...........................................................................87

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 88

ADV7342/ADV7343

either standard definition (SD), enhanced definition (ED), or

high definition (HD) video formats.

DETAILED FEATURES

High definition (HD) programmable features

(720p/1080i/1035i)

4× oversampling (297 MHz)

Internal test pattern generator

Fully programmable YCrCb to RGB matrix

Gamma correction

The ADV7342/ADV7343 each have a 24-bit pixel input port

that can be configured in a variety of ways. SD video formats

are supported over a SDR interface and ED/HD video formats

are supported over SDR and DDR interfaces. Pixel data can be

supplied in either the YCrCb or RGB color spaces.

Programmable adaptive filter control

Programmable sharpness filter control

CGMS (720p/1080i) and CGMS Type B (720p/1080i)

Undershoot limiter

Dual data rate (DDR) input support

EIA/CEA-861B compliance support

Enhanced definition(ED) programmable features

(525p/625p)

8× oversampling (216 MHz output)

Internal test pattern generator

Color and black bar, hatch, flat field/frame

Individual Y and PrPb output delay

Gamma correction

Programmable adaptive filter control

Fully programmable YCrCb to RGB matrix

Undershoot limiter

The parts also support embedded EAV/SAV timing codes,

external video synchronization signals, and I²C and SPI

communication protocols.

In addition, simultaneous SD and ED/HD input and output are

supported. 216 MHz (SD and ED) and 297 MHz (HD)

oversampling ensures that external output filtering is not

required, while full-drive DACs ensure that external output

buffering is not required.

Cable detection and DAC auto power-down features keep

power consumption to a minimum.

Table 1 lists the video standards directly supported by the

ADV7342/ADV7343.

Table 1. Standards Directly Supported by the

ADV7342/ADV7343¹

Macrovision Rev 1.2 (525p/625p)

CGMS (525p/625p) and CGMS Type B (525p)

Dual data rate (DDR) input support

EIA/CEA-861B compliance support

Standard definition (SD) programmable features

16× oversampling (216 MHz)

Frame

Clock Input

(MHz)

Resolution

720 × 240

720 × 288

720 × 480

I/P²Rate (Hz)

Standard

P

I

59.94

50

29.97

27

ITU-R

BT.601/656

Internal test pattern generator

Color and black bar

Controlled edge rates for start and end of active video

Individual Y and PrPb output delay

Undershoot limiter

720 × 576

720 × 480

720 × 576

I

25

27

ITU-R

BT.601/656

NTSC Square

Pixel

PAL Square

Pixel

29.97

25

24.54

29.5

Gamma correction

Digital noise reduction (DNR)

720 × 483

720 × 576

720 × 483

720 × 576

1920 × 1035

1280 × 720

P

I

59.94

50

59.94

50

30

29.97

60, 50, 30,

25, 24

23.97,

59.94, 29.97

30, 25

29.97

30, 25, 24

23.98, 29.97 74.1758

24 74.25

27

74.25

74.1758

74.25

SMPTE 293M

BTA T-1004

Multiple chroma and luma filters

Luma-SSAF™ filter with programmable gain/attenuation

PrPb SSAF™

Separate pedestal control on component and

composite/S-Video output

VCR FF/RW sync mode

Macrovision Rev 7.1.L1

Copy generation management system (CGMS)

Wide screen signaling

Closed captioning

ITU-R BT.1358

ITU-R BT.1362

SMPTE 240M

SMPTE 296M

I

P

1280 × 720

P

74.1758

SMPTE 296M

EIA/CEA-861B compliance support

1920 × 1080

I

P

74.25

74.1758

74.25

SMPTE 274M

ITU-R BT.709-5

GENERAL DESCRIPTION

The ADV7342/ADV7343 are high speed, digital-to-analog

video encoders in a 64-lead LQFP package. Six high speed, 3.3

V, 11-bit video DACs provide support for composite (CVBS), S-

Video (Y/C), and component (YPrPb/RGB) analog outputs in

¹Other standards are supported in the ED/HD nonstandard timing mode.

²I = interlaced, P = progressive.

Rev. 0 | Page 4 of 88

ADV7342/ADV7343

SPECIFICATIONS

POWER SUPPLY AND VOLTAGE SPECIFICATIONS

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 2.

Parameter

Conditions

Min

Typ

Max

Unit

SUPPLY VOLTAGES

V_DD

V_{DD_IO}

PV_DD

V_AA

1.71

2.97

1.71

2.6

1.8

3.3

1.8

3.3

1.89

3.63

1.89

3.465

V

POWER SUPPLY REJECTION RATIO

0.002

%/%

VOLTAGE REFERENCE SPECIFICATIONS

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 3.

Parameter

Conditions

Min

Typ

Max

1.31

Unit

V

Internal Reference Range, V_REF

External Reference Range, V_REF

External V_REFCurrent¹

1.186

1.15

1.248

1.235

10

μA

¹External current required to overdrive internal V_REF

.

INPUT CLOCK SPECIFICATIONS

V_DD= 1.71 V to 1.89 V. PV_DD= 1.71 V to 1.89 V. V_AA= 2.6 V to 3.465 V. V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 4.

Parameter

Conditions¹

Min

Typ

27

54

74.25

27

74.25

Max

Unit

f_{CLKIN_A}

SD/ED

MHz

f_{CLKIN_A}

ED (at 54 MHz)

f_{CLKIN_A}

f_{CLKIN_B}

HD

ED

HD

CLKIN_A High Time, t₉

CLKIN_A Low Time, t₁₀

CLKIN_B High Time, t₉

CLKIN_B Low Time, t₁₀

CLKIN_A Peak-to-Peak Jitter Tolerance

CLKIN_B Peak-to-Peak Jitter Tolerance

40

% of one clock cycle

ns

2

ns

¹SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.

Rev. 0 | Page 5 of 88

ADV7342/ADV7343

ANALOG OUTPUT SPECIFICATIONS

V_DD= 1.71 V to 1.89 V. PV_DD= 1.71 V to 1.89 V. V_AA= 2.6 V to 3.465 V. V_{DD_IO}= 2.97 V to 3.63 V. V_REF= 1.235 V (driven externally).

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 5.

Parameter

Conditions

Min

33

4.1

Typ

34.6

4.3

Max

37

4.5

Unit

mA

%

Full-Drive Output Current (Full-Scale)¹

Low Drive Output Current (Full-Scale)²

DAC-to-DAC Matching

R_SET= 510 Ω, R_L= 37.5 Ω

R_SET= 4.12 kΩ, R_L= 300 Ω

DAC 1 to DAC 6

1.0

Output Compliance, V_OC

0

1.4

V

Output Capacitance, C_OUT

DAC 1, DAC 2, DAC 3

DAC 4, DAC 5, DAC 6

DAC 1, DAC 2, DAC 3

DAC 4, DAC 5, DAC 6

DAC 1, DAC 2, DAC 3

DAC 4, DAC 5, DAC 6

10

6

8

6

2

pF

ns

Analog Output Delay³

DAC Analog Output Skew

1

ns

¹Applicable to full-drive capable DACs only, that is, DAC 1, DAC 2, DAC 3.

²Applicable to all DACs.

³Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.

DIGITAL INPUT/OUTPUT SPECIFICATIONS

V_DD= 1.71 V to 1.89 V. PV_DD= 1.71 V to 1.89 V. V_AA= 2.6 V to 3.465 V. V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 6.

Parameter

Conditions

Min

Typ

4

Max

Unit

V

μA

pF

V

μA

pF

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Leakage Current, I_IN

Input Capacitance, C_IN

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

2.0

0.8

10

V_IN= V_{DD_IO}

I_SOURCE= 400 μA

I_SINK= 3.2 mA

V_IN= 0.4 V, 2.4 V

2.4

0.4

1.0

4

Rev. 0 | Page 6 of 88

ADV7342/ADV7343

DIGITAL TIMING SPECIFICATIONS

V_DD= 1.71 V to 1.89 V. PV_DD= 1.71 V to 1.89 V. V_AA= 2.6 V to 3.465 V. V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 7.

Parameter

VIDEO DATA AND VIDEO CONTROL PORT^{2, 3}

Data Setup Time, t₁₁

Conditions¹

Min

Typ

Max

Unit

4

SD

2.1

2.3

1.7

1.0

1.1

1.0

2.1

2.3

1.7

1.0

1.1

1.0

ns

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

4

Data Hold Time, t₁₂

4

Control Setup Time, t₁₁

4

Control Hold Time, t₁₂

4

Digital Output Access Time, t₁₃

12

10

ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)

SD

4

Digital Output Hold Time, t₁₄

4.0

ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 3.5

PIPELINE DELAY⁵

SD¹

CVBS/YC Outputs (2×)

CVBS/YC Outputs (16×)

Component Outputs (2×)

Component Outputs (16×)

ED¹

SD oversampling disabled

SD oversampling enabled

SD oversampling disabled

SD oversampling enabled

68

67

78

84

clock cycles

Component Outputs (1×)

Component Outputs (8×)

HD¹

ED oversampling disabled

ED oversampling enabled

41

46

clock cycles

Component Outputs (1×)

Component Outputs (4×)

HD oversampling disabled

HD oversampling enabled

40

44

clock cycles

¹SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

²Video data: C[7:0], Y[7:0], and S[7:0].

³Video control:

,

, and

.

P_HSYNC P_VSYNC P_BLANK S_HSYNC

S_VSYNC

⁴Guaranteed by characterization.

⁵Guaranteed by design.

Rev. 0 | Page 7 of 88

ADV7342/ADV7343

MPU PORT TIMING SPECIFICATIONS

V_DD= 1.71 V to 1.89 V. PV_DD= 1.71 V to 1.89 V. V_AA= 2.6 V to 3.465 V. V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 8.

Parameter

MPU PORT, I²C MODE¹

Conditions

Min

Typ

Max

Unit

See Figure 19

SCL Frequency

SCL High Pulse Width, t₁

SCL Low Pulse Width, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDA, SCL Rise Time, t₆

SDA, SCL Fall Time, t₇

0

400

kHz

μs

ns

μs

0.6

1.3

0.6

100

300

Setup Time (Stop Condition), t₈

MPU PORT, SPI MODE¹

0.6

See Figure 20

SCLK Frequency

0

10

35

40

MHz

ns

SPI_SS to SCLK Setup Time, t₁

SCLK High Pulse Width, t₂

SCLK Low Pulse Width, t₃

Data Access Time after SCLK Falling Edge, t₄

Data Setup Time prior to SCLK Rising Edge, t₅

Data Hold Time after SCLK Rising Edge, t₆

SPI_SS to SCLK Hold Time, t₇

SPI_SS to MISO High Impedance, t₈

20

50

ns

20

0

ns

¹Guaranteed by characterization.

POWER SPECIFICATIONS

V_DD= 1.8 V, PV_DD= 1.8 V, V_AA= 3.3 V, V_{DD_IO}= 3.3 V, T_A= +25°C.

Table 9.

Parameter

Conditions

Min

Typ

Max

Unit

NORMAL POWER MODE^{1, 2}

3

I_DD

SD only (16× oversampling)

90

65

91

95

122

1

124

140

5

mA

ED only (8× oversampling)⁴

HD only (4× oversampling)⁴

SD (16× oversampling) and ED (8× oversampling)

SD (16× oversampling) and HD (4× oversampling)

I_{DD_IO}

I_AA

3 DACs enabled (ED/HD only)

6 DACs enabled (SD only and simultaneous modes )

SD only, ED only or HD only modes

Simultaneous modes

I_PLL

10

SLEEP MODE

I_DD

I_AA

I_{DD_IO}

I_PLL

5

μA

0.3

0.2

0.1

¹R_SET1= 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). R_SET2= 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).

²75% color bar test pattern applied to pixel data pins.

³I_DDis the continuous current required to drive the digital core.

⁴Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.

Rev. 0 | Page 8 of 88

ADV7342/ADV7343

VIDEO PERFORMANCE SPECIFICATIONS

V_DD= 1.8 V, PV_DD= 1.8 V, V_AA= 3.3 V, V_{DD_IO}= 3.3 V, T_A= 25°C, V_REFdriven externally.

Table 10.

Parameter

Conditions

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution

11

Bits

Integral Nonlinearity

R_SET1= 510 kΩ, R_L1= 37.5 Ω

R_SET2= 4.12 kΩ, R_L2= 300 Ω

R_SET1= 510 kΩ, R_L1= 37.5 Ω

R_SET2= 4.12 kΩ, R_L2= 300 Ω

R_SET1= 510 kΩ, R_L1= 37.5 Ω

R_SET2= 4.12 kΩ, R_L2= 300 Ω

0.4

0.5

0.15

0.5

0.25

0.2

LSBs

Differential Nonlinearity¹+ve

Differential Nonlinearity¹−ve

STANDARD DEFINTION (SD) MODE

Luminance Nonlinearity

Differential Gain

Differential Phase

Signal-to-Noise Ratio (SNR)

0.5

0.6

58

%

Degrees

dB

NTSC

Luma ramp

Flat field full bandwidth

75

dB

ENHANCED DEFINITION (ED) MODE

Luma Bandwidth

Chroma Bandwidth

12.5

5.8

MHz

HIGH DEFINITION (HD) MODE

Luma Bandwidth

Chroma Bandwidth

30

13.75

MHz

¹Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal

step value. For −ve DNL, the actual step value lies below the ideal step value.

Rev. 0 | Page 9 of 88

ADV7342/ADV7343

TIMING DIAGRAMS

The following abbreviations are used in Figure 2 to Figure 13:

•

t

₁₃= Control output access time

₁₄= Control output hold time

•

t₉= Clock high time

t₁₀= Clock low time

t₁₁= Data setup time

t₁₂= Data hold time

In addition, refer to Table 31 for the ADV7342/ADV7343 input

configuration.

CLKIN_A

t₁₂

t₉t₁₀

S_HSYNC,

S_VSYNC

CONTROL

INPUTS

IN SLAVE MODE

S7 TO S0/

Y7 TO Y0*

Y0

t₁₁

Y1

Y2

Cb0

Cr0

Cb2

t₁₃

Cr2

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

*SELECTED BY SUBADDRESS 0x01, BIT 7.

Figure 2. SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)

CLKIN_A

t₉

t₁₀

t₁₂

S_HSYNC,

S_VSYNC

CONTROL

INPUTS

IN SLAVE MODE

S7 TO S0/

Y7 TO Y0*

Y2

Y0

Y1

Y3

Y7 TO Y0/

C7 TO C0*

Cb2

Cb0

Cr0

Cr2

t₁₁

t₁₃

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

*SELECTED BY SUBADDRESS 0x01, BIT 7.

Figure 3. SD Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)

CLKIN_A

t₁₂

t₉

t₁₀

S_HSYNC,

S_VSYNC

CONTROL

INPUTS

Y7 TO Y0

C7 TO C0

G0

B0

G1

B1

G2

B2

t₁₁

S7 TO S0

R0

R1

R2

CONTROL

OUTPUTS

t₁₄

t₁₃

Figure 4. SD Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000)

Rev. 0 | Page 10 of 88

ADV7342/ADV7343

CLKIN_A

t₁₂

t₉t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Y7 TO Y0

C7 TO C0

Y0

Y1

Y2

Y3

Y4

Y5

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

Figure 5. ED/HD-SDR Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001)

CLKIN_A

t₁₂

t₉t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Y7 TO Y0

C7 TO C0

Y0

Y1

Y2

Y3

Y4

Y5

Cb1

t₁₁

Cb2

Cr2

Cb3

Cb4

Cb5

Cb0

Cr0

S7 TO S0

Cr1

Cr3

Cr4

Cr5

CONTROL

OUTPUTS

t₁₄

t₁₃

Figure 6. ED/HD-SDR Only, 24-Bit, 4:4:4 YCrCb Pixel Input Mode (Input Mode 001)

CLKIN_A

t₁₂

t₉t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Y7 TO Y0

C7 TO C0

G0

G1

G2

G3

B3

G4

B4

G5

B5

B0

R0

B1

t₁₁

B2

R2

S7 TO S0

R1

R3

R4

R5

CONTROL

OUTPUTS

t₁₄

t₁₃

Figure 7. ED/HD-SDR Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001)

Rev. 0 | Page 11 of 88

ADV7342/ADV7343

CLKIN_A*

t₉

t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Cb2

Y2

Cr2

Cb0

Y0

Cr0

Y1

Y7 TO Y0

t₁₂

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED

USING SUBADDRESS 0x01, BITS 1 AND 2.

HSYNC VSYNC

) Pixel Input Mode (Input Mode 010)

Figure 8. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (

/

CLKIN_A*

t₉

t₁₀

3FF

00

XY

Cb0

Y0

Cr0

Y1

Y7 TO Y0

t₁₂

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED

USING SUBADDRESS 0x01, BITS 1 AND 2.

Figure 9. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010)

CLKIN_B

t₁₂

t₉t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

ED/HD INPUT

Y7 TO Y0

C7 TO C0

Y0

Y1

Y2

Y3

Y5

Y4

Y6

Cb0

Cr0

t₁₁

Cb2

Cr2

Cb4

Cr4

Cb6

CLKIN_A

t₉t₁₀

t₁₂

S_HSYNC,

S_VSYNC

CONTROL

INPUTS

SD INPUT

S7 TO S0

Cb0

Y0

Cr0

t₁₁

Y1

Cb2

Y2

Cr2

Figure 10. SD and ED/HD-SDR, 16-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 011)

Rev. 0 | Page 12 of 88

ADV7342/ADV7343

CLKIN_B

t₉

t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

EH/HD INPUT

Y0

Cr0

Y1

t₁₂

Cb2

Y2

Cr2

Y7 TO Y0

Cb0

t₁₂

t₁₁

CLKIN_A

t₁₂

t₉

t₁₀

S_HSYNC,

S_VSYNC

CONTROL

INPUTS

SD INPUT

S7 TO S0

Cb0

Y0

Cr0

t₁₁

Y1

Cb2

Y2

Cr2

Figure 11. SD and ED/HD-DDR, 8-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 100)

CLKIN_A

t₉t₁₀

P_HSYNC,

CONTROL

INPUTS

P_VSYNC,

P_BLANK

Cb0

t₁₂

Y0

Cr0

Y1

Cb2

Cr2

Y7 TO Y0

Y2

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

HSYNC VSYNC

) Pixel Input Mode (Input Mode 111)

Figure 12. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (

/

CLKIN_A

t₉

t₁₀

Y7 TO Y0

3FF

00

XY

Cb0

Y0

Cr0

Y1

t₁₂

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

Figure 13. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111)

Rev. 0 | Page 13 of 88

ADV7342/ADV7343

Y OUTPUT

c

P_HSYNC

P_VSYNC

a

P_BLANK

Y7 TO Y0

Y2

Y3

Y0

Y1

Cb0 Cr0 Cb2 Cr2

C7 TO C0

b

a AND b AS PER RELEVANT STANDARD.

c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME

EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

/

Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb (

) Input Timing Diagram

Y OUTPUT

c

P_HSYNC

P_VSYNC

a

P_BLANK

Y7 TO Y0

Cr0 Y1

Cb0

Y0

b

a = 32 CLOCK CYCLES FOR 525p

a = 24 CLOCK CYCLES FOR 625p

AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLOCK CYCLES FOR 525p

b(MIN) = 264 CLOCK CYCLES FOR 625p

c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME

EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

) Input Timing Diagram

Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb (

/

Rev. 0 | Page 14 of 88

ADV7342/ADV7343

Y OUTPUT

c

P_HSYNC

P_VSYNC

a

P_BLANK

Y7 TO Y0

Y2

Y3

Y0

Y1

C7 TO C0

Cb0 Cr0 Cb2 Cr2

b

a AND b AS PER RELEVANT STANDARD.

c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

/

Figure 16. HD-SDR, 16-Bit, 4:2:2 YCrCb (

) Input Timing Diagram

Y OUTPUT

c

P_HSYNC

P_VSYNC

a

P_BLANK

Y7 TO Y0

Cr0 Y1

Cb0

Y0

b

a AND b AS PER RELEVANT STANDARD.

c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

) Input Timing Diagram

Figure 17. HD-DDR, 8-Bit, 4:2:2 YCrCb (

/

Rev. 0 | Page 15 of 88

ADV7342/ADV7343

S_HSYNC

S_VSYNC

Y7 TO Y0*

Cr

Y

Cb

Y

PAL = 264 CLOCK CYCLES

NTSC = 244 CLOCK CYCLES

*SELECTED BY SUBADDRESS 0x01, BIT 7.

Figure 18. SD Input Timing Diagram (Timing Mode 1)

t₅

t₃

SDA

t₆

t₁

SCL

t₂

t₇

t₄

t₈

Figure 19. MPU Port Timing Diagram (I²C Mode)

SPI_SS

SCLK

t₂

t₇

t₁

t₃

t₅

D4

t₆

D3

MOSI

MISO

D6

D5

X

D2

X

D1

X

D0

X

D7

X

t₄

D7

t₈

X

D6

D5

D4

D3

D2

D1

D0

Figure 20. MPU Port Timing Diagram (SPI Mode)

Rev. 0 | Page 16 of 88

ADV7342/ADV7343

ABSOLUTE MAXIMUM RATINGS

The ADV7342/ADV7343 are high performance integrated

circuits with an ESD rating of <1 kV, and it is ESD sensitive.

Proper precautions should be taken for handling and assembly.

Table 11.

Parameter¹

Rating

V_AAto AGND

V_DDto DGND

PV_DDto PGND

V_{DD_IO}to GND_IO

V_AAto V_DD

V_DDto PV_DD

V_{DD_IO}to V_DD

AGND to DGND

AGND to PGND

AGND to GND_IO

DGND to PGND

DGND to GND_IO

PGND to GND_IO

Digital Input Voltage to GND_IO

Analog Outputs to AGND

Storage Temperature Range (T_S)

Junction Temperature (T_J)

Lead Temperature (Soldering, 10 sec)

−0.3 V to +3.9 V

−0.3 V to +2.3 V

−0.3 V to +3.9 V

−0.3 V to +2.2 V

−0.3 V to +0.3 V

−0.3 V to +2.2 V

−0.3 V to +0.3 V

−0.3 V to V_{DD_IO}+ 0.3 V

−0.3 V to V_AA

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 12. Thermal Resistance¹

Package Type

θ_JA

θ_JC

Unit

64-Lead LQFP

47

11

°C/W

¹Values are based on a JEDEC 4 layer test board.

The ADV7342/ADV7343 are Pb-free products. The lead finish is

100% pure Sn electroplate. The devices are RoHS compliant,

suitable for Pb-free applications up to 255°C ( 5°C) IR reflow

(JEDEC STD-20).

They are backward-compatible with conventional SnPb

soldering processes. The electroplated Sn coating can be

soldered with Sn/Pb solder paste at conventional reflow

temperatures of 220°C to 235°C.

−65°C to +150°C

150°C

260°C

¹Analog output short circuit to any power supply or common can be of an

indefinite duration.

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 17 of 88

ADV7342/ADV7343

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

V

SFL/MISO

DD_IO

PIN 1

2

3

TEST0

TEST1

Y0

R

SET1

V

REF

4

COMP1

DAC 1

DAC 2

DAC 3

5

Y1

6

Y2

ADV7342/ADV7343

7

Y3

TOP VIEW

(Not to Scale)

8

Y4

V

AA

9

Y5

AGND

DAC 4

DAC 5

DAC 6

10

11

12

13

14

15

16

V

DD

DGND

Y6

Y7

R

SET2

COMP2

PV

TEST2

TEST3

C0

DD

EXT_LF1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 21. Pin Configuration

Table 13. Pin Function Descriptions

Input/

Output

Pin No.

Mnemonic

Description

13, 12,

9 to 4

29 to 25,

18 to 16

62 to 58,

55 to 53

Y7 to Y0

I

8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes.

8-Bit Pixel Port. C0 is the LSB. Refer to Table 31 for input modes.

8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes.

Unused. These pins should be connected to DGND.

C7 to C0

S7 to S0

52, 51, 15, TEST5 to

14, 3, 2

30

63

TEST0

CLKIN_A

CLKIN_B

I

Pixel Clock Input for HD Only (74.25 MHz), ED¹Only (27 MHz or 54 MHz) or SD Only (27 MHz).

Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a

74.25 MHz reference clock for HD operation.

50

49

S_HSYNC

S_VSYNC

I/O

SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD

horizontal synchronization signal. See the External Horizontal and Vertical Synchronization

Control section.

SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD

vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control

section.

22

23

P_HSYNC

P_VSYNC

I

ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical

Synchronization Control section.

ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization

Control section.

24

48

P_BLANK

SFL/MISO

I

ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.

I/O

Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is

used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.

47

R_SET1

I

This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive

operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R_SET1to

AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be

connected from R_SET1to AGND.

Rev. 0 | Page 18 of 88

ADV7342/ADV7343

Input/

Output

Pin No.

Mnemonic

Description

36

R_SET2

I

This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ

resistor must be connected from R_SET2to AGND.

45, 35

COMP1,

COMP2

DAC 1, DAC 2,

DAC 3

DAC 4, DAC 5,

DAC 6

SCL/MOSI

SDA/SCLK

ALSB/SPI_SS

V_REF

O

Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to V_AA.

44, 43, 42

39, 38, 37

DAC Outputs. Full and low drive capable DACs.

DAC Outputs. Low drive only capable DACs.

21

20

19

I

Multifunctional Pin: I²C Clock Input/SPI Data Input.

I/O

I

Multifunctional Pin: I²C Data Input/Output. Also, SPI clock input.

Multifunctional Pin: This signal sets up the LSB²of the MPU I²C address. Also, SPI slave select.

Optional External Voltage Reference Input for DACs or Voltage Reference Output.

Analog Power Supply (3.3 V).

46

41

10, 56

V_AA

V_DD

P

Digital Power Supply (1.8 V). For dual-supply configurations, V_DDcan be connected to other 1.8 V

supplies through a ferrite bead or suitable filtering.

1

34

V_{DD_IO}

PV_DD

P

Input/Output Digital Power Supply (3.3 V).

PLL Power Supply (1.8 V). For dual-supply configurations, PV_DDcan be connected to other 1.8 V

supplies through a ferrite bead or suitable filtering.

33

31

32

40

11, 57

64

EXT_LF1

EXT_LF2

PGND

AGND

DGND

I

G

External Loop Filter for On-Chip PLL 1.

External Loop Filter for On-Chip PLL 2.

PLL Ground Pin.

Analog Ground Pin.

Digital Ground Pin.

GND_IO

Input/Output Supply Ground Pin.

¹ED = enhanced definition = 525p and 625p.

²LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I²C address to 0xD4. Setting it to 1 sets the I²C address to 0xD6. In the ADV7343, setting the

LSB to 0 sets the I²C address to 0x54. Setting it to 1 sets the I²C address to 0x56.

Rev. 0 | Page 19 of 88

ADV7342/ADV7343

TYPICAL PERFORMANCE CHARACTERISTICS

Y RESPONSE IN ED 8× OVERSAMPLING MODE

EDPr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

0

1.0

0.5

–10

–20

–30

–40

–50

–60

–70

–80

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 22. ED 8× Oversampling, PrPb Filter (Linear) Response

Figure 25. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)

HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

10

EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

18.5

37.0

55.5

74.0

92.5

111.0 129.5 148.0

FREQUENCY (MHz)

Figure 23. ED 8× Oversampling, PrPb Filter (SSAF) Response

Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:2:2 Input)

HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE

Y RESPONSE IN ED 8× OVERSAMPLING MODE

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–100

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

10 20 30 40 50 60 70 80 90 100 110 120 130 140

FREQUENCY (MHz)

Figure 24. ED 8× Oversampling, Y Filter Response

Figure 27. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:4:4 Input)

Rev. 0 | Page 20 of 88

ADV7342/ADV7343

Y RESPONSE IN HD 4× OVERSAMPLING MODE

10

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

18.5

37.0

55.5

74.0

92.5

111.0 129.5 148.0

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 28. HD 4× Oversampling, Y Filter Response

Figure 31. SD PAL, Luma Low-Pass Filter Response

Y PASS BAND IN HD 4x OVERSAMPLING MODE

3.0

1.5

0

–10

–20

–30

–40

–50

–60

–70

0

–1.5

–3.0

–4.5

–6.0

–7.5

–9.0

–10.5

–12.0

27.750

46.250

30.063 32.375 34.688 37.000 39.312 41.625 43.937

FREQUENCY (MHz)

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 29. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)

Figure 32. SD NTSC, Luma Notch Filter Response

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

FREQUENCY (MHz)

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 30. SD NTSC, Luma Low-Pass Filter Response

Figure 33. SD PAL, Luma Notch Filter Response

Rev. 0 | Page 21 of 88

ADV7342/ADV7343

Y RESPONSE IN SD OVERSAMPLING MODE

5

4

0

–10

–20

–30

–40

–50

–60

–70

–80

3

2

1

0

–1

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

2

3

4

5

6

7

1

FREQUENCY (MHz)

Figure 34. SD, 16× Oversampling, Y Filter Response

Figure 37. SD Luma SSAF Filter, Programmable Gain

1

0

–10

–20

–30

–40

–50

–60

–70

–1

–2

–3

–4

–5

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 38. SD Luma SSAF Filter, Programmable Attenuation

Figure 35. SD Luma SSAF Filter Response up to 12 MHz

0

4

2

–10

0

–20

–30

–40

–50

–60

–70

–2

–4

–6

–8

–10

–12

0

2

4

6

8

10

12

0

1

2

3

4

6

7

5

FREQUENCY (MHz)

Figure 39. SD Luma CIF Low-Pass Filter Response

Figure 36. SD Luma SSAF Filter, Programmable Responses

Rev. 0 | Page 22 of 88

ADV7342/ADV7343

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 40. SD Luma QCIF Low-Pass Filter Response

Figure 43. SD Chroma 1.3 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

10

12

0

2

4

6

8

FREQUENCY (MHz)

Figure 44. SD Chroma 1.0 MHz Low-Pass Filter Response

Figure 41. SD Chroma 3.0 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

10

12

0

2

4

6

8

10

12

0

2

4

6

8

FREQUENCY (MHz)

Figure 45. SD Chroma 0.65 MHz Low-Pass Filter Response

Figure 42. SD Chroma 2.0 MHz Low-Pass Filter Response

Rev. 0 | Page 23 of 88

ADV7342/ADV7343

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 46. SD Chroma CIF Low-Pass Filter Response

Figure 47. SD Chroma QCIF Low-Pass Filter Response

Rev. 0 | Page 24 of 88

ADV7342/ADV7343

MPU PORT DESCRIPTION

Devices such as a microprocessor can communicate with the

ADV7342/ADV7343 through one of the following protocols:

line low during the ninth clock pulse. This is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition

occurs when the device monitors the SDA and SCL lines

waiting for the start condition and the correct transmitted

•

2-wire serial (I²C-compatible) bus

4-wire serial (SPI-compatible) bus

After power-up or reset, the MPU port is configured for I²C

operation. SPI operation can be invoked at any time by

following the procedure outlined in the SPI Operation section.

I²C OPERATION

W

address. The R/ bit determines the direction of the data.

Logic 0 on the LSB of the first byte means that the master writes

information to the peripheral. Logic 1 on the LSB of the first byte

means that the master reads information from the peripheral.

The ADV7342/ADV7343 support a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. This port

operates in an open-drain configuration. Two inputs, serial data

(SDA) and serial clock (SCL), carry information between any

device connected to the bus and the ADV7342/ADV7343. Each

slave device is recognized by a unique address. The ADV7342/

ADV7343 have four possible slave addresses for both read and

write operations. These are unique addresses for each device

and are illustrated in Figure 48. The LSB either sets a read or

write operation. Logic 1 corresponds to a read operation, while

Logic 0 corresponds to a write operation. A1 is controlled by

The ADV7342/ADV7343 act as a standard slave device on the

bus. The data on the SDA pin is eight bits long, supporting the

W

7-bit addresses plus the R/ bit. It interprets the first byte as

the device address and the second byte as the starting

subaddress. There is a subaddress auto-increment facility. This

allows data to be written to or read from registers in ascending

subaddress sequence starting at any valid subaddress. A data

transfer is always terminated by a stop condition. The user can

also access any unique subaddress register on a one-by-one

basis without updating all the registers.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCL high period, the

user should issue only a start condition, a stop condition, or a

stop condition followed by a start condition. If an invalid

subaddress is issued by the user, the ADV7342/ADV7343 do

not issue an acknowledge and do return to the idle condition. If

the user utilizes the auto-increment method of addressing the

encoder and exceeds the highest subaddress, the following

actions are taken:

SPI_SS

setting the ALSB/

pin of the ADV7342/ADV7343 to

Logic 0 or Logic 1.

1

0

1

0

1

A1

X

ADDRESS

CONTROL

SET UP BY

ALSB/SPI_SS

READ/WRITE

CONTROL

0

1

WRITE

READ

Figure 48. ADV7342 Slave Address = 0xD4 or 0xD6

•

In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge.

This indicates the end of a read. A no acknowledge

condition occurs when the SDA line is not pulled low on

the ninth pulse.

In write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by

the ADV7342/ADV7343, and the parts return to the idle

condition.

To control the various devices on the bus, use the following

protocol. The master initiates a data transfer by establishing

a start condition, defined by a high-to-low transition on SDA

while SCL remains high. This indicates that an address/data

stream follows. All peripherals respond to the start condition

•

W

and shift the next eight bits (7-bit address + R/ bit). The bits

are transferred from MSB down to LSB. The peripheral that

recognizes the transmitted address responds by pulling the data

Rev. 0 | Page 25 of 88

ADV7342/ADV7343

Figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 50 shows bus write and read

sequences.

SDA

SCL

S

P

9

1–7

9

1–7

8

1–7

8

START ADDR R/W ACK SUBADDRESS ACK

DATA

ACK

STOP

Figure 49. I²C Data Transfer

WRITE

S

SLAVE ADDR A(S)

LSB = 0

SUBADDR

A(S)

DATA

A(S)

DATA

A(M)

A(S) P

SEQUENCE

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S)

A(S)

S

SLAVE ADDR A(S)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A (S) = NO-ACKNOWLEDGE BY SLAVE

A (M) = NO-ACKNOWLEDGE BY MASTER

Figure 50. I²C Read and Write Sequence

There is a subaddress auto-increment facility. This allows data

to be written to or read from registers in ascending subaddress

sequence starting at any valid subaddress. The user can also

access any unique subaddress register on a one-by-one basis.

SPI OPERATION

The ADV7342/ADV7343 support a 4-wire serial (SPI-compatible)

bus connecting multiple peripherals. Two inputs, master out

slave in (MOSI) and serial clock (SCLK), and one output,

master in slave out (MISO), carry information between a

master SPI peripheral on the bus and the ADV7342/ADV7343.

Each slave device on the bus has a slave select pin that is

connected to the master SPI peripheral by a unique slave select

line. As such, slave device addressing is not required.

In a write data transfer, 8-bit data bytes are written to the

ADV7342/ADV7343, MSB first, on the MOSI line immediately

after the starting subaddress. The data bytes are clocked into the

ADV7342/ADV7343 on the rising edge of SCLK. When all data

bytes have been written, the master completes the transfer by

SPI_SS

driving and holding the ALSB/

In a read data transfer, after the subaddress has been clocked in

SPI_SS

pin high.

To invoke SPI operation, a master SPI peripheral (for example,

a microprocessor) should issue three low pulses on the ADV7342/

SPI_SS

ADV7343 ALSB/

pin. When the encoder detects the

SPI_SS

on the MOSI line, the ALSB/

for at least one clock cycle. Then, the ALSB/

and held low again. On the first SCLK rising edge after

SPI_SS

pin is driven and held high

third rising edge on the ALSB/

pin, it automatically

SPI_SS

pin is driven

switches to SPI communication mode. The ADV7342/ADV7343

remain in SPI communication mode until a reset or power-

down occurs.

ALSB/

has been driven low, the read command, defined

as 0xD5, is written, MSB first, to the ADV7342/ADV7343 over

the MOSI line. Subsequently, 8-bit data bytes are read from the

ADV7342/ADV7343, MSB first, on the MISO line. The data

bytes are clocked out of the ADV7342/ADV7343 on the falling

edge of SCLK. When all data bytes have been read, the master

completes the transfer by driving and holding the ALSB/

pin high.

To control the ADV7342/ADV7343, use the following protocol

for both read and write transactions. First, the master initiates a

data transfer by driving and holding the ADV7342/ADV7343

SPI_SS

ALSB/

pin low. On the first SCLK rising edge after

has been driven low, the write command, defined

SPI_SS

as 0xD4, is written to the ADV7342/ADV7343 over the MOSI

line. The second byte written to the MOSI line is interpreted as

the starting subaddress. Data on the MOSI line is written MSB

first and clocked on the rising edge of SCLK.

Rev. 0 | Page 26 of 88

ADV7342/ADV7343

REGISTER MAP ACCESS

A microprocessor can read from or write to all registers of the

ADV7342/ADV7343 via the MPU port, except for registers that

are specified as read-only or write-only registers.

REGISTER PROGRAMMING

Table 14 to Table 28 describe the functionality of each register.

All registers can be read from as well as written to, unless

otherwise stated.

The subaddress register determines which register the next

read or write operation accesses. All communication through

the MPU port starts with an access to the subaddress register.

A read/write operation is then performed from/to the target

address, which increments to the next address until the

transaction is complete.

SUBADDRESS REGISTER (SR7 TO SR0)

The subaddress register is an 8-bit write-only register. After the

MPU port is accessed and a read/write operation is selected, the

subaddress is set up. The subaddress register determines to or

from which register the operation takes place.

Table 14. Register 0x00

SR7 to

Bit Number

Register

Setting

Reset

Value

0x12

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x00

Power

Mode

Register

Sleep Mode. With this control enabled, the current consumption is

reduced to μA level. All DACs and the internal PLL circuit are

disabled. I²C registers can be read from and written to in sleep mode.

0

Sleep

mode off.

Sleep

1

mode on.

PLL and Oversampling Control. This control allows the internal PLL

circuit to be powered down and the oversampling to be switched off.

0

1

PLL on.

PLL off.

DAC 3: Power on/off.

DAC 2: Power on/off.

DAC 1: Power on/off.

DAC 6: Power on/off.

DAC 5: Power on/off.

DAC 4: Power on/off.

0

1

DAC 3 off.

DAC 3 on.

DAC 2 off.

DAC 2 on.

DAC 1 off.

DAC 1 on.

DAC 6 off.

DAC 6 on.

DAC 5 off.

DAC 5 on.

DAC 4 off.

DAC 4 on.

0

1

0

1

0

1

0

1

0

1

Rev. 0 | Page 27 of 88

ADV7342/ADV7343

Table 15. Register 0x01 to Register 0x09

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

0x01

Mode Select

Register

Reserved.

0

DDR Clock Edge Alignment.

Note: Only used for ED¹and

HD DDR modes.

0

Chroma clocked in on rising clock edge;

luma clocked in on falling clock edge.

Reserved.

Luma clocked in on rising clock edge;

chroma clocked in on falling clock edge.

0

1

0

1

Reserved.

0

Input Mode.

Note: See Reg. 0x30, Bits[7:3]

for ED/HD format selection.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SD input only.

ED/HD-SDR input only.

ED/HD-DDR input only.

SD and ED/HD-SDR.

SD and ED/HD-DDR.

Reserved.

ED only (at 54 MHz).

Y/C/S Bus Swap.

0

1

Allows data to be applied to data ports in

various configurations (SD feature only).

0x02

Mode

Register 0

Reserved.

Test Pattern Black Bar.²

0

0 must be written to these bits.

Disabled.

Enabled.

0x20

0

1

Manual CSC Matrix Adjust.

Sync on RGB.

0

1

Disable manual CSC matrix adjust.

Enable manual CSC matrix adjust.

No sync.

Sync on all RGB outputs.

RGB component outputs.

YPrPb component outputs.

No sync output.

0

1

RGB/YPrPb Output Select.

SD Sync Output Enable.

0

1

0

1

S_HSYNC

Output SD syncs on

S_VSYNC

and

pins.

ED/HD Sync Output Enable.

0

1

No sync output.

S_HSYNC

Output ED/HD syncs on

and

S_VSYNC

pins.

0x03

0x04

ED/HD CSC

Matrix 0

x

LSBs for GY.

0x03

0xF0

ED/HD CSC

Matrix 1

LSBs for RV.

LSBs for BU.

LSBs for GV.

LSBs for GU.

Bits[9:2 ] for GY.

x

0x05

0x06

0x07

0x08

0x09

ED/HD CSC

Matrix 2

x

0x4E

0x0E

0x24

0x92

0x7C

ED/HD CSC

Matrix 3

x

Bits[9:2] for GU.

Bits[9:2] for GV.

Bits[9:2] for BU.

Bits[9:2] for RV.

ED/HD CSC

Matrix 4

ED/HD CSC

Matrix 5

ED/HD CSC

Matrix 6

¹ED = enhanced definition = 525p and 625p.

²Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).

Rev. 0 | Page 28 of 88

ADV7342/ADV7343

Table 16. Register 0x0A to Register 0x10

SR7 to

Bit Number

Reset

SR0

Register

Bit Description

7

0

…

0

6

0

…

0

5

0

…

1

4

0

…

1

3

0

…

1

2

0

…

1

0

1

…

1

0

1

0

…

1

Register Setting

0%

+0.018%

+0.036%

…

Value

0x0A

DAC 4, DAC 5, DAC 6 Positive Gain to DAC Output Voltage.

Output Levels

0x00

+7.382%

+7.5%

0

1

0

Negative Gain to DAC Output Voltage.

1

0

−7.5%

1

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

1

…

1

0

…

1

−7.382%

−7.364%

…

−0.018%

0%

0x0B

DAC 1, DAC 2, DAC 3 Positive Gain to DAC Output Voltage.

Output Levels

0

0x00

0

…

0

…

0

1

0

…

1

0

…

1

0

…

1

0

…

1

0

1

…

1

0

1

0

…

1

0

+0.018%

+0.036%

…

+7.382%

+7.5%

Negative Gain to DAC Output Voltage.

1

0

−7.5%

1

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

1

…

1

0

…

1

−7.382%

−7.364%

…

−0.018%

0x0D

DAC Power Mode

DAC 1 Low Power Enable.

DAC 2 Low Power Enable.

DAC 3 Low Power Enable.

Reserved.

0

DAC 1 low power

disabled

DAC 1 low power

enabled

0x00

1

0

1

DAC 2 low power

disabled

DAC 2 low power

enabled

0

1

DAC 3 low power

disabled

DAC 3 low power

enabled

0

0x10

Cable Detection

DAC 1 Cable Detect

(Read Only).

0

1

Cable detected on

DAC 1

DAC 1 unconnected

0x00

DAC 2 Cable Detect

(Read Only).

0

1

Cable detected on

DAC 2

DAC 2 unconnected

Reserved.

0

Unconnected DAC

Auto Power-Down.

0

1

DAC auto power-

down disable

DAC auto power-

down enable

Reserved.

0

Rev. 0 | Page 29 of 88

ADV7342/ADV7343

Table 17. Register 0x12 to Register 0x17

SR7 to

Bit Number

Reset

Value

0xXX

SR0

Register

Bit Description

S[7:0] Readback.

Y[7:0] Readback.

C[7:0] Readback.

7

x

6

x

5

x

4

x

3

x

2

x

1

x

0

x

Register Setting

Read only

0x12

0x13

0x14

0x16

Pixel Port Readback (S Bus)

Pixel Port Readback (Y Bus)

Pixel Port Readback (C Bus)

Control Port Readback

Read only

P_BLANK

Read only

.

P_VSYNC

x

P_HSYNC

x

.

S_VSYNC

x

.

S_HSYNC

x

.

SFL/MISO.

x

Reserved.

0

0x17

Software Reset

Reserved.

0

0x00

Software Reset.

0

1

Writing a 1 resets the device;

this is a self-clearing bit

Reserved.

0

Rev. 0 | Page 30 of 88

ADV7342/ADV7343

Table 18. Register 0x30

SR7 to

Bit Number

Reset

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

Note

Value

0x30

ED/HD Mode

Register 1

ED/HD Output Standard.

0

EIA770.2 output.

EIA770.3 output.

ED

HD

0x00

0

1

0

EIA770.1 output

Output levels for full

input range.

1

Reserved.

ED/HD Input

Synchronization

Format.

0

1

External

,

HSYNC VSYNC

and field inputs.¹

Embedded EAV/SAV

codes.

ED/HD Input Mode.

0

SMPTE 293M,

ITU-BT.1358.

525p @ 59.94 Hz

0

1

0

1

0

1

0

1

0

1

Nonstandard timing mode.

BTA-1004, ITU-BT.1362.

ITU-BT.1358.

ITU-BT.1362.

SMPTE 296M-1,

SMPTE 274M-2.

525p @ 59.94 Hz

625p @ 50 Hz

720p @ 60/59.94 Hz

0

1

0

1

SMPTE 296M-3.

SMPTE 296M-4,

SMPTE 274M-5.

720p @ 50 Hz

720p @ 30/29.97 Hz

0

1

0

1

SMPTE 296M-6.

SMPTE 296M-7,

SMPTE 296M-8.

720p @ 25 Hz

720p @ 24/23.98 Hz

0

1

0

1

0

1

0

1

SMPTE 240M.

Reserved.

SMPTE 274M-4,

SMPTE 274M-5.

1035i @ 60/59.94 Hz

1080i @ 30/29.97 Hz

0

1

0

1

SMPTE 274M-6.

SMPTE 274M-7,

SMPTE 274M-8.

1080i @ 25 Hz

1080p @ 0/29.97 Hz

1

0

1

SMPTE 274M-9.

SMPTE 274M-10,

SMPTE 274M-11.

1080p @ 25 Hz

1080p @ 4/23.98 Hz

1

0

1

0

ITU-R BT.709-5.

Reserved.

1080Psf @ 24 Hz

10011–11111

¹Synchronization can be controlled with a combination of either

and

inputs or

and field inputs, depending on Subaddress 0x34, Bit 6.

HSYNC

VSYNC

Rev. 0 | Page 31 of 88

ADV7342/ADV7343

Table 19. Register 0x31 to Register 0x33

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Pixel data valid off.

Pixel data valid on.

0x31

ED/HD Mode

Register 2

ED/HD Pixel Data Valid.

Reserved.

0

ED/HD Test Pattern Enable.

0

1

ED/HD test pattern off.

ED/HD test pattern on.

Hatch.

ED/HD Test Pattern Hatch/Field.

ED/HD VBI Open.

0

1

Field/frame.

Disabled.

0

1

Enabled.

ED/HD Undershoot Limiter.

0

1

0

1

0

1

Disabled.

−11 IRE

−6 IRE

−1.5 IRE

ED/HD Sharpness Filter.

0

1

Disabled.

Enabled.

0x32

ED/HD Mode

Register 3

ED/HD Y Delay with Respect to Falling

0

1

0

1

0

1

0

1

0

0 clock cycles.

1 clock cycle.

2 clock cycles.

3 clock cycles.

4 clock cycles.

0 clock cycles.

1 clock cycle.

2 clock cycles.

3 clock cycles.

4 clock cycles.

Disabled.

0x00

HSYNC

Edge of

.

ED/HD Color Delay with Respect to

0

1

0

1

0

1

0

1

0

HSYNC

Falling Edge of

.

ED/HD CGMS.

0

1

Enabled.

ED/HD CGMS CRC.

0

1

Disabled.

Enabled.

0x33

ED/HD Mode

Register 4

ED/HD Cr/Cb Sequence.

0

1

HSYNC

0x68

Cb after falling edge of

Cr after falling edge of

.

HSYNC

.

Reserved.

0

0 must be written to these bits.

Sinc Compensation Filter on DAC 1,

DAC 2, DAC 3.

0

1

Disabled.

Enabled.

Reserved.

0

0 must be written to this bit.

ED/HD Chroma SSAF.

0

1

Disabled.

Enabled.

4:4:4

ED/HD Chroma Input.

0

1

4:2:2

ED/HD Double Buffering.

0

1

Disabled.

Enabled.

Rev. 0 | Page 32 of 88

ADV7342/ADV7343

Table 20. Register 0x34 to Register 0x35

SR7 to

Bit Number

Reset

Value

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

0x34

ED/HD Mode

Register 5

ED/HD Timing Reset.

Internal ED/HD timing counters enabled.

Resets the internal ED/HD timing counters.

0x48

1

HSYNC

VSYNC

0

1

ED/HD

Control.

HSYNC

output control (refer to Table 51).

1

0

1

Control.

VSYNC

output control (refer to Table 52).

ED/HD Blank Polarity.

0

1

P_BLANK

active high.

active low.

ED Macrovision Enable.

Reserved.

0

1

Macrovision disabled.

Macrovision enabled.

0

0 must be written to this bit.

VSYNC

/Field Input.

0

1

0 = field input.

ED/HD

VSYNC

1 =

input.

Horizontal/Vertical

Counters.²

0

1

Update field/line counter.

Field/line counter free running.

0x35

ED/HD Mode

Register 6

Reserved.

0

0x00

ED/HD RGB Input Enable.

0

1

Disabled.

Enabled.

ED/HD Sync on PrPb.

0

1

Disabled.

Enabled.

ED/HD Color DAC Swap.

0

1

DAC 2 = Pb, DAC 3 = Pr.

DAC 2 = Pr, DAC 3 = Pb.

Gamma Correction Curve A.

Gamma Correction Curve B.

Disabled.

ED/HD Gamma

Correction Curve Select.

0

1

ED/HD Gamma

Correction Enable.

0

1

Enabled.

ED/HD Adaptive

Filter Mode.

0

1

Mode A.

Mode B.

ED/HD Adaptive

Filter Enable

0

1

Disabled.

Enabled.

¹Used in conjunction with ED/HD sync in Subaddress 0x02, Bit 7, set to 1.

²When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

Rev. 0 | Page 33 of 88

ADV7342/ADV7343

Table 21. Register 0x36 to Register 0x43

SR7 to

Bit Number

Reset

SR0

Register

Bit Description

7

x

6

x

5

x

4

x

0

3

x

0

2

x

0

1

x

0

x

0

Register Setting Value

0x36

0x37

0x38

0x39

ED/HD Y Level¹

ED/HD Cr Level¹

ED/HD Cb Level¹

ED/HD Test Pattern Y Level.

ED/HD Test Pattern Cr Level.

ED/HD Test Pattern Cb Level.

Reserved.

Y level value

Cr level value

Cb level value

0xA0

0x80

ED/HD Mode

Register 7

ED/HD EIA/CEA-861B

Synchronization Compliance.

0

1

Disabled

Enabled

Reserved.

0

0x40

ED/HD Sharpness

Filter Gain

ED/HD Sharpness Filter Gain,

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

0x00

…

1

…

1

…

1

…

1

ED/HD Sharpness Filter Gain,

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

0x41

0x42

0x43

ED/HD CGMS

Data 0

ED/HD CGMS Data Bits.

0

C19 C18 C17 C16 CGMS C19 to C16 0x00

ED/HD CGMS

Data 1

C15 C14 C13 C12 C11 C10 C9

C8

C0

CGMS C15 to C8

CGMS C7 to C0

0x00

ED/HD CGMS

Data 2

C7

C6

C5

C4

C3

C2

C1

¹For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).

Table 22. Register 0x44 to Register 0x57

SR7 to

Bit Number

Register

Reset

Value

0x00

SR0

Register

Bit Description

7

x

6

5

x

4

x

3

x

2

x

1

x

0

Setting

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

B0

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

ED/HD Gamma A0

ED/HD Gamma A1

ED/HD Gamma A2

ED/HD Gamma A3

ED/HD Gamma A4

ED/HD Gamma A5

ED/HD Gamma A6

ED/HD Gamma A7

ED/HD Gamma A8

ED/HD Gamma A9

ED/HD Gamma B0

ED/HD Gamma B1

ED/HD Gamma B2

ED/HD Gamma B3

ED/HD Gamma B4

ED/HD Gamma B5

ED/HD Gamma B6

ED/HD Gamma B7

ED/HD Gamma B8

ED/HD Gamma B9

ED/HD Gamma Curve A (Point 24).

ED/HD Gamma Curve A (Point 32).

ED/HD Gamma Curve A (Point 48).

ED/HD Gamma Curve A (Point 64).

ED/HD Gamma Curve A (Point 80).

ED/HD Gamma Curve A (Point 96).

ED/HD Gamma Curve A (Point 128).

ED/HD Gamma Curve A (Point 160).

ED/HD Gamma Curve A (Point 192).

ED/HD Gamma Curve A (Point 224).

ED/HD Gamma Curve B (Point 24).

ED/HD Gamma Curve B (Point 32).

ED/HD Gamma Curve B (Point 48).

ED/HD Gamma Curve B (Point 64).

ED/HD Gamma Curve B (Point 80).

ED/HD Gamma Curve B (Point 96).

ED/HD Gamma Curve B (Point 128).

ED/HD Gamma Curve B (Point 160).

ED/HD Gamma Curve B (Point 192).

ED/HD Gamma Curve B (Point 224).

x

B1

B2

B3

B4

B5

B6

B7

B8

B9

Rev. 0 | Page 34 of 88

ADV7342/ADV7343

Table 23. Register 0x58 to Register 0x5D

SR7 to

Bit Number

Register

Setting

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Gain B = −1

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Gain B = −1

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x58

ED/HD Adaptive Filter Gain 1

ED/HD Adaptive Filter Gain 1,

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 1,

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

0x59

ED/HD Adaptive Filter Gain 2

ED/HD Adaptive Filter Gain 2,

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

0x00

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 2,

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

0x5A

ED/HD Adaptive Filter Gain 3

ED/HD Adaptive Filter Gain 3,

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

0x00

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 3,

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

0x5B

0x5C

0x5D

ED/HD Adaptive Filter

Threshold A

ED/HD Adaptive Filter Threshold A.

ED/HD Adaptive Filter Threshold B.

ED/HD Adaptive Filter Threshold C.

x

Threshold A 0x00

Threshold B 0x00

Threshold C 0x00

ED/HD Adaptive Filter

Threshold B

x

ED/HD Adaptive Filter

Threshold C

Rev. 0 | Page 35 of 88

ADV7342/ADV7343

Table 24. Register 0x5E to Register 0x6E

SR7 to

Bit Number

Register

Setting

Disabled

Enabled

Disabled

Enabled

H5 to H0

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

0x5E

ED/HD CGMS Type B

Register 0

ED/HD CGMS Type B

Enable.

ED/HD CGMS Type B

CRC Enable.

0

1

ED/HD CGMS Type B

Header Bits.

H5

H4

H3

H2

H1

H0

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

ED/HD CGMS Type B

Register 1

ED/HD CGMS Type B

Data Bits.

P7

P6

P5

P4

P3

P2

P1

P0

P7 to P0

0x00

ED/HD CGMS Type B

Register 2

ED/HD CGMS Type B

Data Bits.

P15

P23

P31

P39

P47

P55

P63

P71

P79

P87

P95

P14

P22

P30

P38

P46

P54

P62

P70

P78

P86

P94

P13

P21

P29

P37

P45

P53

P61

P69

P77

P85

P93

P12

P20

P28

P36

P44

P52

P60

P68

P76

P84

P92

P11

P19

P27

P35

P43

P51

P59

P67

P75

P83

P91

P10

P18

P26

P34

P42

P50

P58

P66

P74

P82

P90

P98

P9

P8

P15 to P8

ED/HD CGMS Type B

Register 3

ED/HD CGMS Type B

Data Bits.

P17

P25

P33

P41

P49

P57

P65

P73

P81

P89

P97

P16

P24

P32

P40

P48

P56

P64

P72

P80

P88

P96

P23 to P16

P31 to P24

P39 to P32

P47 to P40

P55 to P48

P63 to P56

P71 to P64

P79 to P72

P87 to P80

P95 to P88

P103 to P96

ED/HD CGMS Type B

Register 4

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 5

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 6

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 7

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 8

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 9

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 10

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 11

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 12

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 13

ED/HD CGMS Type B

Data Bits.

P103 P102 P101 P100 P99

ED/HD CGMS Type B

Register 14

ED/HD CGMS Type B

Data Bits.

P111 P110 P109 P108 P107 P106 P105 P104 P111 to P104 0x00

P119 P118 P117 P116 P115 P114 P113 P112 P119 to P112 0x00

P127 P126 P125 P124 P123 P122 P121 P120 P127 to P120 0x00

ED/HD CGMS Type B

Register 15

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 16

ED/HD CGMS Type B

Data Bits.

Rev. 0 | Page 36 of 88

ADV7342/ADV7343

Table 25. Register 0x80 to Register 0x83

SR7 to

Bit Number

Reset

Value

0x10

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

0

1

0

1

Register Setting

NTSC.

PAL B/D/G/H/I.

PAL M.

0x80

SD Mode

Register 1

SD Standard.

PAL N.

SD Luma Filter.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LPF NTSC.

LPF PAL.

Notch NTSC.

Notch PAL.

SSAF luma.

Luma CIF.

Luma QCIF.

Reserved.

1.3 MHz.

0.65 MHz.

1.0 MHz.

2.0 MHz.

SD Chroma Filter.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved.

Chroma CIF.

Chroma QCIF.

3.0 MHz.

0x82

SD Mode

Register 2

SD PrPb SSAF.

0

1

Disabled.

Enabled.

0x0B

SD DAC Output 1.

SD DAC Output 2.

SD Pedestal.

0

1

Refer to Table 32 in the Output

Configuration section.

0

1

Refer to Table 32 in the Output

Configuration section.

0

1

Disabled.

Enabled.

SD Square Pixel Mode.

SD VCR FF/RW Sync.

SD Pixel Data Valid.

SD Active Video Edge Control.

0

1

Disabled.

Enabled.

0

1

Disabled.

Enabled.

0

1

Disabled.

Enabled.

0

1

Disabled.

Enabled.

0x83

SD Mode

Register 3

SD Pedestal on YPrPb

Output.

0

1

No pedestal on YPrPb.

7.5 IRE pedestal on YPrPb.

Y = 700 mV/300 mV.

Y = 714 mV/286 mV.

700 mV p-p (PAL), 1000 mV p-p (NTSC).

700 mV p-p.

0x04

SD Output Levels Y.

0

1

SD Output Levels PrPb.

0

1

0

1

0

1

1000 mV p-p.

648 mV p-p.

SD VBI Open.

0

1

Disabled.

Enabled.

SD Closed Captioning

Field Control.

0

1

0

1

0

1

Closed captioning disabled.

Closed captioning on odd field only.

Closed captioning on even field only.

Closed captioning on both fields.

Reserved.

0

Rev. 0 | Page 37 of 88

ADV7342/ADV7343

Table 26. Register 0x84 to Register 0x89

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

VSYNC

7

6

5

4

3

2

1

0

1

Register Setting

0x84

SD Mode

Register 4

Disabled.

SD

-3H.

VSYNC

= 2.5 lines (PAL),

= 3 lines (NTSC).

SD SFL/SCR/TR Mode Select.

0

1

0

1

0

1

Disabled.

Subcarrier phase reset mode enabled.

Timing reset mode enabled.

SFL mode enabled.

720 pixels.

710 (NTSC), 702 (PAL).

Chroma enabled.

Chroma disabled.

Enabled.

SD Active Video Length.

SD Chroma.

0

1

0

1

SD Burst.

0

1

Disabled.

SD Color Bars.

0

1

Disabled.

Enabled.

SD Luma/Chroma Swap.

0

1

DAC 2 = luma, DAC 3 = chroma.

DAC 2 = chroma, DAC 3 = luma.

5.17 ꢀs.

0x86

SD Mode

Register 5

NTSC Color Subcarrier Adjust (Delay

from the falling edge of output

HSYNC pulse to start of color burst).

0

1

0

1

0

0x02

5.31 ꢀs.

5.59 ꢀs (must be set for Macrovision

compliance).

1

Reserved.

0

SD EIA/CEA-861B Synchronization

Compliance.

0

1

Disabled.

Enabled.

Reserved.

0

SD Horizontal/Vertical Counter

Mode.¹

0

1

Update field/line counter.

Field/line counter free running.

Normal.

Color reversal enabled.

Disabled.

SD RGB Color Swap.

0

1

0x87

SD Mode

Register 6

SD PrPb Scale.

0

1

0x00

Enabled.

SD Y Scale.

0

1

Disabled.

Enabled.

SD Hue Adjust.

0

1

Disabled.

Enabled.

SD Brightness.

0

1

Disabled.

Enabled.

SD Luma SSAF Gain.

SD Input Standard Auto Detect.

0

1

Disabled.

Enabled.

0

1

Disabled.

Enabled.

Reserved.

0

0 must be written to this bit.

SD YCrCb input.

SD RGB input.

SD RGB Input Enable.

0

1

Rev. 0 | Page 38 of 88

ADV7342/ADV7343

SR7 to

SR0

Bit Number

Reset

Register

Bit Description

Reserved.

7

6

5

4

3

2

1

0

Register Setting

Value

0x88

SD Mode

Register 7

0

0x00

SD Noninterlaced Mode.

0

1

Disabled.

Enabled.

SD Double Buffering.

SD Input Format.

0

1

Disabled.

Enabled.

0

1

0

1

0

1

8-bit input.

16-bit input.

Reserved.

SD Digital Noise Reduction.

SD Gamma Correction Enable.

SD Gamma Correction Curve Select.

SD Undershoot Limiter.

0

1

Disabled.

Enabled.

0

1

Disabled.

Enabled.

0

1

Gamma Correction Curve A.

Gamma Correction Curve B.

Disabled.

−11 IRE.

−6 IRE.

0x89

SD Mode

Register 8

0

1

0

1

0

1

0x00

−1.5 IRE.

Reserved.

0

0 must be written to this bit.

Disabled.

Enabled.

SD Black Burst Output on DAC

Luma.

0

1

SD Chroma Delay.

0

1

0

1

0

1

Disabled.

4 clock cycles.

8 clock cycles.

Reserved.

0

0 must be written to these bits.

¹When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

Rev. 0 | Page 39 of 88

ADV7342/ADV7343

Table 27. Register 0x8A to Register 0x98

SR7 to

Bit Number

Reset

Value

0x08

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Slave mode.

Master mode.

Mode 0.

Mode 1.

Mode 2.

0x8A

SD Timing Register 0

SD Slave/Master Mode.

SD Timing Mode.

0

1

0

1

0

1

Mode 3.

Reserved.

1

SD Luma Delay.

0

1

0

1

0

1

No delay.

2 clock cycles.

4 clock cycles.

6 clock cycles.

−40 IRE.

SD Minimum Luma Value.

SD Timing Reset.

0

1

−7.5 IRE.

x

A low-high-low transition

resets the internal SD

timing counters.

0x8B

SD Timing Register 1

(Note: Applicable in

master modes only,

that is, Subaddress

0x8A, Bit 0 = 1)

HSYNC

0

1

0

1

0

1

t_a= 1 clock cycle.

t_a= 4 clock cycles.

t_a= 16 clock cycles.

t_a= 128 clock cycles.

t_b= 0 clock cycles.

t_b= 4 clock cycles.

t_b= 8 clock cycles.

t_b= 18 clock cycles.

t_c= t_b.

0x00

SD

Width.

HSYNC VSYNC

to

0

1

0

1

0

1

Delay.

Rising

HSYNC VSYNC

to

Edge Delay (Mode 1 Only).

x

0

1

0

1

0

1

0

1

t_c= t_b+ 32 μs.

VSYNC

1 clock cycle.

4 clock cycles.

16 clock cycles.

128 clock cycles.

0 clock cycles.

1 clock cycle.

2 clock cycles.

3 clock cycles.

SD

Width (Mode 2 Only).

HSYNC

0

1

x

0

1

0

1

x

SD

to Pixel Data Adjust.

0x8C

0x8D

0x8E

0x8F

SD F_SCRegister 0¹

SD F_SCRegister 1¹

SD F_SCRegister 2¹

SD F_SCRegister 3¹

SD F_SCPhase

Subcarrier Frequency Bits[7:0].

Subcarrier Frequency Bits[15:8].

x

Subcarrier Frequency

Bits[7:0].

0x1F

0x7C

0xF0

0x21

x

Subcarrier Frequency

Bits[15:8].

Subcarrier Frequency

Bits[23:16].

Subcarrier Frequency

Bits[23:16].

Subcarrier Frequency

Bits[31:24].

Subcarrier Frequency

Bits[31:24].

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

Subcarrier Phase Bits[9:2].

x

Subcarrier Phase Bits[9:2]. 0x00

Extended Data Bits[7:0]. 0x00

Extended Data Bits[15:8]. 0x00

SD Closed Captioning Extended Data on Even Fields.

SD Closed Captioning Data on Odd Fields.

Data Bits[7:0].

Data Bits[15:8].

0x00

SD Closed Captioning Data on Odd Fields.

SD Pedestal Register 0

SD Pedestal Register 1

SD Pedestal Register 2

SD Pedestal Register 3

Pedestal on Odd Fields.

Pedestal on Even Fields.

17 16 15 14 13 12 11 10 Setting any of these bits 0x00

to 1 disables pedestal

25 24 23 22 21 20 19 18

17 16 15 14 13 12 11 10

25 24 23 22 21 20 19 18

0x00

on the line number

indicated by the bit

settings.

¹SD subcarrier frequency registers default to NTSC subcarrier frequency values.

Rev. 0 | Page 40 of 88

ADV7342/ADV7343

Table 28. Register 0x99 to Register 0xA5

SR7 to

Bit Number

Reset

SR0

Register

Bit Description

SD CGMS Data.

SD CGMS CRC.

7

6

5

4

3

2

1

0

Register Setting

Value

0x99

SD CGMS/WSS 0

x

CGMS Data Bits[C19:C16]

Disabled

0x00

0

1

Enabled

SD CGMS on Odd Fields.

SD CGMS on Even Fields.

SD WSS.

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0x9A

SD CGMS/WSS 1

SD CGMS/WSS 2

SD CGMS/WSS Data.

x

CGMS Data Bits[C13:C8] or

WSS Data Bits[W13:W8]

0x00

SD CGMS Data.

x

CGMS Data Bits[C15:C14]

0x9B

0x9C

SD CGMS/WSS Data.

x

CGMS Data Bits[C7:C0] or

WSS Data Bits[W7:W0]

0x00

SD Scale LSB

Register

LSBs for SD Y Scale Value.

LSBs for SD Cb Scale Value.

LSBs for SD Cr Scale Value.

LSBs for SD F_SCPhase.

SD Y Scale Bits[1:0]

SD Cb Scale Bits[1:0]

SD Cr Scale Bits[1:0].

Subcarrier Phase Bits[1:0]

SD Y Scale Bits[9:2]

SD Cb Scale Bits[9:2]

x

0x9D

0x9E

SD Y Scale Register SD Y Scale Value.

x

0x00

SD Cb Scale

Register

SD Cb Scale Value.

0x9F

0xA0

0xA1

SD Cr Scale Register SD Cr Scale Value.

SD Hue Register SD Hue Adjust Value.

x

SD Cr Scale Bits[9:2]

0x00

SD Hue Adjust Bits[7:0]

SD Brightness/WSS SD Brightness Value.

SD Blank WSS Data.

SD Brightness Bits[6:0]

0

1

Disabled

Enabled

−4 dB

…

0xA2

SD Luma SSAF

SD Luma SSAF Gain/Attenuation.

Note: Only applicable if

Register 0x87, Bit 4 = 1.

0

…

0

…

1

0

…

1

0

…

0

0x00

0 dB

…

1

…

1

…

0

…

0

…

+4 dB

Reserved.

0

0xA3

SD DNR 0

Coring Gain Border.

Note: In DNR mode, the values

in brackets apply.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No gain

0x00

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

Coring Gain Data.

Note: In DNR mode, the values

in brackets apply.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No gain

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

Rev. 0 | Page 41 of 88

ADV7342/ADV7343

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

0

4

0

3

0

2

0

1

0

Register Setting

0

0xA4

SD DNR 1

DNR Threshold.

0

1

…

1

…

1

…

1

…

1

…

1

…

0

…

62

1

63

Border Area.

0

1

2 pixels

4 pixels

Block Size Control.

DNR Input Select.

0

1

8 pixels

16 pixels

Filter A

Filter B

Filter C

0xA5

SD DNR 2

0

1

0

1

0

1

0

1

0

0x00

Filter D

DNR Mode.

0

1

DNR mode

DNR sharpness mode

0 pixel offset

1 pixel offset

…

DNR Block Offset.

0

…

1

0

…

1

0

…

1

0

1

…

0

1

14 pixel offset

15 pixel offset

Table 29. Register 0xA6 to Register 0xBB

SR7 to

Bit Number

Register

Reset

SR0

Register

Bit Description

7

6

5

x

4

x

3

x

2

x

1

x

0

x

Setting

Value

0x00

0xXX

0x0X

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

SD Gamma A 0

SD Gamma A 1

SD Gamma A 2

SD Gamma A 3

SD Gamma A 4

SD Gamma A 5

SD Gamma A 6

SD Gamma A 7

SD Gamma A 8

SD Gamma A 9

SD Gamma B 0

SD Gamma B 1

SD Gamma B 2

SD Gamma B 3

SD Gamma B 4

SD Gamma B 5

SD Gamma B 6

SD Gamma B 7

SD Gamma B 8

SD Gamma B 9

SD Brightness Detect

Field Count Register

SD Gamma Curve A (Point 24).

SD Gamma Curve A (Point 32).

SD Gamma Curve A (Point 48).

SD Gamma Curve A (Point 64).

SD Gamma Curve A (Point 80).

SD Gamma Curve A (Point 96).

x

A0

A1

A2

A3

A4

A5

SD Gamma Curve A (Point 128).

SD Gamma Curve A (Point 160).

SD Gamma Curve A (Point 192).

SD Gamma Curve A (Point 224).

SD Gamma Curve B (Point 24).

SD Gamma Curve B (Point 32).

SD Gamma Curve B (Point 48).

SD Gamma Curve B (Point 64).

SD Gamma Curve B (Point 80).

SD Gamma Curve B (Point 96).

SD Gamma Curve B (Point 128).

SD Gamma Curve B (Point 160).

SD Gamma Curve B (Point 192).

SD Gamma Curve B (Point 224).

SD Brightness Value.

A6

A7

A8

A9

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

Read only.

Reserved.

Read only.

Field Count.

Reserved.

Revision Code.

0

Rev. 0 | Page 42 of 88

ADV7342/ADV7343

Table 30. Register 0xE0 to Register 0xF1

SR7 to

Bit Number

Reset

SR0

Register¹

Bit Description

MV Control Bits.

MV Control Bit.

7

x

0

6

x

0

5

x

0

4

x

0

3

x

0

2

x

0

1

x

0

x

Register Setting

Value

0x00

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

Macrovision

Bits[7:1] must be 0.

¹Macrovision registers are available on the ADV7342 only.

Rev. 0 | Page 43 of 88

ADV7342/ADV7343

INPUT CONFIGURATION

Subaddress 0x01, Bit 7), with S0/Y0 being the LSB. The ITU-R

BT.601/656 input standard is supported.

The ADV7342/ADV7343 support a number of different input

modes. The desired input mode is selected using Subaddress

0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard

definition only (SD only) upon power-up. Table 31 provides an

overview of all possible input configurations. Each input mode

is described in detail in the following sections.

16-Bit 4:2:2 YCrCb Mode

Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1

In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on

Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on Subaddress

0x01, Bit 7), with S0/Y0 being the LSB.

STANDARD DEFINITION ONLY

Subaddress 0x01, Bits[6:4] = 000

The CrCb pixel data is input on Pin Y7 to Pin Y0 (or Pin C7 to

Pin C0, depending on Subaddress 0x01, Bit 7), with Y0/C0

being the LSB.

Standard definition (SD) YCrCb data can be input in 4:2:2 format.

Standard definition (SD) RGB data can be input in 4:4:4 format.

A 27 MHz clock signal must be provided on the CLKIN_A pin.

24-Bit 4:4:4 RGB Mode

S_HSYNC

Input synchronization signals are provided on the

S_VSYNC

Subaddress 0x87, Bit 7 = 1

and

pins.

In 24-bit 4:4:4 RGB input mode, the red pixel data is input on

Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to

Pin Y0, and the blue pixel data is input on Pin C7 to Pin C0.

S0, Y0, and C0 are the respective bus LSBs.

8-Bit 4:2:2 YCrCb Mode

Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0

In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is

input on Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on

Table 31. Input Configuration

S

Y

C

1

Input Mode

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

000 SD Only

Y/C/S Bus Swap (0x01[7]) = 0

8-Bit YCrCb²

16-Bit YCrCb^{2, 3}

YCrCb

Y

CrCb

Y/C/S Bus Swap (0x01[7]) = 1

8-Bit YCrCb²

16-Bit YCrCb^{2, 3}

YCrCb

Y

CrCb

B

SD RGB Input Enable (0x87[7]) = 1

24-Bit RGB³

001 ED/HD-SDR Only^{4, 5}

16-Bit YCrCb

R

G

ED/HD RGB Input Enable (0x35[1]) = 0

Y

CrCb

Cb

24-Bit YCrCb

Cr

R

Y

ED/HD RGB Input Enable (0x35[1]) = 1

24-Bit RGB³

G

B

010 ED/HD-DDR Only (8-Bit)⁵

011 SD and ED/HD-SDR (24-Bit)⁵

100 SD and ED/HD-DDR (16-Bit)⁵

111 ED Only (54 MHz) (8-Bit)⁵

YCrCb

YCrCb (SD)

Y (ED/HD)

YCrCb (ED/HD)

YCrCb

CrCb (ED/HD)

¹The input mode is determined by Subaddress 0x01, Bits[6:4].

²In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 26 for more information.

³External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.

⁴In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 19 for more information.

⁵ED = enhanced definition = 525p and 625p.

Rev. 0 | Page 44 of 88

ADV7342/ADV7343

24-Bit 4:4:4 YCrCb Mode

ADV7342/

ADV7343

Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0

2

S_VSYNC,

S_HSYNC

MPEG2

DECODER

In 24-bit 4:4:4 YCrCb input mode, the Y pixel data is input on

Pin Y7 to Pin Y0, with Y0 being the LSB.

27MHz

CLKIN_A

The Cr pixel data is input on Pin S7 to Pin S0, with S0 being

the LSB.

10

YCrCb

S[7:0] OR Y[7:0]*

The Cb pixel data is input on Pin C7 to Pin C0, with C0 being

the LSB.

*SELECTED BY SUBADDRESS 0x01, BIT 7.

Figure 51. SD Only Example Application

24-Bit 4:4:4 RGB Mode

ENHANCED DEFINITION/HIGH DEFINITION ONLY

Subaddress 0x35, Bit 1 = 1

Subaddress 0x01, Bits[6:4] = 001 or 010

In 24-bit 4:4:4 RGB input mode, the red pixel data is input on

Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to Pin

Y0, and the blue pixel data is input on Pin C7 to Pin C0. S0, Y0,

and C0 are the respective bus LSBs.

Enhanced definition (ED) or high definition (HD) YCrCb data

can be input in either 4:2:2 or 4:4:4 formats. If desired, dual data

rate (DDR) pixel data inputs can be employed (4:2:2 format only).

Enhanced definition (ED) or high definition (HD) RGB data

can be input in 4:4:4 format (single data rate only).

MPEG2

DECODER

ADV7342/

ADV7343

CLKIN_

A

The clock signal must be provided on the CLKIN_A pin. Input

YCrCb

10

P_HSYNC

synchronization signals are provided on the

P_VSYNC P_BLANK

,

Cb

Cr

Y

C[7:0]

S[7:0]

Y[7:0]

, and

pins.

INTERLACED TO

PROGRESSIVE

16-Bit 4:2:2 YCrCb Mode (SDR)

Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1

P_VSYNC,

P_HSYNC,

P_BLANK

3

In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is

input on Pin Y7 to Pin Y0, with Y0 being the LSB.

Figure 54. ED/HD Only Example Application

The CrCb pixel data is input on Pin C7 to Pin C0, with C0

being the LSB.

SIMULTANEOUS STANDARD DEFINITION AND

ENHANCED DEFINITION/HIGH DEFINITION

Subaddress 0x01, Bits[6:4] = 011 or 100

8-Bit 4:2:2 YCrCb Mode (DDR)

Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1

The ADV7342/ADV7343 are able to simultaneously process SD

4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz

SD clock signal must be provided on the CLKIN_A pin. The

ED/HD clock signal must be provided on the CLKIN_B pin. SD

In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input

on Pin Y7 to Pin Y0 upon either the rising or falling edge of

CLKIN_A. Y0 is the LSB.

S_HSYNC

input synchronization signals are provided on the

The CrCb pixel data is also input on Pin Y7 to Pin Y0

upon the opposite edge of CLKIN_A. Y0 is the LSB.

S_VSYNC

and

pins. ED/HD input synchronization signals are

P_HSYNC P_VSYNC

P_BLANK

pins.

provided on the

,

and

Whether the Y data is clocked in upon the rising or falling edge

of CLKIN_A is determined by Subaddress 0x01, Bits[2:1] (see

Figure 52 and Figure 53).

SD 8-Bit 4:2:2 YCrCb and ED/HD-SDR 16-Bit 4:2:2 YCrCb

The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin

S0, with S0 being the LSB.

CLKIN_A

The ED/HD 16-bit 4:2:2 Y pixel data is input on Pin Y7 to Pin

Y0, with Y0 being the LSB.

Y[7:0]

3FF

00

X

Y

Cb0

Y0

Cr0

Y1

The ED/HD 16-bit 4:2:2 CrCb pixel data is input on Pin C7 to

Pin C0, with C0 being the LSB.

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

SD 8-Bit 4:2:2 YCrCb and ED/HD-DDR 8-Bit 4:2:2 YCrCb

The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin

S0, with S0 being the LSB.

CLKIN_

A

The ED/HD-DDR 8-bit 4:2:2 Y pixel data is input on Pin Y7 to

Pin Y0 upon the rising or falling edge of CLKIN_B. Y0 is the LSB.

Y[7:0]

3FF

00

XY

Y0

Cb0

Y1

Cr0

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO11 IN THIS CASE.

The ED/HD-DDR 8-bit 4:2:2 CrCb pixel data is also input on Pin

Y7 to Pin Y0 upon the opposite edge of CLKIN_B. Y0 is the LSB.

Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

Rev. 0 | Page 45 of 88

ADV7342/ADV7343

Whether the ED/HD Y data is clocked in upon the rising

or falling edge of CLKIN_B is determined by Subaddress 0x01,

Bits[2:1] (See the input sequence shown in Figure 52 and

Figure 53).

ENHANCED DEFINITION ONLY (AT 54 MHz)

Subaddress 0x01, Bits[6:4] = 111

Enhanced definition (ED) YCrCb data can be input in an

interleaved 4:2:2 format on an 8-bit bus at a rate of 54 MHz.

A 54 MHz clock signal must be provided on the CLKIN_A pin.

S_VSYNC,

S_HSYNC

2

CrCb

P_HSYNC

Input synchronization signals are provided on the

P_VSYNC P_BLANK

,

SDTV

DECODER

27MHz

CLKIN_A

S[7:0]

, and

pins.

10

YCrCb

The interleaved pixel data is input on Pin Y7 to Pin Y0, with Y0

being the LSB.

ADV7342/

ADV7343

HDTV

DECODER

10

CrCb

Y

1080i

OR

C[7:0]

CLKIN_A

10

Y[7:0]

720p

OR

1035i

P_VSYNC,

P_HSYNC,

P_BLANK

3

Y[7:0]

3FF

00

XY

Cb0

Y0

Cr0

Y1

Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)

74.25MHz

CLKIN_B

MPEG2

DECODER

Figure 55. Simultaneous SD and ED Example Application

54MHz

CLKIN_A

YCrCb

S_VSYNC,

S_HSYNC

2

SDTV

DECODER

ADV7342/

ADV7343

27MHz

YCrCb

CLKIN_A

S[7:0]

10

YCrCb

10

Y[7:0]

INTERLACED TO

PROGRESSIVE

P_VSYNC,

P_HSYNC,

P_BLANK

3

ADV7342/

ADV7343

HDTV

DECODER

10

CrCb

Y

1080i

OR

C[7:0]

10

Figure 58. ED Only (at 54 MHz) Example Application

Y[7:0]

720p

OR

1035i

P_VSYNC,

P_HSYNC,

P_BLANK

3

74.25MHz

CLKIN_B

Figure 56. Simultaneous SD and HD Example Application

Rev. 0 | Page 46 of 88

ADV7342/ADV7343

OUTPUT CONFIGURATION

The ADV7342/ADV7343 support a number of different output configurations. Table 32 to Table 35 lists all possible output configurations.

Table 32. SD Only Output Configurations

RGB/YPrPb

SD DAC

Output 2

(0x82, Bit 2)

SD DAC

Output 1

(0x82, Bit 1)

Output Select¹

(0x02, Bit 5)

SD Luma/Chroma

Swap (0x84, Bit 7)

DAC 1 DAC 2

DAC 3

DAC 4 DAC 5

DAC 6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

G

B

R

CVBS

G

Luma

Chroma Luma

B

Luma

Chroma Luma

B

Luma

Chroma Luma

Pb

Luma

Chroma Luma

Pb

Chroma

CVBS

G

Y

CVBS

Y

Luma

Chroma Luma

B

Luma

Chroma Luma

Pb

Luma

Chroma Luma

Pb

Chroma

R

Chroma

G

Chroma CVBS

R

CVBS

Y

Pr

Chroma

Pr

Chroma

Pr

Luma

Chroma CVBS

Pr

Y

Chroma Luma CVBS

¹If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.

Table 33. ED/HD Only Output Configurations

RGB/YPrPb Output Select (0x02, Bit 5)

ED/HD Color DAC Swap (0x35, Bit 3)

DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6

0

1

0

1

0

1

G

Y

B

R

Pb

Pr

R

B

Pr

Pb

N/A

Table 34. Simultaneous SD and ED/HD Output Configurations

ED/HD Color

RGB/YPrPb Output DAC Swap

SD Luma/Chroma

Swap (0x84, Bit 7)

DAC 1

(ED/HD)

DAC 2

(ED/HD)

DAC 3

(ED/HD)

DAC 4

(SD)

DAC 5

(SD)

DAC 6

(SD)

Select (0x02, Bit 5)

(0x35, Bit 3)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

G

Y

B

R

Pb

Pr

R

B

Pr

Pb

CVBS

Luma

Chroma

Luma

Chroma

Luma

Chroma

Luma

Chroma

Luma

Chroma

Luma

Chroma

Luma

Chroma

Luma

Chroma

Table 35. ED Only (at 54 MHz) Output Configurations

RGB/YPrPb Output Select (0x02, Bit 5)

ED/HD Color DAC Swap (0x35, Bit 3)

DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6

0

1

0

1

0

1

G

Y

B

R

Pb

Pr

R

B

Pr

Pb

N/A

Rev. 0 | Page 47 of 88

ADV7342/ADV7343

FEATURES

ED/HD nonstandard timing mode can be enabled by setting

Subaddress 0x30, Bits[7:3] to 00001.

OUTPUT OVERSAMPLING

The ADV7342/ADV7343 include two on-chip phase locked

loops (PLLs) that allow for oversampling of SD, ED, and HD

video data. Table 36 shows the various oversampling rates

supported in the ADV7342/ADV7343.

A clock signal must be provided on the CLKIN_A pin.

P_HSYNC

P_VSYNC

and

must be toggled by the user to

generate the appropriate horizontal and vertical synchronization

pulses on the analog output from the encoder. Figure 59 illustrates

the various output levels that can be generated .Table 37 lists the

transitions required to generate these output levels.

SD Only, ED Only, and HD Only Modes

PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is

unused in these modes. PLL 1 is disabled by default and can be

enabled using Subaddress 0x00, Bit 1 = 0.

Embedded EAV/SAV timing codes are not supported in

ED/HD nonstandard timing mode.

SD and ED/HD Simultaneous Modes

The user must ensure that appropriate pixel data is applied to

the encoder where the blanking level is expected at the output.

Both PLL 1 and PLL 2 are used in simultaneous modes. The use

of two PLLs allows for independent oversampling of SD and

ED/HD video. PLL 1 is used to oversample SD video data, and

PLL 2 is used to oversample ED/HD video data. In simultaneous

modes, PLL 2 is always enabled. PLL 1 is disabled by default and

can be enabled using Subaddress 0x00, Bit 1 = 0.

Macrovision (ADV7342 only) and output oversampling are not

available in ED/HD nonstandard timing mode.

ANALOG

OUTPUT

b

ACTIVE VIDEO

a

ED/HD NONSTANDARD TIMING MODE

b

Subaddress 0x30, Bits[7:3] = 00001

BLANKING LEVEL

c

For any ED/HD input data that does not conform to the

standards available in the ED/HD input mode table

(Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing

mode can be used to interface to the ADV7342/ADV7343.

a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.

b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.

c = SYNCHRONIZATION PULSE LEVEL.

Figure 59. ED/HD Nonstandard Timing Mode Output Levels

Table 36. Output Oversampling Modes and Rates

Input Mode

Subaddress 0x01 [6:4]

PLL and Oversampling Control

Subaddress 0x00, Bit 1

Oversampling Mode and Rate

SD (2×)

SD (16×)

ED (1×)

ED (8×)

000

SD only

ED only

HD only

SD and ED

SD and HD

ED only (at 54 MHz)

1

0

1

0

1

0

1

0

1

0

1

0

001/010

011/100

111

HD (1×)

HD (4×)

SD (2×) and ED (8×)

SD (16×) and ED (8×)

SD (2×) and HD (4×)

SD (16×) and HD (4×)

ED only (at 54 MHz) (1×)

ED only (at 54 MHz) (8×)

111

Table 37. ED/HD Nonstandard Timing Mode Synchronization Signal Generation

Output Level Transition¹

P_HSYNC

P_VSYNC

b → c

c → a

a → b

c → b

1 → 0

0

1 → 0 or 0²

0 → 1

1

0

0 → 1

¹a = tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level.

2

P_VSYNC

If

= 1, it should transition to 0. If

= 0, it should remain at 0. If tri-level synchronization pulse generation is not required, should always be 0.

Rev. 0 | Page 48 of 88

ADV7342/ADV7343

Subcarrier Phase Reset (SCR) Mode

ED/HD TIMING RESET

Subaddress 0x34, Bit 0

In this mode (Subaddress 0x84, Bits[2:1] = 01), a low-to-high

transition on the SFL/MISO pin (Pin 48) resets the subcarrier

phase to 0 on the field following the subcarrier phase reset. This

reset signal must be held high for a minimum of one clock cycle.

An ED/HD timing reset is achieved by toggling the ED/HD

timing reset control bit (Subaddress 0x34, Bit 0) from 0 to 1.

In this state, the horizontal and vertical counters remain reset.

When this bit is set back to 0, the internal counters resume

counting. This timing reset applies to the ED/HD timing

counters only.

Because the field counter is not reset, it is recommended that

the reset signal be applied in Field 7 (PAL) or Field 3 (NTSC).

The reset of the phase then occurs on the next field, that is,

Field 1, lined up correctly with the internal counters. The field

count register at Subaddress 0xBB can be used to identify the

number of the active field.

SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER

PHASE RESET, AND TIMING RESET

Subaddress 0x84, Bits[2:1]

Subcarrier Frequency Lock (SFL) Mode

Together with the SFL/MISO pin and SD Mode Register 4

(Subaddress 0x84, Bits[2:1]), the ADV7342/ADV7343 can be used

in timing reset mode, subcarrier phase reset mode, or SFL mode.

In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7342

/ADV7343 can be used to lock to an external video source. The

SFL mode allows the ADV7342/ADV7343 to automatically alter

the subcarrier frequency to compensate for line length

variations. When the part is connected to a device such as an

ADV7403 video decoder (see Figure 62) that outputs a digital

data stream in the SFL format, the part automatically changes to

the compensated subcarrier frequency on a line-by-line basis.

This digital data stream is 67 bits wide, and the subcarrier is

contained in Bit 0 to Bit 21. Each bit is two clock cycles long.

Timing Reset (TR) Mode

In this mode (Subaddress 0x84, Bits[2:1] = 10), a timing reset is

achieved in a low-to-high transition on the SFL/MISO pin (Pin 48).

In this state, the horizontal and vertical counters remain reset.

Upon releasing this pin (set to low), the internal counters resume

counting, starting with Field 1, and the subcarrier phase is reset.

The minimum time the pin must be held high is one clock

cycle; otherwise, this reset signal might not be recognized. This

timing reset applies to the SD timing counters only.

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 4 OR 8

SC

307

310

313

320

NO TIMING RESET APPLIED

DISPLAY

START OF FIELD 1

F

PHASE = FIELD 1

SC

307

1

2

3

4

5

6

7

21

TIMING RESET PULSE

TIMING RESET APPLIED

Figure 60. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 10)

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 4 OR 8

SC

307

310

313

320

NO F RESET APPLIED

SC

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 1

SC

307

310

313

320

F

RESET PULSE

SC

F

RESET APPLIED

SC

Figure 61. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)

Rev. 0 | Page 49 of 88

ADV7342/ADV7343

CLKIN_A

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

LCC1

SFL

SFL/MISO

COMPOSITE

ADV7403

VIDEO

DECODER

1

VIDEO

P[19:12]

5

Y[7:0]/S[7:0]

4 BITS

RESERVED

14 BITS

SEQUENCE

4

H/L TRANSITION

COUNT START

RESET BIT

SUBCARRIER

PHASE

3

BIT

LOW

13

RESERVED

2

PLL INCREMENT

F

128

SC

21

0

RTC

6768

14

19

TIME SLOT 01

VALID INVALID

SAMPLE SAMPLE

8/LINE

LOCKED

CLOCK

5 BITS

RESERVED

1

2

FOR EXAMPLE, VCR OR CABLE.

F

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7342/ADV7343 F DDS REGISTER IS

SC

F

PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS.

SC

3

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

RESET ADV7342/ADV7343 DDS.

SELECTED BY SUBADDRESS 0x01, BIT 7.

4

5

Figure 62. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)

For the SMPTE 293M (525p) standard, VBI data can be

inserted on Line 13 to Line 42 of each frame, or on Line 6 to

Line 43 for the ITU-R BT.1358 (625p) standard.

SD VCR FF/RW SYNC

Subaddress 0x82, Bit 5

In DVD record applications where the encoder is used with a

decoder, the VCR FF/RW sync control bit can be used for non-

standard input video, that is, in fast forward or rewind modes.

VBI data can be present on Line 10 to Line 20 for NTSC and on

Line 7 to Line 22 for PAL.

In SD Timing Mode 0 (slave option), if VBI is enabled, the

blanking bit in the EAV/SAV code is overwritten. It is possible

to use VBI in this timing mode as well.

In fast forward mode, the sync information at the start of a new

field in the incoming video usually occurs before the correct

number of lines/fields is reached. In rewind mode, this sync

signal usually occurs after the total number of lines/fields is

reached. Conventionally, this means that the output video has

corrupted field signals because one signal is generated by the

incoming video and another is generated when the internal

line/field counters reach the end of a field.

If CGMS is enabled and VBI is disabled, the CGMS data is

nevertheless available at the output.

SD SUBCARRIER FREQUENCY REGISTERS

Subaddress 0x8C to Subaddress 0x8F

Four 8-bit registers are used to set up the subcarrier frequency.

The value of these registers is calculated using:

When the VCR FF/RW sync control is enabled (Subaddress 0x82,

Bit 5), the line/field counters are updated according to the

VSYNC

incoming

the incoming

signal and when the analog output matches

VSYNC

Subcarrier Frequency Register =

signal.

Number of subcarrier periods in one video line

× 2³²

This control is available in all slave-timing modes except

Slave Mode 0.

Number of 27 MHz clk cycles in one video line

where the sum is rounded to the nearest integer.

For example, in NTSC mode:

VERTICAL BLANKING INTERVAL

Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4

227.5

1716

⎛

⎜

⎝

⎞

⎟

⎠

Subcarrier Register Value =

×

³²= 569408543

2

The ADV7342/ADV7343 are able to accept input data that

contains VBI data (such as CGMS, WSS, and VITS) in SD, ED,

and HD modes.

where:

Subcarrier Register Value = 569408543d = 0×21F07C1F

SD F_SCRegister 0: 0x1F

SD F_SCRegister 1: 0x7C

SD F_SCRegister 2: 0xF0

SD F_SCRegister 3: 0x21

If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;

Subaddress 0x83, Bit 4 for SD), VBI data is not present at the

output and the entire VBI is blanked. These control bits are

valid in all master and slave timing modes.

Rev. 0 | Page 50 of 88

ADV7342/ADV7343

Programming the F_SC

A 27 MHz clock signal must be provided on the CLKIN_A pin.

Embedded EAV/SAV timing codes or external horizontal and

The subcarrier frequency register value is divided into four F_SC

registers as shown in the previous example. The four subcarrier

frequency registers must be updated sequentially, starting with

Subcarrier Frequency Register 0 and ending with Subcarrier

Frequency Register 3. The subcarrier frequency updates only

after the last subcarrier frequency register byte has been

received by the ADV7342/ADV7343.

S_HSYNC

vertical synchronization signals provided on the

S_VSYNC

and

pins can be used to synchronize the input pixel data.

All input configurations, output configurations and features

available in NTSC and PAL modes are available in SD non-

interlaced mode.

For 240p/59.94 Hz input, the ADV7342/ADV7343 should be

configured for NTSC operation and Subaddress 0x88, Bit 1

should be set to 1.

Typical F_SCValues

Table 38 outlines the values that should be written to the

subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

For 288p/50 Hz input, the ADV7342/ADV7343 should be

configured for PAL operation and Subaddress 0x88, Bit 1

should be set to 1.

Table 38. Typical F_SCValues

Subaddress

Description

NTSC

0x1F

0x7C

0xF0

0x21

PAL B/D/G/H/I

0xCB

0x8A

0x09

0x2A

SD SQUARE PIXEL MODE

Subaddress 0x82, Bit 4

0x8C

F_SC0

0x8D

F_SC1

0x8E

F_SC2

The ADV7342/ADV7343 can be used to operate in square pixel

mode (Subaddress 0x82, Bit 4). For NTSC operation, an input

clock of 24.5454 MHz is required. Alternatively, for PAL

operation, an input clock of 29.5 MHz is required.

0x8F

F_SC3

SD NONINTERLACED MODE

Subaddress 0x88, Bit 1

The internal timing logic adjusts accordingly for square pixel

mode operation. In square pixel mode, the timing diagrams

shown in Figure 63 and Figure 64 apply.

The ADV7342/ADV7343 support a SD noninterlaced mode.

Using this mode, progressive inputs at twice the frame rate of

NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively)

can be input into the ADV7342/ADV7343. The SD noninterlaced

mode can be enabled using Subaddress 0x88, Bit 1.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

r

C

b

8

0

F

A

B

A

B

A

B

8

0

C

b

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

272 CLOCK

1280 CLOCK

1536 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

344 CLOCK

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 63. Square Pixel Mode EAV/SAV Embedded Timing

HSYNC

FIELD

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 308 CLOCK CYCLES

NTSC = 236 CLOCK CYCLES

Figure 64. Square Pixel Mode Active Pixel Timing

Rev. 0 | Page 51 of 88

ADV7342/ADV7343

EXTENDED (SSAF) PrPb FILTER MODE

FILTERS

0

–10

–20

–30

–40

–50

–60

Table 39 shows an overview of the programmable filters

available on the ADV7342/ADV7343.

Table 39. Selectable Filters

Filter

Subaddress

0x80

0x82

0x33

SD Luma LPF NTSC

SD Luma LPF PAL

SD Luma Notch NTSC

SD Luma Notch PAL

SD Luma SSAF

SD Luma CIF

SD Luma QCIF

0

1

2

3

4

5

6

FREQUENCY (MHz)

SD Chroma 0.65 MHz

SD Chroma 1.0 MHz

SD Chroma 1.3 MHz

SD Chroma 2.0 MHz

SD Chroma 3.0 MHz

SD Chroma CIF

SD Chroma QCIF

SD PrPb SSAF

ED/HD Chroma Input

ED/HD Sinc Compensation Filter

ED/HD Chroma SSAF

Figure 65. PrPb SSAF Filter

If this filter is disabled, one of the chroma filters shown in

Table 40 can be selected and used for the CVBS or luma/

chroma signal.

Table 40. Internal Filter Specifications

Pass-Band

Filter

Ripple (dB)¹

0.16

3 dB Bandwidth (MHz)²

Luma LPF NTSC

Luma LPF PAL

Luma Notch NTSC

Luma Notch PAL

Luma SSAF

4.24

4.81

0.1

0.09

0.1

0.04

2.3/4.9/6.6

3.1/5.6/6.4

6.45

SD Internal Filter Response

Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0

Luma CIF

0.127

3.02

The Y filter supports several different frequency responses,

including two low-pass responses, two notch responses, an

extended (SSAF) response with or without gain boost

attenuation, a CIF response, and a QCIF response. The PrPb

filter supports several different frequency responses, including

six low-pass responses, a CIF response, and a QCIF response, as

shown in Figure 39 and Figure 40.

Luma QCIF

Monotonic

0.09

1.5

0.65

1

1.395

2.2

3.2

0.65

0.5

Chroma 0.65 MHz

Chroma 1.0 MHz

Chroma 1.3 MHz

Chroma 2.0 MHz

Chroma 3.0 MHz

Chroma CIF

0.048

Monotonic

Chroma QCIF

If SD SSAF gain is enabled (Subaddress 0x87, Bit 4), there are 13

response options in the −4 dB to +4 dB range. The desired response

can be programmed using Subaddress 0xA2. The variation of

frequency responses is shown in Figure 36 to Figure 38.

¹Pass-band ripple is the maximum fluctuation from the 0 dB response in the

pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz)

frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity

for a notch filter, where fc, f1, and f2 are the −3 dB points.

²3 dB bandwidth refers to the −3 dB cutoff frequency.

In addition to the chroma filters listed in Table 39, the ADV7342/

ADV7343 contain an SSAF filter specifically designed for the color

difference component outputs, Pr and Pb. This filter has a cutoff

frequency of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see

Figure 65). This filter can be controlled with Subaddress 0x82,

Bit 0.

Rev. 0 | Page 52 of 88

ADV7342/ADV7343

Table 41. Sample Color Values for EIA 770.2/EIA 770.3

ED/HD Output Standard Selection

ED/HD Sinc Compensation Filter Response

Subaddress 0x33, Bit 3

Sample Color

Y Value

Cr Value

Cb Value

The ADV7342/ADV7343 include a filter designed to counter

the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while

operating in ED/HD mode. This filter is enabled by default. It

can be disabled using Subaddress 0x33, Bit 3. The benefit of the

filter is illustrated in Figure 66 and Figure 67.

0.5

White

Black

Red

Green

Blue

Yellow

Cyan

235 (0xEB)

128 (0x80) 128 (0x80)

16

81

(0x10)

(0x51)

240 (0xF0)

90

(0x5A)

(0x36)

145 (0x91)

41 (0x29)

34

(0x22) 54

110 (0x6E)

240 (0xF0)

(0x10)

(0x10) 166 (0xA6)

106 (0x6A) 222 (0xDE) 202 (0xCA)

210 (0xD2) 146 (0x92) 16

170 (0xAA) 16

0.4

0.3

Magenta

0.2

COLOR SPACE CONVERSION MATRIX

0.1

Subaddress 0x03 to Subaddress 0x09

0

The internal color space conversion (CSC) matrix automatically

performs all color space conversions based on the input mode

programmed in the mode select register (Subaddress 0x01,

Bits[6:4]). Table 42 and Table 43 show the options available in

this matrix.

–0.1

–0.2

–0.3

–0.4

–0.5

An SD color space conversion from RGB-in to YPrPb-out is

possible. An ED/HD color space conversion from RGB-in to

YPrPb-out is not possible.

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 66. ED/HD Sinc Compensation Filter Enabled

0.5

0.4

Table 42. SD Color Space Conversion Options

YPrPb/RGB Out

RGB In/YCrCb In

(Reg. 0x87, Bit 7)

Input Output¹(Reg. 0x02, Bit 5)

0.3

YCrCb YPrPb

YCrCb RGB

1

0

1

0

1

0.2

0.1

RGB

YPrPb

RGB

0

–0.1

–0.2

–0.3

–0.4

–0.5

¹CVBS/YC outputs are available for all CSC combinations.

Table 43. ED/HD Color Space Conversion Options

YPrPb/RGB Out

Input Output (Reg. 0x02, Bit 5)

RGB In/YCrCb In

(Reg. 0x35, Bit 1)

YCrCb YPrPb

YCrCb RGB

1

0

1

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 67. ED/HD Sinc Compensation Filter Disabled

RGB

ED/HD TEST PATTERN COLOR CONTROLS

Subaddress 0x36 to Subaddress 0x38

ED/HD Manual CSC Matrix Adjust Feature

The ED/HD manual CSC matrix adjust feature provides custom

coefficient manipulation for color space conversions and is used

in ED and HD modes only. The ED/HD manual CSC matrix

adjust feature can be enabled using Subaddress 0x02, Bit 3.

Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38

are used to program the output color of the internal ED/HD

test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it

be the lines of the cross hatch pattern or the uniform field test

pattern. They are not functional as color controls for external

pixel data input.

Normally, there is no need to enable this feature because the CSC

matrix automatically performs the color space conversion based

on the input mode chosen (ED or HD) and the input and output

color spaces selected (see Table 43). For this reason, the ED/HD

manual CSC matrix adjust feature is disabled by default.

The values for the luma (Y) and the color difference (Cr and

Cb) signals used to obtain white, black, and saturated primary

and complementary colors conform to the ITU-R BT.601-4

standard.

Table 41 shows sample color values that can be programmed

into the color registers when the output standard selection is set

to EIA 770.2/EIA 770.3 (Subaddress 0x30, Bits[1:0] = 00).

Rev. 0 | Page 53 of 88

ADV7342/ADV7343

If RGB output is selected, the ED/HD CSC matrix scalar uses

the following equations:

input standard color space. The user should consider that the

color component conversion could use different scale values.

R = GY × Y + RV × Pr

For example, SMPTE 293M uses the following conversion:

R = Y + 1.402Pr

G = GY × Y − (GU × Pb) − (GV × Pr)

B = GY × Y + BU × Pb

G = Y – 0.714Pr – 0.344Pb

Note that subtractions are implemented in hardware.

B = Y + 1.773Pb

If YPrPb output is selected, the following equations are used:

The programmable CSC matrix is used for external ED/HD

pixel data and is not functional when internal test patterns are

enabled.

Y = GY × Y

Pr = RV × Pr

Pb = BU × Pb

where:

Programming the CSC Matrix

If custom manipulation of the ED/HD CSC matrix coefficients

is required for a YCrCb-to-RGB color space conversion, use the

following procedure:

GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0].

GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6].

GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4].

BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2].

RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].

1. Enable the ED/HD manual CSC matrix adjust feature

(Subaddress 0x02, Bit 3).

2. Set the output to RGB (Subaddress 0x02, Bit 5).

3. Disable sync on PrPb (Subaddress 0x35, Bit 2).

4. Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).

Upon power-up, the CSC matrix is programmed with the

default values shown in Table 44.

The GY value controls the green signal output level, the BU

value controls the blue signal output level, and the RV value

controls the red signal output level.

Table 44. ED/HD Manual CSC Matrix Default Values

Subaddress

Default

0x03

0xF0

0x4E

0x0E

0x24

0x92

0x7C

0x03

0x04

0x05

0x06

0x07

0x08

0x09

SD LUMA AND COLOR CONTROL

Subaddress 0x9C to Subaddress 0x9F

SD Y Scale, SD Cb Scale, and SD Cr Scale are three 10-bit

control registers that scale the SD Y, Cb, and Cr output levels.

Each of these registers represents the value required to scale the

Cb or Cr level from 0.0 to 2.0 times its initial value and the Y

level from 0.0 to 1.5 times its initial level. The value of these 10

bits is calculated using the following equation:

When the ED/HD manual CSC matrix adjust feature is enabled,

the default coefficient values in Subaddress 0x03 to

Subaddress 0x09 are correct for the HD color space only. The

color components are converted according to the following

1080i and 720p standards (SMPTE 274M, SMPTE 296M):

Y, Cb, or Cr Scale Value = Scale Factor × 512

For example, if Scale Factor = 1.3

Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6

Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)

Y, Cb, or Cr Scale Value = 1010 0110 10b

R = Y + 1.575Pr

G = Y − 0.468Pr − 0.187Pb

B = Y + 1.855Pb

Subaddress 0x9C, SD Scale LSB Register = 0x2A

Subaddress 0x9D, SD Y Scale Register = 0xA6

Subaddress 0x9E, SD Cb Scale Register = 0xA6

Subaddress 0x9F, SD Cr Scale Register = 0xA6

The conversion coefficients should be multiplied by 315 before

being written to the ED/HD CSC matrix registers This is

reflected in the default values for GY = 0x13B, GU = 0x03B,

GV = 0x093, BU = 0x248, and RV = 0x1F0.

Note that this feature affects all interlaced output signals, that is,

CVBS, Y/C, YPrPb, and RGB.

If the ED/HD manual CSC matrix adjust feature is enabled and

another input standard (such as ED) is used, the scale values for

GY, GU, GV, BU, and RV must be adjusted according to this

Rev. 0 | Page 54 of 88

ADV7342/ADV7343

For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE.

For NTSC without pedestal and for PAL, the setup can vary

from −7.5 IRE to +15 IRE.

SD HUE ADJUST CONTROL

Subaddress 0xA0

When enabled, the SD hue adjust control register (Subaddress

0xA0) is used to adjust the hue on the SD composite and chroma

outputs. This feature can be enabled using Subaddress 0x87, Bit 2.

The SD brightness control register is an 8-bit register. The seven

LSBs of this 8-bit register are used to control the brightness

level, which can be a positive or negative value.

Subaddress 0xA0 contains the bits required to vary the hue of

the video data, that is, the variance in phase of the subcarrier

during active video with respect to the phase of the subcarrier

during the color burst. The ADV7342/ADV7343 provide a

range of 22.5° in increments of 0.17578125°. For normal

operation (zero adjustment), this register is set to 0x80. Values

0xFF and 0x00 represent the upper and lower limits, respectively,

of the attainable adjustment in NTSC mode. Values 0xFF and

0x01 represent the upper and lower limits, respectively, of the

attainable adjustment in PAL mode.

For example, to add +20 IRE brightness level to an NTSC signal

with pedestal, write 0x28 to Subaddress 0xA1.

0 × (SD Brightness Value) =

0 × (IRE Value × 2.015631) =

0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28

To add –7 IRE brightness level to a PAL signal, write 0x72 to

Subaddress 0xA1.

0 × (SD Brightness Value) =

The hue adjust value is calculated using the following equation:

Hue Adjust (°) = 0.17578125° (HCR_d− 128)

0 × (IRE Value × 2.075631) =

0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b

0001110b into twos complement = 1110010b = 0x72

where HCR_dis the hue adjust control register (decimal)

For example, to adjust the hue by +4°, write 0x97 to the hue

adjust control register.

Table 45. Sample Brightness Control Values¹

Setup Level

(NTSC) with

Pedestal

Setup Level

(NTSC)

Without

Setup

Level

(PAL)

4

⎛

⎜

⎝

⎞

⎟

⎠

Brightness

Control

Value

+ 128 ≈ 151d = 0x97

0.17578125

Pedestal

where the sum is rounded to the nearest integer.

22.5 IRE

15 IRE

7.5 IRE

0 IRE

15 IRE

7.5 IRE

0 IRE

15 IRE

7.5 IRE

0 IRE

0x1E

0x0F

0x00

0x71

To adjust the hue by −4°, write 0x69 to the hue adjust control

register.

−7.5 IRE

−4

⎛

⎜

⎝

⎞

⎟

⎠

+ 128 ≈ 105d = 0x69

¹Values in the range of 0x3F to 0x44 could result in an invalid output signal.

SD INPUT STANDARD AUTO DETECTION

Subaddress 0x87, Bit 5

0.17578125

where the sum is rounded to the nearest integer.

SD BRIGHTNESS DETECT

The ADV7342/ADV7343 include an SD input standard auto-

detect feature. This SD feature can be enabled by setting

Subaddress 0x87, Bit 5 to 1.

Subaddress 0xBA

The ADV7342/ADV7343 allow monitoring of the brightness

level of the incoming video data. The SD brightness detect

register (Subaddress 0xBA) is a read-only register.

When enabled, the ADV7342/ADV7343 can automatically

identify an NTSC or PAL B/D/G/H/I input stream. The

ADV7342/ADV7343 automatically update the subcarrier

frequency registers with the appropriate value for the identified

standard. The ADV7342/ADV7343 are also configured to

correctly encode the identified standard.

SD BRIGHTNESS CONTROL

Subaddress 0xA1, Bits[6:0]

When this feature is enabled, the SD brightness/WSS control

register (Subaddress 0xA1) is used to control brightness by

adding a programmable setup level onto the scaled Y data. This

feature can be enabled using Subaddress 0x87, Bit 3.

The SD standard bits (Subaddress 0x80, Bits[1:0]) and the

subcarrier frequency registers are not updated to reflect the

identified standard. All registers retain their default or user-

defined values.

NTSC WITHOUT PEDESTAL

100 IRE

+7.5 IRE

0 IRE

–7.5 IRE

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

NO SETUP

VALUE ADDED

Figure 68. Examples of Brightness Control Values

Rev. 0 | Page 55 of 88

ADV7342/ADV7343

with respect to the reference video output signal. The overall

gain of the signal is reduced from the reference signal.

DOUBLE BUFFERING

Subaddress 0x33, Bit 7 for ED/HD,

Subaddress 0x88, Bit 2 for SD

The range of this feature is specified for 7.5% of the nominal

output from the DACs. For example, if the output current of the

DAC is 4.33 mA, the DAC gain control feature can change this

output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).

Double-buffered registers are updated once per field. Double

buffering improves overall performance, because modifications

to register settings are not made during active video, but take

effect prior to the start of the active video on the next field.

The reset value of the control registers is 0x00, that is, nominal

DAC current is output. Table 46 is an example of how the

output current of the DACs varies for a nominal 4.33 mA

output current.

Double buffering can be activated on the following ED/HD

registers using Subaddress 0x33, Bit 7: ED/HD Gamma A and

Gamma B curves, and ED/HD CGMS registers.

Double buffering can be activated on the following SD registers

using Subaddress 0x88, Bit 2: SD Gamma A and Gamma B

curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD

closed captioning, and SD Macrovision Bits[5:0] (Subaddress

0xE0, Bits[5:0]).

Table 46. DAC Gain Control

Reg. 0x0A or

Reg.0x0B

DAC

Current (mA) % Gain

Note

0100 0000 (0x40) 4.658

0011 1111 (0x3F) 4.653

0011 1110 (0x3E) 4.648

7.5000%

7.3820%

7.3640%

...

PROGRAMMABLE DAC GAIN CONTROL

Subaddress 0x0A to Subaddress 0x0B

...

It is possible to adjust the DAC output signal gain up or down

from its absolute level. This is illustrated in Figure 69.

0000 0010 (0x02) 4.43

0000 0001 (0x01) 4.38

0000 0000 (0x00) 4.33

0.0360%

0.0180%

0.0000%

DAC 4 to DAC 6 are controlled by Register 0x0A.

Reset value,

nominal

DAC 1 to DAC 3 are controlled by Register 0x0B.

CASE A

1111 1111 (0xFF) 4.25

1111 1110 (0xFE) 4.23

−0.0180%

−0.0360%

...

GAIN PROGRAMMED IN DAC OUTPUT LEVEL

REGISTERS, SUBADDRESS 0x0A, 0x0B

700mV

...

1100 0010 (0xC2) 4.018

1100 0001 (0xC1) 4.013

1100 0000 (0xC0) 4.008

−7.3640%

−7.3820%

−7.5000%

GAMMA CORRECTION

Subaddress 0x44 to Subaddress 0x57 for ED/HD,

Subaddress 0xA6 to Subaddress 0xB9 for SD

300mV

Generally, gamma correction is applied to compensate for the

nonlinear relationship between signal input and output

brightness level (as perceived on a CRT). It can also be applied

wherever nonlinear processing is used.

NEGATIVE GAIN PROGRAMMED IN

CASE B

DAC OUTPUT LEVEL REGISTERS,

SUBADDRESS 0x0A, 0x0B

700mV

Gamma correction uses the function

Signal_OUT= (Signal_IN)^γ

where γ = is the gamma correction factor.

300mV

Gamma correction is available for SD and ED/HD video. For

both variations, there are 20, 8-bit registers. They are used to

program the Gamma Correction Curve A and Gamma

Correction Curve B.

Figure 69. Programmable DAC Gain—Positive and Negative Gain

ED/HD gamma correction is enabled using Subaddress 0x35,

Bit 5. ED/HD Gamma Correction Curve A is programmed at

Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma

Correction Curve B is programmed at Subaddress 0x4E to

Subaddress 0x57.

In Case A of Figure 69, the video output signal is gained. The

absolute level of the sync tip and blanking level both increase

with respect to the reference video output signal. The overall

gain of the signal is increased from the reference signal.

In Case B of Figure 69, the video output signal is reduced. The

absolute level of the sync tip and blanking level both decrease

Rev. 0 | Page 56 of 88

ADV7342/ADV7343

SD gamma correction is enabled using Subaddress 0x88, Bit 6.

SD Gamma Correction Curve A is programmed at Subaddress

0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B

is programmed at Subaddress 0xB0 to Subaddress 0xB9.

To program the gamma correction registers, calculate the

10 programmable curve values using the following formula:

γ

⎛

⎜

⎝

⎞

⎟

⎠

n −16

240 −16

⎛

⎜

⎝

⎞

⎟

⎠

⎟

γ_n=

×(240 −16) + 16

Gamma correction is performed on the luma data only. The

user can choose one of two correction curves, Curve A or

Curve B. Only one of these curves can be used at a time. For

ED/HD gamma correction, curve selection is controlled using

Subaddress 0x35, Bit 4. For SD gamma correction, curve

selection is controlled using Subaddress 0x88, Bit 7.

where:

γ_nis the value to be written into the gamma correction register

for point n on the gamma correction curve.

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.

γ is the gamma correction factor.

For example, setting γ = 0.5 for all programmable curve data

points results in the following y_nvalues:

The shape of the gamma correction curve is controlled by

defining the curve response at 10 different locations along the

curve. By altering the response at these locations, the shape of

the gamma correction curve can be modified. Between these

points, linear interpolation is used to generate intermediate

values. Considering the curve has a total length of 256 points,

the 10 programmable locations are at points 24, 32, 48, 64, 80,

96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are

fixed and cannot be changed.

y₂₄= [(8/224)^0.5× 224] + 16 = 58

y₃₂= [(16/224)^0.5× 224] + 16 = 76

y₄₈= [(32/224)^0.5× 224] + 16 = 101

y₆₄= [(48/224)^0.5× 224] + 16 = 120

y₈₀= [(64/224)^0.5× 224] + 16 = 136

y₉₆= [(80/224)^0.5× 224] + 16 = 150

y₁₂₈= [(112/224)^0.5× 224] + 16 = 174

y₁₆₀= [(144/224)^0.5× 224] + 16 = 195

y₁₉₂= [(176/224)^0.5× 224] + 16 = 214

y₂₂₄= [(208/224)^0.5× 224] + 16 = 232

where the sum of each equation is rounded to the nearest integer.

From curve locations 16 to 240, the values at the programmable

locations and, therefore, the response of the gamma correction

curve should be calculated to produce the following result:

γ

x_DESIRED= (x_INPUT

)

where:

x_DESIREDis the desired gamma corrected output.

x_INPUTis the linear input signal.

γ is the gamma correction factor.

The gamma curves in Figure 70 and Figure 71 are examples only;

any user-defined curve in the range from 16 to 240 is acceptable.

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

300

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

VARIOUS GAMMA VALUES

300

250

SIGNAL OUTPUT

200

0.3

0.5

200

0.5

150

100

150

1.5

100

SIGNAL INPUT

50

1.8

50

0

50

100

150

LOCATION

200

250

0

50

100

150

LOCATION

200

250

Figure 70. Signal Input (Ramp) and Signal Output for Gamma 0.5

Figure 71. Signal Input (Ramp) and Selectable Output Curves

Rev. 0 | Page 57 of 88

ADV7342/ADV7343

The derivative of the incoming signal is compared to the three

programmable threshold values: ED/HD Adaptive Filter

Threshold A, B, and C (Subaddress 0x5B, Subaddress 0x5C,

and Subaddress 0x5D, respectively). The recommended

threshold range is 16 to 235, although any value in the range of

0 to 255 can be used.

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER

CONTROLS

Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D

There are three filter modes available on the ADV7342/ADV7343:

a sharpness filter mode and two adaptive filter modes.

ED/HD Sharpness Filter Mode

The edges can then be attenuated with the settings in the

ED/HD Adaptive Filter Gain 1, 2, and 3 registers (Subaddress

0x58, Subaddress 0x59, and Subaddress 0x5A, respectively), and

the ED/HD sharpness filter gain register (Subaddress 0x40).

To enhance or attenuate the Y signal in the frequency ranges

shown in Figure 72, the ED/HD sharpness filter must be

enabled (Subaddress 0x31, Bit 7) and the ED/HD adaptive filter

must be disabled (Subaddress 0x35, Bit 7).

There are two adaptive filter modes available. The mode

is selected using the ED/HD adaptive filter mode control

(Subaddress 0x35, Bit 6):

To select one of the 256 individual responses, the corresponding

gain values, which range from –8 to +7 for each filter, must be

programmed into the ED/HD sharpness filter gain register at

Subaddress 0x40.

•

Mode A is used when the ED/HD adaptive filter mode

control is set to 0. In this case, Filter B (LPF) is used in the

adaptive filter block. In addition, only the programmed

values for Gain B in the ED/HD sharpness filter gain

register and ED/HD Adaptive Filter Gain 1, 2, and 3

registers are applied when needed. The Gain A values are

fixed and cannot be changed.

ED/HD Adaptive Filter Mode

The ED/HD Adaptive Filter Threshold A, B, and C registers, the

ED/HD Adaptive Filter Gain 1, 2, and 3 registers, and the

ED/HD sharpness filter gain register are used in adaptive filter

mode. To activate the adaptive filter control, the ED/HD

sharpness filter and the ED/HD adaptive filter must be enabled

(Subaddress 0x31, Bit 7, and Subaddress 0x35, Bit 7, respectively).

•

Mode B is used when ED/HD adaptive filter mode control

is set to 1. In this mode, a cascade of Filter A and Filter B is

used. Both settings for Gain A and Gain B in the ED/HD

sharpness filter gain register and ED/HD Adaptive Filter

Gain 1, 2, and 3 registers become active when needed.

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

1.5

1.4

1.6

1.5

1.4

1.3

1.2

1.1

1.0

1.3

1.2

1.1

1.0

INPUT

SIGNAL:

STEP

ꢀ

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.9

0.8

0.7

0.6

0.5

0

2

4

6

8

10

12

FREQUENCY (MHz)

FILTER A RESPONSE (Gain Ka)

FREQUENCY (MHz)

FILTER B RESPONSE (Gain Kb)

FREQUENCY (MHz)

FREQUENCY RESPONSE IN SHARPNESS

FILTER MODE WITH Ka = 3 AND Kb = 7

Figure 72. ED/HD Sharpness and Adaptive Filter Control Block

Rev. 0 | Page 58 of 88

ADV7342/ADV7343

d

a

b

R2

R4

1

e

R1

c

f

1

R2

CH1 500mV

REF A

M 4.00µs

1 9.99978ms

CH1

ALL FIELDS

CH1 500mV

REF A

M 4.00µs

1 9.99978ms

CH1

ALL FIELDS

500mV 4.00µs

Figure 73. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER

APPLICATION EXAMPLES

Sharpness Filter Application

Adaptive Filter Control Application

The register settings in Table 48 are used to obtain the results

shown in Figure 75, that is, to remove the ringing on the input

Y signal, as shown in Figure 74. Input data is generated by an

external signal source.

The ED/HD sharpness filter can be used to enhance or

attenuate the Y video output signal. The register settings in

Table 47 were used to achieve the results shown in Figure 73.

Input data was generated by an external signal source.

Table 48. Register Settings for Figure 75

Subaddress

Register Setting

Table 47. ED/HD Sharpness Control

0x00

0x01

0xFC

0x38

Subaddress

Register Setting

Reference¹

0x02

0x20

0x00

0xFC

0x30

0x00

0x01

0x10

0x31

0x81

0x02

0x20

0x35

0x80

0x30

0x00

0x40

0x00

0x31

0x81

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0xAC

0x9A

0x88

0x28

0x3F

0x64

0x40

0x00

0x08

0x04

0x40

0x80

0x22

a

b

c

d

e

f

¹See Figure 73.

Figure 75. Output Signal from ED/HD Adaptive Filter (Mode A)

Figure 74. Input Signal to ED/HD Adaptive Filter

Rev. 0 | Page 59 of 88

ADV7342/ADV7343

When changing the adaptive filter mode to Mode B

(Subaddress 0x35, Bit 6), the output shown in Figure 76

can be obtained.

DNR MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

NOISE

SIGNAL PATH

INPUT FILTER

BLOCK

FILTER

SUBTRACT

OUTPUT

SIGNAL IN

Y DATA

INPUT

< THRESHOLD?

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

–

FILTER OUTPUT

> THRESHOLD

+

DNR OUT

MAIN SIGNAL PATH

DNR

SHARPNESS

MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

Figure 76. Output Signal from ED/HD Adaptive Filter (Mode B)

BLOCK OFFSET

SD DIGITAL NOISE REDUCTION

GAIN

Subaddress 0xA3 to Subaddress 0xA5

CORING GAIN DATA

CORING GAIN BORDER

NOISE

SIGNAL PATH

Digital noise reduction (DNR) is applied to the Y data only.

A filter block selects the high frequency, low amplitude compo-

nents of the incoming signal (DNR input select). The absolute

value of the filter output is compared to a programmable

threshold value (DNR threshold control). There are two DNR

modes available, DNR mode and DNR sharpness mode.

INPUT FILTER

BLOCK

FILTER

ADD SIGNAL

ABOVE

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

OUTPUT

Y DATA

INPUT

> THRESHOLD?

+

FILTER OUTPUT

< THRESHOLD

+

In DNR mode, if the absolute value of the filter output is smaller

than the threshold, it is assumed to be noise. A programmable

amount (coring gain border, coring gain data) of this noise

signal is subtracted from the original signal. In DNR sharpness

mode, if the absolute value of the filter output is less than the

programmed threshold, it is assumed to be noise. Otherwise, if

the level exceeds the threshold, now identified as a valid signal,

a fraction of the signal (coring gain border, coring gain data) is

added to the original signal to boost high frequency components

and sharpen the video image.

DNR OUT

MAIN SIGNAL PATH

Figure 77. SD DNR Block Diagram

Coring Gain Border—Subaddress 0xA3, Bits[3:0]

These four bits are assigned to the gain factor applied to border

areas. In DNR mode, the range of gain values is 0 to 1 in

increments of 1/8. This factor is applied to the DNR filter

output that lies below the set threshold range. The result is then

subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

In MPEG systems, it is common to process the video information

in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels ×

16 pixels for MPEG1 systems (block size control). DNR can be

applied to the resulting block transition areas that are known to

contain noise. Generally, the block transition area contains two

pixels. It is possible to define this area to contain four pixels

(border area).

Coring Gain Data—Subaddress 0xA3, Bits[7:4]

These four bits are assigned to the gain factor applied to the luma

data inside the MPEG pixel block. In DNR mode, the range of

gain values is 0 to 1 in increments of 1/8. This factor is applied

to the DNR filter output that lies below the set threshold range.

The result is then subtracted from the original signal.

It is also possible to compensate for variable block positioning

or differences in YCrCb pixel timing with the use of the DNR

block offset.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

The digital noise reduction registers are three 8-bit registers.

They are used to control the DNR processing.

Rev. 0 | Page 60 of 88

ADV7342/ADV7343

APPLY DATA

APPLY BORDER

DNR Mode Control—Subaddress 0xA5, Bit 4

CORING GAIN CORING GAIN

This bit controls the DNR mode selected. Logic 0 selects DNR

mode; Logic 1 selects DNR sharpness mode.

O X X X X X X O O X X X X X X O

OFFSET CAUSED

BY VARIATIONS IN

INPUT TIMING

DNR works on the principle of defining low amplitude, high

frequency signals as probable noise and subtracting this noise

from the original signal.

O X X X X X X O O X X X X X X O

DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O

In DNR mode, it is possible to subtract a fraction of the signal

that lies below the set threshold, assumed to be noise, from the

original signal. The threshold is set in DNR Register 1.

Figure 78. SD DNR Offset Control

DNR Threshold—Subaddress 0xA4, Bits[5:0]

These six bits are used to define the threshold value in the range

of 0 to 63. The range is an absolute value.

When DNR sharpness mode is enabled, it is possible to add a

fraction of the signal that lies above the set threshold to the

original signal, because this data is assumed to be valid data and

not noise. The overall effect is that the signal is boosted (similar

to using the extended SSAF filter).

Border Area—Subaddress 0xA4, Bit 6

When this bit is set to Logic 1, the block transition area can be

defined to consist of four pixels. If this bit is set to Logic 0, the

border transition area consists of two pixels, where one pixel

refers to two clock cycles at 27 MHz.

DNR Block Offset Control—Subaddress 0xA5, Bits[7:4]

Four bits are assigned to this control, which allows a shift of the

data block of 15 pixels maximum. Consider the coring gain

positions fixed. The block offset shifts the data in steps of one

pixel such that the border coring gain factors can be applied at the

same position regardless of variations in input timing of the data.

720 × 485 PIXELS

2-PIXEL

BORDER

(NTSC)

DATA

SD ACTIVE VIDEO EDGE CONTROL

Subaddress 0x82, Bit 7

The ADV7342/ADV7343 are able to control fast rising and

falling signals at the start and end of active video in order to

minimize ringing.

8 × 8 PIXEL BLOCK

Figure 79. SD DNR Border Area

When the active video edge control feature is enabled

Block Size Control—Subaddress 0xA4, Bit 7

(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last

three pixels of the active video on the luma channel are scaled

so that maximum transitions on these pixels are not possible.

This bit is used to select the size of the data blocks to be

processed. Setting the block size control function to Logic 1

defines a 16 pixel × 16 pixel data block, and Logic 0 defines an

8 pixel × 8 pixel data block, where one pixel refers to two clock

cycles at 27 MHz.

At the start of active video, the first three pixels are multiplied

by 1/8, 1/2, and 7/8, respectively. Approaching the end of active

video, the last three pixels are multiplied by 7/8, 1/2, and 1/8,

respectively. All other active video pixels pass through

unprocessed.

DNR Input Select Control—Subaddress 0xA5, Bits[2:0]

Three bits are assigned to select the filter, which is applied to the

incoming Y data. The signal that lies in the pass band of the

selected filter is the signal that is DNR processed. Figure 80

shows the filter responses selectable with this control.

1.0

FILTER D

0.8

FILTER C

0.6

0.4

0.2

0

FILTER B

FILTER A

1

2

3

4

5

6

0

FREQUENCY (MHz)

Figure 80. SD DNR Input Select

Rev. 0 | Page 61 of 88

ADV7342/ADV7343

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

DISABLED

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

ENABLED

100 IRE

87.5 IRE

50 IRE

12.5 IRE

0 IRE

Figure 81. Example of Active Video Edge Functionality

VOLTS

0.5

IRE:FLT

100

50

0

F2

L135

–50

2

0

4

6

8

10

12

Figure 82. Example of Video Output with Subaddress 0x82, Bit 7 = 0

VOLTS

IRE:FLT

100

50

0

0.5

0

F2

L135

–50

–2

0

2

4

6

8

10

12

Figure 83. Example of Video Output with Subaddress 0x82, Bit 7 = 1

Rev. 0 | Page 62 of 88

ADV7342/ADV7343

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL

For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input

S_HSYNC S_VSYNC P_HSYNC P_VSYNC

P_BLANK

pixel data or external synchronization signals provided on the

,

, and

pins (see

S_HSYNC

S_VSYNC

and

Table 49). It is also possible to output synchronization signals on the

pins (see Table 50 to Table 52).

Table 49. Timing Synchronization Signal Input Options

Signal

Condition

HSYNC

S_HSYNC

S_VSYNC

P_HSYNC

P_VSYNC

P_BLANK

SD Slave Timing Mode 1, 2, or 3 Selected (Subaddress 0x8A[2:0]).¹

ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).

SD

In

VSYNC

/FIELD In

HSYNC

ED/HD

In

VSYNC

/FIELD In

In

BLANK

¹SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).

Table 50. Timing Synchronization Signal Output Options

Signal

Condition

HSYNC

S_HSYNC

S_VSYNC

S_HSYNC

S_VSYNC

SD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 6 = 1).¹

ED/HD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 7 = 1).

SD

Out

VSYNC

/FIELD Out

HSYNC

ED/HD

Out

VSYNC

/FIELD Out

¹ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).

1

S_HSYNC

Table 51.

Output Control

ED/HD HSYNC

Control

(0x34, Bit 1)

ED/HD Sync

Output Enable

(0x02, Bit 7)

SD Sync

Output Enable

(0x02, Bit 6)

ED/HD Input Sync

Format (0x30, Bit 2)

Signal on S_HSYNC Pin

Duration

x

0

1

Tristate.

–

HSYNC

Pipelined SD

.

See Appendix 5—

SD Timing.

0

1

0

1

x

HSYNC

As per timing.

Pipelined ED/HD

.

Same as line blanking

interval.

Pipelined ED/HD

AV Code H bit.

based on

x

1

x

HSYNC

Same as embedded

Pipelined ED/HD

HSYNC

.

horizontal counter.

1

HSYNC

pulse is aligned with the falling edge of the embedded in the output video.

In all ED/HD standards where there is an

output, the start of the

1

S_VSYNC

Table 52.

Output Control

ED/HD VSYNC

Control

(0x34, Bit 2)

ED/HD Input

Sync Format

(0x30, Bit 2)

ED/HD Sync

Output Enable

(0x02, Bit 7)

SD Sync

Output Enable

(0x02, Bit 6)

Signal on S_VSYNC Pin

Video Standard

Duration

x

X

0

1

x

Tristate.

–

Interlaced

VSYNC

Pipelined SD

/Field.

See Appendix

5—SD Timing.

0

1

0

1

x

VSYNC

As per or

field signal timing.

Field.

Pipelined ED/HD

or field signal.

All HD interlaced

standards

All ED/HD

progressive

standards

Pipelined field signal

based on AV Code F bit.

VSYNC

Vertical blanking

interval.

Pipelined

based

on AV Code V bit.

x

1

x

All ED/HD

standards

except 525p

VSYNC

based on vertical counter.

Aligned with

serration lines.

Pipelined ED/HD

x

525p

VSYNC

based on vertical counter.

Vertical blanking

interval.

Pipelined ED/HD

1

VSYNC

pulse is aligned with the falling edge of the embedded in the output video.

In all ED/HD standards where there is a

output, the start of the

Rev. 0 | Page 63 of 88

ADV7342/ADV7343

With this feature enabled, the cable detection circuitry monitors

DAC 1 and/or DAC 2 once per frame. If they are unconnected,

some or all of the DACs automatically power down. Which

DAC or DACs are powered down depends on the selected

output configuration.

LOW POWER MODE

Subaddress 0x0D, Bits[2:0]

For power sensitive applications, the ADV7342/ADV7343

support an Analog Devices, Inc. proprietary low power mode of

operation on DAC 1, DAC 2, and DAC 3. To utilize this low

power mode, these DACs must be operating in full-drive mode

(R_SET= 510 Ω, R_L= 37.5 Ω). Low power mode is not available in

low drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω). Low power mode

can be independently enabled or disabled on DAC 1, DAC 2, and

DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is

disabled by default on each DAC.

For CVBS/YC output configurations, if DAC 1 is unconnected,

only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and

DAC 3 power down.

For YPrPb and RGB output configurations, if DAC 1 is

unconnected, all three DACs power down. DAC 2 is not

monitored for YPrPb and RGB output configurations.

In low power mode, DAC current consumption is content

dependent. On a typical video stream, it can be reduced by as

much as 40%. For applications requiring the highest possible video

performance, low power mode should be disabled.

Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable

is detected, the appropriate DAC or DACs remain powered up

for the duration of the frame. If no cable is detected, the appropriate

DAC or DACs power down until the next frame, when the process

is repeated.

CABLE DETECTION

PIXEL AND CONTROL PORT READBACK

Subaddress 0x10

Subaddress 0x12 to Subaddress 0x14, Subaddress 0x16

The ADV7342/ADV7343 include an Analog Devices, Inc.

proprietary cable detection feature.

The ADV7342/ADV7343 support the readback of most digital

inputs via the I²C/SPI MPU port. This feature is useful for

board level connectivity testing with upstream devices.

The cable detection feature is available on DAC 1 and DAC 2,

while operating in full-drive mode (R_SET1= 510 Ω, R_L1= 37.5 Ω,

assuming a connected cable). The feature is not available in low

drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω). For a DAC to be

monitored, the DAC must be powered up in Subaddress 0x00.

The pixel port (S[7:0], Y[7:0], and C[7:0]), the control port

(

,

and

),

S_HSYNC S_VSYNC P_HSYNC P_VSYNC

P_BLANK

and the SFL/MISO pin are available for readback via the MPU

port. The readback registers are located at Subaddress 0x12 to

Subaddress 0x14 and Subaddress 0x16.

The cable detection feature can be used with all SD, ED, and

HD video standards. It is available for all output configurations,

that is, CVBS, YC, YPrPb, and RGB output configurations.

When using this feature, a clock signal should be applied to the

CLKIN_A pin to register the levels applied to the input pins.

For CVBS/YC output configurations, both DAC 1 and DAC 2

are monitored, that is, the CVBS and YC luma outputs are

monitored. For YPrPb and RGB output configurations, only

DAC 1 is monitored, that is, the luma or green output is

monitored.

RESET MECHANISM

Subaddress 0x17, Bit 1

The ADV7342/ADV7343 have a software reset accessible via

the I²C/SPI MPU port. A software reset is activated by writing

a 1 to Subaddress 0x17, Bit 1. This resets all registers to their

default values. This bit is self-clearing, that is, after a 1 has been

written to the bit, the bit automatically returns to 0.

Once per frame, the ADV7342/ADV7343 monitor DAC 1

and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,

respectively. If a cable is detected on one of the DACs, the

relevant bit is set to 0. If not, the bit is set to 1.

When operating in SPI mode, a software reset does not cause

the device to revert to I²C mode. For this to occur, the

ADV7342/ADV7343 need to be powered down.

DAC AUTO POWER-DOWN

Subaddress 0x10, Bit 4

For power sensitive applications, a DAC auto power-down

feature can be enabled using Subaddress 0x10, Bit 4. This feature

is only available when the cable detection feature is enabled.

The ADV7342/ADV7343 include a power-on reset (POR)

circuit to ensure correct operation after power-up.

Rev. 0 | Page 64 of 88

ADV7342/ADV7343

PRINTED CIRCUIT BOARD LAYOUT AND DESIGN

For applications requiring an output buffer and reconstruction

filter, the ADA4430-1, ADA4411-3, and ADA4410-6 integrated

video filter buffers should be considered.

DAC CONFIGURATIONS

The ADV7342/ADV7343 contain six DACs. All six DACs can

be configured to operate in low drive mode. Low drive mode is

defined as 4.33 mA full-scale current into a 300 Ω load, R_L.

Table 53. ADV7342/ADV7343 Output Rates

Input Mode

(0x01, Bits[6:4]) (0x00, Bit 1)

PLL Control

DAC 1, DAC 2, and DAC 3 can also be configured to operate in

full-drive mode. Full-drive mode is defined as 34.7 mA full-

scale current into a 37.5 Ω load, R_L. Full-drive is the recommended

mode of operation for DAC 1, DAC 2, and DAC 3.

Output Rate (MHz)

SD Only

ED Only

HD Only

Off

On

Off

On

Off

On

27

216

27

216

74.25

297

(2x)

(16x)

(1x)

(8x)

(1x)

(4x)

The ADV7342/ADV7343 contain two R_SETpins. A resistor

connected between the R_SET1pin and AGND is used to control

the full-scale output current and, therefore, the DAC output

voltage levels of DAC 1, DAC 2, and DAC 3. For low drive

operation, R_SET1must have a value of 4.12 kΩ, and R_Lmust have a

value of 300 Ω. For full-drive operation, R_SET1must have a value

of 510 Ω, and R_Lmust have a value of 37.5 Ω.

Table 54. Output Filter Requirements

Cutoff

Attenuation

–50 dB @

(MHz)

Frequency

Application Oversampling (MHz)

A resistor connected between the R_SET2pin and AGND is used

to control the full-scale output current and, therefore, the DAC

output voltage levels of DAC 4, DAC 5, and DAC 6. R_SET2must

have a value of 4.12 kΩ, and R_Lmust have a value of 300 Ω (that

is, low drive operation only).

SD

ED

HD

2×

16×

1×

8×

1×

4×

>6.5

>12.5

>30

20.5

209.5

14.5

203.5

44.25

267

The resistors connected to the R_SET1and R_SET2pins should have a

1% tolerance.

>30

The ADV7342/ADV7343 contain two compensation pins,

COMP1 and COMP2. A 2.2 nF compensation capacitor should

be connected from each of these pins to V_AA.

10µH

22pF

DAC

OUTPUT

3

4

75Ω

BNC

OUTPUT

600Ω

1

VOLTAGE REFERENCE

The ADV7342/ADV7343 contain an on-chip voltage reference

that can be used as a board-level voltage reference via the V_REF

pin. Alternatively, the ADV7342/ADV7343 can be used with an

external voltage reference by connecting the reference source to

the V_REFpin. For optimal performance, an external voltage

reference such as the AD1580 should be used with the ADV7342/

ADV7343. If an external voltage reference is not used, a 0.1 μF

capacitor should be connected from the V_REFpin to V_AA.

560Ω

Figure 84. Example of Output Filter for SD, 16× Oversampling

4.7µH

DAC

OUTPUT

3

75Ω

BNC

OUTPUT

6.8pF

600Ω

1

600Ω

4

VIDEO OUTPUT BUFFER AND OPTIONAL

OUTPUT FILTER

560Ω

An output buffer is necessary on any DAC that operates in low

drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω). Analog Devices, Inc.

produces a range of op amps suitable for this application, for

example, the AD8061. For more information about line driver

buffering circuits, see the relevant op amp data sheet.

Figure 85. Example of Output Filter for ED, 8× Oversampling

DAC

OUTPUT

3

390nH

75Ω

BNC

OUTPUT

300Ω

3

1

33pF

75Ω

1

An optional reconstruction (anti-imaging) low-pass filter (LPF)

may be required on the ADV7342/ADV7343 DAC outputs if

the ADV7342/ADV7343 are connected to a device that requires

this filtering.

4

500Ω

The filter specifications vary with the application. The use of

16× (SD), 8× (ED), or 4× (HD) oversampling can remove the

requirement for a reconstruction filter altogether.

Figure 86. Example of Output Filter for HD, 4× Oversampling

Rev. 0 | Page 65 of 88

ADV7342/ADV7343

CIRCUIT FREQUENCY RESPONSE

0

PRINTED CIRCUIT BOARD (PCB) LAYOUT

0

–10

–20

–30

–40

–50

–60

–70

–80

24n

21n

18n

15n

12n

9n

–30

The ADV7342/ADV7343 are highly integrated circuits

containing both precision analog and high speed digital

circuitry. They have been designed to minimize interference

effects on the integrity of the analog circuitry by the high speed

digital circuitry. It is imperative that these same design and

layout techniques be applied to the system-level design so that

optimal performance is achieved.

MAGNITUDE (dB)

PHASE (Degrees)

–60

–90

–120

–150

–180

–210

–240

GROUP DELAY (Seconds)

The layout should be optimized for lowest noise on the

ADV7342/ADV7343 power and ground planes by shielding the

digital inputs and providing good power supply decoupling.

6n

3n

0

It is recommended to use a 4-layer printed circuit board with

ground and power planes separating the signal trace layer and

the solder side layer.

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 87. Output Filter Plot for SD, 16× Oversampling

Component Placement

CIRCUIT FREQUENCY RESPONSE

Component placement should be carefully considered to

separate noisy circuits, such as clock signals and high speed

digital circuitry from analog circuitry.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

480

18n

16n

400

320

240

160

80

MAGNITUDE (dB)

The external loop filter components and components connected

to the COMP, V_REF, and R_SETpins should be placed as close as

possible to and on the same side of the PCB as the ADV7342/

ADV7343. Adding vias to the PCB to get the components closer

to the ADV7342/ADV7343 are not recommended.

14n

PHASE

(Degrees)

12n

10n

8n

GROUP DELAY (Seconds)

0

It is recommended that the ADV7342/ADV7343 be placed as

close as possible to the output connector, with the DAC output

traces as short as possible.

6n

–80

–160

–240

4n

2n

0

The termination resistors on the DAC output traces should be

placed as close as possible to and on the same side of the PCB as

the ADV7342/ADV7343. The termination resistors should

overlay the PCB ground plane.

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 88. Output Filter Plot for ED, 8× Oversampling

External filter and buffer components connected to the DAC

outputs should be placed as close as possible to the ADV7342/

ADV7343 to minimize the possibility of noise pickup from

neighboring circuitry, and to minimize the effect of trace

capacitance on output bandwidth. This is particularly important

when operating in low drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω).

CIRCUIT FREQUENCY RESPONSE

0

200

120

40

PHASE

(Degrees)

MAGNITUDE (dB)

–10

–20

–30

–40

–50

GROUP DELAY (Seconds)

Power Supplies

It is recommended that a separate regulated supply be provided

for each power domain (V_AA, V_DD, V_{DD_IO}, and PV_DD). For

optimal performance, linear regulators rather than switch mode

regulators should be used. If switch mode regulators must be

used, care must be taken with regard to the quality of the output

voltage in terms of ripple and noise. This is particularly true for

the V_AAand PV_DDpower domains. Each power supply should be

individually connected to the system power supply at a single

point through a suitable filtering device, such as a ferrite bead.

–40

–120

–200

1

10

100

FREQUENCY (MHz)

Figure 89. Output Filter Plot for HD, 4× Oversampling

Rev. 0 | Page 66 of 88

ADV7342/ADV7343

Power Supply Decoupling

Due to the high clock rates used, avoid long clock traces to the

ADV7342/ADV7343 to minimize noise pickup.

It is recommended that each power supply pin be decoupled

with 10 nF and 0.1 μF ceramic capacitors. The V_AA, PV_DD,

Any pull-up termination resistors for the digital inputs should

be connected to the V_DDpower supply.

V_{DD_IO}, and both V_DDpins should be individually decoupled to

ground. The decoupling capacitors should be placed as close as

possible to the ADV7342/ADV7343 with the capacitor leads

kept as short as possible to minimize lead inductance.

Any unused digital inputs should be tied to ground.

Analog Signal Interconnect

DAC output traces should be treated as transmission lines with

appropriate measures taken to ensure optimal performance (for

example, impedance matched traces). The DAC output traces

should be kept as short as possible. The termination resistors on

the DAC output traces should be placed as close as possible to

and on the same side of the PCB as the ADV7342/ADV7343.

A 1 μF tantalum capacitor is recommended across the V_AA

supply in addition to the 10 nF and 0.1 μF ceramic capacitors.

Power Supply Sequencing

The ADV7342/ADV7343 are robust to all power supply

sequencing combinations. Any particular sequence can be used.

Digital Signal Interconnect

To avoid crosstalk between the DAC outputs, it is recom-

mended that as much space as possible be left between the

traces connected to the DAC output pins. Adding ground traces

between the DAC output traces is also recommended.

The digital signal traces should be isolated as much as possible

from the analog outputs and other analog circuitry. Digital

signal traces should not overlay the V_AAor PV_DDpower planes.

Rev. 0 | Page 67 of 88

ADV7342/ADV7343

TYPICAL APPLICATION CIRCUIT

FERRITE BEAD

V

DD_IO

NOTES

V

POWER

1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED

DD_IO

33µF

10µF

0.1µF

0.01µF

SUPPLY

DECOUPLING

TO THE COMP, R , V

AND DAC OUTPUT PINS SHOULD BE LOCATED

CLOSE TO AND ON THE SAME SIDE OF THE PCB AS THE ADV7342/ADV7343.

SET REF

GND_IO

FERRITE BEAD

2

2. WHEN OPERATING IN I C MODE, THE I C DEVICE ADDRESS IS

CONFIGURABLE USING THE ALSB/SPI_SS PIN:

PV

DD

(1.8V)

PV POWER

DD

SUPPLY

DECOUPLING

33µF

10µF

0.1µF

0.01µF

PGND

2

ALSB/SPI_SS = 0, I C DEVICE ADDRESS = 0xD4 OR 0x54

ALSB/SPI_SS = 1, I C DEVICE ADDRESS = 0xD6 OR 0x56

PGND

2

FERRITE BEAD

V

AA

3. THE RESISTORS CONNECTED TO THE R

SET

PINS SHOULD HAVE A 1%

V

POWER

AA

0.01µF

AGND

1µF

33µF

10µF

0.1µF

TOLERANCE.

SUPPLY

DECOUPLING

AGND

FERRITE BEAD

V

DD

(1.8V)

V

POWER SUPPLY

DD

33µF

10µF

0.1µF

0.01µF

DGND

DECOUPLING FOR

EACH POWER PIN

DGND

V

AA

OPTIONAL. IF THE INTERNAL VOLTAGE

REFERENCE IS USED, A 0.1µF CAPACITOR

2.2nF

SHOULD BE CONNECTED FROM V

TO V .

REF

AA

V

COMP1

COMP2

AA

1.1kΩ

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

1.235V

V

REF

0.1µF

AD1580

R

SET1

SET2

ADV7342/ADV7343

AGND

510Ω

4.12kΩ

S0

S1

S2

S3

S4

S5

S6

S7

AGND

OPTIONAL LPF

DAC 1

DAC 2

DAC 3

DAC 1

DAC 2

DAC 3

DACs 1-3 FULL DRIVE OPTION

PIXEL PORT INPUTS

OPTIONAL LPF

75Ω

AGND

75Ω

C0

C1

C2

C3

C4

C5

C6

C7

DACs 1-3 LOW DRIVE OPTION

AGND

OPTIONAL LPF

AD8061

DAC 4

DAC 5

DAC 6

+

75Ω

R

SET1

+V

–V

DAC 4

4.12kΩ

–

AGND

300Ω

510Ω

TEST0

TEST1

TEST2

TEST3

TEST4

TEST5

OPTIONAL LPF

AGND

AD8061

UNUSED

CONNECT TO DGND

+

–

DAC 1

DAC 2

DAC 3

75Ω

510Ω

+V

–V

DAC 1

AGND

300Ω

OPTIONAL LPF

510Ω

S_HSYNC

S_VSYNC

AGND

AD8061

+

CONTROL

INPUTS/OUTPUTS

+V

–V

510Ω

DAC 5

P_HSYNC

P_VSYNC

P_BLANK

–

300Ω

AGND

OPTIONAL LPF

510Ω

CLKIN_A

CLKIN_B

AGND

CLOCK INPUTS

AD8061

+

–

75Ω

+V

–V

510Ω

SDA/SCLK

SCL/MOSI

SFL/MISO

DAC 2

MPU PORT

INPUTS/OUTPUTS

AGND

300Ω

ALSB/SPI_SS

OPTIONAL LPF

510Ω

EXTERNAL LOOP FILTERS

AGND

AD8061

+

PV

DD

+V

–V

12nF

150nF

12nF

150nF

510Ω

AGND

DAC 6

EXT_LF1

EXT_LF2

–

300Ω

170Ω

510Ω

OPTIONAL LPF

AGND

AD8061

+

–

AGND PGND DGND DGND GND_IO

75Ω

+V

–V

510Ω

DAC 3

170Ω

AGND

LOOP FILTER COMPONENTS

SHOULD BE LOCATED

CLOSE TO THE EXT_LF

PINS AND ON THE SAME

SIDE OF THE PCB AS THE

ADV7342/ADV7343.

300Ω

AGND PGND DGND DGND GND_IO

510Ω

AGND

510Ω

AGND

Figure 90. ADV7342/ADV7343 Typical Application Circuit

Rev. 0 | Page 68 of 88

ADV7342/ADV7343

APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM

When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p

CGMS data is applied to Line 24 of the luminance vertical

blanking interval.

SD CGMS

Subaddress 0x99 to Subaddress 0x9B

The ADV7342/ADV7343 support copy generation management

system (CGMS) conforming to the EIAJ CPR-1204 and ARIB

TR-B15 standards. CGMS data is transmitted on Line 20 of the

odd fields and Line 283 of even fields. Subaddress 0x99,

Bits[6:5] control whether CGMS data is output on odd or even

fields or both.

When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i

CGMS data is applied to Line 19 and Line 582 of the luminance

vertical blanking interval.

The HD CGMS data registers are at Subaddress 0x41,

Subaddress 0x42, and Subaddress 0x43.

SD CGMS data can only be transmitted when the ADV7342/

ADV7343 are configured in NTSC mode. The CGMS data is 20

bits long. The CGMS data is preceded by a reference pulse of

the same amplitude and duration as a CGMS bit (see Figure 91).

The ADV7342/ADV7343 also support CGMS Type B packets in

HD mode (720p and 1080i) in accordance with CEA-805-A.

When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 =

1), 720p CGMS data is applied to Line 23 of the luminance

vertical blanking interval.

ED CGMS

Subaddress 0x41 to Subaddress 0x43

Subaddress 0x5E to Subaddress 0x6E

When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 =

1), 1080i CGMS data is applied to Line 18 and Line 581 of the

luminance vertical blanking interval.

525p

The HD CGMS Type B data registers are at Subaddress 0x5E to

Subaddress 0x6E.

The ADV7342/ADV7343 support copy generation management

system (CGMS) in 525p mode in accordance with EIAJ CPR-

1204-1.

CGMS CRC FUNCTIONALITY

When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p

CGMS data is inserted on Line 41. The 525p CGMS data

registers are at Subaddress 0x41, Subaddress 0x42, and

Subaddress 0x43.

If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS

CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS

data bits, C19 to C14, which comprise the 6-bit CRC check

sequence, are automatically calculated on the ADV7342/ADV7343.

This calculation is based on the lower 14 bits (C13 to C0) of the

data in the CGMS data registers and the result is output with

the remaining 14 bits to form the complete 20 bits of the CGMS

data. The calculation of the CRC sequence is based on the

polynomial x⁶+ x + 1 with a preset value of 111111.

The ADV7342/ADV7343 also support CGMS Type B packets in

525p mode in accordance with CEA-805-A.

When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),

525p CGMS Type B data is inserted on Line 40. The 525p CGMS

Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.

If SD CGMS CRC or ED/HD CGMS CRC are disabled, all

20 bits (C19 to C0) are output directly from the CGMS registers

(CRC must be calculated by the user manually).

625p

The ADV7342/ADV7343 support copy generation management

system (CGMS) in 625p mode in accordance with IEC62375

(2004).

If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is

enabled, the upper six CGMS Type B data bits (P122 to P127)

that comprise the 6-bit CRC check sequence are automatically

calculated on the ADV7342/ADV7343. This calculation is

based on the lower 128 bits (H0 to H5 and P0 to P121) of the

data in the CGMS Type B data registers. The result is output

with the remaining 128 bits to form the complete 134 bits of the

CGMS Type B data. The calculation of the CRC sequence is

based on the polynomial x⁶+ x + 1 with a preset value of

111111.

When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p

CGMS data is inserted on Line 43. The 625p CGMS data

registers are at Subaddress 0x42 and Subaddress 0x43.

HD CGMS

Subaddress 0x41 to Subaddress 0x43

Subaddress 0x5E to Subaddress 0x6E

The ADV7342/ADV7343 support copy generation management

system (CGMS) in HD mode (720p and 1080i) in accordance

with EIAJ CPR-1204-2.

If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5

and P0 to P127) are output directly from the CGMS Type B

registers (CRC must be calculated by the user manually).

Rev. 0 | Page 69 of 88

ADV7342/ADV7343

+100 IRE

CRC SEQUENCE

REF

+70 IRE

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0 IRE

–40 IRE

49.1µs ± 0.5µs

11.2µs

2.235µs ± 20ns

Figure 91. Standard Definition CGMS Waveform

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2

BIT 20

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

–300mV

21.2µs ± 0.22µs

22T

5.8µs ± 0.15µs

6T

T = 1/(f_H× 33) = 963ns

f_H= HORIZONTAL SCAN FREQUENCY

T ± 30ns

Figure 92. Enhanced Definition (525p) CGMS Waveform

R = RUN-IN

PEAK WHITE

500mV ± 25mV

S = START CODE

C0

C13

C9 C10 C11 C12

R

S

C1

C2

C3

C4

C5

C6

C7

C8

LSB

MSB

SYNC LEVEL

13.7µs

5.5µs ± 0.125µs

Figure 93. Enhanced Definition (625p) CGMS Waveform

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2

BIT 20

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

T ± 30ns

–300mV

17.2µs ± 160ns

4T

22T

3.128µs ± 90ns

T = 1/(f_H× 1650/58) = 781.93ns

f_H= HORIZONTAL SCAN FREQUENCY

1H

Figure 94. High Definition (720p) CGMS Waveform

Rev. 0 | Page 70 of 88

ADV7342/ADV7343

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2

BIT 20

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

T ± 30ns

–300mV

22.84µs ± 210ns

22T

4T

4.15µs ± 60ns

T = 1/(f × 2200/77) = 1.038µs

H

f

= HORIZONTAL SCAN FREQUENCY

H

1H

Figure 95. High Definition (1080i) CGMS Waveform

CRC SEQUENCE

+700mV

START

BIT 1 BIT 2

BIT 134

70% ± 10%

H0

H1

H2

H3

H4

H5 P0

P1

P2

P3

P4

.

P122 P123 P124 P125 P126 P127

0mV

–300mV

NOTES

1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.

Figure 96. Enhanced Definition (525p) CGMS Type B Waveform

CRC SEQUENCE

BIT 134

+700mV

START

BIT 1 BIT 2

70% ± 10%

H0

H1

H2

H3

H4

H5 P0

P1

P2

P3

P4

.

P122 P123 P124 P125 P126 P127

0mV

–300mV

NOTES

1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.

Figure 97. High Definition (720p and 1080i) CGMS Type B Waveform

Rev. 0 | Page 71 of 88

ADV7342/ADV7343

APPENDIX 2—SD WIDE SCREEN SIGNALING

(see Figure 98). The latter portion of Line 23 (after 42.5 μs from

HSYNC

video. WSS data transmission on Line 23 can be enabled using

Subaddress 0x99, Bit 7. It is possible to blank the WSS portion

of Line 23 with Subaddress 0xA1, Bit 7.

Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B

the falling edge of

) is available for the insertion of

The ADV7342/ADV7343 support wide screen signaling (WSS)

conforming to the ETSI 300 294 standard. WSS data is

transmitted on Line 23. WSS data can be transmitted only when

the device is configured in PAL mode. The WSS data is 14 bits

long. The function of each of these bits is shown in Table 55.

The WSS data is preceded by a run-in sequence and a start code

Table 55. Function of WSS

Bit Number

Bit Description

13 12 11 10

9

8

7

6

5

4

3

1

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Setting

Aspect Ratio, Format, Position

4:3, full format, N/A

14:9, letterbox, center

14:9, letterbox, top

16:9, letterbox, center

16:9, letterbox, top

>16:9, letterbox, center

14:9, full format, center

16:0, N/A, N/A

Mode

0

1

Camera mode

Film mode

Color Encoding

Helper Signals

0

1

Normal PAL

Motion Adaptive ColorPlus

Not present

0

1

Present

Reserved

0

Teletext Subtitles

0

1

No

Yes

Open Subtitles

0

1

0

1

0

1

No

Subtitles in active image area

Subtitles out of active image area

Reserved

Surround Sound

Copyright

0

1

No

Yes

0

1

No copyright asserted or unknown

Copyright asserted

Copying not restricted

Copying restricted

Copy Protection

0

1

500mV

RUN-IN

SEQUENCE

START

CODE

ACTIVE

VIDEO

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

11.0µs

38.4µs

42.5µs

Figure 98. WSS Waveform Diagram

Rev. 0 | Page 72 of 88

ADV7342/ADV7343

APPENDIX 3—SD CLOSED CAPTIONING

and Line 284. All pixels inputs are ignored on Line 21 and Line

284 if closed captioning is enabled.

Subaddress 0x91 to Subaddress 0x94

The ADV7342/ADV7343 support closed captioning conforming

to the standard television synchronizing waveform for color

transmission. Closed captioning is transmitted during the

blanked active line time of Line 21 of the odd fields and

Line 284 of the even fields.

The FCC Code of Federal Regulations (CFR) 47 Section 15.119

and EIA608 describe the closed captioning information for

Line 21 and Line 284.

The ADV7342/ADV7343 use a single buffering method. This

means that the closed captioning buffer is only 1-byte deep.

Therefore, there is no frame delay in outputting the closed

captioning data, unlike other 2-byte deep buffering systems.

The data must be loaded one line before it is output on Line 21

and Line 284. A typical implementation of this method is to use

Closed captioning consists of a 7-cycle sinusoidal burst that is

frequency- and phase-locked to the caption data. After the clock

run-in signal, the blanking level is held for two data bits and is

followed by the Logic 1 start bit. Sixteen bits of data follow the

start bit. These consist of two 8-bit bytes, seven data bits, and one

odd parity bit. The data for these bytes is stored in the SD closed

captioning registers (Subaddress 0x93 to Subaddress 0x94).

VSYNC

to interrupt a microprocessor, which in turn loads the

new data (2 bytes) in every field. If no new data is required for

transmission, 0s must be inserted in both data registers; this is

called nulling. It is also important to load control codes, all of

which are double bytes, on Line 21. Otherwise, a TV does not

recognize them. If there is a message such as “Hello World”

that has an odd number of characters, it is important to add a

blank character at the end to make sure that the end-of-caption,

2-byte control code lands in the same field.

The ADV7342/ADV7343 also support the extended closed

captioning operation, which is active during even fields and

encoded on Scan Line 284. The data for this operation is stored

in the SD closed captioning registers (Subaddress 0x91 to

Subaddress 0x92).

The ADV7342/ADV7343 automatically generate all clock run-

in signals and timing that support closed captioning on Line 21

10.5 ± 0.25µs

12.91µs

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

P

A

R

I

T

Y

P

A

R

I

T

Y

S

T

A

R

T

D0 TO D6

BYTE 1

50 IRE

40 IRE

BYTE 0

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003µs

27.382µs

33.764µs

Figure 99. SD Closed Captioning Waveform, NTSC

Rev. 0 | Page 73 of 88

ADV7342/ADV7343

APPENDIX 4—INTERNAL TEST PATTERN GENERATION

Note that when programming the F_SCregisters, the user must

SD TEST PATTERNS

write the values in the sequence F_SC0, F_SC1, F_SC2, F_SC3. The full

F_SCvalue to be written is accepted only after the F_SC3 write is

complete.

The ADV7342/ADV7343 are able to generate SD color bar and

black bar test patterns.

The register settings in Table 56 are used to generate an SD

NTSC 75% color bar test pattern. CVBS output is available on

DAC 4, S-Video (Y/C) output is on DAC 5 and DAC 6, and

YPrPb output is on DAC 1 to DAC 3. Upon power-up, the

subcarrier frequency registers default to the appropriate values

for NTSC. All other registers are set as normal/default.

ED/HD TEST PATTERNS

The ADV7342/ADV7343 are able to generate ED/HD color bar,

black bar, and hatch test patterns.

The register settings in Table 58 are used to generate an ED

525p hatch test pattern. YPrPb output is available on DAC 1 to

DAC 3. All other registers are set as normal/default.

Table 56. SD NTSC Color Bar Test Pattern Register Writes

Subaddress

Setting

Table 58. ED 525p Hatch Test Pattern Register Writes

0x00

0xFC

Subaddress

Setting

0x82

0xC9

0x00

0x1C

0x84

0x40

0x01

0x10

0x31

0x05

To generate an SD NTSC black bar test pattern, the same

settings shown in Table 56 should be used with an additional

write of 0x24 to Subaddress 0x02.

To generate an ED 525p black bar test pattern, the same settings

as shown in Table 58 should be used with an additional write of

0x24 to Subaddress 0x02.

For PAL output of either test pattern, the same settings are used,

except that Subaddress 0x80 is programmed to 0x11 and the

subcarrier frequency registers are programmed as shown in

Table 57.

To generate an ED 525p flat field test pattern, the same settings

shown in Table 58 should be used, except that 0x0D should be

written to Subaddress 0x31.

The Y, Cr, and Cb levels for the hatch and flat field test patterns

can be controlled using Subaddress 0x36, Subaddress 0x37, and

Subaddress 0x38, respectively.

Table 57. PAL F_SCRegister Writes

Subaddress

Description

Setting

0xCB

0x8C

F_SC0

For ED/HD standards other than 525p, the same settings as

shown in Table 58 (and subsequent comments) are used except

that Subaddress 0x30, Bits[7:3] are updated as appropriate.

0x8D

F_SC1

0x8A

0x09

0x8E

F_SC2

0x8F

F_SC3

0x2A

Rev. 0 | Page 74 of 88

ADV7342/ADV7343

APPENDIX 5—SD TIMING

Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)

The ADV7342/ADV7343 are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the

pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately

S_VSYNC

S_HSYNC

before and after each line during active picture and retrace. If the

during this mode.

and

pins are not used, they should be tied high

ANALOG

VIDEO

EAV CODE

SAV CODE

C

b

C

r

C

b

8

0

F

A

B

A

B

A

B

8

0

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

1440 CLOCK

268 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

280 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 100. SD Slave Mode 0

Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)

The ADV7342/ADV7343 generate H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is

S_HSYNC

S_VSYNC

output on

and the F bit is output on

.

DISPLAY

VERTICAL BLANK

4

522

523

524

525

1

2

3

5

6

7

8

10

11

20

21

22

9

H

F

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

H

F

ODD FIELD

EVEN FIELD

Figure 101. SD Master Mode 0, NTSC

Rev. 0 | Page 75 of 88

ADV7342/ADV7343

DISPLAY

VERTICAL BLANK

622

623

624

625

4

22

23

1

2

3

5

6

7

21

H

F

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

335

336

318

334

309

310

311

312

313

314

315

316

317

319

320

H

F

ODD FIELD

EVEN FIELD

Figure 102. SD Master Mode 0, PAL

ANALOG

VIDEO

H

F

Figure 103. SD Master Mode 0, Data Transitions

Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)

In this mode, the ADV7342/ADV7343 accept horizontal sync and odd/even field signals. When

HSYNC

is low, a transition of the field

input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-

HSYNC

S_HSYNC

S_VSYNC

and pins, respectively.

624.

and FIELD are input on the

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

3

2

4

5

7

9

10

11

1

6

8

HSYNC

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

FIELD

ODD FIELD EVEN FIELD

Figure 104. SD Slave Mode 1, NTSC

Rev. 0 | Page 76 of 88

ADV7342/ADV7343

DISPLAY

VERTICAL BLANK

3

4

5

7

622

623

624

625

1

2

6

21

22

23

HSYNC

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

FIELD

ODD FIELD

EVEN FIELD

Figure 105. SD Slave Mode 1, PAL

Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)

In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When

field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per

HSYNC

is low, a transition of the

HSYNC

CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions.

and FIELD are output on the

S_HSYNC

S_VSYNC

and

pins, respectively.

HSYNC

FIELD

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 106. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)

Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)

In this mode, the ADV7342/ADV7343 accept horizontal and vertical sync signals. A coincident low transition of both

HSYNC

VSYNC

and

VSYNC

HSYNC

is high indicates the start of an even field. The

inputs indicates the start of an odd field. A

low transition when

HSYNC

VSYNC

S_HSYNC

are input on the and

ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-624.

S_VSYNC

and

pins, respectively.

Rev. 0 | Page 77 of 88

ADV7342/ADV7343

DISPLAY

VERTICAL BLANK

522

523

524

525

1

3

4

5

7

8

20

21

22

2

6

10

11

9

HSYNC

VSYNC

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

Figure 107. SD Slave Mode 2, NTSC

DISPLAY

VERTICAL BLANK

4

622

623

624

625

1

2

3

5

6

7

21

22

23

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

Figure 108. SD Slave Mode 2, PAL

Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)

In this mode, the ADV7342/ADV7343 can generate horizontal and vertical sync signals. A coincident low transition of both

VSYNC

HSYNC

and

inputs indicates the start of an odd field.

VSYNC

HSYNC

is high indicates the start of an even field. The ADV7342/ADV7343 automatically blank all

A

low transition when

HSYNC

VSYNC

S_HSYNC

S_VSYNC

pins, respectively.

normally blank lines as per CCIR-624.

and

are output on the

and

HSYNC

VSYNC

PIXEL

DATA

Cb

Cr

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 109. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)

Rev. 0 | Page 78 of 88

ADV7342/ADV7343

HSYNC

VSYNC

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

PIXEL

DATA

Cb

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 110. SD Timing Mode 2 Odd-to-Even Field Transition (Master/Slave)

Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)

HSYNC

In this mode, the ADV7342/ADV7343 accept or generate horizontal sync and odd/even field signals. When

is high, a transition

of the field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as

HSYNC

VSYNC

S_VSYNC

and pins,

per CCIR-624.

respectively.

and

are output in master mode and input in slave mode on the

DISPLAY

VERTICAL BLANK

522

523

524

525

4

20

21

22

10

11

1

2

3

5

6

7

8

9

HSYNC

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

FIELD

ODD FIELD EVEN FIELD

Figure 111. SD Timing Mode 3, NTSC

DISPLAY

VERTICAL BLANK

622

623

624

625

5

7

21

22

23

1

2

3

4

6

HSYNC

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

FIELD

EVEN FIELD ODD FIELD

Figure 112. SD Timing Mode 3, PAL

Rev. 0 | Page 79 of 88

ADV7342/ADV7343

APPENDIX 6—HD TIMING

DISPLAY

FIELD 1

VERTICAL BLANKING INTERVAL

1124

1125

1

2

3

4

5

6

7

8

20

21

22

560

P_VSYNC

P_HSYNC

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

P_VSYNC

P_HSYNC

HSYNC

VSYNC

Input Timing

Figure 113. 1080i

and

Rev. 0 | Page 80 of 88

ADV7342/ADV7343

APPENDIX 7—VIDEO OUTPUT LEVELS

SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10

Pattern: 100% Color Bars

700mV

300mV

Figure 117. Y Levels—PAL

Figure 114. Y Levels—NTSC

700mV

Figure 118. Pr Levels—PAL

Figure 115. Pr Levels—NTSC

700mV

Figure 119. Pb Levels—PAL

Figure 116. Pb Levels—NTSC

Rev. 0 | Page 81 of 88

ADV7342/ADV7343

ED/HD YPrPb OUTPUT LEVELS

EIA-770.3, STANDARD FOR Y

EIA-770.2, STANDARD FOR Y

INPUT CODE

940

OUTPUT VOLTAGE

940

700mV

64

300mV

EIA-770.3, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

EIA-770.2, STANDARD FOR Pr/Pb

960

OUTPUT VOLTAGE

960

512

64

600mV

700mV

512

64

Figure 122. EIA-770.3 Standard Output Signals (1080i/720p)

Figure 120. EIA-770.2 Standard Output Signals (525p/625p)

Y–OUTPUT LEVELS FOR

FULL INPUT SELECTION

INPUT CODE

1023

OUTPUT VOLTAGE

EIA-770.1, STANDARD FOR Y

INPUT CODE

OUTPUT VOLTAGE

782mV

940

700mV

714mV

64

300mV

64

286mV

Pr/Pb–OUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

INPUT CODE

1023

EIA-770.1, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

960

700mV

512

64

300mV

Figure 123. Output Levels for Full Input Selection

Figure 121. EIA-770.1 Standard Output Signals (525p/625p)

Rev. 0 | Page 82 of 88

ADV7342/ADV7343

SD/ED/HD RGB OUTPUT LEVELS

Pattern: 100%/75% Color Bars

R

700mV/525mV

300mV

G

700mV/525mV

300mV

B

700mV/525mV

300mV

Figure 126. HD RGB Output Levels—RGB Sync Disabled

Figure 124. SD/ED RGB Output Levels—RGB Sync Disabled

R

700mV/525mV

600mV

300mV

700mV/525mV

300mV

0mV

G

700mV/525mV

600mV

700mV/525mV

300mV

0mV

300mV

0mV

B

700mV/525mV

600mV

700mV/525mV

300mV

0mV

300mV

0mV

Figure 127. HD RGB Output Levels—RGB Sync Enabled

Figure 125. SD/ED RGB Output Levels—RGB Sync Enabled

Rev. 0 | Page 83 of 88

ADV7342/ADV7343

SD OUTPUT PLOTS

VOLTS

0.6

VOLTS IRE:FLT

100

0.4

0.2

0

0.5

50

0

–0.2

0

F1

–50

L608

10

L76

20

30

40

50

60

0

10

20

30

MICROSECONDS

PRECISION MODE OFF

40

50

60

MICROSECONDS

NOISE REDUCTION: 0.00dB

APL = 39.1%

625 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

APL = 44.5%

525 LINE NTSC

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1, 2, 3, 4

SYNCHRONOUS SYNC = A

FRAMES SELECTED 1, 2

SLOW CLAMP TO 0.00V AT 6.72µμs

Figure 128. NTSC Color Bars (75%)

Figure 131. PAL Color Bars (75%)

VOLTS

0.5

VOLTS IRE:FLT

0.6

0.4

50

0.2

0

00

0

–0.2

F2

L238

L575

20

0

10

20

30

40

50

60

0

10

30

40

50

60

70

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL = 44.3%

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NO BUNCH SIGNAL

PRECISION MODE OFF

525 LINE NTSC NO FILTERING

SYNCHRONOUS SYNC = SOURCE

FRAMES SELECTED 1, 2

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

SLOW CLAMP TO 0.00V AT 6.72µμs

Figure 129. NTSC Luma

Figure 132. PAL Luma

VOLTS IRE:FLT

VOLTS

0.5

0.4

50

0.2

0

–0.2

–0.4

–50

–0.5

F1

L76

L575

20

0

10

20

30

40

50

60

0

10

30

40

50

60

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC SOURCE.

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

SYNCHRONOUS SYNC = B

FRAMES SELECTED 1, 2

Figure 130. NTSC Chroma

Figure 133. PAL Chroma

Rev. 0 | Page 84 of 88

ADV7342/ADV7343

APPENDIX 8—VIDEO STANDARDS

0

DATUM

H

SMPTE 274M

ANALOG WAVEFORM

DIGITAL HORIZONTAL BLANKING

272T

*1

4T

1920T

DIGITAL

ACTIVE LINE

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

EAV CODE

SAV CODE

F

0

F

0

C

r

C

INPUT PIXELS

Y

V

Y

b

r

H*

4 CLOCK

192

0

2199

SAMPLE NUMBER

2112

2116 2156

44

188

2111

FVH* = FVH AND PARITY BITS

SAV/EAV: LINE 1–562: F = 0

SAV/EAV: LINE 563–1125: F = 1

SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1

SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FRAME RATE OF 30Hz: 40 SAMPLES

FOR A FRAME RATE OF 25Hz: 480 SAMPLES

Figure 134. EAV/SAV Input Data Timing Diagram (SMPTE 274M)

SMPTE 293M

ANALOG WAVEFORM

ANCILLARY DATA

(OPTIONAL)

DIGITAL

SAV CODE

F

EAV CODE

F

ACTIVE LINE

F

0

F

0

C

b

C

r

C

r

INPUT PIXELS

V

Y

V

Y

H*

4 CLOCK

853 857

SAMPLE NUMBER

719

723 736

DATUM

799

0

719

0

H

DIGITAL HORIZONTAL BLANKING

FVH* = FVH AND PARITY BITS

SAV: LINE 43–525 = 200H

SAV: LINE 1–42 = 2AC

EAV: LINE 43–525 = 274H

EAV: LINE 1–42 = 2D8

Figure 135. EAV/SAV Input Data Timing Diagram (SMPTE293M)

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

522 523 524 525

1

2

5

6

7

8

9

12

13

14

15

16

42

43

44

Figure 136. SMPTE 293M (525p)

Rev. 0 | Page 85 of 88

ADV7342/ADV7343

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

12

13

1

2

5

6

7

8

9

43

44

45

622 623

624

625

4

10

11

Figure 137. ITU-R BT.1358 (625p)

DISPLAY

VERTICAL BLANKING INTERVAL

7

1

2

3

4

5

6

747

748

749

750

26

27

744

745

8

25

Figure 138. SMPTE 296M (720p)

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 1

560

1

2

5

6

7

8

21

22

1124

1125

3

4

20

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

Figure 139. SMPTE 274M (1080i)

Rev. 0 | Page 86 of 88

ADV7342/ADV7343

OUTLINE DIMENSIONS

12.20

12.00 SQ

11.80

0.75

0.60

0.45

1.60

MAX

64

49

1

48

PIN 1

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.08

COPLANARITY

16

33

0.15

0.05

SEATING

17

32

PLANE

VIEW A

0.27

0.22

0.17

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 140. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Macrovision¹

Model

Temperature Range

−40°C to +85°C

Antitaping

Package Description

Package Option

ST-64-2

ADV7342BSTZ²

ADV7343BSTZ²

EVAL-ADV7342EBZ²

EVAL-ADV7343EBZ²

Yes

No

Yes

No

64-Lead Low Profile Quad Flat Package [LQFP]

ADV7342 Evaluation Platform

ADV7343 Evaluation Platform

¹Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video.

²Z = Pb-free part.

Rev. 0 | Page 87 of 88

ADV7342/ADV7343

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D06399-0-10/06(0)

Rev. 0 | Page 88 of 88


型号：	ADV7342BSTZ
厂家：	ADI
描述：	Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs 多格式视频编码器六， 11位， 297 MHz的DAC的编码器
文件：	总88页 (文件大小：1069K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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