ADV7343_15 [ADI]
Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs;
| 型号： | ADV7343_15 |
| 厂家： | 
ADI |
| 描述： | Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| 文件： | 总108页 (文件大小：2628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multiformat Video Encoder
Six, 11-Bit, 297 MHz DACs
ADV7342/ADV7343
Data Sheet
Dual data rate (DDR) input support
Enhanced definition(ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7342 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
FEATURES
74.25 MHz 16-/24-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
Six 11-bit, 297 MHz video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD), 4:4:4 YCrCb (ED and HD), and
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
EIA/CEA-861B compliance support
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Fully programmable YCrCb to RGB matrix
Gamma correction
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7342 only)
Copy generation management system (CGMS)
Wide screen signaling
Closed captioning
Serial MPU interface with I2C compatibility
3.3 V analog operation, 1.8 V digital operation, and 1.8 V or
3.3 V I/O operation
Temperature range: −40°C to +85°C
APPLICATIONS
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Undershoot limiter
DVD recorders and players
High definition Blu-ray DVD players
Rev.D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
ADV7342/ADV7343
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SD Subcarrier Frequency Lock................................................. 53
SD VCR FF/RW Sync ................................................................ 54
Vertical Blanking Interval ......................................................... 54
SD Subcarrier Frequency Control............................................ 54
SD Noninterlaced Mode............................................................ 54
SD Square Pixel Mode ............................................................... 55
Filters............................................................................................ 56
ED/HD Test Pattern Color Controls ....................................... 57
Color Space Conversion Matrix ............................................... 57
SD Luma and Color Scale Control........................................... 59
SD Hue Adjust Control.............................................................. 59
SD Brightness Detect ................................................................. 59
SD Brightness Control............................................................... 59
SD Input Standard Autodetection............................................ 60
Double Buffering........................................................................ 61
Programmable DAC Gain Control.......................................... 61
Gamma Correction.................................................................... 61
ED/HD Sharpness Filter and Adaptive Filter Controls......... 63
Applications....................................................................................... 1
Revision History ............................................................................... 4
General Description......................................................................... 5
Functional Block Diagram .............................................................. 6
Specifications..................................................................................... 7
Power Supply and Voltage Specifications.................................. 7
Voltage Reference Specifications................................................ 7
Input Clock Specifications .......................................................... 7
Analog Output Specifications..................................................... 8
Digital Input/Output Specifications—3.3 V ............................. 8
Digital Input/Output Specifications—1.8 V ............................. 8
Digital Timing Specifications—3.3 V........................................ 9
Digital Timing Specifications—1.8 V...................................... 10
MPU Port Timing Specifications ............................................. 11
Power Specifications .................................................................. 11
Video Performance Specifications ........................................... 12
Timing Diagrams............................................................................ 13
Absolute Maximum Ratings.......................................................... 20
Thermal Resistance .................................................................... 20
ESD Caution................................................................................ 20
Pin Configuration and Function Descriptions........................... 21
Typical Performance Characteristics ........................................... 23
MPU Port Description................................................................... 28
I2C Operation.............................................................................. 28
Register Map Access....................................................................... 30
Register Programming............................................................... 30
Subaddress Register (SR7 to SR0) ............................................ 30
Input Configuration ....................................................................... 48
Standard Definition Only.......................................................... 48
Enhanced Definition/High Definition Only .......................... 49
ED/HD Sharpness Filter and Adaptive Filter Application
Examples...................................................................................... 64
SD Digital Noise Reduction...................................................... 65
SD Active Video Edge Control................................................. 66
External Horizontal and Vertical Synchronization Control. 68
Low Power Mode........................................................................ 69
Cable Detection .......................................................................... 69
DAC Autopower-Down............................................................. 69
Sleep Mode .................................................................................. 70
Pixel and Control Port Readback............................................. 70
Reset Mechanism........................................................................ 70
SD Teletext Insertion ................................................................. 70
Printed Circuit Board Layout and Design .................................. 72
Unused Pins ................................................................................ 72
DAC Configurations.................................................................. 72
Voltage Reference ....................................................................... 72
Video Output Buffer and Optional Output Filter.................. 72
Printed Circuit Board (PCB) Layout ....................................... 73
Typical Application Circuit....................................................... 75
Copy Generation Management System....................................... 76
SD CGMS .................................................................................... 76
ED CGMS.................................................................................... 76
Simultaneous Standard Definition and Enhanced
Definition/High Definition....................................................... 49
Enhanced Definition Only (at 54 MHz) ................................. 50
Output Configuration.................................................................... 51
Design Features............................................................................... 52
Output Oversampling................................................................ 52
P_HSYNC
P_VSYNC
and
HD Interlace External
Considerations............................................................................ 53
ED/HD Timing Reset ................................................................ 53
Rev.D | Page 2 of 108
Data Sheet
ADV7342/ADV7343
HD CGMS....................................................................................76
CGMS CRC Functionality .........................................................76
SD Wide Screen Signaling..............................................................79
SD Closed Captioning ....................................................................80
Internal Test Pattern Generation...................................................81
SD Test Patterns...........................................................................81
ED/HD Test Patterns ..................................................................81
SD Timing ........................................................................................82
HD Timing.......................................................................................87
Video Output Levels .......................................................................88
SD YPrPb Output Levels—SMPTE/EBU N10........................88
ED/HD YPrPb Output Levels ...................................................89
SD/ED/HD RGB Output Levels................................................90
SD Output Plots ..........................................................................91
Video Standards ..............................................................................92
Configuration Scripts .....................................................................94
Standard Definition....................................................................94
Enhanced Definition ..................................................................98
High Definition.........................................................................101
Outline Dimensions......................................................................106
Ordering Guide .........................................................................106
Rev.D | Page 3 of 108
ADV7342/ADV7343
Data Sheet
REVISION HISTORY
3/12—Rev. C to Rev. D
Changes to Table 15 ....................................................................... 20
Changes to MPU Port Description Section................................ 27
Changes to I2C Operation Section ............................................... 27
Added Table 16 ............................................................................... 27
Added Figure 49 ............................................................................. 28
Changes to Table 17 ....................................................................... 29
Changes to Table 18 ....................................................................... 29
Changes to Table 21, 0x30 Bit Description ................................. 32
Changes to Table 29 ....................................................................... 39
Changes to Table 30 ....................................................................... 40
Changes to Table 31, 0xA0 Register Name ................................. 42
Changes to Table 32 ....................................................................... 43
Added Table 33 and Table 34 ........................................................ 44
Changes to Standard Definition Only Section ........................... 46
Added Figure 52 ............................................................................. 47
Changes to Figure 53...................................................................... 47
Changes to Figure 56, Figure 57, and Figure 58......................... 48
Renamed Features Section to Design Features Section............. 50
Changes to ED/HD Nonstandard Timing Mode Section......... 50
Changes to Figure 60...................................................................... 51
Changed ADV7340/ADV7341 to ADV7342/ADV7343........... 70
3/12—Rev. B to Rev. C
Reorganized Layout............................................................Universal
Change to Features Section ............................................................. 1
Moved Revision History Section.................................................... 4
Change to Table 1 ............................................................................. 5
Changes to Digital Input/Output Specifications—
1.8 V Section ..................................................................................... 8
Changes to Table 15........................................................................ 21
Changes to Table 21........................................................................ 33
Changes to Table 24........................................................................ 36
Changes to Table 29........................................................................ 41
Changes to Table 30........................................................................ 42
Changes to 24-Bit 4:4:4 RGB Mode Section ............................... 48
Deleted ED/HD Nonstandard Timing Mode Section, Figure 59,
and Table 42, Renumbered Sequentially ..................................... 50
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode
Section, and Figure 60.................................................................... 51
Deleted Figure 61............................................................................ 52
Added External Sync Polarity Section......................................... 52
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section.................................................................................... 53
Changes to ED/HD Test Patterns Section................................... 81
P_HSYNC
P_VSYNC
Added HD Interlace External
and
Considerations Section.................................................................. 51
Changes to SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section.................................................. 51
Changes to Programming the FSC Section................................... 53
Changes to Subaddress 0x8C to Subaddress 0x8F Section....... 53
Changes to Subaddress 0x82, Bit 4 Section................................. 53
Added SD Manual CSC Matrix Adjust Feature Section............ 56
Changes to Subaddress 0x9C to Subaddress 0x9F Section....... 57
Changes to SD Brightness Detect Section................................... 58
Changes to Figure 71...................................................................... 60
Added Sleep Mode Section ........................................................... 68
Changes to Pixel and Control Port Readback Section .............. 68
Added SD Teletext Insertion Section........................................... 68
Added Unused Pins Section.......................................................... 70
Added Figure 86 and Figure 87 .................................................... 70
Changes to Power Supply Sequencing Section........................... 72
Changes to Figure 94...................................................................... 75
Changes to SD Wide Screen Signaling Section .......................... 77
Changes to Internal Test Pattern Generation Section ............... 79
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section.................................. 80
Added Configuration Scripts Section.......................................... 92
9/11—Rev. A to Rev. B
Changes to MPU Port Description Section ................................ 27
3/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Deleted Detailed Features Section, Changes to Table 1............... 4
Changes to Figure 1.......................................................................... 5
Changes to Table 6............................................................................ 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 7 ................................................................................................ 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................ 8
Added Table 9.................................................................................... 9
Changes to MPU Port Timing Specifications Section,
Default Conditions......................................................................... 10
Deleted Figure 20............................................................................ 18
Changes to Table 13........................................................................ 19
10/06—Revision 0: Initial Version
Rev. D | Page 4 of 108
Data Sheet
ADV7342/ADV7343
GENERAL DESCRIPTION
Table 1. Standards Directly Supported by the ADV7342/
ADV7343
The ADV7342/ADV7343 are high speed, digital-to-analog
video encoders in a 64-lead LQFP package. Six high speed,
3.3 V, 11-bit video DACs provide support for composite
(CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog
outputs in standard definition (SD), enhanced definition (ED),
or high definition (HD) video formats.
Active
Resolution
Frame
Clock Input
(MHz)
I/P1 Rate (Hz)
Standard
720 × 240
720 × 288
720 × 480
P
P
I
59.94
50
29.97
27
27
27
ITU-R
BT.601/656
The ADV7342/ADV7343 have a 24-bit pixel input port that can
be configured in a variety of ways. SD video formats are sup-
ported over an SDR interface, and ED/HD video formats are
supported over SDR and DDR interfaces. Pixel data can be
supplied in either the YCrCb or RGB color spaces.
720 × 576
640 × 480
768 × 576
I
I
I
25
27
ITU-R
BT.601/656
NTSC Square
Pixel
PAL Square
Pixel
29.97
25
24.54
29.5
The parts also support embedded EAV/SAV timing codes,
external video synchronization signals, and I2C® communication
protocol.
720 × 483
720 × 483
720 × 483
720 × 576
720 × 483
720 × 576
1920 × 1035
1920 × 1035
1280 × 720
P
P
P
P
P
P
I
59.94
59.94
59.94
50
59.94
50
30
29.97
60, 50, 30,
25, 24
27
27
27
27
27
27
74.25
74.1758
74.25
SMPTE 293M
BTA T-1004
ITU-R BT.1358
ITU-R BT.1358
ITU-R BT.1362
ITU-R BT.1362
SMPTE 240M
SMPTE 240M
SMPTE 296M
In addition, simultaneous SD and ED/HD input and output are
supported. Full-drive DACs ensure that external output buffering
is not required, while 216 MHz (SD and ED) and 297 MHz
(HD) oversampling ensures that external output filtering is not
required.
I
P
Cable detection and DAC autopower-down features keep power
consumption to a minimum.
1280 × 720
P
23.97,
74.1758
SMPTE 296M
Table 1 lists the video standards directly supported by the
ADV7342/ADV7343.
59.94, 29.97
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
I
I
P
P
P
30, 25
29.97
30, 25, 24
23.98, 29.97 74.1758
24 74.25
74.25
74.1758
74.25
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 274M
ITU-R BT.709-5
1 I = interlaced, P = progressive.
Rev.D | Page 5 of 108
ADV7342/ADV7343
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
DGND (2)
V
(2)
AGND
V
AA
SCL
SDA ALSB
SFL
DD
ADV7342/ADV7343
GND_IO
VBI DATA SERVICE
INSERTION
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
V
DD_IO
11-BIT
DAC 1
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
16×
YCrCb
PROGRAMMABLE
ADD
FILTER
TO
LUMINANCE
FILTER
11-BIT
DAC 2
8-/16-/24-BIT
SD
SYNC
RGB
RGB
TO
YCrCb
MATRIX
4:2:2 TO 4:4:4
SD
11-BIT
DAC 3
DEINTERLEAVE
VIDEO
DATA
PROGRAMMABLE
CHROMINANCE
FILTER
16×
FILTER
ADD
BURST
SIN/COS DDS
BLOCK
R
11-BIT
DAC 4
RGB
ASYNC
BYPASS
RGB
G/B
11-BIT
DAC 5
YCbCr
8-/16-/24-BIT
ED/HD
PROGRAMMABLE
YCbCr
TO
SDR/DDR
ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
HDTV FILTERS
4×
FILTER
RGB MATRIX
HDTV
TEST
PATTERN
GENERATOR
11-BIT
DAC 6
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
VIDEO
DATA
POWER
MANAGEMENT
CONTROL
REFERENCE
AND CABLE
DETECT
16x/4x OVERSAMPLING
DAC PLL
R
(2)
VIDEO TIMING GENERATOR
SET
P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC CLKIN (2) PV
PGND EXT_LF (2)
V
COMP (2)
DD
REF
Figure 1.
Rev.D | Page 6 of 108
Data Sheet
ADV7342/ADV7343
SPECIFICATIONS
POWER SUPPLY AND VOLTAGE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
SUPPLY VOLTAGES
VDD
VDD_IO
PVDD
VAA
1.71
1.71
1.71
2.6
1.8
3.3
1.8
3.3
1.89
3.63
1.89
3.465
V
V
V
V
POWER SUPPLY REJECTION RATIO
0.002
%/%
VOLTAGE REFERENCE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
1.31
1.31
Unit
V
V
Internal Reference Range, VREF
External Reference Range, VREF
External VREF Current1
1.186
1.15
1.248
1.235
10
µA
1 External current required to overdrive internal VREF
.
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
Conditions1
Min
Typ
27
Max
Unit
fCLKIN_A
SD/ED
MHz
fCLKIN_A
ED (at 54 MHz)
54
MHz
fCLKIN_A
fCLKIN_B
fCLKIN_B
HD
ED
HD
74.25
27
74.25
MHz
MHz
MHz
CLKIN_A High Time, t9
CLKIN_A Low Time, t10
CLKIN_B High Time, t9
CLKIN_B Low Time, t10
CLKIN_A Peak-to-Peak Jitter Tolerance
CLKIN_B Peak-to-Peak Jitter Tolerance
40
40
40
40
% of one clock cycle
% of one clock cycle
% of one clock cycle
% of one clock cycle
ns
2
2
ns
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
Rev.D | Page 7 of 108
ADV7342/ADV7343
Data Sheet
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V VREF = 1.235 V (driven externally).
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
Full-Drive Output Current (Full-Scale)
RSET = 510 Ω, RL = 37.5 Ω
DAC 1, DAC 2, DAC 3 enabled1
RSET = 510 Ω, RL = 37.5 Ω
DAC 1 enabled only2
RSET = 4.12 kΩ, RL = 300 Ω
DAC 1 to DAC 6
33
34.6
37
mA
33
4.1
0
33.5
37
mA
Low-Drive Output Current (Full-Scale)3
DAC-to-DAC Matching
Output Compliance, VOC
4.3
1.0
4.5
1.4
mA
%
V
Output Capacitance, COUT
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
10
6
8
6
2
pF
pF
ns
ns
ns
ns
Analog Output Delay4
DAC Analog Output Skew
1
1 Applicable to full-drive capable DACs only, that is, DAC 1, DAC 2, DAC 3.
2 The recommended method of bringing this typical value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
3 Applicable to all DACs.
4 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter
Conditions
Min
Typ
4
Max
Unit
V
V
µA
pF
V
V
µA
pF
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
2.0
0.8
10
VIN = VDD_IO
ISOURCE = 400 µA
ISINK = 3.2 mA
VIN = 0.4 V, 2.4 V
2.4
0.4
1.0
4
DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V
When VDD_IO is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, and VS, should use 1.8 V levels.
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
Conditions
Min
Typ
4
Max
Unit
V
V
pF
V
V
Input High Voltage, VIH
Input Low Voltage, VIL
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Output Capacitance
0.7 VDD_IO
0.3 VDD_IO
ISOURCE = 400 µA
ISINK = 3.2 mA
VDD_IO – 0.4
0.4
4
pF
Rev.D | Page 8 of 108
Data Sheet
ADV7342/ADV7343
DIGITAL TIMING SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 8.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t11
Conditions1
Min
Typ
Max
Unit
4
SD
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
4
Data Input Hold Time, t12
4
Control Input Setup Time, t11
4
Control Input Hold Time, t12
4
Control Output Access Time, t13
12
10
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
4
Control Output Hold Time, t14
4.0
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 3.5
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
68
67
78
84
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Component Outputs (1×)
Component Outputs (8×)
HD1
ED oversampling disabled
ED oversampling enabled
41
46
Clock cycles
Clock cycles
Component Outputs (1×)
Component Outputs (4×)
HD oversampling disabled
HD oversampling enabled
40
44
Clock cycles
Clock cycles
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video data: C[7:0], Y[7:0], and S[7:0].
3 Video control:
,
,
,
, and
.
P_HSYNC P_VSYNC P_BLANK S_HSYNC
S_VSYNC
4 Guaranteed by characterization.
5 Guaranteed by design.
Rev.D | Page 9 of 108
ADV7342/ADV7343
Data Sheet
DIGITAL TIMING SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 9.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t11
Conditions1
Min
Typ
Max
Unit
4
SD
1.4
1.9
1.9
1.6
1.4
1.5
1.5
1.3
1.4
1.2
1.0
1.4
1.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
4
Data Input Hold Time, t12
4
Control Input Setup Time, t11
4
Control Input Hold Time, t12
4
Control Output Access Time, t13
13
12
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
4
Control Output Hold Time, t14
4.0
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 5.0
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
68
67
78
84
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Component Outputs (1×)
Component Outputs (8×)
HD1
ED oversampling disabled
ED oversampling enabled
41
46
Clock cycles
Clock cycles
Component Outputs (1×)
Component Outputs (4×)
HD oversampling disabled
HD oversampling enabled
40
44
Clock cycles
Clock cycles
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video data: C[7:0], Y[7:0], and S[7:0].
3 Video control:
,
,
,
, and
.
P_HSYNC P_VSYNC P_BLANK S_HSYNC
S_VSYNC
4 Guaranteed by characterization.
5 Guaranteed by design.
Rev.D | Page 10 of 108
Data Sheet
ADV7342/ADV7343
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 10.
Parameter
MPU PORT, I2C MODE1
Conditions
Min
Typ
Max
Unit
See Figure 19
SCL Frequency
0
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCL High Pulse Width, t1
SCL Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDA, SCL Rise Time, t6
SDA, SCL Fall Time, t7
Setup Time (Stop Condition), t8
0.6
1.3
0.6
0.6
100
300
300
0.6
1 Guaranteed by characterization.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter
Conditions
Min
Typ
Max
Unit
NORMAL POWER MODE1, 2
3
IDD
SD only (16× oversampling)
90
65
91
95
122
1
124
140
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ED only (8× oversampling)4
HD only (4× oversampling)4
SD (16× oversampling) and ED (8× oversampling)
SD (16× oversampling) and HD (4× oversampling)
IDD_IO
5
IAA
Three DACs enabled (ED/HD only)
Six DACs enabled (SD only and simultaneous modes )
SD only, ED only, or HD only modes
Simultaneous modes
IPLL
10
SLEEP MODE
IDD
IAA
IDD_IO
IPLL
5
µA
µA
µA
µA
0.3
0.2
0.1
1 RSET1 = 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). RSET2 = 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).
2 75% color bar test pattern applied to pixel data pins.
3 IDD is the continuous current required to drive the digital core.
4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5 IAA is the total current required to supply all DACs.
Rev.D | Page 11 of 108
ADV7342/ADV7343
Data Sheet
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = 25°C, VREF driven externally.
Table 12.
Parameter
Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE
Resolution
11
Bits
Integral Nonlinearity
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
0.4
0.5
0.15
0.5
0.25
0.2
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
Differential Nonlinearity1 +ve
Differential Nonlinearity1 −ve
STANDARD DEFINTION (SD) MODE
Luminance Nonlinearity
Differential Gain
Differential Phase
Signal-to-Noise Ratio (SNR)
0.5
0.5
0.6
58
%
%
Degrees
dB
NTSC
NTSC
Luma ramp
Flat field full bandwidth
75
dB
ENHANCED DEFINITION (ED) MODE
Luma Bandwidth
Chroma Bandwidth
12.5
5.8
MHz
MHz
HIGH DEFINITION (HD) MODE
Luma Bandwidth
Chroma Bandwidth
30
13.75
MHz
MHz
1 Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
Rev.D | Page 12 of 108
Data Sheet
ADV7342/ADV7343
TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 13:
•
•
t
t
13 = control output access time
14 = control output hold time
•
•
•
•
t9 = clock high time
t10 = clock low time
t11 = data setup time
t12 = data hold time
In addition, refer to Table 36 for the ADV7342/ADV7343 input
configuration.
CLKIN_A
t12
t9 t10
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
IN SLAVE MODE
S7 TO S0/
Y7 TO Y0*
Y0
t11
Y1
Y2
Cb0
Cr0
Cb2
t13
Cr2
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 2. SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
CLKIN_A
t9
t10
t12
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
IN SLAVE MODE
S7 TO S0/
Y7 TO Y0*
Y2
Y0
Y1
Y3
Y7 TO Y0/
C7 TO C0*
Cb2
Cb0
Cr0
Cr2
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 3. SD Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
CLKIN_A
t12
t9
t10
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
Y7 TO Y0
C7 TO C0
G0
B0
G1
B1
G2
B2
t11
S7 TO S0
R0
R1
R2
CONTROL
OUTPUTS
t14
t13
Figure 4. SD Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000)
Rev.D | Page 13 of 108
ADV7342/ADV7343
Data Sheet
CLKIN_A
t12
t9 t10
P_HSYNC,
P_VSYNC,
P_BLANK
CONTROL
INPUTS
Y7 TO Y0
C7 TO C0
Y0
Y1
Y2
Y3
Y4
Y5
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
t13
CONTROL
OUTPUTS
t14
Figure 5. ED/HD-SDR Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001)
CLKIN_A
t12
t9 t10
P_HSYNC,
P_VSYNC,
P_BLANK
CONTROL
INPUTS
Y7 TO Y0
C7 TO C0
Y0
Y1
Y2
Y3
Y4
Y5
Cb1
t11
Cb2
Cr2
Cb3
Cb4
Cb5
Cb0
Cr0
S7 TO S0
Cr1
Cr3
Cr4
Cr5
CONTROL
OUTPUTS
t14
t13
Figure 6. ED/HD-SDR Only, 24-Bit, 4:4:4 YCrCb Pixel Input Mode (Input Mode 001)
CLKIN_A
t12
t9 t10
P_HSYNC,
P_VSYNC,
P_BLANK
CONTROL
INPUTS
Y7 TO Y0
C7 TO C0
G0
G1
G2
G3
B3
G4
B4
G5
B5
B0
R0
B1
t11
B2
R2
S7 TO S0
R1
R3
R4
R5
CONTROL
OUTPUTS
t14
t13
Figure 7. ED/HD-SDR Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001)
Rev.D | Page 14 of 108
Data Sheet
ADV7342/ADV7343
CLKIN_A*
t9
t10
P_HSYNC,
P_VSYNC,
P_BLANK
CONTROL
INPUTS
Cb2
Y2
Cr2
Cb0
Y0
Cr0
Y1
Y7 TO Y0
t12
t12
t11
t11
t13
CONTROL
OUTPUTS
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
HSYNC VSYNC
) Pixel Input Mode (Input Mode 010)
Figure 8. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (
/
CLKIN_A*
t9
t10
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
Y7 TO Y0
t12
t12
t11
t11
t13
CONTROL
OUTPUTS
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 9. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010)
CLKIN_B
t12
t9 t10
P_HSYNC,
P_VSYNC,
P_BLANK
CONTROL
INPUTS
ED/HD INPUT
Y7 TO Y0
C7 TO C0
Y0
Y1
Y2
Y3
Y5
Y4
Y6
Cb0
Cr0
t11
Cb2
Cr2
Cb4
Cr4
Cb6
CLKIN_A
t9 t10
t12
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
SD INPUT
S7 TO S0
Cb0
Y0
Cr0
t11
Y1
Cb2
Y2
Cr2
Figure 10. SD and ED/HD-SDR, 16-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 011)
Rev.D | Page 15 of 108
ADV7342/ADV7343
Data Sheet
CLKIN_B
t9
t10
P_HSYNC,
P_VSYNC,
P_BLANK
CONTROL
INPUTS
EH/HD INPUT
Y0
Cr0
Y1
t12
Cb2
Y2
Cr2
Y7 TO Y0
Cb0
t12
t11
t11
CLKIN_A
t12
t9
t10
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
SD INPUT
S7 TO S0
Cb0
Y0
Cr0
t11
Y1
Cb2
Y2
Cr2
Figure 11. SD and ED/HD-DDR, 8-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 100)
CLKIN_A
t9 t10
P_HSYNC,
CONTROL
INPUTS
P_VSYNC,
P_BLANK
Cb0
t12
Y0
Cr0
Y1
Cb2
Cr2
Y7 TO Y0
Y2
t13
t14
t11
CONTROL
OUTPUTS
HSYNC VSYNC
) Pixel Input Mode (Input Mode 111)
Figure 12. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (
/
CLKIN_A
t9
t10
Y7 TO Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t12
t13
t14
t11
CONTROL
OUTPUTS
Figure 13. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111)
Rev.D | Page 16 of 108
Data Sheet
ADV7342/ADV7343
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Y2
Y3
Y0
Y1
Cb0 Cr0 Cb2 Cr2
C7 TO C0
b
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
/
Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb (
) Input Timing Diagram
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Cr0 Y1
Cb0
Y0
b
a = 32 CLOCK CYCLES FOR 525p
a = 24 CLOCK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLOCK CYCLES FOR 525p
b(MIN) = 264 CLOCK CYCLES FOR 625p
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUTAFTER A TIME
EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
) Input Timing Diagram
Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb (
/
Rev.D | Page 17 of 108
ADV7342/ADV7343
Data Sheet
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Y2
Y3
Y0
Y1
C7 TO C0
Cb0 Cr0 Cb2 Cr2
b
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
/
Figure 16. HD-SDR, 16-Bit, 4:2:2 YCrCb (
) Input Timing Diagram
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Cr0 Y1
Cb0
Y0
b
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
HSYNC VSYNC
) Input Timing Diagram
Figure 17. HD-DDR, 8-Bit, 4:2:2 YCrCb (
/
Rev.D | Page 18 of 108
Data Sheet
ADV7342/ADV7343
S_HSYNC
S_VSYNC
Y7 TO Y0*
Cr
Y
Cb
Y
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 18. SD Input Timing Diagram (Timing Mode 1)
t5
t3
t3
SDA
t6
t1
SCL
t2
t7
t4
t8
Figure 19. MPU Port Timing Diagram (I2C Mode)
Rev.D | Page 19 of 108
ADV7342/ADV7343
Data Sheet
ABSOLUTE MAXIMUM RATINGS
The ADV7342/ADV7343 are high performance integrated
circuits with an ESD rating of <1 kV, and they are ESD sensitive.
Proper precautions should be taken for handling and assembly.
Table 13.
Parameter1
Rating
VAA to AGND
VDD to DGND
PVDD to PGND
VDD_IO to GND_IO
AGND to DGND
AGND to PGND
AGND to GND_IO
DGND to PGND
−0.3 V to +3.9 V
−0.3 V to +2.3 V
−0.3 V to +2.3 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VDD_IO + 0.3 V
−0.3 V to VAA
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 14. Thermal Resistance1
Package Type
θJA
θJC
Unit
64-Lead LQFP
47
11
°C/W
DGND to GND_IO
PGND to GND_IO
1 Values are based on a JEDEC 4-layer test board.
The ADV7342/ADV7343 are RoHS-compliant, Pb-free products.
The lead finish is 100% pure Sn electroplate. The devices are
suitable for Pb-free applications up to 255°C ( 5°C) IR reflow
(JEDEC STD-20).
Digital Input Voltage to GND_IO
Analog Outputs to AGND
Maximum CLKIN Input Frequency
Storage Temperature Range (TS)
Junction Temperature (TJ)
Lead Temperature (Soldering, 10 sec)
80 MHz
−65°C to +150°C
150°C
They are backward compatible with conventional SnPb soldering
processes. The electroplated Sn coating can be soldered with
Sn/Pb solder paste at conventional reflow temperatures of
220°C to 235°C.
260°C
1 Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev.D | Page 20 of 108
Data Sheet
ADV7342/ADV7343
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
SFL
DD_IO
PIN 1
2
3
TEST0
TEST1
Y0
R
SET1
REF
V
4
COMP1
DAC 1
DAC 2
DAC 3
5
Y1
6
Y2
ADV7342/ADV7343
7
Y3
TOP VIEW
(Not to Scale)
8
Y4
V
AA
9
Y5
AGND
DAC 4
DAC 5
DAC 6
10
11
12
13
14
15
16
V
DD
DGND
Y6
Y7
R
SET2
COMP2
PV
TEST2
TEST3
C0
DD
EXT_LF1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 20. Pin Configuration
Table 15. Pin Function Descriptions
Input/
Output
Pin No.
Mnemonic
Description
13, 12,
9 to 4
29 to 25,
18 to 16
62 to 58,
55 to 53
Y7 to Y0
I
I
I
I
8-Bit Pixel Port. Y0 is the LSB. Refer to Table 36 for input modes.
8-Bit Pixel Port. C0 is the LSB. Refer to Table 36 for input modes.
8-Bit Pixel Port. S0 is the LSB. Refer to Table 36 for input modes.
Unused. These pins should be connected to DGND.
C7 to C0
S7 to S0
52, 51, 15, TEST5 to
14, 3, 2
30
63
TEST0
CLKIN_A
CLKIN_B
I
I
Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz), or SD Only (27 MHz).
Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
50
49
S_HSYNC
S_VSYNC
I/O
I/O
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
22
23
P_HSYNC
P_VSYNC
I
I
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
24
48
P_BLANK
SFL
I
ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
I/O
Subcarrier Frequency Lock (SFL) Input. The SFL input is used to drive the color subcarrier DDS
system.
47
RSET1
I
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from RSET1 to
AGND. For low-drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from RSET1 to AGND.
Rev.D | Page 21 of 108
ADV7342/ADV7343
Data Sheet
36
RSET2
I
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from RSET2 to AGND.
45, 35
COMP1,
COMP2
DAC 1, DAC 2,
DAC 3
DAC 4, DAC 5,
DAC 6
SCL
O
O
O
Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to VAA.
44, 43, 42
39, 38, 37
DAC Outputs. Full- and low-drive capable DACs.
DAC Outputs. Low-drive only capable DACs.
21
20
19
I
I2C Clock Input.
I2C Data Input/Output.
SDA
ALSB
I/O
I
This signal sets up the LSB2 of the MPU I2C address (see the Power Supply Sequencing section for
more information).
46
41
10, 56
VREF
VAA
VDD
Optional External Voltage Reference Input for DACs or Voltage Reference Output.
Analog Power Supply (3.3 V).
Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
P
P
1
34
VDD_IO
PVDD
P
P
Input/Output Digital Power Supply (1.8 V or 3.3 V).
PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
33
31
32
40
11, 57
64
EXT_LF1
EXT_LF2
PGND
AGND
DGND
I
I
G
G
G
G
External Loop Filter for On-Chip PLL 1.
External Loop Filter for On-Chip PLL 2.
PLL Ground Pin.
Analog Ground Pin.
Digital Ground Pin.
GND_IO
Input/Output Supply Ground Pin.
1 ED = enhanced definition = 525p and 625p.
2 LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the ADV7343, setting the
LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
Rev.D | Page 22 of 108
Data Sheet
ADV7342/ADV7343
TYPICAL PERFORMANCE CHARACTERISTICS
Y RESPONSE IN ED 8× OVERSAMPLING MODE
EDPr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
0
1.0
0.5
–10
–20
–30
–40
–50
–60
–70
–80
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
20
40
60
80 100 120 140 160 180 200
FREQUENCY (MHz)
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response
Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)
HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
10
EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
0
20
40
60
80 100 120 140 160 180 200
FREQUENCY (MHz)
0
18.5
37.0
55.5
74.0
92.5
111.0 129.5 148.0
FREQUENCY (MHz)
Figure 22. ED 8× Oversampling, PrPb Filter (SSAF™) Response
Figure 25. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:2:2 Input)
HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE
Y RESPONSE IN ED 8× OVERSAMPLING MODE
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–100
0
20
40
60
80 100 120 140 160 180 200
FREQUENCY (MHz)
10 20 30 40 50 60 70 80 90 100 110 120 130 140
FREQUENCY (MHz)
Figure 23. ED 8× Oversampling, Y Filter Response
Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:4:4 Input)
Rev.D | Page 23 of 108
ADV7342/ADV7343
Data Sheet
Y RESPONSE IN HD 4× OVERSAMPLING MODE
10
0
0
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
18.5
37.0
55.5
74.0
92.5
111.0 129.5 148.0
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30. SD PAL, Luma Low-Pass Filter Response
Figure 27. HD 4× Oversampling, Y Filter Response
Y PASS BAND IN HD 4x OVERSAMPLING MODE
3.0
1.5
0
–10
–20
–30
–40
–50
–60
–70
0
–1.5
–3.0
–4.5
–6.0
–7.5
–9.0
–10.5
–12.0
0
2
4
6
8
10
12
27.750
46.250
30.063 32.375 34.688 37.000 39.312 41.625 43.937
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 28. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)
Figure 31. SD NTSC, Luma Notch Filter Response
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. SD NTSC, Luma Low-Pass Filter Response
Figure 32. SD PAL, Luma Notch Filter Response
Rev.D | Page 24 of 108
Data Sheet
ADV7342/ADV7343
Y RESPONSE IN SD OVERSAMPLING MODE
5
4
0
–10
–20
–30
–40
–50
–60
–70
–80
3
2
1
0
–1
5
6
7
0
20
40
60
80 100 120 140 160 180 200
FREQUENCY (MHz)
0
1
2
3
4
FREQUENCY (MHz)
Figure 33. SD, 16× Oversampling, Y Filter Response
Figure 36. SD Luma SSAF Filter, Programmable Gain
1
0
0
–10
–20
–30
–40
–50
–60
–70
–1
–2
–3
–4
–5
0
2
4
6
8
10
12
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34. SD Luma SSAF Filter Response up to 12 MHz
Figure 37. SD Luma SSAF Filter, Programmable Attenuation
4
2
0
–10
0
–20
–30
–40
–50
–60
–70
–2
–4
–6
–8
–10
–12
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. SD Luma SSAF Filter, Programmable Responses
Figure 38. SD Luma CIF Low-Pass Filter Response
Rev.D | Page 25 of 108
ADV7342/ADV7343
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 39. SD Luma QCIF Low-Pass Filter Response
Figure 42. SD Chroma 1.3 MHz Low-Pass Filter Response
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
10
12
0
2
4
6
8
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response
Figure 43. SD Chroma 1.0 MHz Low-Pass Filter Response
0
0
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
–50
–60
–70
10
12
0
2
4
6
8
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 41. SD Chroma 2.0 MHz Low-Pass Filter Response
Figure 44. SD Chroma 0.65 MHz Low-Pass Filter Response
Rev.D | Page 26 of 108
Data Sheet
ADV7342/ADV7343
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 45. SD Chroma CIF Low-Pass Filter Response
Figure 46. SD Chroma QCIF Low-Pass Filter Response
Rev.D | Page 27 of 108
ADV7342/ADV7343
Data Sheet
MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the
ADV7342/ADV7343 through a 2-wire serial (I2C-compatible)
bus. After power-up or reset, the MPU port is configured for
I2C operation.
master initiates a data transfer by establishing a start condition,
defined by a high-to-low transition on SDA while SCL remains
high. This indicates that an address/data stream follows. All
peripherals respond to the start condition and shift the next
W
eight bits (7-bit address plus the R/ bit). The bits are
I2C OPERATION
transferred from MSB down to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
occurs when the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted
The ADV7342/ADV7343 support a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. This port
operates in an open-drain configuration. Two wires, serial data
(SDA) and serial clock (SCL), carry information between any
device connected to the bus and the ADV7342/ADV7343. The
slave address of the device depends on the device (ADV7342 or
ADV7343), the operation (read or write), and the state of the
ALSB pin (0 or 1). See Table 16, Figure 47, and Figure 48. The
LSB sets either a read or a write operation. Logic 1 corresponds
to a read operation, and Logic 0 corresponds to a write
operation. A1 is controlled by setting the ALSB pin of the
ADV7342/ ADV7343 to Logic 0 or Logic 1.
W
address. The R/ bit determines the direction of the data.
Logic 0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first byte
means that the master reads information from the peripheral.
The ADV7342/ADV7343 act as a standard slave device on the
bus. The data on the SDA pin is eight bits long, supporting the
Table 16. ADV7342/ADV7343 I2C Slave Addresses
W
7-bit addresses plus the R/ bit. It interprets the first byte as
Device
ALSB
Operation
Write
Read
Write
Read
Slave Address
the device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
updating all the registers.
ADV7342
0
0
1
1
0
0
1
1
0xD4
0xD5
0xD6
0xD7
ADV7343
Write
Read
0x54
0x55
Write
Read
0x56
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCL high period, the user
should issue only a start condition, a stop condition, or a stop
condition followed by a start condition. If an invalid subaddress
is issued by the user, the ADV7342/ADV7343 do not issue an
acknowledge but return to the idle condition. If the user uses the
auto-increment method of addressing the encoder and exceeds
the highest subaddress, the following actions are taken:
0x57
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 47. ADV7342 I2C Slave Address
•
In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge condition
occurs when the SDA line is not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7342/ADV7343, and the parts return to the idle
condition.
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
•
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 49 shows data transfer for a write sequence and the start
and stop conditions. Figure 50 shows bus write and read
sequences.
Figure 48. ADV7343 I2C Slave Address
Analog Devices, Inc., recommends tying up ALSB. If this is not
done, a power supply sequence (PSS) may be required. For more
information on the PSS, see the Power Supply Sequencing section.
The various devices on the bus use the following protocol. The
Rev.D | Page 28 of 108
Data Sheet
ADV7342/ADV7343
SDA
SCL
S
P
9
1–7
9
9
1–7
8
8
1–7
8
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
Figure 49. I2C Data Transfer
WRITE
S
S
SLAVE ADDR A(S)
LSB = 0
SUBADDR
SUBADDR
A(S)
DATA
A(S)
DATA
A(M)
A(S) P
SEQUENCE
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S)
A(S)
S
SLAVE ADDR A(S)
DATA
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
Figure 50. I2C Read and Write Sequence
Rev.D | Page 29 of 108
ADV7342/ADV7343
Data Sheet
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV7342/ADV7343 via the MPU port, except for registers that
are specified as read-only or write-only registers.
REGISTER PROGRAMMING
Table 17 to Table 35 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
The subaddress register determines which register the next
read or write operation accesses. All communication through
the MPU port starts with an access to the subaddress register.
A read/write operation is then performed from/to the target
address, which increments to the next address until the
transaction is complete.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines to or
from which register the operation takes place.
Table 17. Register 0x00
SR7 to
Bit Number
Register
Setting
Reset
Value
0x12
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0x00
Power
mode
Sleep mode. With this control enabled, the current consumption is
reduced to μA level. All DACs and the internal PLL circuits are
disabled. Registers can be read from and written to in sleep mode.
0
Sleep
mode off
Sleep
1
mode on
PLL and oversampling control. This control allows the internal PLL 1
circuit to be powered down and the oversampling to be switched off.
0
1
PLL 1 on
PLL 1 off
DAC 3 off
DAC 3 on
DAC 2 off
DAC 2 on
DAC 1 off
DAC 1 on
DAC 6 off
DAC 6 on
DAC 5 off
DAC 5 on
DAC 4 off
DAC 4 on
DAC 3: power on/off.
DAC 2: power on/off.
DAC 1: power on/off.
DAC 6: power on/off.
DAC 5: power on/off.
DAC 4: power on/off.
0
1
0
1
0
1
0
1
0
1
0
1
Table 18. Register 0x01 to Register 0x09
SR7 to
Bit Number1
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
0x01
Mode select
Reserved.
0
DDR clock edge alignment
(only used for ED-2 and
HD-DDR modes)
0
0
Chroma clocked in on rising clock edge; luma
clocked in on falling clock edge
Reserved
Reserved
Luma clocked in on rising clock edge;
chroma clocked in on falling clock edge
0
1
1
1
0
1
Reserved.
0
Input mode (see Register
0x30, Bits[7:3] for ED/HD
standard selection)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SD input only
ED/HD-SDR input only
ED/HD-DDR input only
SD and ED/HD-SDR
SD and ED/HD-DDR
Reserved
Reserved
ED only (at 54 MHz)
Y/C/S bus swap
0
1
Allows data to be applied to data ports in
various configurations (SD feature only)
Rev.D | Page 30 of 108
Data Sheet
ADV7342/ADV7343
SR7 to
Bit Number1
Reset
Value
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
0x02
Mode
Register 0
Reserved
0
0 must be written to this bit
Default
0x20
HD interlace external
VSYNC and HSYNC
0
1
If using HD HSYNC/VSYNCinterlace mode,
setting this bit to 1 is recommended (see the
HD Interlace External P_HSYNC and P_VSYNC
Considerations section for more information)
Test pattern black bar.3
Manual CSC matrix adjust
Sync on RGB
0
1
Disabled
Enabled
0
1
Disable manual CSC matrix adjust
Enable manual CSC matrix adjust
No sync
Sync on all RGB outputs
RGB component outputs
YPrPb component outputs
No sync output
0
1
RGB/YPrPb output select
SD sync output enable
ED/HD sync output enable
0
1
0
1
HSYNC
VSYNC
and
Output SD syncs on
No sync output
and
pins
0
1
HSYNC
Output ED/HD syncs on
VSYNC
pins
0x03
0x04
ED/HD CSC
Matrix 0
x
x
x
x
LSBs for GY
0x03
0xF0
ED/HD CSC
Matrix 1
LSBs for RV
LSBs for BU
LSBs for GV
LSBs for GU
Bits[9:2 ] for GY
x
x
x
x
x
x
x
x
0x05
0x06
0x07
0x08
0x09
ED/HD CSC
Matrix 2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x4E
0x0E
0x24
0x92
0x7C
ED/HD CSC
Matrix 3
x
x
x
x
x
x
x
x
Bits[9:2] for GU
Bits[9:2] for GV
Bits[9:2] for BU
Bits[9:2] for RV
ED/HD CSC
Matrix 4
ED/HD CSC
Matrix 5
ED/HD CSC
Matrix 6
1 x = Logic 0 or Logic 1.
2 ED = enhanced definition = 525p and 625p.
3 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0s84, Bit 6 must also be enabled (SD).
Rev.D | Page 31 of 108
ADV7342/ADV7343
Data Sheet
Table 19. Register 0x0A to Register 0x10
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
0
0
0
…
0
6
0
0
0
…
0
5
0
0
0
…
1
4
0
0
0
…
1
3
0
0
0
…
1
2
0
0
0
…
1
1
0
0
1
…
1
0
0
1
0
…
1
Register Setting
Value
0x0A
DAC 4, DAC 5, DAC 6 Positive gain to DAC output voltage
output levels
0%
0x00
+0.018%
+0.036%
…
+7.382%
+7.5%
−7.5%
−7.382%
−7.364%
…
−0.018%
0%
+0.018%
+0.036%
…
+7.382%
+7.5%
−7.5%
−7.382%
−7.364%
…
0
1
0
0
0
0
0
0
Negative gain to DAC output voltage
1
1
1
…
1
1
1
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
1
0
…
1
0x0B
DAC 1, DAC 2, DAC 3 Positive gain to DAC output voltage
output levels
0
0
0
…
0
0
0
0
…
0
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
1
0
…
1
0x00
0
1
0
0
0
0
0
0
Negative gain to DAC output voltage
1
1
1
…
1
1
1
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
1
0
…
1
−0.018%
0x0D
DAC power mode
DAC 1 low power enable
DAC 2 low power enable
DAC 3 low power enable
0
DAC 1 low power
disabled
DAC 1 low power
enabled
0x00
1
0
1
DAC 2 low power
disabled
DAC 2 low power
enabled
0
1
DAC 3 low power
disabled
DAC 3 low power
enabled
Reserved
0
0
0
0
0
0
0x10
Cable detection
DAC 1 cable detect (read only)
0
1
Cable detected on
DAC 1
DAC 1 unconnected
0x00
DAC 2 cable detect (read only)
0
1
Cable detected on
DAC 2
DAC 2 unconnected
Reserved
0
Unconnected DAC autopower-down
0
1
DAC autopower-
down disable
DAC autopower-
down enable
Reserved
0
0
0
Rev.D | Page 32 of 108
Data Sheet
ADV7342/ADV7343
Table 20. Register 0x12 to Register 0x17
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
S[7:0] readback
Y[7:0] readback
C[7:0] readback
P_BLANK
7
x
x
x
6
x
x
x
5
x
x
x
4
x
x
x
3
x
x
x
2
x
x
x
1
x
x
x
0
x
x
x
x
Register Setting
Value
0xXX
0xXX
0xXX
0xXX
0x12
0x13
0x14
0x16
Pixel port readback (S bus)
Pixel port readback (Y bus)
Pixel port readback (C bus)
Control port readback
Read only.
Read only.
Read only.
Read only.
P_VSYNC
x
P_HSYNC
x
S_VSYNC
x
S_HSYNC
x
SFL
x
Reserved
0
0
0
0
0x17
Software reset
Reserved
0
0x00
Software reset
0
1
Writing a 1 resets the device;
this is a self-clearing bit.
Reserved
0
0
0
0
1 x = Logic 0 or Logic 1.
Table 21. Register 0x30
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Note
0x30
ED/HD Mode
Register 1
ED/HD output standard
0
0
EIA770.2 output
EIA770.3 output
ED
HD
0
1
1
0
EIA770.1 output
Output levels for full input
range
1
1
Reserved
ED/HD input
synchronization format
0
1
External
,
and
HSYNC VSYNC
field inputs1
Embedded EAV/SAV codes
SMPTE 293M, ITU-BT.1358
BTA-1004, ITU-BT.1362
ITU-BT.1358
ED/HD standard2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
525p at 59.94 Hz
525p at 59.94 Hz
625p at 50 Hz
ITU-BT.1362
625p at 50 Hz
SMPTE 296M-1, SMPTE 274M-2
SMPTE 296M-3
720p at 60/59.94 Hz
720p at 50 Hz
SMPTE 296M-4, SMPTE 274M-5
SMPTE 296M-6
720p at 30/29.97 Hz
720p at 25 Hz
SMPTE 296M-7,
SMPTE 296M-8
720p at 24/23.98 Hz
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
SMPTE 240M
Reserved
1035i at 60/59.94 Hz
1080i at 30/29.97 Hz
Reserved
SMPTE 274M-4,
SMPTE 274M-5
0
0
1
1
1
1
1
1
0
1
SMPTE 274M-6
1080i at 25 Hz
SMPTE 274M-7,
SMPTE 274M-8
1080p at 30/29.97 Hz
1
1
0
0
0
0
0
0
0
1
SMPTE 274M-9
1080p at 25 Hz
SMPTE 274M-10,
SMPTE 274M-11
1080p at 24/23.98 Hz
1
0
0
1
0
ITU-R BT.709-5
Reserved
1080Psf at 24 Hz
10011–11111
1 Synchronization can be controlled with a combination of either
and
inputs or
and field inputs, depending on Subaddress 0x34, Bit 6.
HSYNC
HSYNC
VSYNC
P_HSYNC
P_VSYNC
Considerations section for more information.
2 See the HD Interlace External
and
Rev.D | Page 33 of 108
ADV7342/ADV7343
Data Sheet
Table 22. Register 0x31 to Register 0x33
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Register Setting
Pixel data valid off.
Pixel data valid on.
0x31
ED/HD Mode
Register 2
ED/HD pixel data valid
Reserved
0
ED/HD test pattern enable
0
1
ED/HD test pattern off.
ED/HD test pattern on.
Hatch.
ED/HD test pattern hatch/field
ED/HD VBI open
0
1
Field/frame.
Disabled.
0
1
Enabled.
ED/HD undershoot limiter
0
0
1
1
0
1
0
1
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
ED/HD sharpness filter
0
1
Disabled.
Enabled.
0x32
ED/HD Mode
Register 3
ED/HD Y delay with respect to the
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
Disabled.
0x00
HSYNC
falling edge of
ED/HD color delay with respect to the
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
HSYNC
falling edge of
ED/HD CGMS
0
1
Enabled.
ED/HD CGMS CRC
0
1
Disabled.
Enabled.
0x33
ED/HD Mode
Register 4
ED/HD Cr/Cb sequence
0
1
HSYNC
0x68
Cb after falling edge of
Cr after falling edge of
.
HSYNC
Reserved
0
0
0 must be written to these bits.
Sinc compensation filter on DAC 1,
DAC 2, DAC 3
0
1
Disabled.
Enabled
Reserved
0
0 must be written to this bit.
Disabled.
Enabled.
ED/HD chroma SSAF
0
1
ED/HD chroma input
0
1
4:4:4.
4:2:2
ED/HD double buffering
0
1
Disabled.
Enabled.
Rev.D | Page 34 of 108
Data Sheet
ADV7342/ADV7343
Table 23. Register 0x34 to Register 0x35
SR7 to
Bit Number
Reset
Value
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Register Setting
0x34
ED/HD Mode
Register 5
ED/HD timing reset
Internal ED/HD timing counters enabled
Resets the internal ED/HD timing counters
0x48
1
HSYNC
VSYNC
0
1
ED/HD
ED/HD
control
HSYNC
output control (refer to Table 56)
1
0
1
control
VSYNC
output control (refer to Table 57)
ED/HD blank polarity
0
1
P_BLANK
P_BLANK
active high
active low
ED Macrovision® enable
Reserved
0
1
Macrovision disabled
Macrovision enabled
0
0 must be written to this bit
VSYNC
/field input
0
1
0 = field input
ED/HD
VSYNC
1 =
input
Horizontal/vertical
counters2
0
1
Update field/line counter
Field/line counter free running
0x35
ED/HD Mode
Register 6
Reserved
0
0x00
ED/HD RGB input enable
0
1
Disabled
Enabled
ED/HD sync on PrPb
0
1
Disabled
Enabled
ED/HD color DAC swap
0
1
DAC 2 = Pb, DAC 3 = Pr
DAC 2 = Pr, DAC 3 = Pb
Gamma Correction Curve A
Gamma Correction Curve B
Disabled
ED/HD gamma
correction curve select
0
1
ED/HD gamma
correction enable
0
1
Enabled
ED/HD adaptive filter
mode
0
1
Mode A
Mode B
ED/HD adaptive filter
enable
0
1
Disabled
Enabled
1 Used in conjunction with ED/HD sync in Subaddress 0x02, Bit 7, set to 1.
2 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Rev.D | Page 35 of 108
ADV7342/ADV7343
Data Sheet
Table 24. Register 0x36 to Register 0x43
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
x
x
x
6
x
x
x
5
x
x
x
4
x
x
x
0
3
x
x
x
0
2
x
x
x
0
1
x
x
x
0
0
x
x
x
0
Register Setting Value
0x36
0x37
0x38
0x39
ED/HD Y level2
ED/HD Cr level2
ED/HD Cb level2
ED/HD Test Pattern Y level
ED/HD Test Pattern Cr level
ED/HD Test Pattern Cb level
Reserved
Y level value
Cr level value
Cb level value
0xA0
0x80
0x80
ED/HD Mode
Register 7
ED/HD EIA/CEA-861B
synchronization compliance
0
1
Disabled
Enabled
Reserved
0
0
0
0
0x3A
ED/HD Mode
Register 8
INV_PHSYNC_POL
0
1
0x00
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
INV_PVSYNC_POL
INV_PBLANK_POL
Reserved
0
1
0
1
0
0
0
0x40
ED/HD sharpness
filter gain
ED/HD sharpness filter gain,
Value A
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
0x00
…
1
…
1
…
1
…
1
ED/HD sharpness filter gain,
Value B
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
…
1
…
1
…
1
…
1
Gain B = −1
0x41
0x42
0x43
ED/HD CGMS
Data 0
ED/HD CGMS data bits
ED/HD CGMS data bits
ED/HD CGMS data bits
0
0
0
0
C19 C18 C17 C16 CGMS C19 to C16 0x00
ED/HD CGMS
Data 1
C15 C14 C13 C12 C11 C10 C9
C7 C6 C5 C4 C3 C2 C1
C8
C0
CGMS C15 to C8
CGMS C7 to C0
0x00
0x00
ED/HD CGMS
Data 2
1 x = Logic 0 or Logic 1.
2 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Rev.D | Page 36 of 108
Data Sheet
ADV7342/ADV7343
Table 25. Register 0x44 to Register 0x57
SR7 to
Bit Number1
Register
Setting
A0
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
SR0
Register
Bit Description
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
ED/HD Gamma A0
ED/HD Gamma A1
ED/HD Gamma A2
ED/HD Gamma A3
ED/HD Gamma A4
ED/HD Gamma A5
ED/HD Gamma A6
ED/HD Gamma A7
ED/HD Gamma A8
ED/HD Gamma A9
ED/HD Gamma B0
ED/HD Gamma B1
ED/HD Gamma B2
ED/HD Gamma B3
ED/HD Gamma B4
ED/HD Gamma B5
ED/HD Gamma B6
ED/HD Gamma B7
ED/HD Gamma B8
ED/HD Gamma B9
ED/HD Gamma Curve A (Point 24)
ED/HD Gamma Curve A (Point 32)
ED/HD Gamma Curve A (Point 48)
ED/HD Gamma Curve A (Point 64)
ED/HD Gamma Curve A (Point 80)
ED/HD Gamma Curve A (Point 96)
ED/HD Gamma Curve A (Point 128)
ED/HD Gamma Curve A (Point 160)
ED/HD Gamma Curve A (Point 192)
ED/HD Gamma Curve A (Point 224)
ED/HD Gamma Curve B (Point 24)
ED/HD Gamma Curve B (Point 32)
ED/HD Gamma Curve B (Point 48)
ED/HD Gamma Curve B (Point 64)
ED/HD Gamma Curve B (Point 80)
ED/HD Gamma Curve B (Point 96)
ED/HD Gamma Curve B (Point 128)
ED/HD Gamma Curve B (Point 160)
ED/HD Gamma Curve B (Point 192)
ED/HD Gamma Curve B (Point 224)
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
1 x = Logic 0 or Logic 1.
Rev.D | Page 37 of 108
ADV7342/ADV7343
Data Sheet
Table 26. Register 0x58 to Register 0x5D
SR7 to
Bit Number1
Register
Setting
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0x58
ED/HD Adaptive Filter Gain 1
ED/HD Adaptive Filter Gain 1,
Value A
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
…
1
…
1
…
1
…
1
ED/HD Adaptive Filter Gain 1,
Value B
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
…
1
…
1
…
1
…
1
0x59
ED/HD Adaptive Filter Gain 2
ED/HD Adaptive Filter Gain 2,
Value A
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
0x00
…
1
…
1
…
1
…
1
ED/HD Adaptive Filter Gain 2,
Value B
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
…
1
…
1
…
1
…
1
0x5A
ED/HD Adaptive Filter Gain 3
ED/HD Adaptive Filter Gain 3,
Value A
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
0x00
…
1
…
1
…
1
…
1
ED/HD Adaptive Filter Gain 3,
Value B
0
0
…
0
1
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
…
1
…
1
…
1
…
1
Gain B = −1
0x5B
0x5C
0x5D
ED/HD Adaptive Filter
Threshold A
ED/HD Adaptive Filter Threshold A
ED/HD Adaptive Filter Threshold B
ED/HD Adaptive Filter Threshold C
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Threshold A 0x00
Threshold B 0x00
Threshold C 0x00
ED/HD Adaptive Filter
Threshold B
x
x
x
x
x
x
x
x
ED/HD Adaptive Filter
Threshold C
1 x = Logic 0 or Logic 1.
Rev.D | Page 38 of 108
Data Sheet
ADV7342/ADV7343
Table 27. Register 0x5E to Register 0x6E
SR7 to
Bit Number
Register
Setting
Disabled
Enabled
Disabled
Enabled
H5 to H0
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
0x5E
ED/HD CGMS Type B
Register 0
ED/HD CGMS Type B
enable
ED/HD CGMS Type B
CRC enable
0
1
ED/HD CGMS Type B
header bits
H5
H4
H3
H2
H1
H0
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
ED/HD CGMS Type B
Register 1
ED/HD CGMS Type B
data bits
P7
P6
P5
P4
P3
P2
P1
P0
P7 to P0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ED/HD CGMS Type B
Register 2
ED/HD CGMS Type B
data bits
P15
P23
P31
P39
P47
P55
P63
P71
P79
P87
P95
P14
P22
P30
P38
P46
P54
P62
P70
P78
P86
P94
P13
P21
P29
P37
P45
P53
P61
P69
P77
P85
P93
P12
P20
P28
P36
P44
P52
P60
P68
P76
P84
P92
P11
P19
P27
P35
P43
P51
P59
P67
P75
P83
P91
P10
P18
P26
P34
P42
P50
P58
P66
P74
P82
P90
P98
P9
P8
P15 to P8
ED/HD CGMS Type B
Register 3
ED/HD CGMS Type B
data bits
P17
P25
P33
P41
P49
P57
P65
P73
P81
P89
P97
P16
P24
P32
P40
P48
P56
P64
P72
P80
P88
P96
P23 to P16
P31 to P24
P39 to P32
P47 to P40
P55 to P48
P63 to P56
P71 to P64
P79 to P72
P87 to P80
P95 to P88
P103 to P96
ED/HD CGMS Type B
Register 4
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 5
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 6
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 7
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 8
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 9
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 10
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 11
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 12
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 13
ED/HD CGMS Type B
data bits
P103 P102 P101 P100 P99
ED/HD CGMS Type B
Register 14
ED/HD CGMS Type B
data bits
P111 P110 P109 P108 P107 P106 P105 P104 P111 to P104 0x00
P119 P118 P117 P116 P115 P114 P113 P112 P119 to P112 0x00
P127 P126 P125 P124 P123 P122 P121 P120 P127 to P120 0x00
ED/HD CGMS Type B
Register 15
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
Register 16
ED/HD CGMS Type B
data bits
Rev.D | Page 39 of 108
ADV7342/ADV7343
Data Sheet
Table 28. Register 0x80 to Register 0x83
SR7 to
Bit Number
Reset
Value
0x10
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Register Setting
NTSC
PAL B/D/G/H/I
PAL M
0x80
SD Mode
Register 1
SD standard
PAL N
SD luma filter
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LPF NTSC
LPF PAL
Notch NTSC
Notch PAL
SSAF luma
Luma CIF
Luma QCIF
Reserved
1.3 MHz
0.65 MHz
1.0 MHz
2.0 MHz
SD chroma filter
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Chroma CIF
Chroma QCIF
3.0 MHz
0x82
SD Mode
Register 2
SD PrPb SSAF
0
1
Disabled
Enabled
0x0B
SD DAC Output 1
SD DAC Output 2
SD pedestal
0
1
Refer to Table 37 in the Output
Configuration section
0
1
Refer to Table 37 in the Output
Configuration section
0
1
Disabled
Enabled
SD square pixel mode
SD VCR FF/RW sync
SD pixel data valid
SD active video edge control
0
1
Disabled
Enabled
0
1
Disabled
Enabled
0
1
Disabled
Enabled
0
1
Disabled
Enabled
0x83
SD Mode
Register 3
SD pedestal on YPrPb
output
0
1
No pedestal on YPrPb
7.5 IRE pedestal on YPrPb
Y = 700 mV/300 mV
Y = 714 mV/286 mV
0x04
SD Output Levels Y
0
1
SD Output Levels PrPb
0
0
1
1
0
1
0
1
700 mV p-p (PAL), 1000 mV p-p (NTSC)
700 mV p-p
1000 mV p-p
648 mV p-p
SD VBI open
0
1
Disabled
Enabled
SD closed captioning field
control
0
0
1
1
0
1
0
1
Closed captioning disabled
Closed captioning on odd field only
Closed captioning on even field only
Closed captioning on both fields
Reserved
Reserved
0
Rev.D | Page 40 of 108
Data Sheet
ADV7342/ADV7343
Table 29. Register 0x84 to Register 0x89
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x84
SD Mode
Register 4
Reserved
0
0x00
SD SFL/SCR/TR mode select
0
1
0
1
Disabled.
SFL mode enabled.
720 pixels.
710 (NTSC), 702 (PAL).
Chroma enabled.
Chroma disabled.
Enabled.
SD active video length
SD chroma
0
1
0
1
SD burs
0
1
Disabled.
SD color bars
0
1
Disabled.
Enabled.
SD luma/chroma swap
0
1
DAC 2 = luma, DAC 3 = chroma.
DAC 2 = chroma, DAC 3 = luma.
5.17 μs.
0x86
SD Mode
Register 5
NTSC color subcarrier adjust (delay
from the falling edge of output
0
0
1
0
1
0
0x02
5.31 μs.
HSYNC
pulse to start of color burst)
5.59 μs (must be set for Macrovision
compliance).
1
1
Reserved.
Reserved
0
SD EIA/CEA-861B synchronization
compliance
0
1
Disabled.
Enabled.
Reserved
0
0
SD horizontal/vertical counter
mode1
0
1
Update field/line counter.
Field/line counter free running.
Normal.
Color reversal enabled.
Disabled.
SD RGB color swap
0
1
0x87
SD Mode
Register 6
SD luma and color scale control
SD luma scale saturation
SD hue adjust
0
1
0x00
Enabled.
0
1
Disabled.
Enabled.
0
1
Disabled.
Enabled.
SD brightness
0
1
Disabled.
Enabled.
SD luma SSAF gain
0
1
Disabled.
Enabled.
SD input standard autodetect
0
1
Disabled.
Enabled.
Reserved.
0
0 must be written to this bit.
SD YCrCb input.
SD RGB input.
SD RGB input enable
0
1
Rev.D | Page 41 of 108
ADV7342/ADV7343
Data Sheet
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
Reserved
7
6
5
4
3
2
1
0
Register Setting
0x88
SD Mode
Register 7
0
SD noninterlaced mode
0
1
Disabled.
Enabled.
SD double buffering
SD input format
0
1
Disabled.
Enabled.
0
0
1
1
0
1
0
1
8-bit YCbCr input.
16-bit YCbCr input.
16-bit RGB input.
Reserved.
SD digital noise reduction
SD gamma correction enable
SD gamma correction curve select
SD undershoot limiter
0
1
Disabled.
Enabled.
0
1
Disabled.
Enabled.
0
1
Gamma correction Curve A.
Gamma correction Curve B.
Disabled.
−11 IRE.
−6 IRE.
0x89
SD Mode
Register 8
0
0
1
1
0
1
0
1
0x00
−1.5 IRE.
Reserved
0
0 must be written to this bit.
Disabled.
Enabled.
SD black burst output on DAC luma
0
1
SD chroma delay
Reserved
0
0
1
1
0
1
0
1
Disabled.
Four clock cycles.
Eight clock cycles.
Reserved.
0
0
0 must be written to these bits.
1 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Table 30. Register 0x8A to Register 0x98
SR7 to
Bit Number1
Reset
Value
0x08
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Register Setting
Slave mode.
Master mode.
Mode 0.
0x8A
SD Timing Register 0
SD slave/master mode
SD timing mode
0
1
0
1
Mode 3.
Reserved
1
SD luma delay
0
0
1
1
0
1
0
1
No delay.
Two clock cycles.
Four clock cycles.
Six clock cycles.
−40 IRE.
SD minimum luma value
SD timing reset
0
1
−7.5 IRE.
0
1
Normal operation.
Freezes the counters;
this bit must be set
back to zero in order to
reset the counters and
resume operation.
Rev.D | Page 42 of 108
Data Sheet
ADV7342/ADV7343
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Register Setting
ta = one clock cycle.
ta = four clock cycles.
ta = 16 clock cycles.
ta = 128 clock cycles.
tb = 0 clock cycles.
tb = four clock cycles.
tb = eight clock cycles.
tb = 18 clock cycles.
tc = tb.
Value
0x8B
SD Timing Register 1
(applicable in master
modes only, that is,
Subaddress 0x8A, Bit
0 = 1)
HSYNC
0x00
SD
SD
SD
width
HSYNC VSYNC
to
0
0
1
1
0
1
0
1
delay
rising
HSYNC VSYNC
to
X2
X2
0
0
1
0
1
0
1
0
1
edge delay (Mode 1 only)
tc = tb + 32 µs.
VSYNC
One clock cycle.
Four clock cycles.
16 clock cycles.
128 clock cycles.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
SD
width (Mode 2 only)
1
HSYNC
0
0
1
1
x
0
1
0
1
x
SD
to pixel data adjust
0x8C
0x8D
0x8E
0x8F
SD FSC Register 03
SD FSC Register 13
SD FSC Register 23
SD FSC Register 33
SD FSC Phase
Subcarrier Frequency Bits[7:0]
Subcarrier Frequency Bits[15:8]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Subcarrier Frequency
Bits[7:0]
0x1F
0x7C
0xF0
0x21
x
x
x
x
x
x
Subcarrier Frequency
Bits[15:8].
Subcarrier Frequency
Bits[23:16]
Subcarrier Frequency
Bits[23:16].
Subcarrier Frequency
Bits[31:24]
Subcarrier Frequency
Bits[31:24].
0x90
0x91
0x92
Subcarrier Phase Bits[9:2]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Subcarrier Phase Bits[9:2]. 0x00
Extended Data Bits[7:0]. 0x00
SD Closed Captioning Extended data on even fields
SD Closed Captioning Extended data on even fields
Extended Data
Bits[15:8].
0x00
0x93
0x94
0x95
0x96
0x97
0x98
SD Closed Captioning Data on odd fields
SD Closed Captioning Data on odd fields
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Data Bits[7:0].
Data Bits[15:8].
0x00
0x00
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
Pedestal on odd fields
Pedestal on odd fields
Pedestal on even fields
Pedestal on even fields
17 16 15 14 13 12 11 10
25 24 23 22 21 20 19 18
17 16 15 14 13 12 11 10
25 24 23 22 21 20 19 18
Setting any of these bits 0x00
to 1 disables the
0x00
pedestal on the line
0x00
number indicated by
0x00
the bit settings.
1 x = Logic 0 or Logic 1.
2 X = don’t care.
3 SD subcarrier frequency registers default to NTSC subcarrier frequency values.
Rev.D | Page 43 of 108
ADV7342/ADV7343
Data Sheet
Table 31. Register 0x99 to Register 0xA5
SR7 to
Bit Number1
Reset
Value
SR0
Register
Bit Description
SD CGMS data
SD CGMS CRC
7
6
5
4
3
2
1
0
Register Setting
0x99
SD CGMS/WSS 0
x
x
x
x
CGMS Data Bits[C19:C16]
Disabled
0x00
0
1
Enabled
SD CGMS on odd fields
SD CGMS on even fields
SD WSS
0
1
Disabled
Enabled
0
1
Disabled
Enabled
0
1
Disabled
Enabled
0x9A
SD CGMS/WSS 1
SD CGMS/WSS data
x
x
x
x
x
x
x
x
CGMS Data Bits[C13:C8] or
WSS Data Bits[W13:W8]
0x00
SD CGMS data
x
x
x
x
CGMS Data Bits[C15:C14]
0x9B
0x9C
SD CGMS/WSS 2
SD scale LSB
SD CGMS/WSS data
x
x
x
x
x
x
x
x
CGMS Data Bits[C7:C0] or
WSS Data Bits[W7:W0]
0x00
0x00
LSBs for SD Y scale value
LSBs for SD Cb scale value
LSBs for SD Cr scale value
LSBs for SD FSC phase
SD Y scale value
SD Y Scale Bits[1:0]
SD Cb Scale Bits[1:0]
SD Cr Scale Bits[1:0].
Subcarrier Phase Bits[1:0]
SD Y Scale Bits[9:2]
x
x
x
x
x
x
x
x
x
x
x
x
0x9D
0x9E
0x9F
0xA0
SD Y scale register
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x00
0x00
0x00
0x00
SD Cb scale register SD Cb scale value
SD Cb Scale Bits[9:2]
SD Cr scale Bits[9:2]
SD Hue Adjust Bits[7:0]
SD Cr scale register
SD Cr scale value
SD hue adjust
register
SD hue adjust value
0xA1
SD brightness/WSS SD brightness value
SD blank WSS data
x
x
x
x
x
x
x
SD Brightness Bits[6:0]
0x00
0
1
Disabled
Enabled
−4 dB
…
0xA2
SD luma SSAF
SD luma SSAF gain/attenuation
0
…
0
0
…
1
0
…
1
0
…
0
0x00
(only applicable if Register
0x87, Bit 4 = 1)
0 dB
…
1
…
1
…
0
…
0
…
+4 dB
Reserved
0
0
0
0
0xA3
SD DNR 0
Coring gain border (in DNR
mode, the values in brackets
apply)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No gain
0x00
+1/16 [−1/8]
+2/16 [−2/8]
+3/16 [−3/8]
+4/16 [−4/8]
+5/16 [−5/8]
+6/16 [−6/8]
+7/16 [−7/8]
+8/16 [−1]
Coring gain data (in DNR
mode, the values in brackets
apply)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No gain
+1/16 [−1/8]
+2/16 [−2/8]
+3/16 [−3/8]
+4/16 [−4/8]
+5/16 [−5/8]
+6/16 [−6/8]
+7/16 [−7/8]
+8/16 [−1]
Rev.D | Page 44 of 108
Data Sheet
ADV7342/ADV7343
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
6
5
0
4
0
3
0
2
0
1
0
0
0
Register Setting
Value
0xA4
SD DNR 1
DNR threshold
0
0x00
0
0
0
0
0
1
1
…
1
…
1
…
1
…
1
…
1
…
0
…
62
1
1
1
1
1
1
63
Border area
0
1
Two pixels
Four pixels
Eight pixels
16 pixels
Filter A
Filter B
Filter C
Filter D
Block size control
DNR input select
0
1
0xA5
SD DNR 2
0
0
0
1
0
1
1
0
1
0
1
0
0x00
DNR mode
0
1
DNR mode
DNR sharpness mode
0 pixel offset
One pixel offset
…
DNR block offset
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
14 pixel offset
15 pixel offset
1 x = Logic 0 or Logic 1.
Table 32. Register 0xA6 to Register 0xBB
SR7 to
Bit Number1
Register
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xXX
SR0
Register
Bit Description
7
6
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Setting
A0
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
SD Gamma A 0
SD Gamma A 1
SD Gamma A 2
SD Gamma A 3
SD Gamma A 4
SD Gamma A 5
SD Gamma A 6
SD Gamma A 7
SD Gamma A 8
SD Gamma A 9
SD Gamma B 0
SD Gamma B 1
SD Gamma B 2
SD Gamma B 3
SD Gamma B 4
SD Gamma B 5
SD Gamma B 6
SD Gamma B 7
SD Gamma B 8
SD Gamma B 9
SD brightness detect
SD Gamma Curve A (Point 24)
SD Gamma Curve A (Point 32)
SD Gamma Curve A (Point 48)
SD Gamma Curve A (Point 64)
SD Gamma Curve A (Point 80)
SD Gamma Curve A (Point 96)
SD Gamma Curve A (Point 128)
SD Gamma Curve A (Point 160)
SD Gamma Curve A (Point 192)
SD Gamma Curve A (Point 224)
SD Gamma Curve B (Point 24)
SD Gamma Curve B (Point 32)
SD Gamma Curve B (Point 48)
SD Gamma Curve B (Point 64)
SD Gamma Curve B (Point 80)
SD Gamma Curve B (Point 96)
SD Gamma Curve B (Point 128)
SD Gamma Curve B (Point 160)
SD Gamma Curve B (Point 192)
SD Gamma Curve B (Point 224)
SD brightness value
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Read only
Rev.D | Page 45 of 108
ADV7342/ADV7343
Data Sheet
SR7 to
Bit Number1
Register
Setting
Reset
Value
0x0X
SR0
Register
Bit Description
Field count
Reserved
7
6
5
4
3
2
1
0
0xBB
Field count
x
x
x
Read only
Reserved
0
0
0
Encoder version code
Read only; first
0
0
0
1
encoder version2
Read only; second
encoder version
1 x = Logic 0 or Logic 1.
2
P_HSYNC
P_VSYNC
Considerations section for information about the first encoder revision.
See the HD Interlace External
and
Table 33. Register 0xBD to Register 0xC8
SR7 to
Bit Number1
Reset
Value
0x42
0x81
0x19
0x10
0x70
0x5E
0x12
0x80
0x26
0x4A
0x70
0x80
SR0
Register
Bit Description
7
x
x
x
x
x
x
x
x
x
x
x
x
6
x
x
x
x
x
x
x
x
x
x
x
x
5
x
x
x
x
x
x
x
x
x
x
x
x
4
x
x
x
x
x
x
x
x
x
x
x
x
3
x
x
x
x
x
x
x
x
x
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
Register Setting
Bits [7:0] for a1
Bits [7:0] for a2
Bits [7:0] for a3
Bits [7:0] for a4
Bits [7:0] for b1
Bits [7:0] for b2
Bits [7:0] for b3
Bits [7:0] for b4
Bits [7:0] for c1
Bits [7:0] for c2
Bits [7:0] for c3
Bits [7:0] for c4
0xBD
0xBE
0xBF
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
SD CSC Matrix 1
SD CSC Matrix 2
SD CSC Matrix 3
SD CSC Matrix 4
SD CSC Matrix 5
SD CSC Matrix 6
SD CSC Matrix 7
SD CSC Matrix 8
SD CSC Matrix 9
SD CSC Matrix 10
SD CSC Matrix 11
SD CSC Matrix 12
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
SD CSC matrix coefficient
1 x = Logic 0 or Logic 1.
Table 34. Register 0xC9 to Register 0xCE
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Register Setting
Disabled.
Enabled.
Value
0xC9
Teletext control
Teletext enable
0x00
Teletext request mode
0
1
Line request signal.
Bit request signal.
S_VSYNC
Teletext input pin
select
0
0
1
1
0
1
0
1
P_VSYNC
C0
Reserved
Reserved
0
0
0
0
Reserved
0xCA
Teletext request
control
Teletext request falling
edge position control
0
0
0
0
0
0
0
1
0 clock cycles.
One clock cycle.
…
0x00
…
1
…
1
…
1
…
0
14 clock cycles.
15 clock cycles.
0 clock cycles.
One clock cycle.
…
1
1
1
1
Teletext request rising
edge position control
0
0
0
0
0
0
0
1
…
1
…
1
…
1
…
0
14 clock cycles.
15 clock cycles.
1
1
1
1
0xCB
0xCC
0xCD
0xCE
TTX Line Enable 0 Teletext on odd fields
TTX Line Enable 1 Teletext on odd fields
TTX Line Enable 2 Teletext on even fields
TTX Line Enable 3 Teletext on even fields
22 21 20 19 18 17 16 15 Setting any of these bits
to 1 enables teletext on
0x00
0x00
0x00
0x00
14 13 12 11 10
9
8
7
the line number indicated
by the bit settings.
22 21 20 19 18 17 16 15
14 13 12 11 10
9
8
7
Rev.D | Page 46 of 108
Data Sheet
ADV7342/ADV7343
Table 35. Register 0xE0 to Register 0xF1
SR7 to
Bit Number1
Reset
SR0
Register2
Bit Description
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register Setting
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Bits[7:1] must be 0
1 x = Logic 0 or Logic 1.
2 Macrovision registers are available on the ADV7342 only.
Rev.D | Page 47 of 108
ADV7342/ADV7343
Data Sheet
INPUT CONFIGURATION
The ADV7342/ADV7343 support a number of different input
modes. The desired input mode is selected using Subaddress
0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard
definition only (SD only) on power-up. Table 36 provides an
overview of all possible input configurations. Each input mode
is described in detail in the following sections.
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on Subaddress
0x01, Bit 7), with Pin S0/Y0 being the LSB.
The CrCb pixel data is input on Pin Y7 to Pin Y0 (or Pin C7 to
Pin C0, depending on Subaddress 0x01, Bit 7), with Pin Y0/C0
being the LSB. Embedded EAV/SAV timing codes are not
supported, so an external synchronization is needed in this mode.
STANDARD DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 000
Standard definition (SD) YCrCb data can be input in 4:2:2 format.
Standard definition (SD) RGB data can be input in 4:4:4 format.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
24-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
S_HSYNC
Input synchronization signals are provided on the
S_VSYNC
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to
Pin Y0, and the blue pixel data is input on Pin C7 to Pin C0.
The S0, Y0, and C0 pins are the respective bus LSBs.
and
pins.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on
Subaddress 0x01, Bit 7), with Pin S0/Y0 being the LSB. The
ITU-R BT.601/656 input standard is supported. Embedded
EAV/SAV timing codes are also supported.
Embedded EAV/SAV timing codes are not supported with SD
RGB mode. In addition, master timing mode is not supported
for SD RGB input mode; therefore, external synchronization
must be used.
Table 36. Input Configuration
S
Y
C
1
Input Mode
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
000 SD only
Y/C/S bus swap (Subaddress 0x01[7]) = 0
8-bit YCrCb2
16-bit YCrCb2, 3
YCrCb
Y
CrCb
Y/C/S bus swap (Subaddress 0x01[7]) = 1
8-bit YCrCb2
16-bit YCrCb2, 3
YCrCb
Y
CrCb
B
SD RGB input enable (Subaddress 0x87[7]) = 1
24-bit RGB3
001 ED/HD-SDR only4, 5
16-bit YCrCb
R
G
ED/HD RGB input enable (Subaddress 0x35[1]) = 0
Y
CrCb
Cb
24-bit YCrCb
Cr
R
Y
ED/HD RGB input enable (Subaddress 0x35[1]) = 1
24-bit RGB3
G
B
010 ED/HD-DDR only (8-bit)5
011 SD and ED/HD-SDR (24-bit)5
100 SD and ED/HD-DDR (16-bit)5
111 ED only (54 MHz) (8-bit)5
YCrCb
YCrCb (SD)
YCrCb (SD)
Y (ED/HD)
YCrCb (ED/HD)
YCrCb
CrCb (ED/HD)
1 The input mode is determined by Subaddress 0x01, Bits[6:4].
2 In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 29 for more information.
3 External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4 In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 22 for more information.
5 ED = enhanced definition = 525p and 625p.
Rev.D | Page 48 of 108
Data Sheet
ADV7342/ADV7343
24-Bit 4:4:4 YCrCb Mode
ADV7342/
ADV7343
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0
2
S_VSYNC,
S_HSYNC
MPEG2
DECODER
In 24-bit 4:4:4 YCrCb input mode, the Y pixel data is input on
Pin Y7 to Pin Y0, with Pin Y0 being the LSB.
27MHz
CLKIN_A
The Cr pixel data is input on Pin S7 to Pin S0, with Pin S0 being
the LSB. The Cb pixel data is input on Pin C7 to Pin C0, with
Pin C0 being the LSB.
8
YCrCb
S[7:0] OR Y[7:0]*
*SELECTED BY SUBADDRESS 0x01, BIT 7.
24-Bit 4:4:4 RGB Mode
Figure 51. SD Only Example Application
Subaddress 0x35, Bit 1 = 1
ENHANCED DEFINITION/HIGH DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 001 or 010
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to Pin Y0,
and the blue pixel data is input on Pin C7 to Pin C0. The S0, Y0,
and C0 pins are the respective bus LSBs.
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in either 4:2:2 or 4:4:4 format. If desired, dual data
rate (DDR) pixel data inputs can be employed (4:2:2 format only).
MPEG2
DECODER
ADV7342/
ADV7343
Enhanced definition (ED) or high definition (HD) RGB data
can be input in 4:4:4 format (single data rate only).
CLKIN_
A
YCrCb
8
8
8
Cb
Cr
Y
The clock signal must be provided on the CLKIN_A pin. Input
C[7:0]
S[7:0]
Y[7:0]
P_HSYNC P_VSYNC
synchronization signals are provided on the
P_BLANK
,
,
INTERLACED TO
PROGRESSIVE
and
pins.
P_VSYNC,
P_HSYNC,
P_BLANK
3
16-Bit 4:2:2 YCrCb Mode (SDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
Figure 54. ED/HD Only Example Application
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin Y7 to Pin Y0, with Pin Y0 being the LSB. The CrCb pixel
data is input on Pin C7 to Pin C0, with Pin C0 being the LSB.
SIMULTANEOUS STANDARD DEFINITION AND
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 011 or 100
8-Bit 4:2:2 YCrCb Mode (DDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
The ADV7342/ADV7343 are able to simultaneously process SD
4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz
SD clock signal must be provided on the CLKIN_A pin. The
ED/HD clock signal must be provided on the CLKIN_B pin.
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin Y7 to Pin Y0 on either the rising or falling edge of
CLKIN_A. Pin Y0 is the LSB.
S_HSYNC
SD input synchronization signals are provided on the
The CrCb pixel data is also input on Pin Y7 to Pin Y0 on the
opposite edge of CLKIN_A. Pin Y0 is the LSB. Whether the Y
data is clocked in on the rising or falling edge of CLKIN_A is
determined by Subaddress 0x01, Bits[2:1] (see Figure 52 and
Figure 53).
S_VSYNC
and
pins. ED/HD input synchronization signals are
P_HSYNC P_VSYNC
P_BLANK
pins.
provided on the
,
and
SD 8-Bit 4:2:2 YCrCb and ED/HD-SDR 16-Bit 4:2:2 YCrCb
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin S0,
with Pin S0 being the LSB.
CLKIN_A
The ED/HD 16-bit 4:2:2 Y pixel data is input on Pin Y7 to Pin Y0,
with Pin Y0 being the LSB.
Y[7:0]
3FF
00
00
X
Y
Cb0
Y0
Cr0
Y1
The ED/HD 16-bit 4:2:2 CrCb pixel data is input on Pin C7 to
Pin C0, with Pin C0 being the LSB.
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
SD 8-Bit 4:2:2 YCrCb and ED/HD-DDR 8-Bit 4:2:2 YCrCb
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin S0,
with Pin S0 being the LSB. The ED/HD-DDR 8-bit 4:2:2 Y pixel
data is input on Pin Y7 to Pin Y0 on the rising or falling edge of
CLKIN_B. Pin Y0 is the LSB.
CLKIN_
A
Y[7:0]
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
The ED/HD-DDR 8-bit 4:2:2 CrCb pixel data is also input on
Pin Y7 to Pin Y0 on the opposite edge of CLKIN_B. Pin Y0 is
the LSB.
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Rev.D | Page 49 of 108
ADV7342/ADV7343
Data Sheet
Whether the ED/HD Y data is clocked in on the rising or falling
edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1]
(see the input sequence shown in Figure 52 and Figure 53).
ENHANCED DEFINITION ONLY (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-bit bus at a rate of 54 MHz.
S_VSYNC,
S_HSYNC
2
A 54 MHz clock signal must be provided on the CLKIN_A pin.
SD
DECODER
27MHz
YCrCb
CLKIN_A
S[7:0]
P_HSYNC
Input synchronization signals are provided on the
P_VSYNC P_BLANK
,
8
, and
pins.
ADV7342/
ADV7343
HD
The interleaved pixel data is input on Pin Y7 to Pin Y0, with
Pin Y0 being the LSB.
DECODER
8
CrCb
Y
525p
OR
625p
C[7:0]
8
3
CLKIN_A
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
Y[7:0]
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
74.25MHz
CLKIN_B
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
Figure 55. Simultaneous SD and ED Example Application
MPEG2
DECODER
S_VSYNC,
S_HSYNC
2
8
54MHz
CLKIN_A
YCrCb
SD
27MHz
YCrCb
DECODER
CLKIN_A
S[7:0]
ADV7342/
ADV7343
8
YCrCb
Y[7:0]
INTERLACED TO
PROGRESSIVE
ADV7342/
ADV7343
HD
DECODER
P_VSYNC,
3
8
8
P_HSYNC,
P_BLANK
CrCb
Y
1080i
OR
720p
OR
C[7:0]
Y[7:0]
Figure 58. ED Only (at 54 MHz) Example Application
P_VSYNC,
P_HSYNC,
P_BLANK
3
1035i
74.25MHz
CLKIN_B
Figure 56. Simultaneous SD and HD Example Application
Rev.D | Page 50 of 108
Data Sheet
ADV7342/ADV7343
OUTPUT CONFIGURATION
The ADV7342/ADV7343 support a number of different output configurations. Table 37 to Table 40 list all possible output configurations.
Table 37. SD Only Output Configurations
RGB/YPrPb
SD DAC
Output 2
SD DAC
Output 1
Output Select1
(Subaddress
0x02, Bit 5)
SD Luma/Chroma
(Subaddress (Subaddress Swap (Subaddress
0x82, Bit 2)
0x82, Bit 1)
0x84, Bit 7)
DAC 1 DAC 2
DAC 3
DAC 4 DAC 5
DAC 6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G
G
B
B
R
R
CVBS
CVBS
G
G
G
Luma
Chroma Luma
B
B
Luma
Chroma Luma
B
B
Luma
Chroma Luma
Pb
Pb
Luma
Chroma Luma
Pb
Pb
Chroma
CVBS
CVBS
CVBS
CVBS
G
G
Y
Y
CVBS
CVBS
CVBS
CVBS
Y
Luma
Chroma Luma
B
B
Luma
Chroma Luma
Pb
Pb
Luma
Chroma Luma
Pb
Pb
Chroma
R
R
R
R
Chroma
G
Chroma CVBS
R
R
CVBS
CVBS
CVBS
Y
Y
Y
Y
Pr
Pr
Chroma
Chroma
Pr
Pr
Chroma
Pr
Pr
Luma
Chroma CVBS
Pr
Pr
Y
Chroma Luma CVBS
1 If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.
Table 38. ED/HD Only Output Configurations
RGB/YPrPb Output Select (Subaddress ED/HD Color DAC Swap (Subaddress
0x02, Bit 5)
0x35, Bit 3)
DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6
0
0
1
1
0
1
0
1
G
G
Y
Y
B
R
Pb
Pr
R
B
Pr
Pb
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table 39. Simultaneous SD and ED/HD Output Configurations
ED/HD Color
RGB/YPrPb Output DAC Swap
Select (Subaddress (Subaddress
SD Luma/Chroma
Swap (Subaddress
0x84, Bit 7)
DAC 1
(ED/HD)
DAC 2
(ED/HD)
DAC 3
(ED/HD)
DAC 4
(SD)
DAC 5
(SD)
DAC 6
(SD)
0x02, Bit 5)
0x35, Bit 3)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
G
G
G
G
Y
Y
Y
Y
B
B
R
R
Pb
Pb
Pr
Pr
R
R
B
B
Pr
Pr
Pb
Pb
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
Luma
Chroma
Luma
Chroma
Luma
Chroma
Luma
Chroma
Luma
Chroma
Luma
Chroma
Luma
Chroma
Luma
Chroma
Table 40. ED Only (at 54 MHz) Output Configurations
RGB/YPrPb Output Select (Subaddress ED/HD Color DAC Swap (Subaddress
0x02, Bit 5)
0x35, Bit 3)
DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6
0
0
1
1
0
1
0
1
G
G
Y
Y
B
R
Pb
Pr
R
B
Pr
Pb
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Rev.D | Page 51 of 108
ADV7342/ADV7343
Data Sheet
DESIGN FEATURES
If a polarity other than the default is needed for ED/HD modes,
0x3A Bits [2:0] can be used to invert PHSYNCB, PVSYNCB or
PBLANKB individually, regardless of whether CEA-861-B mode is
enabled. It is not possible to invert S_HSYNC or S_VSYNC.
OUTPUT OVERSAMPLING
The ADV7342/ADV7343 include two on-chip phase-locked
loops (PLLs) that allow for oversampling of SD, ED, and HD
video data. Table 41 shows the various oversampling rates
supported in the ADV7342/ADV7343.
SD and ED/HD Simultaneous Modes
Both PLL 1 and PLL 2 are used in simultaneous modes. The use
of two PLLs allows for independent oversampling of SD and
ED/HD video. PLL 1 is used to oversample SD video data, and
PLL 2 is used to oversample ED/HD video data. In simultaneous
modes, PLL 2 is always enabled. PLL 1 is disabled by default and
can be enabled using Subaddress 0x00, Bit 1 = 0.
SD Only, ED Only, and HD Only Modes
PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is
unused in these modes. PLL 1 is disabled by default and can be
enabled using Subaddress 0x00, Bit 1 = 0.
External Sync Polarity
For SD and ED/HD modes, the ADV7342/ADV7343 parts
typically expect HS and VS to be low during their respective
blanking periods. However, when the CEA861 compliance bit is
enabled (0x39, Bit 5 for ED/HD modes and 0x86, Bit 3 for SD
modes), the part expects the HS or VS to be active low or high,
depending on the input format selected (0x30 Bits [7:3]).
Table 41. Output Oversampling Modes and Rates
Input Mode
Subaddress 0x01 Bits[6:4]
PLL and Oversampling Control
Subaddress 0x00, Bit 1
Oversampling Mode and Rate
SD (2×)
SD (16×)
ED (1×)
ED (8×)
000
000
SD only
SD only
ED only
ED only
HD only
HD only
SD and ED
SD and ED
SD and HD
SD and HD
ED only (at 54 MHz)
ED only (at 54 MHz)
1
0
1
0
1
0
1
0
1
0
1
0
001/010
001/010
001/010
001/010
011/100
011/100
011/100
011/100
111
HD (1×)
HD (4×)
SD (2×) and ED (8×)
SD (16×) and ED (8×)
SD (2×) and HD (4×)
SD (16×) and HD (4×)
ED only (at 54 MHz) (1×)
ED only (at 54 MHz) (8×)
111
Rev.D | Page 52 of 108
Data Sheet
ADV7342/ADV7343
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
HD INTERLACE EXTERNAL P_HSYNC AND
P_VSYNC CONSIDERATIONS
An ED/HD timing reset is achieved by toggling the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) from 0 to 1.
In this state, the horizontal and vertical counters remain reset.
When this bit is set back to 0, the internal counters resume
counting. This timing reset applies to the ED/HD timing
counters only.
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01
or higher, the user should set Subaddress 0x02, Bit 1 to high to
ensure exactly correct timing in HD interlace modes when
P_HSYNC
P_VSYNC
using the
and
synchronization signals. If
this bit is set to low, the first active pixel on each line is masked
and the Pr and Pb outputs are swapped when using the YCrCb
4:2:2 input format. Setting Subaddress 0x02, Bit 1 to low causes
the encoder to behave in the same way as the first version of
silicon (that is, this setting is backward compatible).
SD SUBCARRIER FREQUENCY LOCK
Subcarrier Frequency Lock (SFL) Mode
In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7342/
ADV7343 can be used to lock to an external video source. The
SFL mode allows the ADV7342/ADV7343 to automatically alter
the subcarrier frequency to compensate for line length variations.
When the part is connected to a device such as an ADV7403 video
decoder (see Figure 59) that outputs a digital data stream in the
SFL format, the part automatically changes to the compensated
subcarrier frequency on a line-by-line basis. This digital data
stream is 67 bits wide, and the subcarrier is contained in Bit 0 to
Bit 21. Each bit is two clock cycles long.
If the encoder revision code (Subaddress 0xBB, Bits[7:6] = 00,
the setting of Subaddress 0x02, Bit1 has no effect. In this version
of the encoder, the first active pixel is masked and Pr and Pb
outputs are swapped when using the YCrCb 4:2:2 input format.
To avoid these limitations, use the newer version of silicon or a
different type of synchronization.
These considerations apply only to the HD interlace modes
P_HSYNC
P_VSYNC
with external
and
synchronization
(EAV/SAV mode is not affected and always has exactly correct
timing). There is no negative effect in setting Subaddress 0x02,
Bit 0 to high, and this bit can remain high for all the other video
standards.
ADV7342/ADV7343
CLKIN_A
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
LLC1
SFL
SFL
COMPOSITE
ADV7403
1
VIDEO
P[19:12]
VIDEO
5
Y[7:0]/S[7:0]
DECODER
4 BITS
RESERVED
14 BITS
SEQUENCE
4
H/L TRANSITION
COUNT START
RESET BIT
SUBCARRIER
PHASE
3
BIT
LOW
13
RESERVED
2
PLL INCREMENT
F
128
SC
21
0
0
RTC
6768
14
19
TIME SLOT 01
VALID INVALID
SAMPLE SAMPLE
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
1
2
FOR EXAMPLE, VCR OR CABLE.
F
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7342/ADV7343 F DDS REGISTER IS
SC
SC
F
PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.
SC
3
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET ADV7342/ADV7343 DDS.
SELECTED BY SUBADDRESS 0x01, BIT 7.
4
5
Figure 59. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
Rev.D | Page 53 of 108
ADV7342/ADV7343
Data Sheet
For example, in NTSC mode
Subcarrier Register Value =
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD FSC Register 0: 0x1F
SD FSC Register 1: 0x7C
SD FSC Register 2: 0xF0
SD FSC Register 3: 0x21
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
227.5
1716
×
32 = 569408543
2
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind mode.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
Programming the FSC
The subcarrier frequency register value is divided into four FSC
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte is received by
the ADV7342/ADV7343. The SD input standard autodetection
feature must be disabled.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
VSYNC
incoming
signal and when the analog output matches
VSYNC
the incoming
signal.
This control is available in all slave-timing modes except Slave
Mode 0.
Typical FSC Values
Table 42 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV7342/ADV7343 are able to accept input data that
contains VBI data (such as CGMS, WSS, and VITS) in SD, ED,
and HD modes.
Table 42. Typical FSC Values
Subaddress
Description
NTSC
0x1F
0x7C
0xF0
0x21
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A
0x8C
FSC0
0x8D
FSC1
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
0x8E
FSC2
0x8F
FSC3
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame or on Line 6 to
Line 43 for the ITU-R BT.1358 (625p) standard.
The ADV7342/ADV7343 support an SD noninterlaced mode.
Using this mode, progressive inputs at twice the frame rate of
NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively)
can be input into the ADV7342/ADV7343. The SD noninterlaced
mode can be enabled using Subaddress 0x88, Bit 1.
VBI data can be present on Line 10 to Line 20 for NTSC and on
Line 7 to Line 22 for PAL.
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Embedded EAV/SAV timing codes or external horizontal and
If CGMS is enabled and VBI is disabled, the CGMS data is,
nevertheless, available at the output.
S_HSYNC
vertical synchronization signals provided on the
S_VSYNC
and
pins can be used to synchronize the input pixel data.
SD SUBCARRIER FREQUENCY CONTROL
Subaddress 0x8C to Subaddress 0x8F
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD non-
interlaced mode.
The ADV7342/ADV7343 are able to generate the color subcarrier
used in CVBS and S-Video (Y-C) outputs from the input pixel
clock. Four 8-bit registers are used to set up the subcarrier
frequency. The value of these registers is calculated using
For 240p/59.94 Hz input, the ADV7342/ ADV7343 should be
configured for NTSC operation, and Subaddress 0x88, Bit 1
should be set to 1.
For 288p/50 Hz input, the ADV7342/ADV7343 should be
configured for PAL operation, and Subaddress 0x88, Bit 1
should be set to 1.
Subcarrier Frequency Register =
Number of subcarrier periods in one video line
× 232
Number of 27 MHz clk cycles in one video line
where the sum is rounded to the nearest integer.
Rev.D | Page 54 of 108
Data Sheet
ADV7342/ADV7343
For CVBS and S-Video (Y-C) outputs, the SD subcarrier
SD SQUARE PIXEL MODE
frequency registers must be updated to reflect the input clock
frequency used in SD square pixel mode. The SD input standard
autodetection feature must be disabled in SD square pixel
mode. In square pixel mode, the timing diagrams shown in
Figure 60 and Figure 61 apply.
Subaddress 0x82, Bit 4
The ADV7342/ADV7343 support an SD square pixel mode
(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of
24.5454 MHz is required. The active resolution is 640 × 480. For
PAL operation, an input clock of 29.5 MHz is required. The
active resolution is 768 × 576.
ANALOG
VIDEO
EAV CODE
SAV CODE
C
b
C
r
C
b
8
0
0
0
F
F
F
F
A
B
A
B
A
B
8
0
0
0
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
Y
Y
Y
INPUT PIXELS
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
272 CLOCK
1280 CLOCK
1536 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
344 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 60. Square Pixel Mode EAV/SAV Embedded Timing
HSYNC
FIELD
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Figure 61. Square Pixel Mode Active Pixel Timing
Rev.D | Page 55 of 108
ADV7342/ADV7343
Data Sheet
EXTENDED (SSAF) PrPb FILTER MODE
FILTERS
0
–10
–20
–30
–40
–50
–60
Table 43 shows an overview of the programmable filters
available on the ADV7342/ADV7343.
Table 43. Selectable Filters
Filter
Subaddress
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x82
0x33
0x33
0x33
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
0
1
2
3
4
5
6
FREQUENCY (MHz)
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD PrPb SSAF
ED/HD Chroma Input
ED/HD Sinc Compensation Filter
ED/HD Chroma SSAF
Figure 62. PrPb SSAF Filter
If this filter is disabled, one of the chroma filters shown in
Table 44 can be selected and used for the CVBS or luma/
chroma signal.
Table 44. Internal Filter Specifications
Pass-Band
Filter
Ripple (dB)1
0.16
3 dB Bandwidth (MHz)2
Luma LPF NTSC
Luma LPF PAL
Luma Notch NTSC
Luma Notch PAL
Luma SSAF
4.24
4.81
0.1
0.09
0.1
0.04
2.3/4.9/6.6
3.1/5.6/6.4
6.45
SD Internal Filter Response
Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0
Luma CIF
0.127
3.02
Luma QCIF
Monotonic
Monotonic
Monotonic
0.09
1.5
0.65
1
1.395
2.2
3.2
0.65
0.5
The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response with or without gain boost
attenuation, a CIF response, and a QCIF response. The PrPb
filter supports several different frequency responses, including
six low-pass responses, a CIF response, and a QCIF response, as
shown in Figure 38 and Figure 39.
Chroma 0.65 MHz
Chroma 1.0 MHz
Chroma 1.3 MHz
Chroma 2.0 MHz
Chroma 3.0 MHz
Chroma CIF
0.048
Monotonic
Monotonic
Monotonic
Chroma QCIF
If SD SSAF gain is enabled (Subaddress 0x87, Bit 4), there are 13
response options in the −4 dB to +4 dB range. The desired response
can be programmed using Subaddress 0xA2. The variation in
frequency responses is shown in Figure 35 to Figure 37.
1 Pass-band ripple is the maximum fluctuation from the 0 dB response in the
pass band, measured in decibels. The pass band is defined to have 0 Hz to fc
(Hz) frequency limits for a low-pass filter and 0 Hz to f1 (Hz) and f2 (Hz) to
infinity for a notch filter, where fc, f1, and f2 are the −3 dB points.
2 3 dB bandwidth refers to the −3 dB cutoff frequency.
In addition to the chroma filters listed in Table 43, the ADV7342/
ADV7343 contain an SSAF filter that is specifically designed for
the color difference component outputs, Pr and Pb. This filter
has a cutoff frequency of ~2.7 MHz and a gain of –40 dB at 3.8
MHz (see Figure 62). This filter can be controlled with Subaddress
0x82, Bit 0.
Rev.D | Page 56 of 108
Data Sheet
ADV7342/ADV7343
Table 45. Sample Color Values for EIA 770.2/EIA 770.3
ED/HD Output Standard Selection
ED/HD Sinc Compensation Filter Response
Subaddress 0x33, Bit 3
Sample Color Y Value
Cr Value
Cb Value
The ADV7342/ADV7343 include a filter designed to counter
the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while
operating in ED/HD mode. This filter is enabled by default. It
can be disabled using Subaddress 0x33, Bit 3. The benefit of the
filter is illustrated in Figure 63 and Figure 64.
0.5
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
235 (0xEB)
128 (0x80) 128 (0x80)
128 (0x80) 128 (0x80)
16
81
(0x10)
(0x51)
240 (0xF0)
90
(0x5A)
(0x36)
145 (0x91)
41 (0x29)
34
(0x22) 54
110 (0x6E)
240 (0xF0)
(0x10)
(0x10) 166 (0xA6)
106 (0x6A) 222 (0xDE) 202 (0xCA)
210 (0xD2) 146 (0x92) 16
170 (0xAA) 16
0.4
0.3
0.2
COLOR SPACE CONVERSION MATRIX
0.1
Subaddress 0x03 to Subaddress 0x09
0
The internal color space conversion (CSC) matrix automatically
performs all color space conversions based on the input mode
programmed in the mode select register (Subaddress 0x01,
Bits[6:4]). Table 46 and Table 47 show the options available in
this matrix.
–0.1
–0.2
–0.3
–0.4
–0.5
An SD color space conversion from RGB-in to YPrPb-out is
possible. An ED/HD color space conversion from RGB-in to
YPrPb-out is not possible.
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 63. ED/HD Sinc Compensation Filter Enabled
0.5
0.4
Table 46. SD Color Space Conversion Options
YPrPb/RGB Out
(Subaddress
0x02, Bit 5)
RGB In/YCrCb In
(Subaddress
0x87, Bit 7)
0.3
Input
YCrCb
YCrCb
RGB
Output1
YPrPb
RGB
YPrPb
RGB
0.2
1
0
1
0
0
0
1
1
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
RGB
1 CVBS/YC outputs are available for all CSC combinations.
Table 47. ED/HD Color Space Conversion Options
YPrPb/RGB Out
(Subaddress
0x02, Bit 5)
RGB In/YCrCb In
(Subaddress
0x35, Bit 1)
0
5
10
15
20
25
30
Input
YCrCb
YCrCb
RGB
Output
YPrPb
RGB
FREQUENCY (MHz)
1
0
0
0
0
1
Figure 64. ED/HD Sinc Compensation Filter Disabled
ED/HD TEST PATTERN COLOR CONTROLS
RGB
Subaddress 0x36 to Subaddress 0x38
SD Manual CSC Matrix Adjust Feature
Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38
are used to program the output color of the internal ED/HD
test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it
be the lines of the crosshatch pattern or the uniform field test
pattern. They are not functional as color controls for external
pixel data input.
The SD manual CSC matrix adjust feature provides custom
coefficient manipulation for RGB to YPbPr conversion (for
YPbPr to RGB conversion, this matrix adjustment is not
available).
Normally, there is no need to modify the SD matrix coefficients
because the CSC matrix automatically performs the color space
conversion based on the output color space selected (see Table 46).
Note that Bit 7 in Subaddress 0x87 must be set to enable RGB
input and, therefore, use the CSC manual adjustment.
The values for the luma (Y) and the color difference (Cr and
Cb) signals used to obtain white, black, and saturated primary
and complementary colors conform to the ITU-R BT.601-4
standard.
Table 45 shows sample color values that can be programmed
into the color registers when the output standard selection is set
to EIA 770.2/EIA 770.3 (Subaddress 0x30, Bits[1:0] = 00).
Rev.D | Page 57 of 108
ADV7342/ADV7343
Data Sheet
The SD CSC matrix scalar uses the following equations:
Y = (a1 × R) + (a2 × G) + (a3 × B) + a4
Table 49. ED/HD Manual CSC Matrix Default Values
Subaddress
Default
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C
Pr = (b1 × R) + (b2 × G) + (b3 × B) + b4
Pb = (c1 × R) + (c2 × G) + (c3 × B) + c4
The coefficients and their default values and register locations
are shown in Table 48.
Table 48. SD Manual CSC Matrix Default Values
Coefficient
Subaddress
0xBD
0xBE
0xBF
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
Default
0x42
0x81
0x19
0x10
0x70
0x5E
0x12
0x80
0x26
0x4A
0x70
0x80
When the ED/HD manual CSC matrix adjust feature is enabled,
the default coefficient values in Subaddress 0x03 to Subaddress
0x09 are correct for the HD color space only. The color
components are converted according to the following 1080i and
720p standards (SMPTE 274M, SMPTE 296M):
a1
a2
a3
a4
b1
b2
b3
b4
c1
c2
c3
c4
R = Y + 1.575Pr
G = Y − 0.468Pr − 0.187Pb
B = Y + 1.855Pb
The conversion coefficients should be multiplied by 315 before
being written to the ED/HD CSC matrix registers This is
reflected in the default values for GY = 0x13B, GU = 0x03B,
GV = 0x093, BU = 0x248, and RV = 0x1F0.
ED/HD Manual CSC Matrix Adjust Feature
If the ED/HD manual CSC matrix adjust feature is enabled and
another input standard (such as ED) is used, the scale values for
GY, GU, GV, BU, and RV must be adjusted according to this
input standard color space. The user should consider that the
color component conversion may use different scale values.
The ED/HD manual CSC matrix adjust feature provides custom
coefficient manipulation for color space conversions and is used
in ED and HD modes only. The ED/HD manual CSC matrix
adjust feature can be enabled using Subaddress 0x02, Bit 3.
Normally, there is no need to enable this feature because the CSC
matrix automatically performs the color space conversion based
on the input mode chosen (ED or HD) and the input and output
color spaces selected (see Table 47). For this reason, the ED/HD
manual CSC matrix adjust feature is disabled by default.
For example, SMPTE 293M uses the following conversion:
R = Y + 1.402Pr
G = Y – 0.714Pr – 0.344Pb
B = Y + 1.773Pb
If RGB output is selected, the ED/HD CSC matrix scalar uses
the following equations:
The programmable CSC matrix is used for external ED/HD
pixel data and is not functional when internal test patterns are
enabled.
R = GY × Y + RV × Pr
Programming the CSC Matrix
G = GY × Y − (GU × Pb) − (GV × Pr)
B = GY × Y + BU × Pb
If custom manipulation of the ED/HD CSC matrix coefficients
is required for a YCrCb-to-RGB color space conversion, use the
following procedure:
Note that subtractions are implemented in hardware.
If YPrPb output is selected, the following equations are used:
Y = GY × Y
1. Enable the ED/HD manual CSC matrix adjust feature
(Subaddress 0x02, Bit 3).
2. Set the output to RGB (Subaddress 0x02, Bit 5).
3. Disable sync on PrPb (Subaddress 0x35, Bit 2).
4. Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).
Pr = RV × Pr
Pb = BU × Pb
where:
The GY value controls the green signal output level, the BU
value controls the blue signal output level, and the RV value
controls the red signal output level.
GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0].
GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6].
GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4].
BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2].
RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].
On power-up, the CSC matrix is programmed with the default
values shown in Table 49.
Rev.D | Page 58 of 108
Data Sheet
ADV7342/ADV7343
For example, to adjust the hue by +4°, write 0x97 to the hue
adjust control register.
SD LUMA AND COLOR SCALE CONTROL
Subaddress 0x9C to Subaddress 0x9F
4
When enabled, the SD luma and color scale control feature can
be used to scale the SD Y, Cb, and Cr output levels. This feature
can be enabled using Subaddress 0x87, Bit 0. This feature affects
all SD output signals, that is, CVBS, Y-C, YPrPb, and RGB.
+ 128 ≈151d = 0x97
0.17578125
where the sum is rounded to the nearest integer.
To adjust the hue by −4°, write 0x69 to the hue adjust control
register.
When enabled, three 10-bit registers (SD Y Scale, SD Cb scale,
and SD Cr scale) control the scaling of the SD Y, Cb, and Cr
output levels. The SD Y scale register contains the scaling factor
used to scale the Y level from 0.0 to 1.5 times its initial level.
The SD Cb scale and SD Cr scale registers contain the scaling
factors to scale the Cb and Cr levels from 0.0 to 2.0 times their
initial levels, respectively.
−4
+ 128 ≈105d = 0x69
0.17578125
where the sum is rounded to the nearest integer.
SD BRIGHTNESS DETECT
Subaddress 0xBA
The values to be written to these 10-bit registers are calculated
using the following equation:
The ADV7342/ADV7343 allow monitoring of the brightness
level of the incoming video data. This feature is used to monitor
the average brightness of the incoming Y signal on a field-by-
field basis. The information is read from the I2C and, based on
this information, the color saturation, contrast, and brightness
controls can be adjusted (for example, to compensate for very
dark pictures).
Y, Cb, or Cr Scale Value = Scale Factor × 512
For example, if Scale Factor = 1.3
Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6
Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)
Y, Cb, or Cr Scale Value = 1010 0110 10b
The luma data is monitored in the active video area only. The
average brightness I2C register is updated on the falling edge of
Subaddress 0x9C, SD scale LSB register = 0x2A
Subaddress 0x9D, SD Y scale register = 0xA6
Subaddress 0x9E, SD Cb scale register = 0xA6
Subaddress 0x9F, SD Cr scale register = 0xA6
every
signal. The SD brightness detect register (Subad-
VSYNC
dress 0xBA) is a read-only register.
SD BRIGHTNESS CONTROL
Subaddress 0xA1, Bits[6:0]
It is recommended that the SD luma scale saturation feature
(Subaddress 0x87, Bit 1) be enabled when scaling the Y output
level to avoid excessive Y output levels.
When this feature is enabled, the SD brightness/WSS control
register (Subaddress 0xA1) is used to control brightness by
adding a programmable setup level onto the scaled Y data. This
feature can be enabled using Subaddress 0x87, Bit 3.
SD HUE ADJUST CONTROL
Subaddress 0xA0
When enabled, the SD hue adjust control register (Subaddress
0xA0) is used to adjust the hue on the SD composite and chroma
outputs. This feature can be enabled using Subaddress 0x87, Bit 2.
For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE.
For NTSC without pedestal and for PAL, the setup can vary
from −7.5 IRE to +15 IRE.
Subaddress 0xA0 contains the bits required to vary the hue of
the video data, that is, the variance in phase of the subcarrier
during active video with respect to the phase of the subcarrier
during the color burst. The ADV7342/ADV7343 provide a range
of 22.5° in increments of 0.17578125°. For normal operation
(zero adjustment), this register is set to 0x80. Value 0xFF and
Value 0x00 represent the upper and lower limits, respectively, of
the attainable adjustment in NTSC mode. Value 0xFF and Value
0x01 represent the upper and lower limits, respectively, of the
attainable adjustment in PAL mode.
The SD brightness control register is an 8-bit register. The seven
LSBs of this 8-bit register are used to control the brightness
level, which can be a positive or negative value.
For example, to add a +20 IRE brightness level to an NTSC
signal with pedestal, write 0x28 to Subaddress 0xA1.
0 × (SD Brightness Value) =
0 × (IRE Value × 2.015631) =
0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28
The hue adjust value is calculated using the following equation:
Hue Adjust (°) = 0.17578125° (HCRd − 128)
where HCRd is the hue adjust control register (decimal).
Rev.D | Page 59 of 108
ADV7342/ADV7343
Data Sheet
To add a –7 IRE brightness level to a PAL signal, write 0x72 to
Subaddress 0xA1.
SD INPUT STANDARD AUTODETECTION
Subaddress 0x87, Bit 5
0 × (SD Brightness Value) =
The ADV7342/ADV7343 include an SD input standard
autodetect feature. This SD feature can be enabled by setting
Subaddress 0x87, Bits[5:1].
0 × (IRE Value × 2.075631) =
0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b
0001110b into twos complement = 1110010b = 0x72
When enabled, the ADV7342/ADV7343 can automatically
identify an NTSC or a PAL B/D/G/H/I input stream. The
ADV7342/ADV7343 automatically update the subcarrier
frequency registers with the appropriate value for the identified
standard. The ADV7342/ADV7343 are also configured to
correctly encode the identified standard.
Table 50. Sample Brightness Control Values1
Setup Level
(NTSC) with
Pedestal
Setup Level
(NTSC) Without Level
Pedestal
15 IRE
7.5 IRE
0 IRE
Setup
Brightness
Control Value
(PAL)
22.5 IRE
15 IRE
7.5 IRE
0 IRE
15 IRE
7.5 IRE
0 IRE
0x1E
0x0F
0x00
0x71
The SD standard bits (Subaddress 0x80, Bits[1:0]) and the
subcarrier frequency registers are not updated to reflect the
identified standard. All registers retain their default or user-
defined values.
−7.5 IRE
−7.5 IRE
1 Values in the range of 0x3F to 0x44 may result in an invalid output signal.
NTSC WITHOUT PEDESTAL
100 IRE
+7.5 IRE
–7.5 IRE
0 IRE
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
NO SETUP
VALUE ADDED
Figure 65. Examples of Brightness Control Values
Rev.D | Page 60 of 108
Data Sheet
ADV7342/ADV7343
In Case B of Figure 66, the video output signal is reduced. The
absolute level of the sync tip and the blanking level decrease
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD;
Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double
buffering improves overall performance because modifications
to register settings are not made during active video but take
effect prior to the start of the active video on the next field.
The range of this feature is specified for 7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
Double buffering can be activated on the following ED/HD
registers using Subaddress 0x33, Bit 7: the ED/HD Gamma A
and Gamma B curves and ED/HD CGMS registers.
The reset value of the control registers is 0x00; that is, nominal
DAC current is output. Table 51 shows how the output current
of the DACs varies for a nominal 4.33 mA output current.
Double buffering can be activated on the following SD registers
using Subaddress 0x88, Bit 2: the SD Gamma A and Gamma B
curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD
closed captioning, and SD Macrovision Bits[5:0] (Subaddress
0xE0, Bits[5:0]) registers.
Table 51. DAC Gain Control
Subaddress 0x0A
or Subaddress
0x0B
DAC
Current (mA) % Gain
Note
0100 0000 (0x40)
0011 1111 (0x3F)
0011 1110 (0x3E)
...
4.658
4.653
4.648
...
7.5000%
7.3820%
7.3640%
...
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0A to Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 66.
...
...
...
0000 0010 (0x02)
0000 0001 (0x01)
0000 0000 (0x00)
4.43
4.38
4.33
0.0360%
0.0180%
0.0000%
DAC 4 to DAC 6 are controlled by Register 0x0A.
DAC 1 to DAC 3 are controlled by Register 0x0B.
CASE A
Reset value,
nominal
1111 1111 (0xFF)
1111 1110 (0xFE)
...
4.25
4.23
...
−0.0180%
−0.0360%
...
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0A, 0x0B
700mV
...
...
...
1100 0010 (0xC2)
1100 0001 (0xC1)
1100 0000 (0xC0)
4.018
4.013
4.008
−7.3640%
−7.3820%
−7.5000%
300mV
GAMMA CORRECTION
Subaddress 0x44 to Subaddress 0x57 for ED/HD;
Subaddress 0xA6 to Subaddress 0xB9 for SD
NEGATIVE GAIN PROGRAMMED IN
CASE B
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0A, 0x0B
700mV
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and output brightness
level (as perceived on a CRT). It can also be applied wherever
nonlinear processing is used.
Gamma correction uses the function
SignalOUT = (SignalIN)γ
300mV
where γ is the gamma correction factor.
Gamma correction is available for SD and ED/HD video. For
both variations, there are twenty 8-bit registers. They are used
to program the Gamma Correction Curve A and Gamma
Correction Curve B.
Figure 66. Programmable DAC Gain—Positive and Negative Gain
In Case A of Figure 66, the video output signal is gained. The
absolute level of the sync tip and the blanking level increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
ED/HD gamma correction is enabled using Subaddress 0x35,
Bit 5. ED/HD Gamma Correction Curve A is programmed at
Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma
Correction Curve B is programmed at Subaddress 0x4E to
Subaddress 0x57.
Rev.D | Page 61 of 108
ADV7342/ADV7343
Data Sheet
SD gamma correction is enabled using Subaddress 0x88, Bit 6.
SD Gamma Correction Curve A is programmed at Subaddress
0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B
is programmed at Subaddress 0xB0 to Subaddress 0xB9.
To program the gamma correction registers, calculate the
10 programmable curve values using the following formula:
γ
n −16
240 −16
γn =
×(240
−
16)
+
16
Gamma correction is performed on the luma data only. The
user can choose one of two correction curves, Curve A or
Curve B. Only one of these curves can be used at a time. For
ED/HD gamma correction, curve selection is controlled using
Subaddress 0x35, Bit 4. For SD gamma correction, curve
selection is controlled using Subaddress 0x88, Bit 7.
where:
γn is the value to be written into the gamma correction register
for point n on the gamma correction curve.
n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.
γ is the gamma correction factor.
For example, setting γ = 0.5 for all programmable curve data
points results in the following yn values:
The shape of the gamma correction curve is controlled by
defining the curve response at 10 different locations along the
curve. By altering the response at these locations, the shape of
the gamma correction curve can be modified. Between these
points, linear interpolation is used to generate intermediate
values. Considering that the curve has a total length of 256
points, the 10 programmable locations are at the following
points: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. The
following locations are fixed and cannot be changed: 0, 16, 240,
and 255.
y
y
y
y
y
y
y
y
y
y
24 = [(8/224)0.5 × 224] + 16 = 58
32 = [(16/224)0.5 × 224] + 16 = 76
48 = [(32/224)0.5 × 224] + 16 = 101
64 = [(48/224)0.5 × 224] + 16 = 120
80 = [(64/224)0.5 × 224] + 16 = 136
96 = [(80/224)0.5 × 224] + 16 = 150
128 = [(112/224)0.5 × 224] + 16 = 174
160 = [(144/224)0.5 × 224] + 16 = 195
192 = [(176/224)0.5 × 224] + 16 = 214
224 = [(208/224)0.5 × 224] + 16 = 232
From the curve locations, 16 to 240, the values at the
programmable locations and, therefore, the response of the
gamma correction curve, should be calculated to produce the
following result:
γ
x
DESIRED = (xINPUT
)
where the sum of each equation is rounded to the nearest integer.
where:
The gamma curves in Figure 67 and Figure 68 are examples only;
any user-defined curve in the range from 16 to 240 is acceptable.
x
x
DESIRED is the desired gamma corrected output.
INPUT is the linear input signal.
γ is the gamma correction factor.
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR
300
250
200
150
100
50
VARIOUS GAMMA VALUES
300
250
SIGNAL OUTPUT
0.3
0.5
200
0.5
150
1.5
100
SIGNAL INPUT
1.8
50
0
0
50
100
150
LOCATION
200
250
0
0
50
100
150
LOCATION
200
250
Figure 67. Signal Input (Ramp) and Signal Output for Gamma 0.5
Figure 68. Signal Input (Ramp) and Selectable Output Curves
Rev.D | Page 62 of 108
Data Sheet
ADV7342/ADV7343
The derivative of the incoming signal is compared to the three
programmable threshold values: ED/HD adaptive filter
(Threshold A, Threshold B, and Threshold C) registers
(Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D,
respectively). The recommended threshold range is 16 to 235,
although any value in the range of 0 to 255 can be used.
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
CONTROLS
Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D
There are three filter modes available on the ADV7342/ADV7343:
a sharpness filter mode and two adaptive filter modes.
ED/HD Sharpness Filter Mode
The edges can then be attenuated with the settings in the
ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers
(Subaddress 0x58, Subaddress 0x59, and Subaddress 0x5A,
respectively), and the ED/HD sharpness filter gain register
(Subaddress 0x40).
To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 69, the ED/HD sharpness filter must be
enabled (Subaddress 0x31, Bit 7) and the ED/HD adaptive filter
must be disabled (Subaddress 0x35, Bit 7).
To select one of the 256 individual responses, the corresponding
gain values, which range from –8 to +7 for each filter, must be
programmed into the ED/HD sharpness filter gain register at
Subaddress 0x40.
There are two adaptive filter modes available. The mode
is selected using the ED/HD adaptive filter mode control
(Subaddress 0x35, Bit 6) as follows:
•
Mode A is used when the ED/HD adaptive filter mode
control is set to 0. In this case, Filter B (LPF) is used in the
adaptive filter block. In addition, only the programmed
values for Gain B in the ED/HD sharpness filter gain
register and ED/HD adaptive filter (Gain 1, Gain 2, and
Gain 3) registers are applied when needed. The Gain A
values are fixed and cannot be changed.
ED/HD Adaptive Filter Mode
The ED/HD adaptive filter (Threshold A, Threshold B, and
Threshold C) registers, the ED/HD adaptive filter (Gain 1, Gain
2, and Gain 3) registers, and the ED/HD sharpness filter gain
register are used in adaptive filter mode. To activate the
adaptive filter control, the ED/HD sharpness filter and the
ED/HD adaptive filter must be enabled (Subaddress 0x31, Bit 7,
and Subaddress 0x35, Bit 7, respectively).
•
Mode B is used when ED/HD adaptive filter mode control
is set to 1. In this mode, a cascade of Filter A and Filter B is
used. Both settings for Gain A and Gain B in the ED/HD
sharpness filter gain register and ED/HD adaptive filter
(Gain 1, Gain 2, and Gain 3) registers become active when
needed.
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK
1.5
1.5
1.4
1.6
1.5
1.4
1.4
1.3
1.2
1.1
1.0
1.3
1.2
1.1
1.0
INPUT
SIGNAL
STEP
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.9
0.8
0.7
0.6
0.5
0
2
4
6
8
10
12
FREQUENCY (MHz)
FILTER A RESPONSE (Gain Ka)
FREQUENCY (MHz)
FILTER B RESPONSE (Gain Kb)
FREQUENCY (MHz)
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 69. ED/HD Sharpness and Adaptive Filter Control Block
Rev.D | Page 63 of 108
ADV7342/ADV7343
Data Sheet
d
a
b
R2
R4
1
e
R1
c
f
1
R2
CH1 500mV
REF A
M 4.00µs
1 9.99978ms
CH1
ALL FIELDS
CH1 500mV
M 4.00µs
1 9.99978ms
CH1
ALL FIELDS
500mV 4.00µs
REF A
500mV 4.00µs
Figure 70. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES
Sharpness Filter Application
Adaptive Filter Control Application
The register settings in Table 53 are used to obtain the results
shown in Figure 72, that is, to remove the ringing on the input
Y signal, as shown in Figure 71. Input data is generated by an
external signal source.
The ED/HD sharpness filter can be used to enhance or
attenuate the Y video output signal. The register settings in
Table 52 are used to achieve the results shown in Figure 70.
Input data was generated by an external signal source.
Table 53. Register Settings for Figure 72
Subaddress
Register Setting
Table 52. ED/HD Sharpness Control Settings for Figure 70
0x00
0x01
0xFC
0x38
Subaddress
Register Setting
Reference1
0x02
0x20
0x00
0xFC
0x30
0x00
0x01
0x10
0x31
0x81
0x02
0x20
0x35
0x80
0x30
0x00
0x40
0x00
0x31
0x81
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0xAC
0x9A
0x88
0x28
0x3F
0x64
0x40
0x40
0x40
0x40
0x40
0x40
0x00
0x08
0x04
0x40
0x80
0x22
a
b
c
d
e
f
1 See Figure 70.
Figure 72. Output Signal from ED/HD Adaptive Filter (Mode A)
Figure 71. Input Signal to ED/HD Adaptive Filter
Rev.D | Page 64 of 108
Data Sheet
ADV7342/ADV7343
When the adaptive filter mode is changed to Mode B
(Subaddress 0x35, Bit 6), the output shown in Figure 73
can be obtained.
DNR MODE
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
CORING GAIN DATA
CORING GAIN BORDER
NOISE
SIGNAL PATH
INPUT FILTER
BLOCK
FILTER
SUBTRACT
OUTPUT
SIGNAL IN
Y DATA
INPUT
< THRESHOLD?
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
–
FILTER OUTPUT
> THRESHOLD
+
DNR OUT
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
Figure 73. Output Signal from ED/HD Adaptive Filter (Mode B)
BLOCK OFFSET
SD DIGITAL NOISE REDUCTION
GAIN
Subaddress 0xA3 to Subaddress 0xA5
CORING GAIN DATA
CORING GAIN BORDER
NOISE
SIGNAL PATH
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude compo-
nents of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available: DNR mode and DNR sharpness mode.
INPUT FILTER
BLOCK
FILTER
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
OUTPUT
Y DATA
INPUT
> THRESHOLD?
+
FILTER OUTPUT
< THRESHOLD
+
In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (coring gain border, coring gain data) of this noise
signal is subtracted from the original signal. In DNR sharpness
mode, if the absolute value of the filter output is less than the
programmed threshold, it is assumed to be noise. Otherwise, if
the level exceeds the threshold, now identified as a valid signal,
a fraction of the signal (coring gain border, coring gain data) is
added to the original signal to boost high frequency components
and sharpen the video image.
DNR OUT
MAIN SIGNAL PATH
Figure 74. SD DNR Block Diagram
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
These four bits are assigned to the gain factor applied to border
areas. In DNR mode, the range of gain values is 0 to 1 in
increments of 1/8. This factor is applied to the DNR filter
output that lies below the set threshold range. The result is then
subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels ×
16 pixels for MPEG1 systems (block size control). DNR can be
applied to the resulting block transition areas that are known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block. In DNR mode, the range of
gain values is 0 to 1 in increments of 1/8. This factor is applied
to the DNR filter output that lies below the set threshold range.
The result is then subtracted from the original signal.
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
Rev.D | Page 65 of 108
ADV7342/ADV7343
Data Sheet
APPLY DATA
APPLY BORDER
DNR Input Select Control—Subaddress 0xA5, Bits[2:0]
CORING GAIN CORING GAIN
Three bits are assigned to select the filter, which is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that is DNR processed. Figure 77
shows the filter responses selectable with this control.
O X X X X X X O O X X X X X X O
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
O X X X X X X O O X X X X X X O
DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O
DNR Mode Control—Subaddress 0xA5, Bit 3
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
Figure 75. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal because this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using the extended SSAF filter).
720 × 485 PIXELS
TWO-PIXEL
BORDER
(NTSC)
DATA
DNR Block Offset Control—Subaddress 0xA5, Bits[7:4]
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
8 × 8 PIXEL BLOCK
8 × 8 PIXEL BLOCK
Figure 76. SD DNR Border Area
SD ACTIVE VIDEO EDGE CONTROL
Subaddress 0x82, Bit 7
Block Size Control—Subaddress 0xA4, Bit 7
This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines an
8 pixel × 8 pixel data block, where one pixel refers to two clock
cycles at 27 MHz.
The ADV7342/ADV7343 are able to control fast rising and
falling signals at the start and end of active video in order to
minimize ringing.
When the active video edge control feature is enabled
(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last
three pixels of the active video on the luma channel are scaled
so that maximum transitions on these pixels are not possible.
1.0
FILTER D
0.8
At the start of active video, the first three pixels are multiplied by
1/8, 1/2, and 7/8, respectively. Approaching the end of active video,
the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively.
All other active video pixels pass through unprocessed.
FILTER C
0.6
0.4
0.2
0
FILTER B
FILTER A
1
2
3
0
4
5
6
FREQUENCY (MHz)
Figure 77. SD DNR Input Select
Rev.D | Page 66 of 108
Data Sheet
ADV7342/ADV7343
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
0 IRE
100 IRE
87.5 IRE
50 IRE
12.5 IRE
0 IRE
Figure 78. Example of Active Video Edge Functionality
VOLTS
0.5
IRE:FLT
100
50
0
0
F2
L135
–50
2
0
4
6
8
10
12
Figure 79. Example of Video Output with Subaddress 0x82, Bit 7 = 0
VOLTS
IRE:FLT
100
50
0
0.5
0
F2
L135
–50
–2
0
2
4
6
8
10
12
Figure 80. Example of Video Output with Subaddress 0x82, Bit 7 = 1
Rev.D | Page 67 of 108
ADV7342/ADV7343
Data Sheet
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input
S_HSYNC S_VSYNC P_HSYNC P_VSYNC
P_BLANK
pixel data or external synchronization signals provided on the
,
,
,
, and
pins (see
S_HSYNC
S_VSYNC
and
Table 54). It is also possible to output synchronization signals on the
pins (see Table 55 to Table 57).
Table 54. Timing Synchronization Signal Input Options
Signal
Pin
Condition
HSYNC
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0])1
SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0])1
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
SD
SD
In
VSYNC
/FIELD In
HSYNC
ED/HD
ED/HD
ED/HD
In
VSYNC
BLANK
/FIELD In
In
1 SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 55. Timing Synchronization Signal Output Options
Signal
Pin
Condition
HSYNC
S_HSYNC
S_VSYNC
S_HSYNC
S_VSYNC
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
SD
SD
Out
VSYNC
/FIELD Out
HSYNC
ED/HD
ED/HD
Out
VSYNC
/FIELD Out
1 ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
1, 2
S_HSYNC
Table 56.
Output Control
ED/HD HSYNC
Control
(Subaddress
ED/HD Input Sync
Format
(Subaddress
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
SD Sync
Output Enable
(Subaddress
0x02, Bit 6)
Signal on S_HSYNC Pin
0x30, Bit 2)
0x34, Bit 1)
Duration
X
X
0
1
X
X
0
0
0
0
1
1
0
1
X
X
Tristate
N/A
HSYNC
Pipelined SD
See the SD Timing section.
HSYNC
HSYNC
HSYNC
timing.
Pipelined ED/HD
As per
Same as line blanking
interval.
Pipelined ED/HD
AV Code H bit
based on
based on
X
1
1
X
HSYNC
Same as embedded
Pipelined ED/HD
HSYNC
.
horizontal counter
1
HSYNC
HSYNC
HSYNC
pulse is aligned with the falling edge of the embedded in the output video.
In all ED/HD standards where there is an
2 X = don’t care.
output, the start of the
Rev.D | Page 68 of 108
Data Sheet
ADV7342/ADV7343
1, 2
S_VSYNC
Table 57.
Output Control
ED/HD VSYNC
Control
(Subaddress
0x34, Bit 2)
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
SD Sync Output
Enable
(Subaddress 0x02,
Bit 6)
Signal on S_VSYNC Pin
Video Standard
Duration
X
X
X
X
0
0
0
1
X
Tristate
N/A
Interlaced
VSYNC
/field
Pipelined SD
See the SD Timing
section
0
1
1
0
0
0
1
1
1
x
X
VSYNC
VSYNC
As per or
field signal timing
Field
Pipelined ED/HD
or field signal
X
X
All HD interlaced
standards
All ED/HD
progressive
standards
Pipelined field signal
based on AV Code F bit
VSYNC
Vertical blanking
interval
Pipelined
based
on AV Code V bit
X
X
1
1
1
1
X
X
All ED/HD
standards
except 525p
VSYNC
Aligned with
serration lines
Pipelined ED/HD
based on the
vertical counter
525p
VSYNC
based on the vertical
counter
Vertical blanking
interval
Pipelined ED/HD
1
VSYNC
VSYNC
VSYNC
pulse is aligned with the falling edge of the embedded in the output video.
In all ED/HD standards where there is a
2 X = don’t care.
output, the start of the
DAC 1 is monitored; that is, the luma or green output is
monitored.
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
Once per frame, the ADV7342/ADV7343 monitor DAC 1
and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,
respectively. If a cable is detected on one of the DACs, the
relevant bit is set to 0. If not, the bit is set to 1.
For power-sensitive applications, the ADV7342/ADV7343
support an Analog Devices proprietary low power mode of
operation on DAC 1, DAC 2, and DAC 3. To use this low power
mode, these DACs must be operating in full-drive mode (RSET1
= 510 Ω, RL = 37.5 Ω). Low power mode is not available in low-
drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode can
be independently enabled or disabled on DAC 1, DAC 2, and
DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is
disabled by default on each DAC.
DAC AUTOPOWER-DOWN
Subaddress 0x10, Bit 4
For power-sensitive applications, a DAC autopower-down
feature can be enabled using Subaddress 0x10, Bit 4. This feature
is available only when the cable detection feature is enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame. If they are unconnected,
some or all of the DACs automatically power down. Which
DAC or DACs are powered down depends on the selected
output configuration.
In low power mode, DAC current consumption is content
dependent. On a typical video stream, it can be reduced by as
much as 40%. For applications requiring the highest possible video
performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10
For CVBS/YC output configurations, if DAC 1 is unconnected,
only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and
DAC 3 power down.
The ADV7342/ADV7343 include an Analog Devices propri-
etary cable detection feature. The cable detection feature is
available on DAC 1 and DAC 2, while operating in full-drive
mode (RSET1 = 510 Ω, RL1 = 37.5 Ω, assuming a connected
For YPrPb and RGB output configurations, if DAC 1 is
unconnected, all three DACs power down. DAC 2 is not
monitored for YPrPb and RGB output configurations.
cable). The feature is not available in low-drive mode (RSET1
4.12 kΩ, RL = 300 Ω). For a DAC to be monitored, the DAC
must be powered up in Subaddress 0x00.
=
Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is
detected, the appropriate DAC or DACs remain powered up for
the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame, when the process
is repeated.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, YC, YPrPb, and RGB output configurations.
For CVBS/YC output configurations, both DAC 1 and DAC 2
are monitored; that is, the CVBS and YC luma outputs are
monitored. For YPrPb and RGB output configurations, only
Rev.D | Page 69 of 108
ADV7342/ADV7343
Data Sheet
The ADV7342/ADV7343 include a power-on reset (POR)
circuit to ensure correct operation after power-up.
SLEEP MODE
Subaddress 0x00, Bit 0
SD TELETEXT INSERTION
Subaddress 0xC9 to Subaddress 0xCE
In sleep mode, most of the digital I/O pins of the ADV7342/
ADV7343 are disabled. For inputs, this means that the external
data is ignored, and internally the logic normally driven by a
given input is just tied low or high. This includes CLKINx.
The ADV7342/ADV7343 support the insertion of teletext data,
using a 2-pin interface, when operating in PAL mode. Teletext
insertion is enabled using Subaddress 0xC9, Bit 0.
For digital output pins, this means that the pin goes into tristate
(high impedance) mode.
In accordance with the PAL WST teletext standard, teletext data
should be inserted into the ADV7342/ADV7343 at a rate of
6.9375 Mbps. The teletext data can be inserted on the
There are some exceptions to allow the user to continue to
communicate with the part via I2C: the ALSB, SDA, and SCL
pins are kept alive.
,
, or C0 pin. The pin on which the teletext
S_VSYNC P_VSYNC
data is inserted is selected using Subaddress 0xC9, Bits [3:2].
PIXEL AND CONTROL PORT READBACK
When teletext insertion is enabled, a teletext request signal is
output from the ADV7342/ADV7343 to indicate when teletext
data should be inserted. The teletext request signal is output on
the SFL pin. The position (relative to the teletext data) and
width of the request signal are configurable using Subaddress
0xCA. The request signal can operate in either a line or a bit
mode. The request signal mode is controlled using Subaddress
0xC9, Bit 1.
Subaddress 0x12 to Subaddress 0x14, Subaddress 0x16
The ADV7342/ADV7343 support the readback of most digital
inputs via the I2C MPU port. This feature is useful for board
level connectivity testing with upstream devices.
The pixel port (S[7:0], Y[7:0], and C[7:0]), the control port
(
,
,
,
, and
),
S_HSYNC S_VSYNC P_HSYNC P_VSYNC
P_BLANK
and the SFL pin are available for readback via the MPU port.
The readback registers are located at Subaddress 0x12 to
Subaddress 0x14 and Subaddress 0x16.
To account for the noninteger relationship between the teletext
insertion rate (6.9375 Mbps) and the pixel clock (27 MHz), a
teletext insertion protocol is implemented in the ADV7342/
ADV7343. At a rate of 6.9375 Mbps, the time taken for the
insertion of 37 teletext bits equates to 144 pixel clock cycles (at
27 MHz). For every 37 teletext bits inserted into the ADV7342/
ADV7343, the 10th, 19th, 28th, and 37th bits are carried for three
pixel clock cycles, and the remainder are carried for four pixel
clock cycles (totaling 144 pixel clock cycles). The teletext
insertion protocol repeats every 37 teletext bits or 144 pixel
clock cycles until all 360 teletext bits are inserted.
When using this feature, apply a clock signal to the CLKIN_A
pin to register the levels applied to the input pins.
RESET MECHANISM
Subaddress 0x17, Bit 1
The ADV7342/ADV7343 have a software reset accessible via
the I2C MPU port. A software reset is activated by writing
a 1 to Subaddress 0x17, Bit 1. This resets all registers to their
default values. This bit is self-clearing; that is, after a 1 has been
written to the bit, the bit automatically returns to 0.
45 BYTES (360 BITS) – PAL
ADDRESS AND DATA
TELETEXT VBI LINE
RUN-IN CLOCK
Figure 81. Teletext VBI Line
Rev.D | Page 70 of 108
Data Sheet
ADV7342/ADV7343
tSYNTTXOUT
CVBS/Y
tPD
tPD
HSYNC
10.2µs
TTX
DATA
TTX
DEL
TTX
REQ
PROGRAMMABLE PULSE EDGES
TTX
ST
tSYNTTXOUT = 10.2µs.
tPD = PIPELINE DELAY THROUGH ADV7342/ADC7343.
TTX
DEL
= TTX
REQ
TO TTX
DATA
(PROGRAMMABLE RANGE = 4 BITS [0 TO 15 PIXEL CLOCK CYCLES]).
Figure 82. Teletext Functionality Diagram
Rev.D | Page 71 of 108
ADV7342/ADV7343
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT AND DESIGN
An optional reconstruction (anti-imaging) low-pass filter (LPF)
may be required on the ADV7342/ADV7343 DAC outputs if
the ADV7342/ADV7343 are connected to a device that requires
this filtering.
UNUSED PINS
If the
,
,
, and
pins are
P_VSYNC
S_HSYNC S_VSYNC P_HSYNC
not used, they should be tied to VDD_IO through a pull-up resistor
(10 kΩ or 4.7 kΩ). Any other unused digital inputs should be tied
to ground. Unused digital output pins should be left floating. DAC
outputs can be either left floating or connected to GND. Disabling
these outputs is recommended.
The filter specifications vary with the application. The use of
16× (SD), 8× (ED), or 4× (HD) oversampling can remove the
requirement for a reconstruction filter altogether.
For applications requiring an output buffer and reconstruction
filter, the ADA4430-1, ADA4411-3, and ADA4410-6 integrated
video filter buffers should be considered.
DAC CONFIGURATIONS
The ADV7342/ADV7343 contain six DACs. All six DACs can
be configured to operate in low-drive mode. Low-drive mode is
defined as 4.33 mA full-scale current into a 300 Ω load, RL.
Table 58. ADV7342/ADV7343 Output Rates
Input Mode
(Subaddress 0x01, (Subaddress
Bits[6:4])
PLL Control
DAC 1, DAC 2, and DAC 3 can also be configured to operate in
full-drive mode. Full-drive mode is defined as 34.7 mA full-
scale current into a 37.5 Ω load, RL. Full-drive is the recommended
mode of operation for DAC 1, DAC 2, and DAC 3.
0x00, Bit 1)
Output Rate (MHz)
SD Only
Off
On
Off
On
Off
On
27
216
27
216
74.25
297
(2x)
(16x)
(1x)
(8x)
(1x)
(4x)
The ADV7342/ADV7343 contain two RSET pins. A resistor
connected between the RSET1 pin and AGND is used to control
the full-scale output current and, therefore, the DAC output
voltage levels of DAC 1, DAC 2, and DAC 3. For low-drive
operation, RSET1 must have a value of 4.12 kΩ, and RL must have a
value of 300 Ω. For full-drive operation, RSET1 must have a value
of 510 Ω, and RL must have a value of 37.5 Ω.
ED Only
HD Only
Table 59. Output Filter Requirements
Cutoff
Frequency
Attenuation
–50 dB at
(MHz)
A resistor connected between the RSET2 pin and AGND is used
to control the full-scale output current and, therefore, the DAC
output voltage levels of DAC 4, DAC 5, and DAC 6. RSET2 must
have a value of 4.12 kΩ, and RL must have a value of 300 Ω (that
is, low-drive operation only).
Application Oversampling (MHz)
SD
SD
ED
ED
HD
HD
2×
16×
1×
8×
1×
4×
>6.5
>6.5
>12.5
>12.5
>30
20.5
209.5
14.5
203.5
44.25
267
The resistors connected to the RSET1 and RSET2 pins should have a
1% tolerance.
>30
The ADV7342/ADV7343 contain two compensation pins,
COMP1 and COMP2. A 2.2 nF compensation capacitor should
10µH
22pF
DAC
OUTPUT
3
4
be connected from each of these pins to VAA
.
75Ω
BNC
OUTPUT
600Ω
600Ω
1
VOLTAGE REFERENCE
The ADV7342/ADV7343 contain an on-chip voltage reference
that can be used as a board-level voltage reference via the VREF
pin. Alternatively, the ADV7342/ADV7343 can be used with an
external voltage reference by connecting the reference source to
the VREF pin. For optimal performance, use an external voltage
reference such as the AD1580 with the ADV7342/ ADV7343. If an
external voltage reference is not used, a 0.1 µF capacitor should
560Ω
560Ω
Figure 83. Example of Output Filter for SD, 16× Oversampling
4.7µH
DAC
OUTPUT
3
75Ω
BNC
OUTPUT
6.8pF
6.8pF
600Ω
1
600Ω
be connected from the VREF pin to VAA
.
4
VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER
560Ω
560Ω
An output buffer is necessary on any DAC that operates in low-
drive mode (RSETx = 4.12 kΩ, RL = 300 Ω). Analog Devices
produces a range of op amps suitable for this application, for
example, the AD8061. For more information about line driver
buffering circuits, see the relevant op amp data sheet.
Figure 84. Example of Output Filter for ED, 8× Oversampling
Rev.D | Page 72 of 108
Data Sheet
ADV7342/ADV7343
DAC
CIRCUIT FREQUENCY RESPONSE
OUTPUT
0
–10
–20
–30
–40
–50
200
120
40
PHASE
(Degrees)
3
390nH
33pF
75Ω
MAGNITUDE (dB)
BNC
300Ω
3
1
OUTPUT
33pF
75Ω
1
4
GROUP DELAY (Seconds)
4
500Ω
500Ω
–40
–120
–200
Figure 85. Example of Output Filter for HD, 4× Oversampling
CIRCUIT FREQUENCY RESPONSE
0
0
–10
–20
–30
–40
–50
–60
–70
–80
24n
21n
18n
15n
12n
9n
–30
MAGNITUDE (dB)
–60
1
10
100
–90
FREQUENCY (MHz)
PHASE (Degrees)
Figure 88. Output Filter Plot for HD, 4× Oversampling
–120
–150
–180
–210
–240
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADV7342/ADV7343 are highly integrated circuits
containing both precision analog and high speed digital
circuitry. They are designed to minimize interference effects on
the integrity of the analog circuitry by the high speed digital
circuitry. It is imperative that these same design and layout
techniques be applied to the system-level design so that optimal
performance is achieved.
GROUP DELAY (Seconds)
6n
3n
0
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 86. Output Filter Plot for SD, 16× Oversampling
The layout should be optimized for lowest noise on the
ADV7342/ADV7343 power and ground planes by shielding the
digital inputs and providing good power supply decoupling.
CIRCUIT FREQUENCY RESPONSE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
480
18n
16n
400
320
240
160
80
It is recommended to use a 4-layer printed circuit board with
ground and power planes separating the signal trace layer and
the solder side layer.
MAGNITUDE (dB)
14n
PHASE
(Degrees)
12n
10n
8n
GROUP DELAY (Seconds)
Component Placement
Component placement should be carefully considered to
separate noisy circuits, such as clock signals and high speed
digital circuitry, from analog circuitry.
0
6n
–80
–160
–240
The external loop filter components and components connected
to t he C OM P, V REF, and RSETx pins should be placed as close as
possible to and on the same side of the PCB as the ADV7342/
ADV7343. Adding vias to the PCB to get the components closer
to the ADV7342/ADV7343 is not recommended.
4n
2n
0
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 87. Output Filter Plot for ED, 8× Oversampling
It is recommended that the ADV7342/ADV7343 be placed as
close as possible to the output connector, with the DAC output
traces as short as possible.
The termination resistors on the DAC output traces should be
placed as close as possible to and on the same side of the PCB as
the ADV7342/ADV7343. The termination resistors should
overlay the PCB ground plane.
Rev.D | Page 73 of 108
ADV7342/ADV7343
Data Sheet
External filter and buffer components connected to the DAC
outputs should be placed as close as possible to the ADV7342/
ADV7343 to minimize the possibility of noise pickup from
neighboring circuitry and to minimize the effect of trace
capacitance on output bandwidth. This is particularly important
when operating in low-drive mode (RSETx = 4.12 kΩ, RL = 300 Ω).
be established a minimum of 250 µs prior to the VDD power
supply being established. The VAA and PVDD power supplies can
be established at any time and in any order. Tying ALSB to
VDD_IO completely removes this PSS requirement.
Digital Signal Interconnect
The digital signal traces should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal traces should not overlay the VAA or PVDD power plane.
Power Supplies
It is recommended that a separate regulated supply be provided
for each power domain (VAA, VDD, VDD_IO, and PVDD). For
optimal performance, linear regulators rather than switch mode
regulators should be used. If switch mode regulators must be
used, care must be taken with regard to the quality of the output
voltage in terms of ripple and noise. This is particularly true for
the VAA and PVDD power domains. Each power supply should be
individually connected to the system power supply at a single
point through a suitable filtering device, such as a ferrite bead.
Due to the high clock rates used, avoid long clock traces to the
ADV7342/ADV7343 to minimize noise pickup.
Any pull-up termination resistors for the digital inputs should
be connected to the VDD_IO power supply.
Any unused digital inputs should be tied to ground.
Analog Signal Interconnect
DAC output traces should be treated as transmission lines with
appropriate measures taken to ensure optimal performance (for
example, impedance matched traces). The DAC output traces
should be kept as short as possible. The termination resistors on
the DAC output traces should be placed as close as possible to,
and on the same side of the PCB as, the ADV7342/ADV7343.
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 10 nF and 0.1 µF ceramic capacitors. The VAA, PVDD
,
VDD_IO, and both VDD pins should be individually decoupled to
ground. The decoupling capacitors should be placed as close as
possible to the ADV7342/ADV7343 with the capacitor leads
kept as short as possible to minimize lead inductance.
To avoid crosstalk between the DAC outputs, it is recom-
mended that as much space as possible be left between the
traces connected to the DAC output pins. Adding ground traces
between the DAC output traces is also recommended.
A 1 µF tantalum capacitor is recommended across the VAA
supply in addition to the 10 nF and 0.1 µF ceramic capacitors.
Power Supply Sequencing
If the ALSB pin is tied low, a power supply sequence is required
for proper operation of the part. The VDD_IO power supply must
Rev.D | Page 74 of 108
Data Sheet
ADV7342/ADV7343
TYPICAL APPLICATION CIRCUIT
FERRITE BEAD
V
DD_IO
NOTES
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS
CONNECTED TO THE COMP, R , V AND DAC OUTPUT
PINS SHOULD BE LOCATED CLOSE TO AND ON THE SAME
SIDE OF THE PCB AS THE ADV7342/ADV7343.
V
POWER
DD_IO
33µF
10µF
0.1µF
0.01µF
SUPPLY
DECOUPLING
SET REF
GND_IO
FERRITE BEAD
GND_IO
GND_IO
GND_IO
PV
DD
(1.8V)
PV POWER
DD
SUPPLY
DECOUPLING
2
33µF
10µF
0.1µF
0.01µF
PGND
2. THE I C DEVICE ADDRESS IS CONFIGURABLE USING THE
ALSB PIN:
PGND
FERRITE BEAD
PGND
PGND
2
ALSB = 0, I C DEVICE ADDRESS = 0xD4 OR 0x54
ALSB = 1, I C DEVICE ADDRESS = 0xD6 OR 0x56
2
V
AA
V
POWER
AA
0.01µF
AGND
1µF
33µF
10µF
0.1µF
SUPPLY
DECOUPLING
ADI RECOMMENDS TO TIE ALSB TO VDD_IO. PLEASE
REFER TO POWER SUPPLY SEQUENCING SECTION FOR
MORE INFORMATION ON THIS.
AGND
AGND
AGND
AGND
FERRITE BEAD
V
DD
(1.8V)
3. THE RESISTORS CONNECTED TO THE R
SET
HAVE A 1% TOLERANCE.
PINS SHOULD
V
POWER SUPPLY
DD
33µF
10µF
0.1µF
0.01µF
DGND
DECOUPLING FOR
EACH POWER PIN
OPTIONAL. IF THE INTERNAL VOLTAGE
REFERENCE IS USED, A 0.1µF CAPACITOR
DGND
DGND
DGND
SHOULD BE CONNECTED FROM V
TO V
.
V
V
REF
AA
AA
AA
2.2nF
2.2nF
Y0
Y1
Y2
Y3
Y4
Y5
Y6
V
COMP1
COMP2
AA
1.1kΩ
1.235V
V
REF
0.1µF
AD1580
R
R
SET1
ADV7342/ADV7343 SET2
Y7
AGND
510Ω
4.12kΩ
S0
S1
S2
S3
S4
S5
S6
S7
AGND
AGND
PIXEL PORT INPUTS
OPTIONAL LPF
OPTIONAL LPF
DAC 1
DAC 2
DAC 3
DAC 1
DAC 2
DAC 3
DAC1 TO DAC3 FULL DRIVE OPTION
C0
C1
C2
C3
C4
C5
C6
C7
OPTIONAL LPF
75Ω
AGND
75Ω
75Ω
AGND
AGND
TIE EITHER LOW
OR HIGH
(SEE NOTE 2)
DAC1 TO DAC3 LOW DRIVE OPTION
ALSB
DAC 4
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
ADA4411-3
R
SET1
UNUSED
CONNECT TO DGND
75Ω
DAC 4
DAC 5
DAC 6
4.12kΩ
LPF
AGND
ADA4411-3
300Ω
S_HSYNC
S_VSYNC
75Ω
DAC 1
DAC 2
DAC 3
DAC 1
DAC 2
DAC 3
AGND
LPF
CONTROL
INPUTS/OUTPUTS
P_HSYNC
P_VSYNC
P_BLANK
ADA4411-3
300Ω
75Ω
DAC 5
AGND
LPF
CLKIN_A
CLKIN_B
CLOCK INPUTS
ADA4411-3
300Ω
SDA
SCL
75Ω
I2C PORT
AGND
LPF
EXTERNAL LOOP FILTERS
ADA4411-3
PV
DD
300Ω
12nF
75Ω
EXT_LF1
EXT_LF2
DAC 6
150nF
AGND
170Ω
LPF
300Ω
ADA4411-3
12nF
150nF
75Ω
170Ω
LPF
AGND
AGND PGND DGND DGND GND_IO
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PINS AND ON THE SAME
SIDE OF THE PCB AS THE
ADV7342/ADV7343.
300Ω
AGND
AGND PGND DGND DGND GND_IO
Figure 89. ADV7342/ADV7343 Typical Application Circuit
Rev.D | Page 75 of 108
ADV7342/ADV7343
Data Sheet
COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
The ADV7342/ADV7343 support a copy generation
management system (CGMS) conforming to the EIAJ CPR-
1204 and ARIB TR-B15 standards. CGMS data is transmitted
on Line 20 of odd fields and Line 283 of even fields. Subaddress
0x99, Bits[6:5] control whether CGMS data is output on odd or
even fields or both.
The HD CGMS data registers are at Subaddress 0x41, Subad-
dress 0x42, and Subaddress 0x43.
The ADV7342/ADV7343 also support CGMS Type B packets in
HD mode (720p and 1080i) in accordance with CEA-805-A.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
720p CGMS data is applied to Line 23 of the luminance vertical
blanking interval.
SD CGMS data can be transmitted only when the ADV7342/
ADV7343 are configured in NTSC mode. The CGMS data is 20
bits long. The CGMS data is preceded by a reference pulse of
the same amplitude and duration as a CGMS bit (see Figure 90).
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
1080i CGMS data is applied to Line 18 and Line 581 of the
luminance vertical blanking interval.
ED CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
The HD CGMS Type B data registers are at Subaddress 0x5E to
Subaddress 0x6E.
525p Mode
CGMS CRC FUNCTIONALITY
The ADV7342/ADV7343 support a copy generation manage-
ment system (CGMS) in 525p mode in accordance with EIAJ
CPR-1204-1.
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS
CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS
data bits, C19 to C14, which comprise the 6-bit CRC check
sequence, are automatically calculated on the ADV7342/ADV7343.
This calculation is based on the lower 14 bits (C13 to C0) of the
data in the CGMS data registers, and the result is output with
the remaining 14 bits to form the complete 20 bits of the CGMS
data. The calculation of the CRC sequence is based on the
polynomial x6 + x + 1 with a preset value of 111111.
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p
CGMS data is inserted on Line 41 and the 525p CGMS data
registers are at Subaddress 0x41, Subaddress 0x42, and Sub-
address 0x43. The ADV7342/ADV7343 also support CGMS
Type B packets in 525p mode in accordance with CEA-805-A.
When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
525p CGMS Type B data is inserted on Line 40. The 525p CGMS
Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
If SD CGMS CRC or ED/HD CGMS CRC are disabled, all
20 bits (C19 to C0) are output directly from the CGMS registers
(CRC must be calculated by the user manually).
625p Mode
If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is
enabled, the upper six CGMS Type B data bits (P122 to P127)
that comprise the 6-bit CRC check sequence are automatically
calculated on the ADV7342/ADV7343. This calculation is
based on the lower 128 bits (H0 to H5 and P0 to P121) of the
data in the CGMS Type B data registers. The result is output
with the remaining 128 bits to form the complete 134 bits of the
CGMS Type B data. The calculation of the CRC sequence is
based on the polynomial x6 + x + 1 with a preset value of
111111.
The ADV7342/ADV7343 support a copy generation management
system (CGMS) in 625p mode in accordance with IEC62375
(2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p
CGMS data is inserted on Line 43. The 625p CGMS data
registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5
and P0 to P127) are output directly from the CGMS Type B
registers (CRC must be calculated by the user manually).
The ADV7342/ADV7343 support a copy generation management
system (CGMS) in HD mode (720p and 1080i) in accordance
with EIAJ CPR-1204-2.
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
Rev.D | Page 76 of 108
Data Sheet
ADV7342/ADV7343
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
49.1µs ± 0.5µs
11.2µs
2.235µs ± 20ns
Figure 90. Standard Definition CGMS Waveform
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2
BIT 20
70% ± 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
21.2µs ± 0.22µs
22T
5.8µs ± 0.15µs
6T
T = 1/(fH × 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T ± 30ns
Figure 91. Enhanced Definition (525p) CGMS Waveform
PEAK WHITE
R = RUN-IN
S = START CODE
C0
LSB
C13
C9 C10 C11 C12
R
S
C1
C2
C3
C4
C5
C6
C7
C8
500mV ± 25mV
SYNC LEVEL
MSB
13.7µs
5.5µs ± 0.125µs
Figure 92. Enhanced Definition (625p) CGMS Waveform
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2
BIT 20
70% ± 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
T ± 30ns
–300mV
17.2µs ± 160ns
4T
22T
3.128µs ± 90ns
T = 1/(fH × 1650/58) = 781.93ns
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 93. High Definition (720p) CGMS Waveform
Rev.D | Page 77 of 108
ADV7342/ADV7343
Data Sheet
CRC SEQUENCE
BIT 20
+700mV
REF
BIT 1 BIT 2
70% ± 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
T ± 30ns
–300mV
22.84µs ± 210ns
22T
4T
4.15µs ± 60ns
T = 1/(f × 2200/77) = 1.038µs
H
f
= HORIZONTAL SCAN FREQUENCY
H
1H
Figure 94. High Definition (1080i) CGMS Waveform
CRC SEQUENCE
+700mV
START
BIT 1 BIT 2
BIT 134
70% ± 10%
H0
H1
H2
H3
H4
H5 P0
P1
P2
P3
P4
.
.
.
P122 P123 P124 P125 P126 P127
0mV
–300mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 95. Enhanced Definition (525p) CGMS Type B Waveform
CRC SEQUENCE
BIT 134
+700mV
START
BIT 1 BIT 2
70% ± 10%
H0
H1
H2
H3
H4
H5 P0
P1
P2
P3
P4
.
.
.
P122 P123 P124 P125 P126 P127
0mV
–300mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 96. High Definition (720p and 1080i) CGMS Type B Waveform
Rev.D | Page 78 of 108
Data Sheet
ADV7342/ADV7343
SD WIDE SCREEN SIGNALING
Figure 97). The latter portion of Line 23 (after 42.5 µs from the
Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B
HSYNC
falling edge of
) is available for the insertion of video.
The ADV7342/ADV7343 support wide screen signaling (WSS)
conforming to the ETSI 300 294 standard. WSS data is trans-
mitted on Line 23. WSS data can be transmitted only when the
device is configured in PAL mode. The WSS data is 14 bits long.
The function of each of these bits is shown in Table 60. The
WSS data is preceded by a run-in sequence and a start code (see
WSS data transmission on Line 23 can be enabled using
Subaddress 0x99, Bit 7. It is possible to blank the WSS portion
of Line 23 with Subaddress 0xA1, Bit 7.
Table 60. Function of WSS
Bit Number
Bit Description
13 12 11 10
9
8
7
6
5
4
3
1
0
0
1
0
1
1
0
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Setting
Aspect Ratio, Format, Position
4:3, full format, N/A
14:9, letterbox, center
14:9, letterbox, top
16:9, letterbox, center
16:9, letterbox, top
>16:9, letterbox, center
14:9, full format, center
16:0, N/A, N/A
Mode
0
1
Camera mode
Film mode
Color Encoding
Helper Signals
0
1
Normal PAL
Motion Adaptive ColorPlus
Not present
0
1
Present
Reserved
0
N/A
Teletext Subtitles
0
1
No
Yes
Open Subtitles
0
0
1
1
0
1
0
1
No
Subtitles in active image area
Subtitles out of active image area
Reserved
Surround Sound
Copyright
0
1
No
Yes
0
1
No copyright asserted or unknown
Copyright asserted
Copying not restricted
Copying restricted
Copy Protection
0
1
500mV
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
11.0µs
38.4µs
42.5µs
Figure 97. WSS Waveform Diagram
Rev.D | Page 79 of 108
ADV7342/ADV7343
Data Sheet
SD CLOSED CAPTIONING
and Line 284. All pixels inputs are ignored on Line 21 and on
Line 284 if closed captioning is enabled.
Subaddress 0x91 to Subaddress 0x94
The ADV7342/ADV7343 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and
Line 284 of the even fields.
The FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA-608 describe the closed captioning information for
Line 21 and Line 284.
The ADV7342/ADV7343 use a single buffering method. This
means that the closed captioning buffer is only 1-byte deep.
Therefore, there is no frame delay in outputting the closed
captioning data, unlike other 2-byte deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
Closed captioning consists of a seven-cycle sinusoidal burst that
is frequency- and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for two data bits
and is followed by the Logic 1 start bit. Sixteen bits of data
follow the start bit. These consist of two 8-bit bytes, seven data
bits, and one odd parity bit. The data for these bytes is stored in
the SD closed captioning registers (Subaddress 0x93 to
Subaddress 0x94).
VSYNC
to interrupt a microprocessor, which in turn loads the
new data (two bytes) in every field. If no new data is required
for transmission, 0s must be inserted in both data registers; this
is called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21. Otherwise, a TV does not
recognize them. If there is a message such as “Hello World”
that has an odd number of characters, it is important to add a
blank character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
The ADV7342/ADV7343 also support the extended closed
captioning operation, which is active during even fields and
encoded on scan Line 284. The data for this operation is stored
in the SD closed captioning registers (Subaddress 0x91 to
Subaddress 0x92).
The ADV7342/ADV7343 automatically generate all clock run-
in signals and timing that support closed captioning on Line 21
10.5 ± 0.25µs
12.91µs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
P
A
R
I
T
Y
S
T
A
R
T
D0 TO D6
D0 TO D6
BYTE 1
50 IRE
40 IRE
BYTE 0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003µs
27.382µs
33.764µs
Figure 98. SD Closed Captioning Waveform, NTSC
Rev.D | Page 80 of 108
Data Sheet
ADV7342/ADV7343
INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
ED/HD TEST PATTERNS
The ADV7342/ADV7343 are able to internally generate ED/HD
black bar and hatch test patterns. For ED test patterns, a 27 MHz
clock signal must be applied to the CLKIN_A pin. For HD test
patterns, a 74.25 MHz clock signal must be applied to the
CLKIN_A pin.
The ADV7342/ADV7343 are able to internally generate SD
color bar and black bar test patterns. For this function, a
27 MHz clock signal must be applied to the CLKIN_A pin.
The register settings in Table 61 are used to generate an SD
NTSC 75% color bar test pattern. CVBS output is available on
DAC 4, S-Video (Y-C) output is on DAC 5 and DAC 6, and
YPrPb output is on DAC 1 to DAC 3. On power-up, the
subcarrier frequency registers default to the appropriate values
for NTSC. All other registers are set as normal/default.
The register settings in Table 63 are used to generate an ED
525p hatch test pattern. YPrPb output is available on DAC 1 to
DAC 3. All other registers are set as normal/default.
Table 63. ED 525p Hatch Test Pattern Register Writes
Subaddress
Setting
Table 61. SD NTSC Color Bar Test Pattern Register Writes
0x00
0x01
0x31
0x1C
0x10
0x05
Subaddress
Setting
0x00
0xFC
0x82
0xC9
0x84
0x40
To generate an ED 525p black bar test pattern, the settings
shown in Table 63 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an SD NTSC black bar test pattern, the settings
shown in Table 61 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the settings
shown in Table 63 should be used, except that 0x0D should be
written to Subaddress 0x31.
For PAL output of either test pattern, the same settings are used,
except that Subaddress 0x80 is programmed to 0x11, and the
subcarrier frequency registers are programmed as shown in
Table 62.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
Table 62. PAL FSC Register Writes
Subaddress
For ED/HD standards other than 525p, the settings shown in
Table 63 (and subsequent comments) are used, except that
Subaddress 0x30, Bits[7:3] are updated as appropriate.
Description
Setting
0xCB
0x8A
0x8C
0x8D
FSC0
FSC1
0x8E
FSC2
0x09
0x8F
FSC3
0x2A
Note that, when programming the FSC registers, the user must
write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full
FSC value to be written is accepted only after the FSC3 write is
complete.
Rev.D | Page 81 of 108
ADV7342/ADV7343
Data Sheet
SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV7342/ADV7343 are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the
pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
S_VSYNC
S_HSYNC
before and after each line during active picture and retrace. If the
VDD_IO during this mode.
and
pins are not used, they should be tied to
ANALOG
VIDEO
EAV CODE
SAV CODE
C
b
C
r
8
0
0
0
F
F
F
F
A
B
A
B
A
B
8
0
0
0
C
b
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
Y
Y
Y
INPUT PIXELS
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
1440 CLOCK
1440 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
280 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 99. SD Slave Mode 0
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV7342/ADV7343 generate H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is
S_HSYNC
S_VSYNC
output on
and the F bit is output on
.
DISPLAY
DISPLAY
VERTICAL BLANK
4
522
523
524
525
1
2
3
5
6
7
8
10
11
20
21
22
9
H
F
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
H
F
ODD FIELD
EVEN FIELD
Figure 100. SD Master Mode 0, NTSC
Rev.D | Page 82 of 108
Data Sheet
ADV7342/ADV7343
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
4
22
23
1
2
3
5
6
7
21
H
F
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
318
334
335
336
309
310
311
312
313
314
315
316
317
319
320
H
F
ODD FIELD
EVEN FIELD
Figure 101. SD Master Mode 0, PAL
ANALOG
VIDEO
H
F
Figure 102. SD Master Mode 0, Data Transitions
Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)
In this mode, the ADV7342/ADV7343 accept horizontal sync and odd/even field signals. When
HSYNC
is low, a transition of the field
input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as required by
HSYNC S_HSYNC S_VSYNC
the CCIR-624 standard.
and FIELD are input on the
and
pins, respectively.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
3
4
5
7
9
10
11
1
2
6
8
HSYNC
FIELD
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
FIELD
ODD FIELD EVEN FIELD
Figure 103. SD Slave Mode 1, NTSC
Rev.D | Page 83 of 108
ADV7342/ADV7343
Data Sheet
DISPLAY
DISPLAY
VERTICAL BLANK
3
4
5
7
622
623
624
625
1
2
6
21
22
23
HSYNC
FIELD
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
FIELD
ODD FIELD
EVEN FIELD
Figure 104. SD Slave Mode 1, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When
field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as
HSYNC
is low, a transition of the
HSYNC
required by the CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions.
S_HSYNC S_VSYNC
and
FIELD are output on the
and
pins, respectively.
HSYNC
FIELD
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 105. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV7342/ADV7343 accept horizontal and vertical sync signals. A coincident low transition of both
VSYNC HSYNC
HSYNC
VSYNC
and
inputs indicates the start of an odd field. A
ADV7342/ADV7343 automatically blank all normally blank lines as required by the CCIR-624 standard.
S_HSYNC S_VSYNC
low transition when
is high indicates the start of an even field. The
HSYNC VSYNC
and
are input
on the
and
pins, respectively.
Rev.D | Page 84 of 108
Data Sheet
ADV7342/ADV7343
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
3
4
5
7
8
20
21
22
2
6
10
11
9
HSYNC
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
Figure 106. SD Slave Mode 2, NTSC
DISPLAY
DISPLAY
VERTICAL BLANK
4
622
623
624
625
1
2
3
5
6
7
21
22
23
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
Figure 107. SD Slave Mode 2, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV7342/ADV7343 can generate horizontal and vertical sync signals. A coincident low transition of both
VSYNC VSYNC HSYNC
HSYNC
and
is high indicates the start of an even field. The
inputs indicates the start of an odd field. A
ADV7342/ADV7343 automatically blank all normally blank lines as required by the CCIR-624 standard.
S_HSYNC S_VSYNC
low transition when
HSYNC
VSYNC
are output
and
on the
and
pins, respectively.
HSYNC
VSYNC
PIXEL
DATA
Cb
Cr
Y
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 108. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev.D | Page 85 of 108
ADV7342/ADV7343
Data Sheet
HSYNC
VSYNC
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PIXEL
DATA
Cb
Cr
Y
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 109. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
HSYNC
In this mode, the ADV7342/ADV7343 accept or generate horizontal sync and odd/even field signals. When
is high, a transition
of the field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as
HSYNC
VSYNC
S_VSYNC
required by the CCIR-624 standard.
and
are output in master mode and input in slave mode on the and
S_VSYNC
pins, respectively.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
4
20
21
22
10
11
1
2
3
5
6
7
8
9
HSYNC
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
FIELD
ODD FIELD EVEN FIELD
Figure 110. SD Timing Mode 3, NTSC
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
FIELD
EVEN FIELD ODD FIELD
Figure 111. SD Timing Mode 3, PAL
Rev.D | Page 86 of 108
Data Sheet
HD TIMING
ADV7342/ADV7343
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
P_VSYNC
P_HSYNC
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
P_VSYNC
P_HSYNC
HSYNC
VSYNC
Input Timing
Figure 112. 1080i
and
Rev.D | Page 87 of 108
ADV7342/ADV7343
Data Sheet
VIDEO OUTPUT LEVELS
SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10
Pattern: 100% Color Bars
700mV
700mV
300mV
300mV
Figure 113. Y Levels—NTSC
Figure 116. Y Levels—PAL
700mV
700mV
Figure 114. Pr Levels—NTSC
Figure 117. Pr Levels—PAL
700mV
700mV
Figure 115. Pb Levels—NTSC
Figure 118. Pb Levels—PAL
Rev.D | Page 88 of 108
Data Sheet
ADV7342/ADV7343
ED/HD YPrPb OUTPUT LEVELS
EIA-770.3, STANDARD FOR Y
EIA-770.2, STANDARD FOR Y
INPUT CODE
INPUT CODE
940
OUTPUT VOLTAGE
OUTPUT VOLTAGE
940
700mV
700mV
64
64
300mV
300mV
EIA-770.3, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
EIA-770.2, STANDARD FOR Pr/Pb
960
OUTPUT VOLTAGE
960
512
64
600mV
700mV
700mV
512
64
Figure 121. EIA-770.3 Standard Output Signals (1080i/720p)
Figure 119. EIA-770.2 Standard Output Signals (525p/625p)
Y–OUTPUT LEVELS FOR
FULL INPUT SELECTION
INPUT CODE
1023
OUTPUT VOLTAGE
EIA-770.1, STANDARD FOR Y
INPUT CODE
OUTPUT VOLTAGE
782mV
940
700mV
714mV
64
300mV
64
286mV
Pr/Pb–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
INPUT CODE
1023
EIA-770.1, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
960
700mV
700mV
512
64
64
300mV
Figure 122. Output Levels for Full Input Selection
Figure 120. EIA-770.1 Standard Output Signals (525p/625p)
Rev.D | Page 89 of 108
ADV7342/ADV7343
Data Sheet
SD/ED/HD RGB OUTPUT LEVELS
Pattern: 100%/75% Color Bars
R
R
700mV/525mV
700mV/525mV
300mV
300mV
G
G
700mV/525mV
700mV/525mV
300mV
300mV
B
B
700mV/525mV
700mV/525mV
300mV
300mV
Figure 125. HD RGB Output Levels—RGB Sync Disabled
Figure 123. SD/ED RGB Output Levels—RGB Sync Disabled
R
R
700mV/525mV
600mV
300mV
700mV/525mV
300mV
0mV
0mV
G
G
700mV/525mV
600mV
700mV/525mV
300mV
0mV
300mV
0mV
B
B
700mV/525mV
600mV
700mV/525mV
300mV
0mV
300mV
0mV
Figure 126. HD RGB Output Levels—RGB Sync Enabled
Figure 124. SD/ED RGB Output Levels—RGB Sync Enabled
Rev.D | Page 90 of 108
Data Sheet
ADV7342/ADV7343
SD OUTPUT PLOTS
VOLTS
0.6
VOLTS IRE:FLT
100
0.4
0.2
0
0.5
50
0
0
–0.2
0
F1
–50
L608
10
L76
20
30
40
50
60
0
10
20
30
MICROSECONDS
PRECISION MODE OFF
40
50
60
MICROSECONDS
NOISE REDUCTION: 0.00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
APL = 44.5%
525 LINE NTSC
PRECISION MODE OFF
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1, 2, 3, 4
SYNCHRONOUS SYNC = A
FRAMES SELECTED 1, 2
SLOW CLAMP TO 0.00V AT 6.72µµs
Figure 127. NTSC Color Bars (75%)
Figure 130. PAL Color Bars (75%)
VOLTS
0.5
VOLTS IRE:FLT
0.6
0.4
50
0.2
0
00
0
–0.2
F2
L238
L575
20
0
10
20
30
40
50
60
0
10
30
40
50
60
70
MICROSECONDS
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.3%
APL NEEDS SYNC SOURCE.
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
NO BUNCH SIGNAL
PRECISION MODE OFF
PRECISION MODE OFF
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V AT 6.72µµs
SYNCHRONOUS SYNC = SOURCE
FRAMES SELECTED 1, 2
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 128. NTSC Luma
Figure 131. PAL Luma
VOLTS IRE:FLT
VOLTS
0.5
0.4
50
0.2
0
0
0
–0.2
–0.4
–50
–0.5
F1
L76
L575
20
0
10
20
30
40
50
60
0
10
30
40
50
60
MICROSECONDS
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC SOURCE.
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
APL NEEDS SYNC SOURCE.
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
NO BUNCH SIGNAL
PRECISION MODE OFF
PRECISION MODE OFF
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1
SYNCHRONOUS SYNC = B
FRAMES SELECTED 1, 2
Figure 129. NTSC Chroma
Figure 132. PAL Chroma
Rev.D | Page 91 of 108
ADV7342/ADV7343
VIDEO STANDARDS
Data Sheet
0
DATUM
H
SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
272T
*1
4T
4T
1920T
DIGITAL
ACTIVE LINE
ANCILLARY DATA
(OPTIONAL) OR BLANKING CODE
EAV CODE
SAV CODE
F
F
F
F
0
0
0
0
F
F
0
0
0
0
C
C
r
C
INPUT PIXELS
Y
V
V
Y
b
r
H*
H*
4 CLOCK
4 CLOCK
192
0
2199
SAMPLE NUMBER
2112
2116 2156
44
188
2111
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FRAME RATE OF 30Hz: 40 SAMPLES
FOR A FRAME RATE OF 25Hz: 480 SAMPLES
Figure 133. EAV/SAV Input Data Timing Diagram (SMPTE 274M)
SMPTE 293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
DIGITAL
SAV CODE
F
EAV CODE
F
ACTIVE LINE
F
F
0
0
0
0
F
F
0
0
0
0
C
b
C
r
C
r
INPUT PIXELS
V
Y
V
Y
Y
H*
H*
4 CLOCK
4 CLOCK
853 857
SAMPLE NUMBER
719
723 736
DATUM
799
0
719
0
H
DIGITAL HORIZONTAL BLANKING
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 134. EAV/SAV Input Data Timing Diagram (SMPTE 293M)
ACTIVE
VIDEO
ACTIVE
VIDEO
VERTICAL BLANK
522 523 524 525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 135. SMPTE 293M (525p)
Rev.D | Page 92 of 108
Data Sheet
ADV7342/ADV7343
ACTIVE
VIDEO
ACTIVE
VIDEO
VERTICAL BLANK
12
13
1
2
5
6
7
8
9
43
44
45
622 623
624 625
4
10
11
Figure 136. ITU-R BT.1358 (625p)
DISPLAY
VERTICAL BLANKING INTERVAL
7
1
2
3
4
5
6
747
748
749
750
26
27
744
745
8
25
Figure 137. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
560
1
2
5
6
7
8
21
22
1124
1125
3
4
20
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
Figure 138. SMPTE 274M (1080i)
Rev.D | Page 93 of 108
ADV7342/ADV7343
Data Sheet
CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to
configure the ADV7342/ ADV7343 for basic operation. Certain
features are enabled by default. If required for a specific
application, additional features can be enabled.
Table 64 lists the scripts available for the SD modes of
operation. Similarly, Table 85 and Table 111 list the scripts
available for ED and HD modes of operation, respectively. For
all scripts, only the necessary register writes are included. All
other registers are assumed to have their default values.
STANDARD DEFINITION
Table 64. SD Configuration Scripts
Input Format
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
Input Data Width1
8-bit SDR
Synchronization Format
Input Color Space
YCrCb
YCrCb
Output Color Space
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
Table Number
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
8-bit SDR
8-bit SDR
8-bit SDR
YCrCb
YCrCb
HSYNC VSYNC
/
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
HSYNC VSYNC
YCrCb
/
HSYNC VSYNC
YCrCb
/
HSYNC VSYNC
RGB
/
HSYNC VSYNC
/
RGB
NTSC Sq. Pixel
NTSC Sq. Pixel
8-bit SDR
16-bit SDR
EAV/SAV
HSYNC VSYNC
/
YCrCb
RGB
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
Table 73
Table 74
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
8-bit SDR
8-bit SDR
8-bit SDR
8-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
HSYNC VSYNC
/
HSYNC VSYNC
/
HSYNC VSYNC
/
HSYNC VSYNC
/
HSYNC VSYNC
/
RGB
PAL Sq. Pixel
PAL Sq. Pixel
8-bit SDR
16-bit SDR
EAV/SAV
HSYNC VSYNC
/
YCrCb
RGB
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
Table 83
Table 84
1 SDR = single data rate.
Rev.D | Page 94 of 108
Data Sheet
ADV7342/ADV7343
Table 65. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Table 69. 16-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x10
Software reset.
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x82
0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x8A
0x08
0x0C
16-bit input enabled.
HSYNC VSYNC
Timing Mode 2 (slave).
synchronization.
/
Table 66. 8-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
Table 70. 16-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
RGB output enabled. RGB output sync
enabled.
0x82
0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x80
0x82
0x10
0xC9
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Table 67. 8-Bit 525i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress Setting Description
0x88
0x8A
0x08
0x0C
16-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
Table 71. 24-Bit 525i RGB In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
RGB output enabled. RGB output sync
enabled.
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
0x80
0x82
0x10
0xC9
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
NTSC standard. SSAF luma filter
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Table 68. 8-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x87
0x88
0x8A
0x80
0x10
0x0C
RGB input enabled.
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset.
24-bit RGB input enabled
All DACs enabled. PLL enabled (16×).
SD input mode.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
RGB output enabled. RGB output sync
enabled.
0x80
0x82
0x10
0xC9
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Rev.D | Page 95 of 108
ADV7342/ADV7343
Data Sheet
Table 75. 8-Bit 625i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Subaddress Setting Description
Table 72. 24-Bit 525i RGB In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset.
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x11
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x80
0x82
0x10
0xC9
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC1
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Table 76. 8-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x87
0x88
0x8A
0x80
0x10
0x0C
RGB input enabled.
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x11
Software reset.
24-bit RGB input enabled
All DACs enabled. PLL enabled (16×).
SD input mode.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Table 73. 8-Bit NTSC Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress Setting Description
0x82
0x8A
0xC1
0x0C
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x17
0x00
0x01
0x80
0x02
0x1C
0x00
0x10
Software reset
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
Table 77. 8-Bit 625i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress Setting Description
enabled. 1.3 MHz chroma filter enabled.
0x82
0xDB
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled. Square pixel mode enabled.
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in NTSC square pixel mode (24.5454
MHz input clock).
RGB output enabled. RGB output sync
enabled.
0x80
0x82
0x11
0xC1
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Table 74. 16-Bit NTSC Square Pixel RGB In, CVBS/Y-C Out
Subaddress Setting Description
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x17
0x00
0x01
0x80
0x02
0x1C
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
Table 78. 8-Bit 625i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
NTSC standard. SSAF luma filter
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset.
enabled. 1.3 MHz chroma filter enabled.
All DACs enabled. PLL enabled (16×).
SD input mode.
0x82
0xDB
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal
RGB output enabled. RGB output sync
enabled.
enabled. Square pixel mode enabled.
0x87
0x88
0x8A
0x80
0x10
0x0C
RGB input enabled.
0x80
0x82
0x11
0xC1
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
16-bit RGB input enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Subcarrier frequency register values for
CVBS and/or S-Video (Y-C) output in
NTSC square pixel mode (24.5454 MHz
input clock).
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Rev.D | Page 96 of 108
Data Sheet
ADV7342/ADV7343
Table 79. 16-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out
Table 82. 24-Bit 625i RGB In, RGB and CVBS/Y-C Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x11
Software reset.
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
RGB output enabled. RGB output sync
enabled.
0x82
0xC1
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x80
0x82
0x11
0xC1
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x88
0x8A
0x08
0x0C
16-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x87
0x88
0x8A
0x80
0x10
0x0C
RGB input enabled.
24-bit RGB input enabled
Table 80. 16-Bit 625i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x17
0x00
0x01
0x02
0x02
0xFC
0x00
0x10
Software reset.
Table 83. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress Setting Description
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
0x17
0x00
0x01
0x80
0x02
0x1C
0x00
0x11
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
0x80
0x82
0x11
0xC1
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xD3
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
0x88
0x8A
0x08
0x0C
16-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x8C
0x8D
0x8E
0x8F
0x0C
0x8C
0x79
0x26
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
Table 81. 24-Bit 625i RGB In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x00
0x01
0x80
0x02
0xFC
0x00
0x11
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
Table 84. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out
Subaddress Setting Description
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x17
0x00
0x01
0x80
0x02
0x1C
0x00
0x11
Software reset.
0x82
0xC1
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x87
0x88
0x8A
0x80
0x10
0x0C
RGB input enabled.
24-Bit RGB input enabled
0x82
0xD3
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x87
0x88
0x8A
0x80
0x10
0x0C
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x8C
0x8D
0x8E
0x8F
0x0C
0x8C
0x79
0x26
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
Rev.D | Page 97 of 108
ADV7342/ADV7343
Data Sheet
ENHANCED DEFINITION
Table 85. ED Configuration Scripts
Input Format
Input Data Width1 Synchronization Format
Input Color Space
YCrCb
YCrCb
Output Color Space
Table Number
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
YPrPb
YPrPb
RGB
YPrPb
YPrPb
RGB
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YCrCb
YCrCb
YPrPb
YPrPb
RGB
EAV/SAV
YCrCb
YCrCb
HSYNC VSYNC
RGB
/
HSYNC VSYNC
/
RGB
RGB
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YPrPb
YPrPb
RGB
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
Table 108
Table 109
Table 110
RGB
YPrPb
YPrPb
RGB
RGB
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
YPrPb
YPrPb
RGB
HSYNC VSYNC
RGB
/
HSYNC VSYNC
RGB
/
1 SDR = single data rate; DDR = dual data rate.
Table 86. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Table 88. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x31
0x04
0x01
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x02
0x30
0x31
0x10
0x04
0x01
RGB output enabled. RGB output sync
enabled.
Pixel data valid.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Table 87. 8-Bit 525p YCrCb In, YPrPb Out
Subaddress Setting Description
Pixel data valid.
Table 89. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x04
Software reset.
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x30
0x31
0x00
0x01
525p at 59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
0x31
0x01
Pixel data valid.
Rev.D | Page 98 of 108
Data Sheet
ADV7342/ADV7343
Table 95. 24-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Table 90. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x00
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
Table 91. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
Table 96. 24-Bit 525p YCrCb In, RGB Out
Subaddress Setting Description
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
RGB output enabled. RGB output sync
enabled.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x30
0x31
0x04
0x01
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
RGB output enabled. RGB output sync
enabled.
Pixel data valid.
0x30
0x00
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Table 92. 16-Bit 525p YCrCb In, RGB Out
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
Table 97. 24-Bit 525p RGB In, RGB Out
Subaddress Setting Description
RGB output enabled. RGB output sync
enabled.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x30
0x31
0x00
0x01
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
RGB output enabled. RGB output sync
enabled.
Pixel data valid.
0x30
0x00
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Table 93. 24-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x31
0x33
0x35
0x01
0x28
0x02
Pixel data valid.
4:4:4 input data.
RGB input enabled.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x04
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Table 98. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
Table 94. 24-Bit 525p YCrCb In, YPrPb Out
Subaddress Setting Description
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x31
0x1C
0x01
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x00
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
Pixel data valid.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
Rev.D | Page 99 of 108
ADV7342/ADV7343
Data Sheet
Table 99. 8-Bit 625p YCrCb In, YPrPb Out
Subaddress Setting Description
Table 104. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x18
0x01
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
0x30
0x31
0x1C
0x01
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
Pixel data valid.
Table 100. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Table 105. 16-Bit 625p YCrCb In, RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
0x02
0x30
0x31
0x10
0x1C
0x01
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x18
0x01
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Pixel data valid.
Table 106. 24-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
Table 101. 8-Bit 625p YCrCb In, RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x1C
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x02
0x30
0x10
0x18
RGB output enabled. RGB output sync
enabled.
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Table 107. 24-Bit 625p YCrCb In, YPrPb Out
Subaddress Setting Description
0x31
0x01
Pixel data valid.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x18
Software reset.
Table 102. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x1C
Software reset.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Table 108. 24-Bit 625p YCrCb In (EAV/SAV), RGB Out
0x31
0x01
Pixel data valid.
Subaddress Setting Description
Table 103. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x18
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
0x30
0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
0x31
0x01
Pixel data valid.
Rev.D | Page 100 of 108
Data Sheet
ADV7342/ADV7343
Table 109. 24-Bit 625p YCrCb In, RGB Out
Subaddress Setting Description
Table 110. 24-Bit 625p RGB In, RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
RGB output enabled. RGB output sync
enabled.
0x30
0x18
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x30
0x18
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31
0x33
0x01
0x28
Pixel data valid.
4:4:4 input data.
0x31
0x33
0x35
0x01
0x28
0x02
Pixel data valid.
4:4:4 input data.
RGB input enabled.
HIGH DEFINITION
Table 111. HD Configuration Scripts
Input Format
Input Data Width1 Synchronization Format Input Color Space Output Color Space Table Number
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YPrPb
YPrPb
RGB
Table 112
Table 113
Table 114
Table 115
Table 116
Table 117
Table 118
Table 119
Table 120
Table 121
Table 122
Table 123
Table 124
RGB
YPrPb
YPrPb
RGB
RGB
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
YPrPb
YPrPb
RGB
HSYNC VSYNC
RGB
/
HSYNC VSYNC
/
RGB
1080i at 30 Hz/29.97 Hz 8-bit DDR
1080i at 30 Hz/29.97 Hz 8-bit DDR
1080i at 30 Hz/29.97 Hz 8-bit DDR
1080i at 30 Hz/29.97 Hz 8-bit DDR
1080i at 30 Hz/29.97 Hz 16-bit SDR
1080i at 30 Hz/29.97 Hz 16-bit SDR
1080i at 30 Hz/29.97 Hz 16-bit SDR
1080i at 30 Hz/29.97 Hz 16-bit SDR
1080i at 30 Hz/29.97 Hz 24-bit SDR
1080i at 30 Hz/29.97 Hz 24-bit SDR
1080i at 30 Hz/29.97 Hz 24-bit SDR
1080i at 30 Hz/29.97 Hz 24-bit SDR
1080i at 30 Hz/29.97 Hz 24-bit SDR
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YPrPb
YPrPb
RGB
Table 125
Table 126
Table 127
Table 128
Table 129
Table 130
Table 131
Table 132
Table 133
Table 134
Table 135
Table 136
Table 137
RGB
YPrPb
YPrPb
RGB
RGB
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
YPrPb
YPrPb
RGB
HSYNC VSYNC
RGB
/
HSYNC VSYNC
RGB
/
1 SDR = single data rate; DDR = dual data rate.
Rev.D | Page 101 of 108
ADV7342/ADV7343
Data Sheet
Table 116. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Table 112. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x2C
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x30
0x31
0x2C
0x01
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Pixel data valid. 4× oversampling.
Table 117. 16-Bit 720p YCrCb In, YPrPb Out
Subaddress Setting Description
Table 113. 8-Bit 720p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x28
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x30
0x31
0x28
0x01
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output
levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Pixel data valid. 4× oversampling.
Table 118. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
Table 114. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
RGB output enabled. RGB output sync
enabled.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x31
0x2C
0x01
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x02
0x30
0x31
0x10
0x2C
0x01
RGB output enabled. RGB output sync
enabled.
Pixel data valid. 4× oversampling.
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Table 119. 16-Bit 720p YCrCb In, RGB Out
Subaddress Setting Description
Pixel data valid. 4× oversampling.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
Table 115. 8-Bit 720p YCrCb In, RGB Out
Subaddress Setting Description
RGB output enabled. RGB output sync
enabled.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
0x30
0x31
0x28
0x01
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
Pixel data valid. 4× oversampling.
0x02
0x30
0x10
0x28
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output
levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Rev.D | Page 102 of 108
Data Sheet
ADV7342/ADV7343
Table 120. 24-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
Table 124. 24-Bit 720p RGB In, RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x2C
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
RGB output enabled. RGB output sync
enabled.
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
0x30
0x28
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x33
0x35
0x01
0x28
0x02
Pixel data valid. 4× oversampling.
4:4:4 input data.
Table 121. 24-Bit 720p YCrCb In, YPrPb Out
RGB input enabled.
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x28
Software reset.
Table 125. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
All DACs enabled. PLL enabled (4×).
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x31
0x6C
0x01
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 122. 24-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
Table 126. 8-Bit 1080i YCrCb In, YPrPb Out
Subaddress Setting Description
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
RGB output enabled. RGB output sync
enabled.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x30
0x31
0x68
0x01
1080i at 30 Hz/29.97 Hz. HSYNC/
VSYNC synchronization. EIA-770.3
output levels.
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
Pixel data valid. 4× oversampling.
Table 123. 24-Bit 720p YCrCb In, RGB Out
Subaddress Setting Description
Table 127. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
0x02
0x30
0x10
0x6C
RGB output enabled. RGB output sync
enabled.
0x30
0x28
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
1080i at 30 Hz/29.97 Hz. HSYNC/
VSYNC synchronization. EIA-770.3
output levels.
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
0x31
0x01
Pixel data valid. 4× oversampling.
Rev.D | Page 103 of 108
ADV7342/ADV7343
Data Sheet
Table 128. 8-Bit 1080i YCrCb In, RGB Out
Table 132. 16-Bit 1080i YCrCb In, RGB Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (4×).
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
0x02
0x30
0x31
0x10
0x68
0x01
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x68
0x01
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Pixel data valid. 4× oversampling.
Table 133. 24-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
Table 129. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x6C
Software reset.
Subaddress Setting Description
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x6C
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 134. 24-Bit 1080i YCrCb In, YPrPb Out
Table 130. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x68
Software reset.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x68
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 131. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Table 135. 24-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x6C
0x01
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
Rev.D | Page 104 of 108
Data Sheet
ADV7342/ADV7343
Table 136. 24-Bit 1080i YCrCb In, RGB Out
Subaddress Setting Description
Table 137. 24-Bit 1080i RGB In, RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
RGB output enabled. RGB output sync
enabled.
0x30
0x68
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x30
0x68
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x33
0x01
0x28
Pixel data valid. 4× oversampling.
4:4:4 input data.
0x31
0x33
0x35
0x01
0x28
0x02
Pixel data valid. 4× oversampling.
4:4:4 input data.
RGB input enabled.
Rev.D | Page 105 of 108
ADV7342/ADV7343
Data Sheet
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
PLANE
17
32
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 139. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Macrovision2
Antitaping
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ST-64-2
ST-64-2
ADV7342BSTZ
ADV7343BSTZ
EVAL-ADV7342EBZ
EVAL-ADV7343EBZ
Yes
No
Yes
No
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
ADV7342 Evaluation Platform
ADV7343 Evaluation Platform
1 Z = RoHS Compliant Part.
2 Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video.
Rev.D | Page 106 of 108
Data Sheet
NOTES
ADV7342/ADV7343
Rev.D | Page 107 of 108
ADV7342/ADV7343
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06399-0-3/12(D)
Rev. D | Page 108 of 108
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