ADV7393_技术文档

Low Power, Chip Scale

10-Bit SD/HD Video Encoder

ADV7390/ADV7391/ADV7392/ADV7393

NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)

Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant

Programmable features

Luma and chroma filter responses

Vertical blanking interval (VBI)

FEATURES

3 high quality, 10-bit video DACs

16× (216 MHz) DAC oversampling for SD

8× (216 MHz) DAC oversampling for ED

4× (297 MHz) DAC oversampling for HD

37 mA maximum DAC output current

Multiformat video input support

4:2:2 YCrCb (SD, ED, and HD)

Subcarrier frequency (F_SC) and phase

Luma delay

Copy generation management system (CGMS)

Closed captioning and wide screen signaling (WSS)

Integrated subcarrier locking to external video source

Complete on-chip video timing generator

On-chip test pattern generation

Serial MPU interface with dual I²C® and SPI® compatibility

2.7 V or 3.3 V analog operation

1.8 V digital operation

3.3 V I/O operation

Temperature range: −40°C to +85°C

4:4:4 RGB (SD)

Multiformat video output support

Composite (CVBS) and S-Video (Y/C)

Component YPrPb (SD, ED, and HD)

Component RGB (SD, ED, and HD)

Lead frame chip scale package (LFCSP) options

32-lead, 5 mm × 5 mm LFCSP

40-lead, 6 mm × 6 mm LFCSP

Advanced power management

Patented content-dependent low power DAC operation

Automatic cable detection and DAC power-down

Individual DAC on/off control

Sleep mode with minimal power consumption

74.25 MHz 8-/10-/16-bit high definition input support

Compliant with SMPTE 274M (1080i), 296M (720p),

and 240M (1035i)

APPLICATIONS

Mobile handsets

Digital still cameras

Portable media and DVD players

Portable game consoles

Digital camcorders

Set-top box (STB)

Automotive infotainment (ADV7393 only)

EIA/CEA-861B compliance support

NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support

FUNCTIONAL BLOCK DIAGRAM

ALSB/

SPI_SS

SCL/ SDA/

MOSI SCLK

SFL/

MISO

V_AA

DGND (2)

V_DD(2)

AGND

ADV739x

GND_IO

VDD_IO

VBI DATA SERVICE

INSERTION

MPU PORT

SUBCARRIER FREQUENCY

LOCK (SFL)

10-BIT

DAC 1

DAC 2

DAC 3

DAC 1

YUV

16×

FILTER

PROGRAMMABLE

LUMINANCE

FILTER

TO

ADD

10-BIT

DAC 2

YCrCb/

RGB

SYNC

RGB/YCrCb

4:2:2 TO 4:4:4

TO

YUV

P15 TO P0/

P7 TO P0

INPUT

DEINTERLEAVE

MATRIX

PROGRAMMABLE

CHROMINANCE

FILTER

10-BIT

DAC 3

16×

FILTER

ADD

BURST

SIN/COS DDS

BLOCK

ASYNC

BYPASS

YCrCb

YCbCr

PROGRAMMABLE

TO

ED/HD FILTERS

RGB MATRIX

4×

FILTER

HDTV

TEST

PATTERN

GENERATOR

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

POWER

MANAGEMENT

CONTROL

REFERENCE

AND CABLE

DETECT

VIDEO TIMING GENERATOR

16x/4x OVERSAMPLING PLL

R_SET

RESET

HSYNC

VSYNC

CLKIN PV_DDPGND EXT_LF

COMP

Figure 1.

Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.

Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098, and other intellectual property rights.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7390/ADV7391/ADV7392/ADV7393

TABLE OF CONTENTS

Features .............................................................................................. 1

SD Subcarrier Frequency Lock, Subcarrier Reset, and Timing

Reset............................................................................................. 46

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Detailed Features .............................................................................. 4

General Description......................................................................... 4

Specifications..................................................................................... 5

Power Supply Specifications........................................................ 5

Input Clock Specifications .......................................................... 5

Analog Output Specifications..................................................... 5

Digital Input/Output Specifications........................................... 6

MPU Port Timing Specifications ............................................... 6

Digital Timing Specifications ..................................................... 7

Video Performance Specifications ............................................. 8

Power Specifications .................................................................... 8

Timing Diagrams.............................................................................. 9

Absolute Maximum Ratings.......................................................... 15

Thermal Resistance .................................................................... 15

ESD Caution................................................................................ 15

Pin Configurations and Function Descriptions ......................... 16

Typical Performance Characteristics ........................................... 18

MPU Port Description................................................................... 23

I²C Operation.............................................................................. 23

SPI Operation.............................................................................. 24

Register Map.................................................................................... 25

Register Programming............................................................... 25

Subaddress Register (SR7 to SR0) ............................................ 25

ADV7390/ADV7391 Input Configuration ................................. 41

Standard Definition.................................................................... 41

Enhanced Definition/High Definition .................................... 41

Enhanced Definition (At 54 MHz) .......................................... 41

ADV7392/ADV7393 Input Configuration ................................. 42

Standard Definition.................................................................... 42

Enhanced Definition/High Definition .................................... 43

Enhanced Definition (At 54 MHz) .......................................... 43

Output Configuration.................................................................... 44

Features ............................................................................................ 45

Output Oversampling................................................................ 45

ED/HD Nonstandard Timing Mode........................................ 45

ED/HD Timing Reset ................................................................ 46

SD VCR FF/RW Sync ................................................................ 47

Vertical Blanking Interval ......................................................... 47

SD Subcarrier Frequency Registers.......................................... 47

SD NonInterlaced Mode............................................................ 48

SD Square Pixel Mode ............................................................... 48

Filters............................................................................................ 49

ED/HD Test Pattern Color Controls ....................................... 50

Color Space Conversion Matrix ............................................... 50

SD Luma and Color Control..................................................... 51

SD Hue Adjust Control.............................................................. 52

SD Brightness Detect ................................................................. 52

SD Brightness Control............................................................... 52

SD Input Standard Auto Detection.......................................... 52

Double Buffering........................................................................ 53

Programmable DAC Gain Control.......................................... 53

Gamma Correction.................................................................... 53

ED/HD Sharpness Filter and Adaptive Filter Controls......... 55

ED/HD Sharpness Filter and Adaptive Filter Application

Examples...................................................................................... 56

SD Digital Noise Reduction...................................................... 57

SD Active Video Edge Control................................................. 59

External Horizontal and Vertical

Synchronization Control........................................................... 60

Low Power Mode........................................................................ 61

Cable Detection .......................................................................... 61

DAC Auto Power-Down............................................................ 61

Pixel and Control Port Readback............................................. 61

Reset Mechanisms...................................................................... 61

Printed Circuit Board Layout and Design .................................. 62

DAC Configurations.................................................................. 62

Video Output Buffer and Optional Output Filter.................. 62

Printed Circuit Board (PCB) Layout ....................................... 63

Typical Application Circuit....................................................... 65

Appendix 1–Copy Generation Management System ................ 66

SD CGMS .................................................................................... 66

ED CGMS.................................................................................... 66

HD CGMS................................................................................... 66

CGMS CRC Functionality ........................................................ 66

Appendix 2–SD Wide Screen Signaling ...................................... 69

Rev. 0 | Page 2 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Appendix 3–SD Closed Captioning..............................................70

Appendix 4–Internal Test Pattern Generation............................71

SD Test Patterns...........................................................................71

ED/HD Test Patterns ..................................................................71

Appendix 5–SD Timing..................................................................72

Appendix 6–HD Timing ................................................................77

Appendix 7–Video Output Levels.................................................78

SD YPrPb Output Levels—SMPTE/EBU N10........................78

ED/HD YPrPb Output Levels ...................................................79

SD/ED/HD RGB Output Levels................................................80

SD Output Plots ..........................................................................81

Appendix 8–Video Standards........................................................82

Appendix 9–Configuration Scripts...............................................84

Standard Definition....................................................................84

Enhanced Definition ..................................................................90

High Definition...........................................................................92

Outline Dimensions........................................................................95

Ordering Guide ...........................................................................96

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 96

ADV7390/ADV7391/ADV7392/ADV7393

(YPrPb/RGB) analog outputs in either standard-definition (SD)

or high-definition (HD) video formats.

DETAILED FEATURES

High definition (HD) programmable features

(720p/1080i/1035i)

4× oversampling (297 MHz)

Internal test pattern generator

Color and black bar, hatch, flat field/frame

Fully programmable YCrCb to RGB matrix

Gamma correction

Optimized for low power operation, occupying a minimal

footprint and requiring few external components, these

encoders are ideally suited to portable and power sensitive

applications requiring TV-Out functionality. Cable detection

and DAC auto power-down features ensure that power

consumption is kept to a minimum.

Programmable adaptive filter control

Programmable sharpness filter control

CGMS (720p/1080i) and CGMS Type B (720p/1080i)

Dual data rate (DDR) input support

EIA/CEA-861B compliance support

Enhanced definition (ED) programmable features

(525p/625p)

The ADV7390/ADV7391 have an 8-bit video input port that

supports SD video formats over a SDR interface and HD video

formats over a DDR interface.

The ADV7392/ADV7393 have a 16-bit video input port that

can be configured in a variety of ways. SD RGB input is

supported.

8× oversampling (216 MHz output)

Internal test pattern generator

Color and black bar, hatch, flat field/frame

Individual Y and PrPb output delay

Gamma correction

Programmable adaptive filter control

Fully programmable YCrCb to RGB matrix

Undershoot limiter

Macrovision Rev 1.2 (525p/625p)

CGMS (525p/625p) and CGMS Type B (525p)

Dual data rate (DDR) input support

EIA/CEA-861B compliance support

Standard definition (SD) programmable features

16× oversampling (216 MHz)

All members of the family support embedded EAV/SAV timing

codes, external video synchronization signals and the I²C and

SPI communication protocols.

Table 1 lists the video standards directly supported by the

ADV739x family.

Table 1. Standards Directly Supported by the ADV739x¹

Frame

Clock Input

(MHz)

Resolution

720 × 240

720 × 288

720 × 480

I/P²Rate (Hz)

Standard

P

I

59.94

50

29.97

27

ITU-R

BT.601/656

720 × 576

720 × 480

720 × 576

I

25

27

ITU-R

BT.601/656

NTSC Square

Pixel

PAL Square

Pixel

Internal test pattern generator

Color and black bar

Controlled edge rates for start and end of active video

Individual Y and PrPb output delay

Undershoot limiter

29.97

25

24.54

29.5

720 × 483

720 × 576

720 × 483

720 × 576

1920 × 1035

1280 × 720

P

I

59.94

50

59.94

50

30

29.97

60, 50, 30,

25, 24

27

74.25

74.1758

74.25

SMPTE 293M

BTA T-1004

Gamma correction

Digital noise reduction (DNR)

ITU-R BT.1358

ITU-R BT.1362

SMPTE 240M

SMPTE 296M

Multiple chroma and luma filters

Luma-SSAF™ filter with programmable gain/attenuation

PrPb SSAF™

Separate pedestal control on component and

composite/S-Video output

VCR FF/RW sync mode

Macrovision Rev 7.1.L1

Copy generation management system (CGMS)

Wide screen signaling (WSS)

Closed captioning

I

P

1280 × 720

P

23.97,

74.1758

SMPTE 296M

59.94, 29.97

1920 × 1080

I

P

30, 25

29.97

30, 25, 24

23.98, 29.97 74.1758

24 74.25

74.25

74.1758

74.25

SMPTE 274M

ITU-R BT.709-

5

EIA/CEA-861B compliance support

GENERAL DESCRIPTION

The ADV7390/ADV7391/ADV7392/ADV7393 are a family of

high speed, digital-to-analog video encoders on single

monolithic chips. Three 2.7 V/3.3 V 10-bit video DACs provide

¹Other standards are supported in the ED/HD nonstandard timing mode.

²I = interlaced, P = progressive.

support for composite (CVBS), S-Video (YC), or component

Rev. 0 | Page 4 of 96

ADV7390/ADV7391/ADV7392/ADV7393

SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 2.

Parameter

Conditions

Min

Typ

Max

Unit

SUPPLY VOLTAGES

V_DD

V_{DD_IO}

PV_DD

V_AA

1.71

2.97

1.71

2.6

1.8

3.3

1.8

3.3

1.89

3.63

1.89

3.465

V

POWER SUPPLY REJECTION RATIO

0.002

%/%

INPUT CLOCK SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 3.

Parameter

f_CLKIN

Conditions¹

SD/ED

Min

Typ

27

54

Max

Unit

MHz

ED (at 54 MHz)

HD

74.25

CLKIN High Time, t₉

CLKIN Low Time, t₁₀

CLKIN Peak-to-Peak Jitter Tolerance

40

% of one clock cycle

ns

2

¹SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.

ANALOG OUTPUT SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 4.

Parameter

Conditions

Min

Typ

34.6

4.3

Max

Unit

mA

%

V

pF

ns

Full-Drive Output Current

Low Drive Output Current

DAC-to-DAC Matching

Output Compliance, V_OC

Output Capacitance, C_OUT

Analog Output Delay¹

DAC Analog Output Skew

R_SET= 510 Ω, R_L= 37.5 Ω

R_SET= 4.12 kΩ, R_L= 300 Ω

DAC 1, DAC 2, DAC 3

33

37

2.0

0

1.4

10

6

1

DAC 1, DAC 2, DAC 3

ns

¹Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.

Rev. 0 | Page 5 of 96

ADV7390/ADV7391/ADV7392/ADV7393

DIGITAL INPUT/OUTPUT SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 5.

Parameter

Conditions

Min

Typ

4

Max

Unit

V

μA

pF

V

μA

pF

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Leakage Current, I_IN

Input Capacitance, C_IN

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

2.0

0.8

10

V_IN= V_{DD_IO}

I_SOURCE= 400 μA

I_SINK= 3.2 mA

V_IN= 0.4 V, 2.4 V

2.4

0.4

1

4

MPU PORT TIMING SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 6.

Parameter

MPU PORT, I²C MODE¹

Conditions

Min

Typ

Max

Unit

See Figure 15

SCL Frequency

SCL High Pulse Width, t₁

SCL Low Pulse Width, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDA, SCL Rise Time, t₆

SDA, SCL Fall Time, t₇

0

400

kHz

μs

ns

μs

0.6

1.3

0.6

100

300

Setup Time (Stop Condition), t₈

MPU PORT, SPI MODE¹

0.6

See Figure 16

SCLK Frequency

0

10

35

40

MHz

ns

SPI_SS to SCLK Setup Time, t₁

SCLK High Pulse Width, t₂

SCLK Low Pulse Width, t₃

Data Access Time after SCLK Falling Edge, t₄

Data Setup Time prior to SCLK Rising Edge, t₅

Data Hold Time after SCLK Rising Edge, t₆

SPI_SS to SCLK Hold Time, t₇

SPI_SS to MISO High Impedance, t₈

20

50

ns

20

0

ns

¹Guaranteed by characterization.

Rev. 0 | Page 6 of 96

ADV7390/ADV7391/ADV7392/ADV7393

DIGITAL TIMING SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 7.

Parameter

VIDEO DATA AND VIDEO CONTROL PORT^{2, 3}

Data Input Setup Time, t₁₁

Conditions¹

Min

Typ

Max

Unit

4

SD

2.1

2.3

1.7

1.0

1.1

1.0

2.1

2.3

1.7

1.0

1.1

1.0

ns

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

4

Data Input Hold Time, t₁₂

4

Control Input Setup Time, t₁₁

4

Control Input Hold Time, t₁₂

4

Control Output Access Time, t₁₃

12

10

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)

SD

4

Control Output Hold Time, t₁₄

4.0

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 3.5

PIPELINE DELAY⁵

SD¹

CVBS/YC Outputs (2×)

CVBS/YC Outputs (8×)

CVBS/YC Outputs (16×)

Component Outputs (2×)

Component Outputs (8×)

Component Outputs (16×)

ED¹

SD oversampling disabled

SD oversampling enabled

SD oversampling disabled

SD oversampling enabled

68

79

67

78

69

84

clock cycles

Component Outputs (1×)

Component Outputs (4×)

Component Outputs (8×)

HD¹

ED oversampling disabled

ED oversampling enabled

41

49

46

clock cycles

Component Outputs (1×)

Component Outputs (2×)

Component Outputs (4×)

RESET CONTROL

HD oversampling disabled

HD oversampling enabled

40

42

44

clock cycles

RESET Low Time

100

ns

¹SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

²Video Data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.

³Video Control:

and

.

HSYNC

VSYNC

⁴Guaranteed by characterization.

⁵Guaranteed by design.

Rev. 0 | Page 7 of 96

ADV7390/ADV7391/ADV7392/ADV7393

VIDEO PERFORMANCE SPECIFICATIONS

Table 8.

Parameter

Conditions

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution

10

Bits

Integral Nonlinearity (INL)¹

Differential Nonlinearity (DNL)^{1, 2}

STANDARD DEFINTION (SD) MODE

Luminance Nonlinearity

Differential Gain

R_SET= 510 Ω, R_L= 37.5 Ω

0.5

LSBs

0.5

0.6

58

%

Degrees

dB

NTSC

Luma ramp

Differential Phase

Signal-to-Noise Ratio (SNR)³

Flat field full bandwidth

75

dB

ENHANCED DEFINITION (ED) MODE

Luma Bandwidth

Chroma Bandwidth

12.5

5.8

MHz

HIGH DEFINITION (HD) MODE

Luma Bandwidth

Chroma Bandwidth

30.0

13.75

MHz

¹Measured on DAC 1, DAC 2, and DAC 3.

²Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal

step value. For −ve DNL, the actual step value lies below the ideal step value.

³Measured on the ADV7392/ADV7393 operating in 10-bit input mode.

POWER SPECIFICATIONS

Table 9.

Parameter

Conditions

Min

Typ

Max

Unit

NORMAL POWER MODE^{1, 2}

3

I_DD

SD (16× oversampling enabled), CVBS

SD (16× oversampling enabled), YPrPb

ED (8× oversampling enabled)⁴

33

68

59

81

1

50

122

4

mA

HD (4× oversampling enabled)⁴

I_{DD_IO}

5

I_AA

1 DAC enabled

All DACs enabled

I_PLL

SLEEP MODE

I_DD

I_AA

I_{DD_IO}

I_PLL

5

μA

0.3

0.2

0.1

¹R_SET= 510 Ω (all DACs operating in full-drive mode).

²75% color bar test pattern applied to pixel data pins.

³I_DDis the continuous current required to drive the digital core.

⁴Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.

⁵I_AAis the total current required to supply all DACs.

Rev. 0 | Page 8 of 96

ADV7390/ADV7391/ADV7392/ADV7393

TIMING DIAGRAMS

The following abbreviations are used in Figure 2 to Figure 9.

In addition, refer to Table 30 for the ADV7390/ADV7391 input

configuration and Table 31 for the ADV7392/ADV7393 input

configuration.

•

t₉= Clock high time

t₁₀= Clock low time

t₁₁= Data setup time

t₁₂= Data hold time

t₁₃= Control output access time

t₁₄= Control output hold time

CLKIN

t₁₂

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

IN SLAVE MODE

Y0

t₁₁

Y1

Y2

PIXEL PORT

Cb0

Cr0

Cb2

t₁₃

Cr2

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

Figure 2. SD Input, 8-/10-Bit 4:2:2 YCrCb (Input Mode 000)

CLKIN

t₉

t

t₁₂

10

CONTROL

INPUTS

HSYNC

VSYNC

IN SLAVE MODE

Y2

Y0

Y1

Y3

PIXEL PORT

Cb2

Cb0

Cr0

Cr2

t₁₁

t₁₃

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

Figure 3. SD Input, 16-Bit 4:2:2 YCrCb (Input Mode 000)

Rev. 0 | Page 9 of 96

ADV7390/ADV7391/ADV7392/ADV7393

CLKIN

t₉

t

t₁₂

10

CONTROL

INPUTS

HSYNC

VSYNC

IN SLAVE MODE

Y2

Y0

Y1

Y3

PIXEL PORT

Cb2

Cb0

Cr0

Cr2

t₁₁

t₁₃

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

Figure 4. SD Input, 16-Bit 4:4:4 RGB (Input Mode 000)

CLKIN

t₁₂

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

PIXEL PORT

G0

B0

G1

B1

G2

B2

t₁₁

PIXEL PORT

R0

R1

R2

CONTROL

OUTPUTS

t₁₄

t₁₃

Figure 5. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb (Input Mode 001)

CLKIN*

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

PIXEL PORT

Cb0

t₁₂

Y0

Cr0

Y1

t₁₂

Cb2

Y2

Cr2

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.

HSYNC VSYNC

), Input Mode 010

Figure 6. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (

/

Rev. 0 | Page 10 of 96

ADV7390/ADV7391/ADV7392/ADV7393

CLKIN*

t₉

t₁₀

PIXEL PORT

3FF

00

XY

Cb0

Y0

Cr0

Y1

t₁₂

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.

Figure 7. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010

CLKIN

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

Cb0

Y0

Cr0

Y1

Cb2

Cr2

PIXEL PORT

Y2

t₁₂

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

HSYNC VSYNC

Figure 8. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (

/

), Input Mode 111

CLKIN

t₉

t₁₀

PIXEL PORT

3FF

00

XY

Cb0

Y0

Cr0

Y1

t₁₂

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

Figure 9. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111

Rev. 0 | Page 11 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

PIXEL PORT*

Y2

Y3

Y0

Y1

Cb0 Cr0 Cb2

Cr2

a

a = AS PER RELEVANT STANDARD.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME

EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

/

Figure 10. ED-SDR, 16-Bit 4:2:2 YCrCb (

) Input Timing Diagram

Y OUTPUT

b

HSYNC

VSYNC

Cr0

Y1

Cb0

Y0

PIXEL PORT

a

a(MIN) = 244 CLOCK CYCLES FOR 525p.

a(MIN) = 264 CLOCK CYCLES FOR 625p.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME

EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

) Input Timing Diagram

Figure 11. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (

/

Rev. 0 | Page 12 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Y OUTPUT

b

HSYNC

VSYNC

Y2

Y3

Y0

Y1

PIXEL PORT

Cb0 Cr0 Cb2

Cr2

a

a = AS PER RELEVANT STANDARD.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

/

Figure 12. HD-SDR, 16-Bit 4:2:2 YCrCb (

) Input Timing Diagram

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

Cr0

Y1

Cb0

Y0

a

a = AS PER RELEVANT STANDARD.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

) Input Timing Diagram

Figure 13. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (

/

Rev. 0 | Page 13 of 96

ADV7390/ADV7391/ADV7392/ADV7393

HSYNC

VSYNC

Cr

Y

PIXEL PORT

Cb

Y

PAL = 264 CLOCK CYCLES

NTSC = 244 CLOCK CYCLES

Figure 14. SD Input Timing Diagram (Timing Mode 1)

t₅

t₃

SDA

t₆

t₁

SCL

t₂

t₇

t₄

t₈

Figure 15. MPU Port Timing Diagram (I²C Mode)

SPI_SS

SCLK

t₂t₃

t₁

t₇

t₅

t₆

D3

MOSI

MISO

D6

D5

X

D4

D2

X

D1

X

D0

X

D7

X

t₄

t₈

X

D7

D6

D5

D4

D3

D2

D1

D0

Figure 16. MPU Port Timing Diagram (SPI Mode)

Rev. 0 | Page 14 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 10.

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter¹

Rating

V_AAto AGND

V_DDto DGND

PV_DDto PGND

V_{DD_IO}to GND_IO

V_AAto V_DD

V_DDto PV_DD

V_{DD_IO}to V_DD

AGND to DGND

AGND to PGND

AGND to GND_IO

DGND to PGND

DGND to GND_IO

PGND to GND_IO

Digital Input Voltage to GND_IO

Analog Outputs to AGND

Storage Temperature Range (t_S)

Junction Temperature (t_J)

Lead Temperature (Soldering, 10 sec)

−0.3 V to +3.9 V

−0.3 V to +2.3 V

−0.3 V to +3.9 V

−0.3 V to +2.2 V

−0.3 V to +0.3 V

−0.3 V to +2.2 V

−0.3 V to +0.3 V

−0.3 V to V_{DD_IO}+ 0.3 V

−0.3 V to V_AA

Table 11. Thermal Resistance¹

Package Type

32-Lead LFCP

40-Lead LFCSP

2

θ_JA

27

26

θ_JC

32

Unit

°C/W

¹Values are based on a JEDEC 4 layer test board.

²With the exposed metal paddle on the underside of the LFCSP soldered to

the PCB ground.

The ADV739x is a Pb-free product. The lead finish is 100% pure

Sn electroplate. The device is RoHS compliant, suitable for Pb-

free applications up to 255°C ( 5°C) IR reflow (JEDEC STD-20).

The ADV739x is backward-compatible with conventional SnPb

soldering processes. The electroplated Sn coating can be

soldered with SnPb solder pastes at conventional reflow

temperatures of 220°C to 235°C.

−60°C to +100°C

150°C

260°C

ESD CAUTION

¹Analog output short circuit to any power supply or common can be of an

indefinite duration.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 15 of 96

ADV7390/ADV7391/ADV7392/ADV7393

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

R

1

2

3

4

5

6

7

8

24

V

DD_IO

P2

P3

SET

R

SET

PIN 1

DD_IO

P4

1

2

30

PIN 1

INDICATOR

23 COMP

22 DAC 1

21 DAC 2

20 DAC 3

29 COMP

28 DAC 1

27 DAC 2

26 DAC 3

P5

3

P6

4

ADV7392/

ADV7393

TOP VIEW

(Not to Scale)

P4

ADV7390/

ADV7391

TOP VIEW

(Not to Scale)

P7

DD

5

V

DD

V

6

25 V

AA

DGND

P5

19

18 AGND

17 PV

V

7

24

23

22

21

AGND

DGND

AA

8

P8

PV

DD

9

P9

EXT_LF

PGND

P6

DD

10

P10

Figure 17. ADV7390/ADV7391 Pin Configuration

Figure 18. ADV7392/ADV7393 Pin Configuration

Table 12. Pin Function Descriptions

Pin Number

ADV7390/91 ADV7392/93

Input/

Output Description

Mnemonic

9 to 7, 4 to 2,

31, 30

P7 to P0

I

8-Bit Pixel Port (P7 to P0). P0 is the LSB. Refer to Table 30 for input

modes (ADV7390/ADV7391).

18 to 15, 11 to 8, 5 P15 to P0

to 2, 39 to 37, 34

I

16-Bit Pixel Port (P15 to P0). P0 is the LSB. Refer to Table 31 for input

modes (ADV7392/ADV7393).

13

27

19

CLKIN

I

Pixel Clock Input for HD (74.25 MHz), ED¹(27 MHz or 54 MHz), or

SD (27 MHz).

Horizontal Synchronization Signal. This pin can also be configured to

output an SD, ED, or HD horizontal synchronization signal. See the

External Horizontal and Vertical Synchronization Control section.

33

HSYNC

I/O

26

25

24

32

31

30

VSYNC

SFL/MISO

R_SET

I/O

I

Vertical Synchronization Signal. This pin can also be configured to

output an SD, ED, or HD vertical synchronization signal. See the

External Horizontal and Vertical Synchronization Control section.

Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data

Output (MISO). The SFL input is used to drive the color subcarrier

DDS system, timing reset, or subcarrier reset.

Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For

full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor

must be connected from R_SETto AGND. For low drive operation (for

example, into a 300 Ω load), a 4.12 kΩ resistor must be connected

from R_SETto AGND.

23

22, 21, 20

12

11

10

29

28, 27, 26

14

13

12

COMP

DAC 1, DAC 2, DAC 3

SCL/MOSI

SDA/SCLK

ALSB/SPI_SS

O

I

I/O

I

Compensation Pin. Connect a 2.2 nF capacitor from COMP to V_AA.

DAC Outputs. Full-drive and low-drive capable DACs.

Multifunctional Pin: I²C Clock Input/SPI Data Input.

Multifunctional Pin: I²C Data Input/Output. Also, SPI clock input.

Multifunctional Pin: ALSB sets up the LSB²of the MPU I²C

address/SPI slave select (SPI_SS).

14

20

RESET

I

Resets the on-chip timing generator and sets the ADV739x into its

default mode.

19

5, 28

25

6, 35

V_AA

V_DD

P

Analog Power Supply (3.3 V).

Digital Power Supply (1.8 V). For dual-supply configurations, V_DDcan

be connected to other 1.8 V supplies through a ferrite bead or

suitable filtering.

1

17

1

23

V_{DD_IO}

PV_DD

P

Input/Output Digital Power Supply (3.3 V).

PLL Power Supply (1.8 V). For dual-supply configurations, PV_DDcan

be connected to other 1.8 V supplies through a ferrite bead or

suitable filtering.

Rev. 0 | Page 16 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Pin Number

ADV7390/91 ADV7392/93

Input/

Output Description

Mnemonic

EXT_LF

PGND

AGND

DGND

16

22

I

External Loop Filter for the Internal PLL.

15

21

G

PLL Ground Pin.

Analog Ground Pin.

Digital Ground Pin.

Input/Output Supply Ground Pin.

18

24

6, 29

32

7, 36

40

GND_IO

¹ED = enhanced definition = 525p and 625p.

²LSB = least significant bit. In the ADV7390, setting the LSB to 0 sets the I²C address to 0xD4. Setting it to 1 sets the I²C address to 0xD6.

In the ADV7391, setting the LSB to 0 sets the I²C address to 0x54. Setting it to 1 sets the I²C address to 0x56.

Rev. 0 | Page 17 of 96

ADV7390/ADV7391/ADV7392/ADV7393

TYPICAL PERFORMANCE CHARACTERISTICS

Y RESPONSE IN ED 8× OVERSAMPLING MODE

EDPr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

0

1.0

0.5

–10

–20

–30

–40

–50

–60

–70

–80

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 19. ED 8× Oversampling, PrPb Filter (Linear) Response

Figure 22. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)

HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

10

EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

18.5

37.0

55.5

74.0

92.5

111.0 129.5 148.0

FREQUENCY (MHz)

Figure 20. ED 8× Oversampling, PrPb Filter (SSAF) Response

Figure 23. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:2:2 Input)

HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE

Y RESPONSE IN ED 8× OVERSAMPLING MODE

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–100

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

10 20 30 40 50 60 70 80 90 100 110 120 130 140

FREQUENCY (MHz)

Figure 21. ED 8× Oversampling, Y Filter Response

Figure 24. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:4:4 Input)

Rev. 0 | Page 18 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Y RESPONSE IN HD 4× OVERSAMPLING MODE

10

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

2

4

6

8

10

12

0

18.5

37.0

55.5

74.0

92.5

111.0 129.5 148.0

FREQUENCY (MHz)

Figure 25. HD 4× Oversampling, Y Filter Response

Figure 28. SD PAL, Luma Low-Pass Filter Response

Y PASS BAND IN HD 4x OVERSAMPLING MODE

3.0

0

–10

–20

–30

–40

–50

–60

–70

1.5

0

–1.5

–3.0

–4.5

–6.0

–7.5

–9.0

–10.5

–12.0

2

4

6

8

10

27.750

46.250

30.063 32.375 34.688 37.000 39.312 41.625 43.937

FREQUENCY (MHz)

Figure 29. SD NTSC, Luma Notch Filter Response

Figure 26. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

2

4

6

8

10

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 30. SD PAL, Luma Notch Filter Response

Figure 27. SD NTSC, Luma Low-Pass Filter Response

Rev. 0 | Page 19 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Y RESPONSE IN SD OVERSAMPLING MODE

5

4

0

–10

–20

–30

–40

–50

–60

–70

–80

3

2

1

0

–1

5

6

7

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

1

2

3

4

FREQUENCY (MHz)

Figure 31. SD 16× Oversampling, Y Filter Response

Figure 34. SD Luma SSAF Filter, Programmable Gain

1

0

–10

–20

–30

–40

–50

–60

–70

–1

–2

–3

–4

–5

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 35. SD Luma SSAF Filter, Programmable Attenuation

Figure 32. SD Luma SSAF Filter Response up to 12 MHz

0

4

2

–10

0

–20

–30

–40

–50

–60

–70

–2

–4

–6

–8

–10

–12

0

2

4

6

8

10

12

0

1

2

3

4

5

6

7

FREQUENCY (MHz)

Figure 36. SD Luma CIF Low-Pass Filter Response

Figure 33. SD Luma SSAF Filter, Programmable Responses

Rev. 0 | Page 20 of 96

ADV7390/ADV7391/ADV7392/ADV7393

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 37. SD Luma QCIF Low-Pass Filter Response

Figure 40. SD Chroma 1.3 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

10

12

0

2

4

6

8

FREQUENCY (MHz)

Figure 41. SD Chroma 1.0 MHz Low-Pass Filter Response

Figure 38. SD Chroma 3.0 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

10

12

0

2

4

6

8

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 42. SD Chroma 0.65 MHz Low-Pass Filter Response

Figure 39. SD Chroma 2.0 MHz Low-Pass Filter Response

Rev. 0 | Page 21 of 96

ADV7390/ADV7391/ADV7392/ADV7393

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 43. SD Chroma CIF Low-Pass Filter Response

Figure 44. SD Chroma QCIF Low-Pass Filter Response

Rev. 0 | Page 22 of 96

ADV7390/ADV7391/ADV7392/ADV7393

MPU PORT DESCRIPTION

Devices such as a microprocessor can communicate with the

ADV739x through one of the following protocols:

The bits are transferred from MSB down to LSB. The peripheral

that recognizes the transmitted address responds by pulling the

data line low during the ninth clock pulse. This is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is

when the device monitors the SDA and SCL lines waiting for

the start condition and the correct transmitted address. The

•

2-wire serial (I²C-compatible) bus

4-wire serial (SPI-compatible) bus

After power-up or reset, the MPU port is configured for I²C

operation. SPI operation can be invoked at any time by

following the procedure outlined in the SPI Operation section.

W

R/ bit determines the direction of the data.

I²C OPERATION

Logic 0 on the LSB of the first byte means that the master writes

information to the peripheral. Logic 1 on the LSB of the first byte

means that the master reads information from the peripheral.

The ADV739x supports a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. This port

operates in an open-drain configuration. Two inputs, serial data

(SDA) and serial clock (SCL), carry information between any

device connected to the bus and the ADV739x. Each slave

device is recognized by a unique address. The ADV739x has

four possible slave addresses for both read and write operations.

These are unique addresses for each device and are illustrated in

Figure 45 and Figure 46. The LSB either sets a read or write

operation. Logic 1 corresponds to a read operation, while Logic

0 corresponds to a write operation. A1 is controlled by setting

The ADV739x acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

W

addresses plus the R/ bit. It interprets the first byte as the

device address and the second byte as the starting subaddress.

There is a subaddress auto-increment facility. This allows data

to be written to or read from registers in ascending subaddress

sequence starting at any valid subaddress. A data transfer is

always terminated by a stop condition. The user can also access

any unique subaddress register on a one-by-one basis without

updating all the registers.

SPI_SS

the ALSB/

pin of the ADV739x to Logic 0 or Logic 1.

1

0

1

0

1

A1

X

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, they cause an

immediate jump to the idle condition. During a given SCL high

period, the user should only issue a start condition, a stop

condition, or a stop condition followed by a start condition. If

an invalid subaddress is issued by the user, the ADV739x does

not issue an acknowledge and does return to the idle condition.

If the user utilizes the auto-increment method of addressing the

encoder and exceeds the highest subaddress, the following

actions are taken:

ADDRESS

CONTROL

SET UP BY

ALSB/SPI_SS

READ/WRITE

CONTROL

0

1

WRITE

READ

Figure 45. ADV7390/ADV7392 Slave Address = 0xD4 or 0xD6

0

1

0

1

0

1

A1

X

ADDRESS

CONTROL

•

In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge.

This indicates the end of a read. A no acknowledge condition

occurs when the SDA line is not pulled low on the ninth pulse.

In write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by

the ADV739x, and the part returns to the idle condition.

SET UP BY

ALSB/SPI_SS

READ/WRITE

CONTROL

•

0

1

WRITE

READ

Figure 46. ADV7391/ADV7393 Slave Address = 0x54 or 0x56

To control the various devices on the bus, use the following

protocol. The master initiates a data transfer by establishing a

start condition, defined by a high-to-low transition on SDA

while SCL remains high. This indicates that an address/data

stream follows. All peripherals respond to the start condition

Figure 47 shows an example of data transfer for a write sequence

and the start and stop conditions. Figure 48 shows bus write

and read sequences.

W

and shift the next eight bits (7-bit address + R/ bit).

Rev. 0 | Page 23 of 96

ADV7390/ADV7391/ADV7392/ADV7393

SDA

SCL

S

P

9

1–7

9

1–7

8

1–7

8

START ADDR R/W ACK SUBADDRESS ACK

DATA

ACK

STOP

Figure 47. I²C Data Transfer

WRITE

S

SLAVE ADDR A(S)

LSB = 0

SUBADDR

A(S)

DATA

A(S)

DATA

A(M)

A(S) P

SEQUENCE

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S)

A(S)

S

SLAVE ADDR A(S)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A (S) = NO-ACKNOWLEDGE BY SLAVE

A (M) = NO-ACKNOWLEDGE BY MASTER

Figure 48. I²C Read and Write Sequence

SPI OPERATION

The ADV739x supports a 4-wire serial (SPI-compatible) bus

connecting multiple peripherals. Two inputs, master out slave in

(MOSI) and serial clock (SCLK), and one output, master in

slave out (MISO), carry information between a master SPI

peripheral on the bus and the ADV739x. Each slave device on

the bus has a slave select pin that is connected to the master SPI

peripheral by a unique slave select line. As such, slave device

addressing is not required.

There is a subaddress auto-increment facility. This allows data

to be written to or read from registers in ascending subaddress

sequence starting at any valid subaddress. The user can also

access any unique subaddress register on a one-by-one basis.

In a write data transfer, 8-bit data bytes are written to the

ADV739x, MSB first, on the MOSI line immediately after the

starting subaddress. The data bytes are clocked into the

ADV739x on the rising edge of SCLK. When all data bytes have

To invoke SPI operation, a master SPI peripheral (for example, a

microprocessor) should issue three low pulses on the ADV739x

been written, the master completes the transfer by driving and

SPI_SS

holding the ADV739x ALSB/

In a read data transfer, after the subaddress has been clocked in

SPI_SS

pin high.

SPI_SS

edge on the ALSB/

ALSB/

pin. When the encoder detects the third rising

SPI_SS

pin, it automatically switches to SPI

on the MOSI line, the ALSB/

for at least one clock cycle. Then, the ALSB/

and held low again. On the first SCLK rising edge after

SPI_SS

pin is driven and held high

communication mode. The ADV739x remains in SPI commu-

nication mode until a hardware reset or power-down occurs.

SPI_SS

pin is driven

To control the ADV739x, use the following protocol for both read

and write transactions. First, the master initiates a data transfer by

ALSB/

has been driven low, the read command, defined

as 0xD5, is written, MSB first, to the ADV739x over the MOSI

line. Subsequently, 8-bit data bytes are read from the ADV739x,

MSB first, on the MISO line. The data bytes are clocked out of

the part on the falling edge of SCLK. When all data bytes have

been read, the master completes the transfer by driving and

SPI_SS

driving and holding the ADV739x ALSB/

pin low. On the

SPI_SS

first SCLK rising edge after ALSB/

has been driven low,

the write command, defined as 0xD4, is written to the ADV739x

over the MOSI line. The second byte written to the MOSI line is

interpreted as the starting subaddress. Data on the MOSI line is

written MSB first and clocked on the rising edge of SCLK.

SPI_SS

holding the ADV739x ALSB/

pin high.

Rev. 0 | Page 24 of 96

ADV7390/ADV7391/ADV7392/ADV7393

REGISTER MAP

A microprocessor can read from or write to all registers of the

ADV739x via the MPU port, except for registers that are

specified as read-only or write-only registers.

REGISTER PROGRAMMING

Table 13 to Table 27 describe the functionality of each register.

All registers can be read from as well as written to, unless

otherwise stated.

The subaddress register determines the register accessed by the

next read or write operation. All communication through the

MPU port starts with an access to the subaddress register. A

read/write operation is then performed from/to the target

address, incrementing to the next address until the transaction

is complete.

SUBADDRESS REGISTER (SR7 TO SR0)

The subaddress register is an 8-bit write-only register. After the

MPU port is accessed and a read/write operation is selected, the

subaddress is set up. The subaddress register determines which

register performs the next operation.

Table 13. Register 0x00

SR7 to

Bit Number

Register

Setting

Reset

Value

0x12

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x00

Power

Mode

Register

Sleep Mode. With this control enabled, the current consumption is

reduced to μA level. All DACs and the internal PLL circuit are

disabled. Registers can be read from and written to in sleep mode.

0

Sleep

mode off.

Sleep

1

mode on.

PLL and Oversampling Control. This control allows the internal PLL

circuit to be powered down and the oversampling to be switched off.

0

1

PLL on.

PLL off.

DAC 3: Power on/off.

DAC 2: Power on/off.

DAC 1: Power on/off.

Reserved.

0

1

DAC 3 off.

DAC 3 on.

DAC 2 off.

DAC 2 on.

DAC 1 off.

DAC 1 on.

0

1

0

1

0

Rev. 0 | Page 25 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 14. Register 0x01 to Register 0x09

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

0x01

Mode Select

Register

Reserved.

0

DDR Clock Edge Alignment.

Note: Only used for ED¹and

HD DDR modes.

0

Chroma clocked in on rising clock edge and

luma clocked in on falling clock edge.

Reserved.

Luma clocked in on rising clock edge and

chroma clocked in on falling clock edge.

0

1

0

1

Reserved.

0

Input Mode.

Note: See Reg. 0x30, Bits[7:3]

for ED/HD format selection.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SD input.

ED/HD-SDR input²

ED/HD-DDR input.

Reserved.

ED (at 54 MHz) input.

Reserved.

0

0x02

Mode

Register 0

Reserved.

Test Pattern Black Bar.³

0

Zero must be written to these bits.

Disabled.

Enabled.

0x20

0

1

Manual RGB Matrix Adjust.

Sync on RGB.

0

1

Disable manual RGB matrix adjust.

Enable manual RGB matrix adjust.

No sync.

Sync on all RGB outputs.

RGB component outputs.

YPrPb component outputs.

No sync output.

0

1

RGB/YPrPb Output Select.

SD Sync Output Enable.

ED/HD Sync Output Enable.

0

1

0

1

HSYNC

VSYNC

Output SD syncs on

No sync output.

and

pins.

0

1

HSYNC

VSYNC

Output ED/HD syncs on

pins.

and

0x03

0x04

ED/HD CSC

Matrix 0

x

LSBs for GY.

0x03

0xF0

ED/HD CSC

Matrix 1

LSBs for RV.

LSBs for BU.

LSBs for GV.

LSBs for GU.

Bits[9:2] for GY.

x

0x05

0x06

0x07

0x08

0x09

ED/HD CSC

Matrix 2

x

0x4E

0x0E

0x24

0x92

0x7C

ED/HD CSC

Matrix 3

x

Bits[9:2] for GU.

Bits[9:2] for GV.

Bits[9:2] for BU.

Bits[9:2] for RV.

ED/HD CSC

Matrix 4

ED/HD CSC

Matrix 5

ED/HD CSC

Matrix 6

¹ED = enhanced definition = 525p and 625p.

²Available on the ADV7392/ADV7393 (40-pin devices) only.

³Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).

Rev. 0 | Page 26 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 15. Register 0x0B to Register 0x17

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

0

…

0

6

0

…

0

5

0

…

1

4

0

3

0

2

0

…

1

0

1

…

1

0

1

0

…

1

Register Setting

0%

+0.018%

+0.036%

…

0x0B

DAC 1, DAC 2,

DAC 3 Output

Level

Positive Gain to DAC Output Voltage.

0

…

1

…

1

+7.382%

+7.5%

0

1

0

Negative Gain to DAC Output

Voltage.

1

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

1

…

1

0

1

0

…

1

−7.5%

−7.382%

−7.364%

…

−0.018%

0x0D

DAC Power

Mode

DAC 1 Low Power Mode.

DAC 2 Low Power Mode.

DAC 3 Low Power Mode.

SD/ED Oversample Rate Select.

Reserved.

0

1

DAC 1 low power disabled 0x00

DAC 1 low power enabled

DAC 2 low power disabled

DAC 2 low power enabled

DAC 3 low power disabled

DAC 3 low power enabled

SD = 16×, ED = 8×

0

1

0

1

0

1

SD = 8×, ED = 4×

0

0x10

Cable Detection DAC 1 Cable Detect.

Read Only.

0

1

Cable detected on DAC 1 0x00

DAC 1 unconnected

DAC 2 Cable Detect.

Read Only.

0

1

Cable detected on DAC 2

DAC 2 unconnected

Reserved.

0

x

Unconnected DAC auto power-down.

0

1

DAC auto power-down

disable

DAC auto power-down

enable

Reserved.

0

x

0

x

0

x

0x13

Pixel Port

P[7:0] Readback (ADV7390/ADV7391).

x

Read only

0xXX

Readback A¹

P[15:8] Readback (ADV7392/ADV7393).

P[7:0] Readback (ADV7392/ADV7393).

0x14

0x16

Pixel Port

x

Read only

0xXX

Readback B¹

Control Port

Readback¹

Reserved.

VSYNC

HSYNC

x

Readback.

x

SFL/MISO Readback.

Reserved.

x

0x17

Software Reset

Reserved.

0

0x00

Software Reset.

0

1

Writing a 1 resets the

device; this is a self-

clearing bit

Reserved.

0

¹For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.

Rev. 0 | Page 27 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 16. Register 0x30

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

Note

0x30

ED/HD Mode

Register 1

ED/HD Output Standard.

0

EIA-770.2 output

EIA-770.3 output

ED

HD

0

1

0

EIA-770.1 output

Output levels for full

input range

1

Reserved

ED/HD Input

Synchronization Format.

0

1

External

,

HSYNC VSYNC

and field inputs¹

Embedded EAV/SAV

codes

ED/HD Input Mode.

0

1

0

1

0

1

0

1

0

1

SMPTE 293M, ITU-BT.1358 525p @ 59.94 Hz

Nonstandard timing mode

BTA-1004, ITU-BT.1362

ITU-BT.1358

ITU-BT.1362

525p @ 59.94 Hz

625p @ 50 Hz

SMPTE 296M-1,

SMPTE 274M-2

720p @

60 Hz/59.94 Hz

0

1

0

1

SMPTE 296M-3

SMPTE 296M-4,

SMPTE 274M-5

720p @ 50 Hz

720p @

30 Hz/29.97 Hz

0

1

0

1

SMPTE 296M-6

SMPTE 296M-7,

SMPTE 296M-8

720p @ 25 Hz

720p @

24 Hz/23.98 Hz

0

1

0

1

0

SMPTE 240M

1035i @

60 Hz/59.94 Hz

0

1

0

1

0

1

0

1

Reserved

SMPTE 274M-4,

SMPTE 274M-5

1080i @

30 Hz/29.97 Hz

0

1

0

1

SMPTE 274M-6

SMPTE 274M-7,

SMPTE 274M-8

1080i @ 25 Hz

1080p @

30 Hz/29.97 Hz

1

0

1

SMPTE 274M-9

SMPTE 274M-10,

SMPTE 274M-11

1080p @ 25 Hz

1080p @

24 Hz/23.98 Hz

1

0

1

0

ITU-R BT.709-5

Reserved

1080Psf @ 24 Hz

10011 to 11111

¹Synchronization can be controlled with a combination of either

and

inputs or

and field inputs, depending on Subaddress 0x34, Bit 6.

HSYNC

VSYNC

Rev. 0 | Page 28 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 17. Register 0x31 to Register 0x33

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Pixel data valid off

Pixel data valid on

4×

0x31

ED/HD Mode

Register 2

ED/HD Pixel Data Valid.

HD Oversample Rate Select.

ED/HD Test Pattern Enable.

ED/HD Test Pattern Hatch/Field.

0

1

2×

0

1

HD test pattern off

HD test pattern on

Hatch

0

1

Field/frame

Disabled

ED/HD Vertical Blanking Interval (VBI)

Open.

0

1

Enabled

ED/HD Undershoot Limiter.

0

1

0

1

0

1

Disabled

−11 IRE

−6 IRE

−1.5 IRE

ED/HD Sharpness Filter.

0

1

Disabled

Enabled

0x32

ED/HD Mode

Register 3

ED/HD Y Delay with Respect to Falling

0

1

0

1

0

1

0

1

0

0 clock cycles

1 clock cycle

2 clock cycles

3 clock cycles

4 clock cycles

0 clock cycles

1 clock cycle

2 clock cycles

3 clock cycles

4 clock cycles

Disabled

0x00

HSYNC

Edge of

.

ED/HD Color Delay with Respect to

HSYNC

0

1

0

1

0

1

0

1

0

Falling Edge of

.

ED/HD CGMS Enable.

0

1

Enabled

ED/HD CGMS CRC Enable.

ED/HD Cr/Cb Sequence.

0

1

Disabled

Enabled

0x33

ED/HD Mode

Register 4

0

1

HSYNC

0x68

Cb after falling edge of

Cr after falling edge of

Reserved.

0

0 must be written to this bit

8-bit input

10-bit input¹

ED/HD Input Format.

0

1

Sinc Compensation Filter on DAC 1,

DAC 2, DAC 3.

0

1

Disabled

Enabled

Reserved.

0

0 must be written to this bit

Disabled

Enabled

ED/HD Chroma SSAF Filter.

0

1

Reserved.

1

1 must be written to this bit

Disable

Enabled

ED/HD Double Buffering.

0

1

¹Available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. 0 | Page 29 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 18. Register 0x34 to Register 0x38

SR7 to

Bit Number

Reset

Value

0x48

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

0x34

ED/HD Mode

Register 5

ED/HD Timing Reset.

Internal ED/HD timing counters enabled

Resets the internal ED/HD timing counters

1

HSYNC

VSYNC

0

1

HSYNC

ED/HD

Control.

output control (refer to Table 50)

1

0

1

VSYNC

Control.

output control (refer to Table 51)

Reserved.

1

ED Macrovision Enable.²

0

1

ED Macrovision disabled

ED Macrovision enabled

0 must be written to this bit

Reserved.

0

VSYNC

0

1

0 = Field input

ED/HD

Input.

Input/Field

VSYNC

1 =

input

ED/HD Horizontal/Vertical

Counter Mode.³

0

1

Update field/line counter

Field/line counter free running

0x35

ED/HD Mode

Register 6

Reserved.

0

0x00

Reserved.

0

ED/HD Sync on PrPb.

0

1

Disabled

Enabled

ED/HD Color DAC Swap.

0

1

DAC 2 = Pb, DAC 3 = Pr

DAC 2 = Pr, DAC 3 = Pb

Gamma Correction Curve A

Gamma Correction Curve B

Disabled

ED/HD Gamma Correction

Curve Select.

0

1

ED/HD Gamma

Correction Enable.

0

1

Enabled

ED/HD Adaptive

Filter Mode.

0

1

Mode A

Mode B

ED/HD Adaptive

Filter Enable.

0

1

x

Disabled

Enabled

0x36

0x37

0x38

ED/HD Y Level⁴

ED/HD Cr Level⁴

ED/HD Test Pattern Y Level.

ED/HD Test Pattern Cr Level.

ED/HD Cb Level⁴ED/HD Test Pattern Cb Level.

x

Y level value

0xA0

0x80

Cr level value

Cb level value

¹Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.

²Applies to the ADV7390 and ADV7392 only.

³When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

⁴For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).

Rev. 0 | Page 30 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 19. Register 0x39 to Register 0x43

SR7 to

Bit Number

Reset

Register Setting Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x39

ED/HD Mode

Register 7

Reserved.

0

ED/HD EIA/CEA-861B

Synchronization Compliance.

0

1

Disabled

Enabled

Reserved.

0

0x40

ED/HD Sharpness

Filter Gain

ED/HD Sharpness Filter Gain

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

0x00

…

1

…

1

…

1

…

1

ED/HD Sharpness Filter Gain

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

0x41

0x42

0x43

ED/HD CGMS

Data 0

ED/HD CGMS Data Bits.

0

C19 C18 C17 C16 CGMS C19 to C16 0x00

ED/HD CGMS

Data 1

C15 C14 C13 C12 C11 C10 C9

C8

C0

CGMS C15 to C8

CGMS C7 to C0

0x00

ED/HD CGMS

Data 2

C7

C6

C5

C4

C3

C2

C1

Table 20. Register 0x44 to Register 0x57

SR7 to

Bit Number

Register

Reset

Value

0x00

SR0

Register

Bit Description

7

x

6

5

x

4

x

3

x

2

x

1

x

0

Setting

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

B0

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

ED/HD Gamma A0

ED/HD Gamma A1

ED/HD Gamma A2

ED/HD Gamma A3

ED/HD Gamma A4

ED/HD Gamma A5

ED/HD Gamma A6

ED/HD Gamma A7

ED/HD Gamma A8

ED/HD Gamma A9

ED/HD Gamma B0

ED/HD Gamma B1

ED/HD Gamma B2

ED/HD Gamma B3

ED/HD Gamma B4

ED/HD Gamma B5

ED/HD Gamma B6

ED/HD Gamma B7

ED/HD Gamma B8

ED/HD Gamma B9

ED/HD Gamma Curve A (Point 24).

ED/HD Gamma Curve A (Point 32).

ED/HD Gamma Curve A (Point 48).

ED/HD Gamma Curve A (Point 64).

ED/HD Gamma Curve A (Point 80).

ED/HD Gamma Curve A (Point 96).

ED/HD Gamma Curve A (Point 128).

ED/HD Gamma Curve A (Point 160).

ED/HD Gamma Curve A (Point 192).

ED/HD Gamma Curve A (Point 224).

ED/HD Gamma Curve B (Point 24).

ED/HD Gamma Curve B (Point 32).

ED/HD Gamma Curve B (Point 48).

ED/HD Gamma Curve B (Point 64).

ED/HD Gamma Curve B (Point 80).

ED/HD Gamma Curve B (Point 96).

ED/HD Gamma Curve B (Point 128).

ED/HD Gamma Curve B (Point 160).

ED/HD Gamma Curve B (Point 192).

ED/HD Gamma Curve B (Point 224).

x

B1

B2

B3

B4

B5

B6

B7

B8

B9

Rev. 0 | Page 31 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 21. Register 0x58 to Register 0x5D

SR7 to

Bit Number

Register

Setting

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Gain B = −1

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Gain B = −1

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x58

ED/HD Adaptive Filter Gain 1

ED/HD Adaptive Filter Gain 1,

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 1,

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

0x59

ED/HD Adaptive Filter Gain 2

ED/HD Adaptive Filter Gain 2,

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

0x00

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 2,

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

0x5A

ED/HD Adaptive Filter Gain 3

ED/HD Adaptive Filter Gain 3,

Value A.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

0x00

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 3,

Value B.

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

0x5B

0x5C

0x5D

ED/HD Adaptive Filter

Threshold A

ED/HD Adaptive Filter Threshold A.

ED/HD Adaptive Filter Threshold B.

ED/HD Adaptive Filter Threshold C.

x

Threshold A 0x00

Threshold B 0x00

Threshold C 0x00

ED/HD Adaptive Filter

Threshold B

x

ED/HD Adaptive Filter

Threshold C

Rev. 0 | Page 32 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 22. Register 0x5E to Register 0x6E

SR7 to

Bit Number

Register

Setting

Disabled

Enabled

Disabled

Enabled

H5 to H0

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

0x5E

ED/HD CGMS Type B

Register 0

ED/HD CGMS Type B

Enable.

ED/HD CGMS Type B

CRC Enable.

0

1

ED/HD CGMS Type B

Header Bits.

H5

H4

H3

H2

H1

H0

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

ED/HD CGMS Type B

Register 1

ED/HD CGMS Type B

Data Bits.

P7

P6

P5

P4

P3

P2

P1

P0

P7 to P0

0x00

ED/HD CGMS Type B

Register 2

ED/HD CGMS Type B

Data Bits.

P15

P23

P31

P39

P47

P55

P63

P71

P79

P87

P95

P14

P22

P30

P38

P46

P54

P62

P70

P78

P86

P94

P13

P21

P29

P37

P45

P53

P61

P69

P77

P85

P93

P12

P20

P28

P36

P44

P52

P60

P68

P76

P84

P92

P11

P19

P27

P35

P43

P51

P59

P67

P75

P83

P91

P10

P18

P26

P34

P42

P50

P58

P66

P74

P82

P90

P98

P9

P8

P15 to P8

ED/HD CGMS Type B

Register 3

ED/HD CGMS Type B

Data Bits.

P17

P25

P33

P41

P49

P57

P65

P73

P81

P89

P97

P16

P24

P32

P40

P48

P56

P64

P72

P80

P88

P96

P23 to P16

P31 to P24

P39 to P32

P47 to P40

P55 to P48

P63 to P56

P71 to P64

P79 to P72

P87 to P80

P95 to P88

P103 to P96

ED/HD CGMS Type B

Register 4

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 5

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 6

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 7

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 8

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 9

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 10

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 11

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 12

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 13

ED/HD CGMS Type B

Data Bits.

P103 P102 P101 P100 P99

ED/HD CGMS Type B

Register 14

ED/HD CGMS Type B

Data Bits.

P111 P110 P109 P108 P107 P106 P105 P104 P111 to P104 0x00

P119 P118 P117 P116 P115 P114 P113 P112 P119 to P112 0x00

P127 P126 P125 P124 P123 P122 P121 P120 P127 to P120 0x00

ED/HD CGMS Type B

Register 15

ED/HD CGMS Type B

Data Bits.

ED/HD CGMS Type B

Register 16

ED/HD CGMS Type B

Data Bits.

Rev. 0 | Page 33 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 23. Register 0x80 to Register 0x83

SR7 to

Bit Number

Reset

Value

0x10

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

0

1

0

1

Register Setting

NTSC

PAL B, PAL D, PAL G, PAL H, PAL I

PAL M

0x80

SD Mode

Register 1

SD Standard.

PAL N

SD Luma Filter.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LPF NTSC

LPF PAL

Notch NTSC

Notch PAL

Luma SSAF

Luma CIF

Luma QCIF

Reserved

SD Chroma Filter.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.3 MHz

0.65 MHz

1.0 MHz

2.0 MHz

Reserved

Chroma CIF

Chroma QCIF

3.0 MHz

0x82

SD Mode

Register 2

SD PrPb SSAF Filter.

SD DAC Output 1.

0

1

Disabled

Enabled

0x0B

0

1

Refer to Table 32 in the Output

Configuration section

Reserved.

0

SD Pedestal.

0

1

Disabled

Enabled

SD Square Pixel Mode.

SD VCR FF/RW Sync.

SD Pixel Data Valid.

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0

1

Disabled

Enabled

SD Active Video Edge

Control.

0

1

Disabled

Enabled

0x83

SD Mode

Register 3

SD Pedestal YPrPb Output.

0

1

No pedestal on YPrPb

7.5 IRE pedestal on YPrPb

Y = 700 mV/300 mV

Y = 714 mV/286 mV

700 mV p-p (PAL), 1000 mV p-p (NTSC)

700 mV p-p

0x04

SD Output Levels Y.

0

1

SD Output Levels PrPb.

0

1

0

1

0

1

1000 mV p-p

648 mV p-p

SD Vertical Blanking

Interval (VBI) Open.

0

1

Disabled

Enabled

SD Closed Captioning

Field Control.

0

1

0

1

0

1

Closed captioning disabled

Closed captioning on odd field only

Closed captioning on even field only

Closed captioning on both fields

Reserved

Reserved.

0

Rev. 0 | Page 34 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 24. Register 0x84 to Register 0x87

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

VSYNC

7

6

5

4

3

2

1

0

1

Register Setting

0x84

SD Mode

Register 4

Disabled

SD

-3H.

VSYNC

= 2.5 lines (PAL),

= 3 lines (NTSC)

SD SFL/SCR/TR Mode Select.

0

1

0

1

0

1

Disabled

Subcarrier reset mode enabled

Timing reset mode enabled

SFL mode enabled

720 pixels

710 (NTSC), 702 (PAL)

Chroma enabled

Chroma disabled

Enabled

SD Active Video Length.

SD Chroma.

0

1

0

1

SD Burst.

0

1

Disabled

SD Color Bars.

0

1

Disabled

Enabled

SD Luma/Chroma Swap.

0

1

DAC 2 = luma, DAC 3 = chroma

DAC 2 = chroma, DAC 3 = luma

5.17 ꢀs

5.31 ꢀs

5.59 ꢀs (must be set for

Macrovision compliance)

0x86

SD Mode

Register 5

NTSC Color Subcarrier Adjust (Delay from

the falling edge of output HSYNC pulse to

start of color burst).

0

1

0

1

0

0x02

1

Reserved

Reserved.

0

SD EIA/CEA-861B Synchronization

Compliance.

0

1

Disabled

Enabled

Reserved.

0

SD Horizontal/Vertical Counter Mode.¹

0

1

Update field/line counter

Field/line counter free running

Normal

Color reversal enabled

Disabled

SD RGB Color Swap.²

SD PrPb Scale.

0

1

0x87

SD Mode

Register 6

0

1

0x00

Enabled

SD Y Scale.

0

1

Disabled

Enabled

SD Hue Adjust.

0

1

Disabled

Enabled

SD Brightness.

0

1

Disabled

Enabled

SD Luma SSAF Gain.

SD Input Standard Auto Detection.

0

1

Disabled

Enabled

0

1

Disabled

Enabled

Reserved.

SD RGB Input Enable.²

0

0 must be written to this bit

SD YCrCb input

SD RGB input

0

1

¹When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

²Available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. 0 | Page 35 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 25. Register 0x88 to Register 0x89

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

Reserved.

7

6

5

4

3

2

1

0

Register Setting

0x88

SD Mode

Register 7

0

SD Noninterlaced Mode.

0

1

Disabled

Enabled

SD Double Buffering.

SD Input Format.

0

1

Disabled

Enabled

0

1

0

1

0

1

8-bit input

16-bit input¹

10-bit input¹

Reserved

SD Digital Noise Reduction.

SD Gamma Correction Enable.

SD Gamma Correction Curve Select.

SD Undershoot Limiter.

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0

1

Gamma Correction Curve A

Gamma Correction Curve B

Disabled

−11 IRE

−6 IRE

0x89

SD Mode

Register 8

0

1

0

1

0

1

0x00

−1.5 IRE

Reserved.

0

0 must be written to this bit

Disabled

Enabled

SD Black Burst Output on DAC Luma.

0

1

SD Chroma Delay.

0

1

0

1

0

1

Disabled

4 clock cycles

8 clock cycles

Reserved

Reserved.

0

0 must be written to these bits

¹Available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. 0 | Page 36 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 26. Register 0x8A to Register 0x98

SR7 to

Bit Number

Reset

Value

0x08

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Slave mode

Master mode

Mode 0

Mode 1

Mode 2

0x8A

SD Timing Register 0

SD Slave/Master Mode.

SD Timing Mode.

0

1

0

1

0

1

Mode 3

Reserved.

1

SD Luma Delay.

0

1

0

1

0

1

No delay

2 clock cycles

4 clock cycles

6 clock cycles

−40 IRE

SD Minimum Luma Value.

SD Timing Reset.

0

1

−7.5 IRE

x

A low-high-low transition

resets the internal SD

timing counters

0x8B

SD Timing Register 1

Note: Applicable in

master modes only,

that is, Subaddress

0x8A, Bit 0 = 1.

HSYNC

0

1

0

1

0

1

t_a= 1 clock cycle

t_a= 4 clock cycles

t_a= 16 clock cycles

t_a= 128 clock cycles

t_b= 0 clock cycles

t_b= 4 clock cycles

t_b= 8 clock cycles

t_b= 18 clock cycles

t_c= t_b

0x00

SD

Width.

HSYNC VSYNC

to

0

1

0

1

0

1

Delay.

Rising

HSYNC VSYNC

to

Edge Delay (Mode 1 Only).

x

0

1

0

1

0

1

0

1

t_c= t_b+ 32 μs

VSYNC

1 clock cycle

4 clock cycles

16 clock cycles

128 clock cycles

0 clock cycles

1 clock cycle

2 clock cycles

3 clock cycles

Width (Mode 2 Only).

HSYNC

0

1

x

0

1

0

1

x

to Pixel Data Adjust.

0x8C

0x8D

0x8E

0x8F

SD F_SCRegister 0¹

SD F_SCRegister 1¹

SD F_SCRegister 2¹

SD F_SCRegister 3¹

SD F_SCPhase

Subcarrier Frequency Bits[7:0]

Subcarrier Frequency Bits[15:8]

Subcarrier Frequency Bits[23:16]

Subcarrier Frequency Bits[31:24]

Subcarrier Phase Bits[9:2]

x

Subcarrier Frequency

Bits[7:0]

0x1F

0x7C

0xF0

0x21

x

Subcarrier Frequency

Bits[15:8]

Subcarrier Frequency

Bits[23:16]

Subcarrier Frequency

Bits[31:24]

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

x

Subcarrier Phase Bits[9:2]

Extended Data Bits[7:0]

0x00

SD Closed Captioning Extended Data on Even Fields.

SD Closed Captioning Data on Odd Fields.

Extended Data Bits[15:8]. 0x00

Data Bits[7:0]

Data Bits[15:8]

0x00

SD Closed Captioning Data on Odd Fields.

SD Pedestal Register 0

SD Pedestal Register 1

SD Pedestal Register 2

SD Pedestal Register 3

Pedestal on Odd Fields.

Pedestal on Even Fields.

17 16 15 14 13 12 11 10 Setting any of these bits 0x00

to 1 disables pedestal

25 24 23 22 21 20 19 18

17 16 15 14 13 12 11 10

25 24 23 22 21 20 19 18

0x00

on the line number

indicated by the bit

settings

¹SD subcarrier frequency registers default to NTSC subcarrier frequency values.

Rev. 0 | Page 37 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 27. Register 0x99 to Register 0xA5

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

SD CGMS Data.

SD CGMS CRC.

7

6

5

4

3

2

1

0

Register Setting

CGMS Data Bits[C19:C16]

Disabled

0x99

SD CGMS/WSS 0

x

0

1

Enabled

SD CGMS on Odd Fields.

SD CGMS on Even Fields.

SD WSS.

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0x9A

SD CGMS/WSS 1

SD CGMS/WSS 2

SD CGMS/WSS Data.

x

CGMS Data Bits[C13:C8] or

WSS Data Bits[W13:W8]

0x00

SD CGMS Data.

x

CGMS Data Bits[C15:C14]

0x9B

0x9C

SD CGMS/WSS Data.

x

CGMS Data Bits[C7:C0] or

WSS Data Bits[W7:W0]

0x00

SD Scale LSB

Register

LSBs for SD Y Scale Value.

LSBs for SD Cb Scale Value.

LSBs for SD Cr Scale Value.

LSBs for SD F_SCPhase.

SD Y Scale Bits[1:0]

SD Cb Scale Bits[1:0]

SD Cr Scale Bits[1:0]

Subcarrier Phase Bits[1:0]

SD Y Scale Bits[7:2]

SD Cb Scale Bits[7:2]

x

0x9D

0x9E

SD Y Scale Register SD Y Scale Value.

x

0x00

SD Cb Scale

Register

SD Cb Scale Value.

0x9F

0xA0

0xA1

SD Cr Scale Register SD Cr Scale Value.

SD Hue Register SD Hue Adjust Value.

x

SD Cr Scale Bits[7:2]

0x00

SD Hue Adjust Bits[7:0]

SD Brightness/WSS SD Brightness Value.

SD Blank WSS Data.

SD Brightness Bits[6:0]

0

1

Disabled

Enabled

−4 dB

…

0xA2

SD Luma SSAF

SD Luma SSAF Gain/Attenuation.

0

…

0

…

1

0

…

1

0

…

0

0x00

Note: Only applicable if

Subaddress 0x87, Bit 4 = 1.

0 dB

…

1

…

1

…

0

…

0

…

+4 dB

Reserved.

0

0xA3

SD DNR 0

Coring Gain Border.

Note: In DNR mode, the values

in brackets apply.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No gain

0x00

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

Coring Gain Data.

Note: In DNR mode, the values

in brackets apply.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No gain

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

Rev. 0 | Page 38 of 96

ADV7390/ADV7391/ADV7392/ADV7393

SR7 to

SR0

Bit Number

Reset

Value

0x00

Register

Bit Description

7

6

5

0

4

0

3

0

2

0

1

0

Register Setting

0

0xA4

SD DNR 1

DNR Threshold.

0

1

…

1

…

1

…

1

…

1

…

1

…

0

…

62

1

63

Border Area.

Block Size.

0

1

2 pixels

4 pixels

0

1

8 pixels

16 pixels

Filter A

Filter B

Filter C

0xA5

SD DNR 2

DNR Input Select.

0

1

0

1

0

1

0

1

0

0x00

Filter D

DNR Mode.

0

1

DNR mode

DNR sharpness mode

0 pixel offset

1 pixel offset

…

DNR Block Offset.

0

…

1

0

…

1

0

…

1

0

1

…

0

1

14 pixel offset

15 pixel offset

Table 28. Register 0xA6 to Register 0xBB

SR7 to

Bit Number

Reset

Value

0x00

0xXX

0x0X

SR0

Register

Bit Description

7

x

6

5

4

x

3

x

2

1

x

0

x

Register Setting

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

SD Gamma A0

SD Gamma A1

SD Gamma A2

SD Gamma A3

SD Gamma A4

SD Gamma A5

SD Gamma A6

SD Gamma A7

SD Gamma A8

SD Gamma A9

SD Gamma B0

SD Gamma B1

SD Gamma B2

SD Gamma B3

SD Gamma B4

SD Gamma B5

SD Gamma B6

SD Gamma B7

SD Gamma B8

SD Gamma B9

SD Brightness Detect

Field Count Register

SD Gamma Curve A (Point 24).

SD Gamma Curve A (Point 32).

SD Gamma Curve A (Point 48).

SD Gamma Curve A (Point 64).

SD Gamma Curve A (Point 80).

SD Gamma Curve A (Point 96).

x

X

x

A0

A1

A2

A3

A4

A5

SD Gamma Curve A (Point 128).

SD Gamma Curve A (Point 160).

SD Gamma Curve A (Point 192).

SD Gamma Curve A (Point 224).

SD Gamma Curve B (Point 24).

SD Gamma Curve B (Point 32).

SD Gamma Curve B (Point 48).

SD Gamma Curve B (Point 64).

SD Gamma Curve B (Point 80).

SD Gamma Curve B (Point 96).

SD Gamma Curve B (Point 128).

SD Gamma Curve B (Point 160).

SD Gamma Curve B (Point 192).

SD Gamma Curve B (Point 224).

SD Brightness Value.

A6

A7

A8

A9

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

Read only

Reserved

Read only

Field Count.

Reserved.

0

Revision Code.

0

Rev. 0 | Page 39 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 29. Register 0xE0 to Register 0xF1

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register¹

Bit Description

MV Control Bits.

MV Control Bit.

7

x

0

6

x

0

5

x

0

4

x

0

3

x

0

2

x

0

1

x

0

x

Register Setting

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

Macrovision

Bits[7:1] must be 0

¹Macrovision registers are only available on the ADV7390 and the ADV7392.

Rev. 0 | Page 40 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ADV7390/ADV7391 INPUT CONFIGURATION

The ADV7390/ADV7391 supports a number of different input

modes. The desired input mode is selected using Subaddress 0x01,

Bits[6:4]. The ADV7390/ADV7391 defaults to standard

definition (SD) mode upon power-up. Table 30 provides an

overview of all possible input configurations. Each input mode

is described in detail in this section.

The CrCb pixel data is also input on Pin P7 to Pin P0

upon the opposite edge of CLKIN. P0 is the LSB.

Whether the Y data is clocked in upon the rising or falling edge

of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see

Figure 50 and Figure 51).

CLKIN

Table 30. ADV7390/ADV7391 Input Configuration

Input Mode

P7 P6 P5 P4 P2 P2 P1 P0

P[7:0]

3FF

00

XY

Cb0

Y0

Cr0

Y1

000 SD

010 ED/HD-DDR

111 ED (at 54 MHz)

YCrCb

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

Figure 50. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

STANDARD DEFINITION

Subaddress 0x01, Bits[6:4] = 000

CLKIN

SD YCrCb data can be input in an interleaved 4:2:2 format over

an 8-bit bus rate of 27 MHz.

P[7:0]

3FF

00

XY

Y0

Cb0

Y1

Cr0

A 27 MHz clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.

Figure 51. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

HSYNC

VSYNC

the

and

pins. Embedded EAV/SAV timing

codes are also supported. The ITU-R BT.601/656 input standard

is supported.

MPEG2

DECODER

ADV7390/

ADV7391

CLKIN

YCrCb

The interleaved pixel data is input on Pin P7 to Pin P0, with P0

being the LSB.

8

YCrCb

P[7:0]

ADV7390/

ADV7391

INTERLACED TO

PROGRESSIVE

2

VSYNC,

MPEG2

HSYNC

2

DECODER

VSYNC,

HSYNC

27MHz

CLKIN

Figure 52. ED/HD-DDR Example Application

8

YCrCb

ENHANCED DEFINITION (AT 54 MHz)

P[7:0]

Subaddress 0x01, Bits[6:4] = 111

Figure 49. SD Example Application

ED YCrCb data can be input in an interleaved 4:2:2 format over

an 8-bit bus rate of 54 MHz.

ENHANCED DEFINITION/HIGH DEFINITION

Subaddress 0x01, Bits[6:4] = 010

A 54 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes are supported. External

synchronization signals are not supported in this mode.

ED or HD YCrCb data can be input in an interleaved 4:2:2

format over an 8-bit DDR bus.

The clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

The interleaved pixel data is input on Pin P7 to Pin P0, with P0

being the LSB.

HSYNC

VSYNC

the

and

pins. Embedded EAV/SAV timing

CLKIN

codes are also supported.

8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)

P[7:0]

3FF

00

XY

Cb0

Y0

Cr0

Y1

In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input

on Pin P7 to Pin P0 upon either the rising or falling edge of

CLKIN. P0 is the LSB.

Figure 53. ED (At 54 MHz) Input Sequence (EAV/SAV)

Rev. 0 | Page 41 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ADV7392/ADV7393 INPUT CONFIGURATION

16-Bit 4:2:2 YCrCb Mode

The ADV7392/ADV7393 supports a number of different input

modes. The desired input mode is selected using Subaddress 0x01,

Bits[6:4]. The ADV7392/ADV7393 defaults to standard

definition (SD) mode upon power-up. Table 31 provides an

overview of all possible input configurations. Each input mode

is described in detail in this section.

Subaddress 0x87, Bit 7 = 0

Subaddress 0x88, Bits[4:3] = 01

In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on

Pin P15 to Pin P8, with P8 being the LSB.

The CrCb pixel data is input on Pin P7 to Pin P0, with P0 being

the LSB.

STANDARD DEFINITION

Subaddress 0x01, Bits[6:4] = 000

The pixel data is updated at half the rate of the clock, that is, at a

rate of 13.5 MHz (see Figure 3).

SD YCrCb data can be input in 4:2:2 format over an 8-, 10-, or 16-

bit bus. SD RGB data can be input in 4:4:4 format over a 16-bit bus.

16-Bit 4:4:4 RGB Mode

A 27 MHz clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

Subaddress 0x87, Bit 7 = 1

In 16-bit 4:4:4 RGB input mode, the red pixel data is input on

Pin P4 to Pin P0, the green pixel data is input on Pin P10 to

Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.

P0, P5, and P11 are the respective bus LSBs.

HSYNC

VSYNC

the

and

pins. Embedded EAV/SAV timing

codes are also supported in 8-bit and 10-bit modes.

8-Bit 4:2:2 YCrCb Mode

Subaddress 0x87, Bit 7 = 0

Subaddress 0x88, Bits[4:3] = 00

The pixel data is updated at half the rate of the clock, that is, at a

rate of 13.5 MHz (see Figure 4).

In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is

input on Pin P15 to Pin P8, with P8 being the LSB. The ITU-R

BT.601/656 input standard is supported.

ADV7392/

ADV7393

2

VSYNC,

MPEG2

HSYNC

DECODER

10-Bit 4:2:2 YCrCb Mode

27MHz

CLKIN

Subaddress 0x87, Bit 7 = 0

Subaddress 0x88, Bits[4:3] = 10

8/10

YCrCb

P[15:8]/P[15:6]

In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is

input on Pin P15 to Pin P6, with P6 being the LSB. The ITU-R

BT.601/656 input standard is supported.

Figure 54. SD Example Application

Table 31. ADV7392/ADV7393 Input Configuration

1

Input Mode

P15

P14

P13

P12

P11

P10

P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

2

000

SD

SD RGB Input Enable (0x87[7]) = 0

YCrCb

SD RGB Input Enable (0x87[7]) = 1

8-Bit

YCrCb

10-Bit

16-Bit

3

Y

CrCb

16-Bit³

B

G

R

001

010

ED/HD-SDR (16-Bit)

Y

CrCb

4

ED/HD-DDR

ED/HD Input Format (0x33[2]) = 0

ED/HD Input Format (0x33[2]) = 1

8-Bit

YCrCb

10-Bit

ED (At 54 MHz)

8-Bit

YCrCb

111

ED/HD Input Format (0x33[2]) = 0

YCrCb

ED/HD Input Format (0x33[2]) = 1

10-Bit

YCrCb

¹The input mode is determined by Subaddress 0x01, Bits[6:4].

²In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].

³External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.

⁴ED = enhanced definition = 525p and 625p.

Rev. 0 | Page 42 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ENHANCED DEFINITION/HIGH DEFINITION

Subaddress 0x01, Bits[6:4] = 001 or 010

M

PEG2

ADV7392/

ADV7393

DECODER

CLKIN

YCrCb

ED or HD YCrCb data can be input in a 4:2:2 format over an

8-/10-bit DDR bus or a 16-bit SDR bus.

8

CrCb

Y

P[7:0]

The clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

INTERLACED TO

PROGRESSIVE

P[15:8]

HSYNC

codes are also supported.

VSYNC

the

and

pins. Embedded EAV/SAV timing

2

VSYNC

HSYNC

16-Bit 4:2:2 YCrCb Mode (SDR)

Figure 57. ED/HD-SDR Example Application

In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on

Pin P15 to Pin P8, with P8 being the LSB.

MPEG2

ADV7392/

DECODER

The CrCb pixel data is input on Pin P7 to Pin P0, with P0

being the LSB.

ADV7393

CLKIN

YCrCb

8-/10-Bit 4:2:2 YCrCb Mode (DDR)

8/10

2

YCrCb

In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is

input on Pin P15 to Pin P8/P6 upon either the rising or falling

edge of CLKIN. P8/P6 is the LSB.

P[15:8]/P[15:6]

INTERLACED TO

PROGRESSIVE

VSYNC

HSYNC

The CrCb pixel data is also input on Pin P15 to Pin P8/P6

upon the opposite edge of CLKIN. P8/P6 is the LSB.

Figure 58. ED/HD-DDR Example Application

10-bit mode is enabled using Subaddress 0x33, Bit 2. Whether

the Y data is clocked in upon the rising or falling edge of CLKIN

is determined by Subaddress 0x01, Bits[2:1] (see Figure 55 and

Figure 56).

ENHANCED DEFINITION (AT 54 MHz)

Subaddress 0x01, Bits[6:4] = 111

ED YCrCb data can be input in an interleaved 4:2:2 format on

an 8-/10-bit bus at a rate of 54 MHz.

A 54 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes are supported. External

synchronization signals are not supported in this mode.

CLKIN

P[15:8]/

P]15:6]

3FF

00

X

Y

Cb0

Y0

Cr0

Y1

The interleaved pixel data is input on Pin P15 to Pin P8/P6,

with P8/P6 being the LSB.

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

10-bit mode is enabled using Subaddress 0x33, Bit 2.

Figure 55. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

CLKIN

P[15:8]/P[15:6]

NOTES

3FF

00

XY

Cb0

Y0

Cr0

Y1

P[15:8]/

P[15:P6]

3FF

00

XY

Y0

Cb0

Y1

Cr0

1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

NOTES

Figure 59. ED (At 54 MHz) Input Sequence (EAV/SAV)

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.

2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

Figure 56. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

MPEG2

DECODER

ADV7392/

ADV7393

54MHz

CLKIN

YCrCb

8/10

2

YCrCb

P[15:8]/P[15:6]

INTERLACED TO

PROGRESSIVE

VSYNC,

HSYNC

Figure 60. ED (At 54 MHz) Example Application

Rev. 0 | Page 43 of 96

ADV7390/ADV7391/ADV7392/ADV7393

OUTPUT CONFIGURATION

The ADV739x supports a number of different output configurations. Table 32 to Table 34 lists all possible output configurations.

Table 32. SD Output Configurations

RGB/YPrPb Output Select¹

(0x02, Bit 5)

SD DAC Output 1

(0x82, Bit 1)

SD Luma/Chroma Swap

(0x84, Bit 7)

DAC 1

G

Y

CVBS

DAC 2

B

Pb

Luma

Chroma

DAC 3

R

Pr

Chroma

Luma

0

1

0

1

0

1

¹If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.

Table 33. ED/HD Output Configurations

RGB/YPrPb Output Select (0x02, Bit 5)

ED/HD Color DAC Swap (0x35, Bit 3)

DAC 1

DAC 2

DAC 3

0

1

0

1

0

1

G

Y

B

R

Pb

Pr

R

B

Pr

Pb

Table 34. ED (at 54 MHz) Output Configurations

RGB/YPrPb Output Select (0x02, Bit 5)

ED/HD Color DAC Swap (0x35, Bit 3)

DAC 1

DAC 2

DAC 3

0

1

0

1

0

1

G

Y

B

R

Pb

Pr

R

B

Pr

Pb

Rev. 0 | Page 44 of 96

ADV7390/ADV7391/ADV7392/ADV7393

FEATURES

various output levels that can be generated. Table 36 lists the

transitions required to generate the various output levels.

OUTPUT OVERSAMPLING

The ADV739x include an on-chip phase-locked loop (PLL) that

allows for oversampling of SD, ED, and HD video data. By

default, the PLL is disabled. The PLL can be enabled using

Subaddress 0x00, Bit 1 = 0.

Embedded EAV/SAV timing codes are not supported in

ED/HD nonstandard timing mode.

The user must ensure that appropriate pixel data is applied to

the encoder where the blanking level is expected at the output.

Table 35 shows the various oversampling rates supported in the

ADV739x.

Macrovision (ADV7390/ADV7392 only) and output

oversampling are not available in ED/HD nonstandard timing

mode. The PLL must be disabled (Subaddress 0x00, Bit 1 = 1) in

ED/HD nonstandard timing mode.

ED/HD NONSTANDARD TIMING MODE

Subaddress 0x30, Bits[7:3] = 00001

For any ED/HD input data that does not conform to

the standards listed in the ED/HD input mode table

(Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard

timing mode can be used to interface to the ADV739x.

ED/HD nonstandard timing mode can be enabled by

setting Subaddress 0x30, Bits[7:3] to 00001.

ANALOG

OUTPUT

b

ACTIVE VIDEO

a

b

BLANKING LEVEL

c

HSYNC

a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.

b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.

c = SYNCHRONIZATION PULSE LEVEL.

A clock signal must be provided on the CLKIN pin.

VSYNC

and

must be toggled by the user to generate the

appropriate horizontal and vertical synchronization pulses on

the analog output from the encoder. Figure 61 illustrates the

Figure 61. ED/HD Nonstandard Timing Mode Output Levels

Table 35. Output Oversampling Modes and Rates

Input Mode

(0x01, Bits[6:4])

PLL and Oversampling

Control (0x00, Bit 1)

SD/ED Oversample Rate

Select (0x0D, Bit 3)

HD Oversample Rate

Select (0x31, Bit 1)

Oversampling Mode

and Rate

000

001/010 ED

001/010 HD

SD

1

0

1

0

1

0

1

0

x

1

0

x

1

0

x

1

0

x

1

0

x

SD (2×)

SD (8×)

SD (16×)

ED (1×)

ED (4×)

ED (8×)

HD (1×)

HD (2×)

HD (4×)

111

ED (at 54 MHz)

ED (@ 54 MHz) (1×)

ED (@ 54 MHz) (4×)

ED (@ 54 MHz) (8×)

Table 36. ED/HD Nonstandard Timing Mode Synchronization Signal Generation

Output Level Transition¹

HSYNC

VSYNC

b → c

c → a

a → b

c → b

1 → 0

0

1 → 0 or 0²

0 → 1

1

0

0 → 1

¹a = Tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. See Figure 61.

²If

= 1, it should transition to 0. If = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, should always be 0.

VSYNC

Rev. 0 | Page 45 of 96

ADV7390/ADV7391/ADV7392/ADV7393

•

In subcarrier reset (SCR) mode (Subaddress 0x84, Bits[2:1]

= 01), a low-to-high transition on the SFL/MISO pin resets

the subcarrier phase to 0 on the field following the

subcarrier phase reset.

ED/HD TIMING RESET

Subaddress 0x34, Bit 0

An ED/HD timing reset is achieved by setting the ED/HD

timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this

state, the horizontal and vertical counters remain reset. When

this bit is set back to 0, the internal counters resume counting.

This timing reset applies to the ED/HD timing counters only.

This reset signal must be held high for a minimum of one

clock cycle.

Because the field counter is not reset, it is recommended to

apply the reset signal in Field 7 (PAL) or Field 3 (NTSC).

The reset of the phase then occurs on the next field, that is,

Field 1, which is lined up correctly with the internal

counters. The field count register at Subaddress 0xBB can

be used to identify the number of the active field.

SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER

RESET, AND TIMING RESET

Subaddress 0x84, Bits[2:1]

Together with the SFL/MISO pin and SD Mode Register 4

(Subaddress 0x84, Bits[2:1]), the ADV739x can be used in

timing reset mode, subcarrier phase reset mode, or SFL mode.

•

In subcarrier frequency lock (SFL) mode (Subaddress 0x84,

Bits[2:1] = 11), the ADV739x can be used to lock to an

external video source. The SFL mode allows the ADV739x

to automatically alter the subcarrier frequency to compensate

for line length variations. When the part is connected to a

device such as an ADV7403 video decoder that outputs a

digital data stream in the SFL format, the part automatically

changes to the compensated subcarrier frequency on a

line-by-line basis (see Figure 64). This digital data stream is

67 bits wide and the subcarrier is contained in Bit 0 to Bit

21. Each bit is two clock cycles long.

•

In timing reset (TR) mode (Subaddress 0x84, Bits[2:1] = 10),

a timing reset is achieved in a low-to-high transition on the

SFL/MISO pin. In this state, the horizontal and vertical

counters remain reset. Upon releasing this pin (set to low),

the internal counters resume counting, starting with Field 1,

and the subcarrier phase is reset.

The minimum time the pin must be held high is one clock

cycle; otherwise, this reset signal may not be recognized.

This timing reset applies to the SD timing counters only.

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 4 OR 8

SC

307

310

313

320

NO TIMING RESET APPLIED

DISPLAY

START OF FIELD 1

F

PHASE = FIELD 1

SC

307

1

2

3

4

5

6

7

21

TIMING RESET PULSE

TIMING RESET APPLIED

Figure 62. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 10)

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 4 OR 8

SC

307

310

313

320

NO F RESET APPLIED

SC

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 1

SC

307

310

313

320

F

RESET PULSE

SC

F

RESET APPLIED

SC

Figure 63. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)

Rev. 0 | Page 46 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ADV739x

CLKIN

DAC 1

DAC 2

DAC 3

LCC1

SFL

SFL/MISO

COMPOSITE

P19 TO

P10

ADV7403

VIDEO

DECODER

1

VIDEO

5

PIXEL PORT

4 BITS

RESERVED

21

0

14 BITS

SEQUENCE

4

H/L TRANSITION

COUNT START

RESET BIT

SUBCARRIER

PHASE

3

BIT

LOW

RESERVED

2

PLL INCREMENT

F

128

SC

13

0

RTC

6768

14

19

TIME SLOT 01

VALID

SAMPLE

INVALID

SAMPLE

8/LINE

LOCKED

CLOCK

5 BITS

RESERVED

1

2

FOR EXAMPLE, VCR OR CABLE.

F

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx F DDS REGISTER IS

SC

F

PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS.

SC

3

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

RESET ADV739x DDS.

4

5

REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 “INPUT CONFIGURATION” TABLES FOR PIXEL DATA PIN ASSIGNMENTS.

Figure 64. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)

VBI data can be present on Line 10 to Line 20 for NTSC and on

Line 7 to Line 22 for PAL.

SD VCR FF/RW SYNC

Subaddress 0x82, Bit 5

In SD Timing Mode 0 (slave option), if VBI is enabled, the

blanking bit in the EAV/SAV code is overwritten. It is possible

to use VBI in this timing mode as well.

In DVD record applications where the encoder is used with a

decoder, the VCR FF/RW sync control bit can be used for non-

standard input video, that is, in fast forward or rewind modes.

If CGMS is enabled and VBI is disabled, the CGMS data is

nevertheless available at the output.

In fast forward mode, the sync information at the start of a new

field in the incoming video usually occurs before the correct

number of lines/fields is reached. In rewind mode, this sync

signal usually occurs after the total number of lines/fields is

reached. Conventionally, this means that the output video has

corrupted field signals because one signal is generated by the

incoming video and another is generated when the internal

line/field counters reach the end of a field.

SD SUBCARRIER FREQUENCY REGISTERS

Subaddress 0x8C to Subaddress 0x8F

Four 8-bit registers are used to set up the subcarrier frequency.

The value of these registers is calculated using the following

equation:

Subcarrier Frequency Register =

When the VCR FF/RW sync control is enabled (Subaddress 0x82,

Bit 5), the line/field counters are updated according to the

Number of subcarrier periods in one video line

× 2³²

VSYNC

incoming

the incoming

signal and when the analog output matches

VSYNC

Number of 27 MHz clock cycles in one video line

signal.

where the sum is rounded to the nearest integer.

For example, in NTSC mode:

This control is available in all slave-timing modes except

Slave Mode 0.

227.5

1716

⎛

⎜

⎝

⎞

⎟

⎠

Subcarrier Register Value =

×

³²= 569408543

2

VERTICAL BLANKING INTERVAL

Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4

where:

The ADV739x is able to accept input data that contains vertical

blanking interval (VBI) data (such as CGMS, WSS, VITS) in

SD, ED, and HD modes.

Subcarrier Register Value = 569408543d = 0×21F07C1F

SD F_SCRegister 0: 0x1F

SD F_SCRegister 1: 0x7C

SD F_SCRegister 2: 0xF0

SD F_SCRegister 3: 0x21

If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;

Subaddress 0x83, Bit 4 for SD), VBI data is not present at the

output and the entire VBI is blanked. These control bits are

valid in all master and slave timing modes.

For the SMPTE 293M (525p) standard, VBI data can be

inserted on Line 13 to Line 42 of each frame, or on Line 6 to

Lind 43 for the ITU-R BT.1358 (625p) standard.

Rev. 0 | Page 47 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Programming the F_SC

A 27 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes or external horizontal and

The subcarrier frequency register value is divided into four F_SC

registers as shown in the previous example. The four subcarrier

frequency registers must be updated sequentially, starting with

Subcarrier Frequency Register 0 and ending with Subcarrier

Frequency Register 3. The subcarrier frequency updates only

after the last subcarrier frequency register byte has been

received by the ADV739x.

HSYNC

vertical synchronization signals provided on the

VSYNC

and

pins can be used to synchronize the input pixel data.

All input configurations, output configurations, and features

available in NTSC and PAL modes are available in SD noninter-

laced mode.

For 240p/59.94 Hz input, the ADV739x should be configured for

NTSC operation and Subaddress 0x88, Bit 1 should be set to 1.

Typical F_SCValues

Table 37 outlines the values that should be written to the

subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

For 288p/50 Hz input, the ADV739x should be configured for

PAL operation and Subaddress 0x88, Bit 1 should be set to 1.

Table 37. Typical F_SCValues

SD SQUARE PIXEL MODE

Subaddress

Description

NTSC

0x1F

0x7C

0xF0

0x21

PAL B/D/G/H/I

0xCB

0x8A

0x09

0x2A

Subaddress 0x82, Bit 4

0x8C

0x8D

0x8E

0x8F

F_SC0

F_SC1

F_SC2

F_SC3

The ADV739x can be used to operate in square pixel mode

(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of

24.5454 MHz is required. Alternatively, for PAL operation, an

input clock of 29.5 MHz is required. The internal timing logic

adjusts accordingly for square pixel mode operation.

SD NONINTERLACED MODE

Subaddress 0x88, Bit 1

In square pixel mode, the timing diagrams shown in Figure 65

and Figure 66 apply.

The ADV739x supports a SD noninterlaced mode. Using this

mode, progressive inputs at twice the frame rate of NTSC and

PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input

into the ADV739x. The SD noninterlaced mode can be enabled

using Subaddress 0x88, Bit 1.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

b

C

r

C

b

8

0

F

A

B

A

B

A

B

8

0

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

272 CLOCK

1280 CLOCK

1536 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

344 CLOCK

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 65. Square Pixel Mode EAV/SAV Embedded Timing

HSYNC

FIELD

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 308 CLOCK CYCLES

NTSC = 236 CLOCK CYCLES

Figure 66. Square Pixel Mode Active Pixel Timing

Rev. 0 | Page 48 of 96

ADV7390/ADV7391/ADV7392/ADV7393

EXTENDED (SSAF) PrPb FILTER MODE

FILTERS

0

Table 38 shows an overview of the programmable filters

available on the ADV739x.

–10

–20

–30

–40

–50

–60

Table 38. Selectable Filters

Filter

Subaddress

0x80

0x82

0x33

SD Luma LPF NTSC

SD Luma LPF PAL

SD Luma Notch NTSC

SD Luma Notch PAL

SD Luma SSAF

SD Luma CIF

SD Luma QCIF

0

1

2

3

4

5

6

FREQUENCY (MHz)

SD Chroma 0.65 MHz

SD Chroma 1.0 MHz

SD Chroma 1.3 MHz

SD Chroma 2.0 MHz

SD Chroma 3.0 MHz

SD Chroma CIF

SD Chroma QCIF

SD PrPb SSAF

ED/HD Sinc Compensation Filter

ED/HD Chroma SSAF

Figure 67. PrPb SSAF Filter

If this filter is disabled, one of the chroma filters shown in

Table 39 can be selected and used for the CVBS or luma/

chroma signal.

Table 39. Internal Filter Specifications

Pass-Band

Filter

Ripple (dB)¹

0.16

3 dB Bandwidth (MHz)²

Luma LPF NTSC

Luma LPF PAL

Luma Notch NTSC

Luma Notch PAL

Luma SSAF

4.24

4.81

0.1

0.09

0.1

0.04

2.3/4.9/6.6

3.1/5.6/6.4

6.45

SD Internal Filter Response

Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0

The Y filter supports several different frequency responses,

including two low-pass responses, two notch responses, an

extended (SSAF) response with or without gain boost

attenuation, a CIF response, and a QCIF response. The PrPb

filter supports several different frequency responses, including

six low-pass responses, a CIF response, and a QCIF response, as

shown in Figure 36 and Figure 37.

Luma CIF

Luma QCIF

0.127

3.02

1.5

0.65

1

1.395

2.2

3.2

0.65

0.5

Monotonic

0.09

Chroma 0.65 MHz

Chroma 1.0 MHz

Chroma 1.3 MHz

Chroma 2.0 MHz

Chroma 3.0 MHz

Chroma CIF

0.048

Monotonic

If SD Luma SSAF gain is enabled (Subaddress 0x87, Bit 4), there

are 13 response options in the range −4 dB to +4 dB. The desired

response can be programmed using Subaddress 0xA2. The

variation of frequency responses are shown in Figure 33 to

Figure 35.

Chroma QCIF

¹Pass-band ripple is the maximum fluctuation from the 0 dB response in the

pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz)

frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity

for a notch filter, where fc, f1, and f2 are the −3 dB points.

²3 dB bandwidth refers to the −3 dB cutoff frequency.

In addition to the chroma filters listed in Table 38, the ADV739x

contains an SSAF filter specifically designed for the color difference

component outputs, Pr and Pb. This filter has a cutoff frequency

of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see Figure 67).

This filter can be controlled with Subaddress 0x82, Bit 0.

Rev. 0 | Page 49 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ED/HD Sinc Compensation Filter Response

Table 40 shows sample color values that can be programmed

into the color registers when the output standard selection is set

to EIA770.2/EIA770.3 (Subaddress 0x30, Bits[1:0] = 00).

Subaddress 0x33, Bit 3

The ADV739x includes a filter designed to counter the effect of

sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in

ED/HD mode. This filter is enabled by default. It can be

disabled using Subaddress 0x33, Bit 3. The benefit of the filter is

illustrated in Figure 68 and Figure 69.

Table 40. Sample Color Values for EIA770.2/EIA770.3

ED/HD Output Standard Selection

Sample Color

Y Value

Cr Value

Cb Value

White

Black

Red

Green

Blue

Yellow

Cyan

235 (0xEB)

128 (0x80) 128 (0x80)

0.5

16

81

(0x10)

(0x51)

240 (0xF0)

90

(0x5A)

(0x36)

0.4

0.3

145 (0x91)

41 (0x29)

34

(0x22) 54

110 (0x6E)

240 (0xF0)

(0x10)

(0x10) 166 (0xA6)

106 (0x6A) 222 (0xDE) 202 (0xCA)

0.2

210 (0xD2) 146 (0x92) 16

170 (0xAA) 16

0.1

0

Magenta

–0.1

–0.2

–0.3

–0.4

–0.5

COLOR SPACE CONVERSION MATRIX

Subaddress 0x03 to Subaddress 0x09

The internal color space conversion (CSC) matrix automatically

performs all color space conversions based on the input mode

programmed in the mode select register (Subaddress 0x01,

Bits[6:4]). Table 41 and Table 42 show the options available in

this matrix.

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 68. ED/HD Sinc Compensation Filter Enabled

0.5

0.4

An SD color space conversion from RGB-in to YPrPb-out is

possible on the ADV7392/ADV7393. An ED/HD color space

conversion from RGB-in to YPrPb-out is not possible.

0.3

0.2

Table 41. SD Color Space Conversion Options

0.1

YPrPb/RGB Out

RGB In/YCrCb In

(Reg. 0x87, Bit 7)

0

Input Output¹(Reg. 0x02, Bit 5)

–0.1

–0.2

–0.3

–0.4

–0.5

YCrCb YPrPb

YCrCb RGB

1

0

1

0

1

RGB²

YPrPb

RGB

¹CVBS/YC outputs are available for all CSC combinations.

²Available on the ADV7392/ADV7393 (40-pin devices) only.

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 69. ED/HD Sinc Compensation Filter Disabled

Table 42. ED/HD Color Space Conversion Options

Input

YCrCb

Output

YPrPb

RGB

YPrPb/RGB Out (Reg. 0x02, Bit 5)

ED/HD TEST PATTERN COLOR CONTROLS

Subaddress 0x36 to Subaddress 0x38

1

0

Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38

are used to program the output color of the internal ED/HD

test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it

be the lines of the cross hatch pattern or the uniform field test

pattern. They are not functional as color controls for external

pixel data input.

ED/HD Manual CSC Matrix Adjust Feature

The ED/HD manual CSC matrix adjust feature provides custom

coefficient manipulation for color space conversions and is used

in ED and HD modes only. The ED/HD manual CSC matrix

adjust feature can be enabled using Subaddress 0x02, Bit 3.

The values for the luma (Y) and color difference (Cr and Cb)

signals used to obtain white, black, and saturated primary and

complementary colors conform to the ITU-R BT.601-4

standard.

Normally, there is no need to enable this feature because the CSC

matrix automatically performs the color space conversion based

on the input mode chosen (ED or HD) and the output color

space selected (see Table 42). For this reason, the ED/HD

manual CSC matrix adjust feature is disabled by default.

Rev. 0 | Page 50 of 96

ADV7390/ADV7391/ADV7392/ADV7393

If RGB output is selected, the ED/HD CSC matrix scalar uses

the following equations:

For example, SMPTE 293M uses the following conversion:

R = Y + 1.402Pr

R = GY × Y + RV × Pr

G = Y − 0.714Pr − 0.344Pb

B = Y + 1.773Pb

G = GY × Y − (GU × Pb) − (GV × Pr)

B = GY × Y + BU × Pb

The programmable CSC matrix is used for external ED/HD

pixel data and is not functional when internal test patterns are

enabled.

Note that subtractions are implemented in hardware.

If YPrPb output is selected, the following equations are used:

Programming the CSC Matrix

Y = GY × Y

Pr = RV × Pr

Pb = BU × Pb

where:

If custom manipulation of the ED/HD CSC matrix coefficients

is required for a YCrCb-to-RGB color space conversion, follow

the following procedure:

1. Enable the ED/HD manual CSC matrix adjust feature

(Subaddress 0x02, Bit 3).

GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0].

GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6].

GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4].

BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2].

RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].

2. Set the output to RGB (Subaddress 0x02, Bit 5).

3. Disable sync on PrPb (Subaddress 0x35, Bit 2).

4. Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).

The GY value controls the green signal output level, the BU

value controls the blue signal output level, and the RV value

controls the red signal output level.

Upon power-up, the CSC matrix is programmed with the

default values shown in Table 43.

Table 43. ED/HD Manual CSC Matrix Default Values

SD LUMA AND COLOR CONTROL

Subaddress 0x9C to Subaddress 0x9F

Subaddress

Default

0x03

0xF0

0x4E

0x0E

0x24

0x92

0x7C

0x03

0x04

SD Y Scale, SD Cb Scale, and SD Cr Scale are three 10-bit

control registers that scale the SD Y, Cb, and Cr output levels.

0x05

0x06

Each of these registers represent the value required to scale the

Cb or Cr level from 0.0 to 2.0 and the Y level from 0.0 to 1.5

times its initial level. The value of these 10 bits is calculated

using the following equation:

0x07

0x08

0x09

Y, Cb, or Cr Scale Value = Scale Factor × 512

For example, if Scale Factor = 1.3

When the ED/HD manual CSC matrix adjust feature is

enabled, the default coefficient values in Subaddress 0x03

to Subaddress 0x09 are correct for the HD color space only.

The color components are converted according to the following

1080i and 720p standards (SMPTE 274M, SMPTE 296M):

Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6

Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)

Y, Cb, or Cr Scale Value = 1010 0110 10b

R = Y + 1.575Pr

Subaddress 0x9C, SD Scale LSB Register = 0x2A

Subaddress 0x9D, SD Y Scale Register = 0xA6

Subaddress 0x9E, SD Cb Scale Register = 0xA6

Subaddress 0x9F, SD Cr Scale Register = 0xA6

G = Y − 0.468Pr − 0.187Pb

B = Y + 1.855Pb

The conversion coefficients should be multiplied by 315 before

being written to the ED/HD CSC matrix registers. This is

reflected in the default values for GY = 0x13B, GU = 0x03B,

GV = 0x093, BU = 0x248, and RV = 0x1F0.

Note that this feature affects all interlaced output signals, that is,

CVBS, Y-C, YPrPb, and RGB.

If the ED/HD manual CSC matrix adjust feature is enabled and

another input standard (such as ED) is used, the scale values for

GY, GU, GV, BU, and RV must be adjusted according to this

input standard color space. The user should consider that the

color component conversion might use different scale values.

Rev. 0 | Page 51 of 96

ADV7390/ADV7391/ADV7392/ADV7393

For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE.

For NTSC without pedestal (see Figure 70) and for PAL, the

setup can vary from −7.5 IRE to +15 IRE.

SD HUE ADJUST CONTROL

Subaddress 0xA0

When enabled, the SD hue adjust control register

(Subaddress 0xA0) is used to adjust the hue on the SD

composite and chroma outputs. This feature can be

enabled using Subaddress 0x87, Bit 2.

The SD brightness control register is an 8-bit register. The seven

LSBs of this 8-bit register are used to control the brightness

level, which can be a positive or negative value.

For example,

Subaddress 0xA0 contains the bits required to vary the hue of

the video data, that is, the variance in phase of the subcarrier

during active video with respect to the phase of the subcarrier

during the color burst. The ADV739x provides a range of

22.5° in increments of 0.17578125°. For normal operation

(zero adjustment), this register is set to 0x80. Values 0xFF and

0x00 represent the upper and lower limits, respectively, of the

attainable adjustment in NTSC mode. Values 0xFF and 0x01

represent the upper and lower limits, respectively, of the

attainable adjustment in PAL mode.

To add +20 IRE brightness level to an NTSC signal with

pedestal, write 0x28 to Subaddress 0xA1.

0 × (SD Brightness Value) =

0 × (IRE Value × 2.015631) =

0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28

To add –7 IRE brightness level to a PAL signal, write 0x72 to

Subaddress 0xA1.

0 × (SD Brightness Value) =

The hue adjust value is calculated using the following equation:

Hue Adjust (°) = 0.17578125° (HCR_d− 128)

0 × (IRE Value × 2.075631) =

0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b

0001110b into two’s complement = 1110010b = 0x72

where = HCR_dhue adjust control register (decimal)

For example, to adjust the hue by +4°, write 0x97 to the hue

adjust control register:

Table 44. Sample Brightness Control Values¹

Setup Level

(NTSC) with

Pedestal

Setup Level

(NTSC) Without Level

Pedestal

15 IRE

7.5 IRE

0 IRE

Setup

4

⎛

⎜

⎝

⎞

⎟

⎠

+ 128 ≈ 151d = 0x97

Brightness

Control Value

0.17578125

(PAL)

where the sum is rounded to the nearest integer.

22.5 IRE

15 IRE

7.5 IRE

0 IRE

15 IRE

7.5 IRE

0 IRE

0x1E

0x0F

0x00

0x71

To adjust the hue by −4°, write 0x69 to the hue adjust control

register:

−7.5 IRE

−4

⎛

⎜

⎝

⎞

⎟

⎠

¹Values in the range of 0x3F to 0x44 can result in an invalid output signal.

SD INPUT STANDARD AUTO DETECTION

Subaddress 0x87, Bit 5

+ 128 ≈ 105d = 0x69

0.17578125

where the sum is rounded to the nearest integer.

SD BRIGHTNESS DETECT

Subaddress 0xBA

The ADV739x include an SD input standard auto detect feature

that can be enabled by setting Subaddress 0x87, Bit 5 to Bit 1.

The ADV739x allows monitoring of the brightness level of the

incoming video data. The SD brightness detect register

(Subaddress 0xBA) is a read-only register.

When enabled, the ADV739x can automatically identify an

NTSC or PAL B/D/G/H/I input stream. The ADV739x

automatically updates the subcarrier frequency registers with

the appropriate value for the identified standard. The ADV739x

is also configured to correctly encode the identified standard.

SD BRIGHTNESS CONTROL

Subaddress 0xA1, Bits[6:0]

The SD standard bits (Subaddress 0x80, Bits[1:0]) and the

subcarrier frequency registers are not updated to reflect the

identified standard. All registers retain their default or user-

defined values.

When this feature is enabled, the SD brightness/WSS control

register (Subaddress 0xA1) is used to control brightness by

adding a programmable setup level onto the scaled Y data. This

feature can be enabled using Subaddress 0x87, Bit 3.

NTSC WITHOUT PEDESTAL

100 IRE

+7.5 IRE

–7.5 IRE

0 IRE

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

NO SETUP

VALUE ADDED

Figure 70. Examples of Brightness Control Values

Rev. 0 | Page 52 of 96

ADV7390/ADV7391/ADV7392/ADV7393

In Case B of Figure 71, the video output signal is reduced. The

absolute level of the sync tip and blanking level both decrease

with respect to the reference video output signal. The overall

gain of the signal is reduced from the reference signal.

DOUBLE BUFFERING

Subaddress 0x33, Bit 7 for ED/HD,

Subaddress 0x88, Bit 2 for SD

Double-buffered registers are updated once per field. Double

buffering improves overall performance because modifications

to register settings are not be made during active video, but take

effect prior to the start of the active video on the next field.

The range of this feature is specified for 7.5% of the nominal

output from the DACs. For example, if the output current of the

DAC is 4.33 mA, the DAC gain control feature can change this

output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).

Using Subaddress 0x33, Bit 7, double buffering can be activated

on the following ED/HD registers: ED/HD Gamma A and

Gamma B curves, and ED/HD CGMS registers.

The reset value of the control registers is 0x00, that is, nominal

DAC current is output. Table 45 is an example of how the

output current of the DACs varies for a nominal 4.33 mA

output current.

Using Subaddress 0x88, Bit 2, double buffering can be activated

on the following SD registers: SD Gamma A and Gamma B curves,

SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD closed

captioning, and SD Macrovision Bits[5:0] (Subaddress 0xE0,

Bits[5:0]).

Table 45. DAC Gain Control

DAC Current

Subaddress 0x0B (mA)

% Gain

7.5000%

7.3820%

7.3640%

...

Note

0100 0000 (0x40)

0011 1111 (0x3F)

0011 1110 (0x3E)

...

4.658

4.653

4.648

...

PROGRAMMABLE DAC GAIN CONTROL

Subaddress 0x0B

It is possible to adjust the DAC output signal gain up or down

from its absolute level. This is illustrated in Figure 71.

...

DAC 1 to DAC 3 are controlled by Register 0x0B.

CASE A

0000 0010 (0x02)

0000 0001 (0x01)

0000 0000 (0x00)

4.43

4.38

4.33

0.0360%

0.0180%

0.0000%

Reset value,

nominal

GAIN PROGRAMMED IN DAC OUTPUT LEVEL

REGISTERS, SUBADDRESS 0x0B

700mV

1111 1111 (0xFF)

1111 1110 (0xFE)

...

4.25

4.23

...

−0.0180%

−0.0360%

...

1100 0010 (0xC2)

1100 0001 (0xC1)

1100 0000 (0xC0)

4.018

4.013

4.008

−7.3640%

−7.3820%

−7.5000%

300mV

GAMMA CORRECTION

NEGATIVE GAIN PROGRAMMED IN

Subaddress 0x44 to Subaddress 0x57 for ED/HD,

Subaddress 0xA6 to Subaddress 0xB9 for SD

CASE B

DAC OUTPUT LEVEL REGISTERS,

SUBADDRESS 0x0B

700mV

Generally, gamma correction is applied to compensate for the

nonlinear relationship between signal input and output

brightness level (as perceived on a CRT). It can also be applied

wherever nonlinear processing is used.

Gamma correction uses the function

Signal_OUT= (Signal_IN)^γ

300mV

where γ = gamma correction factor.

Gamma correction is available for SD and ED/HD video. For

both variations, there are 20, 8-bit registers. They are used to

program Gamma Correction Curve A and Curve B.

Figure 71. Programmable DAC Gain—Positive and Negative Gain

In Case A of Figure 71, the video output signal is gained. The

absolute level of the sync tip and blanking level both increase

with respect to the reference video output signal. The overall

gain of the signal is increased from the reference signal.

ED/HD gamma correction is enabled using Subaddress 0x35,

Bit 5. ED/HD Gamma Correction Curve A is programmed at

Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma

Correction Curve B is programmed at Subaddress 0x4E to

Subaddress 0x57.

Rev. 0 | Page 53 of 96

ADV7390/ADV7391/ADV7392/ADV7393

SD gamma correction is enabled using Subaddress 0x88, Bit 6.

SD Gamma Correction Curve A is programmed at Subaddress

0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B

is programmed at Subaddress 0xB0 to Subaddress 0xB9.

To program the gamma correction registers, calculate the

10 programmable curve values using the following formula:

γ

⎛

⎜

⎝

⎞

⎟

⎠

n −16

240 −16

⎛

⎜

⎝

⎞

⎟

⎠

⎟

γ_n

=

×(240 −16) + 16

Gamma correction is performed on the luma data only. The

user can choose one of two correction curves, Curve A or

Curve B. Only one of these curves can be used at a time. For

ED/HD gamma correction, curve selection is controlled using

Subaddress 0x35, Bit 4. For SD gamma correction, curve

selection is controlled using Subaddress 0x88, Bit 7.

where:

γ_n= value to be written into the gamma correction register for

point n on the gamma correction curve

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224

γ = gamma correction factor

For example, setting γ = 0.5 for all programmable curve data

points results in the following y_nvalues:

The shape of the gamma correction curve is controlled by

defining the curve response at 10 different locations along the

curve. By altering the response at these locations, the shape of

the gamma correction curve can be modified. Between these

points, linear interpolation is used to generate intermediate

values. Considering the curve to have a total length of 256

points, the 10 programmable locations are at points 24, 32, 48,

64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255

are fixed and cannot be changed.

y

₂₄= [(8/224)^0.5× 224] + 16 = 58

₃₂= [(16/224)^0.5× 224] + 16 = 76

₄₈= [(32/224)^0.5× 224] + 16 = 101

₆₄= [(48/224)^0.5× 224] + 16 = 120

₈₀= [(64/224)^0.5× 224] + 16 = 136

₉₆= [(80/224)^0.5× 224] + 16 = 150

₁₂₈= [(112/224)^0.5× 224] + 16 = 174

₁₆₀= [(144/224)^0.5× 224] + 16 = 195

₁₉₂= [(176/224)^0.5× 224] + 16 = 214

₂₂₄= [(208/224)^0.5× 224] + 16 = 232

From curve locations 16 to 240, the values at the programmable

locations and, therefore, the response of the gamma correction

curve, should be calculated to produce the following result:

γ

x

_DESIRED= (x_INPUT

)

where:

x

_DESIRED= desired gamma corrected output

_INPUT= linear input signal

where the sum of each equation is rounded to the nearest integer.

The gamma curves in Figure 72 and Figure 73 are examples only;

any user-defined curve in the range from 16 to 240 is acceptable.

γ = gamma correction factor

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

300

250

200

150

100

50

VARIOUS GAMMA VALUES

300

250

SIGNAL OUTPUT

0.3

0.5

200

0.5

150

1.5

100

SIGNAL INPUT

1.8

50

0

50

100

150

LOCATION

200

250

0

50

100

150

LOCATION

200

250

Figure 72. Signal Input (Ramp) and Signal Output for Gamma 0.5

Figure 73. Signal Input (Ramp) and Selectable Output Curves

Rev. 0 | Page 54 of 96

ADV7390/ADV7391/ADV7392/ADV7393

The derivative of the incoming signal is compared to the three

programmable threshold values: ED/HD Adaptive Filter

Threshold A, Threshold B, and Threshold C (Subaddress 0x5B,

Subaddress 0x5C, and Subaddress 0x5D). The recommended

threshold range is 16 to 235, although any value in the range of

0 to 255 can be used.

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER

CONTROLS

Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D

There are three filter modes available on the ADV739x:

sharpness filter mode and two adaptive filter modes.

ED/HD Sharpness Filter Mode

The edges can then be attenuated with the settings in the

ED/HD Adaptive Filter Gain 1, Gain 2, and Gain 3 registers

(Subaddress 0x58, Subaddress 0x59 and Subaddress 0x5A), and

the ED/HD sharpness filter gain register (Subaddress 0x40).

To enhance or attenuate the Y signal in the frequency ranges

shown in Figure 74, the ED/HD sharpness filter must be

enabled (Subaddress 0x31, Bit 7 = 1) and the ED/HD adaptive

filter must be disabled (Subaddress 0x35, Bit 7 = 0).

There are two adaptive filter modes available. The mode is

selected using the ED/HD adaptive filter mode control

(Subaddress 0x35, Bit 6):

To select one of the 256 individual responses, the corresponding

gain values, ranging from −8 to +7 for each filter, must be

programmed into the ED/HD sharpness filter gain register at

Subaddress 0x40.

•

Mode A is used when the ED/HD adaptive filter mode

control is set to 0. In this case, Filter B (LPF) is used in the

adaptive filter block. In addition, only the programmed

values for Gain B in the ED/HD sharpness filter gain

register and ED/HD Adaptive Filter Gain 1, Gain 2, and

Gain 3 registers are applied when needed. The Gain A

values are fixed and cannot be changed.

ED/HD Adaptive Filter Mode

In ED/HD adaptive filter mode, the following registers are used:

•

ED/HD Adaptive Filter Threshold A

ED/HD Adaptive Filter Threshold B

ED/HD Adaptive Filter Threshold C

ED/HD Adaptive Filter Gain 1

ED/HD Adaptive Filter Gain 2

ED/HD Adaptive Filter Gain 3

•

Mode B is used when ED/HD adaptive filter mode control is

set to 1. In this mode, a cascade of Filter A and Filter B is used.

Both settings for Gain A and Gain B in the ED/HD sharpness

filter gain register and ED/HD Adaptive Filter Gain 1, Gain 2,

and Gain 3 registers become active when needed.

ED/HD sharpness filter gain register

To activate the adaptive filter control, the ED/HD sharpness

filter and the ED/HD adaptive filter must be enabled

(Subaddress 0x31, Bit 7 = 1, and Subaddress 0x35, Bit 7 = 1,

respectively).

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

1.5

1.4

1.6

1.5

1.4

1.3

1.2

1.1

1.0

1.3

1.2

1.1

1.0

ꢀ

INPUT

SIGNAL:

STEP

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.9

0.8

0.7

0.6

0.5

0

2

4

6

8

10

12

FREQUENCY (MHz)

FILTER A RESPONSE (Gain Ka)

FREQUENCY (MHz)

FILTER B RESPONSE (Gain Kb)

FREQUENCY (MHz)

FREQUENCY RESPONSE IN SHARPNESS

FILTER MODE WITH Ka = 3 AND Kb = 7

Figure 74. ED/HD Sharpness and Adaptive Filter Control Block

Rev. 0 | Page 55 of 96

ADV7390/ADV7391/ADV7392/ADV7393

d

e

a

b

R2

R4

1

R1

c

f

1

R2

CH1 500mV

REF A

M 4.00µs

1 9.99978ms

CH1

ALL FIELDS

CH1 500mV

REF A

M 4.00µs

1 9.99978ms

CH1

ALL FIELDS

500mV 4.00µs

Figure 75. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values

Adaptive Filter Control Application

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER

APPLICATION EXAMPLES

Sharpness Filter Application

The register settings in Table 47 are used to obtain the results

shown in Figure 77, that is, to remove the ringing on the input

Y signal, as shown in Figure 76. Input data is generated by an

external signal source.

The ED/HD sharpness filter can be used to enhance or

attenuate the Y video output signal. The register settings in

Table 46 were used to achieve the results shown in Figure 75.

Input data was generated by an external signal source.

Table 47. Register Settings for Figure 77

Subaddress

Register Setting

0x00

0xFC

Table 46. ED/HD Sharpness Control

Subaddress

Register Setting

Reference¹

0x01

0x38

0x02

0x20

0x00

0xFC

0x30

0x00

0x01

0x10

0x31

0x81

0x02

0x20

0x35

0x80

0x30

0x00

0x40

0x00

0x31

0x81

0x58

0xAC

0x40

0x00

a

b

c

d

e

f

0x59

0x9A

0x40

0x08

0x5A

0x5B

0x88

0x40

0x04

0x28

0x40

0x5C

0x5D

0x3F

0x40

0x80

0x64

0x40

0x22

¹See Figure 75.

Rev. 0 | Page 56 of 96

ADV7390/ADV7391/ADV7392/ADV7393

In DNR mode, if the absolute value of the filter output is

smaller than the threshold, it is assumed to be noise. A

programmable amount (coring gain border, coring gain data) of

this noise signal is subtracted from the original signal. In DNR

sharpness mode, if the absolute value of the filter output is less

than the programmed threshold, it is assumed to be noise as

before. However, if the level exceeds the threshold, now being

identified as a valid signal, a fraction of the signal (coring gain

border, coring gain data) is added to the original signal to boost

high frequency components and sharpen the video image.

In MPEG systems, it is common to process the video information

in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels

× 16 pixels for MPEG1 systems (block size control). DNR can

be applied to the resulting block transition areas known to

contain noise. Generally, the block transition area contains two

pixels. It is possible to define this area to contain four pixels

(border area).

Figure 76. Input Signal to ED/HD Adaptive Filter

It is also possible to compensate for variable block positioning

or differences in YCrCb pixel timing with the use of the DNR

block offset.

The digital noise reduction registers are three 8-bit registers.

They are used to control the DNR processing.

DNR MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

Figure 77. Output Signal from ED/HD Adaptive Filter (Mode A)

GAIN

CORING GAIN DATA

When changing the adaptive filter mode to Mode B

(Subaddress 0x35, Bit 6), the output shown in Figure 78

can be obtained.

CORING GAIN BORDER

NOISE

SIGNAL PATH

INPUT FILTER

BLOCK

FILTER

SUBTRACT

OUTPUT

SIGNAL IN

Y DATA

INPUT

< THRESHOLD?

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

–

FILTER OUTPUT

> THRESHOLD

+

DNR OUT

MAIN SIGNAL PATH

DNR

SHARPNESS

MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

NOISE

SIGNAL PATH

Figure 78. Output Signal from ED/HD Adaptive Filter (Mode B)

INPUT FILTER

BLOCK

FILTER

ADD SIGNAL

ABOVE

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

SD DIGITAL NOISE REDUCTION

Subaddress 0xA3 to Subaddress 0xA5

OUTPUT

Y DATA

INPUT

> THRESHOLD?

Digital noise reduction (DNR) is applied to the Y data only.

A filter block selects the high frequency, low amplitude compo-

nents of the incoming signal (DNR input select). The absolute

value of the filter output is compared to a programmable

threshold value (DNR threshold control). There are two DNR

modes available: DNR mode and DNR sharpness mode.

+

FILTER OUTPUT

< THRESHOLD

+

DNR OUT

MAIN SIGNAL PATH

Figure 79. SD DNR Block Diagram

Rev. 0 | Page 57 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Coring Gain Border—Subaddress 0xA3, Bits[3:0]

Block Size—Subaddress 0xA4, Bit 7

These four bits are assigned to the gain factor applied to border

areas. In DNR mode, the range of gain values is 0 to 1 in

increments of 1/8. This factor is applied to the DNR filter

output that lies below the set threshold range. The result is then

subtracted from the original signal.

This bit is used to select the size of the data blocks to be

processed. Setting the block size control function to Logic 1

defines a 16 pixel × 16 pixel data block, and Logic 0 defines an

8 pixel × 8 pixel data block, where one pixel refers to two clock

cycles at 27 MHz.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

DNR Input Select—Subaddress 0xA5, Bits[2:0]

These three bits are assigned to select the filter that is applied to

the incoming Y data. The signal that lies in the pass band of the

selected filter is the signal processed by DNR. Figure 82 shows

the filter responses selectable with this control.

Coring Gain Data—Subaddress 0xA3, Bits[7:4]

These four bits are assigned to the gain factor applied to the luma

data inside the MPEG pixel block. In DNR mode, the range of

gain values is 0 to 1 in increments of 1/8. This factor is applied

to the DNR filter output that lies below the set threshold range.

The result is then subtracted from the original signal.

1.0

FILTER D

0.8

FILTER C

0.6

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

0.4

0.2

0

FILTER B

APPLY DATA

APPLY BORDER

FILTER A

CORING GAIN CORING GAIN

O X X X X X X O O X X X X X X O

1

2

3

0

4

5

6

FREQUENCY (MHz)

OFFSET CAUSED

BY VARIATIONS IN

INPUT TIMING

O X X X X X X O O X X X X X X O

Figure 82. SD DNR Input Select

DNR Mode—Subaddress 0xA5, Bit 4

DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O

This bit controls the DNR mode selected. Logic 0 selects DNR

mode; Logic 1 selects DNR sharpness mode.

Figure 80. SD DNR Offset Control

DNR Threshold—Subaddress 0xA4, Bits[5:0]

DNR works on the principle of defining low amplitude, high

frequency signals as probable noise and subtracting this noise

from the original signal.

These six bits are used to define the threshold value in the range

of 0 to 63. The range is an absolute value.

In DNR mode, it is possible to subtract a fraction of the signal

that lies below the set threshold, assumed to be noise, from the

original signal. The threshold is set in DNR Register 1.

Border Area—Subaddress 0xA4, Bit 6

When this bit is set to Logic 1, the block transition area can be

defined to consist of four pixels. If this bit is set to Logic 0, the

border transition area consists of two pixels, where one pixel

refers to two clock cycles at 27 MHz.

When DNR sharpness mode is enabled, it is possible to add a

fraction of the signal that lies above the set threshold to the

original signal because this data is assumed to be valid data and

not noise. The overall effect is that the signal is boosted (similar

to using the extended SSAF filter).

720 × 485 PIXELS

2-PIXEL

(NTSC)

BORDER

DATA

Block Offset Control—Subaddress 0xA5, Bits[7:4]

Four bits are assigned to this control that allows a shift in the

data block of 15 pixels maximum. The coring gain positions are

fixed. The block offset shifts the data in steps of one pixel such

that the border coring gain factors can be applied at the same

position regardless of variations in input timing of the data.

8 × 8 PIXEL BLOCK 8 × 8 PIXEL BLOCK

Figure 81. SD DNR Border Area

Rev. 0 | Page 58 of 96

ADV7390/ADV7391/ADV7392/ADV7393

SD ACTIVE VIDEO EDGE CONTROL

Subaddress 0x82, Bit 7

At the start of active video, the first three pixels are multiplied

by ⅛, ½, and ⅞, respectively. Approaching the end of active

video, the last three pixels are multiplied by ⅞, ½, and ⅛,

respectively. All other active video pixels pass through

unprocessed.

The ADV739x is able to control fast rising and falling signals at

the start and end of active video to minimize ringing.

When the active video edge control feature is enabled

(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last

three pixels of the active video on the luma channel are scaled

so that maximum transitions on these pixels are not possible.

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

DISABLED

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

ENABLED

100 IRE

0 IRE

100 IRE

87.5 IRE

50 IRE

12.5 IRE

0 IRE

Figure 83. Example of Active Video Edge Functionality

VOLTS

0.5

IRE:FLT

100

50

0

F2

L135

–50

2

0

4

6

8

10

12

Figure 84. Example of Video Output with Subaddress 0x82, Bit 7 = 0

VOLTS

IRE:FLT

100

50

0

0.5

0

F2

L135

–50

–2

0

2

4

6

8

10

12

Figure 85. Example of Video Output with Subaddress 0x82, Bit 7 = 1

Rev. 0 | Page 59 of 96

ADV7390/ADV7391/ADV7392/ADV7393

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL

For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or

HSYNC

VSYNC

external synchronization signals provided on the

and

pins (see Table 49 to Table 51).

pins (see Table 48). It is also possible to output synchronization

HSYNC VSYNC

signals on the

and

Table 48. Timing Synchronization Signal Input Options

Signal

Condition

HSYNC

VSYNC

HSYNC

VSYNC

SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).¹

ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).

SD

In

VSYNC

/FIELD In

HSYNC

ED/HD

In

VSYNC

/FIELD In

¹SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).

Table 49. Timing Synchronization Signal Output Options

Signal

Condition

HSYNC

VSYNC

HSYNC

VSYNC

SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).¹

ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).²

SD

Out

VSYNC

/FIELD Out

HSYNC

ED/HD

Out

VSYNC

/FIELD Out

¹ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).

²ED/HD timing synchronization inputs must also be disabled, that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).

1

HSYNC

Table 50.

Output Control

ED/HD HSYNC

Control

Format (0x30, Bit 2) (0x34, Bit 1)

ED/HD Sync

Output Enable

(0x02, Bit 7)

SD Sync

Output Enable

(0x02, Bit 6)

ED/HD Input Sync

Signal on HSYNC Pin

Duration

x

0

1

Tristate.

–

HSYNC

See Error! Reference

source not found..

Pipelined SD

.

0

1

0

1

x

HSYNC

As per timing.

Pipelined ED/HD

.

Same as line blanking

interval.

Pipelined ED/HD

AV Code H bit.

based on

x

1

x

HSYNC

Same as embedded

Pipelined ED/HD

HSYNC

.

horizontal counter.

1

HSYNC

pulse is aligned with the falling edge of the embedded in the output video.

In all ED/HD standards where there is a

output, the start of the

1

VSYNC

Table 51.

Output Control

ED/HD VSYNC

Control

(0x34, Bit 2)

ED/HD Input

Sync Format

(0x30, Bit 2)

ED/HD Sync

Output Enable Output Enable

(0x02, Bit 7)

SD Sync

Signal on VSYNC Pin

(0x02, Bit 6)

Video Standard

Duration

x

0

1

x

Tristate.

–

Interlaced

VSYNC

/Field. See Error!

Pipelined SD

Reference source

not found..

0

1

x

0

1

x

VSYNC

As per or

Field signal timing.

Field.

Pipelined ED/HD

or field signal.

All HD interlaced

standards

All ED/HD progressive

standards

Pipelined Field signal

based on AV Code F bit.

VSYNC

Vertical blanking

interval.

Pipelined

based on

AV Code V bit.

All ED/HD standards

except 525p

VSYNC

based on vertical counter.

VSYNC

Pipelined ED/HD

based on vertical counter.

Aligned with

serration lines.

Pipelined ED/HD

525p

Vertical blanking

interval.

1

VSYNC

pulse is aligned with the falling edge of the embedded in the output video.

In all ED/HD standards where there is a

output, the start of the

Rev. 0 | Page 61 of 96

ADV7390/ADV7391/ADV7392/ADV7393

For CVBS/YC output configurations, if DAC 1 is unconnected,

only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and

DAC 3 power down.

LOW POWER MODE

Subaddress 0x0D, Bits[2:0]

For power sensitive applications, the ADV739x supports an

Analog Devices, Inc. proprietary low power mode of operation.

To utilize this low power mode, the DACs must be operating in

full-drive mode (R_SET= 510 Ω, R_L= 37.5 Ω). Low power mode is

not available in low drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω).

Low power mode can be independently enabled or disabled on

each DAC using Subaddress 0x0D, Bits[2:0]. Low power mode

is disabled by default on all DACs.

For YPrPb and RGB output configurations, if DAC 1 is

unconnected, all three DACs are powered down. DAC 2 is not

monitored for YPrPb and RGB output configurations.

Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable

is detected, the appropriate DAC or DACs remain powered up

for the duration of the frame. If no cable is detected, the

appropriate DAC or DACs power down until the next frame,

when the process is repeated.

In low power mode, DAC current consumption is content

dependent, and on a typical video stream, it can be reduced by

as much as 40%. For applications requiring the highest possible

video performance, low power mode should be disabled.

PIXEL AND CONTROL PORT READBACK

Subaddress 0x13, Subaddress 0x14, Subaddress 0x16

The ADV739x supports the readback of most digital inputs via

the I²C/SPI MPU port. This feature is useful for board-level

connectivity testing with upstream devices.

CABLE DETECTION

Subaddress 0x10, Bits[1:0]

The ADV739x includes an Analog Devices, Inc. proprietary

cable detection feature.

HSYNC VSYNC

, and

The pixel port (P[15:0] or P[7:0]),

,

SFL/MISO are available for readback via the MPU port.

The readback registers are located at Subaddress 0x13,

Subaddress 0x14, and Subaddress 0x16.

The cable detection feature is available on DAC 1 and DAC 2

when operating in full-drive mode (R_SET= 510 Ω, R_L= 37.5 Ω,

assuming a connected cable). The feature is not available in low-

drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω). For a DAC to be

monitored, the DAC must be powered up in Subaddress 0x00.

When using this feature, a clock signal should be applied to the

CLKIN pin to register the levels applied to the input pins.

The SD input mode (Subaddress 0x01, Bits[6:4] = 000) must be

selected when using this feature.

The cable detection feature can be used with all SD, ED, and

HD video standards. It is available for all output configurations,

that is, CVBS, YC, YPrPb, and RGB output configurations.

RESET MECHANISMS

Subaddress 0x17, Bit 1

For CVBS/YC output configurations, both DAC 1 and DAC 2

are monitored, that is, the CVBS and YC luma outputs are

monitored. For YPrPb and RGB output configurations, only

DAC 1 is monitored, that is, the luma or green output is

monitored.

A hardware reset is activated with a high-to-low transition on

RESET

the

pin in accordance with the timing specifications.

This resets all registers to their default values. After a hardware

reset, the MPU port is configured for I²C operation. For correct

device operation, a hardware reset is necessary after power-up.

Once per frame, the ADV739x monitors DAC 1 and/or DAC 2,

updating Subaddress 0x10, Bit 0 and/or Bit 1, respectively. If a

cable is detected on one of the DACs, the relevant bit is set to 0.

If not, the bit is set to 1.

The ADV739x also has a software reset accessible via the

I²C/SPI MPU port. A software reset is activated by writing a 1

to Subaddress 0x17, Bit 1. This resets all registers to their

default values. This bit is self-clearing, that is, after a 1 has been

written to the bit, the bit automatically returns to 0.

DAC AUTO POWER-DOWN

Subaddress 0x10, Bit 4

When operating in SPI mode, a software reset does not cause

the device to revert to I²C mode. For this to occur, a hardware

For power sensitive applications, a DAC auto power-down

feature can be enabled using Subaddress 0x10, Bit 4. This

feature is only available when the cable detection feature is

enabled.

RESET

reset via the

pin or a power-down needs to occur.

A hardware reset is necessary after power-up for correct device

operation. If no hardware reset functionality is required by the

pin can be connected to a RC network

to provide the hardware reset necessary after power-up. After

power-up, the time constant of the RC network holds the

pin low for long enough to cause a reset to take place.

All subsequent resets can be done via software.

With this feature enabled, the cable detection circuitry monitors

DAC 1 and/or DAC 2 once per frame, and if they are

unconnected, automatically powers down some or all of the

DACs. Which DAC or DACs are powered down depends on the

selected output configuration.

RESET

application, the

RESET

Rev. 0 | Page 61 of 96

ADV7390/ADV7391/ADV7392/ADV7393

PRINTED CIRCUIT BOARD LAYOUT AND DESIGN

DAC CONFIGURATIONS

Table 52. ADV739x Output Rates

Input Mode

(0x01, Bits[6:4])

The ADV739x contains three DACs. All three DACs can be

configured to operate in full-drive mode. Full-drive mode is

defined as 34.7 mA full-scale current into a 37.5 Ω load, R_L.

Full-drive is the recommended mode of operation for the DACs.

Oversampling

Output Rate (MHz)

SD

Off

On

Off

On

Off

On

27

(2×)

(8×)

(16×)

(1×)

(4×)

(8×)

(1×)

(2×)

(4×)

108

216

27

108

216

74.25

148.5

297

Alternatively, all three DACs can be configured to operate in low

drive mode. Low drive mode is defined as 4.33 mA full-scale

current into a 300 Ω load, R_L.

ED

The ADV739x contains a R_SETpin. A resistor connected between

the R_SETpin and AGND is used to control the full-scale output

current and, therefore, the output voltage levels of DAC 1, DAC 2,

and DAC 3. For full-drive operation, R_SETmust have a value

of 510 Ω and RL must have a value of 37.5 Ω. For low drive

operation, R_SETmust have a value of 4.12 kΩ, and R_Lmust have

a value of 300 Ω.

HD

Table 53. Output Filter Requirements

Cutoff

Attenuation

–50 dB @

(MHz)

Frequency

Application Oversampling (MHz)

The resistor connected to the R_SETpin should have a 1%

tolerance.

SD

ED

HD

2×

8×

16×

1×

4×

8×

1×

2×

4×

> 6.5

> 12.5

> 30

20.5

101.5

209.5

14.5

The ADV739x contains a compensation pin, COMP. A 2.2 nF

compensation capacitor should be connected from the COMP

pin to V_AA

.

95.5

VIDEO OUTPUT BUFFER AND OPTIONAL

OUTPUT FILTER

203.5

44.25

118.5

267

> 30

An output buffer is necessary on any DAC that operates in low

drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω). Analog Devices Inc.

produces a range of op amps suitable for this application, for

example, the AD8061. For more information about line driver

buffering circuits, see the relevant op amp data sheet.

10µH

DAC

OUTPUT

3

4

75Ω

BNC

OUTPUT

600Ω

22pF

600Ω

1

An optional reconstruction (anti-imaging) low-pass filter (LPF)

may be required on the ADV739x DAC outputs. The filter

specifications vary with the application. The use of 16× (SD),

8× (ED), or 4× (HD) oversampling can remove the requirement

for a reconstruction filter altogether.

560Ω

Figure 86. Example of Output Filter for SD, 16× Oversampling

For applications requiring an output buffer and reconstruction

filter, the ADA4430-1 and ADA4411-3 integrated video filter

buffers should be considered.

4.7µH

DAC

OUTPUT

3

75Ω

BNC

OUTPUT

6.8pF

600Ω

1

600Ω

4

560Ω

Figure 87. Example of Output Filter for ED, 8× Oversampling

DAC

OUTPUT

3

390nH

75Ω

BNC

OUTPUT

300Ω

3

1

33pF

75Ω

1

4

500Ω

Figure 88. Example of Output Filter for HD, 4× Oversampling

Rev. 0 | Page 62 of 96

ADV7390/ADV7391/ADV7392/ADV7393

CIRCUIT FREQUENCY RESPONSE

0

PRINTED CIRCUIT BOARD (PCB) LAYOUT

0

–10

–20

–30

–40

–50

–60

–70

–80

24n

21n

18n

15n

12n

9n

–30

The ADV739x is a highly integrated circuit containing both

precision analog and high speed digital circuitry. It has been

designed to minimize interference effects on the integrity of the

analog circuitry by the high speed digital circuitry. It is imperative

that these same design and layout techniques be applied to the

system-level design so that optimal performance is achieved.

MAGNITUDE (dB)

–60

–90

PHASE (Degrees)

–120

–150

–180

–210

–240

The layout should be optimized for lowest noise on the

ADV739x power and ground planes by shielding the digital

inputs and providing good power supply decoupling.

GROUP DELAY (Seconds)

6n

3n

0

It is recommended to use a 4-layer printed circuit board with

ground and power planes separating the signal trace layer and

the solder side layer.

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 89. Output Filter Plot for SD, 16× Oversampling

Component Placement

Component placement should be carefully considered to

separate noisy circuits, such as clock signals and high speed

digital circuitry from analog circuitry.

CIRCUIT FREQUENCY RESPONSE

0

480

18n

16n

–10

400

320

240

160

80

MAGNITUDE (dB)

The external loop filter components and components connected

to the COMP and R_SETpins should be placed as close as possible

to and on the same side of the PCB as the ADV739x. Adding

vias to the PCB to get the components closer to the ADV739x is

not recommended.

–20

–30

–40

–50

–60

–70

–80

–90

14n

PHASE

(Degrees)

12n

10n

8n

GROUP DELAY (Seconds)

It is recommended that the ADV739x be placed as close as

possible to the output connector, with the DAC output traces as

short as possible.

0

6n

–80

–160

–240

4n

The termination resistors on the DAC output traces should be

placed as close as possible to and on the same side of the PCB as

the ADV739x. The termination resistors should overlay the

PCB ground plane.

2n

0

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 90. Output Filter Plot for ED, 8× Oversampling

External filter and buffer components connected to the DAC

outputs should be placed as close as possible to the ADV739x to

minimize the possibility of noise pickup from neighboring

circuitry, and to minimize the effect of trace capacitance on

output bandwidth. This is particularly important when

operating in low drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω).

CIRCUIT FREQUENCY RESPONSE

0

200

120

40

PHASE

(Degrees)

MAGNITUDE (dB)

–10

–20

–30

–40

–50

GROUP DELAY (Seconds)

Power Supplies

It is recommended that a separate regulated supply be provided

for each power domain (V_AA, V_DD, V_{DD_IO}, and PV_DD). For

optimal performance, linear regulators rather than switch mode

regulators should be used. If switch mode regulators must be

used, care must be taken with regard to the quality of the output

voltage in terms of ripple and noise. This is particularly true for

the V_AAand PV_DDpower domains. Each power supply should be

individually connected to the system power supply at a single

point through a suitable filtering device, such as a ferrite bead.

–40

–120

–200

1

10

100

FREQUENCY (MHz)

Figure 91. Output Filter Plot for HD, 4× Oversampling

Rev. 0 | Page 63 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Power Supply Decoupling

Due to the high clock rates used, avoid long clock traces to the

ADV739x to minimize noise pickup.

It is recommended that each power supply pin be decoupled

with 10 nF and 0.1 μF ceramic capacitors. The V_AA, PV_DD

,

Any pull-up termination resistors for the digital inputs should

be connected to the V_DDpower supply.

V_{DD_IO}, and both V_DDpins should be individually decoupled to

ground. The decoupling capacitors should be placed as close as

possible to the ADV739x with the capacitor leads kept as short

as possible to minimize lead inductance.

Any unused digital inputs should be tied to ground.

Analog Signal Interconnect

DAC output traces should be treated as transmission lines with

appropriate measures taken to ensure optimal performance (for

example, impedance matched traces). The DAC output traces

should be kept as short as possible. The termination resistors on

the DAC output traces should be placed as close as possible to

and on the same side of the PCB as the ADV739x.

A 1 μF tantalum capacitor is recommended across the V_AA

supply in addition to the 10 nF and 0.1 μF ceramic capacitors.

Power Supply Sequencing

The ADV739x is robust to all power supply sequencing

combinations. Any particular sequence can be used.

Digital Signal Interconnect

To avoid crosstalk between the DAC outputs, it is

recommended that as much space as possible be left between

the traces connected to the DAC output pins. Adding ground

traces between the DAC output traces is also recommended.

The digital signal traces should be isolated as much as possible

from the analog outputs and other analog circuitry. Digital

signal traces should not overlay the V_AAor PV_DDpower planes.

Rev. 0 | Page 64 of 96

ADV7390/ADV7391/ADV7392/ADV7393

TYPICAL APPLICATION CIRCUIT

FERRITE BEAD

NOTES

V

DD_IO

V

POWER

DD_IO

1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED

TO THE COMP, R

CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS THE ADV739x.

33µF

10µF

0.1µF

0.01µF

SUPPLY

DECOUPLING

AND DAC OUTPUT PINS SHOULD BE LOCATED

SET

GND_IO

GND_IO GND_IO

FERRITE BEAD

PV

DD

2. WHEN OPERATING IN I2C MODE, THE I2C DEVICE ADDRESS IS

CONFIGURABLE USING THE ALSB/SPI_SS PIN:

PV

SUPPLY

DECOUPLING

POWER

DD

33µF

10µF

0.1µF

0.01µF

PGND

FERRITE BEAD

PGND

2

ALSB/SPI_SS = 0, I C DEVICE ADDRESS = 0xD4 OR 0x54

2

ALSB/SPI_SS = 1, I C DEVICE ADDRESS = 0xD6 OR 0x56

V

AA

DD

V

POWER

AA

33µF

10µF

0.1µF

0.01µF

AGND

1µF

3. THE RESISTOR CONNECTED TO THE R

SET

TOLERANCE.

PIN SHOULD HAVE A 1%

SUPPLY

DECOUPLING

AGND

FERRITE BEAD

AGND

4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULL-

DRIVE (R

= 510Ω, R = 37.5Ω).

L

SET

V

POWER SUPPLY

DECOUPLING FOR

EACH POWER PIN

DD

33µF

10µF

0.1µF

0.01µF

DGND

V

AA

2.2nF

P0

P1

P2

P3

P4

P5

P6

P7

COMP

R

SET

ADV739x

510Ω

AGND

PIXEL PORT INPUTS

DACs 1 TO 3 FULL DRIVE OPTION

(RECOMMENDED)

P8

P9

DACs 1 TO 3 LOW DRIVE OPTION

OPTIONAL LPF

P10

P11

P12

P13

P14

P15

DAC 1

DAC 2

DAC 3

DAC 1

DAC 2

DAC 3

ADV7392/

ADV7393

ONLY

R

SET

4.12kΩ

OPTIONAL LPF

75Ω

AGND

ADA4411-3

AGND AGND AGND

75Ω

DAC 1

DAC 2

DAC 3

DAC 1

DAC 2

DAC 3

HSYNC

VSYNC

CONTROL

INPUTS/OUTPUTS

LPF

300Ω

CLKIN

CLOCK INPUT

AGND

ADA4411-3

SDA/SCLK

SCL/MOSI

SFL/MISO

MPU PORT

INPUTS/OUTPUTS

75Ω

ALSB/SPI_SS

LPF

300Ω

RESET

AGND

EXTERNAL LOOP FILTER

ADA4411-3

PV

DD

12nF

75Ω

EXT_LF

LPF

150nF

170Ω

300Ω

LOOP FILTER COMPONENTS

SHOULD BE LOCATED

CLOSE TO THE EXT_LF

PIN AND ON THE

SAME SIDE OF THE PCB

AS THE ADV739x.

AGND

AGND PGND DGND DGND GND_IO

Figure 92. ADV739x Typical Application Circuit

Rev. 0 | Page 65 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 1–COPY GENERATION MANAGEMENT SYSTEM

When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i

CGMS data is applied to Line 19 and Line 582 of the luminance

vertical blanking interval.

SD CGMS

Subaddress 0x99 to Subaddress 0x9B

The ADV739x supports copy generation management system

(CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15

standards. CGMS data is transmitted on Line 20 of the odd fields

and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control

whether CGMS data is output on odd or even fields or both.

The HD CGMS data registers are at Subaddress 0x41,

Subaddress 0x42, and Subaddress 0x43.

The ADV739x also supports CGMS Type B packets in HD

mode (720p and 1080i) in accordance with CEA-805-A.

SD CGMS data can only be transmitted when the ADV739x is

configured in NTSC mode. The CGMS data is 20 bits long. The

CGMS data is preceded by a reference pulse of the same

amplitude and duration as a CGMS bit (see Figure 93).

When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),

720p CGMS data is applied to Line 23 of the luminance vertical

blanking interval.

When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),

1080i CGMS data is applied to Line 18 and Line 581 of the

luminance vertical blanking interval.

ED CGMS

Subaddress 0x41 to Subaddress 0x43

Subaddress 0x5E to Subaddress 0x6E

The HD CGMS Type B data registers are at Subaddress 0x5E to

Subaddress 0x6E.

525p

The ADV739x supports copy generation management system

(CGMS) in 525p mode in accordance with EIAJ CPR-1204-1.

CGMS CRC FUNCTIONALITY

If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS

CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS

data bits (C19 to C14) that comprise the 6-bit CRC check

sequence are automatically calculated on the ADV739x. This

calculation is based on the lower 14 bits (C13 to C0) of the data

in the CGMS data registers, and the result is output with the

remaining 14 bits to form the complete 20 bits of the CGMS

data. The calculation of the CRC sequence is based on the

polynomial x⁶+ x + 1 with a preset value of 111111.

When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p

CGMS data is inserted on Line 41. The 525p CGMS data

registers are at Subaddress 0x41, Subaddress 0x42, and

Subaddress 0x43.

The ADV739x also supports CGMS Type B packets in 525p

mode in accordance with CEA-805-A.

When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),

525p CGMS Type B data is inserted on Line 40. The 525p CGMS

Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.

If SD CGMS CRC or ED/HD CGMS CRC is disabled, all 20 bits

(C19 to C0) are output directly from the CGMS registers (CRC

must be calculated by the user manually).

625p

The ADV739x supports copy generation management system

(CGMS) in 625p mode in accordance with IEC 62375 (2004).

If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is

enabled, the upper six CGMS Type B data bits (P122 to P127)

that comprise the 6-bit CRC check sequence are automatically

calculated on the ADV739x. This calculation is based on the

lower 128 bits (H0 to H5 and P0 to P121) of the data in the

CGMS Type B data registers. The result is output with the

remaining 128 bits to form the complete 134 bits of the CGMS

Type B data. The calculation of the CRC sequence is based on

the polynomial x⁶+ x + 1 with a preset value of 111111.

When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p

CGMS data is inserted on Line 43. The 625p CGMS data

registers are at Subaddress 0x42 and Subaddress 0x43.

HD CGMS

Subaddress 0x41 to Subaddress 0x43

Subaddress 0x5E to Subaddress 0x6E

The ADV739x supports copy generation management system

(CGMS) in HD mode (720p and 1080i) in accordance with

EIAJ CPR-1204-2.

If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5

and P0 to P127) are output directly from the CGMS Type B

registers (CRC must be calculated by the user manually).

When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p

CGMS data is applied to Line 24 of the luminance vertical

blanking interval.

Rev. 0 | Page 66 of 96

ADV7390/ADV7391/ADV7392/ADV7393

+100 IRE

+70 IRE

CRC SEQUENCE

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0 IRE

–40 IRE

49.1µs ± 0.5µs

11.2µs

2.235µs ± 20ns

Figure 93. Standard Definition CGMS Waveform

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

70% ± 10%

0mV

–300mV

21.2µs ± 0.22µs

22T

5.8µs ± 0.15µs

6T

T = 1/(f_H× 33) = 963ns

f_H= HORIZONTAL SCAN FREQUENCY

T ± 30ns

Figure 94. Enhanced Definition (525p) CGMS Waveform

R = RUN-IN

S = START CODE

PEAK WHITE

C0

LSB

C13

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

R

S

500mV ± 25mV

SYNC LEVEL

MSB

13.7µs

5.5µs ± 0.125µs

Figure 95. Enhanced Definition (625p) CGMS Waveform

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

T ± 30ns

–300mV

17.2µs ± 160ns

4T

22T

3.128µs ± 90ns

T = 1/(f_H× 1650/58) = 781.93ns

f_H= HORIZONTAL SCAN FREQUENCY

1H

Figure 96. High Definition (720p) CGMS Waveform

Rev. 0 | Page 67 of 96

ADV7390/ADV7391/ADV7392/ADV7393

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

T ± 30ns

–300mV

22.84µs ± 210ns

22T

4T

4.15µs ± 60ns

T = 1/(f × 2200/77) = 1.038µs

H

f

= HORIZONTAL SCAN FREQUENCY

H

1H

Figure 97. High Definition (1080i) CGMS Waveform

CRC SEQUENCE

BIT 134

+700mV

START

BIT 1 BIT 2

70% ± 10%

.

0mV

–300mV

NOTES

1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.

Figure 98. Enhanced Definition (525p) CGMS Type B Waveform

CRC SEQUENCE

BIT 134

+700mV

START

BIT 1 BIT 2

70% ±10%

.

0mV

–300mV

NOTES

1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.

Figure 99. High Definition (720p and 1080i) CGMS Type B Waveform

Rev. 0 | Page 68 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 2–SD WIDE SCREEN SIGNALING

(see Figure 100). The latter portion of Line 23 (after 42.5 μs

Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B

HSYNC

from the falling edge of

) is available for the insertion of

The ADV739x supports wide screen signaling (WSS)

video. WSS data transmission on Line 23 can be enabled using

Subaddress 0x99, Bit 7. It is possible to blank the WSS portion

of Line 23 with Subaddress 0xA1, Bit 7.

conforming to the ETSI 300 294 standard. WSS data is

transmitted on Line 23. WSS data can only be transmitted when

the device is configured in PAL mode. The WSS data is 14 bits

long. The function of each of these bits is shown in Table 54.

The WSS data is preceded by a run-in sequence and a start code

Table 54. Function of WSS Bits

Bit Number

Bit Description

13 12 11 10

9

8

7

6

5

4

3

1

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Setting

Aspect Ratio, Format, Position

4:3, full format, N/A

14:9, letterbox, center

14:9, letterbox, top

16:9, letterbox, center

16:9, letterbox, top

>16:9, letterbox, center

14:9, full format, center

16:0, N/A, N/A

Mode

0

1

Camera mode

Film mode

Color Encoding

Helper Signals

0

1

Normal PAL

Motion Adaptive ColorPlus

Not present

0

1

Present

Reserved

0

Teletext Subtitles

0

1

No

Yes

Open Subtitles

0

1

0

1

0

1

No

Subtitles in active image area

Subtitles out of active image area

Reserved

Surround Sound

Copyright

0

1

No

Yes

0

1

No copyright asserted or unknown

Copyright asserted

Copying not restricted

Copying restricted

Copy Protection

0

1

500mV

RUN-IN

SEQUENCE

START

CODE

ACTIVE

VIDEO

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

11.0µs

38.4µs

42.5µs

Figure 100. WSS Waveform Diagram

Rev. 0 | Page 69 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 3–SD CLOSED CAPTIONING

All pixels inputs are ignored on Line 21 and Line 284 if closed

captioning is enabled.

Subaddress 0x91 to Subaddress 0x94

The ADV739x supports closed captioning conforming to the

standard television synchronizing waveform for color

transmission. When enabled, closed captioning is transmitted

during the blanked active line time of Line 21 of the odd fields

and Line 284 of the even fields. Closed captioning can be

enabled using Subaddress 0x83, Bits[6:5].

The FCC Code of Federal Regulations (CFR) Title 47 Section

15.119 and EIA-608 describe the closed captioning information

for Line 21 and Line 284.

The ADV739x uses a single buffering method. This means that

the closed captioning buffer is only 1-byte deep. Therefore,

there is no frame delay in outputting the closed captioning data

unlike other 2-byte deep buffering systems. The data must be

loaded one line before it is output on Line 21 and Line 284. A

Closed captioning consists of a 7-cycle sinusoidal burst that is

frequency and phase-locked to the caption data. After the clock

run-in signal, the blanking level is held for two data bits and is

followed by a Logic 1 start bit. Sixteen bits of data follow the start

bit. The data consists of two 8-bit bytes (seven data bits, and one

odd parity bit per byte). The data for these bytes is stored in SD

closed captioning registers (Subaddress 0x93 to Subaddress 0x94).

VSYNC

typical implementation of this method is to use

to

interrupt a microprocessor, which in turn loads the new data

(2 bytes) in every field. If no new data is required for transmis-

sion, 0s must be inserted in both data registers; this is called

nulling. It is also important to load control codes, all of which

are double bytes, on Line 21. Otherwise, a TV does not recognize

them. If there is a message such as “Hello World” that has an

odd number of characters, it is important to add a blank

character at the end to make sure that the end-of-caption,

2-byte control code lands in the same field.

The ADV739x also supports the extended closed captioning

operation, which is active during even fields and encoded on

Line 284. The data for this operation is stored in SD closed

captioning registers (Subaddress 0x91 to Subaddress 0x92).

The ADV739x automatically generates all clock run-in signals

and timing that support closed captioning on Line 21 and Line 284.

10.5 ± 0.25µs

12.91µs

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

P

A

R

I

T

Y

P

A

R

I

T

Y

S

T

A

R

T

D0 TO D6

BYTE 1

50 IRE

40 IRE

BYTE 0

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003µs

27.382µs

33.764µs

Figure 101. SD Closed Captioning Waveform, NTSC

Rev. 0 | Page 70 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 4–INTERNAL TEST PATTERN GENERATION

ED/HD TEST PATTERNS

SD TEST PATTERNS

The ADV739x is able to generate ED/HD color bar, black bar,

and hatch test patterns.

The ADV739x is able to generate SD color bar and black bar

test patterns.

The register settings in Table 57 are used to generate an ED

525p hatch test pattern. All other registers are set as normal/

default. Component YPrPb output is available on DAC 1 to

DAC 3. For component RGB output rather than YPrPb output,

0 should be written to Subaddress 0x02, Bit 5.

The register settings in Table 55 are used to generate an SD NTSC

75% color bar test pattern. All other registers are set as normal/

default. Component YPrPb output is available on DAC 1 to

DAC 3. Upon power-up, the subcarrier frequency registers

default to the appropriate values for NTSC.

Table 57. ED 525p Hatch Test Pattern Register Writes

Table 55. SD NTSC Color Bar Test Pattern Register Writes

Subaddress

Setting

Subaddress

Setting

0x00

0x1C

0x00

0x1C

0x01

0x10

0x82

0xC9

0x31

0x05

0x84

0x40

To generate an ED 525p black bar test pattern, the same settings

as shown in Table 57 should be used with an additional write of

0x24 to Subaddress 0x02.

For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9

should be written to Subaddress 0x82.

For component RGB output rather than YPrPb output, 0 should

be written to Subaddress 0x02, Bit 5.

To generate an ED 525p flat field test pattern, the same settings

shown in Table 57 should be used, except that 0x0D should be

written to Subaddress 0x31.

To generate an SD NTSC black bar test pattern, the same

settings shown in Table 55 should be used with an additional

write of 0x24 to Subaddress 0x02.

The Y, Cr, and Cb levels for the hatch and flat field test patterns

can be controlled using Subaddress 0x36, Subaddress 0x37, and

Subaddress 0x38, respectively.

For PAL output of either test pattern, the same settings are used,

except that Subaddress 0x80 is programmed to 0x11 and the

subcarrier frequency (F_SC) registers are programmed as shown

in Table 56.

For ED/HD standards other than 525p, the same settings as

shown in Table 57 (and subsequent comments) are used except

that Subaddress 0x30, Bits[7:3] are updated as appropriate.

Table 56. PAL F_SCRegister Writes

Subaddress

Description

Setting

0xCB

0x8C

F_SC0

0x8D

F_SC1

0x8A

0x09

0x8E

F_SC2

0x8F

F_SC3

0x2A

Note that when programming the F_SCregisters, the user must

write the values in the sequence F_SC0, F_SC1, F_SC2, F_SC3. The full

F

_SCvalue to be written is only accepted after the F_SC3 write is

complete.

Rev. 0 | Page 71 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 5–SD TIMING

Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)

The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All

timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after

VSYNC

HSYNC

each line during active picture and retrace. If the

and

pins are not used, they should be tied high when using this mode.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

b

C

r

8

0

F

A

B

A

B

A

B

8

0

C

b

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

1440 CLOCK

268 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

280 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 102. SD Timing Mode 0, Slave Option

Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)

The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output on

HSYNC

VSYNC

and the F bit is output on

.

DISPLAY

VERTICAL BLANK

4

522

523

524

525

1

2

3

5

6

7

8

10

11

20

21

22

9

H

F

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

H

F

ODD FIELD

EVEN FIELD

Figure 103. SD Timing Mode 0, Master Option, NTSC

Rev. 0 | Page 72 of 96

ADV7390/ADV7391/ADV7392/ADV7393

DISPLAY

VERTICAL BLANK

622

623

624

625

4

22

23

1

2

3

5

6

7

21

H

F

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

335

336

318

334

309

310

311

312

313

314

315

316

317

319

320

H

F

ODD FIELD

EVEN FIELD

Figure 104. SD Timing Mode 0, Master Option, PAL

ANALOG

VIDEO

H

F

Figure 105. SD Timing Mode 0, Master Option, Data Transitions

Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)

HSYNC

In this mode, the ADV739x accepts horizontal synchronization and odd/even field signals. When

is low, a transition of the field

input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624.

HSYNC

VSYNC

and pins, respectively.

and FIELD are input on the

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

3

4

5

7

9

10

11

1

2

6

8

HSYNC

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

FIELD

ODD FIELD EVEN FIELD

Figure 106. SD Timing Mode 1,Slave Option, NTSC

Rev. 0 | Page 73 of 96

ADV7390/ADV7391/ADV7392/ADV7393

DISPLAY

VERTICAL BLANK

3

4

5

7

622

623

624

625

1

2

6

21

22

23

HSYNC

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

FIELD

ODD FIELD

EVEN FIELD

Figure 107. SD Timing Mode 1, Slave Option, PAL

Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)

In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When

HSYNC

is low, a transition of the

field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624.

HSYNC HSYNC

Pixel data is latched on the rising clock edge following the timing signal transitions.

and FIELD are output on the

and

VSYNC

pins, respectively.

HSYNC

FIELD

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 108. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)

Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)

In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both

VSYNC VSYNC HSYNC

HSYNC

and

is high indicates the start of an even field. The

VSYNC HSYNC VSYNC

inputs indicates the start of an odd field. A

low transition when

HSYNC

ADV739x automatically blanks all normally blank lines as per CCIR-624.

pins, respectively.

and

are input on the

and

Rev. 0 | Page 74 of 96

ADV7390/ADV7391/ADV7392/ADV7393

DISPLAY

VERTICAL BLANK

522

523

524

525

1

3

4

5

7

8

20

21

22

2

6

10

11

9

HSYNC

VSYNC

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

Figure 109. SD Timing Mode 2, Slave Option, NTSC

DISPLAY

VERTICAL BLANK

4

622

623

624

625

1

2

3

5

6

7

21

22

23

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

Figure 110. SD Timing Mode 2, Slave Option, PAL

Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)

In this mode, the ADV739x can generate horizontal and vertical synchronization signals. A coincident low transition of both

VSYNC

HSYNC

and

inputs indicates the start of an odd field.

VSYNC HSYNC

A

low transition when

is high indicates the start of an even field. The ADV739x automatically blanks all normally blank

VSYNC HSYNC VSYNC

HSYNC

lines as per CCIR-624.

and

are output on the

and

pins, respectively.

HSYNC

VSYNC

PIXEL

DATA

Cb

Cr

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 111. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)

Rev. 0 | Page 75 of 96

ADV7390/ADV7391/ADV7392/ADV7393

HSYNC

VSYNC

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

PIXEL

DATA

Cb

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 112. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)

Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)

HSYNC

In this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When

is high, a

transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as

HSYNC

VSYNC

HSYNC

VSYNC

and pins, respectively.

per CCIR-624.

and

are output in master mode and input in slave mode on the

DISPLAY

VERTICAL BLANK

522

523

524

525

4

20

21

22

10

11

1

2

3

5

6

7

8

9

HSYNC

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

FIELD

ODD FIELD EVEN FIELD

Figure 113. SD Timing Mode 3, NTSC

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

5

6

7

21

22

23

HSYNC

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

FIELD

EVEN FIELD ODD FIELD

Figure 114. SD Timing Mode 3, PAL

Rev. 0 | Page 76 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 6–HD TIMING

DISPLAY

FIELD 1

VERTICAL BLANKING INTERVAL

1124

1125

1

2

3

4

5

6

7

8

20

21

22

560

VSYNC

HSYNC

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

VSYNC

HSYNC

VSYNC

Input Timing

Figure 115. 1080i

and

Rev. 0 | Page 77 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 7–VIDEO OUTPUT LEVELS

SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10

Pattern: 100% Color Bars

700mV

300mV

Figure 119. Y Levels—PAL

Figure 116. Y Levels—NTSC

700mV

Figure 120. Pr Levels—PAL

Figure 117. Pr Levels—NTSC

700mV

Figure 121. Pb Levels—PAL

Figure 118. Pb Levels—NTSC

Rev. 0 | Page 78 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ED/HD YPrPb OUTPUT LEVELS

EIA-770.3, STANDARD FOR Y

EIA-770.2, STANDARD FOR Y

INPUT CODE

940

OUTPUT VOLTAGE

940

700mV

64

300mV

EIA-770.3, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

EIA-770.2, STANDARD FOR Pr/Pb

960

OUTPUT VOLTAGE

960

512

64

600mV

700mV

512

64

Figure 124. EIA-770.3 Standard Output Signals (1080i/720p)

Figure 122. EIA-770.2 Standard Output Signals (525p/625p)

Y–OUTPUT LEVELS FOR

FULL INPUT SELECTION

EIA-770.1, STANDARD FOR Y

INPUT CODE

1023

OUTPUT VOLTAGE

INPUT CODE

OUTPUT VOLTAGE

782mV

940

700mV

714mV

64

300mV

286mV

Pr/Pb–OUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

INPUT CODE

1023

EIA-770.1, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

960

700mV

512

64

300mV

Figure 125. Output Levels for Full Input Selection

Figure 123. EIA-770.1 Standard Output Signals (525p/625p)

Rev. 0 | Page 79 of 96

ADV7390/ADV7391/ADV7392/ADV7393

SD/ED/HD RGB OUTPUT LEVELS

Pattern: 100%/75% Color Bars

R

700mV/525mV

300mV

G

700mV/525mV

300mV

B

700mV/525mV

300mV

Figure 128. HD RGB Output Levels—RGB Sync Disabled

Figure 126. SD/ED RGB Output Levels—RGB Sync Disabled

R

700mV/525mV

600mV

700mV/525mV

300mV

0mV

300mV

0mV

G

700mV/525mV

600mV

700mV/525mV

300mV

0mV

300mV

0mV

B

700mV/525mV

600mV

700mV/525mV

300mV

0mV

300mV

0mV

Figure 129. HD RGB Output Levels—RGB Sync Enabled

Figure 127. SD/ED RGB Output Levels—RGB Sync Enabled

Rev. 0 | Page 80 of 96

ADV7390/ADV7391/ADV7392/ADV7393

SD OUTPUT PLOTS

VOLTS

0.6

VOLTS IRE:FLT

100

0.4

0.2

0

0.5

50

0

–0.2

F1

L76

–50

L608

0

10

20

30

40

50

60

0

10

20

30

MICROSECONDS

PRECISION MODE OFF

40

50

60

MICROSECONDS

NOISE REDUCTION: 0.00dB

APL = 39.1%

625 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

APL = 44.5%

525 LINE NTSC

SLOW CLAMP TO 0.00V AT 6.72μµs

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1, 2, 3, 4

SYNCHRONOUS SYNC =A

FRAMES SELECTED 1, 2

Figure 133. PAL Color Bars (75%)

Figure 130. NTSC Color Bars (75%)

VOLTS

0.5

VOLTS IRE:FLT

0.6

0.4

50

0.2

0

00

0

–0.2

F2

L238

L575

20

0

10

20

30

40

50

60

0

10

30

40

50

60

70

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL = 44.3%

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NO BUNCH SIGNAL

PRECISION MODE OFF

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00V AT 6.72μµs

SYNCHRONOUS SYNC = SOURCE

FRAMES SELECTED 1, 2

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

Figure 131. NTSC Luma

Figure 134. PAL Luma

VOLTS IRE:FLT

VOLTS

0.5

0.4

50

0.2

0

–0.2

–0.4

–50

–0.5

F1

L76

L575

20

0

10

20

30

40

50

60

0

10

30

40

50

60

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC SOURCE.

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

SYNCHRONOUS SYNC = B

FRAMES SELECTED 1, 2

Figure 132. NTSC Chroma

Figure 135. PAL Chroma

Rev. 0 | Page 81 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 8–VIDEO STANDARDS

0

DATUM

H

SMPTE 274M

ANALOG WAVEFORM

DIGITAL HORIZONTAL BLANKING

272T

*1

4T

1920T

DIGITAL

ACTIVE LINE

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

EAV CODE

SAV CODE

F

0

F

0

C

r

C

INPUT PIXELS

Y

V

Y

b

r

H*

4 CLOCK

192

0

2199

SAMPLE NUMBER

2112

2116 2156

44

188

2111

FVH* = FVH AND PARITY BITS

SAV/EAV: LINE 1–562: F = 0

SAV/EAV: LINE 563–1125: F = 1

SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1

SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FRAME RATE OF 30Hz: 40 SAMPLES

FOR A FRAME RATE OF 25Hz: 480 SAMPLES

Figure 136. EAV/SAV Input Data Timing Diagram (SMPTE 274M)

SMPTE 293M

ANALOG WAVEFORM

ANCILLARY DATA

(OPTIONAL)

DIGITAL

SAV CODE

F

EAV CODE

F

ACTIVE LINE

F

0

F

0

C

b

C

r

C

INPUT PIXELS

V

Y

V

Y

r

Y

H*

4 CLOCK

853 857

SAMPLE NUMBER

719

723 736

DATUM

799

0

719

0

H

DIGITAL HORIZONTAL BLANKING

FVH* = FVH AND PARITY BITS

SAV: LINE 43–525 = 200H

SAV: LINE 1–42 = 2AC

EAV: LINE 43–525 = 274H

EAV: LINE 1–42 = 2D8

Figure 137. EAV/SAV Input Data Timing Diagram (SMPTE 293M)

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

522 523 524 525

1

2

5

6

7

8

9

12

13

14

15

16

42

43

44

Figure 138. SMPTE 293M (525p)

Rev. 0 | Page 82 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

12

13

1

2

5

6

7

8

9

43

44

45

622 623

624

625

4

10

11

Figure 139. ITU-R BT.1358 (625p)

DISPLAY

VERTICAL BLANKING INTERVAL

1

2

3

4

5

6

7

747

748

749

750

26

27

744

745

8

25

Figure 140. SMPTE 296M (720p)

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 1

560

1

2

5

6

7

8

21

22

1124

1125

3

4

20

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

Figure 141. SMPTE 274M (1080i)

Rev. 0 | Page 83 of 96

ADV7390/ADV7391/ADV7392/ADV7393

APPENDIX 9–CONFIGURATION SCRIPTS

The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by

default. If required for a specific application, further features can be enabled. Table 58 lists the scripts available for SD modes of operation.

Similarly, Table 89 and Table 106 list the scripts available for ED and HD modes of operation, respectively.

STANDARD DEFINITION

Table 58. SD Configuration Scripts

Input Format

525i (NTSC)

Input Data Width

Synchronization Format

EAV/SAV

Input Color Space

YCrCb

Output Color Space

YPrPb

CVBS/Y-C (S-Video)

Table Number

8-Bit SDR

Table 59

Table 60

Table 61

Table 62

Table 63

Table 64

Table 65

Table 66

Table 67

Table 68

Table 69

Table 70

Table 71

Table 72

Table 73

525i (NTSC)

8-Bit SDR

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

YCrCb

RGB

YPrPb

8-Bit SDR

RGB

10-Bit SDR

16-Bit SDR

YPrPb

HSYNC VSYNC

/

HSYNC VSYNC

/

EAV/SAV

CVBS/ Y-C (S-Video)

RGB

HSYNC VSYNC

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

CVBS/ Y-C (S-Video)

RGB

/

HSYNC VSYNC

/

RGB

625i (PAL)

8-Bit SDR

10-Bit SDR

16-Bit SDR

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

/

YCrCb

RGB

YPrPb

CVBS/Y-C (S-Video)

YPrPb

Table 74

Table 75

Table 76

Table 77

Table 78

Table 79

Table 80

Table 81

Table 82

Table 83

Table 84

Table 85

Table 86

Table 87

Table 88

RGB

EAV/SAV

YPrPb

HSYNC VSYNC

/

HSYNC VSYNC

/

EAV/SAV

CVBS/Y-C (S-Video)

RGB

HSYNC VSYNC

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

CVBS/Y-C (S-Video)

RGB

/

HSYNC VSYNC

RGB

/

Table 59. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out

Table 60. 8-Bit 525i YCrCb In (EAV/SAV), CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x82

0xCB

Pixel data valid. CVBS/S-Video out.

SSAF PrPb filter enabled. Active video

edge control enabled. Pedestal enabled.

Rev. 0 | Page 84 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 61. 8-Bit 525i YCrCb In, YPrPb Out

Subaddress Setting Description

Table 64. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0x8A

0xC9

0x0C

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x82

0x88

0xC9

0x10

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

10-bit input enabled.

Table 65. 10-Bit 525i YCrCb In, YPrPb Out

Subaddress Setting Description

Table 62. 8-Bit 525i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

RGB output enabled. RGB output sync

enabled.

enabled. 1.3 MHz chroma filter enabled.

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Table 63. 8-Bit 525i YCrCb In, RGB Out

Subaddress Setting Description

Table 66. 10-Bit 525i YCrCb In, CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0xCB

Pixel data valid. CVBS/S-Video out. SSAF

PrPb filter enabled. Active video edge

control enabled. Pedestal enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x8A

0x0C

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Rev. 0 | Page 85 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out

Table 70. 16-Bit 525i YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

RGB output enabled. RGB output sync

enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x10

10-bit input enabled.

0x88

0x8A

0x08

0x0C

16-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Table 68. 10-Bit 525i YCrCb In, RGB Out

Subaddress Setting Description

Table 71. 16-Bit 525i RGB In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

0x87

0x88

0x8A

0x80

0x08

0x0C

RGB input enabled.

16-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Table 69. 16-Bit 525i YCrCb In, YPrPb Out

Subaddress Setting Description

Table 72. 16-Bit 525i RGB In, CVBS/Y-C Out

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

Subaddress Setting Description

All DACs enabled. PLL enabled (16×).

SD input mode.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

NTSC standard. SSAF luma filter

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. pedestal enabled.

enabled. 1.3 MHz chroma filter enabled.

0x82

0xCB

Pixel data valid. CVBS/S-Video out. SSAF

PrPb filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x8A

0x08

0x0C

16-bit input enabled.

HSYNC VSYNC

Timing Mode 2 (Slave).

synchronization.

/

0x87

0x88

0x8A

0x80

0x08

0x0C

RGB input enabled.

16-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Rev. 0 | Page 86 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 73. 16-Bit 525i RGB In, RGB Out

Table 76. 8-Bit 625i YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0x8A

0xC1

0x0C

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x87

0x88

0x8A

0x80

0x08

0x0C

RGB input enabled.

16-bit input enabled.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Table 74. 8-Bit 625i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

Table 77. 8-Bit 625i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

RGB output enabled. RGB output sync

enabled.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Table 75. 8-Bit 625i YCrCb In (EAV/SAV), CVBS/Y-C Out

Subaddress Setting Description

Table 78. 8-Bit 625i YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x82

0xC3

Pixel data valid. CVBS/S-Video out.

SSAF PrPb filter enabled. Active video

edge control enabled.

RGB output enabled. RGB output sync

enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x8A

0x0C

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Rev. 0 | Page 87 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 79. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

Table 82. 10-Bit 625i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

RGB output enabled. RGB output sync

enabled.

0x82

0x88

0xC1

0x10

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

10-bit input enabled.

0x88

0x8C

0x8D

0x8E

0x8F

0x10

0xCB

0x8A

0x09

0x2A

10-bit input enabled.

PAL F_SCvalue.

Table 80. 10-Bit 625i YCrCb In, YPrPb Out

Subaddress Setting Description

PAL F_SCvalue.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

PAL F_SCvalue.

All DACs enabled. PLL enabled (16×).

SD input mode.

Table 83. 10-Bit 625i YCrCb In, RGB Out

Subaddress Setting Description

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

RGB output enabled. RGB output sync

enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Table 81. 10-Bit 625i YCrCb In, CVBS/Y-C Out

Subaddress Setting Description

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

Table 84. 16-Bit 625i YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x82

0xC3

Pixel Data Valid. CVBS/S-Video Out.

SSAF PrPb Filter Enabled. Active Video

Edge Control Enabled.

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

0x88

0x8A

0x08

0x0C

16-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Rev. 0 | Page 88 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 85. 16-Bit 625i YCrCb In, RGB Out

Table 87. 16-Bit 625i RGB In, CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0xC3

Pixel data valid. CVBS/S-Video out.

SSAF PrPb filter enabled. Active video

edge control enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x87

0x88

0x8A

0x80

0x08

0x0C

RGB input enabled.

16-bit input enabled.

0x88

0x8A

0x08

0x0C

16-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Table 88. 16-Bit 625i RGB In, RGB Out

Subaddress Setting Description

Table 86. 16-Bit 625i RGB In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x87

0x88

0x8A

0x80

0x08

0x0C

RGB input enabled.

16-bit input enabled.

0x87

0x88

0x8A

0x80

0x08

0x0C

RGB input enabled.

16-bit input enabled.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

Timing Mode 2 (Slave). HSYNC/VSYNC

synchronization.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

PAL F_SCvalue.

Rev. 0 | Page 89 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ENHANCED DEFINITION

Table 89. ED Configuration Scripts

Input Format

Input Data Width

Synchronization Format

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

/

Input Color Space

YCrCb

Output Color Space

Table Number

Table 98

Table 100

Table 99

Table 101

Table 90

Table 91

525p

8-Bit DDR

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

10-Bit DDR

16-Bit SDR

YCrCb

525p

YCrCb

Table 92

Table 93

RGB

625p

8-Bit DDR

10-Bit DDR

16-Bit SDR

EAV/SAV

YCrCb

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

Table 102

Table 104

Table 103

Table 105

Table 94

Table 95

Table 96

Table 97

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

RGB

/

Table 90. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

Table 93. 16-Bit 525p YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x04

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

525p @ 59.94 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

RGB output enabled. RGB output sync

enabled.

0x31

0x01

Pixel data valid.

0x30

0x31

0x00

0x01

525p @ 59.94 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

Pixel data valid.

Table 91. 16-Bit 525p YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x00

Software reset.

Table 94. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x1C

Software reset.

525p @ 59.94 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

0x31

0x01

Pixel data valid.

625p @ 50 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

0x31

0x01

Pixel data valid.

Table 92. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

Table 95. 16-Bit 625p YCrCb In, YPrPb Out

Subaddress Setting Description

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x18

Software reset.

RGB output enabled. RGB output sync

enabled.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

0x30

0x31

0x04

0x01

525p @ 59.94 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

625p @ 50 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

Pixel data valid.

0x31

0x01

Pixel data valid.

Rev. 0 | Page 90 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out

Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

RGB output enabled. RGB output sync

enabled.

0x02

0x30

0x31

0x10

0x04

0x01

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x1C

0x01

625p @ 50 Hz. EAV/SAV synchroniza-

tion. EIA-770.2 output levels.

525p @ 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

Pixel data valid.

Table 97. 16-Bit 625p YCrCb In, RGB Out

Subaddress Setting Description

Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

RGB output enabled. RGB output sync

enabled.

0x02

0x30

0x10

0x04

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x18

0x01

625p @ 50 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

525p @ 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

Pixel data valid.

0x31

0x33

0x01

0x6C

Pixel data valid.

10-bit input enabled.

Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

0x30

0x31

0x04

0x01

525p @ 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

Pixel data valid.

0x30

0x31

0x1C

0x01

625p @ 50 Hz. EAV/SAV synchroniza-

tion. EIA-770.2 output levels.

Pixel data valid.

Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

0x30

0x04

525p @ 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x31

0x33

0x01

0x6C

Pixel data valid.

0x30

0x1C

625p @ 50 Hz. EAV/SAV synchroniza-

tion. EIA-770.2 output levels.

10-bit input enabled.

0x31

0x33

0x01

0x6C

Pixel data valid.

10-bit input enabled.

Rev. 0 | Page 91 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 105. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 104. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x10

0x1C

RGB output enabled. RGB output sync

enabled.

625p @ 50 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

0x02

0x30

0x31

0x10

0x1C

0x01

RGB output enabled. RGB output sync

enabled.

625p @ 50 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

0x31

0x33

0x01

0x6C

Pixel data valid.

10-bit input enabled.

Pixel data valid.

HIGH DEFINITION

Table 106. HD Configuration Scripts

Input Format

Input Data Width

Synchronization Format

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

/

Input Color Space

YCrCb

Output Color Space

Table Number

Table 115

Table 117

Table 116

Table 118

Table 107

Table 108

Table 109

Table 110

720p

8-Bit DDR

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

10-Bit DDR

16-Bit SDR

YCrCb

720p

YCrCb

RGB

1080i

8-Bit DDR

10-Bit DDR

16-Bit SDR

EAV/SAV

YCrCb

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

Table 119

Table 121

Table 120

Table 122

Table 111

Table 112

Table 113

Table 114

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

RGB

/

Rev. 0 | Page 92 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 112. 16-Bit 1080i YCrCb In, YPrPb Out

Subaddress Setting Description

Table 107. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x18

Software reset.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x2C

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

720p @ 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x31

0x01

Pixel data valid. 4× oversampling.

0x31

0x01

Pixel data valid. 4× oversampling.

Table 113. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 108. 16-Bit 720p YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x28

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

RGB output enabled. RGB output sync

enabled.

720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

0x30

0x31

0x6C

0x01

1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x31

0x01

Pixel data valid. 4× oversampling.

Table 109. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 114. 16-Bit 1080i YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

RGB output enabled. RGB output sync

enabled.

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x2C

0x01

720p @ 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x30

0x31

0x18

0x01

1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

Table 110. 16-Bit 720p YCrCb In, RGB Out

Subaddress Setting Description

Table 115. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x2C

0x01

720p @ 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x30

0x31

0x28

0x01

720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

Table 116. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

Table 111. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x6C

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x30

0x2C

720p @ 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x31

0x01

Pixel data valid. 4× oversampling.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Rev. 0 | Page 93 of 96

ADV7390/ADV7391/ADV7392/ADV7393

Table 117. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out

Table 120. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x31

0x10

0x2C

0x01

RGB output enabled. RGB output sync

enabled.

0x30

0x6C

1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

720p @ 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Pixel data valid. 4× oversampling.

Table 121. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 118. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x31

0x10

0x6C

0x01

RGB output enabled. RGB output sync

enabled.

0x02

0x30

0x10

0x2C

RGB output enabled. RGB output sync

enabled.

1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

720p @ 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Table 122. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 119. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x10

0x6C

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x6C

0x01

1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Rev. 0 | Page 94 of 96

ADV7390/ADV7391/ADV7392/ADV7393

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

3.10 SQ

2.95

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

0.80 MAX

0.65 TYP

3.50 REF

12° MAX

EXPOSED PADDLE MUST BE SOLDERED

TO PCB GROUND FOR PROPER

HEAT DISSIPATION, NOISE IMMUNITY AND

MECHANICAL STRENGTH BENEFITS.

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 142. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BCS SQ

EXPOSED

PAD

(BOT TOM VIEW)

0.50

0.40

0.30

21

10

20

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

EXPOSED PADDLE MUST BE SOLDERED

TO PCB GROUND FOR PROPER

HEAT DISSIPATION, NOISE IMMUNITY AND

MECHANICAL STRENGTH BENEFITS.

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 143. 40-Lead Frame Chip Scale Package [LFCSP]

(CP-40)

Dimensions shown in millimeters

Rev. 0 | Page 95 of 96

ADV7390/ADV7391/ADV7392/ADV7393

ORDERING GUIDE

Macrovision¹

Model

Temperature Range Anti-Taping

Package Description

Package Option

CP-32-2

CP-40

ADV7390BCPZ²

−40°C to +85°C

Yes

No

Yes

No

N/A

Yes

No

Yes

No

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ADV739x Evaluation Platform Front-End Board.

ADV7390 Evaluation Board

ADV7390BCPZ-REEL²−40°C to +85°C

ADV7391BCPZ²

ADV7391BCPZ-REEL²−40°C to +85°C

ADV7392BCPZ²

−40°C to +85°C

ADV7392BCPZ-REEL²−40°C to +85°C

ADV7393BCPZ²

−40°C to +85°C

ADV7393BCPZ-REEL²−40°C to +85°C

EVAL-ADV739xFEZ^{2, 3}

EVAL-ADV7390EBZ²

EVAL-ADV7391EBZ²

ADV7391 Evaluation Board

ADV7392 Evaluation Board

ADV7393 Evaluation Board

EVAL-ADV7392EBZ²

EVAL-ADV7393EBZ²

¹Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video.

²Z = Pb-free.

³To be used in conjunction with any one of the ADV793x evaluation boards; this front-end board contains an Analog Devices decoder and Xilinx Spartan-3 FPGA.

2

Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C

2

Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D06234-0-10/06(0)

Rev. 0 | Page 96 of 96


型号：	ADV7393
厂家：	ADI
描述：	Low Power, Chip Scale 10-Bit SD/HD Video Encoder 低功耗，芯片级，10位标清/高清视频编码器编码器
文件：	总96页 (文件大小：2253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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