ADV7400AKSTZ-1101 [ADI]
10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer; 10位综合型多格式SDTV / HDTV视频解码器和RGB图形数字化仪
| 型号： | ADV7400AKSTZ-1101 |
| 厂家： | 
ADI |
| 描述： | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| 文件： | 总16页 (文件大小：772K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADV7400A
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, nominal input range = 1.6 V, operating
temperature range, unless otherwise noted.
1 2
,
Table 1. Electrical Characteristics
Parameter
Symbol Test Conditions
Min Typ
Max
Unit
STATIC PERFORMANCE3
Resolution (each ADC)
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
N
10
2.ꢀ
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
INL
BSL at 27 MHz (at a 10-bit level)
0.6
−0.6/+0.7
INL
INL
INL
DNL
DNL
DNL
DNL
BSL at ꢀ4 MHz (at a 10-bit level)
BSL at 74 MHz (at a 10-bit level)
BSL at 110 MHz (at an 8-bit level)4
At 27 MHz (at a 10-bit level)
At ꢀ4 MHz (at a 10-bit level)
At 74 MHz (at a 10-bit level)
At 110 MHz (at an 8-bit level)4
−1.2/+1.ꢀ
−0.9/+1.6
−0.2/+0.2ꢀ −0.3/+0.7
−0.2/+0.2ꢀ
0.8
−0.2/+1.ꢀ
Input High Voltage
Input Low Voltage
XTAL High Voltage
XTAL Low Voltage
Input High Voltage
Input Low Voltage
VIH
VIL
VIH
VIL
VIH
VIL
IIN
2
V
V
V
V
V
V
µA
µA
pF
0.8
0.4
Pin 38
Pin 38
1.2
0.7
HS_IN, VS_IN low trigger mode
HS_IN, VS_IN low trigger mode
Pins listed in Note ꢀ
All other input pins
0.4
Input Current
−60
−10
+60
+10
10
Input Capacitance6
DIGITAL OUTPUTS
CIN
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
VOH
VOL
ILEAK
ISOURCE = 0.4 mA
ISINK = 3.2 mA
Pins listed in Note 7
All other output pins
2.4
V
V
µA
µA
pF
0.4
60
10
20
Output Capacitance6
POWER REQUIREMENTS6
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
COUT
DVDD
DVDDIO
PVDD
1.6ꢀ 1.8
3.0 3.3
1.6ꢀ 1.8
2
3.6
2
V
V
V
Analog Power Supply
Digital Core Supply Current
AVDD
IDVDD
3.1ꢀ 3.3
3.4ꢀ
V
CVBS input sampling at ꢀ4 MHz
Graphics RGB sampling at 110 MHz
CVBS input sampling at ꢀ4 MHz
Graphics RGB sampling at 110 MHz
ꢀ4 MHz
110 MHz
CVBS input sampling at ꢀ4 MHz
Graphics RGB sampling at 110 MHz
82
62
2
17
10.ꢀ
6
8ꢀ
218
1.ꢀ
12.ꢀ
20
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
4
Digital I/O Supply Current
PLL Supply Current
IDVDDIO
IPVDD
4
Analog Supply Current
IAVDD
4
Power-Down Current
Green Mode Power-Down
Power-Up Time
IPWRDN
IPWRDNG
TPWRUP
Sync bypass function
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +8ꢀ°C.
3 All ADC linearity tests performed at input range of full scale are −12.ꢀ%, and at zero scale they are +12.ꢀ%.
4 Specifications for the ADV7400AKSTZ-110 and the ADV7400ABSTZ-110 only.
ꢀ Pins: 1, 2, 3, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 3ꢀ, 4ꢀ, 79, 83, 84, 87, 88, 9ꢀ, 96, 97, 100.
6 Guaranteed by characterization.
7 Pins: 4ꢀ, 34, 33, 32, 31, 30, 29, 24, 14, 13 (P20 to P29).
Rev. A | Page 3 of 16
ADV7400A
VIDEO SPECIFICATIONS
AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless
otherwise noted.
Table 2. Video Specifications1, 2, 3
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
DP
DG
LNL
CVBS I/P, modulated ꢀ step
CVBS I/P, modulated ꢀ step
CVBS I/P, ꢀ step
0.ꢀ
0.ꢀ
0.ꢀ
0.7
0.7
0.7
degree
%
%
Luma ramp
ꢀ4
ꢀ8
ꢀ6
60
60
dB
dB
dB
SNR Unweighted
Analog Front End Crosstalk
Luma flat field
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
−ꢀ
40
+ꢀ
70
%
Hz
FSC Subcarrier Lock Range
Color Lock in Time
Sync Depth Range
1.3
60
kHz
line
%
20
ꢀ
200
200
Color Burst Range
%
Vertical Lock Time
2
100
field
line
Horizontal Lock Time
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
HUE
CL_AC
1
1
degree
%
%
ꢀ
400
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
0.ꢀ
0.4
0.2
%
degree
%
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
CVBS, 1 V input
CVBS, 1 V input
1
1
%
%
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +8ꢀ°C.
3 Guaranteed by characterization.
Rev. A | Page 4 of 16
ADV7400A
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless
otherwise noted.
Table 3. Timing Characteristics1, 2, 3
Parameter
Symbol Test Conditions
Min
Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range4
I2C® PORT
27.0
MHz
ppm
kHz
ꢀ0
110
110
14.8
12.82ꢀ
MHz
SCLK Frequency
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
t1
t2
t3
t4
tꢀ
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
Reset Pulse Width
ꢀ
ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio
t9:t10
4ꢀ:ꢀꢀ
ꢀꢀ:4ꢀ % duty
cycle
DATA and CONTROL OUTPUTS
Data Output Transition Time (SDP)
Data Output Transition Time (SDP)
Data Output Transition Time (CP)
Data Output Transition Time (CP)
Data Output Transition Time DDR (CP)ꢀ t1ꢀ
Data Output Transition Time DDR (CP)ꢀ t16
Data Output Transition Time DDR (CP)ꢀ t17
Data Output Transition Time DDR (CP)ꢀ t18
DATA and CONTROL INPUTS
t11
t12
t13
t14
Negative clock edge to start of valid data
3.4
2.4
1.1
2.2
ns
ns
ns
ns
ns
ns
ns
ns
End of valid data to negative clock edge
End of valid data to negative clock edge
Negative clock edge to start of valid edge
Positive clock edge to end of valid data
Start of valid data to positive clock edge
Negative clock edge to end of valid data
−2.7 + TLLC1/4
−1.3 + TLLC1/4
−2.1 + TLLC1/4
Start of valid data to negative clock edge −0.9 + TLLC1/4
Input Setup Time
t19
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
9
2.2
7
ns
ns
ns
ns
Input Hold Time
t20
DE_IN, data inputs
1
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +8ꢀ°C.
3 Guaranteed by characterization.
4 Maximum LLC1 frequency is 80 MHz for the ADV7400AKSTZ-80.
ꢀ DDR timing specifications depend on LLC1 output pixel clock; TLCC1/4 = 9.2ꢀ ns at LLC1 = 27 MHz.
Rev. A | Page ꢀ of 16
ADV7400A
ANALOG SPECIFICATIONS
AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless
otherwise noted.
Table 4. Analog Specifications1, 2, 3
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
0.1
10
1.7
0.7ꢀ
0.7ꢀ
60
µF
MΩ
V
mA
mA
µA
µA
Clamps switched off
Voltage Clamp Level
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
SDP only
SDP only
SDP only
SDP only
60
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +8ꢀ°C.
3 Guaranteed by characterization.
THERMAL SPECIFICATIONS
Table 5. Thermal Specifications
Thermal Characteristic
Symbol Test Conditions
θJC 4-layer PCB with solid ground plane
θJA
Typ
Unit
°C/W
°C/W
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal Resistance
7
30
4-layer PCB with solid ground plane (still air)
Rev. A | Page 6 of 16
ADV7400A
ABSOLUTE MAXIMUM RATINGS
Table 6.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD to AGND
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO – PVDD
DVDDIO – DVDD
AVDD – PVDD
4 V
2.2 V
2.2 V
4 V
−0.3 V to +0.3V
−0.3 V to +0.3 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
AVDD – DVDD
Analog Inputs to AGND
AGND − 0.3 V to
AVDD + 0.3 V
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Infrared Reflow Soldering (20 sec)
1ꢀ0°C
−6ꢀ°C to +1ꢀ0°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 16
ADV7400A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AIN12
AIN5
P32
PIN 1
2
P31
3
AIN11
AIN4
INT
4
HS/CS
5
AIN10
AGND
CAPC2
CAPC1
BIAS
DGND
6
DVDDIO
7
P15
8
P14
9
P13
10
P12
AGND
CML
ADV7400A
11
DGND
12
REFOUT
AVDD
CAPY2
CAPY1
AGND
NC
DVDD
LQFP
TOP VIEW
(Not to Scale)
13
14
15
16
17
18
19
20
21
22
23
24
25
P29
P28
SFL/SYNC_OUT
SCLK2
DGND
DVDDIO
SDA2
P11
AIN3
AIN9
AIN2
AIN8
P10
AIN1
P9
AIN7
P8
SOG
P27
AGND
P7
NC = NO CONNECT
Figure 2. LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
ꢀ, 11, 17, 40, 89
49, ꢀ0, ꢀ1, 60, 66, 70 AGND
6, 18
12, 39, 90
63
DGND
G
G
P
P
P
P
I
Digital Ground.
Analog Ground.
DVDDIO
DVDD
AVDD
PVDD
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
47, 48
ꢀ4, ꢀ6, ꢀ8, 72, 74,
76, ꢀ3, ꢀꢀ, ꢀ7, 71,
73, 7ꢀ
AIN1 to AIN12
42, 41, 28, 27, 26,
P2 to P9,
O
Video Pixel Output Port.
2ꢀ, 23, 22, 10, 9, 8, 7, P12 to P19
94, 93, 92, 91
33, 32, 31, 30, 29,
24, 14, 13
44, 43, 21, 20, 4ꢀ,
34, 2, 1, 100, 97, 96,
9ꢀ, 88, 87, 84, 83
P22 to P29
I/O
I
Video Pixel Input/Output Port.
Video Pixel Input Port.
P0, P1, P10, P11,
P20 to P21,
P31 to P40
Rev. A | Page 8 of 16
ADV7400A
Pin No.
Mnemonic
Type
Description
3
INT
O
Interrupt Pin. This pin can be programmed active low or active high. When SDP/CP
status bits change, this pin triggers an interrupt. The set of events which triggers an
interrupt can be modified via I2C registers.
4
HS/CS
O
Horizontal Synchronization/Composite Synchronization. HS is a horizontal
synchronization output signal in SDP and CP modes. CS is a digital composite
synchronization signal that can be selected while in CP mode.
99
98
VS
O
O
Vertical Synchronization. Vertical synchronization output signal in SDP and CP
modes.
Field Synchronization/Data Enable. Field synchronization output signal in all
interlaced video modes. This pin also can be enabled as a data enable signal in CP
mode to allow direct connection to a HDMI/DVI Tx IC.
FIELD/DE
81, 19
82, 16
80
SDA1, SDA2
SCLK1, SCLK2
ALSB
I/O
I2C Port Serial Data Input/Output Pin. SDA1 is the data line for the control port and
SDA2 is the data line for the VBI readback port.
I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock line for the
control port, and SCLK2 is the clock line for the VBI data readback port.
This pin selects the I2C address for the ADV7400A control and VBI readback ports.
When set to a Logic 0, ALSB sets the address for a write to control port of 0x40 and
the readback address for the VBI port of 0x21. When set to a Logic 1, ALSB sets the
address for a write to the control port of 0x42 and the readback address for the VBI
port of 0x23.
I
I
78
36
RESET
LLC1
I
System Reset Input, Active Low. A minimum low reset pulse width of ꢀ ms is required
to reset the ADV7400A circuitry.
Line-locked output clock for the pixel data output by the ADV7400A (the range is
13.ꢀ MHz to 110 MHz for the ADV7400AKSTZ-110; 13.ꢀ MHz to 80 MHz for the
ADV7400AKSTZ-80).
O
38
37
XTAL
I
Input pin for 27 MHz crystal, or it can be overdriven by an external 3.3 V 27 MHz clock
oscillator source to clock the ADV7400A.
This pin should be connected to the 27 MHz crystal or left as a no connect if an
external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7400A. In
crystal mode the crystal must be a fundamental crystal.
XTAL1
O
46
1ꢀ
ELPF
SFL/SYNC_OUT
O
O
The recommend external loop filter must be connected to this ELPF pin.
SFL (Subcarrier Frequency Lock). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when this decoder is connected to any Analog
Devices digital video encoder.
SYNC_OUT is the sliced sync output signal available only in CP mode.
64
6ꢀ
61, 62
68, 69
67
REFOUT
CML
CAPY1 to CAPY2
CAPC1 to CAPC2
BIAS
O
O
I
I
O
Internal Voltage Reference Output.
Common-Mode Level Pin for the Internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor between this pin and
ground.
86
HS_IN/CS_IN
I
Can be configured in CP mode to be either a digital HS input signal or a digital CS
input signal, which are used to extract timing in ꢀ-wire or 4-wire RGB mode.
8ꢀ
79
VS_IN
DE_IN
I
I
VS Input Signal. Used in CP mode for ꢀ-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode, for example, 24-bit
RGB data from a DVI Rx IC.
ꢀ9
3ꢀ
NC
DCLK_IN
NC
I
No Connect Pin. This pin can be tied to AGND or AVDD.
Clock Input Signal. Used in 24-bit digital input mode and also in digital CVBS input
mode.
ꢀ2
77
SOG
SOY
I
I
Sync On Green Input Pin. Used in embedded sync mode.
Sync On Luma Input Pin. Used in embedded sync mode.
Rev. A | Page 9 of 16
ADV7400A
DETAILED FUNCTIONALITY
ANALOG FRONT END
•
•
Luminance digital noise reduction (DNR)
•
•
•
Three high quality 10-bit ADCs enable true 8-bit video
decoder
Color controls include hue, brightness, saturation, contrast,
and Cr and Cb offset controls
12 analog input channel mux enables multisource
connection without the requirement of an external mux
•
Certified Macrovision® copy protection detection on
composite and S-video for all worldwide formats
(PAL/NTSC/SECAM)
Three current and voltage clamp control loops ensure any
dc offsets are removed from the video signal
•
•
•
•
4× oversampling (54 MHz) for CVBS and S-video modes
Line-locked clock output (LLC)
SDP PIXEL DATA OUTPUT MODES
•
•
•
8-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
Letterbox detection supported
Free-run output mode provides stable timing when no
video input is present
16-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
•
•
•
•
•
•
•
•
Vertical blanking interval data processor
Closed captioning (CC) and extended data service (EDS)
Wide screen signaling (WSS)
24-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
CP PIXEL DATA OUTPUT MODES
•
Single data rate (SDR) 16-bit 4:2:2 YCrCb for all standards
Copy generation management system (CGMS)
EDTV
•
Single data rate (SDR) 24-bit 4:4:4 YCrCb/RGB for all
standards
Gemstar™ 1×/2× electronic program guide-compatible
Clocked from a single 27 MHz crystal
•
•
Double data rate (DDR) 8-bit 4:2:2 YCrCb for all standards
Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all
standards
Subcarrier frequency lock (SFL) output for downstream
video encoder
COMPOSITE AND S-VIDEO PROCESSING
•
Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N, Nc
60) and SECAM B/D/G/K/L standards in the form of
CVBS and S-video
•
•
Differential gain typically 0.5%
Differential phase typically 0.5°
COMPONENT VIDEO PROCESSING
•
Super adaptive 2D 5-line comb filters for NTSC and PAL
give superior chrominance and luminance separation for
composite video
•
Formats supported include 525i, 625i, 525p, 625p, 720p,
1080i, and many other HDTV formats
•
•
Full automatic detection and autoswitching of all
worldwide standards (PAL/NTSC/SECAM)
•
Automatic adjustments include gain (contrast) and offset
(brightness); manual adjustment controls are also
supported
Automatic gain control with white peak mode ensures the
video is always processed without loss of the video
processing range
•
•
•
•
Support for analog component YPrPb/RGB video formats
with embedded sync or with separate HS, VS, or CS
•
•
Adaptive digital line length tracking (ADLLT)
Any-to-any 3 × 3 color space conversion matrix supports
YCrCb-to-RGB and RGB-to-YCrCb
Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
Standard identification (STDI) enables system level
component format detection
•
•
IF filter block compensates for high frequency luma
attenuation due to tuner SAW filter
Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
Chroma transient improvement (CTI)
Rev. A | Page 10 of 16
ADV7400A
•
•
Free-run output mode provides stable timing when no
video input is present
DIGITAL VIDEO INPUT PORT
•
Support for raw 10-bit CVBS data from digital tuner
Arbitrary pixel sampling support for nonstandard video
sources
•
Support for 24-bit RGB input data from DVI Rx chip,
output converted to YCrCb 4:2:2
RGB GRAPHICS PROCESSING
•
Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p,
1080i, 720p, VGA to SXGA @ 60 Hz input data from
HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
•
110 MSPS conversion rate supports RGB input resolutions
up to 1280 × 1024 @ 60 Hz (SXGA); (80 MSPS conversion
rate for ADV7400AKSTZ-80)
GENERAL FEATURES
•
Automatic or manual clamp and gain controls for graphics
modes
•
HS, VS, and FIELD output signals with programmable
position, polarity, and width
•
•
•
•
Contrast and brightness controls
INT
•
Programmable interrupt request output pin,
SDP/CP status changes
, signals
Sampling PLL clock with 500 ps p-p jitter at 110 MSPS
32-phase DLL allows optimum pixel clock sampling
•
•
Supports two I2C host port interfaces (control and VBI)
Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power power-down mode, and green
PC mode
Automatic detection of sync source and polarity by SSPD
block
•
•
Standard identification is enabled by STDI block
•
•
Industrial temperature range (−40°C to +85°C)
RGB can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric backend
IC interfacing
110 MHz and 80 MHz speed grades (ADV7400AKSTZ-
110 and ADV7400AKSTZ-80)
•
100-pin 14 mm × 14 mm Pb-free LQFP package
•
•
Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
Arbitrary pixel sampling support for nonstandard video
sources
Rev. A | Page 11 of 16
ADV7400A
DETAILED DESCRIPTION
The ADV7400A implements a patented adaptive-digital-line-
length-tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7400A to track and decode poor quality video sources
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The SDP contains a chroma transient
improvement (CTI) processor. This processor increases the
edge rate on chroma transitions, resulting in a sharper video
image.
ANALOG FRONT END
The ADV7400A analog front end includes three 10-bit ADCs,
which digitize the analog video signal before applying it to the
SDP or CP (see Table 8 for sampling rates). The analog front
end uses differential channels to each ADC to ensure high
performance in a mixed-signal application.
The front end also includes a 12-channel input mux, which
enables multiple video signals to be applied to the ADV7400A.
Current and voltage clamps are positioned in front of each ADC
to ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping either in the CP or SDP.
The SDP can process a variety of VBI data services, such as
closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7400A SDP
section has a Macrovision 7.1 detection circuit, which allows it
to detect Types I, II, and III protection levels. The decoder is
fully robust to all Macrovision signal inputs.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
anti-aliasing filters. This has the benefit of an increased signal-
to-noise ratio (SNR).
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range
of component video formats in any color space. Component
video standards supported by the CP are 525i, 625i, 525p, 625p,
720p, 1080i, 1250i, VGA up to SXGA @ 60 Hz, and many other
standards not listed here.
Table 8. Maximum ADC Sampling Rates
Model
Max ADC Sampling Rate
ADV7400AKSTZ-80
ADV7400AKSTZ-110
80 MHz
110 MHz
The CP section of the ADV7400A also contains an automatic
gain control (AGC) block. In cases where no embedded sync is
present, the video gain can be set manually. The AGC block is
followed by a digital clamp circuit that ensures the video signal
is clamped to the correct blanking level. Automatic adjustments
within the CP include gain (contrast) and offset (brightness);
manual adjustment controls are also supported.
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite and S-video formats. The
video standards supported by the SDP include PAL B/D/I/G/H,
PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and
SECAM B/D/G/K/L. The ADV7400A can automatically detect
the video standard and process it accordingly.
A fully programmable any-to-any 3 × 3 color space conversion
matrix is placed between the analog front end and the CP
section. This enables YPrPb to RGB and RGB to YCrCb conver-
sions. Many other standards of color space may be implemented
using the color space converter.
The SDP has a 5-line super adaptive 2D comb filter that gives
superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to tuner SAW filter.
The output section of the CP is highly flexible. It can be config-
ured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edge of the clock. In SDR
mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these
modes HS, VS, and FIELD/DE (where applicable) timing refer-
ence signals are provided. In DDR mode, the ADV7400A can be
configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb
pixel output interface with corresponding timing signals.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
Rev. A | Page 12 of 16
ADV7400A
VBI extraction of CGMS data is performed by the CP section of
the ADV7400A for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the I2C
interface. For more detailed product information about the
ADV7400A, contact your local ADI sales office or email
video.products@analog.com.
The ADV7400A is capable of supporting an external DVI/
HDMI receiver. The digital interface expects 24-bit 4:4:4 or
16-bit 4:2:2 bit data (either graphics RGB or component video
YCrCb), accompanied by HS, VS, DE, and a fully synchro-nous
clock signal. The data is processed in the CP and output as 16-
bit 4:2:2 YCrCb data.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these types
of signals.
Rev. A | Page 13 of 16
ADV7400A
TIMING DIAGRAMS
t3
t5
t3
SDA1/SDA2
t6
t1
SCLK1/SCLK2
t2
t7
t4
t8
Figure 3. I2C Timing
t9
t10
LLC1
t11
t12
P2–P9, P12–P19,
P22–P29, VS, HS,
FIELD/DE,
SFL/SYNC_OUT
Figure 4. Pixel Port and Control Output SDR Timing (SD Core)
t9
t10
LLC1
t13
t14
P2–P9, P12–P19,
P22–P29
Figure 5. Pixel Port SDR Timing (CP Core)
LLC1
t16
t18
t15
t17
P6–P9,
P12–P19
Figure 6. Pixel Port DDR Timing (CP Core)
Rev. A | Page 14 of 16
ADV7400A
t9
t10
LLC1
t13
t14
VS, HS,
FIELD/DE
Figure 7. Control Output SDR/DDR Timing (CP Core)
DCLK_IN
t20
t9
t10
HS_IN
VS_IN
DE_IN
CONTROL
INPUTS
P0–P1, P10–P11,
P20–P21, P22–P29,
P31–P32, P33–P40
t19
Figure 8. Digital Input Port and Control Input Timing
Rev. A | Page 1ꢀ of 16
ADV7400A
OUTLINE DIMENSIONS
16.00
BSC SQ
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
25
51
50
0.15
0.05
26
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 9. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADV7400AKSTZ-1101
ADV7400AKSTZ-801
ADV7400ABSTZ-1101
EVAL-ADV7400AEBM
Temperature Range
Package Description
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
Evaluation Board
Package Option
ST-100
ST-100
−2ꢀ°C to +70°C
−2ꢀ°C to +70°C
−40°C to + 8ꢀ°C
ST-100
1 Z = Pb-free part. The ADV7400A is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on
the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 2ꢀꢀ°C
(
ꢀ°C). In addition, it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb
solder pastes at conventional reflow temperatures of 220°C to 23ꢀ°C.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05000–0–3/05(A)
Rev. A | Page 16 of 16
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