ADV7481 [ADI]
Integrated Video Decoder and Dual Mode HDMI/MHL Receiver;
| 型号： | ADV7481 |
| 厂家： | 
ADI |
| 描述： | Integrated Video Decoder and Dual Mode HDMI/MHL Receiver |
| 文件： | 总22页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated Video Decoder and
Dual Mode HDMI/MHL Receiver
ADV7481
Data Sheet
Adaptive TMDS equalizer
FEATURES
5 V detect and Hot Plug assert
Component video processor
Analog input
Worldwide NTSC/PAL/SECAM color demodulation support
with autodetection
One 10-bit ADC, 4× oversampling for CVBS, Y/C, and YPbPr
8 analog video input channels with on-chip antialiasing filter
Fully differential, pseudo differential, and single-ended
CVBS video input support
STB diagnostics on differential video inputs
CVBS (composite), Y/C (S-Video), and YPbPr (component)
video input support
Fast switching capability between analog inputs
Adaptive contrast enhancement (ACE)
Excellent common-mode noise rejection capabilities
Rovi (Macrovision) copy protection detection
Up to 4 V common-mode input range solution
Vertical blanking interval (VBI) data slicer
Mobile High-Definition Link (MHL) capable receiver
High-bandwidth Digital Content Protection (HDCP)
authentication and decryption support
75 MHz maximum pixel clock frequency, allowing HDTV
formats up to 720p/1080i at 60 Hz
Any-to-any 3 × 3 color space conversion (CSC) matrix
Contrast/brightness/hue/saturation video adjustment
Timing adjustments controls for horizontal sync
(HS)/vertical sync (VS)/data enable (DE) timing
Video mute function
Serial digital audio output interface
HDMI/MHL audio extraction support
Advanced audio muting feature
I2S-compatible, left justified, and right justified audio
output modes
8-channel TDM output mode available
2 Mobile Industry Processor Interface (MIPI) Camera Serial
Interface 2 (CSI-2) transmitters
4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing
options for HDMI/MHL/SDP/digital input port sources
1-lane transmitter for standard definition processor (SDP)
sources
8-bit digital input/output port
General
2-wire serial microprocessor unit (MPU) interface (I2C
compatible)
24 bits per pixel mode supported
HDCP repeater support, up to 25 KSVs supported
Adaptive TMDS equalizer
High-Definition Multimedia Interface (HDMI) capable
receiver
−40°C to +85°C temperature grade
100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package
Qualified for automotive applications
HDCP authentication and decryption support
162 MHz maximum pixel clock frequency, allowing HDTV
formats up to 1080p and display resolutions up to UXGA
(1600 × 1200 at 60 Hz)
HDCP repeater support, up to 25 KSVs supported
Integrated CEC controller, CEC 1.4 compatible
APPLICATIONS
Portable devices
Automotive infotainment (head unit and rear seat
entertainment systems)
HDMI repeaters and video switches
FUNCTIONAL BLOCK DIAGRAM
ADV7481
RXCP/RXCN
MHL_SENSE
CBUS
RX0P/RX0N
RX1P/RX1N
RX2P/RX2N
DDC_SCL/
CD_PULLUP
DDC_SDA
HPD/CBUS
CD_SENSE
SPI_MISO
SPI_MOSI
SPI_SCLK
SPI SLAVE
DDC
SPI_CS
HDMI/MHL
RECEIVER
ALSB
SCLK
SDATA
I2C SLAVE
AUDIO
PROCESSOR
CEC
HPD
INTRQ1 TO
INTRQ3
INTERRUPTS
CONTROLLER
CEC
RX_5V/VBUS
VBUS_EN
EDID RAM
HDCP
CP
CORE
I2S_MCLK
I2S_LRCLK
I2S_SCLK
I2S_SDATA
AUDIO OUTPUT
FORMATTER
LLC
8-BIT TTL
INPUT/OUTPUT
P0 TO P7
4-LANE
MIPI CSI-2
TRANSMITTER
CLKAP/CLKAN
DA0P/DA0N TO
DA3P/DA3N
AIN1 TO
AIN8
SD
CORE
AFE
1-LANE
MIPI CSI-2
TRANSMITTER
CLKBP/CLKBN
DB0P/DB0N
DIAG1 TO
DIAG4
DIAGNOSTIC
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2014 Analog Devices, Inc. All rights reserved.
www.analog.com
ADV7481
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power-Down Sequence.............................................................. 17
Theory of Operation ...................................................................... 18
Combined HDMI/MHL Receiver............................................ 18
MHL Receiver............................................................................. 18
HDMI Receiver........................................................................... 18
Component Processor ............................................................... 19
Analog Front End....................................................................... 19
Short to Battery Diagnostics..................................................... 19
Standard Definition Processor ................................................. 20
8-Bit Digital Input/Output Port ............................................... 20
Audio Processing........................................................................ 21
MIPI CSI-2 Transmitters........................................................... 21
Interrupts..................................................................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Automotive Products................................................................. 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Detailed Functional Block Diagram .............................................. 4
Specifications..................................................................................... 5
Electrical Characteristics............................................................. 5
Analog Video Specifications ....................................................... 7
MIPI Video Output Specifications............................................. 8
Analog Specifications................................................................... 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Power Supply Recommendation .................................................. 17
Power-Up Sequence ................................................................... 17
REVISION HISTORY
6/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 22
Data Sheet
ADV7481
GENERAL DESCRIPTION
The ADV7481 is an integrated video decoder and combined
HDMI®/MHL® receiver. It is targeted at connectivity enabled
head units requiring a wired, uncompressed digital audio/video
link from smartphones and other consumer electronics devices
to support streaming and integration of cloud-based
multimedia content and applications into an automotive
infotainment system.
well as S-Video and YPbPr video signals, supporting a wide
range of consumer and automotive video sources.
Short to battery (STB) events can be detected on differential
input video signals. STB protection is provided by ac coupling
the input video signals. The ADV7481, in combination with an
external resistor divider, provides a common-mode input range
of 4 V, enabling the removal of large signal common-mode
transients present on the video lines.
The ADV7481 MHL 2.1 capable receiver supports a maximum
pixel clock frequency of 75 MHz, allowing resolutions up to
720p/1080i at 60 Hz in 24-bit mode. The ADV7481 features a
link control bus (CBUS) that handles the link layer, translation
layer, CBUS electrical discovery, and display data channel
(DDC) commands. The implementation of the MHL sideband
channel (MSC) commands by the system processor can be
handled either by the I2C bus, or via a dedicated serial
peripheral interface (SPI) bus. A dedicated interrupt pin
(INTRQ3) is available to indicate that events related to CBUS
have occurred.
The automatic gain control (AGC) and clamp restore circuitry
allow an input video signal up to 1.0 V p-p at the analog video
input pins of the ADV7481. Alternatively, the AGC and clamp
restore circuitry can be bypassed for manual settings.
The SDP of the ADV7481 is capable of decoding a large
selection of analog baseband video signals in composite,
S-Video, and component formats. The SDP supports world-
wide NTSC, PAL, and SECAM standards.
The ADV7481 features an 8-bit digital input/output port,
supporting input and output video resolutions up to 720p/1080i
in both the 8-bit interleaved 4:2:2 SDR and DDR modes.
The ADV7481 also features an enable pin (VBUS_EN) to
dynamically enable or disable the output of a voltage regulator,
which provides a 5 V voltage bus (VBUS) signal to the MHL
source.
To enable glueless interfacing of these video input sources to the
latest generation of infotainment system on chips (SoCs), the
ADV7481 features two MIPI® CSI-2 transmitters. The four-lane
transmitter provides four data lanes, two data lanes, and one
data lane muxing options, and can be used to output video from
the HDMI receiver, the MHL receiver, the SDP, and the digital
input port. The single-lane transmitter can be used to output
video from the SDP only.
The ADV7481 HDMI capable receiver supports a maximum
pixel clock frequency of 162 MHz, allowing HDTV formats up
to 1080p, and display resolutions up to UXGA (1600 × 1200 at
60 Hz). The device integrates a consumer electronics control
(CEC) controller that supports the capability discovery and
control (CDC) feature. The HDMI input port has dedicated 5 V
detect and Hot Plug™ assert pins.
The ADV7481 offers a flexible audio output port for audio data
extracted from the MHL or HDMI streams. The HDMI/MHL
receiver has advanced audio functionality, such as a mute
controller that prevents audible extraneous noise in the audio
output. Additionally, the ADV7481 can be set to output time
division multiplexing (TDM) serial audio, which allows the
transmission of eight multiplexed serial audio channels on a
single audio output interface port.
The HDMI/MHL receiver includes an adaptive transition
minimized differential signaling (TMDS) equalizer that ensures
robust operation of the interface with long cables.
The ADV7481 single receiver port is capable of accepting both
HDMI and MHL electrical signals. Automatic detection
between HDMI and MHL is achieved by using cable impedance
detection through the CD_SENSE pin.
The ADV7481 is programmed via a 2-wire, serial, bidirectional
port (I2C compatible).
The ADV7481 contains a component processor (CP) that
processes the video signals from the HDMI/MHL receiver. It
provides features such as contrast, brightness, and saturation
adjustments, as well as free run and timing adjustment controls
for HS/VS/DE timing.
Fabricated in an advanced CMOS process, the ADV7481 is
available in a 9 mm × 9 mm, RoHS-compliant, 100-ball
CSP_BGA package and is specified over the −40°C to +85°C
temperature range.
The ADV7481 analog front end (AFE) comprises a single high
speed, 10-bit analog-to-digital converter (ADC) that digitizes
the analog video signal before applying it to the SDP.
The ADV7481 is offered in automotive and industrial versions.
The eight analog video inputs can accept single-ended, pseudo
differential, and fully differential composite video signals, as
Rev. 0 | Page 3 of 22
ADV7481
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
SCLK
2
ADV7481
SDATA
ALSB
I C SLAVE/
CONTROL
RESET
GENERAL
INTERRUPTS
CONTROLLER
INTRQ1
INTRQ2
SPI_MISO
SPI_MOSI
SPI_SCLK
SPI
SLAVE
SPI_CS
CBUS
INTRQ3
INTERRUPTS
CONTROLLER
CBUS
CONTROLLER
PACKET/
INFOFRAME
MEMORY
MHL LINK
DISCOVERY
BLOCK
VBUS_EN
CD_SENSE
I2S_MCLK
I2S_LRCLK
I2S_SCLK
I2S_SDATA
AUDIO
PROCESSOR
PACKET
PROCESSOR
HDCP
KEYS
HDCP
ENGINE
AUDIO OUTPUT
FORMATTER
5V DETECT AND
HPD PIN
CONTROLLER
HPD/CBUS
RX_5V/VBUS
CEC
CONTROLLER
CEC
EDID/
REPEATER
DDC_SDA
DDC_SCL/
CD_PULLUP
CONTROLLER
RXCP/RXCN
PLL
8-BIT
MIPI CSI-2
TRANSMITTER A
RX0P/RX0N
RX1P/RX1N
RX2P/RX2N
TO
COMPONENT
PROCESSOR
(CP)
COLOR
HDMI/MHL
PROCESSOR
6-BIT
DITHER
BLOCK
SAMPLER
EQUALIZER
SPACE
CLKAP/CLKAN
DA0P/DA0N
DA1P/DA1N
DA2P/DA2N
DA3P/DA3N
CONVERSION
LLC
P0
P1
P2
P3
P4
P5
P6
P7
CSI-2 Tx
D-PHY Tx
8-BIT
DIGITAL
INPUT/
OUTPUT
PORT
CLOCK PROCESSING BLOCK
ADLLT PROCESSING
XTALP
XTALN
PLL
MIPI CSI-2
TRANSMITTER B
AFE
STANDARD DEFINITION
PROCESSOR (SDP)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AA
10-BIT ADC
FILTER
ACE
2D COMB
AA
FILTER
CLKBP/CLKBN
DB0P/DB0N
+
SHA
CSI-2 Tx
D-PHY Tx
DOWN-
DITHER
VBI SLICER
ADC
AA
FILTER
–
COLOR DEMOD
AA
FILTER
STANDARD
AUTODETECTION
DIAG1
DIAG2
DIAG3
DIAG4
VREFP
VREFN
REFERENCE
DIAGNOSTICS
Figure 2.
Rev. 0 | Page 4 of 22
Data Sheet
ADV7481
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max
Unit
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS1
N
INL
DNL
10
Bits
LSB
LSB
CVBS mode
CVBS mode
2
0.6
SCLK, SDATA, RESET, ALSB, SPI_CS, SPI_SCLK,
SPI_MOSI, LLC, and P0 to P7
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance2
CRYSTAL INPUT
VIH
VIL
IIN
DVDDIO = 3.14 V to 3.46 V
DVDDIO = 3.14 V to 3.46 V
2
V
V
µA
pF
0.8
+10
10
−10
CIN
Input High Voltage
Input Low Voltage
DIGITAL OUTPUTS1
VIH
VIL
XTALP
XTALP
1.2
V
V
0.4
LLC, P0 to P7, I2S_MCLK, I2S_SCLK, I2S_LRCLK,
I2S_SDATA, SPI_MISO, SDATA, INTRQ1 to INTRQ3
(when configured to drive when active), and
VBUS_EN
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance2
VOH
VOL
ILEAK
COUT
DVDDIO = 3.14 V to 3.46 V and ISOURCE = 0.4 mA
DVDDIO = 3.14 V to 3.46 V and ISINK = 3.2 mA
2.4
V
V
µA
pF
0.4
20
10
POWER REQUIREMENTS
Digital Power Supply
HDMI/MHL Terminator Supply
HDMI/MHL Comparator Supply
PLL Power Supply
MIPI Transmitters Power Supply
Digital Input/Output Power Supply1
Analog Power Supply
DVDD
TVDD
CVDD
PVDD
MVDD
DVDDIO
AVDD
1.71 1.8
3.14 3.3
1.71 1.8
1.71 1.8
1.71 1.8
3.14 3.3
1.71 1.8
1.89
3.46
1.89
1.89
1.89
3.46
1.89
V
V
V
V
V
V
V
3.3 V operation
CURRENT CONSUMPTION1, 2, 3, 4
Digital Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
IDVDD
279
mA
mA
mA
74.5
74.7
Y/C Input
71.3
72.8
68.1
93.5
32.5
mA
mA
mA
mA
mA
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
Rev. 0 | Page 5 of 22
ADV7481
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max
Unit
mA
mA
mA
HDMI/MHL Terminator Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
ITVDD
40
0.7
0.7
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
HDMI/MHL Comparator Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
PLL Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
MIPI Transmitters Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
Digital Input/Output Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
0.7
0.7
35
24.4
0.7
mA
mA
mA
mA
mA
mA
mA
mA
ICVDD
IPVDD
IMVDD
IDVDDIO
IAVDD
92
52
77
78
93
0.1
0.1
0.1
0.1
63.9
55.9
0.1
mA
mA
mA
mA
mA
mA
mA
mA
37.5
37.5
37.7
37.7
29.2
29.3
27.9
mA
mA
mA
mA
mA
mA
mA
mA
23.3
23.3
23.2
23.2
45.7
38.5
38.1
mA
mA
mA
mA
mA
mA
mA
mA
0.2
0.2
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
Analog Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
0.2
0.2
3.6
0.6
0.2
mA
mA
mA
mA
mA
mA
mA
mA
51.9
70
Y/C Input
63
mA
mA
mA
mA
mA
YPbPr Input
HDMI Input
MHL Input
78.5
0.1
0.1
0.1
8-Bit Digital Input
Rev. 0 | Page 6 of 22
Data Sheet
ADV7481
Parameter
POWER-DOWN CURRENTS2, 5
Symbol
Test Conditions/Comments
Min Typ
Max
Unit
Digital Supply
IDVDD_PD
ITVDD_PD
ICVDD_PD
IPVDD_PD
IMVDD_PD
IDVDDIO_PD
IAVDD_PD
0.2
0.4
0.1
0.1
0.1
0.2
0.1
4
mA
mA
mA
mA
mA
mA
mA
mW
HDMI/MHL Terminator Supply
HDMI/MHL Comparator Supply
PLL Supply
MIPI Transmitters Supply
Digital Input/Output Supply
Analog Supply
Total Power Dissipation in Power-Down
Mode
1 The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.
2 Guaranteed by lab characterization.
3 Typical current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V), Philips test pattern, and at room temperature.
4 Maximum current consumption values are recorded with maximum rated voltage supply levels (including DVDDIO = 3.46 V), MoireX video pattern for analog inputs,
pseudorandom test pattern for digital inputs, and at worst-case temperature.
5 Typical power-down current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V) at room temperature.
ANALOG VIDEO SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 2.
Parameter
NONLINEAR SPECIFICATIONS1, 2
Symbol
Test Conditions/Comments
Min Typ
Max
Unit
Differential Phase
Differential Gain
Luma Nonlinearity
DP
DG
LNL
CVBS input, modulated five-step
CVBS input, modulated five-step
CVBS input, five-step
0.9
0.5
2.0
Degrees
%
%
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted2
SNR
Luma ramp
57.1
58
60
dB
dB
dB
dB
Luma flat field
Analog Front-End Crosstalk3
Common-Mode Rejection Ratio2, 4
LOCK TIME SPECIFICATIONS
Horizontal Lock Range3
Vertical Lock Range3
Subcarrier Lock Range3
Color Lock-In Time3
Synchronization Depth Range3
Color Burst Range3
Fast Switch Speed2, 5
CMRR
73
−5
40
1.3
60
20
5
+5
70
%
Hz
kHz
Lines
%
%
ms
fSC
200
200
100
1 These specifications apply to all CVBS input types, as well as to single-ended and differential CVBS inputs.
2 Guaranteed by lab characterization.
3 Guaranteed by design.
4 The CMRR of this circuit design is critically dependent on the external resistor matching its inputs. This measurement was performed with 0.1% tolerant resistors, a
common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
5 The time it takes the ADV7481 to switch from one analog input (single ended or differential) to another, for example, switching from AIN1 to AIN2.
Rev. 0 | Page 7 of 22
ADV7481
Data Sheet
MIPI VIDEO OUTPUT SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
The ADV7481 MIPI CSI-2 transmitters conform to the MIPI D-PHY Version 1.00.00 specification by characterization. The clock lane of
the ADV7481 remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some
measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements
were performed with the ADV7481 operating with a nominal 1 Gbps output data rate.
Table 3.
Parameter
UNIT INTERVAL1
Symbol
Min
Typ
Max
Unit
UI
1
12.5
ns
DATA LANE LP Tx DC SPECIFICATIONS2
Thevenin Output
High Level
Low Level
VOH
VOL
1.1
−50
1.2
0
1.3
+50
V
mV
CLOCK LANE LP Tx DC SPECIFICATIONS2
Thevenin Output
High Level
Low Level
VOH
VOL
1.1
−50
1.2
0
1.3
+50
V
mV
DATA LANE HS Tx SIGNALING REQUIREMENTS
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
CLOCK LANE HS Tx SIGNALING REQUIREMENTS
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
HS Tx CLOCK TO DATA LANE TIMING REQUIREMENTS
Data to Clock Skew
|V1|
140
200
270
10
360
250
mV p-p
mV
mV
150
140
200
200
mV
|V2|
270
10
360
250
mV p-p
mV
mV
150
200
mV
0.35 × UI
0.65 × UI
ns
1 Guaranteed by design.
2 These measurements were performed with CLOAD = 50 pF.
ANALOG SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Large Clamp
Required by design
0.1
µF
Source Current
Sink Current
0.32
0.32
mA
mA
Fine Clamp
Source Current
Sink Current
7
7
µA
µA
Rev. 0 | Page 8 of 22
Data Sheet
ADV7481
TIMING SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 5.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
CLOCK AND CRYSTAL
Nominal Frequency1
28.63636
MHz
ppm
MHz
MHz
MHz
MHz
MHz
Frequency Stability1
50
Input LLC Clock Frequency Range2, 3
Output LLC Clock Frequency Range2, 3
SPI_SCLK Frequency3
I2S_SCLK Frequency3
I2S_MCLK Frequency3
I2C PORT
DVDDIO = 3.14 V to 3.46 V
DVDDIO = 3.14 V to 3.46 V
13.5
13.5
148.5
148.5
10
12.288
24.576
SCLK Frequency
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time (Stop Condition)
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
SPI PORT
Slave Mode
SPI_CS Falling Edge to SPI_SCLK
Active Edge
t9
SPI_SCLK active edge (rising or falling 35
edge) depends on the values of CPHA
and CPOL
SPI_SCLK active edge (rising or falling 35
edge) depends on the values of CPHA
and CPOL
ns
ns
ns
SPI_SCLK Active Edge to SPI_CS
Rising Edge
t10
SPI_CS Pulse Width
SPI_SCLK High Time3
t11
t12
50
45
55
55
% duty
cycle
% duty
cycle
SPI_SCLK Low Time3
t12
45
SPI_MOSI Setup Time
SPI_MOSI Hold Time
SPI_SCLK Falling Edge to SPI_MISO t15
Start of Data Invalid3
SPI_SCLK Falling Edge to SPI_MISO
End of Data Invalid3
t13
t14
SPI Mode 0, SPI Mode 3
SPI Mode 0, SPI Mode 3
SPI Mode 0, SPI Mode 3
0
35
ns
ns
ns
50
50
t16
SPI Mode 0, SPI Mode 3
ns
SPI_MOSI Setup Time
SPI_MOSI Hold Time
SPI_SCLK Rising Edge to SPI_MISO
Start of Data Invalid
SPI_SCLK Rising Edge to SPI_MISO
End of Data Invalid
t17
t18
t19
SPI Mode 1, SPI Mode 2
SPI Mode 1, SPI Mode 2
SPI Mode 1, SPI Mode 2
0
35
ns
ns
ns
35
35
t20
SPI Mode 1, SPI Mode 2
ns
RESET FEATURE
RESET Pulse Width1
5
ms
Rev. 0 | Page 9 of 22
ADV7481
Data Sheet
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
8-BIT DIGITAL INPUT PORT2
LLC High Time3
DVDDIO = 3.14 V to 3.46 V
t21
45
45
55
55
% duty
cycle
% duty
cycle
LLC Low Time3
SDR and DDR Modes Setup Time
SDR and DDR Modes Hold Time
DDR Mode Setup Time
DDR Mode Hold Time
8-BIT DIGITAL OUTPUT PORT2
t22
t23
t24
t25
Data latched on rising edge
Data latched on rising edge
Data latched on falling edge
Data latched on falling edge
DVDDIO = 3.14 V to 3.46 V
1
1
1
1
ns
ns
ns
ns
LLC High Time
t26
40
60
60
% duty
cycle
% duty
cycle
LLC Low Time
40
SDR Modes Setup Time4, 5
SDR Modes Hold Time4, 5
DDR Modes Setup Time4, 5
DDR Modes Hold Time4, 5
DDR Mode Setup Time4, 5
DDR Modes Hold Time4, 5
t36
t37
t27
t28
t29
t30
At P0 to P7 output pin, data latched
on rising edge
At P0 to P7 output pin, data latched
on rising edge
At P0 to P7 output pin, data latched
on rising edge
At P0 to P7 output pin, data latched
on rising edge
At P0 to P7 output pin, data latched
on falling edge
At P0 to P7 output pin, data latched
on falling edge
1.98
2.50
1.66
3.52
1.71
3.17
ns
ns
ns
ns
ns
ns
I2S PORT, MASTER MODE
I2S_SCLK High Time
t31
45
45
55
55
10
10
5
% duty
cycle
% duty
cycle
ns
ns
ns
ns
I2S_SCLK Low Time
I2S_LRCLK Data Transition Time
t32
t33
t34
t35
End of valid data to I2S_SCLK falling
edge
I2S_SCLK falling edge to start of valid
data
End of valid data to I2S_SCLK falling
edge
I2S_SCLK falling edge to start of valid
data
I2S_SDATA Data Transition Time
5
1 Required by design.
2 The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.
3 Guaranteed by design.
4 These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000.
5 Guaranteed by lab characterization.
Rev. 0 | Page 10 of 22
Data Sheet
ADV7481
Timing Diagrams
t5
t3
t3
SDATA
SCLK
t1
t6
t4
t7
t8
t2
Figure 3. I2C Timing
t11
t
9
t10
SPI
MODE
SPI_CS
CPOL CPHA
SPI_SCLK
SPI_SCLK
0
0
1
1
0
1
0
1
0
1
2
3
SPI_SCLK
SPI_SCLK
W/R
0
DEVICE ADDRESS
SUB ADDRESS
DATA IN 0
DATA IN 1
SPI_MO SI
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
7
7
6
5
4
3
2
1
1
1
0
0
0
DUMMY BYTE
DATA OUT 0
DELAY MODE 1
SPI_MI SO
6
6
5
4
3
2
DATA OUT 0
DATA OUT 1
DELAY MODE 0
SPI_MI SO
7
6
5
4
3
2
1
0
5
4
3
2
Figure 4. Detailed SPI Slave Timing Diagram
t12
t16
t13
t14
t15
SPI_SCLK
SPI_MOSI
SPI_CS
SPI_MISO
Figure 5. SPI Slave Mode Timing (SPI Mode 0 and SPI Mode 3)
t20
t17
t12
t19
t18
SPI_SCLK
SPI_MO SI
SPI_CS
SPI_MISO
Figure 6. SPI Slave Mode Timing (SPI Mode 1 and SPI Mode 2)
Rev. 0 | Page 11 of 22
ADV7481
Data Sheet
t21
t22
t23
LLC
P7 TO P0
Figure 7. 8-Bit Digital Pixel Video Input, SDR Video Data Timing
t21
LLC
t24
t23
t25
t22
P7 TO P0
Figure 8. 8-Bit Digital Pixel Video Input, DDR Video Data Timing
t26
LLC
t36
t37
P7 TO P0
Figure 9. 8-Bit Digital Pixel Video Output, SDR Video Data Timing
t26
LLC
t27
t29
t28
t30
P7 TO P0
Figure 10. 8-Bit Digital Pixel Video Output, DDR Video Data Timing
t31
I2S_SCLK
t32
I2S_LRCLK
t33
t34
I2S_SDATA
LEFT JUSTIFIED
MODE
MSB
MSB – 1
MSB
t35
t34
I2S_SDATA
I S MODE
2
MSB – 1
t35
t34
I2S_SDATA
RIGHT JUSTIFIED
MODE
MSB
LSB
t35
Figure 11. I2S Timing
Rev. 0 | Page 12 of 22
Data Sheet
ADV7481
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
Rating
To reduce power consumption when using the ADV7481, turn
off unused sections of the device.
TVDD, DVDDIO to GND
4 V
AVDD, PVDD, MVDD, DVDD, CVDD 2.2 V
to GND
Due to printed circuit board (PCB) metal variation, and,
therefore, variation in PCB heat conductivity, the value of θJA
may differ for various PCBs.
CVDD to DVDD
−0.3 V to +0.3 V
MVDD to DVDD
PVDD to DVDD
AVDD to DVDD
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
The most efficient measurement solution is achieved using the
package surface temperature to estimate the die temperature.
This eliminates the variance associated with the θJA value.
Digital Inputs Voltage to GND
GND − 0.3 V to DVDDIO +
0.3 V
Do not exceed the maximum junction temperature (TJ max) of
125°C. The following equation calculates the junction
temperature (TJ) using the measured package surface
temperature and applies only when no heat sink is used on the
device under test (DUT):
Digital Outputs Voltage to GND
GND − 0.3 V to DVDDIO +
0.3 V
Analog Inputs to GND
XTALN and XTALP to GND
HDMI/MHL Digital Inputs Voltage
to GND
−0.3 V to AVDD + 0.3 V
−0.3 V to PVDD + 0.3 V
−0.3 V to CVDD + 0.3 V
TJ = TS + (ΨJT ×WTOTAL
where:
TS is the package surface temperature (°C).
JT = 0.81°C/W for the 100-ball CSP_BGA (based on 2s2p test
board defined by JEDEC standards.
TOTAL = (PVDD × IPVDD) + (TVDD × ITVDD) − PUpStream
(CVDD × ICVDD) + (AVDD × IAVDD) + (DVDD × IDVDD) +
(DVDDIO × IDVDDIO) + (MVDD × IMVDD
)
5 V Tolerant Inputs Voltage to
GND1, 2
Maximum Junction Temperature
(TJ max)
−0.3 V to +5.5 V
125°C
Ψ
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
−65°C to +150°C
260°C
W
+
)
1 The following inputs are 3.3 V inputs but are 5 V tolerant:
DDC_SCL/CD_PULLUP, DDC_SDA, HPD/CBUS, RX_5V/VBUS, CD_SENSE and
CEC.
where PUpStream is the quantity of TVDD power consumed on the
upstream HDMI or MHL transmitter. PUpStream can be estimated
to be around 110 mW for a nominal HDMI transmitter. PUpStream
can be estimated to be around 42.82 mW for a nominal MHL
transmitter.
2 The following inputs are 1.8 V inputs but are 5 V tolerant: DIAG1, DIAG2,
DIAG3, and DIAG4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 13 of 22
ADV7481
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
DDC_
SCL/CD_
PULLUP
I2S_
SDATA
VBUS_
EN
GND
GND
RX2P
RX1P
RX0P
RXCP
GND
A
B
C
D
E
F
A
B
C
D
E
F
I2S_
DDC_
SDA
HPD/
MVDD
CVDD
RX2N
RX1N
RX0N
TVDD
GND
GND
GND
GND
RXCN
CEC
GND
AIN8
AIN6
AIN4
AIN2
DIAG2
GND
SCLK
CBUS
I2S_
LRCLK
I2S_
MCLK
CD_
SENSE
RX_5V/
VBUS
CLKAN CLKAP
AIN7
AIN5
AIN3
AIN1
DA0N
DA1N
DA2N
DA3N
DA0P INTRQ3 DVDD
GND
GND
GND
GND
GND
DIAG4
DIAG3
VREFN
DA1P INTRQ2
DA2P INTRQ1
GND
GND
AVDD
GND
DA3P
TEST
DVDD
GND
VREFP DIAG1
G
H
J
G
H
J
SPI_
MOSI
PVDD
SPI_CS RESET
DB0N
DB0P DVDDIO
P1
P2
P4
P5
SPI_
SCLK
MISO
CLKBN CLKBP MVDD
P7
XTALN XTALP
SPI_
K
GND
1
MVDD
2
P0
3
P3
4
P6
5
LLC
6
SDATA
SCLK
ALSB
9
GND
10
K
7
8
Figure 12. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
Ground.
I2S Audio Output.
Ground.
HDMI Digital Input Channel 2.
HDMI Digital Input Channel 1.
A1
A2
A3
A4
GND
I2S_SDATA
GND
RX2P
RX1P
Ground
Output
Ground
HDMI
A5
HDMI
A6
A7
RX0P
RXCP
HDMI/MHL
HDMI
HDMI Digital Input Channel 0 or MHL Positive Input.
HDMI Input Clock.
A8
A9
DDC_SCL/CD_PULLUP
VBUS_EN
HDMI/MHL
MHL
HDCP Slave Serial Clock or MHL Cable Detect Pull-Up.
Enable Control Signal for Voltage Regulator Providing a 5 V VBUS
Supply.
A10
B1
B2
GND
Ground
Power
Output
Power
Ground.
MIPI Supply Voltage (1.8 V).
Audio Serial Clock.
HDMI/MHL Comparator Supply Voltage (1.8 V). This is the supply
for the HDMI/MHL sensitive analog circuitry. Blocks on this supply
include the TMDS PLL and the equalizers.
MVDD
I2S_SCLK
CVDD
B3
B4
B5
B6
B7
B8
B9
B10
RX2N
RX1N
RX0N
RXCN
DDC_SDA
HPD/CBUS
GND
HDMI
HDMI
HDMI/MHL
HDMI
HDMI
HDMI Digital Input Channel 2 Complement.
HDMI Digital Input Channel 1 Complement.
HDMI Digital Input Channel 0 Complement or MHL Negative Input.
HDMI Input Clock Complement.
HDCP Slave Serial Data.
HDMI Hot Plug Assert or MHL CBUS.
Ground.
HDMI/MHL
Ground
Rev. 0 | Page 14 of 22
Data Sheet
ADV7481
Pin No.
C1
C2
C3
C4
C5
C6
C7
Mnemonic
Type
Description
CLKAN
CLKAP
I2S_LRCLK
I2S_MCLK
CD_SENSE
TVDD
Output
Output
Output
Output
MHL
MIPI Transmitter A Negative Output Clock.
MIPI Transmitter A Positive Output Clock.
Audio Left/Right Clock.
Audio Master Clock Output.
MHL Cable Detection Sense Input.
HDMI/MHL Terminator Supply Voltage (3.3 V).
CEC Channel.
Power
HDMI
CEC
C8
RX_5V/VBUS
HDMI/MHL
HDMI 5 V Detect or MHL VBUS. A large pull-down resistor (100 kΩ,
typical) to ground must be connected to this pin.
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1
F2
F3
F4
F5
F6
F7
F8
AIN7
AIN8
Input
Input
Analog Video Input Channel.
Analog Video Input Channel.
MIPI Transmitter A Negative Data Output.
MIPI Transmitter A Positive Data Output.
Interrupt Request Output.
Digital Supply Voltage (1.8 V).
Ground.
DA0N
DA0P
INTRQ3
DVDD
GND
GND
GND
DIAG4
AIN5
AIN6
DA1N
DA1P
INTRQ2
GND
GND
GND
AVDD
DIAG3
AIN3
Output
Output
Output
Power
Ground
Ground
Ground
Input
Ground.
Ground.
Analog Video Diagnostic Input. This input is 5 V tolerant.
Analog Video Input Channel.
Analog Video Input Channel.
MIPI Transmitter A Negative Data Output.
MIPI Transmitter A Positive Data Output.
Interrupt Request Output.
Ground.
Input
Input
Output
Output
Output
Ground
Ground
Ground
Power
Input
Input
Input
Output
Output
Output
Ground
Ground
Ground
Ground
Output
Input
Ground.
Ground.
Analog Supply Voltage (1.8 V).
Analog Video Diagnostic Input. This input is 5 V tolerant.
Analog Video Input Channel.
Analog Video Input Channel.
MIPI Transmitter A Negative Data Output.
MIPI Transmitter A Positive Data Output.
Interrupt Request Output.
Ground.
AIN4
DA2N
DA2P
INTRQ1
GND
GND
GND
GND
VREFN
AIN1
Ground.
Ground.
Ground.
Internal Voltage Reference Output.
Analog Video Input Channel.
Analog Video Input Channel.
MIPI Transmitter A Negative Data Output.
MIPI Transmitter A Positive Data Output.
Do Not Connect. This pin must be left unconnected.
Digital Supply Voltage (1.8 V).
Ground.
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
AIN2
Input
DA3N
DA3P
TEST
DVDD
GND
GND
GND
VREFP
DIAG1
DIAG2
Output
Output
Miscellaneous
Power
Ground
Ground
Ground
Output
Input
Ground.
Ground.
Internal Voltage Reference Output.
Analog Video Diagnostic Input. This input is 5 V tolerant.
Analog Video Diagnostic Input. This input is 5 V tolerant.
Input
Rev. 0 | Page 15 of 22
ADV7481
Data Sheet
Pin No.
H1
H2
H3
H4
H5
H6
H7
Mnemonic
DB0N
DB0P
DVDDIO
P1
P4
SPI_MOSI
SPI_CS
RESET
Type
Description
Output
Output
Power
Input/Output
Input/Output
Input
MIPI Transmitter B Negative Data Output.
MIPI Transmitter B Positive Data Output.
Digital Input/Output Supply Voltage (3.3 V).
Video Pixel Input/Output Port.
Video Pixel Input/Output Port.
SPI Slave Data Input.
Input
SPI Slave Chip Select Input.
H8
Input
System Reset Input, Active Low. A minimum low reset pulse of
5 ms is required to reset the chip.
H9
H10
J1
J2
J3
J4
J5
J6
J7
PVDD
GND
CLKBN
CLKBP
MVDD
P2
P5
P7
SPI_MISO
SCLK
XTALN
Power
Ground
Output
Output
PLL Supply Voltage (1.8 V).
Ground.
MIPI Transmitter B Negative Output Clock.
MIPI Transmitter B Positive Output Clock.
MIPI Supply Voltage (1.8 V).
Video Pixel Input/Output Port.
Video Pixel Input/Output Port.
Video Pixel Input/Output Port.
SPI Slave Data Output.
Power
Input/Output
Input/Output
Input/Output
Output
Input
Output
J8
J9
I2C Port Serial Clock Input.
Crystal Output. This pin must be connected to the 28.63636 MHz
crystal or not connected if an external 1.8 V, 28.63636 MHz clock
oscillator is used. In crystal mode, the crystal must be a
fundamental crystal.
J10
XTALP
Input
Crystal Input or External Clock Input. This pin must be connected
to the 28.63636 MHz crystal or connected to an external 1.8 V,
28.63636 MHz clock oscillator if a clock oscillator is used. In crystal
mode, the crystal must be a fundamental crystal.
K1
K2
K3
K4
K5
K6
K7
K8
K9
GND
MVDD
P0
P3
P6
Ground
Power
Ground.
MIPI Supply Voltage (1.8 V).
Video Pixel Input/Output Port.
Video Pixel Input/Output Port.
Video Pixel Input/Output Port.
Line Locked Clock. Input/output clock for the pixel data.
SPI Slave Clock Input.
Input/Output
Input/Output
Input/Output
Input/Output
Input
LLC
SPI_SCLK
SDATA
ALSB
Input/Output
Input
I2C Port Serial Data Input/Output.
Main I2C Address Selection Pin. This pin selects the main I2C
address (IO Map I2C address) for the device. When ALSB is set to
Logic 0, the IO Map I2C write address is 0xE0; when ALSB is set to
Logic 1, the IO Map I2C write address is 0xE2.
K10
GND
Ground
Ground.
Rev. 0 | Page 16 of 22
Data Sheet
ADV7481
POWER SUPPLY RECOMMENDATION
POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
Adhere to the absolute maximum ratings at all times during
power-up (see Table 6). The power-up sequence for the
ADV7481 is as follows:
The ADV7481 power supplies can be deasserted simultaneously
as long as a higher rated supply (for example, DVDDIO) does not
fall to a voltage level less than a lower rated supply (for example,
D
VDD), and the absolute maximum ratings specifications are
RESET
1. Assert
(pull the pin low).
followed.
2. Power up the 3.3 V supplies (DVDDIO and TVDD). These
supplies must be powered up simultaneously.
3. Power up the 1.8 V supplies (DVDD, CVDD, PVDD, MVDD, and
AVDD). These supplies must be powered up simultaneously.
RESET
4.
can be deasserted (pulled high) 5 ms after all
supplies are fully powered up.
RESET
5. After all power supplies and the
pin are powered up
and stable, wait an additional 5 ms before initiating I2C
communication with the ADV7481.
3.3V
RESET
0V
3.3V
3.3V SUPPLIES
0V
1.8V
1.8V SUPPLIES
0V
RESET > 5ms
Figure 13. Supply Power-Up Sequence
Rev. 0 | Page 17 of 22
ADV7481
Data Sheet
THEORY OF OPERATION
The implementation of the MSC commands by the system
COMBINED HDMI/MHL RECEIVER
processor can be handled either through the I2C bus, or via a
dedicated SPI bus. A dedicated interrupt pin (INTRQ3) is
available to indicate that events related to the CBUS have
occurred.
The ADV7481 features a combined HDMI/MHL receiver. This
single receiver port is capable of accepting both HDMI and
MHL electrical signals. Automatic detection between HDMI
and MHL is achieved by using cable impedance detection
through the CD_SENSE pin.
The main MHL receiver features include
Both MHL and HDMI interfaces of the ADV7481 allow
authentication of a video receiver, decryption of encoded data at
the receiver, and renewability of that authentication during
transmission, as specified by the HDCP 1.4 protocol.
•
Support for a pixel clock up to 75 MHz in 24-bit mode,
allowing support for video formats up to 720p/1080i and
display resolutions up to XGA in either RGB, YCbCr 4:4:4,
or YCbCr 4:2:2 formats.
•
Integrated fully adaptive equalizer for cable lengths up to
2 meters.
HDCP 1.4 support
Internal HDCP keys.
HDCP repeater support, up to 25 key selection vectors
(KSVs) supported.
Dual extended display identification data (EDID) support is
provided via an on-chip 512-byte EDID RAM. The EDID RAM
must be programmed at power-up. It can be configured as two
256-byte EDIDs for dual mode operation (one 256-byte EDID
for the HDMI receiver, and one 256-byte EDID for the MHL
receiver), or as a single 512-byte EDID for single mode operation.
•
•
•
•
•
•
•
Pulse code modulation (PCM) audio packet support.
Support for 8-channel TDM output data up to 48 kHz.
Repeater support.
Internal EDID RAM (512-byte for single mode, and
256-byte for dual mode operation).
The ADV7481 has a synchronization regeneration block used to
regenerate the data enable (DE) signal based on the measurement
of the video format being displayed and to filter the horizontal
and vertical synchronization signals to prevent glitches.
The combined HDMI/MHL receiver also supports TMDS error
reduction coding, 4-bit (TERC4) error detection, used for the
detection of corrupted HDMI or MHL packets.
•
Scratchpad register support with a size of 64 bytes.
HDMI RECEIVER
MHL RECEIVER
The HDMI receiver supports video formats ranging from 480i
to 1080p, and display resolutions from VGA (640 × 480 at
60 Hz) to UXGA (1600 × 1200 at 60 Hz).
The MHL receiver supports video formats ranging from 480i to
720p/1080i, and display resolutions from VGA (640 × 480 at
60 Hz) to XGA (1024 × 768 at 60 Hz).
The HDMI receiver allows programmable equalization of the
HDMI data signals. This equalization compensates for the high
frequency losses inherent in HDMI and DVI cabling, especially
at longer lengths and higher frequencies. The receiver is capable
of equalizing for cable lengths up to 30 meters to achieve robust
receiver performance.
The MHL receiver allows programmable equalization of the
MHL data signals. This equalization compensates for the high
frequency losses inherent in MHL cabling, especially at longer
lengths and higher frequencies. The receiver is capable of
equalizing for cable lengths of up to 2 meters to achieve robust
receiver performance.
The main HDMI receiver features include
The MHL receiver includes the following pins:
•
162.0 MHz (UXGA at 24 BPP) maximum TMDS clock
frequency.
Integrated fully adaptive equalizer for cable lengths up to
30 meters.
HDCP 1.4 support.
Internal HDCP keys.
HDCP repeater support, up to 25 key selection vectors
(KSVs) supported.
PCM audio packet support.
Support for 8-channel TDM output data up to 48 kHz.
Repeater support.
Internal EDID RAM (512-byte for single mode, and
256-byte for dual mode operation).
Hot Plug assert output pin (HPD/CBUS).
CEC controller.
•
RX0N and RX0P. In MHL mode, this differential pair
receives the data transmitted as a differential signal and the
clock transmitted on the common mode.
HPD/CBUS. In MHL mode, this pin is used for CBUS
communication.
VBUS_EN. This pin provides an enable signal for an
external source providing 5 V of power to the MHL source
on VBUS.
•
•
•
•
•
•
•
•
•
•
•
•
RX_5V/VBUS. In MHL mode, this pin is an input
monitoring the VBUS signal provided by an external
source enabled by VBUS_EN.
CD_SENSE. This pin detects whether the signals provided
to the HDMI/MHL receiver are HDMI signals or MHL
signals. A high level indicates MHL, and a low level
indicates HDMI.
•
•
Rev. 0 | Page 18 of 22
Data Sheet
ADV7481
ANALOG INPUT
CVBS_P
100nF
COMPONENT PROCESSOR
1.3kΩ
AINx
The ADV7481 has one any-to-any 3 × 3 CSC matrix. The CSC
block is located in the processing path before the CP section.
CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions.
Many other standards of color space can be implemented using
the color space converter.
430Ω
75Ω
430Ω
100nF
ANALOG INPUT
CVBS_N
1.3kΩ
AINy
CP features include
Figure 15. Typical Pseudo Differential Input Resistor Divider Network
•
Support for all video modes supported by the HDMI/MHL
receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p,
and display resolutions from VGA (640 × 480 at 60 Hz) to
UXGA (1600 × 1200 at 60 Hz).
ANALOG INPUT
100nF
1.3kΩ
AINx
CVBS_P
430Ω
150Ω
•
•
•
Manual adjustments including gain (contrast), offset
(brightness), hue, and saturation.
Free run output mode that provides stable timing when no
video input is present.
430Ω
100nF
ANALOG INPUT
CVBS_N
1.3kΩ
AINy
Timing adjustments controls for HS/VS/DE timing.
Figure 16. Typical Fully Differential Input Resistor Divider Network
The ADC features three clocking rates that allow 4×
oversampling per channel for CVBS mode, Y/C mode, and
YPbPr mode.
ANALOG FRONT END
The ADV7481 AFE comprises a single high speed, 10-bit ADC
that digitizes the analog video signal before applying it to the
SDP. The AFE uses differential channels to the ADC to ensure
high performance in mixed-signal applications and to enable
differential CVBS to be connected directly to the ADV7481.
The fully differential AFE of the ADV7481 provides inherent
small and large signal noise rejection, improved electro-
magnetic interference (EMI) protection, and the ability to
absorb ground bounce. Support is provided for both true
differential and pseudo differential signals.
Up to eight analog inputs can be connected to the AFE. The
front end also includes an 8-channel input mux that enables
different configurations of single-ended CVBS (up to eight),
pseudo differential or fully differential CVBS (up to four), Y/C
(up to four), and YPbPr (up to two) analog inputs.
The main AFE features include
•
•
•
A single 172 MHz, 10-bit ADC that enables true 8-bit
video decoding.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is within the range of the
ADC. Figure 14 shows a typical voltage divider network for
single-ended inputs, Figure 15 shows a typical voltage divider
network for pseudo differential inputs, and Figure 16 shows a
typical voltage divider network for fully differential inputs. The
choice of the resistor divider shown in Figure 16 provides a
common-mode range of up to 4 V in fully differential CVBS
input mode. Fine clamping of the video signal is performed
downstream by digital fine clamping within the ADV7481.
8-channel analog input mux that enables multiple source
connections without the requirement of an external mux.
A current clamp control loop that ensures that any dc
offsets are removed from the video signal entering the SDP.
Diagnostic capability on all differential inputs.
Support for 4 V common-mode input range.
Support for analog input signals up to 1 V p-p.
Support for single-ended, pseudo differential, and fully
differential inputs.
•
•
•
•
SHORT TO BATTERY DIAGNOSTICS
In differential mode, the ADV7481 is protected against STB
events by ac coupling capacitors (see Figure 15 and Figure 16).
The input network resistors are sized to reduce the current flow
during an STB event, thus preventing damage to the resistors.
Note that the input network resistors and the ac coupling
capacitors must be chosen with ratings guaranteeing they are
able to withstand the high voltage of STB events.
ANALOG
INPUT
100nF
AIN
24Ω
51Ω
Figure 14. Typical Single-Ended Input Voltage Divider Network
The four diagnostic inputs of the ADV7481 provide diagnostic
capability for all differential inputs. The ADV7481 can detect an
STB event on either the positive or the negative composite input
and trigger an interrupt. The 75 Ω (pseudo differential) or 150 Ω
(fully differential) parallel termination resistor enables one
Rev. 0 | Page 19 of 22
ADV7481
Data Sheet
DIAGx pin to sense an STB event on either input, because there
is a minimal voltage drop across the resistor.
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the
video standard and signal quality without requiring user
intervention. Video user controls such as brightness, contrast,
saturation, and hue are also available with the ADV7481.
R4
DIAGx
R5
ANALOG INPUT
100nF
1.3kΩ
The ADV7481 implements the patented Adaptive Digital Line
Length Tracking (ADLLT™) algorithm to track varying video
line lengths from sources such as a VCR. ADLLT enables the
ADV7481 to track and decode poor quality video sources such
as VCRs and noisy sources from tuner outputs, VCD players,
and camcorders. The ADV7481 contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
CVBS_P
AINx
430Ω
75Ω
OR
150Ω
430Ω
100nF
ANALOG INPUT
CVBS_N
1.3kΩ
AINy
Figure 17. Diagnostic Connection for Differential Inputs
The ACE of the ADV7481 offers improved visual detail using
an algorithm that automatically varies contrast levels to enhance
picture detail. ACE allows the contrast of an image to increase
depending on the content of the picture. Typically, this allows
bright areas to be made brighter and dark areas to be made
darker. However, the ADV7481 ACE feature also allows the
contrast within dark areas to increase without significantly
affecting the bright areas of the picture. This feature is
particularly useful in automotive applications, where it is
important to discern objects in shaded areas.
Resistors R4 and R5 divide down the voltage at the input
connector to protect the DIAGx pin from an STB event. The
DIAGx pin circuitry compares this voltage to a programmable
reference voltage, known as the diagnostic slice level. When the
diagnostic slice level is exceeded, an STB event has occurred.
R4 and R5 are sized to allow the use of low cost, small footprint
resistors that are tolerant of STB events.
Use the following equation to find the STB voltage for a selected
diagnostic slice level.
R5 + R4
R5
Downdithering converts the output of the ADV7481 from an 8-
bit to a 6-bit output, enabling ease of design for standard LCD
panels.
VSTB_TRIGGER
=
×DIAGNOSTIC_SLICE_LEVEL
where:
STB_TRIGGER is the minimum voltage required at the input
connector to trigger the STB interrupt on the ADV7481.
DIAGNOSTIC_SLICE_LEVEL is the programmable reference
voltage.
V
The SDP can process a variety of VBI data services, such as
closed captioning (CCAP), wide screen signaling (WSS), and
copy generation management system (CGMS).
The ADV7481 is fully Rovi® (Macrovision®) compliant;
detection circuitry enables Type I, Type II, and Type III
protection levels to be identified and reported to the user. The
decoder is also fully robust to all Macrovision signal inputs.
For example, with a diagnostic slice level programmed to
1.125 V, an R4 value of 9.1 kΩ, and an R5 value of 1 kΩ, the
minimum voltage required at the input connector to trigger the
STB interrupt is approximately 11.4 V.
8-BIT DIGITAL INPUT/OUTPUT PORT
When the DIAGx pin voltage exceeds the diagnostic slice level
voltage, a hardware interrupt is triggered and indicated by one
of the interrupt pins. A readback register specifies the input on
which the STB event occurred.
The ADV7481 features an 8-bit digital bidirectional port. The
following formats are supported both as input and output ports:
•
8-bit interleaved 4:2:2 SDR input/output with embedded
timing codes
STANDARD DEFINITION PROCESSOR
•
8-bit interleaved 4:2:2 DDR input/output with embedded
timing codes
The ADV7481 is capable of decoding a large selection of
baseband video signals in composite (both single-ended and
differential), S-Video, and component formats. The video
standards supported by the video processor include
The maximum input and output video resolution supported is
720p/1080i in both SDR and DDR modes.
Video received on the 8-bit digital input port can be routed to
the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit
digital output port can be routed from either the SD core or the
CP core.
• PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,
PAL Nc, and PAL 60
• NTSC J, NTSC M, and NTSC 4.43
• SECAM B, SECAM D, SECAM G, SECAM K, and SECAM L
The ADV7481 can automatically detect the video standard and
process it accordingly.
The ADV7481 has a five-line adaptive 2D comb filter that
provides superior chrominance and luminance separation when
Rev. 0 | Page 20 of 22
Data Sheet
ADV7481
The main features of the four-lane MIPI transmitter
(Transmitter A) include
AUDIO PROCESSING
The ADV7481 features an audio processor that handles the
audio extracted from the MHL or HDMI stream by the
HDMI/MHL receiver. It contains an audio mute controller that
can detect a variety of conditions that may result in audible
extraneous noise in the audio output. On detection of these
conditions, a 2-channel linear PCM audio signal can be ramped
down to a mute state to prevent audio clicks or pops.
•
•
Support for 8-bit and 10-bit YCbCr 4:2:2 video modes.
Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4
(RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes.
Support for video formats ranging from 480i to 1080p, and
display resolutions from VGA to UXGA (certain
restrictions apply to the muxing option, video mode, and
video format that can be selected).
•
The audio is output on a single flexible serial digital audio
output port supporting I2S-compatible, left justified, and right
justified audio output modes in master mode only. TDM is also
supported, allowing up to eight audio channels with a sample
rate up to 48 kHz to be transmitted over the single serial digital
audio interface.
•
Data lanes and clock lane remapping to ease PCB layout.
The single lane transmitter consists of a single differential data
lane (DB0N and DB0P) and a differential clock lane (CLKBN
and CLKBP). It transmits video received on the AFE (processed
through the SDP).
MIPI CSI-2 TRANSMITTERS
The main features of the single lane MIPI transmitter
(Transmitter B) include
The ADV7481 features two MIPI CSI-2 transmitters: a four-
lane transmitter (Transmitter A) and a single lane transmitter
(Transmitter B).
•
•
Support for 8-bit YCbCr 4:2:2 video mode.
Support for 480i and 576i video formats.
The four-lane transmitter consists of four differential data lanes
(DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N, and
DA3P), and a differential clock lane (CLKAN and CLKAP). It
supports four data lanes, two data lanes, and one data lane
muxing options, and can be used to transmit video received on
either the HDMI/MHL receiver (processed through the CP),
the 8-bit digital input port, or the AFE (processed through the
SDP).
INTERRUPTS
The ADV7481 features three interrupt request pins. INTRQ1
and INTRQ2 can be programmed to trigger interrupts based on
various selectable events related to the HDMI/MHL receiver
(video and audio related), the SDP, and the CP. INTRQ3 is
dedicated to events related to the MHL CBUS.
Rev. 0 | Page 21 of 22
ADV7481
Data Sheet
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
A1 BALL
CORNER
A1 BALL
CORNER
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
7.20
BSC SQ
0.80
BSC
G
H
J
K
0.90
REF
BOTTOM VIEW
DETAIL A
TOP VIEW
0.975
0.910
0.845
0.26
REF
DETAIL A
*
0.383
0.343
0.303
1.400
1.253
1.173
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-275-DDAB-1
WITH THE EXCEPTION TO PACKAGE HEIGHT
Figure 18. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-100-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3
Temperature Range
Package Description
Package Option
BC-100-4
BC-100-4
ADV7481WBBCZ
ADV7481WBBCZ-RL
−40°C to +85°C
−40°C to +85°C
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 This device is programmed with internal HDCP keys. Customer must have HDCP adopter status (consult Digital Protection, LLC, for licensing requirements) to
purchase any components with internal HDCP keys
AUTOMOTIVE PRODUCTS
The ADV7481W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12046-0-6/14(0)
Rev. 0 | Page 22 of 22
相关型号：
©2020 ICPDF网 联系我们和版权申明