ADXL356CEZ_技术文档

Low Noise, Low Drift, Low Power,

3-Axis MEMS Accelerometers

Data Sheet

ADXL356/ADXL357

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

V

1P8DIG

1P8ANA

RANGE

Hermetic package offers optimal long-term stability

0 g offset vs. temperature (all axes): 0.75 mg/°C maximum

Ultralow noise spectral density (all axes): 75 μg/√Hz

Low power, V_SUPPLY(LDO regulator enabled)

ADXL356 in measurement mode: 150 μA

ADXL357 in measurement mode: 200 μA

ADXL356/ADXL357 in standby mode: 21 μA

ADXL356 has user adjustable analog output bandwidth

ADXL357 digital output features

LDO

POWER

V

LDO

SUPPLY

MANAGEMENT

Y

X

OUT

X

ANALOG

FILTER

Z

ST1

Y

Z

OUT

3-AXIS

SENSOR

ST2

OUT

CONTROL

LOGIC

STBY

TEMP

SENSOR

TEMP

ADXL356

V

DDIO

Digital SPI and limited I²C interfaces supported

20-bit ADC

V

SS

SSIO

Figure 1. ADXL356

Data interpolation routine for synchronous sampling

Programmable high- and low-pass digital filters

Integrated temperature sensor

V

DDIO

1P8ANA

1P8DIG

POWER

MANAGEMENT

LDO

X

V

LDO

ADXL357

SUPPLY

Voltage range options

Y

ADC

INT1

INT2

DRDY

CONTROL

LOGIC

V

_SUPPLYwith internal regulators: 2.25 V to 3.6 V

_1P8ANA, V_1P8DIGwith internal LDO regulator bypassed: 1.8 V

typical 10%

DIGITAL

ADC

ANALOG

FILTER

Z

FILTER

3-AXIS

SENSOR

CS/SCL

SCLK/V

SSIO

TEMP

SENSOR

SERIAL

I/O

FIFO

ADC

MOSI/SDA

MISO/ASEL

Operating temperature range: −40°C to +125°C

14-terminal, 6 mm × 5.6 mm × 2.2 mm, LCC package

V

SSIO

SS

Figure 2. ADXL357

APPLICATIONS

Inertial measurement units (IMUs)/attitude and heading

reference systems (AHRSs)

Platform stabilization systems

Structural health monitoring

Seismic imaging

Tilt sensing

Robotics

Condition monitoring

GENERAL DESCRIPTION

The analog output ADXL356 and the digital output ADXL357

are low noise density, low 0 g offset drift, low power, 3-axis

accelerometers with selectable measurement ranges. The

ADXL356B supports the ±±0 g and ±ꢀ0 g ranges, the ADXL356C

supports the ±±0 g and ±ꢁ0 g ranges, and the ADXL357 supports

the ±±0 g, ±ꢀ0 g, and ±ꢁ0 g ranges.

The low drift, low noise, and low power ADXL357 enables

accurate tilt measurement in an environment with high

vibration. The low noise of the ADXL356 over higher

frequencies is ideal for condition-based monitoring and other

vibration sensing applications.

The ADXL357 multifunction pin names may be referenced only

by their relevant function for either the serial peripheral

interface (SPI) or limited I^ꢀC interface.

The ADXL356/ADXL357 offer industry leading noise, minimal

offset drift over temperature, and long-term stability, enabling

precision applications with minimal calibration.

¹Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621.

Rev. A

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ADXL356/ADXL357

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. ±

DRDY Pin.................................................................................... ꢀ9

FIFO_FULL................................................................................. ꢀ9

FIFO_OVR.................................................................................. ꢀ9

Activity......................................................................................... ꢀ9

External Synchronization and Interpolation.......................... ꢀ9

ADXL357 Register Map................................................................. 3ꢀ

Register Definitions........................................................................ 33

Analog Devices ID Register...................................................... 33

Analog Devices MEMS ID Register......................................... 33

Device ID Register ..................................................................... 33

Product Revision ID Register ................................................... 33

Status Register............................................................................. 33

FIFO Entries Register ................................................................ 3ꢁ

Temperature Data Registers...................................................... 3ꢁ

X-Axis Data Registers................................................................ 3ꢁ

Y-Axis Data Registers................................................................ 35

Z-Axis Data Registers ................................................................ 35

FIFO Access Register................................................................. 36

X-Axis Offset Trim Registers.................................................... 36

Y-Axis Offset Trim Registers.................................................... 36

Z-Axis Offset Trim Registers.................................................... 37

Activity Enable Register ............................................................ 37

Activity Threshold Registers..................................................... 37

Activity Count Register ............................................................. 37

Filter Settings Register............................................................... 38

FIFO Samples Register .............................................................. 38

Interrupt Pin (INTx) Function Map Register......................... 38

Data Synchronization ................................................................ 39

I^ꢀC Speed, Interrupt Polarity, and Range Register................. 39

Power Control Register ............................................................. 39

Self Test Register......................................................................... ꢁ0

Reset Register.............................................................................. ꢁ0

PCB Footprint Pattern ................................................................... ꢁ±

Outline Dimensions....................................................................... ꢁꢀ

Ordering Guide .......................................................................... ꢁꢀ

Applications....................................................................................... ±

Functional Block Diagrams............................................................. ±

General Description......................................................................... ±

Revision History ............................................................................... 3

Specifications..................................................................................... ꢁ

Analog Output for the ADXL356............................................... ꢁ

Digital Output for the ADXL357 ............................................... 5

SPI Digital Interface Characteristics for the ADXL357 .......... 7

I^ꢀC Digital Interface Characteristics for the ADXL357........... 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

Recommended Soldering Profile ............................................... 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions ......................... ±0

Typical Performance Characteristics ........................................... ±ꢀ

Root Allan Variance (RAV) ADXL357 Characteristics......... ꢀ0

Theory of Operation ...................................................................... ꢀ±

Applications Information .............................................................. ꢀꢀ

Analog Output ............................................................................ ꢀꢀ

Digital Output............................................................................. ꢀꢀ

Axes of Acceleration Sensitivity ............................................... ꢀ3

Power Sequencing ...................................................................... ꢀ3

Power Supply Description......................................................... ꢀ3

Overrange Protection................................................................. ꢀ3

Self Test ........................................................................................ ꢀ3

Filter ............................................................................................. ꢀꢁ

Serial Communications ................................................................. ꢀ6

SPI Protocol................................................................................. ꢀ6

SPI Bus Sharing........................................................................... ꢀ6

I^ꢀC Protocol................................................................................. ꢀ7

Reading Acceleration or Temperature Data from the Interface

....................................................................................................... ꢀ7

FIFO ................................................................................................. ꢀ8

Interrupts ......................................................................................... ꢀ9

DATA_RDY................................................................................. ꢀ9

Rev. A | Page 2 of 42

Data Sheet

ADXL356/ADXL357

REVISION HISTORY

6/2020—Rev. 0 to Rev. A

Changes to DRDY Pin Section, FIFO_OVR Section, Activity

Section, NVM_BUSY Section, and External Synchronization

and Interpolation Section ..............................................................ꢀ9

Changed EXT_SYNC = 00—No External Sync or Interpolation

Section to EXT_SYNC = 00, EXT_CLK = 0—No External

Synchronization or Interpolation Section; EXT_SYNC = ±0—

External Sync with Interpolation Section to EXT_SYNC = ±0,

EXT_CLK = 0—External Synchronization with Interpolation

Section; and EXT_SYNC = 0±—External Sync and External

Clock, No Interpolation Filter Section to EXT_SYNC = 0±,

EXT_CLK = ±—External Synchronization and External Clock,

No Interpolation Filter Section .....................................................30

Changes to EXT_SYNC = 00, EXT_CLK = 0—No External

Synchronization or Interpolation Section, EXT_SYNC = ±0,

EXT_CLK = 0—External Synchronization with Interpolation

Section, Table ±3, and EXT_SYNC = 0±, EXT_CLK = ±—

External Synchronization and External Clock, No Interpolation

Filter Section....................................................................................30

Added EXT_SYNC = ±0, EXT_CLK = ±—External

Changes to Features Section, Applications Section, and General

Description Section...........................................................................±

Changes to Table ± ............................................................................ꢁ

Changes to Table ꢀ ............................................................................5

Changes to Input Current Parameter, Table 3...............................7

Changes to Acceleration (Any Axis, 0.± ms) Parameter, Table 5;

Thermal Resistance Section; and Table 6.......................................9

Moved Recommended Soldering Profile Section, Figure 5, and

Table 7.................................................................................................9

Changes to Table 8 ..........................................................................±0

Changes to Typical Performance Section and Figure 8 to

Figure ±3...........................................................................................±ꢀ

Changes to Figure ±ꢁ to Figure ±9 ................................................±3

Changes to Figure ꢀ3 to Figure ꢀ5 ................................................±ꢁ

Changes to Figure 3ꢀ to Figure 37 ................................................±6

Changes to Figure ꢁꢁ Caption, Figure ꢁ7 Caption, and Figure ꢁ8

Caption .............................................................................................±8

Changes to Figure 50 Caption, Figure 5ꢀ Caption, and

Figure 53...........................................................................................±9

Changes to Theory of Operation Section ....................................ꢀ±

Changes to Power Sequencing Section, V_±P8ANASection, and

Overrange Protection Section .......................................................ꢀ3

Changes to Self Test Section, Filter Section, Figure 6ꢀ, and

Figure 63...........................................................................................ꢀꢁ

Changes to Table ±± ........................................................................ꢀ5

Changes to Serial Communications Section and Figure 6ꢁ ......ꢀ6

Added SPI Bus Sharing Section and Figure 65; Renumbered

Sequentially......................................................................................ꢀ6

Changes to I^ꢀC Protocol Section ...................................................ꢀ7

Changes to FIFO Section ...............................................................ꢀ8

Synchronization and External Clock, with Interpolation Filter

Section ..............................................................................................30

Changes to Table ±ꢁ ........................................................................3±

Changes to Figure 7ꢁ, Figure 75 Caption, and Figure 76 ..........3±

Changes to Temperature Data Registers Section, Table ꢀ3,

Table ꢀꢁ, and Table ꢀ5.....................................................................3ꢁ

Changes to Table ꢀ7, Table ꢀ8, Table 30 and Table 3±................35

Change to Table ꢁꢀ Title.................................................................37

Changes to Table ꢁꢁ ........................................................................38

Changes to Reset Register Section................................................ꢁ0

Changes to Figure 77 ......................................................................ꢁ±

Changes to Ordering Guide...........................................................ꢁꢀ

2/2017—Revision 0: Initial Version

Rev. A | Page 3 of 42

ADXL356/ADXL357

Data Sheet

SPECIFICATIONS

ANALOG OUTPUT FOR THE ADXL356

T_A= ꢀ5°C, V_SUPPLY= 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = ± g, and full-scale range = ±±0 g, unless

otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Each axis

Min

Typ

Max

Unit

SENSOR INPUT

Output Full-Scale Range (FSR)

ADXL356B supports two ranges

ADXL356C supports two ranges

10, 20

10, 40

5.5

0.1

1.3

1

g

Resonant Frequency¹

Nonlinearity

kHz

% FSR

%

10 g

40 g

Cross Axis Sensitivity

SENSITIVITY

Ratiometric to V_1P8ANA

Sensitivity at X_OUT, Y_OUT, Z_OUT

10 g

20 g

40 g

73.6

36.8

18.4

80

40

20

0.01

0.1

0.2

86.4

43.2

21.6

mV/g

%/°C

%

Sensitivity Change Due to Temperature T_A= −40°C to +125°C

Repeatability²

X-axis and y-axis

Z-axis

%

0 g OFFSET

0 g Output for X_OUT, Y_OUT, Z_OUT

Each axis, 10 g

Referred to V_1P8ANA/2

T_A= −40°C to +125°C

−375

−0.75

125

0.2

+375

+0.75

mg

mg/°C

0 g Offset vs. Temperature (X-Axis, Y-Axis,

and Z-Axis)³

Repeatability²

X-axis and y-axis

Z-axis

Offset due to 7.5 g rms vibration, 10 g

range, in a 1 g orientation

4.25

5

<0.1

mg

g

Vibration Rectification Error (VRE)⁴

NOISE

Spectral Density⁵

X-Axis, Y-Axis, and Z-Axis

10 g

40 g

10 g

75

110

μg/√Hz

Velocity Random Walk

X-Axis and Y-Axis

Z-Axis

38.2

26.5

2.4

mm/sec/Hr

kHz

BANDWIDTH

SELF TEST

−3 dB, overall transfer function⁶

Output Change

Z-Axis

10 g range⁷

0.5

1.25

2.5

3.0

g

POWER SUPPLY

Voltage Range

8

V_SUPPLY

2.25

V_1P8DIG2.5

1.62

3.6

1.98

V

V_DDIO

V_1P8ANA, V_1P8DIG

Internal low dropout (LDO) regulator

bypassed, V_SUPPLY= 0 V

1.8

Current

Measurement Mode

V_SUPPLY

V_1P8ANA

LDO regulator enabled

LDO regulator disabled

150

138

12

μA

V_1P8DIG

Rev. A | Page 4 of 42

Data Sheet

ADXL356/ADXL357

Parameter

Standby Mode

V_SUPPLY

V_1P8ANA

V_1P8DIG

Turn On Time⁹

Test Conditions/Comments

Min

Typ

Max

Unit

LDO regulator enabled

LDO regulator disabled

10 g range

Power-off to standby

X_OUT, Y_OUT, Z_OUT, and TEMP pins

No load

21

7

10

<10

μA

ms

OUTPUT AMPLIFIER

Swing

Output Series Resistance

TEMPERATURE SENSOR

Output at 25°C

0.03

−40

V_1P8ANA− 0.03

V

kΩ

32

967

3.0

mV

mV/°C

Scale Factor

TEMPERATURE

Operating Temperature Range

+125

°C

¹The resonant frequency is a sensor characteristic.

²Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life (HTOL) (T_A= 150°C, V_SUPPLY= 3.6 V, and 1000 hours),

temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows

the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: 4.25 mg × √(2.5 years/10 years) = 2.125 mg.

³The temperature change is −40°C to +25°C, or +25°C to +125°C.

⁴The VRE measurement is the shift in dc offset while the device is subject to 7.5 g rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is

configured for the 10 g range and an output data rate of 4 kHz. The VRE scales with the range setting.

⁵Based on characterization.

⁶Overall transfer function includes the sensor mechanical response and all other filters on the signal chain.

7

10 g indicates a test condition. The self test result converted to the acceleration value is independent of the selected range.

⁸When V_1P8ANAand V_1P8DIGare generated internally, V_SUPPLYis valid. To disable the LDO regulator and drive V_1P8ANAand V_1P8DIGexternally, connect V_SUPPLYto V_SS

.

⁹Standby to measurement mode. This specification is valid when the output is within 5 mg of the final value.

DIGITAL OUTPUT FOR THE ADXL357

T_A= ꢀ5°C, V_SUPPLY= 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = ± g, full-scale range = ±±0 g, and output

data rate (ODR) = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced only by their relevant function.

Table 2.

Parameter

Test Conditions/Comments

Each axis

Min

Typ

Max

Unit

SENSOR INPUT

Output Full Scale Range (FSR)

User selectable, supports three ranges

10,

20,

40

g

Nonlinearity

10 g

40 g

0.1

1.3

1

% FSR

%

Cross Axis Sensitivity

SENSITIVITY¹

Each axis

X-Axis, Y-Axis, and Z-Axis Sensitivity

10 g

20 g

40 g

47,104 51,200 55,296 LSB/g

23,552 25,600 27,648 LSB/g

11,776 12,800 13,824 LSB/g

X-Axis, Y-Axis, and Z-Axis Scale Factor

10 g

20 g

40 g

19.5

39

78

0.01

0.1

0.2

μg/LSB

%/°C

%

Sensitivity Change due to Temperature

Repeatability²

T_A= −40°C to +125°C

X-axis and y-axis

Z-axis

%

0 g OFFSET

Each axis, 10 g

X-Axis, Y-Axis, and Z-Axis 0 g Output

−375

−0.75

125

0.20

+375

+0.75

mg

mg/°C

0 g Offset vs. Temperature (X-Axis, Y-Axis, and

T_A= −40°C to +125°C

Z-Axis)³

Rev. A | Page 5 of 42

ADXL356/ADXL357

Data Sheet

Parameter

Repeatability²

Test Conditions/Comments

X-axis and y-axis

Z-axis

Offset due to 7.5 g rms vibration, 10 g

range, in a 1 g orientation

Min

Typ

4.25

5

Max

Unit

mg

g

VRE⁴

<0.1

NOISE

Spectral Density⁵

X-Axis, Y-Axis, and Z-Axis

10 g

40 g

10 g

75

90

μg/√Hz

Velocity Random Walk

X-Axis and Y-Axis

Z-Axis

38.2

26.5

mm/sec/Hr

BANDWIDTH AND OUTPUT DATA RATE

Analog-to-Digital Converter (ADC) Resolution

Low-Pass Filter Passband Frequency

High-Pass Filter Passband Frequency When

Enabled (Disabled by Default)

20

Bits

Hz

User programmable, Register 0x28

User programmable, Register 0x28 for 4 kHz

ODR

0.977

0.0095

1000

10

SELF TEST

Output Change

Z-Axis

10 g range⁶

0.5

1.25

3.0

g

POWER SUPPLY

Voltage Range

V_SUPPLYOperating⁷

V_DDIO

V_1P8ANAand V_1P8DIG

Current

2.25

V_1P8DIG

1.62

2.5

1.8

3.6

1.98

V

Internal LDO regulator bypassed, V_SUPPLY= 0 V

Measurement Mode

V_SUPPLY

V_1P8ANA

LDO regulator enabled

LDO regulator disabled

200

160

35.5

μA

V_1P8DIG

Standby Mode

V_SUPPLY

V_1P8ANA

V_1P8DIG

Turn On Time⁸

LDO regulator enabled

LDO regulator disabled

10 g range

21

7

10

<10

μA

ms

Power-off to standby

TEMPERATURE SENSOR

Output at 25°C

1885

LSB

Scale Factor

−9.05

LSB/°C

TEMPERATURE

Operating Temperature Range

−40

+125

°C

¹Characterized but not 100% tested.

²Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (T_A= 150°C, V_SUPPLY= 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and

1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain

offset repeatability of the x-axis for 2.5 years, use the following equation: 4.25 mg × √(2.5 years/10 years) = 2.125 mg.

³The temperature change is −40°C to +25°C or +25°C to +125°C.

⁴The VRE measurement is the shift in dc offset while the device is subject to 7.5 g rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the 10 g range

and an output data rate of 4 kHz. The VRE scales with the range setting.

⁵Based on characterization.

6

10 g indicates a test condition. The self test result converted to the acceleration value is independent of the selected range.

⁷When V_1P8ANAand V_1P8DIGare generated internally, V_SUPPLYis valid. To disable the LDO regulator and drive V_1P8ANAand V_1P8DIGexternally, connect V_SUPPLYto V_SS

.

⁸Standby to measurement mode. This specification is valid when the output is within 1 mg of final value.

Rev. A | Page 6 of 42

Data Sheet

ADXL356/ADXL357

SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357

Note that multifunction pin names may be referenced by their relevant function only.

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

DC INPUT LEVELS

Input Voltage

Low Level

High Level

Input Current

Low Level

V_IL

V_IH

0.3 × V_DDIO

V

0.7 × V_DDIO

−0.2

I_IL

I_IH

Input voltage (V_IN) = 0 V

V_IN= V_DDIO

μA

High Level

0.2

DC OUTPUT LEVELS

Output Voltage

Low Level

High Level

Output Current

Low Level

V_OL

V_OH

I_OL= I_{OL, MIN}

I_OH= I_{OH, MAX}

0.2 × V_DDIO

V

0.8 × V_DDIO

−10

I_OL

I_OH

V_OL= V_{OL, MAX}

V_OH= V_{OH, MIN}

mA

High Level

4

AC INPUT LEVELS

SCLK Frequency

SCLK High Time

SCLK Low Time

CS Setup Time

CS Hold Time

0.1

40

20

40

20

10

MHz

ns

t_HIGH

t_LOW

t_CSS

ns

t_CSH

t_CSD

t_SCLKS

t_SU

ns

CS Disable Time

Rising SCLK Setup Time

MOSI Setup Time

MOSI Hold Time

AC OUTPUT LEVELS

Propagation Delay

Enable MISO Time

Disable MISO Time

ns

t_HD

t_P

t_EN

t_DIS

Load capacitance (C_LOAD) = 30 pF

30

20

ns

30

t_CSD

CS

t_CSH

t_SCLKS

t_CSS

t_HIGH

t_LOW

SCLK

t_SU

t_HD

MOSI

MISO

t_DIS

t_P

t_EN

Figure 3. SPI Interface Timing Diagram

Rev. A | Page 7 of 42

ADXL356/ADXL357

Data Sheet

I²C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357

Note that multifunction pin names may be referenced only by their relevant function.

Table 4.

Test Conditions/

Symbol Comments

I2C_HS = 0 (Fast Mode)

Typ Max

I2C_HS = 1 (High Speed Mode)

Parameter

Min

Typ

Max

Unit

DC INPUT LEVELS

Input Voltage

Low Level

High Level

Hysteresis of Schmitt

Triggered Inputs

V_IL

V_IH

V_HYS

0.3 × V_DDIO

V

0.7 × V_DDIO

0.05 × V_DDIO

0.7 × V_DDIO

0.1 × V_DDIO

Input Current

I_IL

0.1 × V_DDIO< V_IN<

0.9 × V_DDIO

−10

+10

μA

DC OUTPUT LEVELS

Output Voltage

Low Level

I_OL= 3 mA

V_DDIO> 2 V

V_DDIO≤ 2 V

V_OL1

V_OL2

0.4

0.2 × V_DDIO

0.4

0.2 × V_DDIO

V

Output Current

Low Level

I_OL

V_OL= 0.4 V

V_OL= 0.6 V

20

6

20

6

mA

AC INPUT LEVELS

SCL Frequency

SCL High Time

0

1

0

60

160

10

3.4

MHz

ns

t_HIGH

t_LOW

t_SUSTA

t_HDSTA

t_SUDAT

t_HDDAT

t_SUSTO

t_BUF

t_RCL

t_FCL

t_RDA

t_FDA

260

500

260

50

0

260

500

SCL Low Time

Start Setup Time

Start Hold Time

SDA Setup Time

SDA Hold Time

Stop Setup Time

Bus Free Time

SCL Input Rise Time

SCL Input Fall Time

SDA Input Rise Time

SDA Input Fall Time

Width of Spikes to

Suppress

0

160

120

50

80

160

10

t_SP

Not shown in Figure 4

C_LOAD= 500 pF

AC OUTPUT LEVELS

Propagation Delay

Data

Acknowledge

Output Fall Time

t_VDDAT

t_VDACK

t_F

97

450

120

27

135

ns

Not shown in Figure 4

20 ×

(V_DDIO/5.5)

t_FDA

t_RDA

t_BUF

SDA

SCL

t_SUSTA

t_HDSTA

t_VDDAT

t_VDACK

t_SUSTO

t_SUSTA

t_SUDAT

t_HDDAT

t_LOW

t_FCL

t_RCL

t_HIGH

t_VDDAT

Figure 4. I²C Interface Timing Diagram

Rev. A | Page 8 of 42

Data Sheet

ADXL356/ADXL357

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Rating

RECOMMENDED SOLDERING PROFILE

Acceleration (Any Axis, 0.1 ms)

Unpowered

Powered

Figure 5 and Table 7 provide details about the recommended

soldering profile.

10,000 g

5.4 V

CRITICAL ZONE

t_P

T

TO T

L

P

V_SUPPLY, V_DDIO

T

P

RAMP-UP

V_1P8ANA, V_1P8DIGConfigured as Inputs

ADXL356

1.98 V

T

L

t_L

T

SMAX

Digital Inputs (RANGE, ST1, ST2, STBY)

Analog Outputs (X_OUT, Y_OUT, Z_OUT, TEMP)

ADXL357

−0.3 V to V_DDIO+ 0.3 V

−0.3 V to V_1P8ANA+ 0.3 V

T

SMIN

t_S

Digital Pins (CS/SCL, SCLK/V_SSIO

,

−0.3 V to V_DDIO+ 0.3 V

RAMP-DOWN

PREHEAT

MOSI/SDA, MISO/ASEL, INT1, INT2,

DRDY)

Operating Temperature Range

Storage Temperature Range

t_{25°C TO PEAK}

−40°C to +125°C

−55°C to +150°C

TIME

Figure 5. Recommended Soldering Profile

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 7. Recommended Soldering Profile

Condition

Profile Feature

Sn63/Pb37

Pb-Free

Average Ramp Rate from Liquid 3°C/sec

3°C/sec

maximum

Temperature (T_L) to Peak

Temperature (T_P)

maximum

Preheat

Minimum Temperature

(T_SMIN

Maximum Temperature

(T_SMAX

100°C

150°C

200°C

THERMAL RESISTANCE

)

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

)

Time from T_SMINto T_SMAX(t_S)

60 sec to

120 sec

60 sec to

180 sec

3°C/sec

maximum

217°C

θ_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. ψ_JBis

the junction to board thermal resistance.

T_SMAXto T_LRamp-Up Rate

3°C/sec

maximum

Liquid Temperature (T_L)

183°C

Table 6. Thermal Resistance

Package Type

E-14-1¹

Time Maintained Above T_L(t_L)

60 sec to

150 sec

240°C +

0°C/−5°C

10 sec to

30 sec

60 sec to

150 sec

260°C +

0°C/−5°C

20 sec to

40 sec

θ_JA

ψ_JB

Unit

Peak Temperature (T_P)

Time of Actual T_P− 5°C (t_P)

Ramp-Down Rate

42

17.6

°C/W

¹Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board with four thermal vias. See JEDEC JESD51.

6°C/sec

maximum

Time from 25°C to Peak

Temperature (t_{25°C TO PEAK}

6 minutes

maximum

8 minutes

maximum

)

ESD CAUTION

Rev. A | Page 9 of 42

ADXL356/ADXL357

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Y

RANGE

ST1

1

2

11 V

10 V

SUPPLY

1P8ANA

ADXL356

TOP VIEW

ST2

3

4

9

8

V

(Not to Scale)

SS

X

TEMP

1P8DIG

Z

Figure 6. ADXL356 Pin Configuration

Table 8. ADXL356 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RANGE

Range Selection Pin. Set this pin to ground to select the 10 g range, or set this pin to V_DDIOto select the

20 g or 40 g range. This pin is model dependent (see the Ordering Guide section).

2

3

ST1

ST2

Self Test Pin 1. This pin enables self test mode. This pin must be forced low when not in self test mode.

Self Test Pin 2. This pin activates electromechanical self test actuation. This pin must be forced low when not

in self test mode.

4

5

6

7

TEMP

V_DDIO

V_SSIO

Temperature Sensor Output.

Digital Interface Supply Voltage.

Digital Ground.

Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin

to V_DDIOto enter measurement mode.

STBY

8

V_1P8DIG

Digital Supply. This pin requires a decoupling capacitor. If V_SUPPLYconnects to V_SS, supply the voltage to this

pin externally.

9

V_SS

Analog Ground.

10

V_1P8ANA

Analog Supply. This pin requires a decoupling capacitor. If V_SUPPLYconnects to V_SS, supply the voltage to this

pin externally.

11

V_SUPPLY

Supply Voltage. When V_SUPPLYequals 2.25 V to 3.6 V, V_SUPPLYenables the internal LDO regulators to generate

V

_1P8DIGand V_1P8ANA. For V_SUPPLY= V_SS, V_1P8DIGand V_1P8ANAare externally supplied.

12

13

14

X_OUT

Y_OUT

Z_OUT

X-Axis Output.

Y-Axis Output.

Z-Axis Output.

Rev. A | Page 10 of 42

Data Sheet

ADXL356/ADXL357

Y

CS/SCL

SCLK/V

1

2

11 V

10 V

SUPPLY

SSIO

1P8ANA

ADXL357

TOP VIEW

MOSI/SDA 3

MISO/ASEL 4

9

8

V

(Not to Scale)

SS

X

1P8DIG

Z

Figure 7. ADXL357 Pin Configuration (SPI/I²C)

Table 9. ADXL357 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CS/SCL

Chip Select for SPI (CS).

Serial Communications Clock for I²C (SCL).

2

3

4

SCLK/V_SSIO

MOSI/SDA

MISO/ASEL

Serial Communications Clock for SPI (SCLK).

I²C Mode Enable (V_SSIO). Connect this pin to Pin 6 (V_SSIO) to enable I²C mode.

Master Output, Slave Input for SPI (MOSI).

Serial Data for I²C (SDA).

Master Input, Slave Output for SPI (MISO).

Alternate I²C Address Select for I²C (ASEL).

Digital Interface Supply Voltage.

Digital Ground.

Reserved. This pin can be connected to ground or left open.

5

6

7

8

V_DDIO

V_SSIO

RESERVED

V_1P8DIG

Digital Supply. This pin requires a decoupling capacitor. If V_SUPPLYconnects to V_SS, supply the voltage to this

pin externally.

9

V_SS

Analog Ground.

10

V_1P8ANA

Analog Supply. This pin requires a decoupling capacitor. If V_SUPPLYconnects to V_SS, supply the voltage to this

pin externally.

11

V_SUPPLY

Supply Voltage. When V_SUPPLYequals 2.25 V to 3.6 V, V_SUPPLYenables the internal LDO regulators to generate

V

_1P8DIGand V_1P8ANA. For V_SUPPLY= V_SS, V_1P8DIGand V_1P8ANAare externally supplied.

12

13

14

INT1

INT2

DRDY

Interrupt Pin 1.

Interrupt Pin 2.

Data Ready Pin.

Rev. A | Page 11 of 42

ADXL356/ADXL357

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

All figures include data for multiple devices and multiple lots, and they were taken in the ±±0 g range and T_A= ꢀ5°C, unless otherwise noted. For

Figure 5ꢀ, the ODR is derived from a master clock, with a frequency of ±.0ꢀꢁ MHz and ±±.ꢁ4 device to device variation (similar to ODR device

to device variation). For a given device, however, clock frequency variation over the temperature range (−ꢁ0°C to +±ꢀ5°C) is no more than

±±.ꢀ4, guaranteed by design.

10

1

0.1

10

0.01

100

FREQUENCY (Hz)

1k

10k

10

100

FREQUENCY (Hz)

1k

10k

Figure 8. ADXL356 Frequency Response for X-Axis

Figure 11. ADXL357 Frequency Response for X-Axis at 4 kHz ODR

10

1

0.1

10

0.01

100

FREQUENCY (Hz)

1k

10

100

FREQUENCY (Hz)

1k

10k

Figure 9. ADXL356 Frequency Response for Y-Axis

Figure 12. ADXL357 Frequency Response for Y-Axis at 4 kHz ODR

10

1

0.1

10

0.01

100

FREQUENCY (Hz)

1k

10

100

FREQUENCY (Hz)

1k

10k

Figure 10. ADXL356 Frequency Response for Z-Axis

Figure 13. ADXL357 Frequency Response for Z-Axis at 4 kHz ODR

Rev. A | Page 12 of 42

Data Sheet

ADXL356/ADXL357

75

1.0

0.5

50

25

0

–25

–50

–75

–0.5

–1.0

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 14. ADXL356 Zero g Offset Normalized Relative to 25°C vs.

Figure 17. ADXL356 Sensitivity Normalized Relative to 25°C vs. Temperature

X-Axis

Temperature, X-Axis

75

50

1.0

0.5

25

0

–25

–50

–75

–0.5

–1.0

–40 –25 –10

5

20

35

50

65

80

95 110 125

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 15. ADXL356 Zero g Offset Normalized Relative to 25°C vs.

Figure 18. ADXL356 Sensitivity Normalized Relative to 25°C vs. Temperature,

Y-Axis

Temperature, Y-Axis

75

50

1.0

0.5

25

0

–25

–50

–75

–0.5

–1.0

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 16. ADXL356 Zero g Offset Normalized Relative to 25°C vs.

Temperature, Z-Axis

Figure 19. ADXL356 Sensitivity Normalized Relative to 25°C vs. Temperature,

Z-Axis

Rev. A | Page 13 of 42

ADXL356/ADXL357

Data Sheet

40

35

30

25

20

15

10

5

25

20

15

10

5

0

X-AXIS OFFSET AT 25°C (mg)

X-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 23. ADXL356 Sensitivity Histogram at 25°C, X-Axis

Figure 20. ADXL356 Zero g Offset Histogram at 25°C, X-Axis

25

30

25

20

15

10

5

20

15

10

5

0

Y-AXIS OFFSET AT 25°C (mg)

Y-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 24. ADXL356 Sensitivity Histogram at 25°C, Y-Axis

Figure 21. ADXL356 Zero g Offset Histogram at 25°C, Y-Axis

25

20

15

10

5

20

15

10

5

0

Z-AXIS OFFSET AT 25°C (mg)

Z-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 22. ADXL356 Zero g Offset Histogram at 25°C, Z-Axis

Figure 25. ADXL356 Sensitivity Histogram at 25°C, Z-Axis

Rev. A | Page 14 of 42

Data Sheet

ADXL356/ADXL357

0.20

0.15

0.10

0.05

0

0.10

0.05

0

–0.05

–0.10

–0.15

–0.05

–0.10

–0.20

0

2

4

6

8

10

0

5

10

15

20

25

INPUT VIBRATION (

g

rms)

INPUT VIBRATION (g rms)

Figure 26. ADXL356 VRE, X-Axis Offset from +1 g, 10 g Range,

X-Axis Orientation = +1 g

Figure 29. ADXL356 VRE, X-Axis Offset from −1 g, 40 g Range,

X-Axis Orientation = −1 g

0.20

0.15

0.10

0.05

0

0.2

0.1

0

–0.05

–0.10

–0.15

–0.20

–0.1

–0.2

0

2

4

6

8

10

0

5

10

15

20

25

INPUT VIBRATION (

g

rms)

INPUT VIBRATION (g rms)

Figure 27. ADXL356 VRE, Y-Axis Offset from +1 g, 10 g Range,

Y-Axis Orientation = +1 g

Figure 30. ADXL356 VRE, Y-Axis Offset from −1 g, 40 g Range,

Y-Axis Orientation = −1 g

0.20

0.15

0.10

0.05

0

0.2

0.1

0

–0.05

–0.10

–0.15

–0.20

–0.1

–0.2

0

2

4

6

8

10

0

5

10

15

20

25

INPUT VIBRATION (

g

rms)

INPUT VIBRATION (g rms)

Figure 28. ADXL356 VRE, Z-Axis Offset from +1 g, 10 g Range,

Z-Axis Orientation = +1 g

Figure 31. ADXL356 VRE, Z-Axis Offset from −1 g, 40 g Range,

Z-Axis Orientation = −1 g

Rev. A | Page 15 of 42

ADXL356/ADXL357

Data Sheet

75

1.0

0.8

50

0.6

0.4

25

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–25

–50

–75

–45 –30 –15

0

15 30 45 60 75 90 105 120 135

TEMPERATURE (°C)

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 32. ADXL357 Zero g Offset Normalized Relative to 25°C vs.

Figure 35. ADXL357 Sensitivity Normalized Relative to 25°C vs. Temperature

X-Axis

Temperature, X-Axis

75

50

1.0

0.8

0.6

0.4

25

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–25

–50

–75

–45

–25

–5

15

35

55

75

95

115

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 33. ADXL357 Zero g Offset Normalized Relative to 25°C vs.

Figure 36. ADXL357 Sensitivity Normalized Relative to 25°C vs. Temperature

Y-Axis

Temperature, Y-Axis

75

50

1.0

0.8

0.6

0.4

25

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–25

–50

–75

–45

–25

–5

15

35

55

75

95

115

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 37. ADXL357 Sensitivity Normalized Relative to 25°C vs. Temperature

Z-Axis

Figure 34. ADXL357 Zero g Offset Normalized Relative to 25°C vs.

Temperature, Z-Axis

Rev. A | Page 16 of 42

Data Sheet

ADXL356/ADXL357

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

0

X-AXIS OFFSET AT 25°C (m

g

)

X-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 38. ADXL357 Zero g Offset Histogram at 25°C, X-Axis

Figure 41. ADXL357 Sensitivity Histogram at 25°C, X-Axis

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

0

Y-AXIS OFFSET AT 25°C (m

g

)

Y-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 39. ADXL357 Zero g Offset Histogram at 25°C, Y-Axis

Figure 42. ADXL357 Sensitivity Histogram at 25°C, Y-Axis

25

30

25

20

15

10

5

20

15

10

5

0

Z-AXIS OFFSET AT 25°C (m

g

)

Z-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 43. ADXL357 Sensitivity Histogram at 25°C, Z-Axis

Figure 40. ADXL357 Zero g Offset Histogram at 25°C, Z-Axis

Rev. A | Page 17 of 42

ADXL356/ADXL357

Data Sheet

0.5

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.05

–0.10

–0.15

–0.20

0

2

4

6

8

10

0

5

10

15

20

25

INPUT VIBRATION (

g

rms)

INPUT VIBRATION (g rms)

Figure 44. ADXL357 VRE, X-Axis Offset from +1 g, 10 g Range,

X-Axis Orientation = +1 g

Figure 47. ADXL357 VRE, X-Axis Offset from −1 g, 40 g Range,

X-Axis Orientation = −1 g

0.5

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.05

–0.10

–0.15

–0.20

0

2

4

6

8

10

0

5

10

15

20

25

INPUT VIBRATION (

g

rms)

INPUT VIBRATION (g rms)

Figure 45. ADXL357 VRE, Y-Axis Offset from +1 g, 10 g Range,

Y-Axis Orientation = +1 g

Figure 48. ADXL357 VRE, Y-Axis Offset from −1 g, 40 g Range,

Y-Axis Orientation = −1 g

0.5

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.05

–0.10

–0.15

–0.20

0

2

4

6

8

10

0

5

10

15

20

25

INPUT VIBRATION (

g

rms)

INPUT VIBRATION (g rms)

Figure 46. ADXL357 VRE, Z-Axis Offset from +1 g, 10 g Range,

Z-Axis Orientation = +1 g

Figure 49. ADXL357 VRE, Z-Axis Offset from +1 g, 40 g Range,

Z-Axis Orientation = +1 g

Rev. A | Page 18 of 42

Data Sheet

ADXL356/ADXL357

1.3

0.0035

0.0030

0.0025

0.0020

0.0015

0.0010

0.0005

0

2600

2500

2300

2100

1900

1700

1500

1300

1100

6

TEMPERATURE SENSOR OUTPUT

LINEAR OFFSET

1.2

1.1

1.0

0.9

0.8

0.7

4

2

0

–2

–4

–0.0005

–0.0010

900

700

TEMPERATURE SENSOR OUTPUT

LINEAR OFFSET

–6

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 50. ADXL356 Temperature Sensor Output and Linear Offset vs.

Temperature

Figure 53. ADXL357 Temperature Sensor Output and Linear Offset vs.

Temperature

35

30

25

20

15

10

5

30

25

20

15

10

5

0

TOTAL SUPPLY CURRENT AT 25°C (µA)

Figure 51. ADXL356 Total Supply Current, 3.3 V

Figure 54. ADXL357 Total Supply Current, 3.3 V

35

30

25

20

15

10

5

0

ODR FREQUENCY (Hz)

Figure 52. ADXL357 Output Data Rate (Internal Clock) Histogram

Rev. A | Page 19 of 42

ADXL356/ADXL357

Data Sheet

ROOT ALLAN VARIANCE (RAV) ADXL357 CHARACTERISTICS

Figure 55 to Figure 57 include data for multiple devices and multiple lots, and they were taken in the ±±0 g range, unless otherwise noted.

1000

100

10

1000

100

10

1

0.01

1

0.01

0.1

1

10

100

1000

0.1

1

10

100

1000

INTEGRATION TIME (Seconds)

Figure 55. ADXL357 RAV, X-Axis

Figure 57. ADXL357 RAV, Z-Axis

1000

100

10

1

0.01

0.1

1

10

100

1000

INTEGRATION TIME (Seconds)

Figure 56. ADXL357 RAV, Y-Axis

Rev. A | Page 20 of 42

Data Sheet

ADXL356/ADXL357

THEORY OF OPERATION

The ADXL356 is a complete 3-axis, ultralow noise and ultrastable

offset microelectromechanical systems (MEMS) accelerometer

with outputs ratiometric to the analog ±.8 V supply, V_±P8ANA. The

ADXL357 adds three high resolution ADCs that use the analog

±.8 V supply as a reference to provide digital outputs insensitive

to the supply voltage. The ADXL356B is pin selectable for ±±0 g

or ±ꢀ0 g full scale, the ADXL356C is pin selectable for ±±0 g or

±ꢁ0 g full scale, and the ADXL357 is programmable for ±±0 g,

±ꢀ0 g, or ±ꢁ0 g full scale. The ADXL357 offers both SPI and I^ꢀC

communications ports.

offset drift and noise. The signal path is fully differential, except

for a differential to single-ended conversion at the analog

outputs of the ADXL356.

The analog accelerometer outputs of the ADXL356 are ratiometric

to V_±P8ANA. Therefore, digitize them carefully. The temperature

sensor output is not ratiometric. The X_OUT, Y_OUT, and Z_OUTanalog

outputs are filtered internally with an antialiasing filter. These

analog outputs also have an internal 3ꢀ kΩ series resistor that

can be used with an external capacitor to set the bandwidth of

the output.

The micromachined, sensing elements are fully differential,

comprising the lateral x-axis and y-axis sensors and the vertical,

teeter totter z-axis sensors. The x-axis and y-axis sensors and

the z-axis sensors go through separate signal paths that minimize

The ADXL357 includes antialias filters before and after the high

resolution Σ-Δ ADC. User-selectable output data rates and filter

corners are provided. The temperature sensor is digitized with a

±ꢀ-bit successive approximation register (SAR) ADC.

Rev. A | Page 21 of 42

ADXL356/ADXL357

Data Sheet

APPLICATIONS INFORMATION

and noise reduction prior to the external ADC. The antialias

filter cutoff frequency must be significantly higher than the

desired signal bandwidth. If the antialias filter corner is too low,

ratiometricity can degrade where the signal attenuation is

different from the reference attenuation.

ANALOG OUTPUT

Figure 58 shows the ADXL356 application circuit. The analog

outputs (X_OUT, Y_OUT, and Z_OUT) are ratiometric to the ±.8 V

analog voltage from the V_±P8ANApin. V_±P8ANAcan be powered

with an on-chip LDO regulator that is powered from V_SUPPLY

_±P8ANAcan also be supplied externally by forcing V_SUPPLYto V_SS,

which disables the LDO regulator. Due to the ratiometric

.

V

DIGITAL OUTPUT

Figure 59 shows the ADXL357 application circuit with the

recommended bypass capacitors. The communications interface

is either SPI or I^ꢀC (see the Serial Communications section for

additional information).

response, the analog output requires referencing to the V_±P8ANA

supply when digitizing to achieve the inherent noise and offset

performance of the ADXL356. The 0 g bias output is nominally

equal to V_±P8ANA/ꢀ. The recommended option is to use the

ADXL356 with a ratiometric ADC (for example, the Analog

Devices, Inc., AD768ꢀ) and V_±P8ANAproviding the voltage

reference. This configuration results in self cancellation of

errors due to minor supply variations.

The ADXL357 includes an internal configurable digital band-

pass filter. Both the high-pass and low-pass poles of the filter

are adjustable, as detailed in the Filter Settings Register section

and Table ꢁꢁ. At power-up, the default conditions for the filters

are as follows:

The ADXL356 outputs two forms of filtering: internal anti-

aliasing filtering with a cutoff frequency of approximately ±.5 kHz,

and external filtering. The external filter uses a fixed, on-chip,

3ꢀ kΩ resistance in series with each output in conjunction with

the external capacitors to implement the low-pass filter antialiasing



High-pass filter (HPF) = dc (off)

Low-pass filter (LPF) = ±000 Hz

Output data rate = ꢁ000 Hz

2.25V TO 3.6V

V

(±20g, ±40g)

DDIO

GND ( ±10g)

0.1µF

1µF

V

11

10

RANGE

1

SUPPLY

1P8ANA

ADC V

REF

ST1

ST2

2

3

4

0.1µF

1µF

ADXL356

V

9

8

SS

1P8DIG

TEMP

V

(MEASUREMENT)

DDIO

GND (STANDBY)

1µF

2.25V TO 3.6V

0.1µF

Figure 58. ADXL356 Application Circuit

2.25V TO 3.6V

0.1µF

1µF

V

11

10

CS/SCL

1

2

3

4

SUPPLY

1P8ANA

SCLK/V

SSIO

MOSI/SDA

MISO/ASEL

0.1µF

1µF

ADXL357

V

TOP VIEW

9

8

SS

(Not to Scale)

1P8DIG

1µF

2.25V TO 3.6V

0.1µF

Figure 59. ADXL357 Application Circuit

Rev. A | Page 22 of 42

Data Sheet

ADXL356/ADXL357

V_1P8ANA

AXES OF ACCELERATION SENSITIVITY

All sensor and analog signal processing circuitry operates in

this domain. Offset and sensitivity of the analog output

ADXL356 are ratiometric to this supply voltage. When using

external ADCs, use V_±P8ANAas the reference voltage. The

Figure 60 shows the axes of acceleration sensitivity. Note that

the output voltage increases when accelerated along the

sensitive axis.

Z

ADXL357 includes ADCs that are ratiometric to V_±P8ANA

,

Y

thereby rendering the offset and sensitivity of the digital output

ADXL357 insensitive to the value of V_±P8ANA. V_±P8ANAcan be an

input or an output as defined by the state of the V_SUPPLYvoltage.

V_1P8DIG

V_±P8DIGis the supply voltage for the internal logic circuitry. A

separate LDO regulator decouples the digital supply noise from

the analog signal path. V_±P8ANAcan be an input or an output as

defined by the state of the V_SUPPLYvoltage. If driven externally,

V_±P8DIGmust be the same voltage as the V_±P8ANAvoltage.

X

Figure 60. Axes of Acceleration Sensitivity

V_DDIO

POWER SEQUENCING

The V_DDIOvalue determines the logic high levels. On the analog

output ADXL356, V_DDIOsets the logic high level for the self test

There are two methods for applying power to the device.

Typically, internal LDO regulators generate the ±.8 V power for

the analog and digital supplies, V_±P8ANAand V_±P8DIG, respectively.

Optionally, the internal LDO regulators can be disabled and

V_±P8ANAand V_±P8DIGare driven by external ±.8 V supplies.

STBY

pins, ST± and STꢀ, as well as the

pin. On the digital output

ADXL357, V_DDIOsets the logic high level for communications

interface ports, as well as the interrupt and DRDY outputs.

The LDO regulators are operational when V_SUPPLYis between

ꢀ.ꢀ5 V and 3.6 V. V_±P8ANAand V_±P8DIGare the regulator outputs in

this mode. Alternatively, when tying V_SUPPLYto V_SS, V_±P8ANAand

V_±P8DIGare supply voltage inputs with a ±.6ꢀ V to ±.98 V range.

When using the internal LDO regulators, connect V_SUPPLYto a

voltage source between ꢀ.ꢀ5 V and 3.6 V. In this case, the

recommended power sequence is to apply power to V_DDIO

,

followed by applying power to V_SUPPLYapproximately ±0 μs later.

If necessary, V_SUPPLYand V_DDIOcan be powered from the same

voltage source, so that both are powered at the same time.

OVERRANGE PROTECTION

To avoid electrostatic capture of the proof mass when the

accelerometer is subject to input acceleration beyond its full-

scale range, all sensor drive clocks turn off for 0.5 ms. In the

±±0 g range setting, the overrange protection activates for input

signals beyond approximately ±ꢁ0 g (±ꢀ54), and for the ±ꢀ0 g

and ±ꢁ0 g range settings, the threshold corresponds to about

±80 g (±ꢀ54).

However, V_SUPPLYcannot be powered before V_DDIO

.

To disable the internal LDO regulators, tie V_SUPPLYto ground and

use external ±.8 V supplies to power V_±P8ANAand V_±P8DIG. V_±P8ANA

and V_±P8DIGmust have the same voltage level. The maximum

acceptable tolerance between the external V_±P8ANAand V_±P8DIG

voltage levels is 50 mV. In the case of bypassing the LDO regulators,

the recommended power sequence is to apply power to V_DDIO

,

When overrange protection occurs, the X_OUT, Y_OUT, and Z_OUTpins

on the ADXL356 begin to drive to midscale, whereas the

ADXL357 floats toward zero, and the first in, first out (FIFO)

buffer begins filling with this data.

followed by applying power to V_±P8DIGapproximately ±0 μs later,

and then applying power to V_±P8ANAapproximately ±0 μs later. If

necessary, V_±P8DIGand V_DDIOcan be powered from the same

external ±.8 V supply, which can also be tied to V_±P8ANAwith

proper isolation, so that all are powered at the same time. In this

case, proper decoupling and low frequency isolation are

important to maintain the noise performance of the sensor.

SELF TEST

The ADXL356 and ADXL357 incorporate a self test feature

that effectively tests the mechanical and electronic system.

Enabling self test stimulates the sensor electrostatically to

produce an output corresponding to the test signal applied as

well as the mechanical force exerted. Only the z-axis response is

specified to validate device functionality.

POWER SUPPLY DESCRIPTION

The ADXL356/ADXL357 have four different power supply

domains: V_SUPPLY, V_±P8ANA, V_±P8DIG, and V_DDIO. The internal

analog and digital circuitry operates at ±.8 V nominal.

In the ADXL356, drive the ST± pin to V_DDIOto invoke self test

mode. Then, by driving the STꢀ pin to V_DDIO, the ADXL356

applies an electrostatic force to the mechanical sensor and

induces a change in output in response to the force. The self test

delta (or response) is the difference in output voltage in the

z-axis when STꢀ is high vs. STꢀ is low, while ST± is asserted.

V_SUPPLY

V_SUPPLYis ꢀ.ꢀ5 V to 3.6 V, which is the input range to the two

LDO regulators that generate the nominal ±.8 V outputs for

V_±P8ANAand V_±P8DIG. Connect V_SUPPLYto V_SSto disable the LDO

regulators, which allows driving V_±P8ANAand V_±P8DIGfrom an

external source.

Rev. A | Page 23 of 42

ADXL356/ADXL357

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

After the self test measurement is complete, bring both pins low

to resume normal operation.

The self test operation is similar in the ADXL357, except ST±

and STꢀ can be accessed through the SELF_TEST register

(Register 0xꢀE).

The self test feature rejects externally applied acceleration and

only responds to the self test force, which allows an accurate

measurement of the self test, even in the presence of external

mechanical noise. When the self test feature is not used, both

ST± and STꢀ must be kept low.

FILTER

1

10

100

1k

10k

The ADXL356/ADXL357 use an analog, low-pass, antialiasing

filter to reduce out of band noise and to limit bandwidth. The

ADXL357 provides further digital filtering options to maintain

optimal noise performance at various ODRs.

INPUT FREQUENCY (Hz)

Figure 61. ADXL357 Digital LPF Response for 4 kHz ODR

The ADXL357 also includes an optional digital high-pass filter

with a programmable corner frequency. By default, the high-

pass filter is disabled. The high-pass corner frequency, where

the output is attenuated by 3 dB, is related to the ODR, and the

HPF_CORNER setting in the filter register (Register 0xꢀ8,

Bits[6:ꢁ]). Table ±± shows the HPF_CORNER response. Figure 6ꢀ

and Figure 63 show the simulated high-pass filter pass-band

and delay responses for a 9.88 Hz cutoff.

The analog, low-pass antialiasing filter in the ADXL356/

ADXL357 provides a fixed 3 dB bandwidth of approximately

±.5 kHz, the frequency at which the voltage output response is

attenuated by approximately 304. The shape of the filter

response in the frequency domain is that of a sinc filter. While

the analog antialiasing filter attenuates the output response

around and above its cutoff frequency, the MEMS sensor has a

resonance at 5.5 kHz and mechanically amplifies the output

response at around ꢀ kHz and above. These competing trends

are apparent in the overall transfer function of the ADXL356, as

shown in Figure 8 to Figure ±0. Therefore, the overall −3 dB

bandwidth of the ADXL356 is ꢀ.ꢁ kHz, and the overall

bandwidth with ±ꢁ dB flatness is about ꢁ.ꢁ kHz.

0

–3

–10

–20

The ADXL356 x-axis, y-axis, and z-axis analog outputs include

an amplifier followed by a series 3ꢀ kΩ resistor, and output to

the X_OUT, the Y_OUT, and the Z_OUTpins, respectively.

–30

–40

–50

The ADXL357 provides an internal ꢀ0-bit, Σ-Δ ADC to digitize

the filtered analog signal. Additional digital filtering (beyond the

analog, low-pass, antialiasing filter) consists of a low-pass digital

decimation filter and a bypassable high-pass filter that supports

output data rates between ꢁ kHz and 3.906 Hz. The decimation

filter consists of two stages. The first stage is fixed decimation

with a ꢁ kHz ODR and a low-pass filter cutoff (3 dB) at about

± kHz. A variable second stage decimation filter is used for the

ꢀ kHz output data rate and below (it is bypassed for ꢁ kHz ODR).

Figure 6± shows the low-pass filter response with a ± kHz corner

(ꢁ kHz ODR) for the ADXL357. Note that Figure 6± does not

include the fixed frequency analog, low-pass, antialiasing filter

with a fixed 3 dB bandwidth of approximately ±.5 kHz.

0

9.8801

100

FREQUENCY (Hz)

Figure 62. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an

HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])

40

32.2122

30

20

10

The ADXL357 pass band of the signal path relates to the

combined filter responses, including the analog filter previously

described, and the digital decimation filter/ODR setting. Table ±0

shows the delay associated with the decimation filter for each

setting and provides the attenuation at the ODR/ꢁ corner.

1

0

9.8801

100

FREQUENCY (Hz)

Figure 63. High-Pass Filter Delay Response for a 4 kHz ODR and an

HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])

Rev. A | Page 24 of 42

Data Sheet

ADXL356/ADXL357

The ADXL357 also includes an interpolation filter after the

decimation filters that produces oversampled/upconverted data

and provides an external synchronization option. See the Data

Synchronization section for more details. Table ±ꢀ shows the

delay and attenuation relative to the programmed ODR.

Group delay is the digital filter delay from the input to the ADC

until data is available at the interface (see the Filter section).

This delay is the largest component of the total delay from

sensor to serial interface.

Table 10. Digital Filter Group Delay and Profile

Delay

Attenuation

Programmed ODR (Hz)

4000

ODR (Cycles)

2.52

2.00

1.78

1.63

1.57

1.54

1.51

1.49

Time (ms)

0.63

1.00

1.78

3.26

Decimator at ODR/4 (dB)

Full Path at ODR/4 (dB)

−3.44

−2.21

−1.92

−1.83

−3.63

−2.26

−1.93

−1.83

4000/2 = 2000

4000/4 = 1000

4000/8 = 500

4000/16 = 250

4000/32 = 125

4000/64 = 62.5

4000/128 ≈ 31

4000/256 ≈ 16

4000/512 ≈ 8

4000/1024 ≈ 4

6.27

12.34

24.18

47.59

96.25

189.58

384.31

1.50

Table 11. Digital High-Pass Filter Response

HPF_CORNER Register Setting

(Register 0x28, Bits[6:4])

HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting

Not applicable, no high-pass filter enabled

24.7 × 10⁻⁴× ODR

−3 dB at 4 kHz ODR (Hz)

000

001

010

011

100

101

110

Off

9.88

2.48

0.62

0.1545

0.03816

0.00952

6.2084 × 10⁻⁴× ODR

1.5545 × 10⁻⁴× ODR

0.3862 × 10⁻⁴× ODR

0.0954 × 10⁻⁴× ODR

0.0238 × 10⁻⁴× ODR

Table 12. Combined Digital Interpolation Filter and Decimation Filter Response

Interpolator Data Rate Resolution

Relative to 64 × ODR (Hz)

Combined Interpolator/

Decimator Delay (ODR Cycles)

Combined Interpolator/

Decimator Delay (ms)

Combined Interpolator/Decimator

Output Attenuation at ODR/4 (dB)

64 × 4000 = 256,000

64 × 2000 = 128,000

64 × 1000 = 64,000

64 × 500 = 32,000

64 × 250 = 16,000

64 × 125 = 8000

3.51661

3.0126

2.752

0.88

1.51

2.75

5.27

10.31

20.38

40.52

80.78

161.31

322.48

644.39

−6.18

−4.93

−4.66

−4.58

−4.55

2.6346

2.5773

2.5473

2.53257

2.52452

2.52045

2.5194

2.51714

64 × 62.5 = 4000

64 × 31.25 = 2000

64 × 15.625 = 1000

64 × 7.8125 = 500

64 × 3.90625 = 250

Rev. A | Page 25 of 42

ADXL356/ADXL357

Data Sheet

SERIAL COMMUNICATIONS

The ꢁ-wire serial interface communicates in either the SPI or

I^ꢀC protocol. The interface affectively autodetects the format

being used, requiring no configuration control to select the format.

SPI BUS SHARING

Use a gated buffer on the SCLK line for the ADXL357 device to

achieve the ultralow noise performance and possibly offset shift

when the ADXL357 must share a SPI bus with another slave

device. This gated SCLK allows the clock signal through only

The ADXL357 multifunction pins are referred to by a single

CS

function of the pin, for example, , when only that function is

CS

relevant.

when the chip select ( ) line is low. See Figure 65 for the

example circuit that provides this type of protection.

SPI PROTOCOL

PROCESSOR

ADXL357

Wire the ADXL357 for SPI communication as shown in the

connection diagram in Figure 6ꢁ. The SPI protocol timing is

shown in Figure 66 to Figure 69. The timing scheme follows the

clock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The

SPI clock speed ranges from ±00 kHz to ±0 MHz.

CS

SS1

SS2

SCLK

SN74LVC1G125

PROCESSOR

SS

ADXL357

CS

MOSI

MISO

SCLK

TO SPI SLAVE 2

MOSI

MISO

SCLK

Figure 65. SCLK Protection Example

Figure 64. 4-Wire SPI Connection

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCLK

MOSI

MISO

A6 A5 A4 A3 A2 A1 A0 RW

D7 D6 D5 D4 D3 D2 D1 D0

Figure 66. SPI Timing Diagram—Single-Byte Read

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCLK

MOSI

A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0

MISO

Figure 67. SPI Timing Diagram—Single-Byte Write

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

SCLK

MOSI

A6 A5 A4 A3 A2 A1 A0 RW

BYTE n

BYTE 1

D7 D6 D5 D4 D3 D2 D1 D0 D7

D0 D7 D6 D5 D4 D3 D2 D1 D0

MISO

Figure 68. SPI Timing Diagram—Multibyte Read

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

SCLK

BYTE n

BYTE 1

A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7

D0 D7 D6 D5 D4 D3 D2 D1 D0

MOSI

MISO

Figure 69. SPI Timing Diagram—Multibyte Write

Rev. A | Page 26 of 42

Data Sheet

ADXL356/ADXL357

Figure 70 to Figure 7ꢀ detail the I^ꢀC protocol timing. The I^ꢀC

interface can be used on most buses operating in I^ꢀC standard

mode (±00 kHz), fast mode (ꢁ00 kHz), fast mode plus (± MHz),

and high speed mode (3.ꢁ MHz). The ADXL357 I^ꢀC device ID

is as follows:

I²C PROTOCOL

The ADXL357 supports point to point I^ꢀC communication.

However, when sharing an SDA bus, the ADXL357 may prevent

communication with other devices on that bus. If at any point,

even when the ADXL357 is not being addressed, the 0x3A and

0x3B bytes (when the ADXL357 device address is set to 0x±D),

or the 0xA6 and 0xA7 bytes (when the ADXL357 device address

is set to 0x53) are transmitted on the SDA bus, the ADXL357

responds with an acknowledge bit and pulls the SDA line down.

For example, this response can occur when reading or writing

the data bytes (0x3A/0x3B or 0xA6/0xA7) to another sensor on

the bus. When the ADXL357 pulls the SDA line down,



MISO/ASEL pin = 0, device address = 0x±D

MISO/ASEL pin = ±, device address = 0x53

If other devices are connected to the same I^ꢀC bus, the nominal

operating voltage level of these other devices cannot exceed

V_DDIOby more than 0.3 V. External pull-up resistors, R_P, are

necessary for proper I^ꢀC operation.

communication with other devices on the bus may be

interrupted. To resolve this interruption, the ADXL357 must be

READING ACCELERATION OR TEMPERATURE

DATA FROM THE INTERFACE

CS

connected to a separate SDA bus, or the /SCL pin must be

Acceleration data is left justified and has a register address order of

most significant data to least significant data, which allows the

user to use multibyte transfers and to take only as much data as

required—8 bits, ±6 bits, or ꢀ0 bits, plus the marker. Temperature

data is ±ꢀ bits unsigned, right justified. The ADXL357 temperature

value is split over two bytes, but is not double buffered, meaning

the value can update between readings of the two registers. The

data in XDATA, YDATA, and ZDATA is always the most recent

available. It is not guaranteed that XDATA, YDATA, and ZDATA

form a set corresponding to one sample point in time. The routine

used to retrieve the data from the device controls this data set

continuity. If data transfers are initiated when the DATA_RDY bit

goes high and completes in a time approximately equal to ±/ODR,

XDATA, YDATA, and ZDATA apply to the same data set.

switched high when communication with the ADXL357 is not

desired (it is normally grounded).

The ADXL357 supports standard (±00 kHz), fast (up to ± MHz)

and high speed (up to 3.ꢁ MHz) data transfer modes when the

bus parameters in Table ꢁ are met. There is no minimum SCL

frequency, with the exception that, when reading data, the clock

must be fast enough to read an entire sample set before new data

overwrites it. Single-byte or multiple byte reads/writes are

supported. With the MISO/ASEL pin low, the I^ꢀC address for

the device is 0x±D and an alternate I^ꢀC address of 0x53 can be

chosen by pulling the MISO/ASEL pin high.

There are no internal pull-up or pull-down resistors for any unused

pins. Therefore, there is no known state or default state for the pins

if left floating or unconnected. SCLK/V_SSIOmust be connected

to ground when communicating to the ADXL357 using I^ꢀC.

For multibyte read or write transactions through either serial

interface, the internal register address auto-increments. When

the top of the register address range, 0x3FF, is reached, the auto-

increment stops and does not wrap back to Address 0x00.

Due to communication speed limitations, the maximum output

data rate when using the ꢁ00 kHz I^ꢀC mode is 800 Hz, and it

scales linearly with a change in the I^ꢀC communication speed.

For example, using I^ꢀC at ±00 kHz limits the maximum ODR to

ꢀ00 Hz. Operation at an output data rate above the recommended

maximum may result in an undesirable effect on the acceleration

data, including missing samples or additional noise.

The address auto-increment function disables when the FIFO

address is used, so that data can be read continuously from the

FIFO as a multibyte transaction. In cases where the starting

address of a multibyte transaction is less than the FIFO address,

the address auto-increments until reaching the FIFO address,

and then stops at the FIFO address.

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

SCL

REPEAT

START

DEVICE ADDRESS

REGISTER ADDRESS

DEVICE ADDRESS

DATA BYTE

STOP

A6 A5 A4 A3 A2 A1 A0

AK

0

A6 A5 A4 A3 A2 A1 A0 AK

AK

RW

0

D6 D5 D4 D3 D2 D1 D0 AK

A6 A5 A4 A3 A2 A1 A0

SINGLE BYTE READ

RW

SDA

INDICATE SDA IS

CONTROLLED BY ADXL357

Figure 70. I²C Timing Diagram—Single-Byte Read

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL

START

DEVICE ADDRESS

REGISTER ADDRESS

DATA BYTE

STOP

AK

0

A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

A6 A5 A4 A3 A2 A1 A0

RW

SDA

Figure 71. I²C Timing Diagram—Single-Byte Write

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19

SCL

START

DEVICE ADDRESS

REGISTER ADDRESS

DATA BYTE 1

DATA BYTE n

D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

AK

0

A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7

A6 A5 A4 A3 A2 A1 A0

RW

SDA

Figure 72. I²C Timing Diagram—Multibyte Write

Rev. A | Page 27 of 42

ADXL356/ADXL357

Data Sheet

FIFO

The FIFO operates in a stream mode. That is, when the FIFO

overruns, new data overwrites the oldest data in the FIFO. A

read from the FIFO address guarantees that the three bytes

associated with the acceleration measurement on an axis all

pertain to the same measurement. The FIFO never overflows,

and the data is always taken out in sets (multiples of three data

points).

control logic inserts the two virtual bits (0b00) between the data

bits and the empty indicator bit. Bit ± indicates that an attempt

was made to read an empty FIFO, and that the data is not valid

acceleration data. Bit 0 is a marker bit to identify the x-axis,

which allows a user to verify that the FIFO data was correctly

read. An acceleration data point for a given axis occupies one

FIFO location. The read pointer, RD_PTR, points to the oldest

stored data that was not read already from the interface (see

Figure 73). There are no physical x-acceleration, y-acceleration, or

z-acceleration data registers. The data read from data registers

(Register 0x08 to Register 0x±0) also comes directly from the most

recent data set in the FIFO, which is pointed to by the z pointer,

Z_PTR (see Figure 73).

There are 96 ꢀ±-bit locations in the FIFO. Each location

contains ꢀ0 bits of data and a marker bit for the x-axis data. A

single-byte read from the FIFO address pops one location from

the FIFO. A multibyte read to the FIFO location pops the FIFO

on the read of the first byte and every third byte read thereafter.

Figure 73 shows the organization of the data in the FIFO. The

acceleration data is twos complement, ꢀ0-bit data. The FIFO

Z_PTR + 1

Z_PTR

0

1

0

1

0

Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12

Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4

Z3 Z2 Z1 Z0

Z_PTR – 1

Z_PTR – 2

Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12

X19 X18 X17 X16 X15 X14 X13 X12

Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12

Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12

X19 X18 X17 X16 X15 X14 X13 X12

Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4

X11 X10 X9 X8 X7 X6 X5 X4

Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4

Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4

X11 X10 X9 X8 X7 X6 X5 X4

Y3 Y2 Y1 Y0

X3 X2 X1 X0

Z3 Z2 Z1 Z0

Y3 Y2 Y1 Y0

X3 X2 X1 X0

0

1

0

1

RD_PTR

VIRTUAL BITS

ACCELERATION DATA

(NOT ALLOCATED IN THE FIFO)

EMPTY INDICATOR

X-AXIS MARKER

ASCENDING SPI ADDRESSES

Figure 73. FIFO Data Organization

Rev. A | Page 28 of 42

Data Sheet

ADXL356/ADXL357

INTERRUPTS

The status register (Register 0x0ꢁ) contains five individual bits,

four of which can be mapped to either the INT± pin, the INTꢀ pin,

or both. The polarity of the interrupt, active high or active low,

is also selectable via the INT_POL bit in the range (Register 0xꢀC)

register. In general, the status register clears when read, but this

is not the case if the condition that caused the interrupt persists

after the read of the register. The definition of persist varies

slightly in each case, but it is described in the DATA_RDY,

DRDY Pin, FIFO_FULL, FIFO_OVR, and Activity sections.

The DRDY pin is similar to an interrupt pins (INTx) but clears

differently. This case is also described.

FIFO_OVR

The FIFO_OVR bit is set when the FIFO is so far overrange that

data is lost. The specified size of the FIFO is 96 locations. The

FIFO_OVR bit is set only when there is an attempt to write past

this 96-location limit.

A read of the status register clears FIFO_OVR. FIFO_OVR is

not set again until data is lost subsequent to this status register

read.

ACTIVITY

The activity bit (Register 0x0ꢁ, Bit 3) is set when the measured

acceleration on any axis is above the value set in the ACT_

THRESH bits for ACT_COUNT consecutive measurements.

An overthreshold condition can shift from one axis to another

on successive measurements and is still counted toward the

consecutive ACT_COUNT count.

DATA_RDY

The DATA_RDY bit is set when new acceleration data is

available to the interface and clears on a read of the status

register. This bit is not set again until acceleration data that is

newer than the status register read is available.

A read of the status register clears the activity bit (Register 0x0ꢁ,

Bit 3), but the bit sets again at the end of the next measurement if

the activity bit (Register 0x0ꢁ, Bit 3) conditions are still satisfied.

Special logic on the clearing of the DATA_RDY bit covers the

corner case where new data arrives during the read of the status

register. In this case, the data ready condition may be missed

completely. This logic results in a delay of the clearing of

DATA_RDY of up to four 5±ꢀ kHz cycles.

NVM_BUSY

The NVM_BUSY bit indicates that the nonvolatile memory

(NVM) controller is busy and, therefore, the NVM cannot be

accessed to read or write. The interrupt functionality requires

the NVM_BUSY bit to be cleared to function.

DRDY PIN

The DRDY pin is not a status register bit. DRDY instead

behaves similar to an unmaskable interrupt. DRDY is set when

new acceleration data is available to the interface. DRDY clears

on a read of the FIFO, on a read of XDATA, YDATA, or

ZDATA, or by an autoclear function that occurs approximately

halfway between output acceleration data sets.

A status register read that occurs after the NVM controller is no

longer busy clears NVM_BUSY.

EXTERNAL SYNCHRONIZATION AND

INTERPOLATION

DRDY is always active high. The INT_POL bit does not affect

DRDY. In external synchronization modes (EXT_SYNC = 0±,

EXT_SYNC = ±0), the first few DRDY pulses after initial

synchronization can be lost or corrupted. The length of this

potential corruption is equal to or less than the group delay.

Therefore, the samples within one group delay is lost or

corrupted after the first synchronization signal. Depending on

the decimation setting and interpolation setting (see Table ±ꢀ),

between one and three samples after the first synchronization

pulse is lost, provided that all the restrictions set in the External

Synchronization and Interpolation section is met.

There are four possible synchronization options for the ADXL357,

three of which are shown in Figure 7ꢁ to Figure 76. For clarity, the

clock frequencies and delays are drawn to scale. The labels in

Figure 7ꢁ to Figure 76 are defined as follows:



Internal ODR is the alignment of the decimated output

data based on the internal clock.



ADC modulator clock shows the internal master clock rate.

DRDY is an output indicator signaling a sample is ready.

The four possible synchronization options are as follows:



No external synchronization (internal clocks used)

Synchronization with an external synchronization signal

and internal clock, interpolation filter enabled

Synchronization with external synchronization and clock

signals, no interpolation filter

FIFO_FULL

The FIFO_FULL bit is set when the entries in the FIFO are

equal to the setting of the FIFO_SAMPLES bits. FIFO_FULL

clears as follows:



Synchronization with external synchronization and clock

signals, interpolation filter enabled



If the number of entries in the FIFO is less than the

number of samples indicated by the FIFO_SAMPLES bits,

which is only the case if sufficient data is read from the

FIFO.



On a read of the status register, but only when the entries

in the FIFO are less than the FIFO_SAMPLES bits.

Rev. A | Page 29 of 42

ADXL356/ADXL357

Data Sheet

EXT_SYNC = 00, EXT_CLK = 0—No External

Synchronization or Interpolation

EXT_SYNC = 01, EXT_CLK = 1—External Synchronization

and External Clock, No Interpolation Filter

This is the default mode of operation for the device. The sensor

runs on an internal ODR and an internal clock that is generated by

an internal oscillator. The internal ODR serves as the synchroniza-

tion master, which generates the data. Register 0xꢀ8 is used to

program the ODR. No external signals are required, and this

mode is used typically when the external processor retrieves

data from the device asynchronously and absolute synchronization

to an external source is not required.

When configured for EXT_SYNC = 0± and EXT_CLK = ± (sync

register, see Table ꢁ7), the user must supply an external clock

(enabled via the EXT_CLK bit) at ±.0ꢀꢁ MHz on the INTꢀ pin

(Pin ±3) and an external synchronization signal, SYNC, on the

DRDY pin (Pin ±ꢁ), as shown in Table ±ꢁ. If configured in this

mode and an external clock is not supplied, the device does not

process any data and reading from the output results in null

values. This mode is schematically shown in Figure 76.

The device outputs a DRDY (active high) to signal that a new

sample is available, and data is retrieved from the real-time

registers or the FIFO. The group delay is based on the

decimation setting, as shown in Table ±0. This mode is shown

in Figure 7ꢁ.

Special restrictions when using this mode include the following:



The external clock frequency on INTꢀ (Pin ±3, see Table ±ꢁ)

must be ±.0ꢀꢁ MHz.



The pulse width of the SYNC signal must be at least

3.9± μs, which represents four cycles of the external clock

(ꢁ ÷ ±.0ꢀꢁ MHz = ~3.9± μs).

EXT_SYNC = 10, EXT_CLK = 0—External Synchronization

with Interpolation



The phase of SYNC must meet an approximate ꢀ5 ns setup

time to the external clock rising edge.

Synchronization using interpolation filters and an external ODR

clock is commonly used when the external processor can

provide a synchronization signal, SYNC, that is asynchronous

to the internal clock at the desired ODR. In this case, an

interpolation filter provides additional time resolution of 6ꢁ

times the programmed ODR (see Table ±ꢀ). Synchronization

with the interpolation filter enabled (EXT_SYNC = ±0) allows

the sensor to operate on an internal clock and output data most

closely associated with the SYNC rising edge.

When using the EXT_SYNC mode and without providing the

SYNC signal, the device runs on its own internal ODR. Similarly,

after external synchronization, the device continues to run

synchronized to the last SYNC pulse it received, which means that

EXT_SYNC = 0± mode can be used with only a single

synchronization pulse.

For more information about the lost sample in Figure 76, see the

DRDY Pin section.

The advantage of this mode is that data is available at an arbitrary

user defined SYNC sample rate and is asynchronous to the internal

clock oscillator. The maximum sample rate cannot exceed

ꢁ000 SPS. The disadvantage of this mode is that the group delay

is increased, with increased attenuation at the band edge.

Additionally, because there is a limit to the time resolution,

there is some distortion related to the mismatch of the external

synchronization relative to the internal clock oscillator. This

mismatch degrades spectral performance. The group delay is

based on the decimation setting and interpolation setting (see

Table ±ꢀ). Figure 75 schematically shows the timings in this

mode, and Table ±3 shows the delay between the SYNC signal

(input) to DRDY (output).

EXT_SYNC = 10, EXT_CLK = 1—External Synchronization

and External Clock, with Interpolation Filter

This mode can be used to run the device on an external clock

and synchronization with an arbitrary sample rate set by the

SYNC signal rate. Conditions for external SYNC and external

clock signals is the same as EXT_SYNC = 0±, EXT_CLK = ±

mode. The interpolation filter provides a frequency resolution

related to the ODR (see Table ±ꢀ). In this case, the data

provided corresponds to the external SYNC signal, which can

be greater than the set ODR and less than ꢁ000 SPS, but the

output pass band remains the same it was prior to the

interpolation filter.

Table 13. EXT_SYNC = 10, DRDY Delay

ODR_LPF

SYNC to DRDY Delay (Oscillator Cycles)

0x0

8

0x1

10

0x2

14

0x3

22

0x4

38

0x5

70

0x6

0x7

0x8

0x9

134

262

1031

2054

4102

0xA

Rev. A | Page 30 of 42

Data Sheet

ADXL356/ADXL357

Table 14. Multiplexing of INT2 and DRDY

Register or Bit Fields

Pins

DRDY (Pin 14)

EXT_SYNC,

Bits[1:0]

INT_MAP,

Bits[7:4]

EXT_CLK

INT2 (Pin 13)

Low

INT2

EXT_CLK

DRDY²

Comments

0

1

0

1

00

0000

DRDY

SYNC

Synchronization is to the internal clocks, and there is no

external clock synchronization.

00

Not 0000

0000

Not 0000¹

01

0000

These options reset the digital filters on every

synchronization pulse and are not recommended.

01³

Not 0000

0000

Not 0000¹

INT2

EXT_CLK

External synchronization, no interpolation filter, and

DRDY (active high) signals that data is ready. Data

represents a sample point group delay earlier in time.

DRDY²

INT2

0

1

10

0000

SYNC

External synchronization, interpolation filter, and DRDY

(active high) signals that data is ready. Data sample

group delay earlier in time.

10³

Not 0000

0000

EXT_CLK

Not 0000

¹No INT2, even though it is enabled.

²DRDY routing through the INT_MAP register takes precedence over the default, per Table 14.

³No DRDY.

GROUP DELAY

(FIXED RELATIVE TO DRDY)

SAMPLE POINT

INTERNAL ODR

ADC MODULATOR CLOCK

DRDY

Figure 74. EXT_SYNC = 00, EXT_CLK = 0, Internal Synchronization, Internal Clock

GROUP DELAY

(FIXED RELATIVE TO SYNC)

SAMPLE POINT

INTERFACE SYNCHRONIZATION DELAY

INTERNAL ODR

INTERPOLATOR

64× ODR

SYNC

110% ODR

DRDY

Figure 75. EXT_SYNC = 10, EXT_CLK = 0, External Synchronization, Internal Clock, Interpolation Filter

GROUP DELAY

SAMPLE POINT

(FIXED RELATIVE TO SYNC)

INTERNAL ODR

EXTERNAL CLOCK

1.024MHz

SYNCHRONIZE

SYNC

LOST SAMPLE

DRDY

Figure 76. EXT_SYNC = 01, EXT_CLK = 1, External Synchronization, External Clock, No Interpolation Filter

Rev. A | Page 31 of 42

ADXL356/ADXL357

Data Sheet

ADXL357 REGISTER MAP

Note that while configuring the ADXL357 in an application, all configuration registers must be programmed before enabling measurement

mode in the POWER_CTL register. When the ADXL357 is in measurement mode, only the following configurations can change: the

HPF_CORNER bits in the filter register, the INT_MAP register, the ST± and STꢀ bits in the SELF_TEST register, and the reset register.

Table 15. ADXL357 Register Map

Hex.

Addr.

0x00

0x01

0x02

0x03

0x04

Register Name

DEVID_AD

DEVID_MST

PARTID

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

DEVID_AD

DEVID_MST

PARTID

Bit 2

Bit 1

Bit 0

Reset R/W

0xAD

0x1D

0xED

0x01

R

REVID

Status

Reserved

NVM_

BUSY

Activity

FIFO_OVR

FIFO_FULL DATA_RDY 0x00

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

FIFO_ENTRIES

TEMP2

Reserved

FIFO_ENTRIES

0x00

R

Reserved

Temperature, Bits[11:8]

0x00

0x01

0x00

0x60

0x00

0x81

0x01

0x00

R

TEMP1

Temperature, Bits[7:0]

XDATA, Bits[19:12]

XDATA, Bits[11:4]

R

XDATA3

R

XDATA2

R

XDATA1

XDATA, Bits[3:0]

YDATA, Bits[3:0]

ZDATA, Bits[3:0]

Reserved

R

YDATA3

YDATA, Bits[19:12]

YDATA, Bits[11:4]

R

YDATA2

R

YDATA1

R

ZDATA3

ZDATA, Bits[19:12]

ZDATA, Bits[11:4]

R

ZDATA2

R

ZDATA1

R

FIFO_DATA

OFFSET_X_H

OFFSET_X_L

OFFSET_Y_H

OFFSET_Y_L

OFFSET_Z_H

OFFSET_Z_L

ACT_EN

FIFO_DATA

R

OFFSET_X, Bits[15:8]

OFFSET_X, Bits[7:0]

OFFSET_Y, Bits[15:8]

OFFSET_Y, Bits[7:0]

OFFSET_Z, Bits[15:8]

OFFSET_Z, Bits[7:0]

R/W

W

Reserved

ACT_Z

ACT_Y

ACT_X

ACT_THRESH_H

ACT_THRESH_L

ACT_COUNT

Filter

ACT_THRESH, Bits[15:8]

ACT_THRESH, Bits[7:0]

ACT_COUNT

Reserved

HPF_CORNER

ODR_LPF

FIFO_SAMPLES

INT_MAP

Sync

FIFO_SAMPLES

ACT_EN2 OVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1

FULL_EN1 RDY_EN1

EXT_SYNC

Reserved

EXT_CLK

Range

I2C_HS

INT_POL

Reserved

Reset

Range

POWER_CTL

SELF_TEST

Reset

Reserved

DRDY_OFF TEMP_OFF Standby

ST2 ST1

Reserved

Rev. A | Page 32 of 42

Data Sheet

ADXL356/ADXL357

REGISTER DEFINITIONS

This section describes the functions of the ADXL357 registers. The ADXL357 powers up with the default register values, as shown in the

reset column of Table ±5.

ANALOG DEVICES ID REGISTER

This register contains the Analog Devices ID, 0xAD.

Address: 0x00, Reset: 0xAD, Name: DEVID_AD

Table 16. Bit Descriptions for DEVID_AD

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

DEVID_AD

Analog Devices ID

0xAD

R

ANALOG DEVICES MEMS ID REGISTER

This register contains the Analog Devices MEMS ID, 0x±D.

Address: 0x01, Reset: 0x1D, Name: DEVID_MST

Table 17. Bit Descriptions for DEVID_MST

Bits

Bit Name

Settings

Description

Reset

0x1D

Access

[7:0]

DEVID_MST

Analog Devices MEMS ID

R

DEVICE ID REGISTER

This register contains the device ID, 0xED (355 octal).

Address: 0x02, Reset: 0xED, Name: PARTID

Table 18. Bit Descriptions for PARTID

Bits

Bit Name

Settings

Description

Reset

0xED

Access

[7:0]

PARTID

Device ID (355 octal)

R

PRODUCT REVISION ID REGISTER

This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision.

Address: 0x03, Reset: 0x01, Name: REVID

Table 19. Bit Descriptions for REVID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

REVID

Mask revision

0x01

R

STATUS REGISTER

This register includes bits that describe the various conditions of the ADXL357.

Address: 0x04, Reset: 0x00, Name: Status

Table 20. Bit Descriptions for Status

Bits Bit Name

Settings Description

Reset Access

[7:5] Reserved

Reserved.

0x0

R

4

3

2

1

0

NVM_BUSY

Activity

FIFO_OVR

FIFO_FULL

DATA_RDY

NVM controller is busy with a refresh, programming, or a built in self test (BIST).

Activity, as defined in the ACT_THRESH_x and ACT_COUNT registers, is detected.

FIFO has overrun, and the oldest data is lost.

FIFO watermark is reached.

A complete x-axis, y-axis, and z-axis measurement was made and results can be read.

Rev. A | Page 33 of 42

ADXL356/ADXL357

Data Sheet

FIFO ENTRIES REGISTER

This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96.

Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES

Table 21. Bit Descriptions for FIFO_ENTRIES

Bits

Bit Name

Settings

Description

Reset

0x0

Access

7

Reserved

R

[6:0]

FIFO_ENTRIES

Number of data samples stored in the FIFO

0x0

TEMPERATURE DATA REGISTERS

These two registers contain the uncalibrated temperature data. The nominal intercept is ±885 LSB at ꢀ5°C and the nominal slope is

−9.05 LSB/°C. TEMPꢀ contains the four most significant bits, and TEMP± contains the eight least significant bits of the ±ꢀ-bit value. The

ADXL357 temperature value is not double buffered, meaning the value can update between reading of the two registers.

Address: 0x06, Reset: 0x00, Name: TEMP2

Table 22. Bit Descriptions for TEMP2

Bits

[7:4]

[3:0]

Bit Name

Settings

Description

Reset

Access

Reserved

Temperature, Bits[11:8]

Uncalibrated temperature data

0x0

R

Address: 0x07, Reset: 0x00, Name: TEMP1

Table 23. Bit Descriptions for TEMP1

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

Temperature, Bits[7:0]

Uncalibrated temperature data

0x00

R

X-AXIS DATA REGISTERS

These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x08, Reset: 0x00, Name: XDATA3

Table 24. Bit Descriptions for XDATA3

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

XDATA, Bits[19:12]

X-axis data

0x00

R

Address: 0x09, Reset: 0x00, Name: XDATA2

Table 25. Bit Descriptions for XDATA2

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

XDATA, Bits[11:4]

X-axis data

0x00

R

Address: 0x0A, Reset: 0x00, Name: XDATA1

Table 26. Bit Descriptions for XDATA1

Bits

[7:4]

[3:0]

Bit Name

Settings

Description

X-axis data

Reserved

Reset

0x0

Access

XDATA, Bits[3:0]

Reserved

R

0x0

Rev. A | Page 34 of 42

Data Sheet

ADXL356/ADXL357

Y-AXIS DATA REGISTERS

These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0B, Reset: 0x00, Name: YDATA3

Table 27. Bit Descriptions for YDATA3

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

YDATA, Bits[19:12]

Y-axis data

0x00

R

Address: 0x0C, Reset: 0x00, Name: YDATA2

Table 28. Bit Descriptions for YDATA2

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

YDATA, Bits[11:4]

Y-axis data

0x00

R

Address: 0x0D, Reset: 0x00, Name: YDATA1

Table 29. Bit Descriptions for YDATA1

Bits

[7:4]

[3:0]

Bit Name

Settings

Description

Y-axis data

Reserved

Reset

0x0

Access

YDATA, Bits[3:0]

Reserved

R

0x0

Z-AXIS DATA REGISTERS

These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0E, Reset: 0x00, Name: ZDATA3

Table 30. Bit Descriptions for ZDATA3

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ZDATA, Bits[19:12]

Z-axis data

0x00

R

Address: 0x0F, Reset: 0x00, Name: ZDATA2

Table 31. Bit Descriptions for ZDATA2

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ZDATA, Bits[11:4]

Z-axis data

0x00

R

Address: 0x10, Reset: 0x00, Name: ZDATA1

Table 32. Bit Descriptions for ZDATA1

Bits

[7:4]

[3:0]

Bit Name

Settings

Description

Z-axis data

Reserved

Reset

0x0

Access

ZDATA, Bits[3:0]

Reserved

R

0x0

Rev. A | Page 35 of 42

ADXL356/ADXL357

Data Sheet

FIFO ACCESS REGISTER

Address: 0x11, Reset: 0x00, Name: FIFO_DATA

Read this register to access data stored in the FIFO.

Table 33. Bit Descriptions for FIFO_DATA

Bits

Bit Name

Settings Description

Reset Access

[7:0]

FIFO_DATA

FIFO data is formatted to 24 bits, three bytes, most significant byte first. A read to this 0x0

address pops an effective three equal byte words of axis data from the FIFO. Two

R

subsequent reads or a multibyte read completes the transaction of this data onto the

interface. Continued reading or a sustained multibyte read of this field continues to

pop the FIFO every third byte. Multibyte reads to this address do not increment the

address pointer. If this address is read due to an auto-increment from the previous

address, it does not pop the FIFO. Instead, it returns zeros and increments on to the

next address.

X-AXIS OFFSET TRIM REGISTERS

Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H

Table 34. Bit Descriptions for OFFSET_X_H

Bits

Bit Name

Settings Description

Reset Access

[7:0]

OFFSET_X,

Bits[15:8]

Offset added to x-axis data after all other signal processing. Data is in twos complement

format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA,

Bits[19:4].

0x0

R/W

Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L

Table 35. Bit Descriptions for OFFSET_X_L

Bits

Bit Name

Settings Description

Reset Access

0x0 R/W

[7:0]

OFFSET_X,

Bits[7:0]

Offset added to x-axis data after all other signal processing. Data is in twos complement

format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA,

Bits[19:4].

Y-AXIS OFFSET TRIM REGISTERS

Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H

Table 36. Bit Descriptions for OFFSET_Y_H

Bits

Bit Name

Settings

Description

Reset Access

0x0 R/W

[7:0]

OFFSET_Y,

Bits[15:8]

Offset added to y-axis data after all other signal processing. Data is in twos complement

format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA,

Bits[19:4].

Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L

Table 37. Bit Descriptions for OFFSET_Y_L

Bits

Bit Name

Settings Description

Reset Access

0x0 R/W

[7:0]

OFFSET_Y,

Bits[7:0]

Offset added to y-axis data after all other signal processing. Data is in twos complement

format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA,

Bits[19:4].

Rev. A | Page 36 of 42

Data Sheet

ADXL356/ADXL357

Z-AXIS OFFSET TRIM REGISTERS

Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H

Table 38. Bit Descriptions for OFFSET_Z_H

Bits

Bit Name

Settings Description

Reset Access

[7:0]

OFFSET_Z,

Bits[15:8]

Offset added to z-axis data after all other signal processing. Data is in twos complement

format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA,

Bits[19:4].

0x0

R/W

Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L

Table 39. Bit Descriptions for OFFSET_Z_L

Bits

Bit Name

Settings Description

Offset added to z-axis data after all other signal processing. Data is in twos complement 0x0

format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA,

Bits[19:4].

Reset Access

[7:0]

OFFSET_Z,

Bits[7:0]

R/W

ACTIVITY ENABLE REGISTER

Address: 0x24, Reset: 0x00, Name: ACT_EN

Table 40. Bit Descriptions for ACT_EN

Bits

[7:3]

2

Bit Name

Reserved

ACT_Z

Settings

Description

Reset

0x0

Access

R

Reserved.

Z-axis data is a component of the activity detection algorithm.

Y-axis data is a component of the activity detection algorithm.

X-axis data is a component of the activity detection algorithm.

0x0

R/W

1

ACT_Y

0x0

0

ACT_X

0x0

ACTIVITY THRESHOLD REGISTERS

Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H

Table 41. Bit Descriptions for ACT_THRESH_H

Bits

Bit Name

Settings Description

Reset Access

0x0 R/W

[7:0]

ACT_THRESH,

Bits[15:8]

Threshold for activity detection. Acceleration magnitude must be above

ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned

magnitude. The significance of ACT_THRESH, Bits[15:0] matches the

significance of Bits[18:3] of XDATA, YDATA, and ZDATA.

Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L

Table 42. Bit Descriptions for ACT_THRESH_L

Bits

Bit Name

Settings Description

Reset Access

[7:0]

ACT_THRESH,

Bits[7:0]

Threshold for activity detection. The acceleration magnitude must be greater

0x0

R/W

than the value in ACT_THRESH to trigger the activity counter. ACT_THRESH is

an unsigned magnitude. The significance of ACT_THRESH, Bits[15:0] matches

the significance of Bits[18:3] of XDATA, YDATA, and ZDATA.

ACTIVITY COUNT REGISTER

Address: 0x27, Reset: 0x01, Name: ACT_COUNT

Table 43. Bit Descriptions for ACT_COUNT

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ACT_COUNT

Number of consecutive events above threshold (from ACT_THRESH) required to

detect activity

0x1

R/W

Rev. A | Page 37 of 42

ADXL356/ADXL357

Data Sheet

FILTER SETTINGS REGISTER

Address: 0x28, Reset: 0x00, Name: Filter

Use this register to specify parameters for the internal high-pass and low-pass filters.

Table 44. Bit Descriptions for Filter

Bits

Bit Name

Settings Description

Reset Access

7

Reserved

0x0

R

[6:4]

HPF_CORNER

−3 dB filter corner for the first-order, high-pass filter relative to the ODR

R/W

000 Not applicable, no high-pass filter enabled

001 24.7 × 10⁻⁴× ODR

010 6.2084 × 10⁻⁴× ODR

011 1.5545 × 10⁻⁴× ODR

100 0.3862 × 10⁻⁴× ODR

101 0.0954 × 10⁻⁴× ODR

110 0.0238 × 10⁻⁴× ODR

ODR and low-pass filter corner

0000 4000 Hz and 1000 Hz

0001 2000 Hz and 500 Hz

0010 1000 Hz and 250 Hz

0011 500 Hz and 125 Hz

[3:0]

ODR_LPF

0x0

R/W

0100 250 Hz and 62.5 Hz

0101 125 Hz and 31.25 Hz

0110 62.5 Hz and 15.625 Hz

0111 31.25 Hz and 7.813 Hz

1000 15.625 Hz and 3.906 Hz

1001 7.813 Hz and 1.953 Hz

1010 3.906 Hz and 0.977 Hz

FIFO SAMPLES REGISTER

Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES

Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid

triggering the FIFO watermark interrupt.

Table 45. Bit Descriptions for FIFO_SAMPLES

Bits Bit Name

Reserved

[6:0] FIFO_SAMPLES

Settings Description

Reset Access

7

Reserved.

0x0

R

Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition.

Values range from 1 to 96.

0x60

R/W

INTERRUPT PIN (INTx) FUNCTION MAP REGISTER

Address: 0x2A, Reset: 0x00, Name: INT_MAP

The INT_MAP register configures the interrupt pins. Bits[7:0] select which functions generate an interrupt on the INT± and INTꢀ pins.

Multiple events can be configured. If the corresponding bit is set to ±, the function generates an interrupt on the interrupt pins.

Table 46. Bit Descriptions for INT_MAP

Bits

Bit Name

ACT_EN2

OVR_EN2

FULL_EN2

RDY_EN2

ACT_EN1

OVR_EN1

FULL_EN1

RDY_EN1

Settings

Description

Reset

0x0

Access

R/W

7

Activity interrupt enable on INT2

FIFO_OVR interrupt enable on INT2

FIFO_FULL interrupt enable on INT2

DATA_RDY interrupt enable on INT2

Activity interrupt enable on INT1

FIFO_OVR interrupt enable on INT1

FIFO_FULL interrupt enable on INT1

DATA_RDY interrupt enable on INT1

Rev. A | Page 38 of 42

6

5

4

3

2

1

0

Data Sheet

ADXL356/ADXL357

DATA SYNCHRONIZATION

Address: 0x2B, Reset: 0x00, Name: Sync

Use this register to control the external timing triggers.

Table 47. Bit Descriptions for Sync

Bits

[7:3]

2

Bit Name

Reserved

EXT_CLK

EXT_SYNC

Settings Description

Reset Access

Reserved.

0x0

R

Enable external clock. See Table 14 for configuration details.

R/W

[1:0]

Enable external synchronization control.

00 Internal synchronization.

01 External synchronization, no interpolation filter. After synchronization, and for

EXT_SYNC within specification, DATA_RDY occurs on EXT_SYNC.

10 External synchronization, interpolation filter, next available data indicated by

DATA_RDY 14 to 8204 oscillator cycles later (longer delay for higher ODR_LPF setting),

data represents a sample point group delay earlier in time.

11 Reserved.

I²C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER

Address: 0x2C, Reset: 0x81, Name: Range

Table 48. Bit Descriptions for Range

Bits

Bit Name

Settings

Description

I²C speed.

Reset

Access

7

I2C_HS

0x1

R/W

1

0

High speed mode.

Fast mode.

6

INT_POL

Interrupt polarity.

INT1 and INT2 are active low.

INT1 and INT2 are active high.

Reserved.

0x0

R/W

0

1

[5:2]

[1:0]

Reserved

Range

0x0

0x1

R

Range.

R/W

01

10

11

10 g.

20 g.

40 g.

POWER CONTROL REGISTER

Address: 0x2D, Reset: 0x01, Name: POWER_CTL

Table 49. Bit Descriptions for POWER_CTL

Bits

[7:3]

2

Bit Name

Settings Description

Reset Access

Reserved

Reserved.

0x0

R

DRDY_OFF

TEMP_OFF

Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready. 0x0

R/W

1

Set to 1 to disable temperature processing. Temperature processing is also disabled

when standby = 1.

0x0

0

Standby

Standby or measurement mode.

0x1

R/W

1

0

Standby mode. In standby mode, the device is in a low power state, and the

temperature and acceleration datapaths are not operating. In addition, digital

functions, including FIFO pointers, reset. Changes to the configuration setting of the

device must be made when standby = 1. An exception is a high-pass filter that can be

changed when the device is operating.

Measurement mode.

Rev. A | Page 39 of 42

ADXL356/ADXL357

Data Sheet

SELF TEST REGISTER

Address: 0x2E, Reset: 0x00, Name: SELF_TEST

Refer to the Self Test section for more information on the operation of the self test feature.

Table 50. Bit Descriptions for SELF_TEST

Bits

[7:2]

1

Bit Name

Reserved

ST2

Settings

Description

Reset

0x0

Access

R

R/W

Reserved.

Set to 1 to enable self test force

Set to 1 to enable self test mode

0

ST1

0x0

RESET REGISTER

Address: 0x2F, Reset: 0x00, Name: Reset

Table 51. Bit Descriptions for Reset

Bits

Bit Name

Settings

Description

Write Code 0x52 to reset the device, similar to a power-on reset (POR)

Reset

0x0

Access

[7:0]

Reset

W

In case of a software reset, an unlikely race condition may occur in products with REVID = 0x0± or earlier. If the race condition occurs,

some factory settings in the NVM load incorrectly to shadow registers (the registers from which the internal logic configures the sensor

and calculates the output after a power-on or a software reset). The incorrect loading of the NVM affects overall performance of the

sensor, such as an incorrect 0 g bias and other performance issues. The incorrect loading of NVM does not occur from a power-on or

after a power cycle. To guarantee reliable operation of the sensor after a software reset, the user can access the shadow registers after a

power-on, read and store the values on the host microprocessor, and compare the values read from the same shadow registers after a

software reset. This method guarantees proper operation in all devices and under all conditions. The recommended steps are as follows:

±. Read the shadow registers, Register 0x50 to Register 0x5ꢁ (five 8-bit registers) after power-up, but before any software reset.

ꢀ. Store these values in a host device (for example, a host microprocessor).

3. After each software reset, read the same five registers. If the values differ, perform a software reset again until they match.

Rev. A | Page 40 of 42

Data Sheet

ADXL356/ADXL357

PCB FOOTPRINT PATTERN

Figure 77 shows the PCB footprint pattern and dimensions in millimeters.

3.22mm

0.68mm

0.70mm

TRIANGULAR MARKER, DETAIL A, POINTS TO PIN 1,

WHICH IS NOT ROUTED INTERNALLY AND DOES NOT

NEED TO BE GROUNDED

14 PLCS

1.8mm × 0.68mm

3.80mm

Figure 77. PCB Footprint Pattern and Dimensions in Millimeters

Rev. A | Page 41 of 42

ADXL356/ADXL357

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

0.80

BSC

6.25

6.00 SQ

5.85

2.25

2.05

1.85

1.674 BSC

0.510 REF

0.30 SQ

(PIN 1 INDEX)

12

14

11

1

DETAIL A

5.60

SQ

3.81

REF

R 0.103

(14 PLCS)

0.508

BSC

8

4

7

5

R 0.25

TOP VIEW

BOTTOM VIEW

SIDE VIEW

0.914

BSC

(4 PLCS)

0.15

BSC

2.54 REF

0.10 BSC

2.20 REF

R 0.203

(14 PLCS)

Figure 78. 14-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-14-1)

Dimensions shown in millimeters

ORDERING GUIDE

Output

Mode

Measurement

Range (g)

Specified

Voltage (V)

Package

Option

Model¹

Temperature Range

−40°C to +125°C

Package Description

14-Terminal LCC

14-Terminal LCC, 13”Reel

14-Terminal LCC, 7”Reel

14-Terminal LCC

14-Terminal LCC, 13”Reel

14-Terminal LCC, 7”Reel

14-Terminal LCC

ADXL356BEZ

Analog

Digital

10, 20

10, 40

3.3

E-14-1

ADXL356BEZ-RL

ADXL356BEZ-RL7

ADXL356CEZ

ADXL356CEZ-RL

ADXL356CEZ-RL7

ADXL357BEZ

ADXL357BEZ-RL

ADXL357BEZ-RL7

EVAL-ADXL356BZ

EVAL-ADXL356CZ

EVAL-ADXL357Z

10, 20, 40

14-Terminal LCC

Evaluation Board for ADXL356B

Evaluation Board for ADXL356C

Evaluation Board for ADXL357

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D15429-6/20(A)

Rev. A | Page 42 of 42


型号：	ADXL356CEZ
厂家：	ADI
描述：	Low Noise, Low Drift, Low Power, 3-Axis MEMS Accelerometers
文件：	总42页 (文件大小：1362K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADXL356CEZ [ADI]

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