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ADuM1440ARQZ [ADI]

Micropower Quad-Channel Digital Isolators; 微功耗四通道数字隔离器
ADuM1440ARQZ
型号： ADuM1440ARQZ
厂家： ADI    ADI
描述：

Micropower Quad-Channel Digital Isolators
微功耗四通道数字隔离器
文件： 总24页 (文件大小：440K)
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Micropower  
Quad-Channel Digital Isolators  
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Ultralow power operation  
3.3 V operation (typical)  
1
2
3
16  
15  
14  
V
V
DD1  
ADuM144x  
QSOP  
DD2  
GND  
GND  
1
2
5.6 µA per channel quiescent current, refresh enabled  
0.3 µA per channel quiescent current, refresh disabled  
148 µA/Mbps per channel typical dynamic current  
2.5 V operation (typical)  
3.1 µA per channel quiescent current, refresh enabled  
0.1 µA per channel quiescent current, refresh disabled  
117 µA/Mbps per channel typical dynamic current  
Small, 16-lead QSOP  
V
V
ENCODE  
ENCODE  
ENCODE  
ENCODE  
DECODE  
DECODE  
DECODE  
DECODE  
V
V
V
V
IA  
OA  
4
5
13  
12  
IB  
OB  
V
V
/V  
IC OC  
/V  
OC IC  
6
7
8
11  
10  
9
/V  
ID OD  
/V  
OD ID  
EN  
EN  
2
1
1
GND  
GND  
2
Figure 1.  
Bidirectional communication  
Up to 2 Mbps data rate (NRZ)  
High temperature operation: 125°C  
High common-mode transient immunity: >25 kV/µs  
Safety and regulatory approvals  
UL 1577 Component Recognition Program (pending)  
2500 V rms for 1 minute per UL 1577  
CSA Component Acceptance Notice #5A (pending)  
VDE Certificate of Conformity (pending)  
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12  
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/  
ADuM1446/ADuM1447 family of quad 2.5 kV digital isolation  
devices are packaged in a small 16-lead QSOP, freeing almost  
70% of board space compared to isolators packages in wide  
body SOIC packages. The devices withstand high isolation  
voltages and meet regulatory requirements, such as UL and  
CSA standards (pending). In addition to the space savings, the  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/  
ADuM1447 operate with supplies as low as 2.25 V.  
V
IORM = 560 VPEAK  
APPLICATIONS  
General-purpose, low power multichannel isolation  
1 MHz, low power peripheral interface (SPI)  
4 mA to 20 mA loop process controls  
Despite the low power consumption, all models of the ADuM1440/  
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
provide low, pulse width distortion at <8 ns. In addition, every  
model has an input glitch filter to protect against extraneous  
noise disturbances.  
GENERAL DESCRIPTION  
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/  
ADuM1446/ADuM14471 are micropower, 4-channel digital  
isolators based on the Analog Devices, Inc., iCoupler® technology.  
Combining high speed, complementary metal oxide semiconductor  
(CMOS) and monolithic air core transformer technologies,  
these isolation components provide outstanding performance  
characteristics superior to the alternatives, such as optocoupler  
devices. As shown in Figure 2, in standard operating mode,  
when ENx = 0 (internal refresh enabled), the current per channel is  
less than 10 µA. When ENx = 1 (internal refresh disabled), the  
current per channel drops to less than 1 µA.  
1000  
100  
10  
EN = 0  
x
EN = 1  
x
1
0.1  
0.1  
1
10  
100  
1000  
10000  
DATA RATE (Mbps)  
Figure 2. Typical Total Supply Current per Channel (VDDx = 3.3 V)  
1 Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
TABLE OF CONTENTS  
Data Sheet  
Features .............................................................................................. 1  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Electrical Characteristics—3.3 V Operation ............................ 3  
Electrical Characteristics—2.5 V Operation ............................ 5  
Recommended Operating Conditions .................................... 10  
Absolute Maximum Ratings ......................................................... 11  
ESD Caution................................................................................ 11  
Pin Configurations and Function Descriptions......................... 12  
Typical Performance Characteristics ........................................... 15  
Applications Information .............................................................. 18  
Printed Circuit Board (PCB) Layout ....................................... 18  
Propagation Delay-Related Parameters................................... 18  
DC Correctness ............................................................................ 18  
Magnetic Field Immunity............................................................. 19  
Power Consumption .................................................................. 20  
Insulation Lifetime..................................................................... 20  
Outline Dimensions....................................................................... 21  
Ordering Guide .......................................................................... 21  
Electrical Characteristics—VDD1 = 3.3 V, VDD2 = 2.5 V  
Operation....................................................................................... 7  
Electrical Characteristics—VDD1 = 2.5 V, VDD2 = 3.3 V  
Operation....................................................................................... 8  
Package Characteristics ............................................................... 9  
Regulatory Information............................................................... 9  
Insulation and Safety-Related Specifications............................ 9  
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation  
Characteristics ............................................................................ 10  
REVISION HISTORY  
10/13—Revision 0: Initial Version  
Rev. 0 | Page 2 of 24  
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION  
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended  
operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications  
are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.  
Table 1.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
SWITCHING SPECIFICATIONS  
Data Rate  
2
180  
Mbps  
ns  
ps/°C  
ns  
ns  
ns  
Within pulse-width distortion (PWD) limit  
50% input to 50% output  
Propagation Delay  
Change vs. Temperature  
Minimum Pulse Width  
Pulse-Width Distortion  
Propagation Delay Skew1  
Channel Matching  
Codirectional  
tPHL, tPLH  
80  
200  
PW  
PWD  
tPSK  
500  
Within PWD limit  
|tPLH − tPHL|  
8
10  
tPSKCD  
tPSKOD  
10  
15  
ns  
ns  
Opposing Direction  
1 tPSK is the magnitude of the worst-case difference in tPHL and tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the  
recommended operating conditions.  
Table 2.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
2 Mbps, no load  
SUPPLY CURRENT  
ADuM1440/ADuM1445  
IDD1  
IDD2  
IDD1  
IDD2  
IDD1  
IDD2  
732  
492  
672  
552  
612  
612  
1000  
750  
900  
900  
900  
900  
µA  
µA  
µA  
µA  
µA  
µA  
ENX = 0 V, VIH =VDD, VIL = 0V  
ENX = 0 V, VIH =VDD, VIL = 0V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ADuM1441/ADuM1446  
ADuM1442/ADuM1447  
Rev. 0 | Page 3 of 24  
 
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Data Sheet  
Table 3. For All Models  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DC SPECIFICATIONS  
Input Threshold  
Logic High  
1
VIH  
VIL  
0.7 VDDx  
V
V
1
Logic Low  
0.3 VDDx  
Output Voltages  
Logic High  
VOH  
VOL  
II  
VDDx1 − 0.1  
VDDx1 − 0.4  
3.0  
2.8  
0.0  
0.2  
V
V
V
V
IOUTx = −20 µA, VIx = VIxH  
IOUTx = −4 mA, VIx = VIxH  
IOUTx = 20 µA, VIx = VIxL  
IOUTx = 4 mA, VIx = VIxL  
Logic Low  
0.1  
0.4  
+1  
1
Input Current per Channel  
Input Switching Thresholds  
Positive Threshold Voltage  
Negative Going Threshold  
Input Hysteresis  
Undervoltage Lockout, VDD1 or VDD2  
Supply Current per Channel  
Quiescent Current  
−1  
+0.01  
µA  
0 V ≤ VIx ≤ VDDx  
VT+  
VT−  
ΔVT  
UVLO  
1.8  
1.2  
0.6  
1.5  
V
V
V
V
Input Supply  
Output Supply  
Input (Refresh Off)  
Output (Refresh Off)  
Dynamic Supply Current  
Input  
IDDI (Q)  
IDDO (Q)  
IDDI (Q)  
IDDO (Q)  
4.8  
0.8  
0.12  
0.13  
10  
3.3  
µA  
µA  
µA  
µA  
ENX low  
ENX low  
ENX high  
ENX high  
IDDI (D)  
IDDO (D)  
88  
60  
µA/Mbps  
µA/Mbps  
Output  
AC SPECIFICATIONS  
Output Rise Time/Fall Time  
Common-Mode Transient Immunity2  
tR/tF  
|CM|  
2
40  
ns  
kV/µs  
10% to 90%  
VIx = VDDx1, VCM = 1000 V,  
25  
transient magnitude = 800 V  
Refresh Rate  
fr  
14  
kbps  
1 VDDx = VDD1 or VDD2  
.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and  
falling common-mode voltage edges.  
Rev. 0 | Page 4 of 24  
 
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION  
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended  
operating range of 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching  
specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.  
Table 4.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
SWITCHING SPECIFICATIONS  
Data Rate  
2
180  
Mbps  
ns  
ps/°C  
ns  
ns  
ns  
Within PWD limit  
50% input to 50% output  
Propagation Delay  
Change vs. Temperature  
Pulse-Width Distortion  
Minimum Pulse Width  
Propagation Delay Skew1  
Channel Matching  
Codirectional  
tPHL, tPLH  
112  
280  
PWD  
PW  
tPSK  
12  
10  
|tPLH − tPHL  
|
500  
Within PWD limit  
tPSKCD  
tPSKOD  
10  
30  
ns  
ns  
Opposing Direction  
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the  
recommended operating conditions.  
Table 5.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
2 Mbps, no load  
SUPPLY CURRENT  
ADuM1440/ADuM1445  
IDD1  
IDD2  
IDD1  
IDD2  
IDD1  
IDD2  
623  
337  
552  
409  
480  
480  
800  
500  
750  
750  
750  
750  
µA  
µA  
µA  
µA  
µA  
µA  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ADuM1441/ADuM1446  
ADuM1442/ADuM1447  
Rev. 0 | Page 5 of 24  
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Data Sheet  
Table 6. For All Models  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DC SPECIFICATIONS  
Input Threshold  
Logic High  
1
VIH  
VIL  
0.7 VDDx  
V
V
1
Logic Low  
0.3 VDDx  
Output Voltages  
Logic High  
VOH  
VOL  
II  
VDDx1 − 0.1  
VDDx1 − 0.4  
2.5  
2.35  
0.0  
0.1  
+0.01  
V
V
V
V
IOx = −20 µA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
IOx = 20 µA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
Logic Low  
0.1  
0.4  
+1  
1
Input Current per Channel  
Input Switching Thresholds  
Positive Threshold Voltage  
Negative Going Threshold  
Input Hysteresis  
Undervoltage Lockout, VDD1 or VDD2  
Supply Current per Channel  
Quiescent Current  
−1  
µA  
0 V ≤ VIx ≤ VDDx  
VT+  
VT−  
ΔVT  
UVLO  
1.5  
1.0  
0.5  
1.5  
V
V
V
V
Input Supply  
Output Supply  
Input (Refresh Off)  
Output (Refresh Off)  
Dynamic Supply Current  
Input  
IDDI (Q)  
IDDO (Q)  
IDDI (Q)  
IDDO (Q)  
2.6  
0.5  
0.05  
0.05  
3.3  
1.8  
µA  
µA  
µA  
µA  
ENX low  
ENX low  
ENX high  
ENX high  
IDDI (D)  
IDDO (D)  
76  
41  
µA/Mbps  
µA/Mbps  
Output  
AC SPECIFICATIONS  
Output Rise Time/Fall Time  
Common-Mode Transient Immunity2  
tR/tF  
|CM|  
2
40  
ns  
kV/µs  
10% to 90%  
VIx = VDDx1, VCM = 1000 V,  
25  
transient magnitude = 800 V  
Refresh Rate  
fr  
14  
kbps  
1 VDDx = VDD1 or VDD2  
.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and  
falling common-mode voltage edges.  
Rev. 0 | Page 6 of 24  
 
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
ELECTRICAL CHARACTERISTICS—VDD1 = 3.3 V, VDD2 = 2.5 V OPERATION  
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and.VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire  
recommended operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.  
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.  
For dc specifications and ac specifications, see Table 3 for Side 1 and see Table 6 for Side 2.  
Table 7.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
SWITCHING SPECIFICATIONS  
Data Rate  
2
Mbps  
Within PWD limit  
Propagation Delay  
Side 1 to Side 2  
Side 2 to Side 1  
Change vs. Temperature  
Pulse-Width Distortion  
Pulse Width  
Propagation Delay Skew1  
Channel Matching  
Codirectional  
tPHL, tPLH  
tPHL, tPLH  
84  
120  
280  
180  
180  
ns  
ns  
ps/°C  
ns  
ns  
50% input to 50% output  
50% input to 50% output  
PWD  
PW  
tPSK  
12  
10  
|tPLH − tPHL  
|
500  
Within PWD limit  
ns  
tPSKCD  
tPSKOD  
10  
60  
ns  
ns  
Opposing Direction  
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the  
recommended operating conditions.  
Table 8.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
2 Mbps, no load  
SUPPLY CURRENT  
ADuM1440/ADuM1445  
IDD1  
IDD2  
IDD1  
IDD2  
IDD1  
IDD2  
732  
337  
672  
409  
612  
480  
1000  
750  
900  
750  
900  
750  
µA  
µA  
µA  
µA  
µA  
µA  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ADuM1441/ADuM1446  
ADuM1442/ADuM1447  
Rev. 0 | Page 7 of 24  
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Data Sheet  
ELECTRICAL CHARACTERISTICS—VDD1 = 2.5 V, VDD2 = 3.3 V OPERATION  
All typical specifications are at TA = 25°C, VDD1 = 2.5, and VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire  
recommended operating range of 2.25 V ≤ VDD1 ≤ 2.75 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.  
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.  
For dc specifications and ac specifications, see Table 6 for Side 1 and see Table 3 for Side 2.  
Table 9.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
SWITCHING SPECIFICATIONS  
Data Rate  
2
Mbps  
Within PWD limit  
Propagation Delay  
Side 1 to Side 2  
Side 2 to Side 1  
tPHL, tPLH  
tPHL, tPLH  
120  
84  
180  
180  
ns  
ns  
50% input to 50% output  
50% input to 50% output  
Change vs. Temperature  
Pulse-Width Distortion  
Pulse Width  
Propagation Delay Skew1  
Channel Matching  
Codirectional  
200  
ps/°C  
ns  
ns  
PWD  
PW  
tPSK  
12  
10  
|tPLH − tPHL  
Within PWD limit  
|
500  
ns  
tPSKCD  
tPSKOD  
10  
60  
ns  
ns  
Opposing Direction  
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the  
recommended operating conditions.  
Table 10.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
2 Mbps, no load  
SUPPLY CURRENT  
ADuM1440/ADuM1445  
IDD1  
IDD2  
IDD1  
IDD2  
IDD1  
IDD2  
623  
492  
552  
552  
480  
612  
1000  
750  
750  
900  
750  
900  
µA  
µA  
µA  
µA  
µA  
µA  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ENX = 0 V, VIH = VDD, VIL = 0 V  
ADuM1441/ADuM1446  
ADuM1442/ADuM1447  
Rev. 0 | Page 8 of 24  
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
PACKAGE CHARACTERISTICS  
Table 11.  
Parameter  
Symbol Min Typ Max Unit Test Conditions/Comments  
Resistance (Input-to-Output)1  
Capacitance (Input-to-Output)1  
Input Capacitance2  
RI-O  
CI-O  
CI  
1013  
2
4.0  
76  
Ω
pF  
pF  
f = 1 MHz  
IC Junction-to-Ambient Thermal Resistance θJA  
°C/W Thermocouple located at center of package underside  
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.  
2 Input capacitance is from any input data pin to ground.  
REGULATORY INFORMATION  
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 are pending approval by the organizations listed in Table 12.  
See Table 17 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross-isolation waveforms  
and insulation levels.  
Table 12.  
UL (Pending)  
CSA (Pending)  
VDE (Pending)  
Recognized under UL 1577 Component  
Recognition Program1  
Approved under CSA Component Acceptance Certified according to DIN V VDE V 0884-10  
Notice #5A  
(VDE V 0884-10):2006-122  
Single protection, 2500 V rms isolation  
voltage  
Basic insulation per CSA 60950-1-03 and  
IEC 60950-1, 400 V rms (566 VPEAK) maximum  
working voltage  
Reinforced insulation, 565 VPEAK  
File E214100  
File 205078  
File 2471900-4880-0001  
1 In accordance with UL 1577, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test voltage of  
≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).  
2 In accordance with DIN V VDE V 0884-10, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test  
voltage ≥1050 VPEAK for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.  
INSULATION AND SAFETY-RELATED SPECIFICATIONS  
Table 13.  
Parameter  
Symbol Value Unit  
Test Conditions/Comments  
Rated Dielectric Insulation Voltage  
Minimum External Tracking and Air Gap (Creepage and  
Clearance)  
2500  
3.1  
V rms  
1-minute duration  
L(I02)  
mm min Measured from input terminals to output  
terminals, shortest distance path along body  
Minimum Clearance in the Plane of the Printed Circuit Board L(I01)  
(PCB Clearance)  
3.8  
mm min Measured from input terminals to output  
terminals, shortest distance through air, line  
of sight, in the PCB mounting plane  
Minimum Internal Gap (Internal Clearance)  
0.017 mm min Insulation distance through insulation  
Tracking Resistance (Comparative Tracking Index)  
Isolation Group  
CTI  
>400  
II  
V
DIN IEC 112/VDE 0303 Part 1  
Material Group (DIN VDE 0110, 1/89, Table 1)  
Rev. 0 | Page 9 of 24  
 
 
 
 
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Data Sheet  
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS  
These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by  
protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.  
Table 14.  
Description  
Test Conditions/Comments  
Symbol Characteristic  
Unit  
Installation Classification per DIN VDE 0110  
For Rated Mains Voltage ≤ 150 V rms  
For Rated Mains Voltage ≤ 300 V rms  
For Rated Mains Voltage ≤ 400 V rms  
Climatic Classification  
Pollution Degree per DIN VDE 0110, Table 1  
Maximum Working Insulation Voltage  
Input-to-Output Test Voltage, Method b1  
I to IV  
I to III  
I to II  
40/105/21  
2
VIORM  
Vpd(m)  
560  
1050  
VPEAK  
VPEAK  
VIORM × 1.875 = Vpd(m), 100% production test,  
t
ini = tm = 1 sec, partial discharge < 5 pC  
Input-to-Output Test Voltage, Method a  
After Environmental Tests Subgroup 1  
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,  
partial discharge < 5 pC  
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,  
partial discharge < 5 pC  
Vpd(m)  
Vpd(m)  
840  
672  
VPEAK  
VPEAK  
After Input and/or Safety Test Subgroup 2  
and Subgroup 3  
Highest Allowable Overvoltage  
Surge Isolation Voltage  
VIOTM  
VIOSM  
3500  
4000  
VPEAK  
VPEAK  
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time  
Safety Limiting Values  
Maximum value allowed in the event of a failure  
(see Figure 3)  
Case Temperature  
Total Power Dissipation at 25°C  
Insulation Resistance at TS  
TS  
IS1  
RS  
150  
1.64  
>109  
°C  
W
Ω
VIO = 500 V  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
RECOMMENDED OPERATING CONDITIONS  
Table 15.  
Parameter  
Symbol  
TA  
VDD1, VDD2  
Value  
Operating Temperature  
Supply Voltages1  
Input Signal Rise and Fall Times  
−40°C to +125°C  
2.25 V to 3.6 V  
1.0 ms  
1 All voltages are relative to their respective grounds. See the DC Correctness  
section for information on immunity to external magnetic fields.  
0
50  
100  
150  
200  
AMBIENT TEMPERATURE (°C)  
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values  
with Case Temperature per DIN V VDE V 0884-10  
Rev. 0 | Page 10 of 24  
 
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Table 17. Maximum Continuous Working Voltage1  
Parameter  
Value  
Constraint  
Table 16.  
Parameter  
AC Voltage  
Rating  
60 Hz Bipolar Waveform  
60 Hz Unipolar Waveform  
Basic Insulation  
DC Voltage  
565 VPEAK 50-year minimum lifetime  
975 VPEAK 50-year minimum lifetime  
975 VPEAK 50-year minimum lifetime  
Supply Voltages (VDD1, VDD2  
Input Voltages (VIA, VIB )  
Output Voltages (VOA, VOB)  
)
−0.5 V to +3.6 V  
−0.5 V to VDDI + 0.5 V  
−0.5 V to VDD2 + 0.5 V  
Average Output Current per Pin1  
Basic Insulation  
Side 1 (IO1)  
Side 2 (IO2)  
Common-Mode Transients2  
Storage Temperature (TST) Range  
Ambient Operating Temperature  
(TA) Range  
−10 mA to +10 mA  
−10 mA to +10 mA  
−100 kV/µs to +100 kV/µs  
−65°C to +150°C  
1 Refers to continuous voltage magnitude imposed across the isolation  
barrier. See the Insulation Lifetime section for more details.  
ESD CAUTION  
−40°C to +125°C  
1 See Figure 3 for maximum safety power values for various temperatures.  
2 Refers to common-mode transients across the insulation barrier. Common-mode  
transients exceeding the absolute maximum ratings can cause latch-up or  
permanent damage.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Table 18. Truth Table (Positive Logic) for all Models  
VIx Input1, 2 VDDI State3  
VDDO State4  
Powered  
Powered  
Powered  
Powered  
ENx Input1  
VOx Output1 Description  
H
L
H
L
Powered  
Powered  
Powered  
Powered  
L
L
H
H
L
H
L
H
L5  
Normal operation; data is high and refresh is enabled.  
Normal operation; data is low and refresh is enabled.  
Output is high, and refresh is disabled.  
Output is low, and refresh is disabled.  
L
Unpowered Powered  
Default  
Input unpowered. Outputs are in the default state, high for  
ADuM1440, ADuM1441, and ADuM1442, and low  
ADuM1445, ADuM1446, and ADuM1447. Outputs return to  
input state within 150 µs of VDDI power restoration. See the  
pin function descriptions (Table 19 through Table 21) for  
more details.  
L
Unpowered Powered  
H
X
Hold  
Z
Input unpowered. Outputs are the last state before input  
power is shut down.  
X
Powered  
Unpowered  
Output unpowered. Output pins are in high impedance  
state. Outputs return to input state within 34 µs of VDDO power  
restoration. See the pin function descriptions (Table 19  
through Table 21) for more details.  
1 H = high, L = low, X = don’t care, and Z = high impedance.  
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).  
3 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).  
4 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).  
5 Low input must follow a falling edge; otherwise, it can be in the default low state.  
Rev. 0 | Page 11 of 24  
 
 
 
 
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
Data Sheet  
V
1
2
3
4
5
6
7
8
16  
V
DD2  
DD1  
1
2
2
GND  
15 GND  
1
V
V
V
V
14  
13  
12  
11  
V
V
V
V
IA  
IB  
IC  
ID  
OA  
OB  
OC  
OD  
ADuM1440/  
ADuM1445  
TOP VIEW  
(Not to Scale)  
EN  
10 EN  
2
1
1
2
9 GND  
2
GND  
1
1
2
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH  
TO GND IS RECOMMENDED.  
1
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING  
BOTH TO GND IS RECOMMENDED.  
2
Figure 4. ADuM1440/ADuM1445 Pin Configuration  
Table 19. ADuM1440/ADuM1445 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range  
between VDD1 (Pin 1) and GND1 (Pin 2).  
2, 8  
GND1  
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is  
recommended.  
3
4
5
6
7
VIA  
VIB  
VIC  
VID  
EN1  
Logic Input A.  
Logic Input B.  
Logic Input C.  
Logic Input D.  
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and watchdog functionality for  
Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables refresh and watchdog functionality for  
lowest power operation, see the Applications Information section for a detailed description of this mode. EN1 and  
EN2 must be set to the same logic state.  
9, 15  
10  
GND2  
EN2  
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is  
recommended.  
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and watchdog functionality  
for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2 disables refresh and watchdog functionality  
for lowest power operation, see the Applications Information section for a detailed description of this mode. EN1  
and EN2 must be set to the same logic state.  
11  
12  
13  
14  
16  
VOD  
VOC  
VOB  
VOA  
VDD2  
Logic Output D.  
Logic Output C.  
Logic Output B.  
Logic Output A.  
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range  
between VDD2 (Pin 16) and GND2 (Pin 15).  
Rev. 0 | Page 12 of 24  
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
V
1
2
3
4
5
6
7
8
16  
V
DD2  
DD1  
1
2
2
GND  
15 GND  
1
V
V
V
14  
13  
12  
11  
V
V
V
V
IA  
IB  
IC  
OA  
OB  
OC  
ID  
ADuM1441/  
ADuM1446  
TOP VIEW  
(Not to Scale)  
V
OD  
EN  
10 EN  
2
1
1
2
9 GND  
2
GND  
1
1
2
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH  
TO GND IS RECOMMENDED.  
1
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING  
BOTH TO GND IS RECOMMENDED.  
2
Figure 5. ADuM1441/ADuM1446 Pin Configuration  
Table 20. ADuM1441/ADuM1446 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range  
between VDD1 (Pin 1) and GND1 (Pin 2).  
2, 8  
GND1  
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is  
recommended.  
3
4
5
6
7
VIA  
VIB  
VIC  
VOD  
EN1  
Logic Input A.  
Logic Input B.  
Logic Input C.  
Logic Output D.  
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and watchdog functionality for  
Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables refresh and watchdog functionality for  
lowest power operation, see the Applications Information section for a detailed description of this mode. EN1 and  
EN2 must be set to the same logic state.  
9, 15  
10  
GND2  
EN2  
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is  
recommended.  
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and watchdog functionality  
for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2 disables refresh and watchdog functionality  
for lowest power operation, see the Applications Information section for a detailed description of this mode. EN1  
and EN2 must be set to the same logic state.  
11  
12  
13  
14  
16  
VID  
Logic Input D.  
Logic Output C.  
Logic Output B.  
Logic Output A.  
VOC  
VOB  
VOA  
VDD2  
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range  
between VDD2 (Pin 16) and GND2 (Pin 15).  
Rev. 0 | Page 13 of 24  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Data Sheet  
V
1
2
3
4
5
6
7
8
16  
V
DD2  
DD1  
1
2
2
GND  
15 GND  
1
V
14  
13  
12  
11  
V
V
V
V
IA  
IB  
OA  
OB  
IC  
ADuM1442/  
ADuM1447  
V
TOP VIEW  
V
V
OC  
(Not to Scale)  
OD  
ID  
EN  
10 EN  
2
1
1
2
9 GND  
2
GND  
1
1
2
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH  
TO GND IS RECOMMENDED.  
1
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING  
BOTH TO GND IS RECOMMENDED.  
2
Figure 6. ADuM1442/ADuM1447 Pin Configuration  
Table 21. ADuM1442/ADuM1447 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range  
between VDD1 (Pin 1) and GND1 (Pin 2).  
2, 8  
GND1  
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is  
recommended.  
3
4
5
6
7
VIA  
VIB  
VOC  
VOD  
EN1  
Logic Input A.  
Logic Input B.  
Logic Output C.  
Logic Output D.  
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and watchdog functionality for  
Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables refresh and watchdog functionality for  
lowest power operation, see the Applications Information section for detailed description of this mode. EN1 and EN2  
must be set to the same logic state.  
9, 15  
10  
GND2  
EN2  
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is  
recommended.  
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and watchdog functionality  
for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2 disables refresh and watchdog functionality  
for lowest power operation, see the Applications Information section for a detailed description of this mode. EN1  
and EN2 must be set to the same logic state.  
11  
12  
13  
14  
16  
VID  
VIC  
VOB  
VOA  
VDD2  
Logic Input D.  
Logic Input C.  
Logic Output B.  
Logic Output A.  
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range  
between VDD2 (Pin 16) and GND2 (Pin 15).  
Rev. 0 | Page 14 of 24  
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
TYPICAL PERFORMANCE CHARACTERISTICS  
350  
140  
120  
100  
80  
300  
15  
4
2
0
10  
250  
5
0
0
20  
40  
0
20  
40  
200  
150  
100  
50  
60  
40  
20  
V
INPUT CURRENT  
V
OUTPUT CURRENT  
DDx  
DDx  
0
0
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
Figure 7. Current Consumption per Input vs. Data Rate for 2.5 V,  
ENx = Low Operation  
Figure 10. Current Consumption per Output vs. Data Rate for 3.3 V,  
ENx = Low Operation  
90  
80  
160  
140  
1.0  
4
2
0
70  
60  
50  
40  
30  
20  
10  
0
120  
100  
80  
60  
40  
20  
0
0.5  
0
0
5
10  
0
20  
40  
V
OUTPUT CURRENT  
V
INPUT CURRENT  
DDx  
DDx  
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
Figure 8. Current Consumption per Output vs. Data Rate for 2.5 V,  
ENx = Low Operation  
Figure 11. Current Consumption per Input vs. Data Rate for 2.5 V,  
ENx = High Operation  
400  
90  
80  
350  
15  
1.0  
10  
70  
300  
0.5  
5
60  
0
250  
0
0
20  
40  
0
5
10  
50  
40  
30  
20  
10  
0
200  
150  
100  
50  
V
INPUT CURRENT  
V
OUTPUT CURRENT  
DDx  
DDx  
0
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
Figure 9. Current Consumption per Input vs. Data Rate for 3.3 V,  
ENx = Low Operation  
Figure 12. Current Consumption per Output vs. Data Rate for 2.5 V,  
ENx = High Operation  
Rev. 0 | Page 15 of 24  
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Data Sheet  
200  
180  
160  
140  
120  
100  
80  
300  
250  
200  
150  
100  
50  
FALLING  
RISING  
1.0  
0.5  
0
0
5
10  
60  
40  
20  
V
INPUT CURRENT  
DDx  
0
0
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
DATA INPUT VOLTAGE (V)  
Figure 13. Current Consumption per Input vs. Data Rate for VDDX = 3.3 V,  
ENx = High Operation  
Figure 16. IDDx Current per Input vs. Data Input Voltage for VDDx = 2.5 V  
140  
10  
9
1.0  
120  
8
0.5  
100  
7
0
0
5
10  
6
80  
60  
40  
20  
0
5
4
3
2
1
OUTPUT  
V
OUTPUT CURRENT  
DDx  
INPUT  
0
–40  
0
500  
1000  
DATA RATE (kbps)  
1500  
2000  
–20  
0
20  
40  
60  
80  
100  
120  
140  
TEMPERATURE (°C)  
Figure 14. Current Consumption per Output vs. Data Rate for VDDx = 3.3 V,  
ENx = High Operation  
Figure 17. Typical Input and Output Supply Current per Channel vs.  
Temperature for VDDx = 2.5 V, Data Rate = 100 kbps  
600  
10  
9
FALLING  
RISING  
500  
400  
300  
200  
100  
0
8
7
6
5
4
3
2
1
OUTPUT  
INPUT  
0
–40  
0
1
2
3
4
–20  
0
20  
40  
60  
80  
100  
120  
140  
DATA INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
Figure 15. Typical IDDx Current per Input vs.  
Data Input Voltage for VDDx = 3.3 V  
Figure 18. Typical Input and Output Supply Current per Channel vs.  
Temperature for VDDx = 3.3 V, Data Rate = 100 kbps  
Rev. 0 | Page 16 of 24  
 
 
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
120  
100  
80  
60  
40  
20  
OUTPUT  
INPUT  
0
–40  
–20  
0
20  
40  
60  
80  
100  
120  
140  
2.0  
2.5  
3.0  
3.5  
4.0  
TEMPERATURE (°C)  
TRANSMITTER V  
(V)  
DDx  
Figure 19. Typical Input and Output Supply Current per Channel vs.  
Temperature for VDDx = 2.5 V, Data Rate = 1000 kbps  
Figure 22. Typical Glitch Filter Operation Threshold  
100  
90  
80  
70  
60  
50  
40  
30  
20  
140  
120  
100  
80  
60  
40  
20  
0
10  
V
V
= 2.5V  
= 3.3V  
DDx  
DDx  
OUTPUT  
INPUT  
0
–40  
–20  
0
20  
40  
60  
80  
100  
120  
140  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
140  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 20. Typical Input and Output Supply Current per Channel vs.  
Temperature for VDDx = 3.3 V, Data Rate = 1000 kbps  
Figure 23. Typical Refresh Period vs. Temperature for  
3.3 V and 2.5 V Operation  
140  
120  
100  
80  
120  
100  
80  
60  
40  
20  
0
60  
40  
20  
V
V
= 2.5V  
= 3.3V  
DDx  
DDx  
0
–40  
–20  
0
20  
40  
60  
80  
100  
120  
140  
2.0  
2.5  
3.0  
3.5  
4.0  
TEMPERATURE (°C)  
V
VOLTAGE (V)  
DDx  
Figure 24. Typical Refresh Period vs. VDDX Voltage  
Figure 21. Typical Propagation Delay vs. Temperature for  
DDx = 3.3 V or VDDx = 2.5 V  
V
Rev. 0 | Page 17 of 24  
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
APPLICATIONS INFORMATION  
Data Sheet  
Channel-to-channel matching is the maximum amount of time  
the propagation delay differs between channels within a single  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/  
ADuM1447 component.  
PRINTED CIRCUIT BOARD (PCB) LAYOUT  
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/  
ADuM1446/ADuM1447 digital isolators require no external  
interface circuitry for the logic interfaces. Power supply bypassing  
is strongly recommended at both input and output supply pins:  
Propagation delay skew is the maximum amount of time the  
propagation delay differs between multiple ADuM1440/  
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
components operating under the same conditions.  
V
DD1 and VDD2 (see Figure 25). Choose a capacitor value between  
0.01 µF and 0.1 µF. The total lead length between both ends of the  
capacitor and the input power supply pin must not exceed 20 mm.  
In edge-based systems, it is critical to reject pulses that are too  
short to be handled by the encode and decode circuits. The  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/  
ADuM1447 implement a glitch filter to reject pulses less than  
the glitch filter operating threshold. This threshold depends on  
the operating voltage, as shown in Figure 22. Any pulse shorter  
than the glitch filter does not pass to the output. When the refresh  
circuit is enabled, pulses that match the glitch filter width have a  
small probability of being stretched until corrected by the next  
refresh cycle, or by the next valid data through that channel. To  
avoid issues with pulse stretching, observe the minimum pulse  
width requirements listed in the switching specifications.  
Using proper PCB design choices, the ADuM1440/ADuM1441/  
ADuM1442/ADuM1445/ADuM1446/ADuM1447 readily meets  
CISPR 22 Class A (and FCC Class A) emissions standards, as  
well as the more stringent CISPR 22 Class B (and FCC Class B)  
standards in an unshielded environment. Refer to the AN-1109  
Application Note, Recommendations for Control of Radiated  
Emissions with iCoupler Devices, for PCB-related EMI mitigation  
techniques, including board layout and stack-up issues.  
V
V
DD2  
DD1  
GND  
V
V
GND  
1
2
V
IA  
IB  
OA  
V
OB  
V
V
V
V
V
V
IC/ OC  
OC/ IC  
V
V
ID/ OD  
OD/ ID  
EN  
1
GND  
1
EN  
GND  
2
DC CORRECTNESS  
2
Standard Operating Mode  
Figure 25. Recommended Printed Circuit Board Layout  
Positive and negative logic transitions at the isolator input cause  
narrow (~1 ns) pulses to be sent to the decoder using the  
transformer. The decoder is bistable and is, therefore, either set  
or reset by the pulses, indicating input logic transitions. When  
refresh and watchdog functions are enabled by pulling EN1 and  
EN2 low, in the absence of logic transitions at the input for more  
than ~140 µs, a periodic set of refresh pulses indicative of the  
correct input state is sent to ensure dc correctness at the output. If  
the decoder receives no internal pulses of more than approximately  
200 µs, the input side is assumed unpowered or nonfunctional,  
in which case, the isolator watchdog circuit forces the output to  
a default state. The default state is either high as in the ADuM1440,  
ADuM1441, and ADuM1442 versions, or low as in the ADuM1445,  
ADuM1446, and ADuM1447 versions.  
For applications involving high common-mode transients, it is  
important to minimize board coupling across the isolation barrier.  
Furthermore, design the board layout so that any coupling that  
does occur equally affects all pins on a given component side.  
Failure to ensure this can cause voltage differentials between  
pins exceeding the absolute maximum ratings of the device,  
thereby leading to latch-up or permanent damage.  
PROPAGATION DELAY-RELATED PARAMETERS  
These products are optimized for minimum power consumption  
by eliminating as many internal bias currents as possible. As a  
result, the timing characteristics are more sensitive to operating  
voltage and temperature than in standard iCoupler products.  
Refer to Figure 17 through Figure 24 for the expected variation  
of these parameters.  
Low Power Operating Mode  
Propagation delay is a parameter defined as the time it takes a  
logic signal to propagate through a component. The input-to-  
output propagation delay time for a high-to-low transition can  
differ from the propagation delay time of a low-to-high transition.  
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/  
ADuM1446/ADuM1447 allow the refresh and watchdog  
functions to be disabled by pulling EN1 and EN2 to logic high for  
the lowest power consumption. These control pins must be set to  
the same value on each side of the component for proper operation.  
INPUT (V  
)
50%  
Ix  
In this mode, the current consumption of the chip drops to the  
microamp range. However, be careful when using this mode  
because dc correctness is no longer guaranteed at startup. For  
example, if the following sequence of events occurs:  
tPLH  
tPHL  
OUTPUT (V  
)
50%  
Ox  
Figure 26. Propagation Delay Parameters  
1. Power is applied to Side 1  
2. A high level is asserted on the VIA input  
3. Power is applied to Side 2  
Pulse width distortion is the maximum difference between  
these two propagation delay values and an indication of how  
accurately the timing of the input signal is preserved.  
Rev. 0 | Page 18 of 24  
 
 
 
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
The high on VIA is not automatically transferred to the Side 2  
OA, and there can be a level mismatch that is not corrected until a  
magnetic field at a given frequency can be calculated. The result  
is shown in Figure 27.  
V
transition occurs at VIA. After power is stable on each side and a  
transition occurs on the input of the channel, that channel’s input  
and output state is correctly matched. This contingency can be  
addressed in several ways, such as sending dummy data, or toggling  
refresh on for a short period to force synchronization after turn on.  
1000  
100  
10  
Recommended Input Voltage for Low Power Operation  
1
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/  
ADuM1446/ADuM1447 implement Schmitt trigger input  
buffers so that the devices operate cleanly in low data rate or  
noisy environments. Schmitt triggers allow a small amount of  
shoot through current when their input voltage is not  
approximate to either VDDx or GNDx levels. This is because the  
two transistors are both slightly on when input voltages are in  
the middle of the supply range. For many digital devices, this  
leakage is not a large portion of the total supply current and  
may not be noticed; however, in the ultralow power ADuM1440/  
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447,  
this leakage can be larger than the total operating current of the  
device and cannot be ignored.  
0.1  
0.01  
0.001  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
Figure 27. Maximum Allowable External Magnetic Flux Density  
For example, at a magnetic field frequency of 1 MHz, the  
maximum allowable magnetic field of 0.5 kgauss induces a  
voltage of 0.25 V at the receiving coil. This is about 50% of the  
sensing threshold and does not cause a faulty output transition.  
Similarly, if such an event occurred during a transmitted pulse  
(and was of the worst-case polarity), it would reduce the received  
pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing  
threshold of the decoder.  
To achieve optimum power consumption with the  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/  
ADuM1447, always drive the inputs as near to VDDx or GNDx levels  
as possible. Figure 15 and Figure 16 illustrate the shoot through  
leakage of an input; therefore, whereas the logic thresholds of the  
input are standard CMOS levels, optimum power performance  
is achieved when the input logic levels are driven within 0.5 V  
of either VDDx or GNDx levels.  
The preceding magnetic flux density values correspond to specific  
current magnitudes at given distances from the ADuM1440/  
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
transformers. Figure 28 shows these allowable current magnitudes  
as a function of frequency for selected distances. As shown, the  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/  
ADuM1447 are extremely immune and can be affected only by  
extremely large currents operating at a high frequency very near  
to the component. For the 1 MHz example noted previously, a  
1.2 kA current would have to be placed 5 mm away from the  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/  
ADuM1447 to affect the operation of the component.  
1000  
MAGNETIC FIELD IMMUNITY  
The magnetic field immunity of the ADuM1440/ADuM1441/  
ADuM1442/ADuM1445/ADuM1446/ADuM1447 is determined  
by the changing magnetic field, which induces a voltage in the  
receiving coil of the transformer large enough to either falsely  
set or reset the decoder. The following analysis defines the  
conditions under which this can occur. The 3.3 V operating  
condition of the ADuM1440/ADuM1441/ADuM1442/  
ADuM1445/ADuM1446/ADuM1447 is examined because it  
represents the most typical mode of operation.  
100  
10  
1
The pulses at the transformer output have an amplitude greater  
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus  
establishing a 0.5 V margin in which induced voltages can be  
tolerated. The voltage induced across the receiving coil is given by  
2
V = (−dβ/dt) ∑ π rn ; n = 1, 2, … , N  
where:  
0.1  
DISTANCE = 5mm  
DISTANCE = 100mm  
DISTANCE = 1m  
0.01  
β is magnetic flux density (gauss).  
rn is the radius of the nth turn in the receiving coil (cm).  
N is the number of turns in the receiving coil.  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
Given the geometry of the receiving coil in the ADuM1440/  
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
and an imposed requirement that the induced voltage be, at most,  
50% of the 0.5 V margin at the decoder, a maximum allowable  
Figure 28. Maximum Allowable Current for  
Various Current-to-ADuM144x Spacings  
Rev. 0 | Page 19 of 24  
 
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Data Sheet  
Note that at combinations of strong magnetic field and high  
frequency, any loops formed by PCB traces can induce error  
voltages sufficiently large enough to trigger the thresholds of  
succeeding circuitry. Take care in the layout of such traces to  
avoid this possibility.  
Analog Devices performs accelerated life testing using voltage levels  
higher than the rated continuous working voltage. Acceleration  
factors for several operating conditions are determined. These  
factors allow calculation of the time to failure at the actual  
working voltage. The values shown in Table 17 summarize the  
peak voltage for 50 years of service life for a bipolar ac operating  
condition and the maximum CSA approved working voltages.  
In many cases, the approved working voltage is higher than the  
50-year service life voltage. Operation at these high working  
voltages can lead to shortened insulation life, in some cases.  
POWER CONSUMPTION  
The supply current at a given channel of the ADuM1440/  
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
isolator is a function of the supply voltage, the data rate of the  
channel, and the output load of the channel.  
The insulation lifetime of the ADuM1440/ADuM1441/  
ADuM1442/ADuM1445/ADuM1446/ADuM1447 depends on  
the voltage waveform type imposed across the isolation barrier.  
The iCoupler insulation structure degrades at different rates  
depending on whether the waveform is bipolar ac, unipolar ac,  
or dc. Figure 29, Figure 30, and Figure 31 illustrate these  
different isolation voltage waveforms.  
For each input channel, the supply current is given by  
I
DDI = IDDI (Q)  
f ≤ 0.5 fr  
f > 0.5 fr  
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)  
For each output channel, the supply current is given by  
DDO = IDDO (Q) f ≤ 0.5 fr  
DDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)  
f > 0.5 fr  
I
Bipolar ac voltage is the most stringent environment. The goal  
of a 50-year operating lifetime under the ac bipolar condition  
determines the Analog Devices recommended maximum  
working voltage.  
I
where:  
DDI (D), IDDO (D) are the input and output dynamic supply currents  
per channel (mA/Mbps).  
DDI (Q), IDDO (Q) are the specified input and output quiescent  
I
In the case of unipolar ac or dc voltage, the stress on the insulation  
is significantly lower. This allows operation at higher working  
voltages while still achieving a 50-year service life. The working  
voltages listed in Table 17 can be applied while maintaining the  
50-year minimum lifetime provided the voltage conforms to  
either the unipolar ac or dc voltage case. Treat any cross-insulation  
voltage waveform that does not conform to Figure 30 or Figure 31  
as a bipolar ac waveform, and limit its peak voltage to the 50-year  
lifetime voltage value listed in Table 17.  
I
supply currents (mA).  
f is the input logic signal frequency (MHz); it is half the input  
data rate, expressed in units of Mbps.  
fr is the input stage refresh rate (Mbps).  
CL is the output load capacitance (pF).  
VDDO is the output supply voltage (V).  
To calculate the total VDD1 and VDD2 supply current, the supply  
currents for each input and output channel corresponding to  
Note that the voltage presented in Figure 30 is shown as sinusoidal  
for illustration purposes only. It is meant to represent any voltage  
waveform varying between 0 V and some limiting value. The  
limiting value can be positive or negative, but the voltage cannot  
cross 0 V.  
V
DD1 and VDD2 are calculated and totaled. Figure 7 through  
Figure 14 show per channel supply currents as a function of  
data rate for an unloaded output condition.  
INSULATION LIFETIME  
RATED PEAK VOLTAGE  
All insulation structures eventually break down when subjected  
to voltage stress over a sufficiently long period. The rate of  
insulation degradation is dependent on the characteristics of the  
voltage waveform applied across the insulation. In addition to  
the testing performed by the regulatory agencies, Analog  
Devices carries out an extensive set of evaluations to determine  
the lifetime of the insulation structure within the ADuM1440/  
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447.  
0V  
Figure 29. Bipolar AC Waveform  
RATED PEAK VOLTAGE  
0V  
Figure 30. Unipolar AC Waveform  
RATED PEAK VOLTAGE  
0V  
Figure 31. DC Waveform  
Rev. 0 | Page 20 of 24  
 
 
 
 
 
Data Sheet  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
OUTLINE DIMENSIONS  
0.197 (5.00)  
0.193 (4.90)  
0.189 (4.80)  
16  
1
9
8
0.158 (4.01)  
0.154 (3.91)  
0.150 (3.81)  
0.244 (6.20)  
0.236 (5.99)  
0.228 (5.79)  
0.010 (0.25)  
0.006 (0.15)  
0.020 (0.51)  
0.010 (0.25)  
0.069 (1.75)  
0.053 (1.35)  
0.065 (1.65)  
0.049 (1.25)  
0.010 (0.25)  
0.004 (0.10)  
0.041 (1.04)  
REF  
SEATING  
PLANE  
8°  
0°  
0.025 (0.64)  
BSC  
0.050 (1.27)  
0.016 (0.41)  
COPLANARITY  
0.004 (0.10)  
0.012 (0.30)  
0.008 (0.20)  
COMPLIANT TO JEDEC STANDARDS MO-137-AB  
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
Figure 32. 16-Lead Shrink Small Outline Package [QSOP]  
(RQ-16)  
(Dimensions shown in inches and (millimeters)  
ORDERING GUIDE  
Number  
Number  
Maximum Default Maximum  
of Inputs, of Inputs, Data Rate Output Propagation  
Temperature  
Delay, 3.3 V (ns) Range  
Package  
Description  
Package  
Option  
Model1, 2  
VDD1 Side  
VDD2 Side  
(Mbps)  
State  
High  
High  
High  
Low  
ADuM1440ARQZ  
ADuM1441ARQZ  
ADuM1442ARQZ  
ADuM1445ARQZ  
ADuM1446ARQZ  
ADuM1447ARQZ  
4
3
2
4
3
2
0
1
2
0
1
2
2
2
2
2
2
2
180  
180  
180  
180  
180  
180  
−40°C to +125°C 16-Lead QSOP RQ-16  
−40°C to +125°C 16-Lead QSOP RQ-16  
−40°C to +125°C 16-Lead QSOP RQ-16  
−40°C to +125°C 16-Lead QSOP RQ-16  
−40°C to +125°C 16-Lead QSOP RQ-16  
−40°C to +125°C 16-Lead QSOP RQ-16  
Low  
Low  
1 Z = RoHS Compliant Part.  
2 Tape and reel is available. The addition of the –RL7 suffix indicates that the product is shipped on 7” tape and reel.  
Rev. 0 | Page 21 of 24  
 
 
 
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
NOTES  
Data Sheet  
Rev. 0 | Page 22 of 24  
Data Sheet  
NOTES  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
Rev. 0 | Page 23 of 24  
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447  
NOTES  
Data Sheet  
©2013 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D11845-0-10/13(0)  
Rev. 0 | Page 24 of 24  

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