ADuM4152ARIZ-RL_技术文档

5 kV, 7-Channel,

SPIsolator Digital Isolators for SPI

Data Sheet

ADuM4151/ADuM4152/ADuM4153

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Supports up to 17 MHz SPI clock speed

4 high speed, low propagation delay, SPI signal isolation

channels

V

1

2

20

19

V

DD1

GND

DD2

GND

ADuM4151

ENCODE

1

2

DECODE

ENCODE

DECODE

MCLK

MO

3

18 SCLK

ENCODE

Three 250 kbps data channels

SI

4

17

16

15

14

13

12

11

20-lead SOIC_IC package with 8.3 mm creepage

High temperature operation: 125°C

High common-mode transient immunity: >25 kV/µs

Safety and regulatory approvals

DECODE

SO

SSS

MI

5

ENCODE

MSS

6

V

7

IA

OA

UL recognition per UL 1577

CONTROL

BLOCK

CONTROL

BLOCK

V

8

IB

OB

5000 V rms for 1 minute SOIC long package

CSA Component Acceptance Notice 5A

VDE certificate of conformity

V

9

OC

IC

GND

1

10

2

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

Maximum working insulation voltage (V_IORM): 849 V peak

Figure 1. ADuM4151 Functional Block Diagram

V

1

2

20

19

V

DD1

DD2

ADuM4152

ENCODE

APPLICATIONS

GND

1

2

DECODE

ENCODE

DECODE

Industrial programmable logic controllers (PLCs)

Sensor isolation

MCLK

MO

3

18 SCLK

ENCODE

SI

4

17

16

15

14

13

12

11

DECODE

GENERAL DESCRIPTION

SO

SSS

MI

5

ENCODE

The ADuM4151/ADuM4152/ADuM4153¹are 7-channel,

SPIsolator™ digital isolators optimized for isolated serial peripheral

interfaces (SPIs). Based on the Analog Devices, Inc., iCoupler®

chip scale transformer technology, the low propagation delay in

MSS

6

V

7

IA

OA

CONTROL

BLOCK

CONTROL

BLOCK

V

8

OB

IB

V

9

OC

IC

SS

the CLK, MO/SI, MI/SO, and SPI bus signals supports SPI

clock rates of up to 17 MHz. These channels operate with 14 ns

propagation delay and 1 ns jitter to optimize timing for SPI.

GND

1

10

2

Figure 2. ADuM4152 Functional Block Diagram

The ADuM4151/ADuM4152/ADuM4153 isolators also provide

three additional independent low data rate isolation channels in

three different channel direction combinations. Data in the slow

channels is sampled and serialized for a 250 kbps data rate with

up to 2.5 µs of jitter in the low speed channels.

V

1

2

20

19

V

DD1

DD2

ADuM4153

ENCODE

GND

1

2

DECODE

ENCODE

DECODE

MCLK

MO

3

18 SCLK

ENCODE

SI

4

17

16

15

14

13

12

11

DECODE

SO

SSS

MI

5

ENCODE

MSS

6

V

7

OA

IA

CONTROL

BLOCK

CONTROL

BLOCK

V

8

OB

IB

V

9

OC

IC

GND

1

10

2

Figure 3. ADuM4153 Functional Block Diagram

¹Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADuM4151/ADuM4152/ADuM4153

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Recommended Operating Conditions .................................... 12

Absolute Maximum Ratings ......................................................... 13

ESD Caution................................................................................ 13

Pin Configurations and Function Descriptions......................... 14

Typical Performance Characteristics ........................................... 17

Applications Information .............................................................. 18

Introduction................................................................................ 18

Printed Circuit Board (PCB) Layout ....................................... 19

Propagation Delay Related Parameters ................................... 19

DC Correctness and Magnetic Field Immunity..................... 19

Power Consumption .................................................................. 20

Insulation Lifetime..................................................................... 20

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3.3 V Operation ............................ 5

Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7

Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9

Package Characteristics ............................................................. 10

Regulatory Information............................................................. 11

Insulation and Safety Related Specifications .......................... 11

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Insulation Characteristics.......................................................... 12

REVISION HISTORY

3/15—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Table 2............................................................................ 3

Changes to Table 5............................................................................ 5

Changes to Table 8............................................................................ 7

Changes to Table 11.......................................................................... 9

Changes to Table 14........................................................................ 11

Changes to Table 16........................................................................ 12

Changes to High Speed Channels Section .................................. 18

10/14—Revision 0: Initial Version

Rev. A | Page 2 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at T_A= 25°C and V_DD1= V_DD2= 5 V. Minimum and maximum specifications apply over the entire

recommended operation range: 4.5 V ≤ V_DD1≤ 5.5 V, 4.5 V ≤ V_DD2≤ 5.5 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching

specifications are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted.

Table 1. Switching Specifications

A Grade

Typ

B Grade

Typ

Parameter

Symbol

Min

Max

Min

Max

Unit

Test Conditions/Comments

MCLK, MO, SO

SPI Clock Rate

SPI_MCLK

DR_FAST

t_PHL, t_PLH

PW

1

2

25

17

34

14

MHz

Mbps

ns

Data Rate Fast (MO, SO)

Propagation Delay

Pulse Width

Within PWD limit

50% input to 50% output

Within PWD limit

12

100

12.5

ns

Pulse Width Distortion

Codirectional Channel Matching¹

Jitter, High Speed

MSS

PWD

t_PSKCD

J_HS

3

2

ns

|t_PLH− t_PHL|

1

Data Rate Fast

Propagation Delay

Pulse Width

Pulse Width Distortion

Setup Time²

DR_FAST

t_PHL, t_PLH

PW

PWD

MSS_SETUP

J_HS

2

25

34

25

Mbps

ns

Within PWD limit

50% input to 50% output

Within PWD limit

21

100

1.5

12.5

10

3

|t_PLH− t_PHL|

Jitter, High Speed

V_IA, V_IB, V_IC

1

ns

Data Rate Slow

Propagation Delay

Pulse Width

DR_SLOW

t_PHL, t_PLH

PW

250

2.6

250

2.6

kbps

µs

Within PWD limit

50% input to 50% output

Within PWD limit

0.1

4

0.1

4

Jitter, Low Speed

V_Ix³Minimum Input Skew⁴

J_LS

t_{VIx SKEW}

2.5

µs

ns

3

10

¹Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2

MSS

The

signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that

reaches the output

MSS

ahead of another fast signal, set up

prior to the competing signal by different times depending on speed grade.

³V_Ix= V_IA, V_IB, or V_IC.

⁴An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 t_{VIx SKEW}time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 2. Supply Current

1 MHz, A Grade

17 MHz, B Grade

Device Number

Symbol

I_DD1

I_DD2

Min

Typ

4.0

6.0

4.8

6.5

4.0

6.0

Max

Min

Typ

14.0

13.5

14.0

13.3

Max

Unit

mA

Test Conditions/Comments

C_L= 0 pF, low speed channels

ADuM4151

8.5

11

22

23

ADuM4152

ADuM4153

I_DD1

I_DD2

8.5

10.5

8.5

21.5

22.5

22

I_DD1

I_DD2

10.5

21

Rev. A | Page 3 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

Table 3. For All Models^{1, 2, 3}

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, V_IA, V_IB, V_IC

Logic High Input Threshold

Logic Low Input Threshold

Input Hysteresis

Input Current per Channel

SCLK, SSS, MI, SI, V_OA, V_OB, V_OC

Logic High Output Voltages

V_IH

V_IL

V_IHYST

I_I

0.7 × V_DDx

V

mV

µA

0.3 × V_DDx

500

−1

+0.01 +1

0 V ≤ V_INPUT≤ V_DDx

V_OH

V_DDx− 0.1

V_DDx− 0.4

5.0

4.8

0.0

0.2

2.6

V

I_OUTPUT= −20 µA, V_INPUT= V_IH

I_OUTPUT= −4 mA, V_INPUT= V_IH

I_OUTPUT= 20 µA, V_INPUT= V_IL

I_OUTPUT= 4 mA, V_INPUT= V_IL

Logic Low Output Voltages

V_OL

0.1

0.4

V_DD1, V_DD2Undervoltage Lockout

Supply Current per High Speed Channel

Dynamic Input Supply Current

Dynamic Output Supply Current

Supply Current for All Low Speed Channels

Quiescent Side 1 Current

UVLO

I_DDI(D)

I_DDO(D)

0.080

0.046

mA/Mbps

I_DD1(Q)

I_DD2Q)

4.3

6.1

mA

Quiescent Side 2 Current

AC SPECIFICATIONS

Output Rise/Fall Time

Common-Mode Transient Immunity⁴

t_R/t_F

|CM|

2.5

35

ns

kV/µs

10% to 90%

V_INPUT= V_DDx, V_CM= 1000 V,

25

transient magnitude = 800 V

¹V_DDx= V_DD1or V_DD2

.

2

MSS

, MO, SO, V_IA, V_IB, or V_ICpins.

SSS

, MI, SI, V_OA, V_OB, or V_OCpins.

V_INPUTis the input voltage of any of the MCLK,

I_OUTPUTis the output current of any of the SCLK,

3

⁴|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V_OHand V_OLlimits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. A | Page 4 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at T_A= 25°C and V_DD1= V_DD2= 3.3 V. Minimum and maximum specifications apply over the entire

recommended operation range: 3.0 V ≤ V_DD1≤ 3.6 V, 3.0 V ≤ V_DD2≤ 3.6 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching

specifications are tested with C_L=15 pF and CMOS signal levels, unless otherwise noted.

Table 4. Switching Specifications

A Grade

B Grade

Parameter

Symbol

Min Typ Max Min Typ Max Unit

Test Conditions/Comments

MCLK, MO, SO

SPI Clock Rate

SPI_MCLK

DR_FAST

t_PHL, t_PLH

PW

1

2

30

12.5

34

20

MHz

Mbps Within PWD limit

Data Rate Fast (MO, SO)

Propagation Delay

Pulse Width

Pulse Width Distortion

Codirectional Channel Matching¹t_PSKCD

ns

50% input to 50% output

Within PWD limit

|t_PLH− t_PHL

100

12.5

PWD

3

4

3

2

|

Jitter, High Speed

MSS

J_HS

1

Data Rate Fast

Propagation Delay

Pulse Width

Pulse Width Distortion

Setup Time²

DR_FAST

t_PHL, t_PLH

PW

PWD

MSS_SETUP

J_LS

2

30

34

30

Mbps Within PWD limit

ns

50% input to 50% output

Within PWD limit

|t_PLH− t_PHL

100

1.5

12.5

10

3

|

Jitter, Low Speed

2.5

V_IA, V_IB, V_IC

Data Rate Slow

Propagation Delay

Pulse Width

DR_SLOW

t_PHL, t_PLH

PW

250

2.6

250

2.6

kbps

µs

Within PWD limit

50% input to 50% output

Within PWD limit

0.1

4

0.1

4

Jitter, Low Speed

V_Ix³Minimum Input Skew⁴

J_LS

t_{VIx SKEW}

2.5

µs

ns

|t_PLH− t_PHL|

3

10

¹Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2

MSS

The

signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that

reaches the output

MSS

ahead of another fast signal, set up

prior to the competing signal by different times depending on speed grade.

³V_Ix= V_IA, V_IB, or V_IC.

⁴An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 t_{VIx SKEW}time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 5. Supply Current

1 MHz, A Grade/B Grade

17 MHz, B Grade

Device Number

Symbol

I_DD1

I_DD2

Min

Typ

3.8

5.1

3.7

5.2

3.7

5.2

Max

7

8

Min

Typ

10.5

9.0

Max

18

17

Unit

mA

Test Conditions/Comments

C_L= 0 pF, low speed channels

ADuM4151

ADuM4152

ADuM4153

I_DD1

I_DD2

6.5

8

11.7

10.0

11.7

10.0

18

16

I_DD1

I_DD2

6.5

9

18

15

Rev. A | Page 5 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

Table 6. For All Models^{1, 2, 3}

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, V_IA, V_IB, V_IC

Logic High Input Threshold

Logic Low Input Threshold

Input Hysteresis

Input Current per Channel

SCLK, SSS, MI, SI, V_OA, V_OB, V_OC

Logic High Output Voltages

V_IH

V_IL

V_IHYST

I_I

0.7 × V_DDx

V

mV

µA

0.3 × V_DDx

500

−1

+0.01 +1

0 V ≤ V_INPUT≤ V_DDx

V_OH

V_DDx− 0.1

V_DDx− 0.4

5.0

4.8

0.0

0.2

2.6

V

I_OUTPUT= −20 µA, V_INPUT= V_IH

I_OUTPUT= −4 mA, V_INPUT= V_IH

I_OUTPUT= 20 µA, V_INPUT= V_IL

I_OUTPUT= 4 mA, V_INPUT= V_IL

Logic Low Output Voltages

V_OL

0.1

0.4

V_DD1, V_DD2Undervoltage Lockout

Supply Current per High Speed Channel

Dynamic Input Supply Current

Dynamic Output Supply Current

Supply Current for All Low Speed Channels

Quiescent Side 1 Current

UVLO

I_DDI(D)

I_DDO(D)

0.086

0.019

mA/Mbps

I_DD1(Q)

I_DD2Q)

2.9

4.7

mA

Quiescent Side 2 Current

AC SPECIFICATIONS

Output Rise/Fall Time

Common-Mode Transient Immunity⁴

t_R/t_F

|CM|

2.5

35

ns

kV/µs

10% to 90%

V_INPUT= V_DDx, V_CM= 1000 V,

25

transient magnitude = 800 V

¹V_DDx= V_DD1or V_DD2

.

2

MSS

, MO, SO, V_IA, V_IB, or V_ICpins.

SSS

, MI, SI, V_OA, V_OB, or V_OCpins.

V_INPUTis the input voltage of any of the MCLK,

I_OUTPUTis the output current of any of the SCLK,

3

⁴|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V_OHand V_OLlimits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. A | Page 6 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= 5 V, and V_DD2= 3.3 V. Minimum and maximum specifications apply over the entire

recommended operation range: 4.5 V ≤ V_DD1≤ 5.5 V, 3.0 V ≤ V_DD2≤ 3.6 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching

specifications are tested with C_L=15 pF and CMOS signal levels, unless otherwise noted.

Table 7. Switching Specifications

A Grade

B Grade

Parameter

Symbol

Min Typ Max Min Typ Max Unit

Test Conditions/Comments

MCLK, MO, SO

SPI Clock Rate

SPI_MCLK

DR_FAST

t_PHL, t_PLH

PW

1

2

27

15.6

34

16

MHz

1/(4 × t_PHL)

Data Rate Fast (MO, SO)

Propagation Delay

Pulse Width

Pulse Width Distortion

Codirectional Channel Matching¹t_PSKCD

Mbps Within PWD limit

ns

50% input to 50% output

Within PWD limit

|t_PLH− t_PHL

100

12.5

PWD

3

2

|

Jitter, High Speed

MSS

J_HS

1

Data Rate Fast

Propagation Delay

Pulse Width

Pulse Width Distortion

Setup Time²

DR_FAST

t_PHL, t_PLH

PW

PWD

MSS_SETUP

J_HS

2

27

34

26

Mbps Within PWD limit

ns

50% input to 50% output

Within PWD limit

|t_PLH− t_PHL

100

1.5

12.5

10

3

|

Jitter, High Speed

V_IA, V_IB, V_IC

Data Rate Slow

Propagation Delay

Pulse Width

DR_SLOW

t_PHL, t_PLH

PW

250

2.6

250

2.6

kbps

µs

Within PWD limit

50% input to 50% output

Within PWD limit

0.1

4

0.1

4

Jitter, Low Speed

V_Ix³Minimum Input Skew⁴

J_LS

t_{VIx SKEW}

2.5

µs

ns

3

10

¹Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2

MSS

The

signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that

reaches the output

MSS

ahead of another fast signal, set up

prior to the competing signal by different times depending on speed grade.

³V_Ix= V_IA, V_IB, or V_IC.

⁴An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 t_{VIx SKEW}time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 8. Supply Current

1 MHz, A Grade/B Grade

17 MHz, B Grade

Device Number

Symbol

I_DD1

I_DD2

Min

Typ

4.0

4.6

4.8

5.0

4.0

4.7

Max

8.5

8

Min

Typ

13.9

9.0

Max

Unit

mA

Test Conditions/Comments

C_L= 0 pF, low speed channels

ADuM4151

22

17

ADuM4152

ADuM4153

I_DD1

I_DD2

8.5

8

14.0

10.0

14.0

10.0

21.5

16

I_DD1

I_DD2

8.5

9

22

15

Rev. A | Page 7 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

Table 9. For All Models^{1, 2, 3}

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, V_IA, V_IB, V_IC

Logic High Input Threshold

Logic Low Input Threshold

Input Hysteresis

Input Current per Channel

SCLK, SSS, MI, SI, V_OA, V_OB, V_OC

Logic High Output Voltages

V_IH

V_IL

V_IHYST

I_I

0.7 × V_DDx

V

mV

µA

0.3 × V_DDx

500

−1

+0.01 +1

0 V ≤ V_INPUT≤ V_DDx

V_OH

V_DDX− 0.1

V_DDX− 0.4

5.0

4.8

0.0

0.2

2.6

V

I_OUTPUT= −20 µA, V_INPUT= V_IH

I_OUTPUT= −4 mA, V_INPUT= V_IH

I_OUTPUT= 20 µA, V_INPUT= V_IL

I_OUTPUT= 4 mA, V_INPUT= V_IL

Logic Low Output Voltages

V_OL

0.1

0.4

V_DD1, V_DD2Undervoltage Lockout

Supply Current for All Low Speed Channels

Quiescent Side 1 Current

UVLO

I_DD1(Q)

I_DD2Q)

4.3

4.7

mA

Quiescent Side 2 Current

AC SPECIFICATIONS

Output Rise/Fall Time

Common-Mode Transient Immunity⁴

t_R/t_F

|CM|

2.5

35

ns

kV/µs

10% to 90%

V_INPUT= V_DDX, V_CM= 1000 V,

25

transient magnitude = 800 V

¹V_DDx= V_DD1or V_DD2

.

2

MSS

, MO, SO, V_IA, V_IB, or V_ICpins.

SSS

, MI, SI, V_OA, V_OB, V_OCpins.

V_INPUTis the input voltage of any of the MCLK,

I_OUTPUTis the output current of any of the SCLK,

3

⁴|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V_OHand V_OLlimits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. A | Page 8 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= 3.3 V, and V_DD2= 5 V. Minimum and maximum specifications apply over the entire

recommended operation range: 3.0 V ≤ V_DD1≤ 3.6 V, 4.5 V ≤ V_DD2≤ 5.5 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching

specifications are tested with C_L=15 pF and CMOS signal levels, unless otherwise noted.

Table 10. Switching Specifications

A Grade

Symbol Min Typ

B Grade

Max Min Typ

Parameter

Max Unit

Test Conditions/Comments

MCLK, MO, SO

SPI Clock Rate

SPI_MCLK

DR_FAST

t_PHL, t_PLH

PW

PWD

t_PSKCD

J_HS

1

2

27

15.6 MHz

Data Rate Fast (MO, SO)

Propagation Delay

Pulse Width

Pulse Width Distortion

Codirectional Channel Matching¹

Jitter, High Speed

MSS

34

16

Mbps Within PWD limit

ns

50% input to 50% output

Within PWD limit

|t_PLH− t_PHL|

100

12.5

3

5

3

2

1

Data Rate Fast

Propagation Delay

Pulse Width

Pulse Width Distortion

Setup Time²

DR_FAST

t_PHL, t_PLH

PW

PWD

MSS_SETUP1.5

J_HS

2

27

34

27

Mbps Within PWD limit

ns

50% input to 50% output

Within PWD limit

|t_PLH− t_PHL

12.5

10

2

3

|

Jitter, High Speed

V_IA, V_IB, V_IC

Data Rate

Propagation Delay

Pulse Width

DR_SLOW

t_PHL, t_PLH

PW

250

2.6

250

2.6

kbps

µs

Within PWD limit

50% input to 50% output

Within PWD limit

0.1

4

0.1

4

Jitter, Low Speed

V_Ix³Minimum Input Skew⁴

J_LS

t_{VIx SKEW}

2.5

µs

ns

|t_PLH− t_PHL|

3

10

¹Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2

MSS

The

signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that

reaches the output

ahead of another fast signal, it must be set up prior to the competing signal by different times depending on speed grade.

³V_Ix= V_IA, V_IB, or V_IC.

⁴An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 t_{VIx SKEW}time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 11. Supply Current

1 MHz, A Grade/B Grade

17 MHz, B Grade

Device Number

Symbol

I_DD1

I_DD2

Min

Typ

2.8

6.0

3.5

6.5

2.8

6.0

Max

7

10.5

6.5

10.5

6.5

10.5

Min

Typ

10.5

13.0

11.7

13.4

11.7

13.4

Max

18

23

Unit

mA

Test Conditions/Comments

C_L= 0 pF, low speed channels

ADuM4151

ADuM4152

ADuM4153

I_DD1

I_DD2

18

22.5

18

I_DD1

I_DD2

21

Rev. A | Page 9 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

Table 12. For All Models^{1, 2, 3}

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, V_IA, V_IB, V_IC

Logic High Input Threshold

Logic Low Input Threshold

Input Hysteresis

Input Current per Channel

SCLK, SSS, MI, SI, V_OA, V_OB, V_OC

Logic High Output Voltages

V_IH

V_IL

V_IHYST

I_I

0.7 × V_DDx

V

mV

µA

0.3 × V_DDx

500

−1

+0.01 +1

0 V ≤ V_INPUT≤ V_DDx

V_OH

V_DDx− 0.1

V_DDx− 0.4

5.0

4.8

0.0

0.2

2.6

V

I_OUTPUT= −20 µA, V_INPUT= V_IH

I_OUTPUT= −4 mA, V_INPUT= V_IH

I_OUTPUT= 20 µA, V_INPUT= V_IL

I_OUTPUT= 4 mA, V_INPUT= V_IL

Logic Low Output Voltages

V_OL

0.1

0.4

V_DD1, V_DD2Undervoltage Lockout

Supply Current for All Low Speed Channels

Quiescent Side 1 Current

UVLO

I_DD1(Q)

I_DD2Q)

2.9

6.1

mA

Quiescent Side 2 Current

AC SPECIFICATIONS

Output Rise/Fall Time

Common-Mode Transient Immunity⁴

t_R/t_F

|CM|

2.5

35

ns

kV/µs

10% to 90%

V_INPUT= V_DDX, V_CM= 1000 V,

25

transient magnitude = 800 V

¹V_DDx= V_DD1or V_DD2

.

2

MSS

, MO, SO, V_IA, V_IB, V_ICpins.

SSS

, MI, SI, V_OA, V_OB, V_OCpins.

V_INPUTis the input voltage of any of the MCLK,

I_OUTPUTis the output current of any of the SCLK,

3

⁴|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V_OHand V_OLlimits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

PACKAGE CHARACTERISTICS

Table 13.

Parameter

Symbol Min Typ Max Unit

Test Conditions/Comments

Resistance (Input to Output)¹

Capacitance (Input to Output)¹

Input Capacitance²

R_I-O

C_I-O

C_I

10¹²

1.0

4.0

46

Ω

pF

f = 1 MHz

IC Junction to Ambient Thermal Resistance θ_JA

°C/W Thermocouple located at center of package underside

¹The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.

²Input capacitance is from any input data pin to ground.

Rev. A | Page 10 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

REGULATORY INFORMATION

The ADuM4151/ADuM4152/ADuM4153 are approved by the organizations listed in Table 14. See Table 19 and the Insulation Lifetime

section for the recommended maximum working voltages for specific cross isolation waveforms and insulation levels.

Table 14.

UL

CSA

VDE

Recognized Under UL 1577

Approved under CSA Component Acceptance

Notice 5A

Certified according to DIN V VDE V 0884-10

(VDE V 0884-10):2006-12²

Component Recognition Program¹

5000 V rms Single Protection

Basic insulation per CSA 60950-1-07+A1+A2

and IEC 60950-12nd Ed+A1+A2., 800 V rms

(1131 V peak) maximum working voltage³

Reinforced insulation, 849 V peak

Reinforced Insulation per CSA 60950-1-

07+A1+A2 and IEC 60950-1 2^ndEd.+A1+A2,

400 V rms (565 V peak) maximum working

voltage

Reinforced insulation (2MOPP) per IEC 60601-1

Ed.3.1, 250 V rms (353 V peak) maximum

working

File E214100

File 205078

File 2471900-4880-0001

¹In accordance with UL 1577, each model is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (current leakage detection limit = 10 µA).

²In accordance with DIN V VDE V 0884-10, each model is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC).

The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.

³Use at working voltages above 400 V_{AC RMS}shortens lifetime of the isolator significantly. See Table 19 for recommended maximum working voltages under ac and dc conditions.

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 15.

Parameter

Symbol Value

Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

5000

8.3

V rms

1-minute duration

L(I01)

L(I02)

mm min Measured from input terminals to output terminals,

shortest distance through air

mm min Measured from input terminals to output terminals,

shortest distance path along body

Minimum External Tracking (Creepage)

8.3

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Material Group

0.017

>400

II

mm min Insulation distance through insulation

CTI

V

DIN IEC 112/VDE 0303, Part 1

Material group (DIN VDE 0110, 1/89, Table 1)

Rev. A | Page 11 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by

protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.

Table 16.

Description

Test Conditions/Comments

Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input-to-Output Test Voltage, Method b1

I to IV

I to III

I to II

40/105/21

2

V_IORM

V_pd(m)

849

1592

V peak

V_IORM× 1.875 = V_pd(m), 100% production test,

t

_ini= t_m= 1 sec, partial discharge < 5 pC

Input-to-Output Test Voltage, Method a

After Environmental Tests Subgroup 1

V_IORM× 1.5 = V_pd(m), t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

V_pd(m)

1274

1019

V peak

After Input and/or Safety Test Subgroup 2 V_IORM× 1.2 = V_pd(m), t_ini= 60 sec, t_m= 10 sec,

and Subgroup 3

partial discharge < 5 pC

Highest Allowable Overvoltage

Surge Isolation Voltage

V_IOTM

V_IOSM

6000

6250

V peak

V_IOSM(TEST)= 10 kV, 1.2 µs rise time, 50 µs, 50% fall time

Safety Limiting Values

Maximum value allowed in the event of a

failure (see Figure 4)

Case Temperature

Safety Total Dissipated Power

Insulation Resistance at T_S

T_S

P_S

R_S

130

2.4

>10⁹

°C

W

Ω

V_IO= 500 V

3.0

2.5

2.0

1.5

1.0

0.5

0

RECOMMENDED OPERATING CONDITIONS

Table 17.

Parameter

Symbol

T_A

V_DD1, V_DD2

Value

Operating Temperature Range

Supply Voltage Range¹

Input Signal Rise and Fall Times

−40°C to +125°C

3.0 V to 5.5 V

1.0 ms

¹See the DC Correctness and Magnetic Field Immunity section for information

on the immunity to the external magnetic fields.

0

50

100

150

AMBIENT TEMPERATURE (°C)

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN V VDE V 0884-10

Rev. A | Page 12 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 19. Maximum Continuous Working Voltage¹

Parameter

Value

Constraint

Table 18.

Parameter

60 Hz AC Voltage

400 V rms

20-year lifetime at

0.1% failure rate, zero

average voltage

Limited by the

creepage of the

package,

Rating

Storage Temperature (T_ST) Range

Ambient Operating Temperature (T_A) −40°C to +125°C

Range

−65°C to +150°C

DC Voltage

1173 V peak

Supply Voltages (V_DD1, V_DD2

)

−0.5 V to +7.0 V

Input Voltages (V_IA, V_IB, V_IC, MCLK, MO, −0.5 V to V_DDx+ 0.5 V

SO, MSS)

Pollution Degree 2,

Material Group II^{2, 3}

Output Voltages (SCLK, SSS, MI, SI,

V_OA, V_OB, V_OC)

Average Current per Output Pin¹

Common-Mode Transients²

−0.5 V to V_DDx+ 0.5 V

¹See the Insulation Lifetime section for more details.

²Other pollution degree and material group requirements yield a different limit.

³Some system level standards allow components to use the printed wiring

board (PWB) creepage values. The supported dc voltage may be higher for

those standards.

−10 mA to +10 mA

−100 kV/µs to +100 kV/µs

¹See Figure 4 for maximum safety rated current values across temperature.

²Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up

or permanent damage.

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. A | Page 13 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

2

3

4

5

6

7

8

9

V

20

19

18

17

16

15

14

13

12

11

DD1

GND

DD2

GND

1

2

MCLK

MO

SCLK

SI

ADuM4151

TOP VIEW

(Not to Scale)

MI

SO

MSS

SSS

V

IA

OA

V

IB

OB

V

OC

IC

GND 10

GND

2

1

Figure 5. ADuM4151 Pin Configuration

Table 20. ADuM4151 Pin Function Descriptions

Pin No. Mnemonic Direction Description

1

V_DD1

Power

Input Power Supply for Isolator Side 1. A bypass capacitor from V_DD1to GND₁to local ground is

required.

2, 10

GND₁

MCLK

MO

MI

MSS

Return

Clock

Input

Output

Input

Ground 1. Ground reference for Isolator Side 1.

SPI Clock from the Master Controller.

SPI Data from the Master to the Slave MO/SI Line.

SPI Data from the Slave to the Master MI/SO Line.

Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns

setup time from the next clock or data edge.

3

4

5

6

7

V_IA

Input

Low Speed Data Input A.

8

V_IB

Input

Low Speed Data Input B.

9

V_OC

GND2

V_IC

V_OB

V_OA

SSS

SO

SI

SCLK

V_DD2

Output

Return

Input

Output

Input

Output

Power

Low Speed Data Output C.

Ground 2. Ground reference for Isolator Side 2.

Low Speed Data Input C.

Low Speed Data Output B.

Low Speed Data Output A.

Slave Select to the Slave. This signal uses an active low logic.

SPI Data from the Slave to the Master MI/SO Line.

SPI Data from the Master to the Slave MO/SI Line.

SPI Clock from the Master Controller.

Input Power Supply for Isolator Side 2. A bypass capacitor from V_DD2to GND₂to local ground is

required.

11, 19

12

13

14

15

16

17

18

20

Rev. A | Page 14 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

V

1

2

3

4

5

6

7

8

9

V

20

19

18

17

16

15

14

13

12

11

DD1

GND

DD2

GND

1

2

MCLK

MO

SCLK

SI

ADuM4152

MI

SO

TOP VIEW

(Not to Scale)

MSS

SSS

V

IA

OA

V

OB

IB

V

OC

IC

GND 10

GND

2

1

Figure 6. ADuM4152 Pin Configuration

Table 21. ADuM4152 Pin Function Descriptions

Pin No. Mnemonic Direction Description

1

2, 10

3

4

5

6

V_DD1

GND₁

MCLK

MO

MI

MSS

Power

Return

Clock

Input

Output

Input

Input Power Supply for Isolator Side 1. A bypass capacitor from V_DD1to GND₁to local ground is required.

Ground 1. Ground reference for Isolator Side 1.

SPI Clock from the Master Controller.

SPI Data from the Master to the Slave MO/SI Line.

SPI Data from the Slave to the Master MI/SO Line.

Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns

setup time from the next clock or data edge.

7

V_IA

Input

Low Speed Data Input A.

8

9

V_OB

V_OC

GND₂

V_IC

Output

Return

Input

Low Speed Data Output B.

Low Speed Data Output C.

Ground 2. Ground reference for Isolator Side 2.

Low Speed Data Input C.

Low Speed Data Input B.

11, 19

12

13

14

15

16

17

18

20

V_IB

Input

V_OA

SSS

SO

SI

SCLK

V_DD2

Output

Input

Output

Power

Low Speed Data Output A.

Slave Select to the Slave. This signal uses an active low logic.

SPI Data from the Slave to the Master MI/SO Line.

SPI Data from the Master to the Slave MO/SI Line.

SPI Clock from the Master Controller.

Input Power Supply for Isolator Side 2. A bypass capacitor from V_DD2to GND₂to local ground is required.

Rev. A | Page 15 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

V

1

2

3

4

5

6

7

8

9

V

20

19

18

17

16

15

14

13

12

11

DD1

GND

DD2

GND

1

2

MCLK

MO

SCLK

SI

ADuM4153

TOP VIEW

(Not to Scale)

MI

SO

MSS

SSS

V

OA

IA

V

OB

IB

V

OC

IC

GND 10

GND

2

1

Figure 7. ADuM4153 Pin Configuration

Table 22. ADuM4153 Pin Function Descriptions

Pin No. Mnemonic Direction Description

1

2, 10

3

4

5

6

V_DD1

GND₁

MCLK

MO

MI

MSS

Power

Return

Clock

Input

Output

Input

Input Power Supply for Isolator Side 1. A bypass capacitor from V_DD1to GND₁to local ground is required.

Ground 1. Ground reference for Isolator Side 1.

SPI Clock from the Master Controller.

SPI Data from the Master to the Slave MO/SI Line

SPI Data from the Slave to the Master MI/SO Line.

Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns

setup time from the next clock or data edge.

7

8

9

V_OA

V_OB

V_OC

GND₂

V_IC

V_IB

V_IA

SSS

SO

SI

Output

Return

Input

Low Speed Data Output A.

Low Speed Data Output B.

Low Speed Data Output C.

Ground 1. Ground reference for Isolator Side 2.

Low Speed Data Input C.

Low Speed Data Input B.

Low Speed Data Input A.

Slave Select to the Slave. This signal uses an active low logic.

SPI Data from the Slave to the Master MI/SO Line.

SPI Data from the Master to the Slave MO/SI Line.

SPI Clock from the Master Controller.

11, 19

12

13

14

15

16

17

18

20

Input

Output

Input

Output

Power

SCLK

V_DD2

Input Power Supply for Isolator Side 2. A bypass capacitor from V_DD2to GND₂to local ground is required.

Table 23. ADuM4151/ADuM4152/ADuM4153 Power-Off Default State Truth Table (Positive Logic)¹

V_DD1State

V_DD2State

Side 1 Outputs Side 2 Outputs

Comments

SSS

Unpowered Powered

Z

Outputs on an unpowered side are high impedance within

one diode drop of ground

Powered

Unpowered

Z

Outputs on an unpowered side are high impedance within one

diode drop of ground

¹Z is high impedance.

Rev. A | Page 16 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

TYPICAL PERFORMANCE CHARACTERISTICS

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

7

6

5

5.0V

3.3V

5.0V

3.3V

4

3

2

1

0

20

40

60

80

0

20

40

DATA RATE (Mbps)

60

80

DATA RATE (Mbps)

Figure 11. Typical Dynamic Supply Current per Output Channel vs. Data Rate

for 5.0 V and 3.3 V Operation

Figure 8. Typical Dynamic Supply Current per Input Channel vs. Data Rate

for 5.0 V and 3.3 V Operation

25

30

25

20

5.0V

20

5.0V

15

3.3V

15

10

5

10

5

0

20

40

60

80

0

20

40

60

80

DATA RATE (Mbps)

Figure 12. Typical I_DD2Supply Current vs. Data Rate for

5.0 V and 3.3 V Operation

Figure 9. Typical I_DD1Supply Current vs. Data Rate for

5.0 V and 3.3 V Operation

25

20

15

10

5

16

14

12

10

8

3.3V

5.0V

3.3V

5.0V

6

4

2

0

–40

10

60

110

–40

10

60

110

AMBIENT TEMPERATURE (°C)

Figure 13. Typical Propagation Delay vs. Ambient Temperature for High

Speed Channels with Glitch Filter (See the High Speed Channels Section)

Figure 10. Typical Propagation Delay vs. Ambient Temperature for High

Speed Channels Without Glitch Filter (See the High Speed Channels Section)

Rev. A | Page 17 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

APPLICATIONS INFORMATION

prevents short pulses from propagating to the output or causing

INTRODUCTION

other errors in operation. The

signal requires a 10 ns setup

MSS

The ADuM4151/ADuM4152/ADuM4153 are a family of devices

created to optimize isolation of SPI for speed and to provide

additional low speed channels for control and status monitoring

functions. The isolators are based on differential signaling

iCoupler technology for enhanced speed and noise immunity.

time in the B grade devices prior to the first active clock edge to

allow the added propagation time of the glitch filter.

Low Speed Data Channels

The low speed data channels are provided as economical

isolated datapaths where timing is not critical. The dc value of

all high and low speed inputs on a given side of the devices are

sampled simultaneously, packetized and shifted across an

isolation coil. The high speed channels are compared for dc

accuracy, and the low speed data is transferred to the appropriate

low speed outputs. The process is then reversed by reading the

inputs on the opposite side of the devices, packetizing them and

sending them back for similar processing. The dc correctness data

for the high speed channels is handled internally, and the low

speed data is clocked to the outputs simultaneously.

High Speed Channels

The ADuM4151/ADuM4152/ADuM4153 have four high speed

channels. The first three channels, CLK, MI/SO, and MO/SI

(the slash indicates the connection of the particular input and

output channel across the isolator), are optimized for either low

propagation delay in the B grade or high noise immunity in the

A grade. The difference between the grades is the addition of a

glitch filter to these three channels in the A grade version,

which increases the propagation delay. The B grade version,

with a maximum propagation delay of 14 ns, supports a

maximum clock rate of 17 MHz in the standard 4-wire SPI.

However, because the glitch filter is not present in the B grade

version, ensure that spurious glitches of less than 10 ns are not

present.

A free running internal clock regulates this bidirectional data

shuttling. Because data is sampled at discrete times based on

this clock, the propagation delay for a low speed channel is

between 0.1 µs and 2.6 µs, depending on where the input data

edge changes with respect to the internal sample clock.

Glitches of less than 10 ns in the B grade devices can cause the

missing of the second edge of the glitch. This pulse condition is

then seen as a spurious data transition on the output that is

corrected by a refresh or the next valid data edge. It is recommended

to use the A grade devices in noisy environments.

Figure 14 illustrates the behavior of the low speed channels and

the relationship between the codirectional channels.

•

Point A: When data is sampled between the input edges of

two low speed data inputs, a very narrow gap between

edges is increased to the width of the output clock.

Point B: Data edges that occur on codirectional channels

between samples are sampled and simultaneously sent to

the outputs, which synchronizes the data edges between

the two channels at the outputs.

The relationship between the SPI signal paths and the pin

mnemonics of the ADuM4151/ADuM4152/ADuM4153 and the

data directions is detailed in Table 24.

•

Table 24. Pin Mnemonics Correspondence to the SPI Signal

Path Names

SPI Signal Path Master Side 1 Data Direction Slave Side 2

•

Point C: Data pulses that are less than the minimum low

speed pulse width may not be transmitted because they

may not be sampled.

CLK

MCLK

MO

MI

SCLK

SI

SO

→

←

→

MO/SI

MI/SO

SS

SAMPLE CLOCK

MSS

SSS

The datapaths are SPI mode agnostic. The CLK and MO/SI SPI

datapaths are optimized for propagation delay and channel to

channel matching. The MI/SO SPI datapath is optimized for

propagation delay. The devices do not synchronize to the clock

channels; therefore, there are no constraints on the clock

polarity or the timing with respect to the data lines. To allow

compatibility with nonstandard SPI interfaces, the MI pin is

always active, and does not tristate when the slave select is not

asserted. This precludes tying several MI lines together without

adding a trisate buffer or multiplexor.

INPUT A

INPUT B

A

B

A

C

B

OUTPUT A

OUTPUT B

A

C

(slave select bar) is typically an active low signal. can have

SS

OUTPUT CLOCK

many different functions in SPI and SPI like busses. Many of

Figure 14. Slow Channel Timing

these functions are edge triggered; therefore, the path contains a

SS

glitch filter in both the A grade and the B grade. The glitch filter

Rev. A | Page 18 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

The low speed data system is carefully designed so that staggered

data transitions at the inputs become either synchronized or

pushed apart when they are presented at the output. Edge order

is always preserved for as long as the edges are separated by at

least t_{VIx SKEW}. In other words, if one edge is leading another at

the input, the order of the edges is not reversed by the isolator.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent via the transformer to the decoder.

The decoder is bistable and is, therefore, either set or reset by

the pulses indicating input logic transitions. In the absence of

logic transitions at the input for more than ~1.2 µs, a periodic

set of refresh pulses indicative of the correct input state are sent

via the low speed channel to ensure dc correctness at the output.

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM4151/ADuM4152/ADuM4153 digital isolators

require no external interface circuitry for the logic interfaces.

Power supply bypassing is strongly recommended at both the

If the low speed decoder receives no pulses for more than about

5 µs, the input side is assumed to be unpowered or nonfunctional,

in which case, the isolator output is forced to a high-Z state by

the watchdog timer circuit.

V

_DD1and V_DD2supply pins (see Figure 15). The capacitor value

must be between 0.01 µF and 0.1 µF. The total lead length

between both ends of the capacitor and the input power supply

pin must not exceed 20 mm.

The limitation on the magnetic field immunity of the device is

set by the condition in which induced voltage in the transformer

receiving coil is sufficiently large to either falsely set or reset the

decoder. The following analysis defines such conditions. The

ADuM4151/ADuM4152/ADuM4153 were examined in a 3 V

operating condition because it represents the most susceptible

mode of operation for this product.

BYPASS < 10mm

V

DD2

DD1

GND

2

GND

1

SCLK

SI

MCLK

MO

ADuM4151/

ADuM4152/

ADuM4153

SO

MI

MSS

SSS

V

/V

V

/V

IA OA

OA IA

The pulses at the transformer output have an amplitude greater

than 1.5 V. The decoder has a sensing threshold of about 1.0 V;

thereby, establishing a 0.5 V margin in which induced voltages

can be tolerated. The voltage induced across the receiving coil is

given by

/V

V

/V

IB OB

V

OC

IC

GND

2

1

Figure 15. Recommended PCB Layout

In applications involving high common-mode transients, it is

important to minimize board coupling across the isolation

barrier. Furthermore, design the PCB layout so that any

coupling that does occur affects all pins equally on a given

component side. Failure to ensure this may cause voltage

differentials between pins that exceed the absolute maximum

ratings of the device, thereby leading to latch-up or permanent

damage.

2

V = (−dβ/dt)∑πr_n; n = 1, 2, …, N

where:

β is the magnetic flux density.

r_nis the radius of the n^thturn in the receiving coil.

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM4151/

ADuM4152/ADuM4153 and an imposed requirement that the

induced voltage be, at most, 50% of the 0.5 V margin at the

decoder, a maximum allowable magnetic field is calculated as

shown in Figure 17.

PROPAGATION DELAY RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The input to

output propagation delay time for a high to low transition may

differ from the propagation delay time of a low to high

transition.

100

10

1

INPUT

50%

t_PLH

t_PHL

OUTPUT

50%

0.1

Figure 16. Propagation Delay Parameters

0.01

Pulse width distortion is the maximum difference between

these two propagation delay values and an indication of how

accurately the timing of the input signal is preserved.

0.001

1k

100M

10k

100k

1M

10M

MAGNETIC FIELD FREQUENCY (Hz)

Channel to channel matching refers to the maximum amount

the propagation delay differs between channels within a single

ADuM4151/ADuM4152/ADuM4153 component.

Figure 17. Maximum Allowable External Magnetic Flux Density

Rev. A | Page 19 of 22

ADuM4151/ADuM4152/ADuM4153

Data Sheet

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.5 kgauss, induces a

voltage of 0.25 V at the receiving coil. This voltage is about 50%

of the sensing threshold and does not cause a faulty output

transition. If such an event occurs, with the worst-case polarity,

during a transmitted pulse, the interference reduces the

received pulse from >1.0 V to 0.75 V. This voltage is still well

above the 0.5 V sensing threshold of the decoder.

These quiescent currents add to the high speed current as is

shown in the following equations for the total current for each

side of the isolator. Dynamic currents are taken from Table 3

and Table 6 for the respective voltages.

For Side 1, the supply current is given by

I

_DD1= I_DDI(D)× (f_MCLK+ f_MO+ f_MSS) +

_MI× (I_DDO(D)+ ((0.5 × 10⁻³) × C_L(MI)× V_DD1)) + I_DD1(Q)

For Side 2, the supply current is given by

_DD2= I_DDI(D)× f_SO

f

The preceding magnetic flux density values correspond to

specific current magnitudes at given distances away from the

ADuM4151/ADuM4152/ADuM4153 transformers. Figure 18

expresses these allowable current magnitudes as a function of

frequency for selected distances. The ADuM4151/ADuM4152/

ADuM4153 are insensitive to external fields. Only extremely

large, high frequency currents, very close to the component are

a concern. For the 1 MHz example noted, placing a 1.2 kA

current 5 mm away from the ADuM4151/ADuM4152/

ADuM4153 affects component operation.

I

+

f

_SCLK× (I_DDO(D)+((0.5 × 10⁻³) × C_L(SCLK)× V_DD2)) +

f_SI× (I_DDO(D)+((0.5 × 10⁻³) × C_L(SI)× V_DD2)) +

f_SSS× (I_DDO(D)+((0.5 × 10⁻³) × C_{L( )}× V_DD2)) + I_DD2(Q)

SSS

where:

_DDI(D), I_DDO(D)are the input and output dynamic supply currents

I

per channel (mA/Mbps).

f_xis the logic signal data rate for the specified channel (Mbps).

C

V

I

_L(x)is the load capacitance of the specified output (pF).

_DDxis the supply voltage of the side being evaluated (V).

_DD1(Q), I_DD2(Q)are the specified Side 1 and Side 2 quiescent

1000

DISTANCE = 1m

100

supply currents (mA).

Figure 8 and Figure 11 show the typical supply current per

channel as a function of data rate for an input and unloaded

output. Figure 9 and Figure 12 show the total I_DD1and I_DD2supply

currents as a function of data rate for the ADuM4151/ADuM4152/

ADuM4153 channel configurations with all high speed channels

running at the same speed and the low speed channels at idle.

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of

insulation degradation is dependent on the characteristics of the

voltage waveform applied across the insulation as well as the

materials and material interfaces.

0.01

1k

10k

100k

1M

10M

100M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 18. Maximum Allowable Current for Various Current to

ADuM4151/ADuM4152/ADuM4153 Spacings

At combinations of strong magnetic field and high frequency,

any loops formed by the PCB traces may induce sufficiently

large error voltages to trigger the thresholds of succeeding

circuitry. Take care to avoid PCB structures that form loops.

Two types of insulation degradation are of primary interest:

breakdown along surfaces exposed to the air and insulation

wear out. Surface breakdown is the phenomenon of surface

tracking and the primary determinant of surface creepage

requirements in system level standards. Insulation wear out is

the phenomenon where charge injection or displacement

currents inside the insulation material cause long-term

insulation degradation.

POWER CONSUMPTION

The supply current at a given channel of the ADuM4151/

ADuM4152/ADuM4153 isolators is a function of the supply

voltage, the data rate of the channel, and the output load of the

channel and whether it is a high or low speed channel.

The low speed channels draw a constant quiescent current

caused by the internal ping-pong datapath. The operating

frequency is low enough that the capacitive losses caused by

the recommended capacitive load are negligible compared to

the quiescent current. The explicit calculation for the data rate

is eliminated for simplicity, and the quiescent current for each

side of the isolator due to the low speed channels can be found

in Table 3, Table 6, Table 9, and Table 12 for the particular

operating voltages.

Rev. A | Page 20 of 22

Data Sheet

ADuM4151/ADuM4152/ADuM4153

Surface Tracking

Calculation and Use of Parameters Example

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working

voltage, the environmental conditions, and the properties of the

insulation material. Safety agencies perform characterization

testing on the surface insulation of components that allow the

components to be categorized into different material groups.

Lower material group ratings are more resistant to surface

tracking and, therefore, can provide adequate lifetime with

smaller creepage. The minimum creepage for a given working

voltage and material group is in each system level standard and

is based on the total rms voltage across the isolation, pollution

degree, and material group. The material group and creepage

for the ADuM4151/ADuM4152/ADuM4153 isolators are

detailed in Table 15.

The following is an example that frequently arises in power

conversion applications. Assume that the line voltage on one

side of the isolation is 240 V ac rms, and a 400 V dc bus voltage

is present on the other side of the isolation barrier. The isolator

material is polyimide. To establish the critical voltages in

determining the creepage clearance and lifetime of a device, see

Figure 19 and the following equations.

V

AC RMS

V

DC

PEAK

RMS

Insulation Wear Out

The lifetime of insulation due to wear out is determined by its

thickness, the material properties, and the voltage stress applied.

It is important to verify that the product lifetime is adequate at

the application working voltage. The working voltage supported

by an isolator for wear out may not be the same as the working

voltage supported for tracking. It is the working voltage

TIME

Figure 19. Critical Voltage Example

The working voltage across the barrier from Equation 1 is

2

applicable to tracking that is specified in most standards.

V_RMS V_{AC RMS}²V_DC

Testing and modeling have shown that the primary driver of

long-term degradation is displacement current in the polyimide

insulation causing incremental damage. The stress on the

insulation can be broken down into broad categories, such as

dc stress, which causes very little wear out because there is no

displacement current, and an ac component time varying

voltage stress, which causes wear out.

V_RMS 240² 400²

V

_RMS= 466 V

The 466 V rms is the working voltage used together with the

material group and pollution degree when looking up the

creepage required by a system standard.

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. The ac rms voltage can be

obtained from Equation 2.

The ratings in certification documents are usually based on 60 Hz

sinusoidal stress because this stress reflects isolation from line

voltage. However, many practical applications have combinations

of 60 Hz ac and dc across the barrier, as shown in Equation 1.

Because only the ac portion of the stress causes wear out, the

equation can be rearranged to solve for the ac rms voltage, as

shown in Equation 2. For insulation wear out with the

polyimide materials used in this product, the ac rms voltage

determines the product lifetime.

V_{AC RMS} V_RMS²V_DC

2

V

_{AC RMS} 466² 400²

_{AC RMS}= 240 V

V

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the waveform is

not sinusoidal. The value is compared to the limits for the working

voltage listed in Table 19 for the expected lifetime, less than a 60 Hz

sine wave, and it is well within the limit for a 50-year service life.

2

V_RMS V_{AC RMS}²V_DC

(1)

or

2

V_{AC RMS} V_RMS²V_DC

(2)

Note that the dc working voltage limit in Table 19 is set by the

creepage of the package as specified in IEC 60664-1. This value

may differ for specific system level standards

where:

V

_{AC RMS}is the time varying portion of the working voltage.

_RMSis the total rms working voltage.

_DCis the dc offset of the working voltage.

Rev. A | Page 21 of 22

ADuM4151/ADuM4152/ADuM4153

OUTLINE DIMENSIONS

Data Sheet

15.40

15.30

15.20

1.93 REF

20

11

10

7.60

7.50

7.40

10.51

10.31

10.11

1

PIN 1

MARK

0.71

0.50 45°

0.31

0.25 BSC

2.64

2.54

2.44

2.24

GAGE

0.32

0.23

PLANE

0.30

0.20

0.10

SEATING

PLANE

8°

0°

1.27 BSC

1.01

0.76

0.51

0.46

0.36

COPLANARITY

0.1

COMPLIANT TO JEDEC STANDARDS MS-013

Figure 20. 20-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]

Wide Body

(RI-20-1)

Dimension shown in millimeters

ORDERING GUIDE

No. of

Inputs,

_DD1Side V_DD2Side (MHz)

Maximum Maximum

Data Rate Propagation

Isolation

Rating

Inputs,

Temperature

Range

Package

Description

Package

Option

Model^{1, 2, 3}

V

5

Delay, 5 V (ns) (V ac)

ADuM4151ARIZ

ADuM4151ARIZ-RL

2

1

25

5000

−40°C to +125°C 20-Lead SOIC_IC

RI-20-1

−40°C to +125°C 20-Lead SOIC_IC, RI-20-1

13”Tape and Reel

ADuM4151BRIZ

ADuM4151BRIZ-RL

5

2

17

14

5000

−40°C to +125°C 20-Lead SOIC_IC

−40°C to +125°C 20-Lead SOIC_IC, RI-20-1

13”Tape and Reel

RI-20-1

ADuM4152ARIZ

ADuM4152ARIZ-RL

4

3

1

25

5000

−40°C to +125°C 20-Lead SOIC_IC

−40°C to +125°C 20-Lead SOIC_IC, RI-20-1

13”Tape and Reel

RI-20-1

ADuM4152BRIZ

ADuM4152BRIZ-RL

4

3

17

14

5000

−40°C to +125°C 20-Lead SOIC_IC

−40°C to +125°C 20-Lead SOIC_IC, RI-20-1

13”Tape and Reel

RI-20-1

ADuM4153ARIZ

ADuM4153ARIZ-RL

3

4

1

25

5000

−40°C to +125°C 20-Lead SOIC_IC

−40°C to +125°C 20-Lead SOIC_IC, RI-20-1

13”Tape and Reel

RI-20-1

ADuM4153BRIZ

ADuM4153BRIZ-RL

3

4

17

14

5000

−40°C to +125°C 20-Lead SOIC_IC

−40°C to +125°C 20-Lead SOIC_IC, RI-20-1

13”Tape and Reel

RI-20-1

EVAL-ADuM3151Z

Evaluation Board

¹Z = RoHS Compliant Part.

²The EVAL-ADuM3151Z uses a functionally equivalent device for evaluation. The pad layout on the EVAL-ADuM3151Z board does not support the 20-lead SOIC_IC package.

³To evaluate the functionality of the alternative low speed channel configurations of the ADuM4152 and the ADuM4153, the user must purchase an ADuM3152 or an

ADuM3153 and replace the component on the EVAL-ADuM3151Z evaluation board.

registered trademarks are the property of their respective owners.

D12370-0-3/15(A)

Rev. A | Page 22 of 22


型号：	ADuM4152ARIZ-RL
厂家：	ADI
描述：	5 kV, 7-Channel, SPIsolator Digital Isolators for SPI
文件：	总22页 (文件大小：447K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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