AMP01BX [ADI]
Low Noise, Precision Instrumentation Amplifier; 低噪声，精密仪表放大器
| 型号： | AMP01BX |
| 厂家： | 
ADI |
| 描述： | Low Noise, Precision Instrumentation Amplifier |
| 文件： | 总22页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, Precision
a
Instrumentation Amplifier
AMP01*
PIN CONFIGURATIONS
18-Lead Cerdip
FEATURES
Low Offset Voltage: 50 V Max
Very Low Offset Voltage Drift: 0.3 V/؇C Max
Low Noise: 0.12 V p-p (0.1 Hz to 10 Hz)
Excellent Output Drive: ؎10 V at ؎50 mA
Capacitive Load Stability: to 1 F
Gain Range: 0.1 to 10,000
Excellent Linearity: 16-Bit at G = 1000
High CMR: 125 dB min (G = 1000)
Low Bias Current: 4 nA Max
R
R
1
2
3
4
5
6
7
8
9
18 +IN
G
17
16
15
14
13
12
11
10
V
NULL
NULL
G
IOS
IOS
–IN
NULL
NULL
V
V
V
R
R
OOS
S
OOS
S
TEST PIN*
SENSE
+V
OP
V+
V–
May Be Configured as a Precision Op Amp
Output-Stage Thermal Shutdown
Available in Die Form
REFERENCE
OUTPUT
–V
OP
AMP01
TOP VIEW
(Not to Scale)
GENERAL DESCRIPTION
The AMP01 is a monolithic instrumentation amplifier designed
for high-precision data acquisition and instrumentation applica-
tions. The design combines the conventional features of an
instrumentation amplifier with a high current output stage. The
output remains stable with high capacitance loads (1 µF), a
unique ability for an instrumentation amplifier. Consequently,
the AMP01 can amplify low level signals for transmission
through long cables without requiring an output buffer. The output
stage may be configured as a voltage or current generator.
*MAKE NO ELECTRICAL CONNECTION
AMP01 BTC/883
28-Terminal LCC
4
3
2
1
28 27 26
25
V
NULL
NC
NULL
NC
5
6
7
8
9
IOS
Input offset voltage is very low (20 µV), which generally elimi-
nates the external null potentiometer. Temperature changes
have minimal effect on offset; TCVIOS is typically 0.15 µV/°C.
Excellent low-frequency noise performance is achieved with a
minimal compromise on input protection. Bias current is very
low, less than 10 nA over the military temperature range. High
common-mode rejection of 130 dB, 16-bit linearity at a gain of
1000, and 50 mA peak output current are achievable simulta-
neously. This combination takes the instrumentation amplifier
one step further towards the ideal amplifier.
V
V
24 NC
23
OOS
R
R
S
S
AMP01
TOP VIEW
(Not to Scale)
22
21
20
19
NULL
NC
OOS
+V
OP
TEST PIN* 10
NC
V+
11
NC
12
13 14 15 16 17 18
NC = NO CONNECT
*MAKE NO ELECTRICAL CONNECTION
AC performance complements the superb dc specifications. The
AMP01 slews at 4.5 V/µs into capacitive loads of up to 15 nF,
settles in 50 µs to 0.01% at a gain of 1000, and boasts a healthy
26 MHz gain-bandwidth product. These features make the
AMP01 ideal for high speed data acquisition systems.
20-Lead SOIC
20
19
18
17
16
15
14
13
12
11
R
G
R
1
2
G
TEST PIN*
+IN
TEST PIN*
–IN
Gain is set by the ratio of two external resistors over a range of
0.1 to 10,000. A very low gain temperature coefficient of
10 ppm/°C is achievable over the whole gain range. Output
voltage swing is guaranteed with three load resistances; 50 Ω,
500 Ω, and 2 kΩ. Loaded with 500 Ω, the output delivers
±13.0 V minimum. A thermal shutdown circuit prevents de-
struction of the output transistors during overload conditions.
3
4
V
V
NULL
NULL
V
NULL
NULL
IOS
IOS
OOS
OOS
5
V
AMP01
TOP VIEW
(Not to Scale)
6
TEST PIN*
SENSE
R
R
S
S
7
REFERENCE
OUTPUT
8
+V
V+
V–
OP
9
The AMP01 can also be configured as a high performance op-
erational amplifier. In many applications, the AMP01 can be
used in place of op amp/power-buffer combinations.
–V
OP
10
*MAKE NO ELECTRICAL CONNECTION
REV. D
*Protected under U.S. Patent Numbers 4,471,321 and 4,503,381.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AMP01–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = ؎15 V, RS = 10 k⍀, RL = 2 k⍀, TA = +25؇C, unless otherwise noted)
AMP01A
Min Typ Max
AMP01B
Min Typ Max
Parameter
Symbol
Conditions
Units
OFFSET VOLTAGE
Input Offset Voltage
VIOS
TA = +25°C
20
40
50
80
40
60
0.3
2
100
150
1.0
6
µV
µV
µV/°C
mV
mV
–55°C ≤ TA ≤ +125°C
–55°C ≤ TA ≤ +125°C
TA = +25°C
Input Offset Voltage Drift
Output Offset Voltage
TCVIOS
VOOS
0.15 0.3
1
3
3
6
–55°C ≤ TA ≤ +125°C
6
10
Output Offset Voltage Drift
TCVOOS
PSR
RG = ∞
–55°C ≤ TA ≤ +125°C
G = 1000
20
50
50
120
µV/°C
dB
dB
dB
dB
Offset Referred to Input
vs. Positive Supply
V+ = +5 V to +15 V
120
110
95
130
130
110
90
110
100
90
120
120
100
80
G = 100
G = 10
G = 1
75
70
–55°C ≤ TA ≤ +125°C
G = 1000
G = 100
G = 10
G = 1
G = 1000
G = 100
G = 10
120
110
95
75
105
90
130
130
110
90
125
105
85
110
100
90
70
105
90
120
120
100
80
115
95
dB
dB
dB
dB
dB
dB
dB
dB
Offset Referred to Input
vs. Negative Supply
V– = –5 V to –15 V
PSR
70
50
70
50
75
60
G = 1
65
–55°C ≤ TA ≤ +125°C
G = 1000
G = 100
G = 10
G = 1
105
90
70
125
105
85
105
90
70
115
95
75
dB
dB
dB
dB
50
85
50
60
Input Offset Voltage Trim
Range
Output Offset Voltage Trim
Range
VS = ±4.5 V to ±18 V1
VS = ±4.5 V to ±18 V1
±6
±6
mV
mV
±100
±100
INPUT CURRENT
Input Bias Current
IB
TA = +25°C
1
4
40
0.2
0.5
3
4
10
2
6
50
0.5
1.0
5
6
15
nA
nA
pA/°C
nA
nA
–55°C ≤ TA ≤ +125°C
–55°C ≤ TA ≤ +125°C
TA = +25°C
–55°C ≤ TA ≤ +125°C
–55°C ≤ TA ≤ +125°C
Input Bias Current Drift
Input Offset Current
TCIB
IOS
1.0
3.0
2.0
6.0
Input Offset Current Drift
TCIOS
RIN
pA/°C
INPUT
Input Resistance
Differential, G = 1000
Differential, G ≤ 100
Common Mode, G = 1000
TA = +25°C2
–55°C ≤ TA ≤ +125°C
VCM = ±10 V, 1 kΩ
Source Imbalance
G = 1000
1
10
20
1
10
20
GΩ
GΩ
GΩ
V
Input Voltage Range
IVR
±10.5
±10.0
±10.5
±10.0
V
Common-Mode Rejection
CMR
125
120
100
85
130
130
120
100
115
110
95
125
125
110
90
dB
dB
dB
dB
G = 100
G = 10
G = 1
75
–55°C ≤ TA ≤ +125°C
G = 1000
G = 100
G = 10
G = 1
120
115
95
125
125
115
95
110
105
90
120
120
105
90
dB
dB
dB
dB
80
75
NOTES
1VIOS and VOOS nulling has minimal affect on TCVIOS and TCVOOS respectively.
2Refer to section on common-mode rejection.
Specifications subject to change without notice.
–2–
REV. D
AMP01
(@ VS = ؎15 V, RS = 10 k⍀, RL = 2 k⍀, TA = +25؇C, –25؇C ≤ TA ≤ +85؇C for E, F
grades, 0؇C ≤ TA ≤ +70؇C for G grade, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
AMP01E
Min Typ Max
AMP01F/G
Min Typ Max
Parameter
Symbol
Conditions
Units
OFFSET VOLTAGE
Input Offset Voltage
VIOS
TA = +25°C
20
40
50
80
40
60
0.3
2
100
150
1.0
6
µV
µV
µV/°C
mV
mV
TMIN ≤ TA ≤ TMAX
TMIN ≤ TA ≤ TMAX
TA = +25°C
1
Input Offset Voltage Drift
Output Offset Voltage
TCVIOS
VOOS
0.15 0.3
1
3
3
6
TMIN ≤ TA ≤ TMAX
6
10
1
Output Offset Voltage Drift
TCVOOS
PSR
RG = ∞
TMIN ≤ TA ≤ TMAX
G = 1000
G = 100
20
100
50
120
µV/°C
dB
dB
dB
dB
Offset Referred to Input
vs. Positive Supply
V+ = +5 V to +15 V
120
110
95
130
130
110
90
110
100
90
120
120
100
80
G = 10
G = 1
75
70
TMIN ≤ TA ≤ TMAX
G = 1000
G = 100
G = 10
120
110
95
75
110
95
130
130
110
90
125
105
85
110
100
90
70
105
90
120
120
100
80
115
95
dB
dB
dB
dB
dB
dB
dB
dB
G = 1
Offset Referred to Input
vs. Negative Supply
V– = –5 V to –15 V
PSR
G = 1000
G = 100
G = 10
75
55
70
50
75
60
G = 1
65
TMIN ≤ TA ≤ TMAX
G = 1000
G = 100
G = 10
G = 1
110
95
75
125
105
85
105
90
70
115
95
75
dB
dB
dB
dB
55
85
50
60
Input Offset Voltage Trim
Range
Output Offset Voltage Trim
Range
VS = ±4.5 V to ±18 V2
VS = ±4.5 V to ±18 V2
±6
±6
mV
mV
±100
±100
INPUT CURRENT
Input Bias Current
IB
TA = +25°C
1
4
40
0.2
0.5
3
4
10
2
6
50
0.5
1.0
5
6
15
mV
mV
pA/°C
mV
mV
TMIN ≤ TA ≤ TMAX
TMIN ≤ TA ≤ TMAX
TA = +25°C
TMIN ≤ TA ≤ TMAX
TMIN ≤ TA ≤ TMAX
Input Bias Current Drift
Input Offset Current
TCIB
IOS
1.0
3.0
2.0
6.0
Input Offset Current Drift
TCIOS
RIN
pA/°C
INPUT
Input Resistance
Differential, G = 1000
Differential, G ≤ 100
Common Mode, G = 1000
TA = +25°C3
TMIN ≤ TA ≤ TMAX
VCM = ±10 V, 1 kΩ
Source Imbalance
G = 1000
1
10
20
1
10
20
GΩ
GΩ
GΩ
V
Input Voltage Range
IVR
±10.5
±10.0
±10.5
±10.0
V
Common-Mode Rejection
CMR
125
120
100
85
130
130
120
100
115
110
95
125
125
110
90
dB
dB
dB
dB
G = 100
G = 10
G = 1
75
TMIN ≤ TA ≤ TMAX
G = 1000
G = 100
G = 10
G = 1
120
115
95
125
125
115
95
110
105
90
120
120
105
90
dB
dB
dB
dB
80
75
NOTES
1Sample tested.
2VIOS and VOOS nulling has minimal affect on TCVIOS and TCVOOS, respectively.
3Refer to section on common-mode rejection.
Specifications subject to change without notice.
REV. D
–3–
AMP01
ELECTRICAL CHARACTERISTICS (@ VS = ؎15 V, RS = 10 k⍀, RL = 2 k⍀, TA = +25؇C, unless otherwise noted)
AMP01A/E
Min Typ Max
AMP01B/F/G
Min Typ Max
Parameter
Symbol Conditions
Units
GAIN
20 × RS
RG
Gain Equation Accuracy
G =
0.3
0.6
0.5
0.8
%
Accuracy Measured
from G = 1 to 1000
Gain Range
Nonlinearity
G
0.1
10k
0.0007 0.005
0.005
0.1
10k
0.0007 0.005
0.005
V/V
%
%
%
%
G = 10001
G = 1001
G = 101
0.005
0.010
10
0.007
0.015
15
G = 11
Temperature Coefficient
GTC
1 ≤ G ≤ 10001, 2
5
5
ppm°C
OUTPUT RATING
Output Voltage Swing
VOUT
RL = 2 kΩ
RL = 500 Ω
RL = 50 Ω
±13.0 ±13.8
±13.0 ±13.5
±2.5 ±4.0
±12.0 ±13.8
±12.0 ±13.5
±13.0 ±13.8
±13.0 ±13.5
±2.5 ±4.0
±12.0 ±13.8
±12.0 ±13.5
V
V
V
V
RL = 2 kΩ Over Temp.
RL = 500 Ω3
V
Positive Current Limit
Negative Current Limit
Capacitive Load Stability
Output-to-Ground Short
Output-to-Ground Short
1 ≤ G ≤ 1000
60
60
100
90
120
120
60
60
100
90
120
120
mA
mA
No Oscillations1
0.1
1
0.1
1
µF
°C
Thermal Shutdown
Temperature
Junction Temperature
165
165
NOISE
Voltage Density, RTI
en
en
en
en
en
fO = 1 kHz
G = 1000
G = 100
G = 10
G = 1
5
10
59
540
0.15
5
10
59
540
0.15
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
Noise Current Density, RTI in
fO = 1 kHz, G = 1000
0.1 Hz to 10 Hz
G = 1000
G = 100
G = 10
Input Noise Voltage
en p-p
en p-p
en p-p
en p-p
en p-p
in p-p
0.12
0.16
1.4
13
0.12
0.16
1.4
13
µV p-p
µV p-p
µV p-p
µV p-p
pA p-p
G = 1
Input Noise Current
0.1 Hz to 10 Hz, G = 1000
2
2
DYNAMIC RESPONSE
Small-Signal
G = 1
G = 10
G = 100
G = 1000
G = 10
To 0.01%, 20 V step
G = 1
G = 10
G = 100
G = 1000
570
100
82
26
4.5
570
100
82
26
4.5
kHz
kHz
kHz
kHz
V/µs
Bandwidth (–3 dB)
BW
Slew Rate
Settling Time
SR
tS
3.5
3.0
12
13
15
50
12
13
15
50
µs
µs
µs
µs
NOTES
1Guaranteed by design.
2Gain tempco does not include the effects of gain and scale resistor tempco match.
3–55°C ≤ TA ≤ +125°C for A/B grades, –25°C ≤ TA ≤ +85°C for E/F grades, 0°C ≤ TA ≤ 70°C for G grades.
Specifications subject to change without notice.
REV. D
–4–
AMP01
ELECTRICAL CHARACTERISTICS (@ VS = ؎15 V, RS = 10 k⍀, RL = 2 k⍀, TA = +25؇C, unless otherwise noted)
AMP01A/E
AMP01B/F/G
Parameter
Symbol Conditions
Min Typ Max
Min Typ Max
Units
SENSE INPUT
Input Resistance
Input Current
Voltage Range
RIN
IIN
35
50
280
65
35
50
280
65
kΩ
µA
V
Referenced to V–
(Note 1)
–10.5
+15
–10.5
+15
REFERENCE INPUT
Input Resistance
Input Current
RIN
IIN
35
50
280
65
35
50
280
65
kΩ
µA
V
Referenced to V–
(Note 1)
Voltage Range
–10.5
+15
–10.5
+15
Gain to Output
1
1
V/V
POWER SUPPLY –25°C ≤ TA ≤ +85°C for E/F Grades, –55°C ≤ TA ≤ +125°C for A/B Grades
Supply Voltage Range
VS
VS
IQ
+V linked to +VOP
–V linked to –VOP
+V linked to +VOP
–V linked to –VOP
±4.5
±4.5
±18
±18
4.8
±4.5
±4.5
±18
±18
4.8
V
V
mA
mA
Quiescent Current
3.0
3.4
3.0
3.4
IQ
4.8
4.8
NOTE
1Guaranteed by design.
Specifications subject to change without notice.
ORDERING GUIDE
Temperature Range Package Description Package Option
Model
AMP01AX
AMP01AX/883C
AMP01BTC/883C –55°C to +125°C
AMP01BX
AMP01BX/883C
AMP01EX
AMP01FX
AMP01GBC
AMP01GS
AMP01GS-REEL
AMP01NBC
–55°C to +125°C
–55°C to +125°C
18-Lead Cerdip
18-Lead Cerdip
28-Terminal LCC
18-Lead Cerdip
18-Lead Cerdip
18-Lead Cerdip
18-Lead Cerdip
Die
Q-18
Q-18
E-28A
Q-18
Q-18
Q-18
Q-18
–55°C to +125°C
–55°C to +125°C
–25°C to +85°C
–25°C to +85°C
0°C to +70°C
0°C to +70°C
20-Lead SOIC
13" Tape and Reel
Die
R-20
R-20
5962-8863001VA* –55°C to +125°C
5962-88630023A* –55°C to +125°C
5962-8863002VA* –55°C to +125°C
18-Lead Cerdip
28-Terminal LCC
18-Lead Cerdip
Q-18
E-28A
Q-18
*Standard military drawing available.
DICE CHARACTERISTICS
Die Size 0.111 × 0.149 inch, 16,539 sq. mils
(2.82 × 3.78 mm, 10.67 sq. mm)
1. R
2. R
3. –INPUT
10. V– (OUTPUT)
11. V–
12. V+
13. V+ (OUTPUT)
G
G
4. V
5. V
NULL
NULL
OOS
OOS
14. R
15. R
16. V
17. V
S
S
6. TEST PIN*
7. SENSE
8. REFERENCE
9. OUTPUT
NULL
NULL
IOS
IOS
18. +INPUT
*MAKE NO ELECTRICAL CONNECTION
REV. D
–5–
AMP01
WAFER TEST LIMITS (@ VS = ؎15 V, RS = 10 k⍀, RL = 2 k⍀, TA = +25؇C, unless otherwise noted)
AMP01NBC
AMP01GBC
Limit
Parameter
Symbol Conditions
Limit
Units
Input Offset Voltage
Output Offset Voltage
Offset Referred to Input
vs. Positive Supply
VIOS
VOOS
PSR
60
4
120
8
µV max
mV max
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
nA max
nA max
V min
V+ = +5 V to +15 V
G = 1000
G = 100
G = 10
120
110
95
110
100
90
G = 1
75
70
Offset Referred to Input
vs. Negative Supply
PSR
V– = –5 V to –15 V
G = 1000
G = 100
G = 10
105
90
70
50
4
1
±10
105
90
70
50
8
3
±10
G = 1
Input Bias Current
IB
IOS
IVR
CMR
Input Offset Current
Input Voltage Range
Common Mode Rejection
Guaranteed by CMR Tests
VCM = ±10 V
G = 1000
G = 100
G = 10
dB min
dB min
dB min
dB min
dB min
125
120
100
85
115
110
95
G = 1
75
20 × RS
RG
Gain Equation Accuracy
Output Voltage Swing
G =
0.6
0.8
% max
VOUT
VOUT
VOUT
RL = 2 kΩ
RL = 500 Ω
RL = 50 Ω
Output to Ground Short
Output to Ground Short
+V Linked to +VOP
–V Linked to –VOP
±13
±13
±2.5
±60
±120
4.8
±13
±13
±2.5
±60
±120
4.8
V min
V min
V min
mA min
mA max
mA max
mA max
Output Current Limit
Output Current Limit
Quiescent Current
IQ
4.8
4.8
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
V+
V
IOS
+V
NULL
OP
A1
OUTPUT
250⍀
250⍀
–V
OP
–IN
+IN
Q1
Q2
REFERENCE
R1
47.5k⍀
R3
47.5k⍀
R
GAIN
SENSE
A2
A3
R
SCALE
R2
2.5k⍀
R4
2.5k⍀
V
NULL
OOS
V–
Figure 1. Simplified Schematic
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AMP01 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–6–
AMP01
ELECTRICAL CHARACTERISTICS (@ VS = ؎15 V, RS = 10 k⍀, RL = 2 k⍀, TA = +25؇C, unless otherwise noted)
AMP01NBC
Typical
AMP01GBC
Typical
Parameter
Symbol
Conditions
Units
Input Offset Voltage Drift
Output Offset Voltage Drift
Input Bias Current Drift
Input Offset Current Drift
Nonlinearity
TCVIOS
TCVOOS
TCIB
0.15
20
40
0.30
50
50
µV/°C
µV/°C
pA/°C
pA/°C
%
RG
=
∞
TCIOS
3
5
G = 1000
G = 1000
0.0007
0.0007
Voltage Noise Density
en
fO = 1 kHz
G = 1000
fO = 1 kHz
G = 1000
0.1 Hz to 10 Hz
G = 1000
5
5
nV/√Hz
pA/√Hz
Current Noise Density
Voltage Noise
in
0.15
0.15
en p-p
in p-p
0.12
2
0.12
2
µV p-p
pA p-p
Current Noise
0.1 Hz to 10 Hz
G = 1000
G = 10
Small-Signal Bandwidth (–3 dB) BW
26
4.5
26
4.5
kHz
V/µs
Slew Rate
SR
Settling Time
tS
To 0.01%, 20 V Step
G = 1000
50
50
µs
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. D
–7–
AMP01
–Typical Performance Characteristics
8
5
4
3
50
T
= +25؇C
A
V
= ؎15V
V
= ؎15V
S
S
40
30
20
10
0
6
4
2
1
UNIT NO.
1
2
2
0
–1
–2
0
–10
3
4
–2
–20
–30
–40
–3
–4
–6
–4
–5
0
؎5
؎10
؎15
؎20
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
POWER SUPPLY VOLTAGE – Volts
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 4. Output Offset Voltage
vs. Temperature
Figure 2. Input Offset Voltage
vs. Temperature
Figure 3. Input Offset Voltage
vs. Supply Voltage
2.0
5
2.5
2.0
1.5
1.0
0.5
0
V
= ؎15V
T = +25؇C
A
T
= +25؇C
S
A
4
3
2
1
0
1.5
1.0
0.5
0
–0.5
–1
–2
–1.0
–1.5
–0.5
–1.0
0
0
؎5
؎10
؎15
؎20
؎5
؎10
؎15
؎20
؎25
0
–75 –50 –25
25 50 75 100 125 150
POWER SUPPLY VOLTAGE – Volts
POWER SUPPLY VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 5. Output Offset Voltage
Change vs. Supply Voltage
Figure 7. Input Bias Current
vs. Supply Voltage
Figure 6. Input Bias Current
vs. Temperature
0.8
0.6
140
120
100
80
140
130
120
110
100
G = 1000
G = 100
V
= ؎15V
V
T
= ؎15V
= +25؇C
S
S
A
0.4
0.2
60
0.0
G = 10
G = 1
40
–0.2
–0.4
–0.6
V
V
T
= 2V p-p
= ؎15V
= +25؇C
CM
S
A
20
0
0
1
10
100
1k
10k
100k
–75 –50 –25
25 50 75 100 125 150
1
10
100
1k
10k
TEMPERATURE – ؇C
FREQUENCY – Hz
VOLTAGE GAIN – G
Figure 8. Input Offset Current
vs. Temperature
Figure 9. Common-Mode Rejection
vs. Voltage Gain
Figure 10. Common-Mode Rejection
vs. Frequency
REV. D
–8–
AMP01
140
120
100
80
140
120
100
80
16
14
12
10
8
G = 1000
G = 100
V
= ؎15V
= +25؇C
S
V
= 0
DM
G = 1000
T
A
V
V
= ؎15V
S
⌬V = ؎1V
S
G = 10
G = 1
G = 100
= ؎10V
= ؎5V
S
60
60
6
40
40
V
= ؎15V
= +25؇C
V
S
S
4
G = 10
T
A
⌬V = ؎1V
20
20
S
2
G = 1
1k
0
0
0
0
1
10
100
10k
100k
1
10
100
1k
10k
100k
–75 –50 –25
25 50 75 100 125 150
FREQUENCY – Hz
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 13. Negative PSR
vs. Frequency
Figure 11. Common-Mode Voltage
Range vs. Temperature
Figure 12. Positive PSR
vs. Frequency
100
10
30
25
20
18
V
R
= ؎15V
= 2k⍀
V
= ؎15V
S
V
= ؎15V
= 20mA p-p
S
S
16
14
12
L
I
OUT
G = 1000
1.0
0.1
10
8
15
10
5
G = 1
6
4
2
0
0.01
0.001
0
100
10
100
1k
10k
100k
1M
1k
10k
100k
1M
10
100
1k
10k
FREQUENCY – Hz
FREQUENCY – Hz
LOAD RESISTANCE – ⍀
Figure 15. Maximum Output Swing
vs. Frequency
Figure 16. Closed-Loop Output
Impedance vs. Frequency
Figure 14. Maximum Output Voltage
vs. Load Resistance
0.08
80
0.02
V
T
= ؎15V
= +25؇C
V
= ؎15V
= 600⍀
= 20V p-p
S
S
V
= ؎15V
S
0.07
G = 1000
G = 100
R
V
A
L
G = 100
f = 1kHz
60
40
OUT
V
= 20V p-p
0.06
0.05
0.04
0.03
0.02
0.01
0
OUT
G = 1000
G = 100
1k
G = 10
G = 1
0.01
20
0
G = 10
–20
G = 1
0
100
–40
10
100
10k
1
10
100
1k
10k
100k
1M
1k
LOAD RESISTANCE – ⍀
10k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 18. Total Harmonic Distortion
vs. Frequency
Figure 17. Closed-Loop Voltage
Gain vs. Frequency
Figure 19. Total Harmonic Distortion
vs. Load Resistance
REV. D
–9–
AMP01
6
6
5
4
70
60
50
40
30
20
10
V
= ؎15V
V
= ؎15V
V
= ؎15V
S
S
S
20V STEP
5
4
3
2
1
0
3
2
1
0
1
10
100
1k
100p
1n
10n
100n
1
1
10
100
1k
VOLTAGE GAIN – G
LOAD CAPACITANCE – F
VOLTAGE GAIN – G
Figure 20. Slew Rate vs.
Voltage Gain
Figure 21. Slew Rate vs.
Load Capacitance
Figure 22. Settling Time to 0.01%
vs. Voltage Gain
15
10
1k
100
10
8
V
= ؎15V
T = +25؇C
A
S
G = 1000
f = 1kHz
7
6
5
4
3
2
1
0
5
0
1
1
10
100
1k
10k
0
؎5
؎10
؎15
؎20
1
10
100
1k
FREQUENCY – Hz
POWER SUPPLY VOLTAGE – Volts
VOLTAGE GAIN – G
Figure 23. Voltage Noise Density
vs. Frequency
Figure 24. RTI Voltage Noise
Density vs. Gain
Figure 25. Positive Supply Current
vs. Supply Voltage
6
–8
–6
T
= +25؇C
A
V
V
= ؎15V
V
= ؎15V
S
S
–7
–6
–5
–4
–3
–2
–1
0
= V
= 0V
SENSE
REF
5
4
3
2
1
0
–5
–4
–3
–2
–1
0
0
–75 –50 –25
0
25 50 75 100 125 150
؎5
؎10
؎15
؎20
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE – ؇C
POWER SUPPLY VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 26. Negative Supply Current
vs. Supply Voltage
Figure 27. Positive Supply Current
vs. Temperature
Figure 28. Negative Supply Current
vs. Temperature
REV. D
–10–
AMP01
INPUT AND OUTPUT OFFSET VOLTAGES
GAIN
Instrumentation amplifiers have independent offset voltages
associated with the input and output stages. While the initial
offsets may be adjusted to zero, temperature variations will
cause shifts in offsets. Systems with auto-zero can correct for
offset errors, so initial adjustment would be unnecessary. How-
ever, many high-gain applications don’t have auto zero. For
these applications, both offsets can be nulled, which has mini-
mal effect on TCVIOS and TCVOOS
The AMP01 uses two external resistors for setting voltage gain
over the range 0.1 to 10,000. The magnitudes of the scale resis-
tor, RS, and gain-set resistor, RG, are related by the formula:
G = 20 × RS/RG, where G is the selected voltage gain (refer to
Figure 29).
V+
R
S
The input offset component is directly multiplied by the ampli-
fier gain, whereas output offset is independent of gain. There-
fore, at low gain, output-offset errors dominate, while at high
14
18
1
15
SENSE
+IN
–IN
13
12
11
7
9
gain, input-offset errors dominate. Overall offset voltage, VOS
referred to the output (RTO) is calculated as follows;
,
R
AMP01
G
2
3
8
OUTPUT
REFERENCE
V
OS (RTO) = (VIOS × G) + VOOS
where VIOS and VOOS are the input and output offset voltage
specifications and G is the amplifier gain. Input offset nulling
(1)
10
20
؋
R V–
S
VOLTAGE GAIN, G =
(
)
alone is recommended with amplifiers having fixed gain above
50. Output offset nulling alone is recommended when gain is
fixed at 50 or below.
R
G
Figure 29. Basic AMP01 Connections for Gains
0.1 to 10,000
In applications requiring both initial offsets to be nulled, the
input offset is nulled first by short-circuiting RG, then the output
offset is nulled with the short removed.
The magnitude of RS affects linearity and output referred errors.
Circuit performance is characterized using RS = 10 kΩ when
operating on ±15 volt supplies and driving a ±10 volt output. RS
may be reduced to 5 kΩ in many applications particularly when
operating on ±5 volt supplies or if the output voltage swing is
limited to ±5 volts. Bandwidth is improved with RS = 5 kΩ and
this also increases common-mode rejection by approximately
6 dB at low gain. Lowering the value below 5 kΩ can cause
instability in some circuit configurations and usually has no
advantage. High voltage gains between two and ten thousand
would require very low values of RG. For RS = 10 kΩ and
AV = 2000 we get RG = 100 Ω; this value is the practical lower
limit for RG. Below 100 Ω, mismatch of wirebond and resistor
temperature coefficients will introduce significant gain tempco
errors. Therefore, for gains above 2,000, RG should be kept
constant at 100 Ω and RS increased. The maximum gain of
10,000 is obtained with RS set to 50 kΩ.
The overall offset voltage drift TCVOS, referred to the output, is
a combination of input and output drift specifications. Input
offset voltage drift is multiplied by the amplifier gain, G, and
summed with the output offset drift;
TCVOS (RTO) = (TCVIOS × G) + TCVOOS
(2)
where TCVIOS is the input offset voltage drift, and TCVOOS is
the output offset voltage specification. Frequently, the amplifier
drift is referred back to the input (RTI), which is then equiva-
lent to an input signal change;
TCVOOS
TCVOS (RTI) = TCVIOS
(3)
G
For example, the maximum input-referred drift of an AMP01 EX
set to G = 1000 becomes;
100µV/°C
TCVOS (RTI ) = 0.3 µV/°C +
= 0.4 µV/°C max
Metal-film or wirewound resistors are recommended for best
results. The absolute values and TCs are not too important,
only the ratiometric parameters.
1000
INPUT BIAS AND OFFSET CURRENTS
AC amplifiers require good gain stability with temperature and
time, but dc performance is unimportant. Therefore, low cost
metal-film types with TCs of 50 ppm/°C are usually adequate
for RS and RG. Realizing the full potential of the AMP01’s offset
voltage and gain stability requires precision metal-film or wire-
wound resistors. Achieving a 15 ppm/°C gain tempco at all gains
requires RS and RG temperature coefficient matching to
5 ppm/°C or better.
Input transistor bias currents are additional error sources that
can degrade the input signal. Bias currents flowing through the
signal source resistance appear as an additional offset voltage.
Equal source resistance on both inputs of an IA will minimize
offset changes due to bias current variations with signal voltage
and temperature. However, the difference between the two bias
currents, the input offset current, produces a nontrimmable
error. The magnitude of the error is the offset current times the
source resistance.
A current path must always be provided between the differential
inputs and analog ground to ensure correct amplifier operation.
Floating inputs, such as thermocouples, should be grounded
close to the signal source for best common-mode rejection.
REV. D
–11–
AMP01
IVR is the data sheet specification for input voltage range; VOUT
is the maximum output signal; G is the chosen voltage gain. For
example, at +25°C, IVR is specified as ±10.5 volt minimum
with ±15 volt supplies. Using a ±10 volt maximum swing out-
put and substituting the figures in (4) simplifies the formula to:
1M
V
= ؎15V
S
100k
5
G
R
R
10.5 –
S
CMVR = ±
(5)
10k
1k
For all gains greater than or equal to 10, CMVR is ±10 volt
minimum; at gains below 10, CMVR is reduced.
G
ACTIVE GUARD DRIVE
Rejection of common-mode noise and line pick-up can be im-
proved by using shielded cable between the signal source and
the IA. Shielding reduces pick-up, but increases input capaci-
tance, which in turn degrades the settling-time for signal
changes. Further, any imbalance in the source resistance be-
tween the inverting and noninverting inputs, when capacitively
loaded, converts the common-mode voltage into a differential
voltage. This effect reduces the benefits of shielding. AC
common-mode rejection is improved by “bootstrapping” the
input cable capacitance to the input signal, a technique called
“guard driving.” This technique effectively reduces the input
capacitance. A single guard-driving signal is adequate at gains
above 100 and should be the average value of the two inputs.
The value of external gain resistor RG is split between two resis-
tors RG1 and RG2; the center tap provides the required signal to
drive the buffer amplifier (Figure 31).
100
1
10
100
VOLTAGE GAIN
1k
10k
Figure 30. RG and RS Selection
Gain accuracy is determined by the ratio accuracy of RS and RG
combined with the gain equation error of the AMP01 (0.6%
max for A/E grades).
All instrumentation amplifiers require attention to layout so
thermocouple effects are minimized. Thermocouples formed
between copper and dissimilar metals can easily destroy the
TCVOS performance of the AMP01 which is typically
0.15 µV/°C. Resistors themselves can generate thermoelectric
EMF’s when mounted parallel to a thermal gradient. “Vishay”
resistors are recommended because a maximum value for ther-
moelectric generation is specified. However, where thermal
gradients are low and gain TCs of 20 ppm–50 ppm are suffi-
cient, general-purpose metal-film resistors can be used for RG
and RS.
GROUNDING
The majority of instruments and data acquisition systems have
separate grounds for analog and digital signals. Analog ground
may also be divided into two or more grounds which will be tied
together at one point, usually the analog power-supply ground.
In addition, the digital and analog grounds may be joined, nor-
mally at the analog ground pin on the A-to-D converter. Fol-
lowing this basic grounding practice is essential for good circuit
performance (Figure 32).
COMMON-MODE REJECTION
Ideally, an instrumentation amplifier responds only to the dif-
ference between the two input signals and rejects common-
mode voltages and noise. In practice, there is a small change in
output voltage when both inputs experience the same common-
mode voltage change; the ratio of these voltages is called the
common-mode gain. Common-mode rejection (CMR) is the
logarithm of the ratio of differential-mode gain to common-
mode gain, expressed in dB. CMR specifications are normally
measured with a full-range input voltage change and a specified
source resistance unbalance.
Mixing grounds causes interactions between digital circuits and
the analog signals. Since the ground returns have finite resis-
tance and inductance, hundreds of millivolts can be developed
between the system ground and the data acquisition compo-
nents. Using separate ground returns minimizes the current flow
in the sensitive analog return path to the system ground point.
Consequently, noisy ground currents from logic gates do not
interact with the analog signals.
The current-feedback design used in the AMP01 inherently
yields high common-mode rejection. Unlike resistive feedback
designs, typified by the three-op-amp IA, the CMR is not de-
graded by small resistances in series with the reference input. A
slight, but trimmable, output offset voltage change results from
resistance in series with the reference input.
Inevitably, two or more circuits will be joined together with their
grounds at differential potentials. In these situations, the differ-
ential input of an instrumentation amplifier, with its high CMR,
can accurately transfer analog information from one circuit to
another.
The common-mode input voltage range, CMVR, for linear
operation may be calculated from the formula:
SENSE AND REFERENCE TERMINALS
|V OUT
2G
|
The sense terminal completes the feedback path for the instru-
mentation amplifier output stage and is normally connected
directly to the output. The output signal is specified with re-
spect to the reference terminal, which is normally connected to
analog ground.
IVR –
CMVR = ±
(4)
REV. D
–12–
AMP01
+15V
C3
0.047F
20
؋
R S
VOLTAGE GAIN, G =
R
10k⍀
(
)
S
R
*
G1
+
C1
C5
10F
A
= 500 WITH COMPONENTS SHOWN
V
0.047F
R4
NC
15
14
R
S
18
6
+IN
R
SENSE
S
+15V
13
R
200⍀
G3
*
12
V+
1
2
3
2
3
7
7
8
R
R
G
R5
*
9
6
R
400⍀
GUARD
DRIVE
G1
AMP01
OUTPUT
R
741
G2
V–
11
200⍀
G
4
V
OOS
10
NULL
5
–15V
V
IOS
–IN
*SOLDER LINK
4
NULL
17
16
*
R2
1M⍀
R1
1M⍀
REFERENCE
GROUND
VR2
100k⍀
VR1
100k⍀
R3
*
C4
0.047F
SIGNAL
GROUND
+
C6
10F
C2
0.047F
–15V
Figure 31. AMP01 Evaluation Circuit Showing Guard-Drive Connection
ANALOG
POWER SUPPLY
DIGITAL
POWER SUPPLY
+15V
0V
–15V
0V
+5V
4.7F
+
C
C
C
C
C
DIGITAL
C
C
GROUND
ANALOG
GROUND
DIGITAL
GROUND
7
8
DIGITAL
DATA
OUTPUT
9
SMP-11
SAMPLE AND HOLD
AMP01
ADC
HOLD
CAPACITOR
OUTPUT
REFERENCE
C = 0.047F CERAMIC CAPACITORS
Figure 32. Basic Grounding Practice
REV. D
–13–
AMP01
combination of these unique features in an instrumentation
amplifier allows low-level transducer signals to be conditioned
and directly transmitted through long cables in voltage or cur-
rent form. Increased output current brings increased internal
dissipation, especially with 50 Ω loads. For this reason, the
power-supply connections are split into two pairs; pins 10 and
13 connect to the output stage only and pins 11 and 12 provide
power to the input and following stages. Dual supply pins allow
dropper resistors to be connected in series with the output stage
so excess power is dissipated outside the package. Additional
decoupling is necessary between pins 10 and 13 to ground to
maintain stability when dropper resistors are used. Figure 34
shows a complete circuit for driving 50 Ω loads.
If heavy output currents are expected and the load is situated
some distance from the amplifier, voltage drops due to track or
wire resistance will cause errors. Voltage drops are particularly
troublesome when driving 50 Ω loads. Under these conditions,
the sense and reference terminals can be used to “remote sense”
the load as shown in Figure 33. This method of connection puts
the I×R drops inside the feedback loop and virtually eliminates
the error. An unbalance in the lead resistances from the sense
and reference pins does not degrade CMR, but will change the
output offset voltage. For example, a large unbalance of 3 Ω will
change the output offset by only 1 mV.
DRIVING 50 ⍀ LOADS
Output currents of 50 mA are guaranteed into loads of up to
50 Ω and 26 mA into 500 Ω. In addition, the output is stable
and free from oscillation even with a high load capacitance. The
V+
R
IN4148 DIODES ARE OPTIONAL. DIODES LIMIT THE OUTPUT
VOLTAGE EXCURSION IF SENSE AND/OR REFERENCE LINES
BECOME DISCONNECTED FROM THE LOAD.
S
*
14
18
1
15
+IN
SENSE
12
11
13
10
*
*
7
9
R
G
AMP01
REMOTE
LOAD
8
TWISTED
PAIRS
2
3
REFERENCE
–IN
OUTPUT
GROUND
V–
Figure 33. Remote Load Sensing
POWER BANDWIDTH, G = 100, 130kHz
POWER BANDWIDTH, G = 10, 200kHz
T.H.D.~0.04% @ 1kHz, 2Vrms
+15V
R1
130⍀
1W
0.047F
R
5k⍀
S
C1
0.047F
14
18
15
+IN
12
SENSE
13
10
1
7
V
OUT
9
R
G
؎3V MAX
AMP01
8
50⍀
LOAD
2
REFERENCE
11
C2
0.047F
3
–IN
R2
130⍀
1W
0.047F
20
؋
R –15V
S
VOLTAGE GAIN, G =
(
)
R
G
RESISTERS R1 AND R2 REDUCE IC DISSIPATION
Figure 34. Driving 50 Ω Loads
REV. D
–14–
AMP01
HEATSINKING
External series resistors could be added to guard against higher
voltage levels at the input, but resistors alone increase the input
noise and degrade the signal-to-noise ratio, especially at high
gains.
To maintain high reliability, the die temperature of any IC
should be kept as low as practicable, preferably below 100°C.
Although most AMP01 application circuits will produce very
little internal heat — little more than the quiescent dissipation
of 90 mW—some circuits will raise that to several hundred
milliwatts (for example, the 4-20 mA current transmitter appli-
cation, Figure 37). Excessive dissipation will cause thermal
shutdown of the output stage thus protecting the device from
damage. A heatsink is recommended in power applications to
reduce the die temperature.
Protection can also be achieved by connecting back-to-back
9.1 V Zener diodes across the differential inputs. This technique
does not affect the input noise level and can be used down to a
gain of 2 with minimal increase in input current. Although
voltage-clamping elements look like short circuits at the limiting
voltage, the majority of signal sources provide less than 50 mA,
producing power levels that are easily handled by low-power
Zeners.
Several appropriate heatsinks are available; the Thermalloy
6010B is especially easy to use and is inexpensive. Intended for
dual-in-line packages, the heatsink may be attached with a
cyanoacrylate adhesive. This heatsink reduces the thermal resis-
tance between the junction and ambient environment to ap-
proximately 80°C/W. Junction (die) temperature can then be
calculated by using the relationship:
Simultaneous connection of the differential inputs to a low
impedance signal above 10 V during normal circuit operation is
unlikely. However, additional protection involves adding 100 Ω
current-limiting resistors in each signal path prior to the voltage
clamp, the resistors increase the input noise level to just
5.4 nV/√Hz (refer to Figure 35).
Input components, whether multiplexers or resistors, should be
carefully selected to prevent the formation of thermocouple
junctions that would degrade the input signal.
TJ – TA
θJA
Pd =
where TJ and TA are the junction and ambient temperatures
respectively, θJA is the thermal resistance from junction to ambi-
ent, and Pd is the device’s internal dissipation.
OPTIONAL PROTECTION
RESISTORS, SEE TEXT.
LINEAR INPUT RANGE,
؎5V MAXIMUM
*
+15V
AMP01
–15V
DIFFERENTIAL PROTECTION
TO ؎30V
100⍀
1W*
OVERVOLTAGE PROTECTION
+IN
Instrumentation amplifiers invariably sit at the front end of
instrumentation systems where there is a high probability of
exposure to overloads. Voltage transients, failure of a trans-
ducer, or removal of the amplifier power supply while the signal
source is connected may destroy or degrade the performance of
an unprotected amplifier. Although it is impractical to protect
an IC internally against connection to power lines, it is relatively
easy to provide protection against typical system overloads.
9.1V 1W
ZENERS
V
OUT
100⍀
1W*
–IN
The AMP01 is internally protected against overloads for gains
of up to 100. At higher gains, the protection is reduced and
some external measures may be required. Limited internal over-
load protection is used so that noise performance would not be
significantly degraded.
Figure 35. Input Overvoltage Protection for Gains
2 to 10,000
POWER SUPPLY CONSIDERATIONS
Achieving the rated performance of precision amplifiers in a
practical circuit requires careful attention to external influences.
For example, supply noise and changes in the nominal voltage
directly affect the input offset voltage. A PSR of 80 dB means
that a change of 100 mV on the supply, not an uncommon
value, will produce a 10 µV input offset change. Consequently,
care should be taken in choosing a power unit that has a low
output noise level, good line and load regulation, and good
temperature stability.
AMP01 noise level approaches the theoretical noise floor of the
input stage which would be 4 nV/√Hz at 1 kHz when the gain is
set at 1000. Noise is the result of shot noise in the input devices
and Johnson noise in the resistors. Resistor noise is calculated
from the values of RG (200 Ω at a gain of 1000) and the input
protection resistors (250 Ω). Active loads for the input transis-
tors contribute less than 1 nV/√Hz of noise. The measured noise
level is typically 5 nV/√Hz.
Diodes across the input transistor’s base-emitter junctions,
combined with 250 Ω input resistors and RG, protect against
differential inputs of up to ±20 V for gains of up to 100. The
diodes also prevent avalanche breakdown that would degrade
the IB and IOS specifications. Decreasing the value of RG for
gains above 100 limits the maximum input overload protection
to ±10 V.
REV. D
–15–
AMP01
+15V
COMPLIANCE, TYPICALLY ؎10V
LINEARITY ~0.01%
OUTPUT RESISTANCE AT 20mA ~5M⍀
0.047F
POWER BANDWIDTH (–3dB) ~60kHz
18
1
INTO 500⍀ LOAD
+IN
R
TRIM
OUT
12
V+
13
10
SENSE
7
R2
200⍀
R
R
G
R1
100⍀
9
R
2k⍀
G
؎I
OUT
AMP01
V
IN
8
2
3
REFERENCE
G
V–
11
R
S
15
–IN
20
؋
R S
R
I
= V
IN
S
OUT
(
)
R
؋
R1 G
14
0.047F
R1 = 100⍀ FOR I
= ؎20mA
OUT
–15V
R
S
V
= ؎100mV FOR ؎20mA FULL SCALE
IN
2k⍀
Figure 36. High Compliance Bipolar Current Source with 13-Bit Linearity
ALL RESISTORS 1% METAL FILM
+15V
TO +30V
R
2k⍀
S
0.047F
14
R
S
18
1
15
+IN
R3
100⍀
R
12
V+
S
13
10
R2
200⍀
R
R
G
2
7
8
R
TRIM
OUT
9
4
6
R
G
AMP01
2.75k⍀
REF-02
R5
2
3
2.21k⍀
G
V–
11
R6
500⍀
ZERO TRIM
R1
100⍀
R4
100⍀
–IN
0V
I
OUT
4mA TO 20mA
0.047F
–5V
COMPLIANCE OF I
, +20V WITH +30V SUPPLY (OUTPUT w.r.t. 0V)
OUT
DIFFERENTIAL INPUT OF 100mV FOR 16mA SPAN
OUTPUT RESISTANCE ~5M⍀ AT I
= 20mA
OUT
LINEARITY 0.01% OF SPAN
Figure 37. 13-Bit Linear 4–20 mA Transmitter Constructed by Adding a Voltage Reference.
Thermocouple Signals Can Be Accepted Without Preamplification.
REV. D
–16–
AMP01
+15V
+
10F
0.047F
10k⍀
14
R
S
2N4921
18
1
15
+IN
R
S
12
V+
0.047F
100⍀
13
SENSE
7
R
R
G
9
V
R
OUT
AMP01
G
(؎10V INTO 10⍀)
8
2
3
REFERENCE
G
10
V–
11
–IN
2N4918
GND
–15V
0.047F
VOLTAGE GAIN, G = 100
POWER BANDWIDTH (–3dB), 60kHz
QUIESCENT CURRENT, 4mA
+
LINEARITY~0.01% @ FULL OUTPUT INTO 10⍀
Figure 38. Adding Two Transistors Increases Output Current to ±1 A Without Affecting the Quiescent Current of 4 mA.
Power Bandwidth is 60 kHz.
Q1, Q2...........J110
Q3, Q4, Q5....J107
IC1 ...............CMP-04
IC2 ...............OP15GZ
+15V
R
10k⍀
S
0.047F
18
1
+IN
–IN
14
R
S
15
S
R
G
12
V+
R
200k⍀ 20k⍀
2k⍀
196⍀
47k⍀
47k⍀
47k⍀
47k⍀
SENSE
13
Q4
7
9
Q5
Q3
AMP01
OUT
GND
V–
Q2
8
10
Q1
V
REFERENCE
OOS
NULL
+15V
11
2
3
5
3
2
V
IOS
R
7
G
4
NULL
6
IC2
4
17
16
2
1
14
+
13
+
0.047F
–15V
100k⍀
100k⍀
+
+
3
4
IC1
6
LINEARITY~0.005%, G = 10 AND 100
~0.02%, G = 1 AND 1000
8
12
27k⍀
10
GAIN ACCURACY, UNTRIMMED~0.5%
+15V
SETTLING TIME TO 0.01%, ALL GAINS,
LESS THAN 75s
5
7
9
11
G1000
TTL COMPATIBLE INPUTS
2.7k⍀
–15V
G1
G10
G100
GAIN SWITCHING TIME, LESS THAN 100s
Figure 39. The AMP01 Makes an Excellent Programmable-Gain Instrumentation Amplifier. Combined Gain-Switching
and Settling Time to 13 Bits Falls Below 100 µs. Linearity Is Better than 12 Bits over a Gain Range 1 to 1000.
REV. D
–17–
AMP01
R
S
+15V
10k⍀
0.047F
*MATCHED TO 0.1%
0V
14
*5k⍀
R
S
18
1
15
+IN
R
S
12
V+
1.5k⍀
13
10
SENSE
R
R
G
7
7
*5k⍀
2
3
9
AMP01
R
G
6
470pF
OP37
4
8
2
3
REFERENCE
G
V–
11
–IN
0.047F
0V
–15V
20
؋
R S
VOLTAGE GAIN, G =
(
)
R
G
R
L
MAXIMUM OUTPUT, 20V p-p INTO 600⍀
T.H.D. 0.01% @ 1kHz, 20V p-p INTO 600⍀, G = 10
+
OUTPUT
DIFFERENTIAL COMMON-MODE
OUTPUT
REFERENCE
(؎5V MAX)
Figure 40. A Differential Input Instrumentation Amplifier with Differential Output Replaces a Transformer in Many
Applications. The Output will Drive a 600 Ω Load at Low Distortion, (0.01%).
+15V
POWER BANDWIDTH (–3dB)~150kHz
TOTAL HARMONIC DISTORTION~0.006%
@1kHz, 20V p-p INTO 500⍀ // 1000pF
+
8
REF
0.047F
10F
7
18
1
SENSE
V
IN
12
V+
13
10
R
R
G
9
R1
390⍀
V
OUT
AMP01
2
3
G
V–
11
R2
4.95k⍀
R
S
C
R
L
L
15
R
S
14
0.047F
10F
+
NC
NC
–15V
R3
50⍀
CLOSED-LOOP VOLTAGE GAIN MUST BE
GREATER THAN 50 FOR STABLE OPERATION
R2
R3
VOLTAGE GAIN, G =
1 +
(
)
NC = NO CONNECT
Figure 41. Configuring the AMP01 as a Noninverting Operational Amplifier Provides Exceptional Performance. The
Output Handles Low Load Impedances at Very Low Distortion, 0.006%.
REV. D
–18–
AMP01
NC
NC
R2
220k⍀
14
R1
3
2
R
S
V
15
IN
R
S
0.01F
4.7k⍀
7
8
SENSE
R
R
G
REF
9
V
OUT
AMP01
R4
1
10
G
V–
11
20V p-p INTO 500⍀ // 1000pF.
V–
TOTAL HARMONIC DISTORTION:
R3
+
<0.005% @ 1kHz, V
= 20V p-p
18
12
OUT
G = 1 TO 1000
13
R2
GAIN (G)
R1 =
0.047F
0.047F
10F
10F
R3 = R1 // R2
+
R4 = 1.5k⍀ @ G = 1
1.2k⍀ @ G = 10
120⍀ @ G = 100 AND 1000
+15V
–15V
Figure 42. TheInvertingOperationalAmplifierConfigurationhasExcellentLinearityovertheGainRange1to1000, Typically
0.005%. Offset Voltage Drift at Unity Gain Is Improved over the Drift in the Instrumentation Amplifier Configuration.
+15V
8
680pF
+
R1
4.7k⍀
REF
7
10F
0.047F
18
1
POWER BANDWIDTH (–3dB)~60kHz
V
IN
SENSE
12
V+
TOTAL HARMONIC DISTORTION~0.001%
@1kHz, 20V p-p INTO 500⍀ // 1000pF
0.01F
13
10
R
R
G
NC = NO CONNECT
9
R
3k⍀
R3
330⍀
G
V
OUT
AMP01
2
3
G
C
R
L
L
V–
11
R2
R
S
4.7k⍀
15
R
S
0.047F
10F
14
+
NC
–15V
NC
Figure 43. Stability with Large Capacitive Loads Combined with High Output Current Capability make the AMP01 Ideal
for Line Driving Applications. Offset Voltage Drift Approaches the TCVIOS Limit, (0.3 µV/°C).
REV. D
–19–
AMP01
V+
V–
16.2k⍀
1F
13
18
1
12
2
3
–
11
R
G
1
10
200k⍀ 20k⍀ 2k⍀ 200⍀
OUTPUT
1.82k⍀
1.62M⍀
1/2 OP215
7
4
+
9
AMP01
8
G
G
100
8
10
G
1
R
V+
V–
G
1000
R
S
2
3
15
16.2k⍀
1F
G
1F
5
6
+
R
S
7
14
1/2 OP215
10k⍀
e
–
OUT
9.09k⍀
1k⍀
G
e
(G = 1, 10, 100) =
1000
n
1000
؋
G G
1,10,100
e
OUT
e
(G = 1000) =
n
100
؋
G 100⍀
Figure 44. Noise Test Circuit (0.1 Hz to 10 Hz)
200⍀
10T
1.91k⍀
0.1%
V
IN
V
OUT
20V p-p
2
؋
HSCH-1001 10k⍀
0.1%
2k⍀
0.1%
10k⍀
0.1%
G
1
G
10
14
S
3
1
R
G
1000
G
100
R
G
15
1.1k⍀
0.1%
102⍀
0.1%
R
10⍀
0.1%
200k⍀ 20k⍀ 2k⍀
0.1%
200⍀
0.1% 0.1% 0.1%
S
7
8
9
AMP01
G
G
100
10
G
1
R
G
1000
10
2
11
G
12
18
13
0.047F
0.047F
V+
V–
Figure 45. Settling-Time Test Circuit
REV. D
–20–
AMP01
+15V
R
S
0.047F
10k⍀
11
20
؋
R S
15
16
9
VOLTAGE GAIN, G =
1
3
18
1
(
)
R
+IN
–IN
G
14
R
S
R
S
12
V+
SENSE
R
13
10
G
DG390
7
9
R
10
15
G
AMP01
ANALOG
SWITCH
V
OUT
200⍀
7.5k⍀
8
2
3
REFERENCE
R
V–
11
G
4
5
6
8
15k⍀
13
14
15
4
؎1mA
14
13
DAC-08
1, 2
16
3
0.047F
R1
100⍀
7.5k⍀
0.01F
TTL INPUT
"OFFSET"
0V
TTL INPUT
"ZERO"
–15V
Figure 46. Instrumentation Amplifier with Autozero
+18V
10k⍀
0.047F
14
18
1
15
R
SENSE
S
12
R
S
13
10
R
R
G
7
9
AMP01
V
OUT
10k⍀
2
8
G
3
11
0.047F
–18V
Figure 47. Burn-In Circuit
REV. D
–21–
AMP01
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Cerdip
(Q-18)
0.005 (0.13) MIN
0.098 (2.49) MAX
18
10
0.310 (7.87)
0.220 (5.59)
1
9
0.320 (8.13)
0.290 (7.37)
PIN 1
0.960 (24.38) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
15؇
0؇
28-Terminal Ceramic Leadless Chip Carrier
(E-28A)
0.300 (7.62)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.150
(3.51)
BSC
0.015 (0.38)
MIN
0.095 (2.41)
0.075 (1.90)
26
4
28
25
5
0.028 (0.71)
0.022 (0.56)
0.458 (11.63)
1
0.442 (11.23)
SQ
0.458
0.011 (0.28)
0.007 (0.18)
R TYP
BOTTOM
VIEW
(11.63)
MAX
SQ
0.050
(1.27)
BSC
0.075
(1.91)
REF
19
18
12
11
45؇ TYP
0.200
(5.08)
BSC
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
20-Lead SOIC
(R-20)
0.5118 (13.00)
0.4961 (12.60)
20
11
1
10
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
؋
45؇ 0.0500 (1.27)
0.0157 (0.40)
8؇
0؇
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
REV. D
–22–
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