AN-0988 [ADI]

The AD9552: A Programmable Crystal Oscillator for Network Clocking Applications; 在AD9552 ：可编程晶体振荡器的时钟网络应用


型号：	AN-0988
厂家：	ADI
描述：	The AD9552: A Programmable Crystal Oscillator for Network Clocking Applications 在AD9552 ：可编程晶体振荡器的时钟网络应用振荡器晶体振荡器时钟
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AN-0988

APPLICATION NOTE

One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

The AD9552: A Programmable Crystal Oscillator for Network Clocking Applications

by Ken Gentile

The ubiquitous quartz crystal oscillator has been the workhorse

of timekeeping applications for decades. Low cost, coupled with

relatively high stability, is the driving force behind the success of

the quartz crystal oscillator in a broad range of applications.

The high resonant Q factor makes the quartz crystal oscillator

an attractive candidate for the resonant element in fixed fre-

quency oscillators. However, an ever-increasing number of

network clock applications require a stable, single frequency

oscillator as a source for synthesizing different network

frequencies. The AD9552 is a low cost, integrated solution

for such applications.

PLL

VOLTAGE

CONTROLLED

OSCILLATOR

f_REF

QUARTZ

CRYSTAL

OSCILLATOR

PHASE

DETECTOR

LOOP

FILTER

f_OUT= N × f_REF

FEEDBACK

DIVIDER

(N)

Figure 1. PLL-Based Frequency Upconverter

Rev. 0 | Page 1 of 8

AN-0988

Application Note

TABLE OF CONTENTS

Frequency Upconversion................................................................. 3

Conclusion..........................................................................................8

The AD9552 Architecture ............................................................... 4

Rev. 0 | Page 2 of 8

Application Note

AN-0988

FREQUENCY UPCONVERSION

The relatively low resonant frequency of a quartz crystal

resonator (typically less than 50 MHz for fundamental mode

resonance) is a shortcoming for network applications requiring

an output frequency in excess of 100 MHz. The higher output

frequency requirement of these applications implies the need

for translating the relatively low output frequency of the basic

crystal oscillator to a higher frequency, a process often referred

to as upconversion. One of the most common upconversion

methods involves the use a phase-locked loop (PLL) with a

frequency divider in its feedback path (see Figure 1). The

output frequency (f_O) is given by

To resolve this restriction, simply place a second programmable

frequency divider at the output, as shown in Figure 2.

With the additional divider the output frequency is given by

f_O= (N/P) × f_REF

where P is the output frequency divider value.

The architecture shown in Figure 2 allows for rational f_OUT/f_REF

ratios (that is, one integer divided by another). Furthermore,

for P > N, f_OUTis less than f_REF, which overcomes the aforemen-

tioned drawback. Note that in the previous architecture (Figure 1)

there is a necessary harmonic relationship between f_OUTand f_REF

because N is an integer. An unintentional benefit of the new

architecture (Figure 2) is the elimination of this harmonic

restriction. The same result is possible by placing the second

divider at the output of the crystal oscillator instead of at the

output of the PLL. Such an arrangement, however, means that

the PLL design must accommodate a range of input frequencies

rather than the single crystal oscillator frequency.

f_O= N × f_REF

where:

N is the frequency divider value.

_REFis the input frequency.

Generally, the bandwidth of the loop filter is relatively narrow

in order to minimize spurious artifacts in the output spectrum.

Furthermore, by making N programmable, the PLL upconverter

solves the problem of producing different output frequencies

from a single frequency source, namely a quartz crystal oscilla-

tor. This architecture is relatively easy to implement, especially

if the feedback divider is only required to provide integer

division factors.

The architecture of Figure 2 satisfies any application for which

the ratio, N/P, meets the required output/input frequency ratio.

The amount of flexibility provided by this architecture depends

on the range of N and P, that is, the larger the range of N and P,

the more flexible the solution. There is a practical limit, how-

ever, to the range of N because the range of N determines the

required frequency range of the voltage controlled oscillator

(VCO). The wider the VCO range, the more difficult it is to

design the VCO without sacrificing performance.

The drawback to the architecture shown in Figure 1 is that

the output frequency must be the same as or greater than f_REF

PLL

VOLTAGE

CONTROLLED

OSCILLATOR

OUTPUT

f_REF

QUARTZ

CRYSTAL

OSCILLATOR

PHASE

DETECTOR

LOOP

FILTER

f_OUT= (N/P) × f_REF

DIVIDER

(P)

FEEDBACK

DIVIDER

(N)

Figure 2. PLL-Based Frequency Upconverter with Output Divider

Rev. 0 | Page 3 of 8

AN-0988

Application Note

THE AD9552 ARCHITECTURE

The AD9552 incorporates the basic architecture of Figure 2, but

has a feedback divider capable of fractional divide values. A

simplified block diagram of the AD9552 appears in Figure 3.

the device (potentially eliminating the need for serial commu-

nication).

The AD9552 has nine configuration pins partitioned into a

group of three (Pin A0 to Pin A2) and a group of six (Pin Y0

to Pin Y5). The A pins select 1 of 8 predefined reference

frequencies (see Table 1), while the Y pins select 1 of 64 output

frequencies (see Table 2). The configuration pins automatically

set the appropriate internal divider values for generating the

frequency at OUT1, as indicated in Table 2.

The AD9552 offers two programming methods. One is via

a serial communication port that provides full control of the

device settings. The other is via configuration selection pins

that allow the user to select one of a predefined set of common

network clock frequencies simply by pin strapping

SERIAL PORT

CONTROLLER

BANK

SPI PORT

N, F, M, P , P

CONFIGURATION

SELECTION PINS

PIN-SELECTED

DIVIDER VALUES

Σ-Δ

MODULATOR

÷ (N + F/M)

3350MHz TO

4050MHz

DETECTOR

PFD/

CHARGE

PUMP

÷ P

OUT

VCO

4 TO 11 1 TO 63

1 TO 63

REF

÷ P

2×

DCXO

QUARTZ CRYSTAL

RESONATOR

LOOP FILTER

Figure 3. The AD9552 Crystal Oscillator and Frequency Up-Converter

Table 1. Pin Strapped Reference Frequency

Reference Frequency (MHz)

10.00

12.00

12.80

16.00

19.20

19.44

20.00

26.00

Rev. 0 | Page 4 of 8

Application Note

AN-0988

Table 2. Pin Strapped Output Frequency

Output (MHz)

51.84

61.44

Output (MHz)

569.1964

622.08

624.7048

625

622.08(239/237)

629.9878

640

62.5

66.666

74.17582

74.25

77.76

98.304

100

106.25

120

125

641.52

625(66/64)

657.421875

657.421875(239/238)

622.08(15/14)

669.1281

622.08(255/237)

625(15/14)

670.8386

622.08(255/236)

625(66/64)(15/14)

625(255/237)(66/64)

693.75

622.08(253/226)

657.421875(255/238)

657.421875(255/237)

716.5372

718.75

719.7344

748.0709

750

777.6

779.5686

781.25

625(10/8)(66/64)

133

155.52

156.25

159.375

161.1328125

10518.75/64

155.52(15/14)

155.52(255/237)

167.6616

177.7371

245.76

250

311.04

320

400

433.925

531.25

537.6

Even though the context of this application note is the use of a

crystal resonator, the AD9552 also provides an alternate input

source. The user can connect a single-ended CMOS clock signal

directly to the REF input pin of the AD9552 instead of using a

crystal resonator.

The benefit of fractional division is that it yields a much wider

selection of VCO output frequencies (within the bandwidth of

the VCO) for a given reference frequency. The reason is that the

ratio, f_VCO/f_REF, must be an integer (N) for an integer-only PLL,

but can be a fractional value (N + F/M) for a fractional PLL,

which allows for a much larger set of valid frequency ratios.

The AD9552 offers two output clock signals, OUT₁and OUT₂.

OUT₁is the primary output. OUT₂is an auxiliary output that

is programmable as an integer submultiple of the frequency at

OUT₁or as a copy of the frequency at the input to the phase-

frequency detector (PFD) of the PLL.

For example, suppose the VCO range is 800 MHz to 1000 MHz

and that f_REFis 25 MHz. For an integer-only PLL, the only

possible VCO output frequencies are 800 MHz to 1000 MHz in

25 MHz steps (corresponding to N values 32 to 40). Conversely,

a fractional PLL supports any output frequency between 800 MHz

and 1000 MHz as long as the fraction, F/M, has the necessary

resolution. In the case of the AD9552, fractional resolution is

limited to 20 bits for both F and M, which yields a resolution

of 1/1,048,575. The user can program the 20-bit values for

both F and M, allowing for a very large set of possible output

frequencies.

The feedback divider of the AD9552 provides fractional

division, but not to the exclusion of integer division. Fractional

division offers a significant amount of flexibility because the

frequency scale factor takes the form N + F/M (where F/M < 1),

instead of simply N as in Figure 1.

Rev. 0 | Page 5 of 8

AN-0988

Application Note

The fractional feedback divider of the AD9552, along with

its output dividers (P₀and P₁), produces a primary output

frequency (f_OUT1) given by

space. The reason is that the SDM moves the spurious energy

far enough out of band to allow for relatively easy filtering. In

fact, Figure 4 and Figure 5 show actual phase noise measure-

ments of the AD9552 pin strapped to yield a 625 MHz output

using a 26 MHz crystal resonator.

_OUT1= [(N + F/M)/(P₀× P₁)] × f_PFD

The secondary output frequency (f_OUT2) of the AD9552 is

_OUT2= f_OUT1/P₂or f_OUT2= f_PFD

The phase noise plot shown in Figure 4 represents the unfiltered

output of the AD9552 and demonstrates the raw performance

of the device. Note the spurious components between 1 MHz

and 100 MHz with magnitudes ranging from about −60 dBc to

−90 dBc. The resulting rms jitter in the SONET OC-192 band

(50 kHz to 80 MHz) is 0.74 ps. On the other hand, exclusion of

the spurious artifacts (see Figure 5) yields 0.51 ps of rms jitter.

Although not shown, measurements in the SONET OC-3 band

(12 kHz to 20 MHz) indicate 0.65 ps of rms jitter, either with or

without the inclusion of the spurious artifacts in the

depending on the selection of the signal source for OUT₂.

In the above equations, f_PFD= f_REFor f_PFD= 2 × f_REF, depending on

the selection of the optional 2× frequency multiplier.

For fractional frequency division, typically the feedback divider

assumes one integer value most of the time (Q, for example),

but periodically changes to Q + 1 in such a way that the average

divide ratio is the desired fractional value. The word, periodi-

cally, is significant because it implies undesirable spurious

artifacts in the output spectrum. To help mitigate the spurious

artifacts that are normally associated with a fractional divider,

the AD9552 uses a sigma-delta modulator (SDM) with a built-

in pseudorandom binary sequence (PRBS) generator to spread

out the spurious energy. The combination of an SDM and PRBS

generator in the feedback divider provides sufficient spurious

suppression to satisfy the specifications of many network clock

applications.

measurement.

For this particular application (synthesizing a 625 MHz output

signal using a 26 MHz crystal), comparison of the rms jitter

values, both with and without the spurious content in both the

OC-3 and OC-192 bands, indicates that the spurs appearing in

the 1 MHz to 10 MHz range have no significant impact on rms

jitter performance. The AD9552 suppresses the spurs in the

1 MHz to 10 MHz range to the point of having no adverse affect

on the rms jitter performance.

Even though the AD9552 generates some spurious artifacts,

thus limiting its usefulness as a general-purpose crystal oscilla-

tor replacement, it is still well suited for the network clocking

Rev. 0 | Page 6 of 8

Application Note

AN-0988

RMS Jitter: 736.208 fsec

Figure 4. AD9552 Phase Noise Measurement

Rev. 0 | Page 7 of 8

AN-0988

Application Note

RMS Jitter: 506.501 fsec

Figure 5. AD9552 Phase Noise Excluding Spurious Artifacts

CONCLUSION

The measurement results for this particular application

(625 MHz out using a 26 MHz crystal) indicate that the

AD9552 meets a 0.65 ps rms jitter requirement in the OC-3

band without the need for additional filtering of the output

signal. On the other hand, it should be possible to achieve

similar rms jitter performance (~0.6 ps) in the OC-192 band

by using an external filter to suppress the spurs beyond the

1 MHz range. For example, one might use a SAW filter

centered at 625 MHz with a 2 MHz bandwidth.

the spurious content of each output/input frequency ratio in an

application to determine if postfiltering is necessary. If external

filtering is necessary, then the appropriate filter parameters

(such as bandwidth, stop-band attenuation, and insertion loss)

must be determined to generate the desired jitter performance.

Although the AD9552 is not the only solution for network

clocking applications, its flexibility, low cost, high reliability, and

ease of use are significant advantages over other solutions.

Applications using a different output/input frequency ratio have

a different set of spurious artifacts. Thus, it is wise to analyze

registered trademarks are the property of their respective owners.

AN07918-0-7/09(0)

Rev. 0 | Page 8 of 8

AN-0988 [ADI]

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