BF516F [ADI]
Blackfin Embedded Processor; Blackfin嵌入式处理器型号: | BF516F |
厂家: | ADI |
描述: | Blackfin Embedded Processor |
文件: | 总68页 (文件大小:2494K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Blackfin
Embedded Processor
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
FEATURES
PERIPHERALS
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages. See Operating Conditions
on Page 20
IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588
support (ADSP-BF518/ADSP-BF518F only)
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 56 interrupt inputs
2 serial peripheral interfaces (SPI)
Qualified for Automotive Applications. See Automotive
Products on Page 65
168-ball CSP_BGA or 176-lead LQFP with exposed pad
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
2 UARTs with IrDA support
MEMORY
116K bytes of on-chip memory
2-wire interface (TWI) controller
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Optional 4M bit SPI flash with boot option
Flexible booting options from internal SPI flash, OTP
memory, external SPI/parallel memories, or from SPI/UART
host devices
Code security with Lockbox secure technology
One-time-programmable (OTP) memory
Memory management unit providing memory protection
Eight 32-bit timers/counters with PWM support
3-phase 16-bit center-based PWM unit
32-bit general-purpose counter
Real-time clock (RTC) and watchdog timer
32-bit core timer
40 general-purpose I/Os (GPIOs)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
RTC
OTP
WATCHDOG TIMER
PERIPHERAL
ACCESS BUS
COUNTER
3-PHASE PWM
TIMER7–0
TWI
JTAG TEST AND EMULATION
INTERRUPT
CONTROLLER
B
SPORT1-0
PORTS
RSI (SDIO)
PPI
L1
L1
DATA
DMA
CONTROLLER
INSTRUCTION
MEMORY
MEMORY
UART1–0
EMAC
SPI1
DMA
EXTERNAL
BUS
16
EXTERNAL ACCESS BUS
DMA CORE BUS
BOOT
ROM
EXTERNAL PORT
FLASH, SDRAM CONTROL
SPI0
4 Mbit SPI Flash
(See Table 1)
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2011 Analog Devices, Inc. All rights reserved.
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
Revision History ...................................................... 2
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 5
Event Handling .................................................... 6
DMA Controllers .................................................. 7
Processor Peripherals ............................................. 7
Dynamic Power Management ................................ 11
Voltage Regulation Interface .................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 15
Development Tools ............................................. 15
Related Signal Chains ........................................... 16
Lockbox Secure Technology Disclaimer .................... 16
Signal Descriptions ................................................. 17
Specifications ........................................................ 20
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 22
Flash Memory Characteristics ................................ 24
Absolute Maximum Ratings ................................... 25
Package Information ............................................ 26
ESD Sensitivity ................................................... 26
Timing Specifications ........................................... 27
Output Drive Currents ......................................... 50
Test Conditions .................................................. 52
Thermal Characteristics ........................................ 56
176-Lead LQFP Lead Assignment ............................... 57
168-Ball CSP_BGA Ball Assignment ........................... 60
Outline Dimensions ................................................ 63
Surface-Mount Design .......................................... 64
Automotive Products .............................................. 65
Ordering Guide ..................................................... 65
Designing an Emulator-Compatible
Processor Board (Target) ................................... 16
Related Documents ............................................. 16
REVISION HISTORY
1/11—Rev. A to Rev. B
Revised tWL, tWH and tOH specification in RSI Controller Timing
(High Speed Mode) ................................................. 36
Revised tMDCIH and tMDCOH specifications in 10/100 Ethernet
MAC Controller Timing: MII Station Management ........ 48
This data sheet release coincides with the release of the revised
ADSP-BF51x Blackfin Processor Hardware Reference. All
redundant information has been removed.
Revised several specifications in Operating Conditions ... 20
Revised fVCO specification in Phase-Locked Loop Operating
Conditions ........................................................... 21
Corrected dimensions in 168-Ball Chip Scale Package Ball Grid
Array [CSP_BGA] (BC-168-1) ................................... 64
Revised several specifications in Electrical Characteristics 22
Added additional fCKIN specification for automotive models in
Clock and Reset Timing .......................................... 27
Changed the parameter VDDMEM to VDDEXT in Asynchronous
Memory Read Cycle Timing ..................................... 29
SDRAM Interface Timing ........................................ 31
Parallel Peripheral Interface Timing ........................... 33
Serial Ports ........................................................... 37
Revised tHFSPE specification in Parallel Peripheral Interface Tim-
ing ..................................................................... 33
Revised tHFSPE specification and added the tPSUD specification in
Parallel Peripheral Interface Timing ........................... 33
Revised the tWL and tWH specifications in
RSI Controller Timing ............................................ 35
Rev. B
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
GENERAL DESCRIPTION
The ADSP-BF512/ADSP-BF512F, ADSP-BF514/ADSP-
BF514F, ADSP-BF516/ADSP-BF516F, ADSP-BF518/ADSP-
BF518F processors are members of the Blackfin® family of prod-
ucts, incorporating the Analog Devices/Intel Micro Signal
Architecture (MSA). Blackfin processors combine a dual-MAC
state-of-the-art signal processing engine, the advantages of a
clean, orthogonal RISC-like microprocessor instruction set, and
single-instruction, multiple-data (SIMD) multimedia capabili-
ties into a single instruction-set architecture.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
The processors are completely code compatible with other
Blackfin processors.
SYSTEM INTEGRATION
Table 1. Processor Comparison
The ADSP-BF51x processors are highly integrated system-on-a-
chip solutions for the next generation of embedded network
connected applications. By combining industry-standard inter-
faces with a high performance signal processing core, cost-
effective applications can be developed quickly, without the
need for costly external components. The system peripherals
include an IEEE-compliant 802.3 10/100 Ethernet MAC with
IEEE-1588 support (ADSP-BF518/ADSP-BF518F only), an RSI
controller, a TWI controller, two UART ports, two SPI ports,
two serial ports (SPORTs), nine general-purpose 32-bit timers
(eight with PWM capability), 3-phase PWM for motor control,
a real-time clock, a watchdog timer, and a parallel peripheral
interface (PPI).
Feature
IEEE-1588
Ethernet MAC
RSI
TWI
SPORTs
UARTs
SPIs
GP Timers
Watchdog Timers
RTC
–
–
–
1
2
2
2
8
1
1
1
–
1
3
–
–
–
1
2
2
2
8
1
1
1
1
1
3
–
–
1
1
2
2
2
8
1
1
1
–
1
3
–
–
1
1
2
2
2
8
1
1
1
1
1
3
–
1
1
1
2
2
2
8
1
1
1
–
1
3
–
1
1
1
2
2
2
8
1
1
1
1
1
3
1
1
1
1
2
2
2
8
1
1
1
–
1
3
1
1
1
1
2
2
2
8
1
1
1
1
1
3
BLACKFIN PROCESSOR CORE
As shown in Figure 1, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
The compare/select and vector search instructions are also
provided.
PPI
Internal 4 Mbit SPI flash
Rotary Counter
3-Phase PWM Pairs
GPIOs
40 40 40 40 40 40 40 40
L1 Instruction SRAM
L1 Instruction
SRAM/Cache
32K
16K
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
32K
32K
4K
32K
L3 Boot ROM
Maximum Speed Grade
Package Options
400 MHz
176-Lead LQFP with Exposed Pad
168-Ball CSP_BGA
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
Rev. B
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
ADDRESS ARITHMETIC UNIT
SP
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
FP
P5
P4
P3
P2
P1
P0
DAG1
DAG0
DA1
DA0
32
32
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
ALIGN
R7.H
R7.L
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
LOOP BUFFER
40
40
40 40
A0
A1
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 1. Blackfin Processor Core
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Rev. B
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
instruction can be issued in parallel with two 16-bit instruc-
tions, allowing the programmer to use many of the core
resources in a single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
MEMORY ARCHITECTURE
The ADSP-BF51x processors view memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. The memory map for both internal and exter-
nal memory space is shown in Figure 2.
Internal (On-Chip) Memory
The ADSP-BF51x processors have three blocks of on-chip
memory that provide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTES)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTES)
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA1 4000
External (Off-Chip) Memory
INSTRUCTION BANK C SRAM/CACHE (16K BYTES)
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The SDRAM controller can be programmed to interface to up
to 128M bytes of SDRAM. A separate row can be open for each
SDRAM internal bank, and the SDRAM controller supports up
to four internal SDRAM banks, improving overall performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
0xFFA1 0000
RESERVED
0xFFA0 8000
INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 4000
INSTRUCTION BANK A SRAM (16K BYTES)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTES)
0xFF90 4000
DATA BANK B SRAM (16K BYTES)
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTES)
0xFF80 4000
DATA BANK A SRAM (16K BYTES)
0xFF80 0000
RESERVED
0xEF00 8000
BOOT ROM (32K BYTES)
0xEF00 0000
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES)
Flash Memory
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTES)
0x2020 0000
The ADSP-BF512F/ADSP-BF514F/ADSP-BF516F/
ADSP-BF518F processors contain a SPI flash memory within
the package of the processor and connected to SPI0.
ASYNC MEMORY BANK 1 (1M BYTES)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTES)
0x2000 0000
The SPI flash memory has a 4M bit capacity and 1.8V (nominal)
operating voltage. The program/erase endurance is 100,000
cycles per block, and this memory has greater than 100 years of
data retention capability. Also included are support for software
write protection and for fast erase and byte-program.
RESERVED
0x08 00 0000
SDRAM MEMORY (16M BYTES
-128M BYTES)
0x0000 0000
Figure 2. ADSP-BF51x Internal/External Memory Map
Rev. B
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
The processors internally connect to the flash memory die with
the SPI0SCK, SPI0SEL4 or PH8, SPI0MOSI, and SPI0MISO sig-
nals similar to an external SPI flash. To further provide a secure
processing environment, these internally connected signals are
not exposed outside of the package. For this reason, program-
ming the ADSP-BF51xF flash memory is performed by running
code on the processor andcannot be programmed from external
signals. Data transfers between the SPI flash and the processor
cannot be probed externally. The flash memory has the follow-
ing additional features
• Serial Interface Architecture—SPI compatible with Mode 0
and Mode 3
• Superior Reliability—Endurance of 100,000 cycles and
greater than 100 years data retention
Booting from ROM
The processors contain a small on-chip boot kernel, which con-
figures the appropriate peripheral for booting. If the processors
are configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 14.
EVENT HANDLING
The event controller handles all asynchronous and synchronous
events to the processor. The processors provide event handling
that supports both nesting and prioritization. Nesting allows
multiple event service routines to be active simultaneously.
Prioritization ensures that servicing of a higher priority event
takes precedence over servicing of a lower priority event. The
controller provides support for five different types of events:
• Emulation—An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor through the JTAG interface.
• Flexible Erase Capability—Uniform 4K Byte sectors and
uniform 32 and 64K Byte overlay blocks
• Fast Erase and Byte-Program—Chip-erase time = 125 ms
(typical), Sector-/Block-Erase Time = 62 ms (typical) Byte-
Program Time = 50 μS (typical)
• Reset—This event resets the processor.
• Nonmaskable Interrupt (NMI)—The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions—Events that occur synchronously to program
flow; that is, the exception is taken before the instruction is
allowed to complete. Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Auto Address Increment (AAI) Programming—Decreases
total chip programming time over byte-program
operations
• End-of-Write Detection—Software polling the BUSY bit in
status register, busy status readout on SO pin
• Software Write Protection—Write protection through
block-protection bits in status register
One-Time Programmable Memory
• Interrupts—Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The event controller consists of two stages, the core event con-
troller (CEC) and the system interrupt controller (SIC). The
core event controller works with the system interrupt controller
to prioritize and control all system events. Conceptually, inter-
rupts from the peripherals enter into the SIC, and are then
routed directly into the general-purpose interrupts of the CEC.
The processors have 64K bits of one-time programmable non-
volatile memory that can be programmed by the developer only
once. It includes the array and logic to support read access and
programming. Additionally, its pages can be write protected.
The OTP memory allows both public and private data to be
stored on-chip. In addition to storing public and private key
data for applications requiring security, OTP allows developers
to store completely user-definable data such as customer ID,
product ID, and MAC address. Therefore, generic parts can be
supplied which are then programmed and protected by the
developer within this non-volatile memory.
I/O Memory Space
The processors do not define a separate I/O space. All resources
are mapped through the flat 32-bit address space. On-chip I/O
devices have their control registers mapped into memory-
mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processors. The inputs
to the CEC, identifies their names in the event vector table
(EVT), and lists their priorities are described in the
ADSP-BF51x Blackfin Processor Hardware Reference Manual
“System Interrupts” chapter.
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
cessor intervention. Memory DMA transfers can be controlled
by a very flexible descriptor-based methodology or by a stan-
dard register-based autobuffer mechanism.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processors provide a default mapping, the user
can alter the mappings and priorities of interrupt events by
writing the appropriate values into the interrupt assignment
registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor
Hardware Reference Manual “System Interrupts” chapter for the
inputs into the SIC and the default mappings into the CEC.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit corresponding to each of the peripheral
interrupt events. For more information, see the ADSP-BF51x
Blackfin Processor Hardware Reference Manual “System Inter-
rupts” chapter.
The processors also have an external DMA controller capability
via dual external DMA request signals when used in conjunc-
tion with the external bus interface unit (EBIU). This
functionality can be used when a high speed interface is
required for external FIFOs and high bandwidth communica-
tions peripherals. It allows control of the number of data
transfers for memory DMA. The number of transfers per edge is
programmable. This feature can be programmed to allow mem-
ory DMA to have an increased priority on the external bus
relative to the core.
PROCESSOR PERIPHERALS
The ADSP-BF51x processors contain a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see Figure 1 on Page 4). The processors
contain dedicated network communication modules and high
speed serial and parallel ports, an interrupt controller for flexi-
ble management of interrupts from the on-chip peripherals or
external sources, and power management control functions to
tailor the performance and power characteristics of the proces-
sor and system to many application scenarios.
All of the peripherals, except for the general-purpose I/O, rotary
counter, TWI, three-phase PWM, real-time clock, and timers,
are supported by a flexible DMA structure. There are also sepa-
rate memory DMA channels dedicated to data transfers
between the processor's various memory spaces, including
external SDRAM and asynchronous memory. Multiple on-chip
buses provide enough bandwidth to keep the processor core
running along with activity on all of the on-chip and external
peripherals.
DMA CONTROLLERS
The ADSP-BF51x processors have multiple independent DMA
channels that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the processor's internal memories and any of its DMA-
capable peripherals. Additionally, DMA transfers can be accom-
plished between any of the DMA-capable peripherals and
external devices connected to the external memory interfaces,
including the SDRAM controller and the asynchronous mem-
ory controller. DMA-capable peripherals include the Ethernet
MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual
DMA-capable peripheral has at least one dedicated DMA
channel.
The processors’ DMA controller supports both one-dimen-
sional (1-D) and two-dimensional (2-D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.
Real-Time Clock
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the DMA controller
include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels that transfer data between the vari-
ous memories of the processor system. This enables transfers of
blocks of data between any of the memories—including external
SDRAM, ROM, SRAM, and flash memory—with minimal pro-
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the proces-
sors. The RTC peripheral has a dedicated power supply so that it
can remain powered up and clocked even when the rest of the
processor is in a low power state. The RTC provides several pro-
grammable interrupt options, including interrupt per second,
minute, hour, or day clock ticks, interrupt on programmable
stopwatch countdown, or interrupt at a programmed alarm
time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of
that day.
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The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode or cause a transition from the hibernate
state.
mechanism for measuring pulse widths and periods of external
events. These timers can be synchronized to an external clock
input to the several other associated PF signals, an external
clock input to the PPI_CLK input signal, or to the internal
SCLK.
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to provide
a software auto-baud detect function for the respective serial
channels.
Connect RTC signals RTXI and RTXO with external compo-
nents as shown in Figure 3.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
RTXI
RTXO
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
R1
X1
C1
C2
3-Phase PWM
The processors integrate a flexible and programmable 3-phase
PWM waveform generator that can be programmed to generate
the required switching patterns to drive a 3-phase voltage
source inverter for ac induction (ACIM) or permanent magnet
synchronous (PMSM) motor control. In addition, the PWM
block contains special functions that considerably simplify the
generation of the required PWM switching patterns for control
of the electronically commutated motor (ECM) or brushless dc
motor (BDCM). Software can enable a special mode for
switched reluctance motors (SRM).
SUGGESTED COMPONENTS:
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 Mꢀ
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
Figure 3. External Components for RTC
Features of the 3-phase PWM generation unit are:
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
transition to full ON and full OFF states
• Possibility to synchronize the PWM generation to an exter-
nal synchronization
• Special provisions for BDCM operation (crossover and
output enable functions)
• Wide variety of special switched reluctance (SR) operating
modes
Watchdog Timer
The ADSP-BF51x processors include a 32-bit timer that can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
nonmaskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
General-Purpose (GP) Counter
A 32-bit GP counter is provided that can sense 2-bit quadrature
or binary codes as typically emitted by industrial drives or man-
ual thumb wheels. The counter can also operate in general-
purpose up/down count modes. Then, count direction is either
controlled by a level-sensitive input signal or by two edge
detectors.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of fSCLK
.
Timers
There are nine general-purpose programmable timer units in
the ADSP-BF51x processors. Eight timers have an external sig-
nal that can be configured either as a pulse width modulator
(PWM) or timer output, as an input to clock the timer, or as a
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A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three signals have a programmable debouncing
circuit.
An internal signal forwarded to the GP timer unit enables one
timer to measure the intervals between count events. Boundary
registers enable auto-zero operation or simple system warning
by interrupts when programmable count values are exceeded.
bit can be transferred to interrupt only addressed nodes in
multi-drop bus (MDB) systems. A frame is terminates by one,
one and a half, two or two and a half stop bits.
The UART ports support automatic hardware flow control
through the Clear To Send (CTS) input and Request To Send
(RTS) output with programmable assertion FIFO levels.
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable inter-frame space.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
Serial Ports
The ADSP-BF51x processors incorporate two dual-channel syn-
chronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configura-
tion, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
Serial ports operate in five modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
2-Wire Interface (TWI)
The processors include a TWI module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I2C® bus standard. The
TWI module offers the capabilities of simultaneous master and
slave operation, support for both 7-bit addressing and multime-
dia data arbitration. The TWI interface utilizes two signals for
transferring clock (SCL) and data (SDA) and supports the pro-
tocol at speeds up to 400k bits/sec. The TWI interface signals
are compatible with 5 V logic levels.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
• Packed I2S mode
• Left-justified mode
Removable Storage Interface (RSI)
Serial Peripheral Interface (SPI) Ports
The RSI controller, available on the ADSP-BF514, ADSP-
BF516, ADSP-BF518, and ADSP-BF518F acts as the host inter-
face for multi-media cards (MMC), secure digital memory cards
(SD Card), secure digital input/output cards (SDIO), and CE-
ATA hard disk drives. The following list describes the main fea-
tures of the RSI controller.
• Support for a single MMC, SD memory, SDIO card or CE-
ATA hard disk drive
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit and 8-bit MMC modes
• Support for 4-bit and 8-bit CE-ATA hard disk drives
• A ten-signal external interface with clock, command, and
up to eight data lines
• Card detection using one of the data signals
• Card interface clock generation from SCLK
• SDIO interrupt and read wait features
• CE-ATA command completion signal recognition and
disable
The processors have two SPI-compatible ports (SPI0 and SPI1)
that enable the processor to communicate with multiple SPI-
compatible devices.
The SPI interface uses three signals for transferring data: two
data signals (master output-slave input–MOSI, and master
input-slave output–MISO) and a clock signal (serial
clock–SCK). An SPI chip select input signal (SPIxSS) lets other
SPI devices select the processor, and multiple SPI chip select
output signals let the processor select other SPI devices. The SPI
select signals are reconfigured general-purpose I/O signals.
Using these signals, the SPI port provides a full-duplex, syn-
chronous serial interface, which supports both master/slave
modes and multimaster environments.
The SPI port baud rate and clock phase/polarities are program-
mable, and it has an integrated DMA channel, configurable to
support transmit or receive data streams. The SPI’s DMA chan-
nel can only service unidirectional accesses at any given time.
UART Ports
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
and none, even, or odd parity. Optionally, an additional address
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
• Programmable receive address filters, including a 64-bin
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames
• Advanced power management supporting unattended
transfer of receive and transmit frames and status to/from
external memory via DMA during low power sleep mode
• System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters
• Support for 802.3Q tagged VLAN frames
10/100 Ethernet MAC
The ADSP-BF516/ADSP-BF516F and ADSP-
BF518/ADSPBF518F processors offer the capability to directly
connect to a network by way of an embedded fast Ethernet
media access controller (MAC) that supports both 10-BaseT
(10M bits/sec) and 100-BaseT (100M bits/sec) operation. The
10/100 Ethernet MAC peripheral on the processor is fully com-
pliant to the IEEE 802.3-2002 standard and it provides
programmable features designed to minimize supervision, bus
use, or message processing by the rest of the processor system.
Some standard features are:
• Support of MII and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Programmable MDC clock rate and preamble suppression
• In RMII operation, seven unused signals may be config-
ured as GPIO signals for other purposes
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS
• Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing
• Flow control (in full-duplex operation): generation and
detection of pause frames
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
ADSP-BF518/ADSP-BF518F processors include hardware sup-
port for IEEE 1588 with an integrated precision time protocol
synchronization engine (PTP_TSYNC). This engine provides
hardware assisted time stamping to improve the accuracy of
clock synchronization between PTP nodes. The main features of
the PTP_SYNC engine are:
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
tocol standards
• Operating range for active and sleep operating modes, see
Table 43 on Page 45 and Table 44 on Page 46
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
• Lock adjustment
• Programmable PTM message support
• Dedicated interrupts
• Programmable alarm
• Internal loopback from transmit to receive
Some advanced features are:
• Buffered crystal output to external PHY for support of a
single crystal system
• Automatic checksum computation of IP header and IP
payload fields of Rx frames
• Independent 32-bit descriptor-driven receive and transmit
DMA channels
• Multiple input clock sources (SCLK, MII clock, external
clock)
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
Ports
• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations
Because of the rich set of peripherals, the processors group the
many peripheral signals to four ports—port F, port G, port H,
and port J. Most of the associated pins/balls are shared by multi-
ple signals. The ports function as multiplexer controls.
• Convenient frame alignment modes support even 32-bit
alignment of encapsulated receive or transmit IP packet
data in memory after the 14-byte MAC header
• Programmable Ethernet event interrupt supports any com-
bination of:
General-Purpose I/O (GPIO)
The ADSP-BF51x processors have 40 bidirectional, general-
purpose I/O (GPIO) signals allocated across three separate
GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ-
ated with Port F, Port G, and Port H, respectively. Each
GPIO-capable signal shares functionality with other peripherals
via a multiplexing scheme; however, the GPIO functionality is
the default state of the device upon power-up. Neither GPIO
output nor input drivers are active by default. Each general-pur-
pose port signal can be individually controlled by manipulation
of the port control, status, and interrupt registers.
• Selected receive or transmit frame status conditions
• PHY interrupt condition
• Wakeup frame detected
• Selected MAC management counter(s) at half-full
• DMA descriptor error
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Parallel Peripheral Interface (PPI)
Code Security with Lockbox Secure Technology
The ADSP-BF51x processors provide a parallel peripheral inter-
face (PPI) that can connect directly to parallel analog-to-digital
and digital-to-analog converters, ITU-R-601/656 video encod-
ers and decoders, and other general-purpose peripherals. The
PPI consists of a dedicated input clock signal, up to three frame
synchronization signals, and up to 16 data signals.
In ITU-R-656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information
is supported.
A security system consisting of a blend of hardware and soft-
ware provides customers with a flexible and rich set of code
security features with Lockbox® secure technology. Key features
include:
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets.
Three distinct ITU-R-656 modes are supported:
• Active video only mode—The PPI does not read in any
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI.
• Vertical blanking only mode—The PPI only transfers verti-
cal blanking interval (VBI) data, as well as horizontal
blanking information and control byte sequences on
VBI lines.
DYNAMIC POWER MANAGEMENT
The ADSP-BF51x processors provide four operating modes,
each with a different performance/power profile. In addition,
dynamic power management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. When configured for a 0 V core
supply voltage, the processor enters the hibernate state. Control
of clocking to each of the processor peripherals also reduces
power consumption. See Table 2 for a summary of the power
settings for each mode.
• Entire field mode—The entire incoming bitstream is read
in through the PPI. This includes active video, control pre-
amble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.
Table 2. Power Settings
Though not explicitly supported, ITU-R-656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
These modes support ADC/DAC connections, as well as video
communication with hardware signalling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
Core
Clock
System
Clock
PLL
Core
Mode/State PLL
Bypassed (CCLK) (SCLK) Power
Full On
Active
Enabled No
Enabled Enabled On
Enabled/ Yes
Enabled Enabled On
Disabled
Enabled
Sleep
—
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Deep Sleep Disabled —
Hibernate Disabled —
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
SDRAM. The SCKELOW bit in the VR_CTL register controls
whether or not SDRAM operates in self-refresh mode, which
allows it to retain its content while the processor is in hiberna-
tion and through the subsequent reset sequence.
Sleep Operating Mode—High Dynamic Power Savings
Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wakeup causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
As shown in Table 3, the processors support up to six different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains, but all domains
must be powered according to the appropriate Specifications
table for processor Operating Conditions; even if the fea-
ture/peripheral is not used.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
Table 3. Power Domains
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the Active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full
on mode.
Power Domain
VDD Range
VDDINT
All internal logic, except RTC, Memory, OTP
RTC internal logic and crystal I/O
Memory logic
VDDRTC
VDDMEM
VDDOTP
VDDFLASH
VDDEXT
OTP logic
Optional internal flash
All other I/O
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and system
blocks (SCLK). Any critical information stored internally (for
example memory contents, register contents) must be written to
a non-volatile storage device prior to removing power if the
processor state is to be preserved. Writing b#00 to the FREQ bits
in the VR_CTL register also causes the EXT_WAKE signal to
transition low, which can be used to signal an external voltage
regulator to shut down.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
Since VDDEXT is still supplied in this mode, all of the external sig-
nals three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to still have
power applied without drawing unwanted current.
The Ethernet module can signal an external regulator to wake
up using the EXT_WAKE signal. If PF15 does not connect as a
PHYINT signal to an external PHY device, it can be pulled low
by any other device to wake the processor up. The processor can
also be woken up by a real-time clock wakeup event or by assert-
ing the RESET pin. All hibernate wakeup events initiate the
hardware reset sequence. Individual sources are enabled by the
VR_CTL register. The EXT_WAKE signal is provided to indi-
cate the occurrence of wakeup events.
Power Savings Factor
2
fCCLKRED
-------------------------
fCCLKNOM
VDDINTRED
-------------------------------
VDDINTNOM
TRED
--------------
TNOM
=
×
×
% Power Savings = (1 – Power Savings Factor) × 100%
where the variables in the equations are:
f
f
CCLKNOM is the nominal core clock frequency
CCLKRED is the reduced core clock frequency
V
V
DDINTNOM is the nominal internal supply voltage
DDINTRED is the reduced internal supply voltage
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables may be held in external SRAM or
Rev. B
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
TNOM is the duration running at fCCLKNOM
BLACKFIN
TRED is the duration running at fCCLKRED
CLKOUT
TO PLL CIRCUITRY
VOLTAGE REGULATION INTERFACE
EN
EN
The ADSP-BF51x processors require an external voltage regula-
tor to power the VDDINT domain. To reduce standby power
consumption in the hibernate state, the external voltage regula-
tor can be signaled through EXT_WAKE to remove power from
the processor core. The EXT_WAKE signal is high-true for
power-up and may be connected directly to the low-true shut
down input of many common regulators.
The Power Good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the PG functionality,
refer to the ADSP-BF51x Blackfin Processor Hardware Reference.
CLKBUF
560 ⍀
XTAL
CLKIN
18 pF *
330 ⍀*
FOR OVERTONE
OPERATION ONLY:
18 pF *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.
CLOCK SIGNALS
The ADSP-BF51x processors can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor CLKIN signal. When an external
clock is used, the XTAL pin/ball must be left unconnected.
Figure 4. External Crystal Connections
25 MHz or 50 MHz crystal may be applied directly to the pro-
cessor. The 25 MHz or 50 MHz output of CLKBUF can then be
connected to an external Ethernet MII or RMII PHY device.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be done simply by writing to
the PLL_DIV register. The maximum allowed CCLK and SCLK
rates depend on the applied voltages VDDINT, VDDEXT, and
VDDMEM, and the VCO is always permitted to run up to the fre-
quency specified by the part’s speed grade. The CLKOUT signal
reflects the SCLK frequency to the off-chip world. It belongs to
the SDRAM interface, but it functions as a reference signal in
other timing specifications as well. While active by default, it
can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL
registers.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A paral-
lel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins/balls. The
on-chip resistance between the CLKIN pin/ball and the XTAL
pin/ball is in the 500 kΩ range. Further parallel resistors are typ-
ically not recommended. The two capacitors and the series
resistor shown in Figure 4 fine tune phase and amplitude of the
sine frequency.
The capacitor and resistor values shown in Figure 4 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on
“EE-168.”
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CCLK
SCLK
÷ 1, 2, 4, 8
÷ 1 to 15
PLL
5ꢁ to 64ꢁ
CLKIN
VCO
The CLKBUF signal is an output signal, which is a buffered ver-
sion of the input clock. This signal is particularly useful in
Ethernet applications to limit the number of required clock
sources in the system. In this type of application, a single
Figure 5. Frequency Modification Methods
Rev. B
|
Page 13 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 4 illustrates typical system clock ratios.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 5. This programmable core clock capability is useful for
fast core frequency modifications.
bits of the reset configuration register, sampled during power-
on resets and software-initiated resets, implement the modes
shown in Table 6.
Table 6. Booting Modes
BMODE2–0 Description
000
001
010
011
100
101
110
111
Idle - No boot
Boot from 8- or 16-bit external flash memory
Boot from internal SPI memory
Boot from external SPI memory (EEPROM or flash)
Boot from SPI0 host
Boot from OTP memory
Boot from SDRAM
Boot from UART0 Host
Table 5. Core Clock Ratios
• Idle/no boot mode (BMODE = 0x0)—In this mode, the
processor goes into idle. The idle boot mode helps recover
from illegal operating modes, such as when the user has
mis configured the OTP memory.
• Boot from 8-bit or 16-bit external flash memory
(BMODE = 0x1)—In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and—depend-
ing on instructions containing in the header—the boot
kernel performs 8-bit or 16-bit boot or starts program exe-
cution at the address provided by the header. By default, all
configuration settings are set for the slowest device possible
(3-cycle hold time, 15-cycle R/W access times, 4-cycle
setup).
Example Frequency Ratios
(MHz)
Signal Name Divider Ratio
CSEL1–0
VCO/CCLK
VCO
300
300
400
200
CCLK
300
150
100
25
00
01
10
11
1:1
2:1
4:1
8:1
Table 4. Example System Clock Ratios
Example Frequency Ratios
(MHz)
Signal Name Divider Ratio
The ARDY is not enabled by default, but it can be enabled
by OTP programming. Similarly, all interface behavior and
timings can be customized by OTP programming. This
includes activation of burst-mode or page-mode operation.
In this mode, all signals belonging to the asynchronous
interface are enabled at the port muxing level.
• Boot from internal SPI memory (BMODE = 0x2)—The
processor uses the internal PH8 GPIO signal to load code
previously loaded to the 4 Mbit internal SPI flash con-
nected to SPI0. Only available on the ADSP-BF512F/
ADSP-BF514F/ADSP-BF516F/ADSP-BF518F.
SSEL3–0
VCO/SCLK
VCO
100
300
400
SCLK
50
0010
2:1
0110
6:1
50
1010
10:1
40
The maximum CCLK frequency not only depends on the part's
speed grade (see Page 65), it also depends on the applied VDDINT
voltage. See Table 9 for details. The maximal system clock rate
(SCLK) depends on the chip package and the applied VDDINT
,
VDDEXT, and VDDMEM voltages (see Table 11 on Page 21).
• Boot from external SPI EEPROM or flash
BOOTING MODES
(BMODE = 0x3)—8-bit, 16-bit, 24-bit or 32-bit address-
able devices are supported. The processor uses the PG15
GPIO signal (at SPI0SEL2) to select a single SPI
EEPROM/flash device connected to the SPI0 interface;
then submits a read command and successive address bytes
(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device
is detected. Pull-up resistors are required on the SSEL and
MISO signals. By default, a value of 0x85 is written to the
SPI0_BAUD register.
• Boot from SPI0 host device (BMODE = 0x4)—The proces-
sor operates in SPI slave mode and is configured to receive
the bytes of the LDR file from an SPI host (master) agent.
In the host, the HWAIT signal must be interrogated by the
The processor has several mechanisms (listed in Table 6) for
automatically loading internal and external memory after a
reset. The boot mode is defined by three BMODE input bits
dedicated to this purpose. There are two categories of boot
modes. In master boot modes the processor actively loads data
from parallel or serial memories. In slave boot modes the pro-
cessor receives data from external host devices.
The boot modes listed in Table 6 provide a number of mecha-
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time or
by proper OTP programming at pre-boot time. The BMODE
Rev. B
|
Page 14 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
host before every transmitted byte. A pull-up resistor is
required on the SPI0SS input. A pull-down on the serial
clock may improve signal quality and booting robustness.
• Boot from OTP memory (BMODE = 0x5)—This provides
a stand-alone booting method. The boot stream is loaded
from on-chip OTP memory. By default the boot stream is
expected to start from OTP page 0x40 on and can occupy
all public OTP memory up to page 0xDF. This is 2560
bytes. Since the start page is programmable the maximum
size of the boot stream can be extended to 3072 bytes.
• Boot from SDRAM (BMODE = 0x6)—This is a warm boot
scenario, where the boot kernel starts booting from address
0x0000 0010. The SDRAM is expected to contain a valid
boot stream and the SDRAM controller must be configured
by the OTP settings.
• Boot from UART0 host (BMODE = 0x7)—Using an auto-
baud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities.
The boot ROM also features C-callable function entries that can
be called by the user application at run time. This enables sec-
ond-stage boot or boot management schemes to be
implemented with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core
processor resources.
When performing the autobaud, the UART expects a “@”
(0x40) character (eight bits data, one start bit, one stop bit,
no parity bit) on the RX0 signal to determine the bit rate.
The UART then replies with an acknowledgement com-
posed of 4 bytes (0xBF—the value of UART0_DLL and
0x00—the value of UART0_DLH). The host can then
download the boot stream. To hold off the host the Blackfin
processor signals the host with the boot host wait
(HWAIT) signal. Therefore, the host must monitor
HWAIT before every transmitted byte.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-harvard architecture,
which supports two 16-bit MACs or four 8-bit ALUs plus
two load/store plus two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or even dis-
abled based on OTP programming. External hardware,
especially booting hosts may watch the HWAIT signal to deter-
mine when the pre-boot has finished and the boot kernel starts
the boot process. By programming OTP memory, the user can
instruct the preboot routine to also customize the PLL, the
SDRAM Controller, and the Asynchronous Interface.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass pre-boot routine and/or boot ker-
nel in case of a software reset. They can also be used to simulate
a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the SDRAM controller or to speed up booting by managing
PLL, clock frequencies, wait states, or serial bit rates.
DEVELOPMENT TOOLS
The ADSP-BF51x processors are supported with a complete set
of CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel-
opment environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF51x processors. For more information about develop-
ment tools, visit www.analog.com.
EZ-KIT Lite Evaluation Board
For evaluation of the processors, use the EZ-KIT Lite® board
being developed by Analog Devices. The board comes with on-
chip emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.
Rev. B
| Page 15 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
The Application Signal Chains page in the Circuits from the
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
TM
Lab site (http://www.analog.com/circuits) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
The Analog Devices family of emulators are tools that every sys-
tem developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG processor. The
emulator uses the TAP to access the internal features of the pro-
cessor, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
processor must be halted to send data and commands, but once
an operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.
• Reference designs applying best practice design techniques
LOCKBOX SECURE TECHNOLOGY DISCLAIMER
Analog Devices products containing Lockbox Secure Technol-
ogy are warranted by Analog Devices as detailed in the Analog
Devices Standard Terms and Conditions of Sale. To our knowl-
edge, the Lockbox Secure Technology, when used in accordance
with the data sheet and hardware reference manual specifica-
tions, provides a secure method of implementing code and data
safeguards. However, Analog Devices does not guarantee that
this technology provides absolute security. ACCORDINGLY,
ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL
EXPRESS AND IMPLIED WARRANTIES THAT THE LOCK-
BOX SECURE TECHNOLOGY CANNOT BE BREACHED,
COMPROMISED, OR OTHERWISE CIRCUMVENTED AND
IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR
ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF
DATA, INFORMATION, PHYSICAL PROPERTY, OR INTEL-
LECTUAL PROPERTY.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see (EE-68) Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
RELATED DOCUMENTS
The following publications that describe the ADSP-BF512/
ADSP-BF514/ADSP-BF516/ADSP-BF518 processors (and
related processors) can be ordered from any Analog Devices
sales office or accessed electronically on our website:
• Getting Started With Blackfin Processors
• ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F,
BF518/BF518F Blackfin Processor Hardware Reference
• ADSP-BF53x/BF56x Blackfin Processor Programming
Reference
• ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F,
BF518/BF518F Blackfin Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
Wikipedia or the Glossary of EE Terms on the Analog Devices
website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
Rev. B
| Page 16 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
SIGNAL DESCRIPTIONS
The processors’ signal definitions are listed in Table 7. In order
to maintain maximum function and reduce package size and
signal count, some signals have dual, multiplexed functions. In
cases where signal function is reconfigurable, the default state is
shown in plain text, while the alternate function is shown in
italics.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. During hiber-
nate all outputs are three-stated unless otherwise noted in
Table 7.
The SDA (serial data) and SCL (serial clock) pins/balls are open
drain and therefore require a pullup resistor. Consult version
2.1 of the I2C specification for the proper resistor value.
It is strongly advised to use the available IBIS models to ensure
that a given board design meets overshoot/undershoot and sig-
nal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D. The termination resistors should
be placed near the processor to reduce transients and improve
signal integrity. The resistance value, typically 33 Ω or 47 Ω,
should be chosen to match the average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure to
verify overshoot/undershoot and signal integrity specifications
on actual hardware.
All I/O signals have their input buffers disabled with the excep-
tion of the signals noted in the data sheet that need pull-ups or
pull downs if unused.
Table 7. Signal Descriptions
Driver
Type1
Signal Name
EBIU
Type Function
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
AMS1–0
ARE
O
I/O
O
O
O
O
O
O
O
O
Address Bus
Data Bus
A
A
Byte Enable or Data Mask
A
A
A
A
A
A
A
Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used)
Asynchronous Memory Read Enable
Asynchronous Memory Write Enable
SDRAM Row Address Strobe
AWE
SRAS
SCAS
SDRAM Column Address Strobe
SWE
SDRAM Write Enable
SCKE
SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-refresh A
is used)
CLKOUT
O
O
O
SDRAM Clock Output
SDRAM A10 Signal
SDRAM Bank Select
B
A
A
SA10
SMS
Port F: GPIO and Multiplexed Peripherals
PF0/ETxD2/PPI D0/SPI1SEL2/TACLK6
I/O
GPIO/Ethernet MII Transmit D2/PPI Data 0/SPI1 Slave Select 2/Timer6 Alternate
C
Clock
PF1/ERxD2/PPI D1/PWM AH/TACLK7
PF2/ETxD3/PPI D2/PWM AL
I/O
I/O
I/O
GPIO/Ethernet MII Receive D2/PPI Data 1/PWM AH Output/Timer7 Alternate Clock C
GPIO/Ethernet Transmit D3/PPI Data 2/PWM AL Output
C
C
PF3/ERxD3/PPI D3/PWM BH/TACLK0
GPIO/Ethernet MII Data Receive D3/PPI Data 3/PWM BH Output/Timer0 Alternate
Clock
PF4/ERxCLK/PPI D4/PWM BL/TACLK1
PF5/ERxDV/PPI D5/PWM CH/TACI0
I/O
I/O
GPIO/Ethernet MII Receive Clock/PPI Data 4/PWM BL Out/Timer1 Alternate CLK
C
C
GPIO/Ethernet MII Receive Data Valid/PPI Data 5/PWM CH Out
/Timer0 Alternate Capture Input
PF6/COL/PPI D6/PWM CL/TACI1
PF7/SPI0SEL1/PPI D7/PWMSYNC
I/O
I/O
GPIO/Ethernet MII Collision/PPI Data 6/PWM CL Out/Timer1 Alternate Capture Input C
GPIO/SPI0 Slave Select 1/PPI Data 7/PWM Sync
C
Rev. B
| Page 17 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 7. Signal Descriptions
Driver
Type1
Signal Name
Type Function
PF8/MDC/PPI D8/SPI1SEL4
PF9/MDIO/PPI D9/TMR2
PF10/ETxD0/PPI D10/TMR3
PF11/ERxD0/PPI D11/PWM AH/TACI3
I/O
I/O
I/O
I/O
GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4
C
C
C
C
GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2
GPIO/Ethernet MII or RMII Transmit D0/PPI Data 10/Timer 3
GPIO/Ethernet MII Receive D0/PPI Data 11/PWM AH output
/Timer3 Alternate Capture Input
PF12/ETxD1/PPI D12/PWM AL
I/O
I/O
I/O
I/O
GPIO/Ethernet MII Transmit D1/PPI Data 12/PWM AL Output
GPIO/Ethernet MII or RMII Receive D1/PPI Data 13/PWM BH Output
GPIO/Ethernet MII Transmit Enable/PPI Data 14/PWM BL Out
GPIO/Ethernet MII PHY Interrupt/PPI Data 15/Alternate PWM Sync
C
C
C
C
PF13/ERxD1/PPI D13/PWM BH
PF14/ETxEN/PPI D14/PWM BL
PF152/RMII PHYINT/PPI D15/PWM_SYNCA
Port G: GPIO and Multiplexed Peripherals
PG0/MIICRS/RMIICRS/HWAIT 3/SPI1SEL3
PG1/ERxER/DMAR1/PWM CH
I/O
I/O
GPIO/Ethernet MII or RMII Carrier Sense or RMII Data Valid/HWAIT/SPI1 Slave Select3 C
GPIO/Ethernet MII or RMII Receive Error/DMA Req 1/PWM CH Out
GPIO/Ethernet MII or RMII Reference Clock/DMA Req 0/PWM CL Out
C
C
PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O
PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3
PG4/RSCLK0/RSI_DATA1/TMR5/TACI5
PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK
PG6/TFS0/RSI_DATA3/TMR0/PPIFS1
PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2
PG8/TSCLK0/RSI_CLK/TMR6/TACI6
PG9/DT0SEC/UART0TX/TMR4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT0 Primary Rx Data/RSI Data 0/SPI0 Slave Select 5/Timer3 Alternate CLK C
GPIO/SPORT0 Rx Clock/RSI Data 1/Timer 5/Timer5 Alternate Capture Input
GPIO/SPORT0 Rx Frame Sync/RSI Data 2/PPI Clock/External Timer Reference
GPIO/SPORT0 Tx Frame Sync/RSI Data 3/Timer0/PPI Frame Sync1
GPIO/SPORT0 Tx Primary Data/RSI Command/Timer 1/PPI Frame Sync2
GPIO/SPORT0 Tx Clock/RSI Clock/Timer 6/Timer6 Alternate Capture Input
GPIO/SPORT0 Secondary Tx Data/UART0 Transmit/Timer 4
D
C
C
C
D
C
C
C
PG10/DR0SEC/UART0RX/TACI4
GPIO/SPORT0 Secondary Rx Data/UART0 Receive/Timer4 Alternate Capture Input
PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2
GPIO/SPI0 Slave Device Select/Asynchronous Memory Bank Select 2/SPI1 Slave
Select 5/Timer2 Alternate CLK
PG12/SPI0SCK/PPICLK/TMRCLK/PTP_PPS
PG13/SPI0MISO4/TMR0/PPIFS1/
I/O
I/O
GPIO/SPI0 Clock/PPI Clock/External Timer Reference/PTP Pulse Per Second Out
GPIO/SPI0 Master In Slave Out/Timer0/PPI Frame Sync1/PTP Clock Out
D
C
PTP_CLKOUT
PG14/SPI0MOSI/TMR1/PPIFS2/PWM TRIP
/PTP_AUXIN
I/O
I/O
GPIO/SPI0 Master Out Slave In/Timer 1/PPI Frame Sync2/PWM Trip/PTP Auxiliary
Snapshot Trigger Input
C
C
PG15/SPI0SEL2/PPIFS3/AMS3
GPIO/SPI0 Slave Select 2/PPI Frame Sync3/Asynchronous Memory Bank Select 3
Port H: GPIO and Multiplexed Peripherals
PH0/DR1PRI/SPI1SS/RSI_DATA4
PH1/RFS1/SPI1MISO/RSI_DATA5
PH2/RSCLK1/SPI1SCK/RSI DATA6
PH3/DT1PRI/SPI1MOSI/RSI DATA7
PH4/TFS1/AOE/SPI0SEL3/CUD
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT1 Primary Rx Data/SPI1 Device Select/RSI Data 4
GPIO/SPORT1 Rx Frame Sync/SPI1 Master In Slave Out/RSI Data 5
GPIO/SPORT1 Rx Clock/SPI1 Clock/RSI Data 6
C
C
D
C
C
GPIO/SPORT1 Primary Tx Data/SPI1 Master Out Slave In/RSI Data 7
GPIO/SPORT1 Tx Frame Sync/Asynchronous Memory Output Enable/SPI0 Slave
Select 3/Counter Up Direction
PH5/TSCLK1/ARDY/PTP_EXT_CLKIN/CDG
PH6/DT1SEC/UART1TX/SPI1SEL1/CZM
PH7/DR1SEC/UART1RX/TMR7/TACI2
I/O
I/O
I/O
GPIO/SPORT1 Tx Clock/Asynchronous Memory Hardware Ready Control/
External Clock for PTP TSYNC/Counter Down Gate
D
C
C
GPIO/SPORT1 Secondary Tx Data/UART1 Transmit/SPI1 Slave Select 1
/Counter Zero Marker
GPIO/SPORT1 Secondary Rx Data/UART1 Receive/Timer 7/Timer2 Alternate Clock
Input
Rev. B
| Page 18 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 7. Signal Descriptions
Driver
Type1
Signal Name
Port J
Type Function
PJ0:SCL
I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)
E
E
PJ1:SDA
I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)
Real Time Clock
RTXI
I
RTC Crystal Input (This ball should be pulled low when not used.)
RTC Crystal Output (Does not three-state during hibernate)
RTXO
O
JTAG Port
TCK
I
JTAG Clock
TDO
O
I
JTAG Serial Data Out
C
C
C
TDI
JTAG Serial Data In
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This signal should be pulled low if the JTAG port is not used.)
Emulation Output
EMU
O
Clock
CLKIN
I
Clock/Crystal Input
XTAL
O
O
Crystal Output (If CLKBUF is enabled, does not three-state during hibernate)
Buffered XTAL Output (If enabled, does not three-state during hibernate)
CLKBUF
Mode Controls
RESET
I
I
I
Reset
NMI
Non-maskable Interrupt (This signal should be pulled high when not used.)
Boot Mode Strap 2-0
BMODE2-0
Voltage Regulation Interface
PG
I
Power Good (This signal should be pulled low when not used.)
Wake up Indication (Does not three-state during hibernate)
ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page 20.
I/O Power Supply
EXT_WAKE
Power Supplies
VDDEXT
O
C
P
P
P
P
P
P
P
G
VDDINT
Internal Power Supply
VDDRTC
Real Time Clock Power Supply
VDDFLASH
VDDMEM
VPPOTP
Internal SPI Flash Power Supply
MEM Power Supply
OTP Programming Voltage
VDDOTP
OTP Power Supply
GND
Ground for All Supplies
1 See Output Drive Currents on Page 50 for more information about each driver type.
2 When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball
is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor.
3 Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity.
4 A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).
Rev. B
| Page 19 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
Conditions
Industrial Models
Min
1.14
1.10
1.33
1.7
Nominal
Max
1.47
1.47
1.47
1.9
Unit
V
VDDINT Internal Supply Voltage
Internal Supply Voltage
Internal Supply Voltage
Commercial Models
V
Automotive Models
V
1, 2
VDDEXT External Supply Voltage
1.8 V I/O, Nonautomotive Models
2.5 V I/O, Nonautomotive Models
3.3 V I/O, All Models
1.8
2.5
3.3
1.8
2.5
3.3
V
External Supply Voltage
External Supply Voltage
2.25
3.0
2.75
3.6
V
V
3
VDDMEM MEM Supply Voltage
1.8 V I/O, Nonautomotive Models
2.5 V I/O, Nonautomotive Models
3.3 V I/O, All Models
1.7
1.9
V
MEM Supply Voltage
MEM Supply Voltage
2.25
3.0
2.75
3.6
V
V
4
VDDRTC RTC Power Supply Voltage
2.25
1.7
3.6
V
4
VDDFLASH Internal SPI Flash Supply
1.8
2.5
1.9
V
Voltage
VDDOTP OTP Supply Voltage
VPPOTP OTP Programming Voltage
For Reads1
2.25
2.75
V
2.25
2.5
7.0
2.75
7.1
V
For Writes5
6.9
V
VIH
High Level Input Voltage6, 7
High Level Input Voltage6, 7
High Level Input Voltage6, 7
High Level Input Voltage
Low Level Input Voltage6, 7
Low Level Input Voltage6, 7
Low Level Input Voltage6, 7
Low Level Input Voltage
Junction Temperature
VDDEXT/VDDMEM = 1.90 V
VDDEXT/VDDMEM = 2.75 V
VDDEXT/VDDMEM = 3.6 V
1.2
V
1.7
V
2
V
8
VIHTWI
VIL
VDDEXT = 1.90 V/2.75 V/3.6 V
VDDEXT/VDDMEM = 1.7 V
0.7 x VBUSTWI
VBUSTWI
0.6
V
V
VDDEXT/VDDMEM = 2.25 V
VDDEXT/VDDMEM = 3.0 V
0.7
V
0.8
V
9
VILTWI
VDDEXT = Minimum
0.3 x VBUSTWI
+95
V
168-Ball CSP_BGA @ TAMBIENT = 0°C to +70°C
0
°C
°C
°C
°C
Junction Temperature
168-Ball CSP_BGA @ TAMBIENT = –40°C to +85°C –40
+105
Junction Temperature
176-Lead LQFP @ TAMBIENT = 0°C to +70°C
176-Lead LQFP @ TAMBIENT = –40°C to +85°C
0
+95
Junction Temperature
–40
+105
1 Must remain powered (even if the associated function is not used).
2 VDDEXT is the supply to the GPIO.
3 Pins/balls that use VDDMEM are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These pins/balls are not tolerant
to voltages higher than VDDMEM. When using any of the asynchronous memory signals AMS3–2, ARDY, or AOE VDDMEM and VDDEXT must be shorted externally.
4 If not used, power with VDDEXT
.
5 The VPPOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent
on voltage and junction temperature) over the lifetime of the part.
6 Bidirectional pins/balls (PF15–0, PG15–0, PH7–0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF51x are
3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
7 Parameter value applies to all input and bidirectional pins/balls except SDA and SCL.
8 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 8.
9 SDA and SCL are pulled up to VBUSTWI. See Table 8.
Rev. B
| Page 20 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 8 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Table 8. TWI_DT Field Selections and VDDEXT/VBUSTWI
TWI_DT
000 (default)
001
010
011
100
101
110
111 (reserved)
VDDEXT Nominal
VBUSTWI Minimum
2.97
1.7
2.97
2.97
4.5
2.25
2.25
—
VBUSTWI Nominal
VBUSTWI Maximum
Unit
V
V
V
V
V
V
V
—
3.3
1.8
2.5
1.8
3.3
1.8
2.5
—
3.3
1.8
3.3
3.3
5
2.5
2.5
—
3.63
1.98
3.63
3.63
5.5
2.75
2.75
—
Clock Related Operating Conditions
Table 9 describes the timing requirements for the processor
clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as
not to exceed the maximum core clock and system clock.
Table 10 describes phase-locked loop operating conditions.
Table 9. Core Clock (CCLK) Requirements
Nominal
Voltage Setting
Parameter
fCCLK
Maximum
400
Unit
Core Clock Frequency (VDDINT =1.33 V Minimum, All Models)
1.400 V
MHz
MHz
MHz
MHz
Core Clock Frequency (VDDINT =1.23 V Minimum, Industrial/Commercial Models)
Core Clock Frequency (VDDINT = 1.14 V Minimum, Industrial Models Only)
Core Clock Frequency (VDDINT = 1.10 V Minimum, Commercial Models Only)
1.300 V
300
1.200 V
200
1.150 V
200
Table 10. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
(Commercial/Industrial Models)
72
84
Instruction Rate1
MHz
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
Instruction Rate1
MHz
1 For more information, see Ordering Guide on Page 65.
Table 11. SCLK Conditions
VDDEXT/VDDMEM
1.8 V Nominal
V
DDEXT/VDDMEM
2.5 V or 3.3 V Nominal
Parameter1
Max
Max
Unit
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ 1.230 V
80
100
MHz
Minimum)
fSCLK
CLKOUT/SCLK Frequency (VDDINT < 1.230 V)
80
80
MHz
1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 28 on Page 31.
Rev. B
| Page 21 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Typical
Max
Unit
VOH
High Level Output Voltage
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
VDDEXT /VDDMEM = 1.7 V,
1.35
V
I
OH = –0.5 mA
VDDEXT /VDDMEM = 2.25 V,
IOH = –0.5 mA
2
V
V
V
VDDEXT /VDDMEM = 3.0 V,
IOH = –0.5 mA
2.4
VOL
VDDEXT /VDDMEM
=
0.4
10
1.7/2.25/3.0 V,
IOL = 2.0 mA
1
IIH
High Level Input Current
Low Level Input Current
VDDEXT /VDDMEM =3.6 V,
VIN = 3.6 V
μA
1
IIL
VDDEXT /VDDMEM =3.6 V, VIN = 0 V
10
75
10
μA
μA
μA
2
IIHP
High Level Input Current JTAG VDDEXT = 3.6 V, VIN = 3.6 V
3
IOZH
Three-State Leakage Current VDDEXT /VDDMEM= 3.6 V,
VIN = 3.6 V
4
IOZHTWI
Three-State Leakage Current VDDEXT =3.0 V, VIN = 5.5 V
10
10
8
μA
μA
pF
3
IOZL
Three-State Leakage Current VDDEXT /VDDMEM= 3.6 V, VIN = 0 V
5, 6
CIN
Input Capacitance
fIN = 1 MHz, TAMBIENT = 25°C,
VIN = 2.5 V
5
4, 6
CINTWI
Input Capacitance
fIN = 1 MHz, TAMBIENT = 25°C,
VIN = 2.5 V
15
pF
7
IDDDEEPSLEEP
VDDINT Current in Deep Sleep
Mode
VDDINT = 1.3 V, fCCLK = 0 MHz,
fSCLK = 0 MHz, TJ = 25°C,
ASF = 0.00
2.1
mA
IDDSLEEP
IDD-IDLE
VDDINT Current in Sleep Mode VDDINT = 1.3 V, fSCLK = 25 MHz,
TJ = 25°C
5.5
12
mA
mA
VDDINT Current in Idle
VDDINT = 1.3 V, fCCLK = 50 MHz,
fSCLK = 25 MHz, TJ = 25°C,
ASF = 0.41
IDD-TYP
VDDINT Current
VDDINT = 1.3 V, fCCLK = 300 MHz,
fSCLK = 25 MHz, TJ = 25°C,
ASF = 1.00
77
mA
mA
ꢀA
IDD-TYP
VDDINT Current
VDDINT = 1.4 V, fCCLK = 400 MHz,
fSCLK = 25 MHz, TJ = 25°C,
ASF = 1.00
108
40
8
IDDHIBERNATE
Hibernate State Current
VDDEXT =VDDMEM =VDDRTC = 3.30
VVDDOTP =VPPOTP =2.5 V,
TJ = 25°C, CLKIN = 0 MHz @ TJ
= 25°C
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJ = 25°C
20
ꢀA
8, 9
IDDSLEEP
VDDINT Current in Sleep Mode fCCLK = 0 MHz, fSCLK > 0 MHz
Table 13 +
mA10
(0.20 × VDDINT × fSCLK
)
8, 10
IDDDEEPSLEEP
VDDINT Current in Deep Sleep
Mode
fCCLK = 0 MHz, fSCLK = 0 MHz
Table 13
mA
Rev. B
|
Page 22 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Parameter
Test Conditions
Min
Typical
Max
Unit
10, 11
IDDINT
VDDINT Current
fCCLK> 0 MHz, fSCLK ≥ 0 MHz
Table 13 +
mA
(Table 14 × ASF) +
(0.20 × VDDINT × fSCLK
)
IDDFLASH1
IDDFLASH2
IDDFLASH3
IDDOTP
Flash Memory Supply Current 1
—Asynchronous Read
10
4
6
mA
ꢀA
Flash Memory Supply Current 2
—Standby
12
16
Flash Memory Supply Current 3
—Program and Erase
11
2
mA
mA
mA
ꢀA
VDDOTP Current
VDDOTP Current
VPPOTP Current
VPPOTP Current
VDDOTP = 2.5 V, TJ = 25°C,
OTP Memory Read
IDDOTP
VDDOTP = 2.5 V, TJ = 25°C,
OTP Memory Write
2
IPPOTP
VPPOTP = 2.5 V, TJ = 25°C,
OTP Memory Read
100
3
IPPOTP
VPPOTP = Table 19 V, TJ = 25°C,
OTP Memory Write
mA
1 Applies to input balls.
2 Applies to JTAG input balls (TCK, TDI, TMS, TRST).
3 Applies to three-statable balls.
4 Applies to bidirectional balls SCL and SDA.
5 Applies to all signal balls, except SCL and SDA.
6 Guaranteed, but not tested.
7 See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
8 Includes current on VDDEXT, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low.
9 Guaranteed maximum specifications.
10Unit for VDDINT is V (Volts). Unit for fSCLK is MHz.
11See Table 12 for the list of IDDINT power vectors covered.
The ASF is combined with the CCLK Frequency and VDDINT
dependent data in Table 14 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the IDDINT specification equation.
Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Table 12. Activity Scaling Factors (ASF)1
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 22 shows the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 13), and IDDINT specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (VDDINT) and
frequency (Table 14).
IDDINT Power Vector
IDD-PEAK
Activity Scaling Factor (ASF)
1.29
1.25
1.00
0.85
0.70
0.41
IDD-HIGH
IDD-TYP
IDD-APP
IDD-NOP
IDD-IDLE
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories (Table 12).
1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF51x
processors.
Rev. B
| Page 23 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 13. Static Current—IDD-DEEPSLEEP (mA)
1
Voltage (VDDINT
)
TJ (°C)1
–40
–20
0
1.10 V
0.9
1.15 V
1.0
1.20 V
1.0
1.25 V
1.1
1.30 V
1.1
1.35 V
1.2
1.40 V
1.3
1.45 V
1.7
1.50 V
1.9
1.0
1.1
1.2
1.3
1.4
1.6
1.7
1.9
2.0
1.2
1.3
1.4
1.6
1.8
2.0
2.2
2.3
2.5
25
1.8
1.9
2.1
2.3
2.5
2.8
3.1
3.3
3.7
40
2.4
2.6
2.8
3.0
3.3
3.7
4.0
4.4
4.9
55
3.3
3.5
3.8
4.3
4.6
5.0
5.5
6.1
6.7
70
4.6
5.0
5.4
6.0
6.4
7.0
7.7
8.4
9.2
85
6.5
7.1
7.7
8.3
9.1
9.9
10.8
15.0
16.6
11.8
16.1
18.0
12.8
17.5
19.4
100
9.2
10.0
10.8
11.7
12.7
13.7
15.3
105
10.3
11.1
12.1
13.1
14.2
1 Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20.
Table 14. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1
2
fCCLK
Voltage (VDDINT)
(MHz)2
1.10 V
N/A
1.15 V
N/A
1.20 V
N/A
1.25 V
N/A
1.30 V
93.4
82.4
71.4
60.4
49.4
38.4
27.4
1.35 V
97.7
86.2
74.7
63.2
51.7
40.2
28.7
1.40 V
102.1
90.1
1.45 V
106.5
94.0
1.50 V
111.0
98.0
400
350
300
250
200
150
100
N/A
N/A
N/A
N/A
N/A
N/A
64.8
54.8
44.7
34.7
24.7
68.1
57.5
47.0
36.5
26.0
78.1
81.5
85.0
N/A
N/A
66.1
69.0
71.9
40.2
31.1
22.0
42.5
32.9
23.4
54.1
56.5
58.9
42.1
44.0
45.9
30.1
31.5
33.0
1 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 22.
2 Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20.
FLASH MEMORY CHARACTERISTICS
Table 15. Reliability Characteristics
Parameter
Min
100,000
100
Units
Cycles
Years
Test Method
JEDEC Standard A117
JEDEC Standard A103
NEND
TDR
Endurance
Data Retention
Table 16. AC Operating Characteristics
Parameter
Min
Max
25
75
Units
MHz
ms
1
fCLK
TSE
Serial Clock Frequency
Sector-Erase
TBE
TSCE
TBP
Block-Erase
Chip-Erase
Byte-Program
75
150
60
ms
ms
ꢀs
2
1 Maximum clock frequency for Read instruction, 0x03, is 20 MHz.
2 AAI-Word Program TBP maximum specification is also at 60 ꢀs maximum time.
Rev. B
| Page 24 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 19. Maximum OTP Memory Programming Time
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 17 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature
VPPOTP
Voltage (V)
25°C
85°C
110°C
25 sec
12 sec
4.5 sec
6.9
7.0
7.1
6000 sec
2400 sec
1000 sec
100 sec
44 sec
18 sec
Table 17. Absolute Maximum Ratings
Table 20 and Table 21 specify the maximum total source/sink
(IOH/IOL) current for a group of pins. Permanent damage can
occur if this value is exceeded. To understand this specification,
if pins PF9, PF8, PF7, PF6, and PF5 from Group 1 in Table 21
table were sourcing or sinking 2 mA each, the total current for
those pins would be 10 mA. This would allow up to 70 mA total
that could be sourced or sunk by the remaining pins in the
group without damaging the device. Note that the VOH and VOL
specifications have separate per-pin maximum current require-
ments as shown in the Electrical Characteristics table.
Parameter
Rating
Internal Supply Voltage (VDDINT
)
–0.3 V to +1.50 V
–0.3 V to +3.8 V
External (I/O) Supply Voltage
(VDDEXT/VDDMEM
)
Input Voltage1, 2
Input Voltage1, 3
–0.5 V to +3.6 V
–0.5 V to +5.5 V
Output Voltage Swing
–0.5 V to
VDDEXT/VDDMEM +0.5 V
IOH/IOL Current per Pin Group4
Storage Temperature Range
80 mA (max)
–65°C to +150°C
+110°C
Table 20. Total Current Pin Groups–VDDMEM Groups
Group Pins in Group
Junction Temperature While biased
1
2
3
4
5
6
7
8
DATA15, DATA14, DATA13, DATA12, DATA11, DATA10
DATA9, DATA8, DATA7, DATA6, DATA5, DATA4
DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18
ADDR17, ADDR16, ADDR15, ADDR14, ADDR13
ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7
ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1
ABE1, ABE0, SA10, SWE, SCAS, SRAS
1 Applies to 100% transient duty cycle. For other duty cycles see Table 18.
2 Applies only when VDDEXT is within specifications. When VDDEXT is outside speci-
fications, the range is VDDEXT 0.2.
3 Applies to signals SCL, SDA.
4 For more information, see the information preceding Table 20 and Table 21.
Table 18. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)2
–0.50
VIN Max (V)2
+3.80
Maximum Duty Cycle3
SMS, SCKE, AMS1, ARE, AWE, AMS0, CLKOUT
100%
40%
25%
15%
10%
Table 21. Total Current Pin Groups–VDDEXT Groups
–0.70
+4.00
Group
Pins in Group
–0.80
+4.10
1
2
3
PF9, PF8, PF7, PF6, PF5, PF4, PF3, PF2
PF1, PF0, PG15, PG14, PG13, PG12, PG11, PG10
–0.90
+4.20
–1.00
+4.30
PG9, PG8, PG7, PG6, PG5, PG4, PG3, PG2, BMODE0,
BMODE1, BMODE2
1 Applies to all signal pins/balls with the exception of CLKIN, XTAL.
2 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
4
5
6
7
PG1, PG0, TDO, EMU, TDI, TCK, TRST, TMS
RESET, NMI, CLKBUF
PH7, PH6, PH5, PH4, PH3, PH2, PH1, PH0
PF15, PF14, PF13, PF12, PF11, SDA, SCL, PF10
3 Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. The is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
When programming OTP memory on the ADSP-BF51x proces-
sor, the VPPOTP pin/ball must be set to the write value specified in
the Operating Conditions on Page 20. There is a finite amount
of cumulative time that the write voltage may be applied
(dependent on voltage and junction temperature) to VPPOTP over
the lifetime of the part. Therefore, maximum OTP memory pro-
gramming time for the processor is shown in Table 19.
Rev. B
| Page 25 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
PACKAGE INFORMATION
The information presented in Figure 6 and Table 22 provides
details about the package branding for the processor. For a com-
plete listing of product availability, see Ordering Guide on
Page 65.
a
ADSP-BF51x
tppZccc
vvvvvv.x n.n
#yyww country_of_origin
B
Figure 6. Product Information on Package
Table 22. Package Brand Information
Brand Key
Field Description
Product Name
ADSP-BF51x
t
Temperature Range
Package Type
pp
Z
Lead Free Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
ccc
vvvvvv.x
n.n
#
RoHS Compliance Designator
Date Code
yyww
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. B
| Page 26 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 23 and Figure 7 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 9 , Table 10,
and Table 11 on Page 21, combinations of CLKIN and clock
multipliers must not select core/peripheral clocks in excess of
the processor’s speed grade.
Table 23. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
CLKIN Frequency (Commercial/Industrial Models1, 2, 3, 4 12
50
50
MHz
MHz
ns
fCKIN
CLKIN Frequency (Automotive Models)1, 2, 3, 4
CLKIN Low Pulse1
14
tCKINL
tCKINH
tWRST
10
CLKIN High Pulse1
10
ns
RESET Asserted Pulse Width Low5
11 × tCKIN
ns
Switching Characteristic
tBUFDLAY
CLKIN to CLKBUF Delay
11
ns
1 Applies to PLL bypass mode and PLL nonbypass mode.
2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 9 through Table 11 on Page 21.
3 The tCKIN period (see Figure 7) equals 1/fCKIN
.
4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5 Applies after power-up sequence is complete. See Table 24 and Figure 8 for power-up reset timing.
tCKIN
CLKIN
tBUFDLAY
tCKINL
tCKINH
tBUFDLAY
CLKBUF
tWRST
RESET
Figure 7. Clock and Reset Timing
Table 24. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, and CLKIN Pins are
Stable and Within Specification
3500 × tCKIN
ns
Rev. B
| Page 27 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
Figure 8. Power-Up Reset Timing
an active Program or Erase operation aborts the operation and
data of the targeted address range may be corrupted or lost due
to the aborted erase or program operation. The device exits AAI
Programming Mode in progress and places the SO pin in high
impedance state.
Flash Reset Timing
Driving the RESET pin low resets the Flash device. Driving the
RESET pin high puts the device in normal operating mode. The
SO pin is in high impedance state while the device is in reset. A
successful reset will reset the status register to its power-up state.
See Table 25 for default power-up modes. A device reset during
Table 25. RESET Timing
Parameter
Min
Max
Unit
Timing Requirements
tRECR
tRECP
fRECE
Reset Recovery from Read
Reset Recovery from Program
Reset Recovery from Erase
100
10
1
ns
ꢀs
ms
SCK
RST
CE
tRECR
tRECP
tRECE
Figure 9. Flash Reset Timing
Rev. B
| Page 28 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Asynchronous Memory Read Cycle Timing
Table 26. Asynchronous Memory Read Cycle Timing
VDDMEM
1.8V Nominal
VDDMEM
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
1.2
4
2.1
0.8
4
ns
ns
ns
ns
tHDAT
tSARDY
tHARDY
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
0.2
0.2
Switching Characteristics
tDO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
6
6
ns
ns
tHO
0.8
0.8
1 Output pins/balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
2 CYCLES
1 CYCLE
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
AOE
ARE
tDO
tHO
tSARDY
tHARDY
ARDY
tSARDY
tHARDY
tSDAT
tHDAT
DATA 15–0
Figure 10. Asynchronous Memory Read Cycle Timing
Rev. B
| Page 29 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Asynchronous Memory Write Cycle Timing
Table 27. Asynchronous Memory Write Cycle Timing
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
tHARDY
Switching Characteristics
ARDY Setup Before CLKOUT
4
ns
ns
ARDY Hold After CLKOUT
0.2
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6
6
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
0
tHO
0.8
1 Output pins/balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
PROGRAMMED
WRITE
ACCESS
2 CYCLES
ACCESS
EXTEND HOLD
1 CYCLE 1 CYCLE
SETUP
2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
tDO
tHO
AWE
ARDY
tSARDY
tHARDY
tENDAT
tHARDY
tDDAT
tSARDY
DATA 15–0
Figure 11. Asynchronous Memory Write Cycle Timing
Rev. B
| Page 30 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
SDRAM Interface Timing
Table 28. SDRAM Interface Timing
VDDMEM
1.8V Nominal
VDDMEM
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSSDAT
tHSDAT
Data Setup Before CLKOUT
Data Hold After CLKOUT
1.5
1.3
1.5
0.8
ns
ns
Switching Characteristics
tSCLK
CLKOUT Period1
12.5
5
10
4
ns
ns
ns
ns
ns
ns
ns
tSCLKH
tSCLKL
tDCAD
tHCAD
tDSDAT
tENSDAT
CLKOUT Width High
CLKOUT Width Low
5
4
Command, Address, Data Delay After CLKOUT2
Command, Address, Data Hold After CLKOUT2
Data Disable After CLKOUT
5
4
5
1
1
5.5
Data Enable After CLKOUT
0
0
1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 11 on Page 21. Package type and reduced supply voltages affect the best-case value listed here.
2 Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
CLKOUT
tSSDAT
tHSDAT
tSCLKL
tSCLKH
DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA (OUT)
tDCAD
tHCAD
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 12. SDRAM Interface Timing
Rev. B
| Page 31 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
External DMA Request Timing
Table 29 and Figure 13 describe the External DMA Request
operations.
Table 29. External DMA Request Timing1
VDDMEM/VDDEXT
1.8 V Nominal
V
DDMEM/VDDEXT
2.5 V/3.3 V Nominal
Min Max
Parameter
Min
Max
Unit
Timing PRequirements
tDR
DMARx Asserted to CLKOUT High Setup
9
0
7.2
ns
ns
ns
ns
tDH
CLKOUT High to DMARx Deasserted Hold Time
DMARx Active Pulse Width
0
tDMARACT
tSCLK + 1
tSCLK + 1
tDMARINACT
DMARx Inactive Pulse Width
1.75 × tSCLK
1.75 × tSCLK
1 Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and
V
DDMEM are NOT equal may require level shifting logic for correct operation.
CLKOUT
tDS
tDH
DMAR0/1
(ACTIVE LOW)
tDMARACT
tDMARINACT
DMAR0/1
(ACTIVE HIGH)
Figure 13. External DMA Request Timing
Rev. B
| Page 32 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Parallel Peripheral Interface Timing
Table 30 and Figure 15 on Page 33, Figure 21 on Page 38, and
Figure 24 on Page 40 describe parallel peripheral interface
operations.
Table 30. Parallel Peripheral Interface Timing
VDDEXT
1.8 V Nominal
VDDEXT
2.5 V/3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tPCLKW
tPCLK
Timing Requirements - GP Input and Frame Capture Modes
PPI_CLK Width
tSCLK – 1.5
tSCLK – 1.5
ns
ns
PPI_CLK Period
2 × tSCLK – 1.5
2 × tSCLK – 1.5
tPSUD
tSFSPE
External Frame Sync Startup Delay1
4 × tPCLK
6.7
4 × tPCLK
6.7
ns
ns
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
tSDRPE
tHDRPE
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
1.75
4.1
2
1.75
3.5
ns
ns
ns
1.6
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
8
8
8
ns
ns
ns
ns
1.7
2.3
1.7
1.9
8.2
1 The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
guaranteed to be received correctly by the PPI peripheral.
PPI_CLK
tPSUD
PPI_FS1/2
Figure 14. PPI with External Frame Sync Timing
DATA SAMPLED /
DATA SAMPLED /
FRAME SYNC SAMPLED
FRAME SYNC SAMPLED
PPI_CLK
tPCLKW
tSFSPE
tHFSPE
tPCLK
PPI_FS1/2
PPI_DATA
tSDRPE
tHDRPE
Figure 15. PPI GP Rx Mode with External Frame Sync Timing
Rev. B
| Page 33 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tHFSPE
tPCLKW
tPCLK
PPI_FS1/2
PPI_DATA
tDDTPE
tHDTPE
Figure 16. PPI GP Tx Mode with External Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
PPI_FS1/2
PPI_DATA
tDFSPE
tPCLKW
tHOFSPE
tPCLK
tSDRPE
tHDRPE
Figure 17. PPI GP Rx Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
tPCLK
DATA
DRIVEN
PPI_CLK
PPI_FS1/2
PPI_DATA
tDFSPE
tPCLKW
tHOFSPE
tDDTPE
tHDTPE
Figure 18. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. B
| Page 34 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
RSI Controller Timing
Table 31 and Figure 19 describe RSI controller timing. Table 32
and Figure 20 describe RSI controller (high speed) timing.
Table 31. RSI Controller Timing
Parameter
Min
Max
Unit
Timing Requirements
tISU
tIH
Input Setup Time
Input Hold Time
5.6
2
ns
ns
Switching Characteristics
1
fPP
Clock Frequency Data Transfer Mode
Clock Frequency Identification Mode
Clock Low Time
0
25
400
MHz
kHz
ns
fOD
tWL
tWH
1002
10
10
Clock High Time
ns
tTLH
tTHL
Clock Rise Time
Clock Fall Time
Output Delay Time During Data Transfer Mode
Output Delay Time During Identification Mode
10
10
14
50
ns
ns
ns
ns
tODLY
tODLY
1 tPP = 1/fPP
2 Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
VOH (MIN)
tPP
SD_CLK
tTHL
tTLH
tISU
tIH
VOL (MAX)
tWL
tWH
INPUT
tODLY
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 19. RSI Controller Timing
Rev. B
| Page 35 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 32. RSI Controller Timing (High Speed Mode)
Parameter
Min
Max
Unit
Timing Requirements
tISU
tIH
Input Setup Time
Input Hold Time
5.6
2
ns
ns
Switching Characteristics
1
fPP
Clock Frequency Data Transfer Mode
Clock Low Time
Clock High Time
0
7
7
50
MHz
ns
ns
tWL
tWH
tTLH
tTHL
tODLY
tOH
Clock Rise Time
Clock Fall Time
Output Delay Time During Data Transfer Mode
Output Hold Time
3
3
4
ns
ns
ns
ns
2.75
1 tPP = 1/fPP
VOH (MIN)
tPP
SD_CLK
tTHL
tTLH
tISU
tIH
VOL (MAX)
tWL
tWH
INPUT
tODLY
tOH
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 20. RSI Controller Timing (High Speed Mode)
Rev. B
| Page 36 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Serial Ports
Table 33 through Table 36 on Page 40 and Figure 21 on Page 38
through Figure 24 on Page 40 describe serial port operations.
Table 33. Serial Ports—External Clock
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
1
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
3
3
ns
ns
ns
ns
ns
ns
ns
ns
1
1
tHFSE
3
3
tSDRE
3
3
1
tHDRE
tSCLKEW
tSCLKE
3.5
7
3
TSCLKx/RSCLKx Width
4.5
TSCLKx/RSCLKx Period
2 × tSCLK
4 × tSCLKE
2 × tSCLK
4 × tSCLKE
4 × tSCLKE
2
tSUDTE
Start-Up Delay From SPORT Enable To First External TFSx
2
tSUDRE
Start-Up Delay From SPORT Enable To First External RFSx 4 × tSCLKE
Switching Characteristics
3
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
10
10
10
10
ns
ns
3
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated 0
TFSx/RFSx)
0
0
3
tDDTE
Transmit Data Delay After TSCLKx
ns
ns
3
tHDTE
Transmit Data Hold After TSCLKx
0
1 Referenced to sample edge.
2 Verified in design but untested.
3 Referenced to drive edge.
Table 34. Serial Ports—Internal Clock
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
1
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
11
9.6
ns
ns
ns
ns
1
1
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
–1.5
11
–1.5
9.6
tSDRI
1
tHDRI
–1.5
–1.5
Switching Characteristics
2
tDFSI
TFSx/RFSxDelayAfterTSCLKx/RSCLKx(InternallyGenerated
TFSx/RFSx)
3
3
3
3
ns
ns
2
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated −2
TFSx/RFSx)
−1
2
tDDTI
Transmit Data Delay After TSCLKx
ns
ns
ns
2
tHDTI
Transmit Data Hold After TSCLKx
−1.8
−1.5
tSCLKIW
TSCLKx/RSCLKx Width
10
8
1 Referenced to sample edge.
2 Referenced to drive edge.
Rev. B
|
Page 37 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
tSCLKE
tSCLKIW
tSCLKEW
RSCLKx
RSCLKx
tDFSI
tDFSE
tHOFSI
tHOFSE
RFSx
RFSx
(OUTPUT)
(OUTPUT)
tSFSI
tHFSI
tSFSE
tHFSE
RFSx
RFSx
(INPUT)
(INPUT)
tHDRE
tSDRI
tHDRI
tSDRE
DRx
DRx
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
SAMPLE EDGE
tSCLKE
tSCLKIW
tSCLKEW
TSCLKx
TSCLKx
tDFSI
tDFSE
tHOFSI
tHOFSE
TFSx
TFSx
(OUTPUT)
(OUTPUT)
tSFSI
tHFSI
tSFSE
tHFSE
TFSx
TFSx
(INPUT)
(INPUT)
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
Figure 21. Serial Ports
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
FIRST
Figure 22. Serial Port Start Up with External Clock and Frame Sync
Rev. B
| Page 38 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 35. Serial Ports—Enable and Three-State1
Parameter
Min
0
Max
Unit
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable Delay from External TSCLKx
ns
ns
ns
ns
Data Disable Delay from External TSCLKx
Data Enable Delay from Internal TSCLKx
Data Disable Delay from Internal TSCLKx
tSCLK + 1
tSCLK + 1
–2.0
1 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
TSCLKx
DTx
tDTENE/I
tDDTTE/I
Figure 23. Enable and Three-State
Rev. B
| Page 39 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 36. External Late Frame Sync
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Switching Characteristics
1, 2
tDDTLFSE
Data Delay from Late External TFSx or External RFSx with
MCE = 1, MFD = 0
12
10
ns
ns
1, 2
tDTENLFSE
Data Enable from Late FS or MCE = 1, MFD = 0
0
0
1 MCE = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFSE
.
2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.
EXTERNAL RFSx IN MULTI-CHANNEL MODE
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
DTx
1ST BIT
LATE EXTERNAL TFSx
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
TSCLKx
TFSx
tDDTLFSE
DTx
1ST BIT
Figure 24. External Late Frame Sync
Rev. B
| Page 40 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Serial Peripheral Interface (SPI) Port—Master Timing
Table 37 and Figure 25 describe SPI port master operations.
Table 37. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSSPIDM
tHSPIDM
Switching Characteristics
Data Input Valid to SCK Edge (Data Input Setup)
11.6
–1.5
9.6
ns
ns
SCK Sampling Edge to Data Input Invalid
–1.5
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
SPISELx low to First SCK Edge
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
tHDSM
Last SCK Edge to SPISELx High
Sequential Transfer Delay
2 × tSCLK –1.5
2 × tSCLK–1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
tSPITDM
tDDSPIDM
tHDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
6
6
–1
–1
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
tSPITDM
SPIxSCK
(OUTPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
tHSPIDM
CPHA = 0
SPIxMISO
(INPUT)
Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. B
| Page 41 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 38 and Figure 26 describe SPI port slave operations.
Table 38. Serial Peripheral Interface (SPI) Port—Slave Timing
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
Serial Clock High Period
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
tSPITDS
tSDSCI
tSSPID
tHSPID
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
2
1.6
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
0
0
12
11
10
0
0
10.3
9
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
10
0
0
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
tHSPID
CPHA = 0
tSSPID
SPIxMOSI
(INPUT)
Figure 26. Serial Peripheral Interface (SPI) Port—Slave Timing
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-BF51x Hardware Reference Manual.
Rev. B
| Page 42 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
General-Purpose Port Timing
Table 39 and Figure 27 describe general-purpose
port operations.
Table 39. General-Purpose Port Timing
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
tSCLK + 1
0
Max
Unit
ns
Timing Requirement
tWFI
Switching Characteristics
tGPOD General-Purpose Port Signal Output Delay from CLKOUT Low 0
General-Purpose Port Signal Input Pulse Width
tSCLK + 1
11
8.5
ns
CLKOUT
GPIO OUTPUT
GPIO INPUT
tGPOD
tWFI
Figure 27. General-Purpose Port Timing
Timer Clock Timing
Table 40 and Figure 28 describe timer clock timing.
Table 40. Timer Clock Timing
Parameter
Min
Max
Unit
Switching Characteristic
tTODP
Timer Output Update Delay After PPICLK High
12
ns
PPI_CLK
tTODP
TMRx OUTPUT
Figure 28. Timer Clock Timing
Rev. B
| Page 43 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Timer Cycle Timing
Table 41 and Figure 29 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (fSCLK/2) MHz.
Table 41. Timer Cycle Timing
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Characteristics
1
tWL
tWH
Timer Pulse Width Input Low (Measured In SCLK Cycles)
tSCLK
tSCLK
10
tSCLK
tSCLK
7
ns
ns
ns
ns
1
Timer Pulse Width Input High (Measured In SCLK Cycles)
Timer Input Setup Time Before CLKOUT Low
Timer Input Hold Time After CLKOUT Low
2
tTIS
tTIH
2
–2
–2
Switching Characteristics
tHTO Timer Pulse Width Output (Measured In SCLK Cycles)
tTOD Timer Output Update Delay After CLKOUT High
tSCLK – 1.5
(232–1)tSCLK
6
tSCLK – 1
(232–1)tSCLK
6
ns
ns
1 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 29. Timer Cycle Timing
Rev. B
| Page 44 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Up/Down Counter/Rotary Encoder Timing
Table 42. Up/Down Counter/Rotary Encoder Timing
VDDEXT
VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tWCOUNT
tCIS
Up/Down Counter/Rotary Encoder Input Pulse Width
tSCLK + 1
tSCLK + 1
ns
ns
ns
Counter Input Setup Time Before CLKOUT Low1
Counter Input Hold Time After CLKOUT Low1
9
7
0
tCIH
0
1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
CLKOUT
tCIS
tCIH
CUD/CDG/CZM
tWCOUNT
Figure 30. Up/Down Counter/Rotary Encoder Timing
10/100 Ethernet MAC Controller Timing
Table 43 through Table 48 and Figure 31 through Figure 36
describe the 10/100 Ethernet MAC Controller operations.
Table 43. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter1
Min
Max
Min
Max
Unit
Timing Requirements
tERXCLKF
tERXCLKW
tERXCLKIS
tERXCLKIH
ERxCLK Frequency (fSCLK = SCLK Frequency)
None
25 + 1%
None
25 + 1%
MHz
ns
ERxCLK Width (tERxCLK = ERxCLK Period)
tERxCLK x 40%
7.5
tERxCLK x 60%
tERxCLK x 35%
tERxCLK x 65%
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
7.5
7.5
ns
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5
ns
1 MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
tERXCLK
tERXCLKW
ERx_CLK
ERxD3–0
ERxDV
ERxER
tERXCLKIS tERXCLKIH
Figure 31. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Rev. B
| Page 45 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 44. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter1
Min
Max
Min
Max
Unit
Switching Characteristics
tETF
ETxCLK Frequency (fSCLK = SCLK Frequency)
None
25 + 1%
None
25 + 1%
MHz
ns
tETXCLKW
tETXCLKOV
tETXCLKOH
ETxCLK Width (tETxCLK = ETxCLK Period)
tETxCLK × 40% tETxCLK × 60%
20
tETxCLK × 35% tETxCLK × 65%
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 0
20
ns
0
ns
1 MII outputs synchronous to ETxCLK are ETxD3–0.
tETXCLK
MIITxCLK
tETXCLKW
tETXCLKOH
ETxD3–0
ETxEN
tETXCLKOV
Figure 32. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Table 45. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Parameter1
Min
Max
Min
None
Max
Unit
Timing Requirements
tEREFCLKF
tEREFCLKW
tEREFCLKIS
REF_CLK Frequency (fSCLK = SCLK Frequency)
None
50 + 1%
50 + 1%
MHz
ns
EREF_CLK Width (tEREFCLK = EREFCLK Period)
tEREFCLK × 40% tEREFCLK × 60%
4
tEREFCLK × 35% tEREFCLK × 65%
4
Rx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)
ns
tEREFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In 2
Hold)
2
ns
1 RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
tREFCLK
tREFCLKW
RMII_REF_CLK
ERxD1–0
ERxDV
ERxER
tREFCLKIS tREFCLKIH
Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Rev. B
| Page 46 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 46. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter1
Min
Max
Unit
Switching Characteristics
tEREFCLKOV
tEREFCLKOH
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
8.1
ns
ns
2
1 RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
tREFCLK
RMII_REF_CLK
tREFCLKOH
ETxD1–0
ETxEN
tREFCLKOV
Figure 34. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Rev. B
| Page 47 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 47. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter
Min
Max
Unit
Timing Requirements
tECOLH
COL Pulse Width High1
tETxCLK × 1.5
tERxCLK × 1.5
ns
ns
tECOLL
COL Pulse Width Low1
tETxCLK × 1.5
tERxCLK × 1.5
ns
ns
tECRSH
tECRSL
CRS Pulse Width High2
CRS Pulse Width Low2
tETxCLK × 1.5
ns
ns
tETxCLK × 1.5
1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2 The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
MIICRS, COL
tECRSH
tECOLH
tECRSL
tECOLL
Figure 35. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
Table 48. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter1
Min
Max
Unit
Timing Requirements
tMDIOS
tMDCIH
Switching Characteristics
tMDCOV MDC Falling Edge to MDIO Output Valid
tMDCOH MDC Falling Edge to MDIO Output Invalid (Hold)
MDIO Input Valid to MDC Rising Edge (Setup)
11.5
0
ns
ns
MDC Rising Edge to MDIO Input Invalid (Hold)
25
ns
ns
–1.25
1 MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
MDC (OUTPUT)
tMDCOH
MDIO (OUTPUT)
tMDCOV
MDIO (INPUT)
tMDIOS
tMDCIH
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Station Management
Rev. B
| Page 48 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
JTAG Test And Emulation Port Timing
Table 49 and Figure 37 describe JTAG port operations.
Table 49. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
4
ns
tSTAP
tHTAP
TDI, TMS Setup Before TCK High
ns
TDI, TMS Hold After TCK High
4
ns
1
tSSYS
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width2 (measured in TCK cycles)
4
ns
1
tHSYS
tTRSTW
Switching Characteristics
tDTDO TDO Delay from TCK Low
System Outputs Delay After TCK Low
5
ns
4
TCK
10
13
ns
ns
3
tDSYS
0
1 System Inputs = DATA15–0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH7–0, MDIO, TD1, TMS, RESET, NMI, BMODE2–0.
2 50 MHz Maximum
3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
DT0PRI, DT0SEC, PF15–0, PG15–0, PH7–0, MDC, MDIO.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 37. JTAG Port Timing
Rev. B
| Page 49 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
OUTPUT DRIVE CURRENTS
Figure 38 through Figure 52 show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF51xF
processors.
The curves represent the current drive capability of the output
drivers. See Table 7 on Page 17 for information about which
driver type corresponds to a particular ball.
240
200
VDDEXT = 3.6V @ – 40
°C
VDDEXT = 3.6V @ – 40
°C
200
160
120
80
160
120
80
VDDEXT = 3.3V @ 25
°C
VDDEXT = 3.3V @ 25
°C
VDDEXT = 3.0V @ 105°C
VDDEXT = 3.0V @ 105°C
V
OH
V
OH
40
40
0
0
–40
–40
–80
–120
–160
–80
V
OL
V
OL
–120
–160
–200
–200
–240
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 41. Driver Type B Current (3.3V VDDEXT/VDDMEM
)
Figure 38. Driver Type A Current (3.3V VDDEXT/VDDMEM
)
160
120
80
160
120
VDDEXT = 2.75V @ – 40
VDDEXT = 2.5V @ 25
°C
VDDEXT = 2.75V @ – 40
VDDEXT = 2.5V @ 25
°C
°
C
°C
V
DDEXT = 2.25V @ 105°C
V
DDEXT = 2.25V @ 105°C
80
40
40
V
OH
V
OH
0
0
–40
–80
–40
–80
V
OL
–120
–160
–200
V
OL
–120
–160
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 42. Driver Type B Current (2.5V VDDEXT/VDDMEM
)
Figure 39. Driver Type A Current (2.5V VDDEXT/VDDMEM
)
80
60
80
60
VDDEXT = 1.9V @ – 40
VDDEXT = 1.8V @ 25
°C
VDDEXT = 1.9V @ – 40
VDDEXT = 1.8V @ 25
°C
°
C
°
C
VDDEXT = 1.7V @ 105°C
VDDEXT = 1.7V @ 105°C
40
20
40
20
V
OH
V
OH
0
0
–20
–20
–40
–60
V
V
OL
OL
–40
–60
–80
–80
–100
0.5
1.0
1.5
0.5
1.0
1.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 40. Driver Type A Current (1.8V VDDEXT/VDDMEM
)
Figure 43. Driver Type B Current (1.8V VDDEXT/VDDMEM)
Rev. B
| Page 50 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
100
80
160
VDDEXT = 3.6V @ – 40
°
C
VDDEXT = 3.6V @ – 40
°C
120
80
40
0
VDDEXT = 3.3V @ 25
°C
VDDEXT = 3.3V @ 25°C
60
40
VDDEXT = 3.0V @ 105
°
C
VDDEXT = 3.0V @ 105°C
V
V
OH
OH
20
0
–20
–40
–40
–80
V
OL
–60
–80
V
OL
–120
–160
–100
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 44. Driver Type C Current (3.3V VDDEXT/VDDMEM
)
Figure 47. Driver Type D Current (3.3V VDDEXT/VDDMEM
)
80
120
100
VDDEXT = 2.75V @ – 40
VDDEXT = 2.5V @ 25
°C
VDDEXT = 2.75V @ – 40
VDDEXT = 2.5V @ 25
°C
°C
60
40
20
°C
80
60
V
DDEXT = 2.25V @ 105°C
VDDEXT = 2.25V @ 105°C
40
V
OH
V
20
OH
0
0
–20
–40
–60
–80
–100
–120
–20
–40
–60
V
V
OL
OL
–80
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 45. Drive Type C Current (2.5V VDDEXT/VDDMEM
)
Figure 48. Driver Type D Current (2.5V VDDEXT/VDDMEM
)
40
30
60
VDDEXT = 1.9V @ – 40
VDDEXT = 1.8V @ 25
°C
VDDEXT = 1.9V @ – 40
VDDEXT = 1.8V @ 25
°C
°
C
°
C
40
20
VDDEXT = 1.7V @ 105°C
VDDEXT = 1.7V @ 105°C
20
10
V
OH
V
OH
0
0
–20
–40
–60
–10
V
OL
–20
–30
V
OL
–40
0.5
1.0
1.5
0
0.5
1.0
1.5
2
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 46. Driver Type C Current (1.8V VDDEXT/VDDMEM
)
Figure 49. Driver Type D Current (1.8V VDDEXT/VDDMEM
)
Rev. B
| Page 51 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
TEST CONDITIONS
60
VDDEXT = 3.6V @ – 40
°C
50
40
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 53
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point VMEAS is VDDEXT/2
or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/2.5 V/3.3 V.
VDDEXT = 3.3V @ 25
°C
VDDEXT = 3.0V @ 105°C
30
20
10
0
–10
–20
–30
–40
–50
–60
INPUT
OR
OUTPUT
V
V
MEAS
MEAS
V
OL
Figure 53. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Output Enable Time Measurement
Figure 50. Driver Type E Current (3.3V VDDEXT/VDDMEM
)
Output signals are considered to be enabled when they have
made a transition from a high impedance state to the point
when they start driving.
The output enable time tENA is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 54.
40
30
VDDEXT = 2.75V @ – 40
VDDEXT = 2.5V @ 25
DDEXT = 2.25V @ 105°C
°C
°C
V
20
10
0
–10
–20
–30
–40
V
OL
REFERENCE
SIGNAL
tDIS_MEASURED
tENA_MEASURED
tDIS
tENA
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
V
(MEASURED)
OH
SOURCE VOLTAGE (V)
(MEASURED)
V
(MEASURED)
-
ΔV
OH
V
(HIGH)
TRIP
V
(LOW)
OL
V
OL
(MEASURED) +
ΔV
TRIP
Figure 51. Driver Type E Current (2.5V VDDEXT/VDDMEM
)
V
OL
V
(MEASURED)
(MEASURED)
tDECAY
tTRIP
20
15
VDDEXT = 1.9V @ – 40
VDDEXT = 1.8V @ 25
°C
°
C
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
VDDEXT = 1.7V @ 105°C
10
5
Figure 54. Output Enable/Disable
0
The time tENA_MEASURED is the interval from when the reference
signal switches to when the output voltage reaches VTRIP(high)
or VTRIP(low). For VDDEXT (nominal) = 1.8 V, VTRIP (high) is
0.95 V, and VTRIP (low) is 0.85 V. For VDDEXT (nominal) = 2.5 V,
–5
V
OL
–10
–15
V
TRIP (high) is 1.3 V and VTRIP (low) is 1.2 V. For VDDEXT (nomi-
nal) = 3.3 V, VTRIP (high) is 1.7 V, and VTRIP (low) is 1.6 V. Time
tTRIP is the interval from when the output starts driving to when
the output reaches the VTRIP(high) or VTRIP(low) trip voltage.
–20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Time tENA is calculated as shown in the equation:
Figure 52. Driver Type E Current (1.8V VDDEXT/VDDMEM
)
tENA = tENA_MEASURED – tTRIP
If multiple signals (such as the data bus) are enabled, the mea-
surement value is that of the first signal to start driving.
Rev. B
| Page 52 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Output Disable Time Measurement
TESTER PIN ELECTRONICS
Output signals are considered to be disabled when they stop
50ꢀ
V
driving, go into a high impedance state, and start to decay from
LOAD
T1
DUT
their output high or low voltage. The output disable time tDIS is
OUTPUT
45ꢀ
the difference between tDIS_MEASURED and tDECAY as shown on the
70ꢀ
left side of Figure 54.
tDIS = tDIS_MEASURED – tDECAY
ZO = 50ꢀꢂ(impedance)
TD = 4.04 1.18 ns
50ꢀ
0.5pF
4pF
2pF
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay
400ꢀ
time can be approximated by the equation:
tDECAY = (CLΔV) ⁄ IL
NOTES:
The time tDECAY is calculated with test loads CL and IL and with
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ΔV equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V
and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8 V.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
The time tDIS_MEASURED is the interval from when the reference
signal switches to when the output voltage decays ΔV from the
measured output high or output low voltage.
Figure 55. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF51x processor’s out-
put voltage and the input threshold for the device requiring the
hold time. CL is the total bus capacitance (per data line), and IL is
the total leakage or three-state current (per data line). The hold
time is tDECAY plus the various output disable times as specified
in the Timing Specifications on Page 27 (for example tDSDAT for
an SDRAM write cycle as shown in SDRAM Interface Timing
on Page 31).
12
10
tRISE
8
tFALL
6
4
2
Capacitive Loading
tRISE = 1.8V @ 25°C
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see Figure 55). VLOAD is equal
to (VDDEXT/VDDMEM)/2. The graphs of Figure 56 through
Figure 67 show how output rise time varies with capacitance.
The delay and hold specifications given should be derated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
tFALL = 1.8V @ 25
°C
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 56. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM
)
Rev. B
| Page 53 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
7
8
7
6
5
6
5
tRISE
tRISE
4
3
tFALL
tFALL
4
3
2
1
2
1
tRISE = 2.5V @ 25°C
tRISE = 2.5V @ 25°C
tFALL = 2.5V @ 25
°C
tFALL = 2.5V @ 25
°C
0
0
0
50
100
150
200
250
250
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 60. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM
Figure 57. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM
)
)
6
6
5
4
5
4
tRISE
tRISE
tFALL
tFALL
3
2
1
3
2
1
tRISE = 3.3V @ 25°C
tRISE = 3.3V @ 25°C
tFALL = 3.3V @ 25
°C
tFALL = 3.3V @ 25
°C
0
0
0
50
100
150
200
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 61. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM
Figure 58. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM
)
)
25
9
8
tRISE
20
15
10
5
7
6
5
tRISE
tFALL
tFALL
4
3
2
1
tRISE = 1.8V @ 25°C
tRISE = 1.8V @ 25°C
tFALL = 1.8V @ 25
°C
tFALL = 1.8V @ 25
°C
0
0
0
50
100
150
200
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 62. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM
Figure 59. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM
)
)
Rev. B
|
Page 54 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
16
14
10
9
8
12
10
tRISE
7
tRISE
6
5
tFALL
tFALL
8
6
4
2
4
3
2
1
tRISE = 2.5V @ 25°C
tRISE = 2.5V @ 25°C
tFALL = 2.5V @ 25
°C
tFALL = 2.5V @ 25
°C
0
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 63. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM
Figure 66. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM
)
)
8
14
7
6
5
4
12
10
8
tRISE
tRISE
tFALL
tFALL
3
6
2
1
4
2
tRISE = 3.3V @ 25°C
tFALL = 3.3V @ 25
°C
tRISE = 3.3V @ 25°C
0
tFALL = 3.3V @ 25
°C
0
50
100
150
200
250
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 67. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM
Figure 64. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM
)
)
14
12
10
8
tRISE
tFALL
6
4
2
tRISE = 1.8V @ 25°C
tFALL = 1.8V @ 25
°C
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 65. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM
)
Rev. B
|
Page 55 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 50. Thermal Characteristics for SQ-176-2 Package
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board use:
Parameter Condition Typical Unit
θJA
0 Linear m/s Airflow
17.4
14.8
14.0
7.8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJMA
θJMA
θJC
1 Linear m/s Airflow
2 Linear m/s Airflow
Not Applicable
TJ = TCASE + (ΨJT × PD)
where:
ΨJT
ΨJT
ΨJT
0 Linear m/s Airflow
1 Linear m/s Airflow
2 Linear m/s Airflow
0.28
0.39
0.48
TJ = Junction temperature (°C)
T
CASE = Case temperature (°C) measured by customer at top
center of package.
ΨJT = From Table 51
PD = Power dissipation (see Total Power Dissipation on Page 23
for the method to calculate PD)
Table 51. Thermal Characteristics for BC-168-1 Package
Parameter Condition Typical Unit
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
θJA
0 Linear m/s Airflow
30.5
27.6
26.3
11.1
0.20
0.35
0.45
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJMA
θJMA
θJC
1 Linear m/s Airflow
2 Linear m/s Airflow
Not Applicable
TJ = TA + (θJA × PD)
ΨJT
ΨJT
ΨJT
0 Linear m/s Airflow
1 Linear m/s Airflow
2 Linear m/s Airflow
where:
TA = Ambient temperature (°C)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 51, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
The LQFP_EP package requires thermal trace squares and ther-
mal vias to an embedded ground plane in the PCB. The paddle
must be connected to ground for proper operation to data sheet
specifications. Refer to JEDEC standard JESD51-5 for more
information.
Rev. B
| Page 56 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
176-LEAD LQFP LEAD ASSIGNMENT
Table 52 lists the LQFP leads by lead number.
Table 53 on Page 58 lists the LQFP by signal mnemonic.
Table 52. 176-Lead LQFP Pin Assignment (Numerical by Lead Number)
Lead No.
1
2
3
4
5
6
7
8
Signal
GND
GND
PF9
PF8
PF7
Lead No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Signal
GND
GND
PG1
PG0
VDDEXT
TDO
EMU
TDI
Lead No.
89
90
91
92
93
94
95
96
Signal
GND
GND
A12
A11
A10
A9
VDDMEM
A8
Lead No.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
GND
Signal
GND
GND
PG
VDDEXT
GND
VDDINT
GND
RTXO
RTXI
VDDRTC
CLKIN
XTAL
VDDEXT
RESET
NMI
VDDEXT
GND
CLKBUF
GND
VDDINT
PH7
PH6
PH5
PH4
GND
VDDEXT
PH3
PH2
PH1
PF6
VDDEXT
VPPOTP
VDDOTP
PF5
PF4
PF3
9
TCK
97
98
99
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TRST
TMS
D15
D14
D13
VDDMEM
D12
D11
D10
VDDINT
D9
D8
D7
GND
VDDMEM
D6
D5
D4
D3
D2
D1
VDDMEM
D0
A19
A18
VDDINT
A17
A16
VDDMEM
GND
A15
A14
A13
GND
GND
VDDINT
GND
VDDINT
A6
A5
A4
VDDMEM
A3
A2
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
PF2
VDDINT
GND
VDDFLASH
VDDFLASH
PF1
PF0
A1
PG15
PG14
GND
VDDINT
VDDEXT
PG13
PG12
PG11
PG10
VDDFLASH
VDDINT
PG9
PG8
PG7
PG6
VDDEXT
PG5
PG4
PG3
PG2
BMODE2
BMODE1
BMODE0
GND
GND
ABE1
ABE0
SA10
GND
VDDMEM
SWE
SCAS
SRAS
VDDINT
GND
SMS
SCKE
AMS1
ARE
AWE
AMS0
VDDMEM
CLKOUT
VDDFLASH
NC1
PH0
GND
VDDINT
PF15
PF14
PF13
PF12
GND
VDDEXT
PF11
SDA
VDDEXT
VDDEXT
EXT_WAKE
GND
GND
SCL
PF10
GND
GND
177*
* Pin no. 177 is the GND supply (see Figure 69) for the processor; this pad must connect to GND.
1 This pin must not be connected.
Rev. B
| Page 57 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 53. 176-Lead LQFP Pin Assignment (Alphabetical by Signal Mnemonic)
Lead No.
107
106
105
103
102
101
97
96
94
93
92
91
86
85
84
81
80
78
77
109
108
123
120
121
122
42
41
40
150
143
125
76
74
73
72
71
70
69
66
65
Signal
A1
A2
A3
A4
A5
A6
A7
A8
Lead No.
58
57
56
51
130
1
2
15
22
43
44
45
46
67
83
87
88
Signal
D13
D14
Lead No.
5
4
Signal
PF7
PF8
Lead No.
113
53
52
50
55
54
7
24
Signal
SWE
TCK
TDI
TDO
D15
3
PF9
EMU
EXT_WAKE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC1
174
171
168
167
166
165
135
48
47
39
38
37
36
34
33
32
31
28
27
26
PF10
PF11
PF12
PF13
PF14
PF15
PG
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
PH4
TMS
TRST
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDFLASH
VDDFLASH
VDDFLASH
VDDFLASH
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDOTP
VDDRTC
VPPOTP
XTAL
A9
35
49
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
ABE0
ABE1
AMS0
AMS1
ARE
AWE
BMODE0
BMODE1
BMODE2
CLKBUF
CLKIN
CLKOUT
D0
128
129
136
145
148
158
170
16
17
29
126
14
23
30
63
79
98
100
116
138
152
164
59
68
75
82
95
104
112
124
9
142
8
89
90
99
111
131
132
133
134
137
139
149
151
157
163
169
175
176
117
127
147
19
25
21
20
162
161
160
159
156
155
154
153
146
141
140
110
114
119
173
172
118
115
PH5
PH6
PH7
D1
D2
D3
D4
D5
D6
D7
D8
RESET
RTXI
RTXO
SA10
SCAS
SCKE
SCL
SDA
SMS
SRAS
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
18
13
12
11
10
6
64
62
61
60
D9
D10
D11
D12
144
GND
177*
* Pin no. 177 is the GND supply (see Figure 69) for the processor; this pad must connect to GND.
1 This pin must not be connected.
Rev. B
| Page 58 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Figure 68 shows the top view of the LQFP_EP lead configura-
tion. Figure 69 shows the bottom view of the LQFP_EP lead
configuration.
PIN 176
PIN 133
PIN 1
PIN 132
PIN 1 INDICATOR
ADSP-BF51X
176-LEAD LQFP_EP
TOP VIEW
PIN 44
PIN 89
PIN 45
PIN 88
Figure 68. 176-Lead LQFP_EP Lead Configuration (Top View)
PIN 133
PIN 176
PIN 132
PIN 1
ADSP-BF51X
176-LEAD
LQFP_EP
GND PAD
(PIN 177)
PIN 1 INDICATOR
BOTTOM VIEW
PIN 89
PIN 44
PIN 88
PIN 45
Figure 69. 176-Lead LQFP_EP Lead Configuration (Bottom View)
Rev. B
| Page 59 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
168-BALL CSP_BGA BALL ASSIGNMENT
Table 54 lists the CSP_BGA by ball number. Table 55 on
Page 61 lists the CSP_BGA balls by signal mnemonic.
Table 54. 168-Ball CSP_BGA Ball Assignment (Numerical by Ball Number)
Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name
A1
GND
SCL
C1
PF4
E10
E12
E13
E14
F1
VDDINT
VDDMEM
ARE
H1
H2
H3
H5
H6
H7
H8
H9
H10
H12
H13
H14
J1
PG12
PG13
PG11
VDDEXT
GND
GND
GND
GND
VDDINT
A3
K6
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
A8
N1
N2
BMODE1
PG1
TDO
TRST
TMS
D13
D9
A2
C2
PF7
K7
A3
SDA
C3
PF8
K8
N3
A4
PF13
PF15
PH2
C4
PF10
VDDEXT
VDDEXT
PF11
VDDEXT
VDDINT
VDDEXT
RTXI
AWE
PF0
K9
N4
A5
C5
K10
K12
K13
K14
L1
N5
A6
C6
F2
PF1
N6
A7
PH1
C7
F3
VDDINT
VDDEXT
GND
GND
GND
GND
VDDINT
SMS
A2
N7
A8
PH5
C8
F5
A1
N8
D5
A9
PH6
C9
F6
PG5
PG3
PG2
A9
N9
D1
A10
A11
A12
A13
A14
B1
PH7
C10
C11
C12
C13
C14
D1
D2
D3
D12
D13
D14
E1
F7
L2
N10
N11
N12
N13
N14
P1
A18
A16
A14
A11
A7
CLKBUF
XTAL
CLKIN
GND
VDDOTP
GND
PF9
F8
ABE0
SCAS
PG10
VDDFLASH
PG9
L3
RTXO
PG
NC1
F9
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
F10
F12
F13
F14
G1
A6
J2
A4
PF3
SCKE
AMS1
PG15
PG14
VDDINT
VDDEXT
GND
GND
GND
GND
VDDINT
SWE
J3
PG4
BMODE2
BMODE0
PG0
EMU
D12
D10
D2
GND
TDI
B2
PF5
J5
VDDMEM
GND
GND
GND
GND
VDDINT
A15
P2
B3
VPPOTP
VDDFLASH
CLKOUT
AMS0
VDDFLASH
PF2
J6
P3
TCK
D15
D14
D11
D8
B4
PF12
PF14
PH0
G2
J7
P4
B5
G3
J8
P5
B6
G5
J9
P6
B7
PH3
G6
J10
J12
J13
J14
K1
P7
B8
PH4
E2
G7
P8
D7
B9
VDDEXT
RESET
NMI
E3
PF6
G8
ABE1
SA10
PG6
D0
P9
D6
B10
B11
B12
B13
B14
E5
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
G9
A17
P10
P11
P12
P13
P14
D4
E6
G10
G12
G13
G14
A13
D3
VDDRTC
VDDEXT
E7
K2
PG8
A12
A19
GND
GND
E8
SRAS
GND
K3
PG7
A10
EXT_WAKE E9
K5
VDDMEM
A5
1 This pin must not be connected.
Rev. B
|
Page 60 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 55. 168-Ball CSP_BGA Ball Assignment (Alphabetical by Signal Mnemonic)
Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name
K14
K13
H12
L14
M14
L13
N14
K12
L12
M13
N13
M12
M11
N12
J12
A1
A11
A13
D13
M9
N9
M8
P11
P10
N8
P9
CLKBUF
CLKIN
CLKOUT
D0
G6
G7
G8
G9
H6
H7
H8
H9
J6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC1
C4
C7
B4
A4
B5
A5
C13
M4
N2
L3
PF10
PF11
PF12
PF13
PF14
PF15
PG
A8
PH5
G5
H5
D12
E1
VDDEXT
VDDEXT
VDDFLASH
VDDFLASH
VDDFLASH
VDDINT
VDDINT
A2
A9
PH6
A3
A10
B10
C11
C12
J14
H14
F13
A2
PH7
A4
RESET
RTXI
RTXO
SA10
SCAS
SCKE
SCL
A5
D1
J2
A6
D2
C9
A7
D3
E7
A8
D4
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
PH4
E8
VDDINT
A9
D5
E9
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
ABE0
ABE1
AMS0
AMS1
ARE
AWE
BMODE0
BMODE1
BMODE2
D6
J7
E10
F3
P8
D7
J8
L2
A3
SDA
P7
D8
J9
M1
L1
F12
G13
G12
P3
SMS
F10
G3
G10
H10
J10
E12
J5
N7
M7
P6
D9
P1
SRAS
SWE
D10
D11
D12
D13
D14
D15
EMU
P13
P14
G14
C14
B11
F1
K1
K3
K2
J3
VDDINT
VDDINT
TCK
N11
M10
N10
P12
H13
J13
M6
N6
P5
P2
TDI
VDDINT
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDMEM
VDDOTP
VDDRTC
VPPOTP
XTAL
N3
TDO
NMI
PF0
J1
N5
TMS
P4
H3
H1
H2
G2
G1
B6
A7
A6
B7
B8
N4
TRST
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
K5
M5
B14
A1
F2
PF1
B9
K6
EXT_WAKE E2
PF2
B13
C5
K7
D14
F14
E13
E14
M3
GND
GND
GND
GND
GND
GND
GND
D1
C1
D2
E3
C2
C3
B3
PF3
K8
A14
B2
PF4
C6
K9
PF5
C8
K10
B1
F6
PF6
C10
E5
F7
PF7
B12
D3
A12
N1
F8
PF8
E6
M2
F9
PF9
F5
1 This pin must not be connected.
Rev. B
|
Page 61 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Figure 70 shows the top view of the CSP_BGA ball configura-
tion. Figure 71 shows the bottom view of the CSP_BGA
ball configuration.
A1 BALL PAD CORNER
A
B
C
D
NC
E
F
KEY
G
H
J
V
V
GND
I/O
DDINT
DDMEM
K
L
V
V
V
DDRTC
DDEXT
M
N
P
DDFLASH
1
2
3
4
5
6
7
8
9
10 11 12 13 14
TOP VIEW
Figure 70. 168-Ball CSP_BGA Ball Configuration (Top View)
A1 BALL PAD CORNER
A
B
C
D
NC
KEY
E
V
V
GND
F
DDINT
DDMEM
G
V
V
V
I/O
H
J
DDRTC
DDEXT
DDFLASH
K
L
M
N
P
14 13 12 11 10
9
8
7
6
5
4
3
2
1
BOTTOM VIEW
Figure 71. 168-Ball CSP_BGA Ball Configuration (Bottom View)
Rev. B
| Page 62 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
OUTLINE DIMENSIONS
Dimensions in Figure 72 are shown in millimeters.
NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND
THERMALLY CONNECTED TO GND. IMPLEMENT THIS BY
SOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS
THE SAME SIZE AS THE EXPOSED PAD. THE GND PCB LAND
SHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN
THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST
PERFORMANCE.
26.20
26.00 SQ
25.80
24.10
24.00 SQ
23.90
1.60
0.75
0.60
0.45
MAX
133
132
133
132
176
1
176
1
1.00 REF
PIN 1
5.80 REF
SQ
EXPOSED
PAD
TOP VIEW
(PINS DOWN)
12°
1.45
1.40
1.35
0.20
0.15
0.09
7°
BOTTOM VIEW
(PINS UP)
89
89
44
45
44
0.15
0°
88
88
45
0.10
0.05
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
0.50
VIEW A
BSC
EXPOSED PAD IS CENTERED ON
THE PACKAGE.
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD
Figure 72. 176-Lead Low Profile Quad Flat Package [LQFP_EP]
(SQ-176-2)
Dimensions shown in millimeters
Rev. B
| Page 63 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
12.10
12.00 SQ
11.90
A1 BALL
CORNER
A1 BALL
CORNER
14 13 12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
10.40
BSC SQ
0.80
BSC
K
L
M
N
P
0.80
REF
TOP VIEW
BOTTOM VIEW
DETAIL A
1.50
1.40
1.30
1.12
1.06
1.00
0.70
REF
DETAIL A
0.34 NOM
0.29 MIN
0.36
REF
0.50
0.45
0.40
COPLANARITY
0.20
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
Figure 73. 168-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-168-1)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 56 is provided as an aid to PCB design. For industry
standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 56. BGA Data for Use with Surface-Mount Design
Package Solder Mask
Opening
Package
Package Ball Attach Type
Package Ball Pad Size
168-Ball CSP_BGA
Solder Mask Defined
0.35 mm diameter
0.48 mm diameter
Rev. B
|
Page 64 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
AUTOMOTIVE PRODUCTS
The ADBF512W and ADBF518 models are available with con-
motive grade products shown in Table 57 are available for use in
automotive applications. Contact your local ADI account repre-
sentative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these
models.
trolled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these auto-
motive models may have specifications that differ from the
commercial models and designers should review the product
Specifications section of this data sheet carefully. Only the auto-
Table 57. Automotive Products
Temperature
Range3
Instruction
Package
Option
Automotive Models1,2
ADBF512WBBCZ4xx
ADBF518WBBCZ4xx
ADBF512WBSWZ4xx
ADBF518WBSWZ4xx
Rate (Max)
400 MHz
400 MHz
400 MHz
400 MHz
Package Description
168-Ball CSP_BGA
168-Ball CSP_BGA
176-Lead LQFP_EP
176-Lead LQFP_EP
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
BC-168-1
BC-168-1
SQ-176-2
SQ-176-2
1 Z = RoHS Compliant Part.
2 The use of xx designates silicon revision.
3 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ)
specification which is the only temperature specification.
ORDERING GUIDE
Temperature
Range2
Processor Instruction
Rate (Max)
Flash
Memory
Package
Option
Model1
Package Description
168-Ball CSP_BGA
168-Ball CSP_BGA
168-Ball CSP_BGA
176-Lead LQFP_EP
176-Lead LQFP_EP
176-Lead LQFP_EP
168-Ball CSP_BGA
168-Ball CSP_BGA
168-Ball CSP_BGA
176-Lead LQFP_EP
176-Lead LQFP_EP
176-Lead LQFP_EP
168-Ball CSP_BGA
168-Ball CSP_BGA
168-Ball CSP_BGA
176-Lead LQFP_EP
176-Lead LQFP_EP
176-Lead LQFP_EP
168-Ball CSP_BGA
168-Ball CSP_BGA
168-Ball CSP_BGA
176-Lead LQFP_EP
ADSP-BF512BBCZ-3
ADSP-BF512BBCZ-4
ADSP-BF512BBCZ-4F4
ADSP-BF512BSWZ-3
ADSP-BF512BSWZ-4
ADSP-BF512BSWZ-4F4
ADSP-BF512KBCZ-3
ADSP-BF512KBCZ-4
ADSP-BF512KBCZ-4F4
ADSP-BF512KSWZ-3
ADSP-BF512KSWZ-4
ADSP-BF512KSWZ-4F4
ADSP-BF514BBCZ-3
ADSP-BF514BBCZ-4
ADSP-BF514BBCZ-4F4
ADSP-BF514BSWZ-3
ADSP-BF514BSWZ-4
ADSP-BF514BSWZ-4F4
ADSP-BF514KBCZ-3
ADSP-BF514KBCZ-4
ADSP-BF514KBCZ-4F4
ADSP-BF514KSWZ-3
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
0ºC to +70ºC
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
300 MHz
N/A
BC-168-1
BC-168-1
BC-168-1
SQ-176-2
SQ-176-2
SQ-176-2
BC-168-1
BC-168-1
BC-168-1
SQ-176-2
SQ-176-2
SQ-176-2
BC-168-1
BC-168-1
BC-168-1
SQ-176-2
SQ-176-2
SQ-176-2
BC-168-1
BC-168-1
BC-168-1
SQ-176-2
N/A
4M bit
N/A
N/A
4M bit
N/A
0ºC to +70ºC
N/A
0ºC to +70ºC
4M bit
N/A
0ºC to +70ºC
0ºC to +70ºC
N/A
0ºC to +70ºC
4M bit
N/A
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
0ºC to +70ºC
N/A
4M bit
N/A
N/A
4M bit
N/A
0ºC to +70ºC
N/A
0ºC to +70ºC
4M bit
N/A
0ºC to +70ºC
Rev. B
|
Page 65 of 68
|
January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Temperature
Range2
Processor Instruction
Rate (Max)
Flash
Memory
Package
Option
Model1
Package Description
176-Lead LQFP_EP
176-Lead LQFP_EP
176-Lead LQFP_EP
168-Ball CSP_BGA
176-Lead LQFP_EP
168-Ball CSP_BGA
176-Lead LQFP_EP
168-Ball CSP_BGA
168-Ball CSP_BGA
168-Ball CSP_BGA
168-Ball CSP_BGA
176-Lead LQFP_EP
176-Lead LQFP_EP
176-Lead LQFP_EP
168-Ball CSP_BGA
168-Ball CSP_BGA
176-Lead LQFP_EP
176-Lead LQFP_EP
ADSP-BF514KSWZ-4
ADSP-BF514KSWZ-4F4
ADSP-BF516KSWZ-3
ADSP-BF516KBCZ-3
ADSP-BF516KSWZ-4
ADSP-BF516KBCZ-4
ADSP-BF516KSWZ-4F4
ADSP-BF516KBCZ-4F4
ADSP-BF516BBCZ-3
ADSP-BF516BBCZ-4
ADSP-BF516BBCZ-4F4
ADSP-BF516BSWZ-3
ADSP-BF516BSWZ-4
ADSP-BF516BSWZ-4F4
ADSP-BF518BBCZ-4
ADSP-BF518BBCZ-4F4
ADSP-BF518BSWZ-4
ADSP-BF518BSWZ-4F4
1 Z = RoHS compliant part.
0ºC to +70ºC
400 MHz
400 MHz
300 MHz
300 MHz
400 MHz
400 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
300 MHz
400 MHz
400 MHz
400 MHz
400 MHz
400 MHz
400 MHz
N/A
SQ-176-2
SQ-176-2
SQ-176-2
BC-168-1
SQ-176-2
BC-168-1
SQ-176-2
BC-168-1
BC-168-1
BC-168-1
BC-168-1
SQ-176-2
SQ-176-2
SQ-176-2
BC-168-1
BC-168-1
SQ-176-2
SQ-176-2
0ºC to +70ºC
4M bit
N/A
0ºC to +70ºC
0ºC to +70ºC
N/A
0ºC to +70ºC
N/A
0ºC to +70ºC
N/A
0ºC to +70ºC
4M bit
4M bit
N/A
0ºC to +70ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
N/A
4M bit
N/A
N/A
4M bit
N/A
4M bit
N/A
4M bit
2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ)
specification which is the only temperature specification.
Rev. B
| Page 66 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
| Page 67 of 68 | January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08574-0-1/11(B)
Rev. B
| Page 68 of 68 | January 2011
相关型号:
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