CN-0232 [ADI]
Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and an External PLL Circuit; 尽量减少使用合成器集成VCO和外部PLL电路的杂散输出
| 型号： | CN-0232 |
| 厂家： | 
ADI |
| 描述： | Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and an External PLL Circuit |
| 文件： | 总6页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Circuit Note
CN-0232
Devices Connected/Referenced
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0232.
Fractional-N PLL Synthesizer with
ADF4350
ADF4153
Integrated VCO
Fractional-N PLL Frequency Synthesizer
Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and
an External PLL Circuit
EVALUATION AND DESIGN SUPPORT
CIRCUIT FUNCTION AND BENEFITS
Circuit Evaluation Boards
The circuit shown in Figure 1 uses the ADF4350 synthesizer with
an integrated VCO and an external PLL to minimize spurious
outputs by isolating the PLL synthesizer circuitry from the VCO
circuit.
ADF4350 Evaluation Board (EVAL-ADF4350EB2Z)
ADF4153 Evaluation Board (EVAL-ADF4153EBZ1)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
LOCK
DETECT
3.3V
V
V
DD
3.3V
VCO
V
VCO
16
17
VCO
30
MUXOUT LD
28
10
4
26
6
32
25
51Ω
51Ω
V
RFOUTA+
1nF
1nF
1nF 1nF
14
15
RF
B+
OUT
REF
29
IN
RF
B–
51Ω
OUT
51Ω
V
VCO
1
2
3
CLK
PHASE
DATA
LE
CHARGE
PUMP
FREQUENCY
DETECTOR
VCO
RF
51Ω
51Ω
1nF
1nF
RFOUTB+
22
R
13
12
A–
A+
SET
OUT
4.7kΩ
COUNTERS
ADF4350
RF
OUT
51Ω
V
TUNE
20
7
CP
OUT
SW
REFERENCE
VCO
5
TUNING
CPGND SD
AGND
9
A
DGND TEMP V
V
TCXO
26MHz
GND
GNDVCO
11 18 21
COM REF
23 24
VOLTAGE
8
31
27
19
10pF
0.1µF 10pF
0.1µF 10pF
0.1µF
V
3.3V
DD
7
14
MUXOUT
15
DV
16
10
SDV
AV
V
P
DD
DD
DD
1nF 1nF
8
REF
IN
LOOP FILTER
360Ω
CLK
DATA
LE
11
12
13
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
2
CP
100nF
22nF
4.7nF
200Ω
1
R
SET
COUNTERS
4.7kΩ
100pF
100pF
ADF4153
RF
RF
A
B
6
5
IN
IN
CPGND
3
AGND DGND
4
9
RF IN
51Ω
51Ω
Figure 1. ADF4153 PLL Connected to ADF4350 (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. 0
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©2012 Analog Devices, Inc. All rights reserved.
CN-0232
Circuit Note
Devices with integrated PLLs and VCOs may have feed through
from the digital PLL circuitry to the VCO, leading to higher
spurious levels due to the close proximity of the PLL circuitry
to the VCO.
For frequency generation, the internal PLL must be enabled and
the desired frequency must be programmed. Then, once sufficient
time has elapsed for band select, the internal PLL can be disabled,
and, finally, the external PLL can be enabled. The external PLL
compares the reference frequency and the VCO output frequency
to generate a stable dc voltage to lock the PLL.
The circuit shown in Figure 1 uses the ADF4350, a fully integrated
fractional-N PLL and VCO that can generate frequencies from
137.5 MHz to 4400 MHz, together with the ADF4153 PLL.
Figure 2 shows the output frequency spurs measured at RFOUTA+
using the ADF4350 internal PLL and VCO with the ADF4153 PLL
disabled. Note the presence of PFD spurs at 13 MHz and 26 MHz.
In addition to improvements in spurious performance,
another possible advantage of using an external PLL is the
possibility of increased frequency resolution. For example,
if the ADF4157 PLL is selected in place of the ADF4153, the
frequency resolution of the PLL can be as fine as 0.7 Hz.
Figure 3 shows the output spurs measured at RFOUTA+ with the
ADF4350 internal PLL circuit disabled and the external ADF4153
PLL active. In this mode, the charge pump output of the ADF4153
drives the loop filter, which in turn drives the VTUNE input of the
ADF4350. The VTUNE input controls the ADF4350 VCO output
frequency.
CIRCUIT DESCRIPTION
The ADF4350 is a wideband PLL and VCO consisting of
three separate multiband VCOs. Each VCO covers a range of
approximately 700 MHz (with some overlap between the
frequencies of the VCO). This permits a fundamental VCO
frequency range of between 2.2 GHz to 4.4 GHz. Frequencies
lower than 2.2 GHz can be generated using internal dividers
within the ADF4350.
In making a comparison between Figure 2 and Figure 3, the spurs
due to the phase frequency detector (PFD) frequency, at 13 MHz
and 26 MHz, in Figure 2 have disappeared into the noise floor
in Figure 3.
COMMON VARIATIONS
For most applications, the internal PLL of the ADF4350 is used to
lock the VCO. In addition to locking the PLL, the PLL circuitry
performs an additional vital function of VCO band select, using
the internal reference (R) and feedback (N) counters of the internal
PLL to compare the VCO output with the reference input.
Different PLLs can be selected. The fractional-N PLL in both the
ADF4350 and ADF4153 has a minimum frequency resolution
of PFD/4095. If finer resolution is required, the ADF4157
can be selected. The resolution of this PLL is PFD/225, thereby
providing an ultrafine resolution of <1 Hz.
For applications requiring simpler software programmability,
the ADF4150 PLL is software compatible with the ADF4350,
easing the software programming sequence.
Rev. 0 | Page 2 of 6
Circuit Note
CN-0232
R&S FSUP SIGNAL SOURCE ANALYZER
RESIDUAL NOISE
(T1 WITHOUT SPURS)
SETTINGS
SPUR LIST
SIGNAL FREQUENCY: 1.6000GHz
SIGNAL LEVEL: 5.44dBm
INT PHN (1.0k .. 30.0M): –49.1dBc 1.000MHz –83.82dBc
2.001MHz –99.68dBc
3.000MHz –89.92dBc
RESIDUAL PM: 0.285°
RESIDUAL FM: 3.24kHz
CROSS CORR MODE: HARMONIC 1
INTERNAL REF TUNED: INTERNAL PHASE DET
RMS JITTER: 0.4946ps 13.000MHz –94.70dBc
PHASE NOISE (dBc/Hz)
RF ATTEN: 5dB
TOP –70dBc/Hz
MARKER 1 (T1)
1kHz
–91.84dBc/Hz
MARKER 2 (T1) MARKER 3 (T1) MARKER 4 (T1)
10.98633kHz
–93.42dBc/Hz
13.00011MHz
–94.7dBc
26.00002MHz
–87.89dBc
–70
LOOP BW 300Hz
2
–80
–90
4
1
3
–100
–110
–120
–130
–140
–150
–160
–170
SPR OFF
TH 0dB
1k
10k
100k
1M
10M 30M
FREQUENCY OFFSET (Hz)
Figure 2. ADF4350 PFD Spurs at 1.6 GHz
R&S FSUP SIGNAL SOURCE ANALYZER
RESIDUAL NOISE
(T1 WITHOUT SPURS)
SETTINGS
SPUR LIST
SIGNAL FREQUENCY: 1.6000GHz
SIGNAL LEVEL: 1.71dBm
INT PHN (1.0k .. 30.0M): –53.3dBc 1000.0kHz –90.44dBc
2.000MHz –85.60dBc
3.000MHz –96.36dBc
RESIDUAL PM: 0.174°
CROSS CORR MODE: HARMONIC 1
INTERNAL REF TUNED: INTERNAL PHASE DET
RESIDUAL FM: 1.846kHz
RMS JITTER: 0.3025ps 4.000MHz –99.28dBc
PHASE NOISE (dBc/Hz)
RF ATTEN: 5dB
TOP –70dBc/Hz
MARKER 1 (T1)
1kHz
–101.23dBc/Hz
MARKER 2 (T1) MARKER 3 (T1) MARKER 4 (T1)
1kHz
100kHz
–120.62dBc
1MHz
–144.68dBc
–101.23dBc/Hz
–70
LOOP BW 300Hz
–80
–90
12
–100
–110
–120
–130
–140
–150
–160
–170
3
4
SPR OFF
TH 0dB
1k
10k
100k
1M
10M 30M
FREQUENCY OFFSET (Hz)
Figure 3. ADF4350 PFD Spurs at 1.6 GHz Using ADF4153 PLL
Rev. 0 | Page 3 of 6
CN-0232
Circuit Note
Functional Block Diagram
CIRCUIT EVALUATION AND TEST
For this experiment, the EVAL-ADF4153EBZ1 and the EVAL-
ADF4350EB2Z are used. The EVAL-ADF4350EB2Z is selected
because it contains the auxiliary RFOUTB+ output stage, which is
connected via SMA cable to the EVAL-ADF4153EBZ1, as shown
in Figure 4.
The CN-0232 uses the EVAL-ADF4350EB2Z board for
evaluation of the described circuit, and with some minor
modifications, allows for quick setup and evaluation. The
EVAL-ADF4350EB2Z board uses the standard ADF4350
programming software, contained on the CD that accompanies
the evaluation board. The EVAL-ADF4153EBZ1 evaluation
board comes with the software for the ADF4153 PLL.
Both PLLs use the same reference input (REFIN) frequency;
therefore, an SMA splitter connects the same REFIN to both
boards.
Equipment Needed
The loop filter output on the EVAL-ADF4153EBZ1 is connected
to the VTUNE pin of the ADF4350 via a shielded coaxial cable to
ensure that no extra noise or spurs appear on the pin. Both
parts are programmed separately. It may be necessary to use
different PCs for each board to ensure no conflicts occur
between hardware drivers.
•
•
•
•
•
•
EVAL-ADF4350EB2Z with programming software.
EVAL-ADF4153EBZ1 with programming software.
5.5 V power supply.
R&S SMA100A signal generator or equivalent.
R&S FSUP26 spectrum analyzer or equivalent.
Two PCs with Windows® XP, Windows, Vista (32-bit), or
Windows 7 (32-bit), one with an USB port and the other
with a printer port. Alternatively, the EVAL-ADF4xxxX-
USB USB adaptor kit can be used instead of the printer
port, if none is available.
Getting Started
The UG-110 user guide details the installation and use of the
EVAL-ADF4350EB2Z evaluation software. UG-110 also
contains board setup instructions and the board schematic,
layout, and bill of materials.
The SMA coaxial cable is required to connect RFOUTB+ of the
EVAL-ADF4350EB2Z to RFIN of the EVAL-ADF4153EBZ1. A
simple SMA splitter is also needed to share the reference source
between the two boards. Some flexible microcoaxial cable is
required to connect the output of the ADF4153 loop filter to the
ADF4350 VTUNE input. To minimize unwanted interference, both
sides of the cable must be grounded to suitable GND points on
each board.
The UG-167 user guide contains similar information relevant to
the EVAL-ADF4153EBZ1. Necessary modifications to the board
are the removal of the VCO (Y1). To reconfigure this board as
an input, remove the R7 resistor and change R8 and R9 to 0 Ω.
The PLL loop filter on the ADF4350 board is unused and
should be removed. At this point, the microcoaxial cable can be
used to connect the output of the ADF4153 loop filter (T7) to
the VTUNE pin of the ADF4350 (T4). It is of critical importance
that the outer shielding of this cable is connected to a ground
point on both boards.
POWER
SUPPLY
5.5V
J14
COM
J15
RFOUTA+
SPECTRUM
ANALYZER
(R&S FSUP26)
USB
J2
J3
PC
RFOUTA−
50Ω
TERM
ADF4350
EVALUATION BOARD
(EVAL-ADF4350EB2Z)
J1
RFOUTB+
J4
J5
RFOUTB−
REFERENCE
FREQUENCY
GENERATOR
(R&S SMA100A)
50Ω
TERM
T4
VTUNE
CP OUT
T7
ADF4153
J5
EVAL-
ADF4xxxX-USB
EVALUATION BOARD
(EVAL-ADF4153EBZ1)
PC
RFIN+
USB
J2
PRINTER
9V BATTERY
Figure 4. Test Setup Functional Diagram
Rev. 0 | Page 4 of 6
Circuit Note
CN-0232
Initialization Procedure
The ADF4350 must go through the band select process for every
new frequency.
1. Initialize the ADF4350 as normal (program R5, R4, R3, R2,
R1, R0), except set DB4, R2 to 1 (ICP three-state enabled),
because the ADF4350 charge pump is unused. Set DB9, R4 to
0 for divided VCO output on RFOUTB+. Enable RFOUTB+
(auxiliary out). This signal is fed to the ADF4153 over the
coax cable.
2. Initialize the ADF4153 (as per the data sheet) to accept the
VCO output frequency as the RF input frequency. Note
that the band select switch is internal; therefore, an external
switch to remove the PLL VTUNE is not required.
3. When the ADF4153 achieves lock, the ADF4350 counter
reset to 1 (DB3, R2) must be activated. Not activating the
counter reset degrades spur performance. Additionally, all
ADF4350 synthesizer blocks can be powered down using
the test mode bit (DB10, R5).
Frequency Update
1. Program DB10, R5 to 0 to reactivate the ADF4350 synthesizer
blocks.
Figure 5. ADF4350 Software Window
2. Program DB3, R2 of the ADF4350 to 0 to deactivate the
counter reset because these counters are required for band
select.
3. Program the ADF4350 and ADF4153 N-counter registers
as appropriate for the new frequency.
4. When the ADF4153 achieves lock, the ADF4350 counter
reset (DB3, R2) can be activated. Additionally all synthesizer
blocks can be powered down using the test mode bit
(DB10, R5).
5. Repeat Step 1 to Step 4 as required for new frequencies.
The software screen captures shown in Figure 5 and Figure 6 show
the software windows for 26 MHz REFIN (ADF4350) and 13 MHz
PFD (ADF4153).
After setting up the equipment, use standard RF test methods to
measure the spectral purity of the output signal.
Figure 6. ADF4153 Software Window
Rev. 0 | Page 5 of 6
CN-0232
Circuit Note
LEARN MORE
CN0232 Design Support Package:
http://www.analog.com/CN0232-DesignSupport
UG-110, User Guide for the EVAL-ADF4350EB2Z board
UG-167, User Guide for the EVAL-ADF4153EBZ1 board
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of “AGND” and “DGND”, Analog Devices.
MT-086 Tutorial, Fundamentals of Phase Locked Loops (PLLs),
Analog Devices.
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
ADIsimPLL Design Tool
Data Sheets and Evaluation Boards
ADF4350 Evaluation Board (EVAL-ADF4350EB2Z)
ADF4153 Evaluation Board (EVAL-ADF4153EBZ1)
ADF4153 Data Sheet
ADF4350 Data Sheet
REVISION HISTORY
4/12—Revision 0: Initial Version
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registered trademarks are the property of their respective owners.
CN10125-0-4/12(0)
Rev. 0 | Page 6 of 6
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