CN-0279 [ADI]
High IF Sampling Receiver Front End with Band-Pass Filter; 高IF与带通滤波器的采样接收机前端
| 型号： | CN-0279 |
| 厂家： | 
ADI |
| 描述： | High IF Sampling Receiver Front End with Band-Pass Filter |
| 文件： | 总5页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Circuit Note
CN-0279
Devices Connected/Referenced
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s AD9642
analog, mixed-signal, and RF design challenges. For more
14-Bit, 250 MSPS Analog-to-Digital Converter
6 GHz Ultrahigh Dynamic Range Differential
Amplifier
information and/or support, visit www.analog.com/CN0279.
ADL5565
High IF Sampling Receiver Front End with Band-Pass Filter
EVALUATION AND DESIGN SUPPORT
CIRCUIT DESCRIPTION
Design and Integration Files
Schematics, Layout Files, Bill of Materials
The circuit accepts a single-ended input and converts it to
differential input using a wide bandwidth (3 GHz) Mini-Circuits
TC2-1T 1:2 transformer. The 6 GHz ADL5565 differential
amplifier has a differential input impedance of 200 Ω when
operating at a gain of 6 dB, and 100 Ω when operating at a
gain of 12 dB. A gain option of 15.5 dB is also available.
CIRCUIT FUNCTION AND BENEFITS
The circuit, shown in Figure 1, is a narrow, band-pass receiver
front end based on the ADL5565 ultralow noise differential
amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-
digital converter (ADC).
The ADL5565 is an ideal driver for the AD9642, and the fully
differential architecture through the band-pass filter and into
the ADC provides good high frequency common-mode rejection,
as well as minimizes second-order distortion products. The
ADL5565 provides a gain of 6 dB or 12 dB, depending on the input
connection. In the circuit, a gain of 12 dB was used to compensate
for the insertion loss of the filter network and transformer
(approximately 5.8 dB), providing an overall signal gain of 5.5 dB.
The third-order, Butterworth antialiasing filter is optimized based
on the performance and interface requirements of the amplifier
and ADC. The total insertion loss due to the filter network and
other components is only 5.8 dB.
The overall circuit has a bandwidth of 18 MHz with a pass-band
flatness of 3 dB. The signal-to-noise ratio (SNR) and spurious-
free dynamic range (SFDR) measured with a 127 MHz analog
input are 71.7 dBFS and 92 dBc, respectively. The sampling
frequency is 205 MSPS, thereby positioning the IF input signal
in the second Nyquist zone between 102.5 MHz and 205 MHz.
5.8dB LOSS
0.5dB LOSS
11.8dB GAIN
+3.3V
5.6dB LOSS
0.2dB LOSS
+1.8V
+1.8V
AVDD DRVDD
ANALOG
INPUT
XFMR
1:2 Z
TC2-1T
+1.5dBm FS
AT 127MHz
0.1µF
0.1µF
1.2pF
620nH
15Ω
5Ω
AD9642
14-BIT
VIP2
100Ω
205MSPS
ADC
5Ω
INPUT
Z = 50Ω
36nH
1.2pF
0.1µF
VIP1
VIN1
VIN2
33pF
33pF
ADL5565
36nH
Z = 100Ω
2.85kΩ
2.5pF
I
G = 12dB
INTERNAL
INPUT Z
5Ω
100Ω
0.1µF
OVERALL
GAIN = 5.5dB
620nH
5Ω
15Ω
0.1µF
FS = 1.75V
p-p DIFF
217Ω
40Ω
187Ω
VCM
Figure 1. 14-Bit, 250 MSPS Wideband Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown)
Gains, Losses, and Signal Levels Measured Values for an Input Frequency of 127 MHz
Rev. 0
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©2012 Analog Devices, Inc. All rights reserved.
CN-0279
Circuit Note
An input signal of 1.5 dBm produces a full-scale 1.75 V p-p
differential signal at the ADC input.
The measured performance of the system is summarized in
Table 1, where the 3 dB bandwidth, 18 MHz centered at 127 MHz.
The total insertion loss of the network is approximately 5.8 dB. The
frequency response is shown in Figure 3, and the SNR and SFDR
performance are shown in Figure 4.
The antialiasing filter is a third-order, Butterworth filter designed
with a standard filter design program. A Butterworth filter was
chosen because of its pass-band flatness. A third-order filter
yields an ac noise bandwidth ratio of 1.05 and can be designed
with the aid of several free filter programs such as Nuhertz
Technologies Filter Free, or the quite universal circuit simulator
(Qucs) free simulation.
Table 1. Measured Performance of the Circuit
Performance Specifications at −1 dBFS
(FS = 1.75 V p-p), Sample Rate = 205 MSPS Final Results
Center Frequency
Pass-Band Flatness (118 MHz to 136 MHz)
SNRFS at 127 MHz
127 MHz
3 dB
71.7 dBFS
92 dBc
To achieve best performance, load the ADL5565 with a net
differential load of 200 Ω. The 15 Ω series resistors isolate the
filter capacitance from the amplifier output, and the 100 Ω resistors
in parallel with the downstream impedance yield a net load
impedance of 217 Ω when added to the 30 Ω series resistance.
SFDR at 127 MHz
H2/H3 at 127 MHz
Overall Gain at 127 MHz
Input Drive at 127 MHz
93 dBc/92 dBc
5.5 dB
0.5 dBm (−1 dBFS)
The 5 Ω resistors in series with the ADC inputs isolate internal
switching transients from the filter and the amplifier.
0
The 2.85 kΩ input impedance was determined using the down-
loadable spreadsheet on the AD9642 webpage. Simply use the
parallel track mode values at the center of the IF frequency of
interest. The spreadsheet shows both the real and imaginary values.
–5
–10
–15
–20
–25
–30
–35
–40
The third-order, Butterworth filter was designed with a source
impedance (differential) of 200 Ω, a load impedance (differential)
of 200 Ω, a center frequency of 127 MHz, and a 3 dB bandwidth
of 20 MHz. The calculated values from a standard filter design
program are shown in Figure 1. Because of the high values of
series inductance required, the 1.59 µH inductors were decreased
to 620 nH, and the 0.987 pF capacitors increased proportionally
to 2.53 pF, thereby maintaining the same resonant frequency of
127 MHz, with more realistic component values.
50
100
150
200
250 300
ANALOG INPUT FREQUENCY (MHz)
Figure 3. Pass-Band Flatness Performance vs. Frequency
(2.53pF) (620nH)
0.987pF 1.59µH
95
90
85
80
75
70
65
60
55
50
100Ω
SFDR (dBc)
+
39.8pF
100Ω
39.5nH
39.8pF
39.5nH
200Ω
–
(2.53pF) (620nH)
0.987pF 1.59µH
SNR (dBFS)
Figure 2. Starting Design for Third-Order, Differential Butterworth Filter with
ZS = 200 Ω, ZL = 200 Ω, FC = 127 MHz, and BW = 20 MHz
The internal 2.5 pF capacitance of the ADC was subtracted
from the value of the second shunt capacitor to yield a value of
37.3 pF. In the circuit, this capacitor was located near the ADC
to reduce/absorb the charge kickback.
The values chosen for the final filter passive components (after
adjusting for actual circuit parasitics) are shown in Figure 1.
118
120
122
124
126
128
130
132
134
136
ANALOG INPUT FREQUENCY (MHz)
Figure 4. SNR/SFDR Performance vs. Frequency, Sample Rate = 205 MSPS
Rev. 0 | Page 2 of 5
Circuit Note
CN-0279
AVDD DRVDD
AVDD_AMP
ANALOG
INPUT
XFMR
1:2 Z
0.1µF
C
L
AAF1
0.1µF
AAF2
R
R
KB
A
ADC
INTERNAL
INPUT Z
R
TADC
Z
Z
/2
O
INPUT
Z = 50Ω
0.1µF
C
C
AAF1
AAF3
L
L
AAF
Z = R /2
AAF
I
GAIN
/2
R
R
C
I
ADC
ADC
INTERNAL
INPUT Z
O
R
TADC
0.1µF
L
R
AAF1
R
C
KB
A
AAF2
0.1µF
Z
Z
Z
AAFL
AL
AAFS
VCM
Figure 5. Generalized Differential Amplifier/ADC Interface with Band-Pass Filter
Filter and Interface Design Procedure
6. Calculate the filter source resistance by
AAFS = ZO + 2RA
In this section, a general approach to the design of the amplifier/
ADC interface with a band-pass filter is presented. To achieve
optimum performance (bandwidth, SNR, and SFDR), there are
certain design constraints placed on the general circuit by the
amplifier and the ADC.
Z
7. Using a filter design program or tables design the filter
using the source and load impedances, ZAAFS and ZAAFL, type
of filter, bandwidth, and order. Use a bandwidth that is about
10% higher than the desired bandwidth of the application
pass band to ensure flatness in the frequency span.
1. The amplifier must see the correct dc load recommended
by the data sheet for optimum performance.
2. The correct amount of series resistance must be used between
the amplifier and the load presented by the filter. This is to
prevent undesired peaking in the pass band.
3. The input to the ADC must be reduced by external parallel
resistors, and the correct series resistance must be used to
isolate the ADC from the filter. This series resistor also
reduces peaking.
After running these preliminary calculations, the circuit must
be given a quick review for the following items.
1. The value of CAAF3 must be at least 10 pF so that it is several
times larger than CADC. This minimizes the sensitivity of
the filter to variations in CADC
.
2. The ratio of ZAAFL to ZAAFS must not be more than about 7 so
that the filter is within the limits of most filter tables and
design programs.
3. The value of CAAF1 must be at least 5 pF to minimize sensitivity
to parasitic capacitance and component variations.
4. The inductor, LAAF, must be a reasonable value of at least
several nH.
5. The value of CAFF2 and LAAF1 must be reasonable values.
Sometimes circuit simulators can make these values too
low or too high. To make these values more reasonable,
simply ratio these values with better standard value
components that maintain the same resonant frequency.
The generalized circuit shown in Figure 5 applies to most high
speed differential amplifier/ADC interfaces and was used as a
basis for the band-pass filter. This design approach tends to
minimize the insertion loss of the filter by taking advantage of
the relatively high input impedance of most high speed ADCs
and the relatively low impedance of the driving source (amplifier).
The basic design process is as follows:
1. Set the external ADC termination resistors, RTADC , so that
the parallel combination of RTADC and RADC is between
200 Ω and 400 Ω.
2. Select RKB based on experience and/or the ADC data sheet
recommendations, typically between 5 Ω and 36 Ω.
3. Calculate the filter load impedance using
In some cases, the filter design program can provide more than
one unique solution, especially with higher order filters. The
solution that uses the most reasonable set of component values
should always be chosen. Also, choose a configuration that ends
in a shunt capacitor so that it can be combined with the ADC
input capacitance.
ZAAFL = 2RTADC || (RADC + 2RKB)
4. Select the amplifier external series resistor, RA. Make RA
less than 10 Ω if the amplifier differential output impedance
is 100 Ω to 200 Ω. Make RA between 5 Ω and 36 Ω if the
output impedance of the amplifier is 12 Ω or less.
5. Select ZAAFL so that the total load seen by the amplifier, ZAL,
is optimum for the particular differential amplifier chosen
using the following equation:
ZAL = 2RA + ZAAFL
Rev. 0 | Page 3 of 5
CN-0279
Circuit Note
Circuit Optimization Techniques and Trade-Offs
Passive Component and PC Board Parasitic Considerations
The parameters in this interface circuit are very interactive;
therefore, it is almost impossible to optimize the circuit for all
key specifications (bandwidth, bandwidth flatness, SNR, SFDR,
and gain). However, the peaking, which often occurs in the
bandwidth response, can be minimized by varying RA and RKB.
The performance of this or any high speed circuit is highly
dependent on proper printed circuit board (PCB) layout. This
includes, but is not limited to, power supply bypassing, controlled
impedance lines (where required), component placement, signal
routing, and power and ground planes. See Tutorial MT-031 and
Tutorial MT-101 for more detailed information regarding PCB
layout for high speed ADCs and amplifiers. In addition, see the
CN-0227 and the CN-0238.
The value of RA also affects SNR performance. Larger values,
while reducing the bandwidth peaking, tend to slightly increase
the SNR because of the higher signal level required to drive the
ADC full scale.
Use low parasitic surface-mount capacitors, inductors, and resistors
for the passive components in the filter. The inductors chosen
are from the Coilcraft 0603CS series. The surface-mount capacitors
used in the filter are 5%, C0G, 0402 type for stability and accuracy.
Select the RKB series resistor on the ADC inputs to minimize
distortion caused by any residual charge injection from the
internal sampling capacitor within the ADC. Increasing this
resistor also tends to reduce bandwidth peaking.
See the CN-0279 Design Support Package for the complete
documentation on the system.
However, increasing RKB increases signal attenuation, and the
amplifier must drive a larger signal to fill the ADC input range.
COMMON VARIATIONS
For optimizing center frequency, pass-band characteristics, the
series capacitor, CAAF2, can be varied by a small amount.
The AD9643 is a dual version of the AD9642.
For lower power and bandwidth, the ADA4950-1 and/or
ADL5561/ADL5562 can also be used. These devices are pin
compatible with the other singles previously listed.
Normally, the ADC input termination resistor, RTADC, is selected
to make the net ADC input impedance between 200 Ω and 400 Ω,
which is typical of most amplifier characteristic load values. Using
too high or too low a value can have an adverse effect on the
linearity of the amplifier.
CIRCUIT EVALUATION AND TEST
This circuit uses a modified AD9642-250EBZ circuit board and
the HSC-ADC-EVALCZ FPGA-based data capture board. The
two boards have mating high speed connectors, allowing for the
quick setup and evaluation of the performance of the circuit. The
modified AD9642-250EBZ board contains the circuit evaluated
as described in this note, and the HSC-ADC-EVALCZ data
capture board is used in conjunction with VisualAnalog® evaluation
software, as well as the SPI Controller software to properly control
the ADC and capture the data. See User Guide UG-386 for the
schematics, BOM, and layout for the AD9642-250EBZ board.
The readme.txt file in the CN-0279 Design Support Package
describes the modifications made to the standard AD9642-250EBZ
board. Application Note AN-835 contains complete details on
how to set up the hardware and software to run the tests described
in this circuit note.
Balancing these trade-offs can be somewhat difficult. In this
design, each parameter was given equal weight; therefore, the
values chosen are representative of the interface performance
for all the design characteristics. In some designs, different values
can be chosen to optimize SFDR, SNR, or input drive level,
depending on system requirements.
The SFDR performance in this design is determined by two
factors: the amplifier and ADC interface component values, as
shown in Figure 1.
Note that the signal in this design is ac-coupled with the 0.1 µF
capacitors to block the common-mode voltages between the
amplifier, its termination resistors, and the ADC inputs. Refer to
the AD9642 data sheet for further details regarding common-
mode voltages.
Rev. 0 | Page 4 of 5
Circuit Note
CN-0279
Rarely Asked Questions: Considerations of High-Speed
LEARN MORE
Converter PCB Design, Part 1: Power and Ground Planes,
November 2010.
CN-0279 Design Support Package:
http://www.analog.com/CN0279-DesignSupport
Rarely Asked Questions: Considerations of High-Speed
Converter PCB Design, Part 2: Using Power and Ground
Planes to Your Advantage, February 2011.
UG-386 User Guide, Evaluating the AD9642/AD9634/AD6672
Analog-to-Digital Converters
Arrants, Alex, Brad Brannon and Rob Reeder, AN-835
Application Note, Understanding High Speed ADC Testing
and Evaluation, Analog Devices.
Rarely Asked Questions: Considerations of High-Speed Converter
PCB Design, Part 3: The E-Pad Low Down, June 2011.
Data Sheets and Evaluation Boards
AD9642 Data Sheet
Ardizzoni, John. A Practical Guide to High-Speed Printed-
Circuit-Board Layout, Analog Dialogue 39-09, September 2005.
ADL5565 Data Sheet
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of “AGND” and “DGND”, Analog Devices.
Circuit Evaluation Board (AD9642-250EBZ)
Standard Data Capture Platform (HSC-ADC-EVALCZ)
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
Quite Universal Circuit Simulator
REVISION HISTORY
Nuhertz Technologies, Filter Free Filter Design Program
7/12—Revision 0: Initial Version
Reeder, Rob, Achieve CM Convergence between Amps and ADCs,
Electronic Design, July 2010.
Reeder, Rob, Mine These High-Speed ADC Layout Nuggets For
Design Gold, Electronic Design, September 15, 2011.
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CN10823-0-7/12(0)
Rev. 0 | Page 5 of 5
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