DAC8043FP [ADI]
12-Bit Serial Input Multiplying CMOS D/A Converter; 12位串行输入乘法CMOS D / A转换器
| 型号： | DAC8043FP |
| 厂家： | 
ADI |
| 描述： | 12-Bit Serial Input Multiplying CMOS D/A Converter |
| 文件： | 总12页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Serial Input
Multiplying CMOS D/A Converter
a
DAC8043
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
12-Bit Accuracy in an 8-Pin Mini-DIP
Fast Serial Data Input
Double Data Buffers
Low ؎1/ 2 LSB Max INL and DNL
Max Gain Error: ؎1 LSB
Low 5 ppm / ؇C Max Tem pco
ESD Resistant
Low Cost
Available in Die Form
APPLICATIONS
Autocalibration System s
Process Control and Industrial Autom ation
Program m able Am plifiers and Attenuators
Digitally-Controlled Filters
P IN CO NNECTIO NS
8-P in Epoxy D IP
(P -Suffix)
8-P in Cer dip
(Z-Suffix)
GENERAL D ESCRIP TIO N
T he DAC8043 is a high accuracy 12-bit CMOS multiplying
DAC in a space-saving 8-pin mini-DIP package. Featuring serial
data input, double buffering, and excellent analog performance,
the DAC8043 is ideal for applications where PC board space is
at a premium. Also, improved linearity and gain error performance
permit reduced parts count through the elimination of trimming
components. Separate input clock and load DAC control lines
allow full user control of data loading and analog output.
T he circuit consists of a 12-bit serial-in, parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC, and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the D/A converter.
16-Lead Wide-Body SO L
(S-Suffix)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N.C.
N.C.
N.C.
N.C.
V
V
REF
DD
T he DAC8043’s fast interface timing may reduce timing design
considerations while minimizing microprocessor wait states. For
applications requiring an asynchronous CLEAR function or more
versatile microprocessor interface logic, refer to the PM-7543.
DAC8043
R
CLK
SRI
LD
FB
TOP VIEW
(Not to Scale)
I
OUT
GND
N.C.
N.C.
GND
N.C.
Operating from a single +5 V power supply, the DAC8043 is
the ideal low power, small size, high performance solution to
many application problems. It is available in plastic and cerdip
packages that are compatible with auto-insertion equipment.
NC = NO CONNECT
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
DAC8043–SPECIFICATIONS
(@ V = +5 V; V = +10 V; IOUT = GND = 0 V; T = Full Temperature Range
specified under Absolute Maximum Ratings unless otherwise noted).
DD
REF
A
ELECTRICAL CHARACTERISTICS
D AC8043
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
ST AT IC ACCURACY
Resolution
N
12
Bits
Nonlinearity
(Note 1)
Differential Nonlinearity
(Note 2)
INL
DAC8043A/E/G
DAC8043F
DAC8043A/E
DAC8043F/G
T A = +25°C
±1/2
1
±1/2
±1
LSB
LSB
LSB
LSB
DNL
GFSE
Gain Error
(Note 3)
DAC8043A/E
DAC8043F/G
T A = Full Temperature Range
All Grades
1
2
LSB
LSB
2
LSB
Gain T empco
(∆ Gain/∆ T emp)
(Note 5)
T CGFS
±5
ppm/°C
Power Supply
Rejection Ratio
PSRR
ILKG
∆VDD = ±5%
±0.0006
±0.002
±5
%/%
nA
(∆ Gain/∆ VDD
)
Output Leakage Current
(Note 4)
T A = +25°C
T A = Full T emperature Range
DAC8043A
DAC8043E/F/G
T A = +25°C
T A = Full T emperature Range
DAC8043A
±100
±25
0.03
nA
nA
LSB
Zero Scale Error
(Notes 7, 12)
IZSE
0.61
0.15
LSB
LSB
DAC8043E/F/G
Input Resistance
(Note 8)
RIN
7
11
15
kΩ
AC PERFORMANCE
Output Current
Settling T ime
tS
T A = +25°C
0.25
1
µs
(Notes 5, 6)
VREF = 0 V
Digital to Analog
Glitch Energy
(Note 5, 10)
IOUT Load = 100 Ω
CEXT = 13 pF
Q
2
20
1
nVs
DAC Register Loaded Alternately with
All 0s and All 1s
VREF = 20 V p-p @ f = 10 kHz
Digital Input = 0000 0000 0000
T A = +25°C
VREF = 6 V rms @ 1 kHz
DAC Register Loaded with All 1s
10 Hz to 100 kHz between RFB and IOUT
Feedthrough Error
(VREF to IOUT
(Note 5, 11)
)
FT
0.7
mV p-p
dB
T otal Harmonic Distortion
(Note 5)
Output Noise Voltage Density
(Note 5, 13)
T HD
en
–85
17
nV/√Hz
DIGIT AL INPUT S
Digital Input
HIGH
VIN
2.4
V
Digital Input
LOW
Input Leakage Current
(Note 9)
Input Capacitance
(Note 5, 11)
VIL
IIL
0.8
±1
V
µA
VIN = 0 V to +5 V
VIN = 0 V
CIN
8
pF
ANALOG OUT PUT S
Output Capacitance
(Note 5)
COUT
Digital Inputs = VIH
Digital Inputs = VIL
110
80
pF
pF
–2–
REV. C
DAC8043
D AC8043
Typ
P aram eter
Sym bol
Conditions
Min
Max
Units
T IMING CHARACT ERIST ICS (NOT ES 5, 14)
Data Setup T ime
Data Hold T ime
Clock Pulse Width High
Clock Pulse Width Low
Load Pulse Width
tDS
tDH
tCH
tCL
tLD
T A = Full T emperature Range
T A = Full T emperature Range
T A = Full T emperature Range
T A = Full T emperature Range
T A = Full T emperature Range
40
80
90
120
120
ns
ns
ns
ns
ns
LSB Clock Into Input Register
to Load DAC Register T ime
tASB
T A = Full T emperature Range
0
ns
POWER SUPPLY
Supply Voltage
Supply Current
VDD
IDD
4.75
5
5.25
500
100
V
Digital Inputs = VIH or VIL
Digital Inputs = 0 V or VDD
µA max
µA max
NOT ES
11±1/2 LSB = ±0.012% of full scale.
12All grades are monotonic to 12-bits over temperature.
13Using internal feedback resistor.
14Applies to IOUT; All digital inputs = 0 V.
15Guaranteed by design and not tested.
16
I
Load = 100 Ω, CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB; tS = propagation delay (tPD) + 9τ where τ = measured time
OUT
constant of the final RC decay.
17
V
= +10 V, all digital inputs = 0 V.
REF
18Absolute temperature coefficient is less than +300 ppm/°C.
19Digital inputs are CMOS gates; IIN is typically 1 nA at +25°C.
10
V
= 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.
REF
11All digit inputs = 0 V.
12Calculated from worst case RREF: IZSE (in LSBs) = (RREF × ILKG × 4096)/VREF
.
13Calculations from en = √4K TRB where: K = Boltzmann constant, J/°K, R = resistance, Ω, T = resistor temperature, °K, B = bandwidth, Hz.
14T ested at VIN = 0 V or VDD
.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS
CAUTIO N
(TA = +25°C unless otherwise noted)
1. Do not apply voltages higher than VDD or less than GND po-
tential on any terminal except VREF (Pin 1) and RFB (Pin 2).
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
Digital Input Voltage Range . . . . . . . . . . . . . . . –0.3 V to VDD
Output Voltage (Pin 3) . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Operating T emperature Range
2. T he digital control inputs are Zener-protected; however, per-
manent damage may occur on unprotected units from high
energy electrostatic fields. Keep units in conductive foam at
all times until ready to use.
3. Use proper antistatic handling procedures.
AZ Versions . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
EZ/FZ/FP Versions . . . . . . . . . . . . . . . . . . . –40°C to +85°C
GP Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
4. Absolute Maximum Ratings apply to both packaged devices
and DICE. Stresses above those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the device.
O RD ERING GUID E 1
Relative
Accuracy Range
Tem perature
P ackage
O ption
Model
P ackage Type
JA
*
JC
Units
DAC8043AZ2
±1/2 LSB
–55°C to +125°C 8-Pin Cerdip
–55°C to +125°C 8-Pin Cerdip
–40°C to +125°C 8-Pin Cerdip
8-Pin Hermetic DIP (Z)
8-Pin Plastic DIP (P)
134
96
12
37
°C/W
°C/W
DAC8043AZ/8832 ±1/2 LSB
DAC8043EZ
DAC8043FS
DAC8043FZ
DAC8043FP
DAC8043GP
DAC8043HP
NOT ES
±1/2 LSB
±1 LSB
±1 LSB
±1 LSB
±1/2 LSB
±1 LSB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
16-Lead (Wide) SOL
8-Pin Cerdip
8-Pin Epoxy DIP
8-Pin Epoxy DIP
8-Pin Epoxy DIP
*JA is specified for worst case mounting conditions, i. e., JA is specified for device
in socket for cerdip and P-DIP packages.
0°C to +70°C
1All commercial and industrial temperature range parts are available with burn-in.
2For devices processed in total compliance to MIL-ST D-883, add/883 after part
number. Consult factory for 883 data sheet.
REV. C
–3–
DAC8043
WAFER TEST LIMITS
P aram eter
@ V = +5 V, V = +10 V; IOUT = GND = 0 V, T = +25؇C.
DD
REF
A
D AC8043GBC
Lim it
Sym bol
Conditions
Units
ST AT IC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Gain Error
N
12
±1
±1
±2
±0.002
±5
Bits min
LSB max
LSB max
LSB max
%/% max
nA max
INL
DNL
GFSE
PSRR
ILKG
Using Internal Feedback Resistor
∆VDD = ±5%
Digital Inputs = VIL
Power Supply Rejection Ratio
Output Leakage Current (IOUT
)
REFERENCE INPUT
Input Resistance
RIN
7/15
kΩ min/max
DIGIT AL INPUT S
Digital Input HIGH
Digital Input LOW
Input Leakage Current
VIH
VIL
IIL
2.4
0.8
±1
V min
V max
µA max
VIN = 0 V to VDD
POWER SUPPLY
Supply Current
IDD
Digital Inputs = VIN or VIL
Digital Inputs = 0 V or VDD
500
100
µA max
µA max
NOT E
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
D ICE CH ARACTERISTICS
1. VREF
2. RFB
3. IOUT
4. GND
5. LD
6. SRI
7. CLK
8. VDD
Substate (die backside) is internally connected to VDD
.
DIE SIZE 0.116 × 0.109 inch, 12,644 sq. m ils (2.95 × 2.77 m m , 8.17 sq. m m )
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–4–
DAC8043
TYPICAL PERFORMANCE CHARACTERISTICS
Gain vs. Frequency (Output Am plifier: OP42)
Total Harm onic Distortion vs. Frequency
(Multiplying Mode)
Supply Current vs. Logic Input Voltage
Linearity Error vs. Digital Code
Linearity Error vs. Reference Voltage
Logic Threshold Voltage vs. Supply Voltage
DNL Error vs. Reference Voltage
REV. C
–5–
DAC8043
P ARAMETER D EFINITIO NS
INTEGRAL NO NLINEARITY (INL)
T his is the single most important DAC specification. ADI mea-
sures INL as the maximum deviation of the analog output (from
the ideal) from a straight line drawn between the end points. It
is expressed as a percent of full-scale range or in terms of LSBs.
Refer to PMI 1988 Data Book section 11 for additional digital-
to-analog converter definitions.
INTERFACE LO GIC INFO RMATIO N
T he DAC8043 has been designed for ease of operation. T he
timing diagram illustrates the input register loading sequence.
Note that the most significant bit (MSB) is loaded first.
Figure 1. Digital Input Protection
T he digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift regis-
ter and then transferred, in parallel, to the 12-bit DAC register.
Once the input register is full, the data is transferred to the
DAC register by taking LD momentarily low.
D IGITAL SECTIO N
A simplified circuit of the DAC8043 is shown in Figure 2. An
inverted R-2R ladder network consisting of silicon-chrome,
highly-stable (+50 ppm/°C) thin-film resistors, and twelve pairs
of NMOS current-steering switches.
T he DAC8043’s digital inputs, SRI, LD, and CLK, are T T L
compatible. T he input voltage levels affect the amount of cur-
rent drawn from the supply; peak supply current occurs as the
digital input (VIN) passes through the transition region. See the
Supply Current vs. Logic Input Voltage graph located under the
typical performance characteristics curves. Maintaining the digi-
tal input voltage levels as close as possible to the supplies, VDD
and GND, minimizes supply current consumption.
T hese switches steer binarily weighted currents into either IOUT
or GND; this yields a constant current in each ladder leg, regard-
less of digital input code. T his constant current results in a con-
stant input resistance at VREF equal to R. T he VREF input may
be driven by any reference voltage or current, ac or dc that is
within the limits stated in the Absolute Maximum Ratings.
T he DAC8043’s digital inputs have been designed with ESD re-
sistance incorporated through careful layout and the inclusion of
input protection circuitry. Figure 1 shows the input protection
diodes and series resistor; this input structure is duplicated on
each digital input. High voltage static charges applied to the in-
puts are shunted to the supply and ground rails through forward
biased diodes. T hese protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.
T he twelve output current-steering NMOS FET switches are in
series with each R-2R resistor, they can introduce bit errors if all
are of the same RON resistance value. T hey were designed such
that the switch “ON” resistance be binarily scaled so that the
voltage drop across each switch remains constant. If, for ex-
ample, switch 1 of Figure 2 was designed with an “ON” resis-
tance of 10 Ω, switch 2 for 20 Ω, etc., a constant 5 mV drop will
then be maintained across each switch.
GENERAL CIRCUIT INFO RMATIO N
T he DAC8043 is a 12-bit multiplying D/A converter with a very
low temperature coefficient. It contains an R-2R resistor ladder
network, data input and control logic, and two data registers.
Write Cycle Tim ing Diagram
REV. C
–6–
DAC8043
D YNAMIC P ERFO RMANCE
O UTP UT IMP ED ANCE
T o further insure accuracy across the full temperature range,
permanently “ON” MOS switches were included in series with
the feedback resistor and the R-2R ladder’s terminating resistor.
T he “Simplified DAC Circuit,” Figure 2, shows the location of
the series switches. T hese series switches are equivalently scaled
to two times switch 1 (MSB) and to switch 12 (LSB) respec-
tively to maintain constant relative voltage drops with varying
temperature. During any testing of the resistor ladder or
RFEEDBACK (such as incoming inspection), VDD must be present
to turn “ON” these series switches.
T he DAC8043’s output resistance, as in the case of the output
capacitance, varies with the digital input code. T his resistance,
looking back into the IOUT terminal, may be between 10 kΩ (the
feedback resistor alone when all digital inputs are LOW) and
7.5 kΩ (the feedback resistor in parallel with approximate 30 kΩ
of the R-2R ladder network resistance when any single bit logic
is HIGH). Static accuracy and dynamic performance will be af-
fected by these variations.
T his variation is best illustrated by using the circuit of Figure 4
and the equation:
RFB
RO
1+
VERROR = VOS
where RO is a function of the digital code, and:
RO = 10 kΩ for more than four bits of logic 1.
RO = 30 kΩ for any single bit of logic 1.
T herefore, the offset gain varies as follows:
at code 0011 1111 1111,
10 kΩ
10 kΩ
1+
VERROR1 = VOS
= 2 VOS
at code 0100 0000 0000,
10 kΩ
30 kΩ
1+
Figure 2. Sim plified DAC Circuit
VERROR2 = VOS
= 4/3 VOS
EQ UIVALENT CIRCUIT ANALYSIS
T he error difference is 2/3 VOS
.
Figure 3 shows an equivalent analog circuit for the DAC8043.
T he (D × VREF)/R current source is code dependent and is the
current generated by the DAC. T he current source ILKG consists
of surface and junction leakages and doubles approximately ev-
ery 10°C. COUT is the output capacitance; it is the result of the
N-channel MOS switches and varies from 80 pF to 110 pF
depending on the digital input code. RO is the equivalent output
resistance that also varies with digital input code. R is the nomi-
nal R-2R resistor ladder resistance.
Since one LSB has a weight (for VREF = +10 V) of 2.4 mV for
the DAC8043, it is clearly important that VOS be minimized,
either using the amplifier’s nulling pins, an external nulling net-
work, or by selection of an amplifier with inherently low VOS
.
Amplifiers with sufficiently low VOS include ADI’s OP77, OP07,
OP27, and OP42.
Figure 3. Equivalent Analog Circuit
Figure 4. Sim plified Circuit
REV. C
–7–
DAC8043
T he gain and phase stability of the output amplifier, board lay-
out, and power supply decoupling will all affect the dynamic
performance. T he use of a small compensation capacitor may be
required when high-speed operational amplifiers are used. It
may be connected across the amplifier’s feedback resistor to
provide the necessary phase compensation to critically damp the
output. T he DAC8043’s output capacitance and the RFB resis-
tor form a pole that must be outside the amplifier’s unity gain
crossover frequency.
T he considerations when using high-speed amplifiers are:
1. Phase compensation (see Figures 5 and 6).
2. Power supply decoupling at the device socket and use of
proper grounding techniques.
Figure 6. Unipolar Operation with Fast Op Am p and Gain
Error Trim m ing (2-Quadrant)
the analog output is shown in T able I. T he limiting parameters
for the VREF range are the maximum input voltage range of the
op amp or ±25 V, whichever is lowest.
AP P LICATIO NS INFO RMATIO N
AP P LICATIO N TIP S
In most applications, linearity depends upon the potential of
IOUT and GND (pins 3 and 4) being exactly equal to each other.
In most applications, the DAC is connected to an external op
amp with its noninverting input tied to ground (see Figures 5
and 6). T he amplifier selected should have a low input bias cur-
rent and low drift over temperature. T he amplifier’s input offset
voltage should be nulled to less than +200 µV (less than 10% of
1 LSB).
Gain error may be trimmed by adjusting R1 as shown in Figure
6. T he DAC register must first be loaded with all 1s. R1 may
then be adjusted until VOUT = –VREF (4095/4096). In the case of
an adjustable VREF, R1 and R2 may be omitted, with VREF ad-
justed to yield the desired full-scale output.
In most applications the DAC8043’s negligible zero scale error
and very low gain error permit the elimination of the trimming
components (R1 and the external R2) without adverse effects on
circuit performance.
T he operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias cur-
rent compensation resistor should not be used. T his resistor can
cause a variable offset voltage appearing as a varying output er-
ror. All grounded pins should tie to a single common ground
point, avoiding ground loops. T he VDD power supply should
have a low noise level with no transients greater than +17 V.
Table I. Unipolar Code Table
D igital Input
MSB
Nom inal Analog O utput
(VO UT as shown in Figures 5 and 6)
LSB
UNIP O LAR O P ERATIO N (2-Q UAD RANT)
4095
–VREF
T he circuit shown in Figures 5 and 6 may be used with an ac or
dc reference voltage. The circuit’s output will range between 0 V
and approximately –VREF (4095/4096) depending upon the digital
input code. The relationship between the digital input and
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
4096
2049
–VREF
4096
2048
V
REF
–VREF
–VREF
–VREF
–VREF
= –
4096
2
2047
4096
1
4096
0
4096
0000 0000 0000
= 0
NOT ES
1Nominal full scale for the circuits of Figures 5 and 6 is given by
4095
FS = –VREF
4096
Figure 5. Unipolar Operation with High Accuracy Op Am p
(2-Quadrant)
2Nominal LSB magnitude for the circuits of Figures 5 and 6 is given by
1
LSB = VREF
or VREF (2–n).
4096
REV. C
–8–
DAC8043
Table II. Bipolar (O ffset Binary) Code Table
Resistors R3, R4, and R5 must be selected to match within 0.01%
and must all be of the same (preferably metal foil) type to assure
temperature coefficient matching. Mismatching between R3 and
R4 causes offset and full scale errors while an R5 to R4 and R3
mismatch will result in full-scale error.
D igital Input
MSB
Nom inal Analog O utput
(VO UT as Shown in Figure 7)
LSB
2047
2048
Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may
be omitted, adjusting the ratio of R3 to R4 to yield VOUT = 0 V.
Full scale can be adjusted by loading the DAC register with
1111 1111 1111 and either adjusting the amplitude of VREF or
the value of R5 until the desired VOUT is achieved.
1111 1111 1111
+VREF
1
1000 0000 0001
1000 0000 0000
+VREF
2048
0
ANALO G/D IGITAL D IVISIO N
1
0111 1111 1111
0000 0000 0001
–VREF
T he transfer function for the DAC8043 connected in the multi-
plying mode as shown in Figures 5, 6 and 7 is:
2048
2047
2048
–VREF
A
A
A
3 +...
A
12
212
1
2
+
+
VO = –VIN
21 22 23
2048
2048
where AX assumes a value of 1 for an “ON” bit and 0 for an
“OFF” bit.
0000 0000 0000
–VREF
NOT ES
T he transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 8
and becomes:
1Nominal full scale for the circuit of Figure 7 is given by
2047
FS = VREF
.
2048
2Nominal LSB magnitude for the circuit of Figure 7 is given by
–VIN
1
VO
=
A
A
A
A
12
24
LSB = VREF
.
1
2
+
+
3 +...
2048
21 22 23
BIP O LAR O P ERATIO N (4-Q UAD RANT)
Figure 7 details a suggested circuit for bipolar, or offset binary
operation. T able II shows the digital input to analog output re-
lationship. T he circuit uses offset binary coding. T wo’s comple-
ment code can be converted to offset binary by software
inversion of the MSB or by the addition of an external inverter
to the MSB input.
T he above transfer function is the division of an analog voltage
(VREF) by a digital word. T he amplifier goes to the rails with all
bits “OFF” since division by zero is infinity. With all bits “ON,”
the gain is 1 (±1 LSB). T he gain becomes 4096 with the LSB,
bit 12 “ON.”
Figure 7. Bipolar Operation (4-Quadrant, Offset Binary)
REV. C
–9–
DAC8043
D AC8043 INTERFACE TO TH E 8085
T he DAC8043’s interface to the 8085 microprocessor is shown
in Figure 10. Note that the microprocessor’s SOD line is used
to present data serially to the DAC.
Data is clocked into the DAC8043 by executing memory write
instructions. T he clock input is generated by decoding address
8000 and WR. Data is loaded into the DAC register with a
memory write instruction to address A000.
Serial data supplied to the DAC8043 must be present in the
right justified format in registers H and L of the microprocessor.
Figure 8. Analog/Digital Divider
INTERFACING TO TH E MC6800
As shown in Figure 9, the DAC8043 may be interfaced to the
6800 by successively executing memory WRIT E instructions
while manipulating the data between WRIT Es, so that each
WRIT E presents the next bit.
In this example the most significant bits are found in memory
location 0000 and 0001. T he four MSBs are found in the lower
half of 0000, the eight LSBs in 0001. T he data is taken from the
DB7 line.
Figure 10. DAC8043-8085 Interface
D AC8043 TO 68000 INTERFACING
T he DAC8043 interfacing to the 68000 microprocessor is
shown in Figure 11. Again, serial data to the DAC is taken from
one of the microprocessor’s data bus lines.
T he serial data loading is triggered by the CLK pulse which is
asserted by a decoded memory WRIT E to memory location
2000, R/W, and φ2. A WRIT E to address 4000 transfers data
from input register to DAC register.
Figure 11. DAC8043–68000 µP Interface
Figure 9. DAC8043–MC6800 Interface
REV. C
–10–
–11–
–12–
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