DAC8420_07 [ADI]
Quad 12-Bit Serial Voltage Output DAC; 四通道12位串行电压输出DAC型号: | DAC8420_07 |
厂家: | ADI |
描述: | Quad 12-Bit Serial Voltage Output DAC |
文件: | 总24页 (文件大小:1183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Quad 12-Bit Serial
Voltage Output DAC
DAC8420
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREFHI
VDD
Guaranteed monotonic over temperature
Excellent matching between DACs
Unipolar or bipolar operation
Buffered voltage outputs
High speed serial digital interface
Reset-to-zero scale or midscale
Wide supply range, +5 V only to 15 V
Low power consumption (35 mW maximum)
Available in 16-Lead PDIP, SOIC, and CERDIP packages
5
1
DAC8420
10
SDI
REG
A
7
6
3
2
DAC A
DAC B
DAC C
DAC D
VOUTA
VOUTB
VOUTC
VOUTD
12
12
11
CS
REG
B
CLK
SHIFT
REGISTER
13
14
NC
LD
APPLICATIONS
REG
C
4
Software controlled calibration
Servo controls
Process control and automation
ATE
DECODE
REG
D
2
9
16
CLSEL CLR
8
15
4
GND
VREFLO
VSS
Figure 1.
GENERAL DESCRIPTION
asynchronously overriding the current DAC register values. The
output voltage range, determined by the inputs VREFHI and
VREFLO, is set by the user for positive or negative unipolar or
bipolar signal swings within the supplies, allowing considerable
design flexibility.
The DAC8420 is a quad, 12-bit voltage-output DAC with serial
digital interface in a 16-lead package. Utilizing BiCMOS tech-
nology, this monolithic device features unusually high circuit
density and low power consumption. The simple, easy-to-use
serial digital input and fully buffered analog voltage outputs
require no external components to achieve a specified per-
formance.
The DAC8420 is available in 16-lead PDIP, SOIC, and CERDIP
packages. Operation is specified with supplies ranging from
+5 V only to 15 V, with references of +2.5 V to 10 V, respec-
tively. Power dissipation when operating from 15 V supplies is
less than 255 mW (maximum) and only 35 mW (maximum)
with a +5 V supply.
The 3-wire serial digital input is easily interfaced to micro-
processors running at 10 MHz with minimal additional
circuitry. Each DAC is addressed individually by a 16-bit
serial word consisting of a 12-bit data word and an address
CLR
header. The user-programmable reset control
forces all
four DAC outputs to either zero scale or midscale,
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
DAC8420
TABLE OF CONTENTS
Features .............................................................................................. 1
CS
Correct Operation of
and CLK........................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Introduction ................................................................................ 14
Digital Interface Operation....................................................... 14
CLR
Using
and CLSEL .............................................................. 14
Programming the Analog Outputs .......................................... 14
VREFHI Input Requirements................................................... 16
Power-Up Sequence ................................................................... 16
Applications..................................................................................... 17
Power Supply Bypassing and Grounding................................ 17
Analog Outputs .......................................................................... 17
Reference Configuration ........................................................... 18
Isolated Digital Interface ........................................................... 19
Dual Window Comparator ....................................................... 20
MC68HC11 Microcontroller Interfacing................................ 20
DAC8420 to M68HC11 Interface Assembly Program.......... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
5/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Endnote 3 ...................................................................... 4
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 2
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 23
9/03—Rev. 0 to Rev. A
Changes to General Description .................................................... 1
Deleted Wafer Test Limits table...................................................... 4
Deleted Dice Characteristics........................................................... 4
Updated Ordering Guide................................................................. 4
Added Power-Up Sequence section ............................................. 12
Updated Outline Dimensions....................................................... 17
Rev. B | Page 2 of 24
DAC8420
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1
@ VDD = +5.0 V 5ꢀ, VSS = 0 V, VVREFHI = +2.5 V, VVREFLD = 0 V, and VSS = −5.0 V 5ꢀ, VVREFLO = −2.5 V, −40°C ≤ TA ≤ +85°C unless
otherwise noted.2
Table 1.
Parameter
Symbol Condition
Min
Typ
Max
Unit
STATIC ACCURACY
Integral Linearity E Grade
Integral Linearity E Grade
Integral Linearity F Grade
Integral Linearity F Grade
Differential Linearity
Zero-Scale Error
Full-Scale Error
Zero-Scale Error
Full-Scale Error
Zero-Scale Temperature Coefficient
Full-Scale Temperature Coefficient
MATCHING PERFORMANCE
Linearity Matching
INL
INL
INL
INL
DNL
ZSE
FSE
ZSE
FSE
TCZSE
TCFSE
±±
±ꢁ
±ꢂ
±ꢀ
±ꢀ
±3
±2
±4
±ꢀ
±4
±4
±ꢃ
±ꢃ
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
VSS = 0 V3
VSS = 0 V3
Monotonic over temperature
RL = 2 kΩ, VSS = −5 V
RL = 2 kΩ, VSS = −5 V
RL = 2 kΩ, VSS = 0 V3
RL = 2 kΩ, VSS = 0 V3
RL = 2 kΩ, VSS = −5 V4
RL = 2 kΩ, VSS = −5 V4
±±
LSB
ppm/°C
ppm/°C
±ꢀ0
±ꢀ0
±ꢀ
LSB
REFERENCE
Positive Reference Input Range5
Negative Reference Input Range5
Negative Reference Input Range
Reference High Input Current
Reference Low Input Current
AMPLIFIER CHARACTERISTICS
Output Current
VVREFHI
VVREFLO
VVREFLO
IVREFHI
VVREFLO + 2.5
VSS
0
−0.75
−ꢀ.0
VDD − 2.5
VVREFHI − 2.5
VVREFHI − 2.5
V
V
V
mA
mA
VSS = 0 V5
Code 0x000, Code 0x555
Code 0x000, Code 0x555, VSS = −5 V
±0.25 +0.75
−0.6
IVREFLO
IOUT
tS
SR
VSS = −5 V
To 0.0ꢀ%6
ꢀ0% to 90%6
−ꢀ.25
2.4
+ꢀ.25
mA
μs
V/μs
Settling Time
Slew Rate
ꢃ
ꢀ.5
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Input Capacitance4
VINH
VINL
IIN
V
V
μA
pF
0.ꢃ
ꢀ0
CIN
ꢀ3
LOGIC TIMING CHARACTERISTICS4, 7
Data Setup Time
Data Hold
Clock Pulse Width High
Clock Pulse Width Low
Select Time
Deselect Delay
Load Disable Time
Load Delay
Load Pulse Width
tDS
tDH
tCH
tCL
tCSS
tCSH
tLDꢀ
tLD2
tLDW
tCLRW
25
55
90
ꢀ20
90
5
ꢀ30
35
ꢃ0
ꢀ50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clear Pulse Width
Rev. B | Page 3 of 24
DAC8420
Parameter
Symbol Condition
Min
Typ
Max
Unit
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSRR
IDD
ISS
0.002
4
−3
0.0ꢀ
7
%/%
mA
mA
−6
PDISS
VSS = 0 V
20
35
mW
ꢀ Typical values indicate performance measured at 25°C.
2 All supplies can be varied ±5% and operation is guaranteed. Device is tested with VDD = 4.75 V.
3 For single-supply operation (VVREFLO = 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at Code 0x005.
4 Guaranteed, but not tested.
5 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
6 VOUT swing between +2.5 V and −2.5 V with VDD = 5.0 V.
7 All input control signals are specified with tr = tf = 5 ns (ꢀ0% to 90% of 5 V) and timed from a voltage level of ꢀ.6 V.
Rev. B | Page 4 of 24
DAC8420
@ VDD = +15.0 V 5ꢀ, VSS = −15.0 V 5ꢀ, VVREFHI = +10.0 V, VVREFLO = −10.0 V, −40°C ≤ TA ≤ +85°C unless otherwise noted.1, 2
Table 2.
Parameter
Symbol Condition
Min
Typ
Max
Unit
STATIC ACCURACY
Integral Linearity E Grade
Integral Linearity F Grade
Differential Linearity
Zero-Scale Error
Full-Scale Error
Zero-Scale Temperature Coefficient
Full-Scale Temperature Coefficient TCFSE
MATCHING PERFORMANCE
Linearity Matching
INL
INL
DNL
ZSE
FSE
TCZSE
±±
±ꢁ
±±
±ꢁ
±ꢀ
±ꢀ
±2
±2
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
Monotonic over temperature
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ3
RL = 2 kΩ3
±4
±4
±ꢀ
LSB
REFERENCE
Positive Reference Input Range4
Negative Reference Input Range4
Reference High Input Current
Reference Low Input Current
AMPLIFIER CHARACTERISTICS
Output Current
VVREFHI
VVREFLO
IVREFHI
VVREFLO + 2.5
−ꢀ0
−2.0
VDD − 2.5
VVREFHI − 2.5
+2.0
V
V
mA
mA
Code 0x000, Code 0x555
Code 0x000, Code 0x555
±ꢀ.0
−2.0
IVREFLO
−3.5
IOUT
tS
SR
−5
+5
mA
μs
V/μs
Settling Time
Slew Rate
To 0.0ꢀ%5
ꢀ0% to 90%5
ꢀ3
2
DYNAMIC PERFORMANCE
Analog Crosstalk3
Digital Feedthrough3
Large Signal Bandwidth
Glitch Impulse
>64
>72
90
dB
dB
kHz
μV-s
3 dB, VVREFHI = 5 V + ꢀ0 V p-p, VVREFLO = −ꢀ0 V3
Code Transition = 0x7FF to 0xꢃ003
6
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Input Capacitance3
VINH
VINL
IIN
2.4
V
V
μA
pF
0.ꢃ
ꢀ0
CIN
ꢀ3
LOGIC TIMING CHARACTERISTICS3, 6
Data Setup Time
Data Hold
Clock Pulse Width High
Clock Pulse Width Low
Select Time
Deselect Delay
Load Disable Time
Load Delay
Load Pulse Width
tDS
tDH
tCH
tCL
tCSS
tCSH
tLDꢀ
tLD2
tLDW
tCLRW
25
20
30
50
55
ꢀ5
40
ꢀ5
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clear Pulse Width
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSRR
IDD
ISS
0.002 0.0ꢀ
%/%
mA
mA
6
9
−ꢃ
−5
PDISS
255
mW
ꢀ Typical values indicate performance measured at 25°C.
2 All supplies can be varied ±5% and operation is guaranteed.
3 Guaranteed, but not tested.
4 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
5 VOUT swing between +ꢀ0 V and −ꢀ0 V.
6 All input control signals are specified with tr = tf = 5 ns (ꢀ0% to 90% of 5 V) and timed from a voltage level of ꢀ.6 V.
Rev. B | Page 5 of 24
DAC8420
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 4.
Table 3.
Package Type
ꢀ6-Lead PDIP (N)
ꢀ6-Lead CERDIP (Q)
ꢀ6-Lead SOIC (RW)
θJA
70ꢀ
ꢃ2ꢀ
ꢃ62
θJC
27
9
Unit
°C/W
°C/W
°C/W
Parameter
Rating
VDD to GND
VSS to GND
VSS to VDD
VSS to VVREFLO
VVREFHI to VVREFLO
VVREFHI to VDD
IVREFHI, IVREFLO
Digital Input Voltage to GND
Output Short-Circuit Duration
Operating Temperature Range
EP, FP, ES, FS, EQ, FQ
Dice Junction Temperature
Storage Temperature Range
Power Dissipation
Lead Temperature
Soldering
−0.3 V, +ꢀꢃ.0 V
+0.3 V, −ꢀꢃ.0 V
−0.3 V, +36.0 V
−0.3 V, VSS − 2.0 V
+2.0 V, VDD − VSS
+2.0 V, +33.0 V
ꢀ0 mA
22
ꢀ θJA is specified for worst case mounting conditions, that is, θJA is specified for
device in socket.
2 θJA is specified for device on board.
ESD CAUTION
−0.3 V, VDD + 0.3 V
Indefinite
–40°C to +ꢃ5°C
ꢀ50°C
–65°C to +ꢀ50°C
ꢀ000 mW
JEDEC Industry Standard
J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 6 of 24
DAC8420
DATA LOAD SEQUENCE
CS
tCSH
tCSS
SDI
A1
A0
X
X
D11
D10
D9
D8
D4
D3
D2
D1
D0
CLK
LD
tLD1
tLD2
tDS
tDH
DATA LOAD TIMING
CLEAR TIMING
CLSEL
SDI
tCLRW
CLR
CLK
CS
tCH
tCL
tS
tCSH
V
OUT
tLD2
tLDW
±1LSB
LD
tS
VOUTx
±1LSB
Figure 2. Timing Diagram
5kΩ
10kΩ
+15V
1N4001
1
16
+
10µF
0.1µF
NC
NC
2
3
4
5
6
7
8
15
14
10kΩ
–10V
1N4001
13 NC
DUT
10µF
0.1µF
0.1µF
+
+
12
11
10
9
5kΩ
NC
NC
10kΩ
+10V
1N4001
10µF
10kΩ
10kΩ
–15V
1N4001
NC = NO CONNECT
10µF
0.1µF
+
Figure 3. Burn-In Diagram
Rev. B | Page 7 of 24
DAC8420
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
1
2
3
4
5
6
7
8
16 CLSEL
15 CLR
14 LD
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
1
2
3
4
5
6
7
8
16 CLSEL
15 CLR
14 LD
DAC8420
TOP VIEW
DAC8420
13 NC
13 NC
TOP VIEW
(Not to Scale)
12 CS
(Not to Scale)
12 CS
11 CLK
10 SDI
11 CLK
10 SDI
9
GND
9
GND
NC = NO CONNECT
NC = NO CONNECT
Figure 4. PDIP and CERDIP
Figure 5. SOIC
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
ꢀ
4
VDD
VREFLO
Positive Power Supply, 5 V to ꢀ5 V.
Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable
range is VSS to (VVREFHI − 2.5 V).
5
VREFHI
Reference Input. Upper DAC ladder reference voltage input. Allowable range is (VDD − 2.5 V) to
(VVREFLO + 2.5 V).
7, 6, 3, 2
ꢃ
9
ꢀ0
VOUTA through VOUTD
Buffered DAC Analog Voltage Outputs.
Negative Power Supply, 0 V to −ꢀ5 V.
Power Supply, Digital Ground.
Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register,
which shifts data in, beginning with DAC Address Bit Aꢀ. This input is ignored when CS is high. SDI
is CMOS/TTL compatible. The format of the ꢀ6-bit serial word is shown in Table ꢃ.
VSS
GND
SDI
ꢀꢀ
ꢀ2
CLK
CS
System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed
with CS.
Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and
disables the serial data register input when high. When low, data input clocking is enabled (see
Table 6). CS is CMOS/TTL compatible.
ꢀ3
ꢀ4
NC
LD
No Connect = Don’t Care.
Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained
in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD,
independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible.
ꢀ5
ꢀ6
CLR
Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to
zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is
unaffected by this control. CLR is CMOS/TTL compatible.
CLSEL
Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A
through Register D to midscale (0xꢃ00). If low, the registers are set to zero (0x000). CLSEL is CMOS/
TTL compatible.
Rev. B | Page ꢃ of 24
DAC8420
Table 6. Control Function Logic Table
CLK1
CS1
LD
CLR
CLSEL
Serial Input Shift Register
DAC Register A to DAC Register D
NC2
NC2
NC2
↑
Low
High
High
NC2
High
High
High
Low
↑
NC (↑)2
NC2
High
High
High
High
High
↓
Low
Low
↑
High
High
High
High
High
High
Low
High /Low
NC2
NC2
NC2
NC2
NC2
No change
No change
No change
Shifts register one bit
Shifts register one bit
No change
Loads midscale value (0xꢃ00)
Loads zero-scale value (0x000)
Latches value
No change
No change
Loads the serial data-word3
Transparent4
Low
High
No change
No change
High
No change
ꢀ
CS
CLK and are interchangeable.
2 NC = Don’t Care.
3
CS
CS
Returning high while CLK is high avoids an additional false clock of serial input data. CLK and are interchangeable.
4
LD
Do not clock in serial data while
is low.
Rev. B | Page 9 of 24
DAC8420
TYPICAL PERFORMANCE CHARACTERISTICS
0.3
0.4
0.3
0.2
0.1
0
T
= +25°C
= +5V
A
T
= +25°C
A
V
V
V
DD
V
V
V
= +15V
= –15V
DD
SS
0.2
0.1
= 0V
SS
VREFLO
= 0V
= –10V
VREFLO
0
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
–0.4
–6
–4
–2
0
2
4
6
8
10
12
14
1.5
2.0
2.5
3.0
3.5
V
(V)
V
(V)
VREFHI
VREFHI
Figure 6. DNL vs. VVREFHI
(
15 V)
Figure 9. INL vs. VVREFHI (+5 V)
0.7
0.5
0.3
0.10
0.05
0
x + 3σ
T
= +25°C
= +5V
A
V
V
V
DD
V
V
V
V
= +15V
= –15V
DD
SS
= 0V
SS
VREFLO
= 0V
= +10V
VREFHI
= –10V
VREFLO
–0.05
–0.10
–0.15
x
0.1
–0.1
–0.3
–0.5
–0.20
–0.25
x – 3σ
0
200
400
600
800
1000
–0.30
1.5
2.0
2.5
3.0
3.5
t
= HOURS OF OPERATION AT 125°C
CURVES NOT NORMALIZED
V
(V)
VREFHI
Figure 7. DNL vs. VVREFHI (+5 V)
Figure 10. Full-Scale Error vs. Time Accelerated by Burn-In
1.2
0.3
0.2
x + 3σ
1.0
0.8
V
V
V
V
= +15V
= –15V
DD
SS
= +10V
= –10V
0.1
VREFHI
VREFLO
x
0.6
0.4
0.2
0
0
–0.1
–0.2
–0.3
T
= +25°C
A
V
V
V
= +15V
= –15V
DD
SS
= –10V
VREFLO
x – 3σ
0
200
t
400
600
800
1000
–6
–4
–2
0
2
4
6
8
10
12
14
= HOURS OF OPERATION AT 125°C
CURVES NOT NORMALIZED
V
(V)
VREFHI
Figure 8. INL vs. VREFHI ( 15 V)
Figure 11. Zero-Scale Error vs. Time Accelerated by Burn-In
Rev. B | Page ꢀ0 of 24
DAC8420
0.2
0.1
1.5
1.0
0.5
0
T
= +25°C
A
V
V
V
V
= +15V
= –15V
DD
SS
V
V
V
V
= +5V
= 0V
DD
SS
= +10V
= –10V
VREFHI
= +2.5V
= 0V
VREFHI
VREFLO
0
–0.1
–0.2
VREFLO
DAC C
DAC D
DAC A
–0.5
–0.3
–0.4
–0.5
–0.6
–1.0
–1.5
DAC B
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
–75
–50
–25
0
25
50
C)
75
100
125
TEMPERATURE (
°
Figure 15. Channel-to-Channel Matching
Figure 12. Full-Scale Error vs. Temperature
13
12
1.2
1.0
T = +25°C
A
V
V
V
V
= +15V
= –15V
DD
V
V
V
= +15V
= –15V
DD
SS
SS
= +10V
= –10V
VREFHI
VREFLO
11
10
9
= –10V
VREFLO
0.8
0.6
0.4
DAC B
DAC C
DAC D
DAC A
8
7
0.2
0
6
–0.2
–0.4
5
4
–7
–5
–3
–1
0
1
3
5
7
9
11
13
–75
–50
–25
0
25
50
C)
75
100
125
V
(V)
TEMPERATURE (
°
VREFHI
Figure 13. Zero-Scale Error vs. Temperature
Figure 16. IDD vs. VVREFHI, All DACs High
0.8
0.9
0.7
T
= +25°C, –55°C, 125°C
= +15V
T
= +25°C
= +15V
A
A
0.7
0.6
V
V
V
V
V
V
V
V
DD
DD
= –15V
= –15V
SS
SS
= +10V
= –10V
= +10V
= –10V
0.5
VREFHI
VREFHI
0.5
0.4
VREFLO
VREFLO
0.3
0.3
0.1
0.2
0.1
–0.1
–0.3
–0.5
–0.7
–0.9
0
–0.1
–0.2
–0.3
–0.4
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
Figure 14. Channel-to-Channel Matching
Figure 17. INL vs. Code
Rev. B | Page ꢀꢀ of 24
DAC8420
1.5
31.25mV
LD
T
= +25°C
A
1.0
0.5
V
V
V
V
= +15V
= –15V
DD
SS
= +10V
= –10V
VREFHI
VREFLO
0
T
= +25°C
4.88mV
A
1 LSB
0mV
V
V
V
V
= +15V
= –15V
DD
SS
–0.5
–1.0
= +10V
= –10V
VREFHI
VREFLO
–18.75mV
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
–9.8µs
10µs/DIV
90.2µs
tSETT
13µs
Figure 18. IVREFHI vs. Code
Figure 21. Positive Settling Time ( 15 V)
–2.50µV
LD
43.75mV
CLR
T
= +25°C
= +5V
T
= +25°C
A
A
V
V
V
V
V
V
V
V
= +15V
= –15V
DD
DD
SS
= –5V
SS
= +2.5V
= –2.5V
= +10V
= –10V
VREFHI
VREFHI
1.22mV
1 LSB
0mV
VREFLO
VREFLO
0mV
1 LSB
–4.88mV
–10.25mV
–6.25mV
–9.8µs
–4.9µs
5µs/DIV
45.1µs
10µs/DIV
90.2µs
tSETT
8µs
tSETT
13µs
Figure 19. Positive Settling Time ( 5 V)
Figure 22. Negative Settling Time ( 15 V)
6.5mV
CLR
5V
T
= +25°C
A
V
V
V
V
= +5V
= –5V
DD
SS
T
= +25°C
A
V
V
V
V
= +5V
= –5V
DD
SS
= +2.5V
= –2.5V
VREFHI
VREFLO
= +2.5V
= –2.5V
VREFHI
VREFLO
+1V/DIV
0
0mV
1 LSB
1.22mV
–5V
–47.6µs
3.5mV
–4.9µs
5µs/DIV
45.1µs
20µs/DIV
152.4µs
V
µs
V
µs
SR
RISE
= 1.65
SR
= 1.17
FALL
tSETT
8µs
Figure 20. Negative Settling Time ( 5 V)
Figure 23. Slew Rate ( 5 V)
Rev. B | Page ꢀ2 of 24
DAC8420
6
25V
LD
I
DD
4
2
CLR
V
V
V
V
= +15V
= –15V
DD
SS
+5V/DIV
0
= +10V
= –10V
VREFHI
0
VREFLO
ALL DACS HIGH (FULL SCALE)
T
= +25°C
A
V
V
V
V
= +15V
= –15V
DD
SS
–2
–4
–6
= +10V
= –10V
VREFHI
VREFLO
I
SS
–25V
–33.6µs
–75
0
75
150
20µs/DIV
166.4µs
V
µs
V
µs
SR
RISE
= 1.9
SR = 2.02
FALL
TEMPERATURE (°C)
Figure 24. Slew Rate ( 15 V)
Figure 27. Power Supply Current vs. Temperature
VOUTA THROUGH VOUTD
T
= +25°C
A
V
V
V
V
= +15V
= –15V
DD
SS
10
0
= +10V
= –10V
VREFHI
VREFLO
–10
–20
–30
DATA = 0x800
T
= +25°C
A
V
V
V
V
= +15V
= –15V
DD
SS
= 0 ±100mV
VREFHI
= –10V
VREFLO
ALL BITS HIGH 200mV p-p
5V/DIV
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 25. Small-Signal Response
Figure 28. DAC Output Current vs. VOUTx
100
90
80
70
60
50
40
30
20
10
0
10
8
6
4
T
= +25°C
A
T = +25°C
A
DATA = 0x000
V
V
V
V
= +15V
= –15V
DD
SS
V
V
V
V
= +15V ±1V
= –15V
DD
2
SS
= +10V
= –10V
VREFHI
= +10V
= –10V
VREFHI
VREFLO
VREFLO
DATA = 0xFFF OR 0x000
0
10
10
100
1k
10k
100k
1M
100
1k 10k
FREQUENCY (Hz)
LOAD RESISTANCE (Ω)
Figure 26. PSRR vs. Frequency
Figure 29. Output Swing vs. Load Resistance
Rev. B | Page ꢀ3 of 24
DAC8420
THEORY OF OPERATION
INTRODUCTION
USING CLR AND CLSEL
The DAC8420 is a quad, voltage-output 12-bit DAC with a serial
digital input capable of operating from a single 5 V supply. The
straightforward serial interface can be connected directly to
most popular microprocessors and microcontrollers, and can
accept data at a 10 MHz clock rate when operating from 15 V
supplies. A unique voltage reference structure ensures maximum
utilization of the DAC output resolution by allowing the user to
set the zero-scale and full-scale output levels within the supply
rails. The analog voltage outputs are fully buffered, and are
capable of driving a 2 kΩ load. Output glitch impulse during
major code transitions is a very low 64 nV-s (typ).
CLR
The clear (
) control allows the user to perform an asyn-
CLR
chronous reset function. Asserting
loads all four DAC
data-word registers, forcing the DAC outputs to either zero
scale (0x000) or midscale (0x800), depending on the state of
CLSEL as shown in Table 6. The clear function is asynchronous
and totally independent of . When
DAC outputs remain latched at the reset value until
strobed, reloading the individual DAC data-word registers
with either the data held in the serial input register prior to the
reset or with new data loaded through the serial interface.
CS
CLR
returns high, the
LD
is
Table 7. DAC Address Word Decode Table
DIGITAL INTERFACE OPERATION
A1
A0
DAC Addressed
CS
The serial input of the DAC8420, consisting of , SDI, and
0
0
DAC A
LD
, is easily interfaced to a wide variety of microprocessor serial
0
ꢀ
DAC B
CS
ports. While
is low, the data presented to the input SDI is
ꢀ
0
DAC C
shifted into the internal serial-to-parallel shift register on the
rising edge of the clock, with the address MSB first, data LSB
last, as shown in Table 6 and in the timing diagram (Figure 2).
The data format, shown in Table 8, is two bits of DAC address
and two don’t care fill bits, followed by the 12-bit DAC data-
word. Once all 16 bits of the serial data-word have been input,
ꢀ
ꢀ
DAC D
PROGRAMMING THE ANALOG OUTPUTS
The unique differential reference structure of the DAC8420
allows the user to tailor the output voltage range precisely to
the needs of the application. Instead of spending DAC resolu-
tion on an unused region near the positive or negative rail, the
DAC8420 allows the user to determine both the upper and
lower limits of the analog output voltage range. Thus, as shown
in Table 9 and Figure 30, the outputs of DAC A through DAC D
range between VREFHI and VREFLO, within the limits specified
in the Specifications section. Note also that VREFHI must be
greater than VREFLO.
LD
the load control
is strobed and the word is parallel-shifted
out onto the internal data bus. The two address bits are decoded
and used to route the 12-bit data-word to the appropriate DAC
data register (see the Applications section).
CORRECT OPERATION OF CS AND CLK
CS
In Table 6, the control pins CLK and
require some attention
during a data load cycle. Since these two inputs are fed to the
same logical OR gate, the operation is in fact identical. The user
must take care to operate them accordingly to avoid clocking in
false data bits. In the timing diagram, CLK must be halted high
V
DD
2.5V MIN
V
VREFHI
0xFFF
CS
or
CLK following the rising edge that latched in the last data bit.
CS
must be brought high during the last high portion of the
1 LSB
2.5V MIN
Otherwise, an additional rising edge is generated by
while CLK is low, causing
rising
to act as the clock and allowing a
CS
false data bit into the serial input register. The same issue must
also be considered in the beginning of the data load sequence.
0x000
–10V MIN
V
VREFLO
0V MIN
V
SS
Figure 30. Output Voltage Range Programming
Table 8.
(FIRST)
(LAST)
B15
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
Aꢀ
A0
NC
NC
Dꢀꢀ
(MSB)
Dꢀ0
D9
Dꢃ
D7
D6
D5
D4
D3
D2
Dꢀ
D0
—Address Word—
—DAC Data-Word—
(LSB)
Rev. B | Page ꢀ4 of 24
DAC8420
Table 9. Analog Output Code
DAC Data-Word (Hex)
0xFFF
VOUT
Note
Full-scale output
Midscale + ꢀ
Midscale
(VREFHI −VREFLO)
4096
(VREFHI −VREFLO)
4096
(VREFHI −VREFLO)
4096
(VREFHI −VREFLO)
4096
VREFLO +
× 4095
× 2049
× 2048
× 2047
×0
0xꢃ0ꢀ
0xꢃ00
0x7FF
0x000
VREFLO +
VREFLO +
VREFLO +
VREFLO +
Midscale − ꢀ
Zero scale
(VREFHI −VREFLO)
4096
Rev. B | Page ꢀ5 of 24
DAC8420
POWER-UP SEQUENCE
VREFHI INPUT REQUIREMENTS
To prevent a CMOS latch-up condition, power up VDD, VSS,
and GND prior to any reference voltages. The ideal power-up
sequence is GND, VSS, VDD, VREFHI, VREFLO, and digital
inputs. Noncompliance with the power-up sequence over an
extended period can elevate the reference currents and eventually
damage the device. On the other hand, if the noncompliant
power-up sequence condition is as short as a few milliseconds,
the device can resume normal operation without being damaged
once VDD/VSS is powered.
The DAC8420 utilizes a unique, patented DAC switch driver
circuit that compensates for different supply, reference voltage,
and digital code inputs. This ensures that all DAC ladder switches
are always biased equally, ensuring excellent linearity under all
conditions. Thus, as shown in Table 1, the VREFHI input of the
DAC8420 requires both sourcing and sinking current capabili-
ties from the reference voltage source. Many positive voltage
references are intended as current sources only and offer little
sinking capability. The user should consider references such as
the AD584, AD586, AD587, AD588, AD780, and REF43 for
such an application.
Rev. B | Page ꢀ6 of 24
DAC8420
APPLICATIONS
performance of the device, the supply should be as noise free as
possible. In the case of 5 V only systems, it is desirable to use
the same 5 V supply for both the analog circuitry and the
digital portion of the circuit. Unfortunately, the typical 5 V
supply is extremely noisy due to the fast edge rates of the
popular CMOS logic families, which induce large inductive
voltage spikes, and busy microcontroller or microprocessor
buses, and therefore commonly have large current spikes during
bus activity. However, by properly filtering the supply as shown
in Figure 32, the digital 5 V supply can be used. The inductors
and capacitors generate a filter that not only rejects noise due
to the digital circuitry, but also filters out the lower frequency
noise of switch mode power supplies. The analog supply should
be connected as close as possible to the origin of the digital
supply to minimize noise pickup from the digital section.
POWER SUPPLY BYPASSING AND GROUNDING
In any circuit where accuracy is important, careful consid-
eration of the power supply and ground return layout helps
to ensure the rated performance. The DAC8420 has a single
ground pin that is internally connected to the digital section
as the logic reference level. The first thought may be to connect
this pin to digital ground; however, in large systems digital
ground is often noisy because of the switching currents of other
digital circuitry. Any noise that is introduced at the ground pin
can couple into the analog output. Thus, to avoid error-causing
digital noise in the sensitive analog circuitry, the ground pin
should be connected to the system analog ground. The ground
path (circuit board trace) should be as wide as possible to reduce
any effects of parasitic inductance and ohmic drops. A ground
plane is recommended if possible. The noise immunity of the
on-board digital circuitry, typically in the hundreds of milli-
volts, is well able to reject the common-mode noise typically
seen between system analog and digital grounds. Finally, the
analog and digital ground should be connected to each other
at a single point in the system to provide a common reference.
This is preferably done at the power supply.
FERRITE BEADS:
2 TURNS, FAIR-RITE
#2677006301
TTL/CMOS
LOGIC
CIRCUITS
+5V
+
+
100µF
ELECT.
0.1µF
CER.
10µF TO 22µF
TANT.
+5V
RETURN
Good grounding practice is also essential to maintaining analog
performance in the surrounding analog support circuitry. With
two reference inputs and four analog outputs capable of moderate
bandwidth and output current, there is a significant potential
for ground loops. Again, a ground plane is recommended as the
most effective solution to minimizing errors due to noise and
ground offsets.
+5V
POWER SUPPLY
Figure 32. Single-Supply Analog Supply Filter
ANALOG OUTPUTS
The DAC8420 features buffered analog voltage outputs capable
of sourcing and sinking up to 5 mA when operating from 15 V
supplies, eliminating the need for external buffer amplifiers in
most applications while maintaining specified accuracy over the
rated operating conditions. The buffered outputs are simply an
op amp connected as a voltage follower, and thus have output
characteristics very similar to the typical operational amplifier.
These amplifiers are short-circuit protected. The user should
verify that the output load meets the capabilities of the device,
in terms of both output current and load capacitance. The
DAC8420 is stable with capacitive loads up to 2 nF typically.
However, any capacitive load will increase the settling time,
and should be minimized if speed is a concern.
1
+V
V
DD
S
10µF
0.1µF
8
9
–V
V
GND
S
SS
10µF
0.1µF
10µF = TANTALUM
0.1µF = CERAMIC
The output stage includes a P-channel MOSFET to pull the
output voltage down to the negative supply. This is very important
in single-supply systems where VREFLO usually has the same
potential as the negative supply. With no load, the zero-scale
output voltage in these applications is less than 500 μV typically,
or less than 1 LSB when VVREFHI = 2.5 V. However, when sinking
current, this voltage does increase because of the finite imped-
ance of the output stage. The effective value of the pull-down
resistor in the output stage is typically 320 ꢁ. With a 100 kΩ
resistor connected to 5 V, the resulting zero-scale output voltage
Figure 31. Recommended Supply Bypassing Scheme
The DAC8420 should have ample supply bypassing, located as
close to the package as possible. Figure 31 shows the recom-
mended capacitor values of 10 μF in parallel with 0.1 μF. The
0.1 μF capacitor should have low effective series resistance (ESR)
and effective series inductance (ESI) (such as any common
ceramic type capacitor), which provide a low impedance path
to ground at high frequencies to handle transient currents due
to internal logic switching. To preserve the specified analog
Rev. B | Page ꢀ7 of 24
DAC8420
is 16 mV. Thus, the best single-supply operation is obtained with
the output load connected to ground, so the output stage does not
have to sink current.
AD588 as shown in Figure 33. Many applications utilize the
DACs to synthesize symmetric bipolar waveforms, which
require an accurate, low drift bipolar reference. The AD588
provides both voltages and needs no external components.
Additionally, the part is trimmed in production for 12-bit
accuracy over the full temperature range without user calibra-
tion. Performing a clear with the reset select CLSEL high allows
the user to easily reset the DAC outputs to midscale, or 0 V in
these applications.
Like all amplifiers, the DAC8420 output buffers do generate
voltage noise, 52 nV/√Hz typically. This is easily reduced by
adding a simple RC low-pass filter on each output.
REFERENCE CONFIGURATION
The two reference inputs of the DAC8420 allow a great deal
of flexibility in circuit design. The user must take care, however,
to observe the minimum voltage input levels on VREFHI and
VREFLO to maintain the accuracy shown in the data sheet.
These input voltages can be set anywhere across a wide range
within the supplies, but must be a minimum of 2.5 V apart in
any case (see Figure 30). A wide output voltage range can be
obtained with 5 V references, which can be provided by the
When driving the reference inputs VREFHI and VREFLO, it is
important to note that VREFHI both sinks and sources current,
and that the input currents of both are code dependent. Many
voltage reference products have a limited current sinking
capability and must be buffered with an amplifier to drive
VREFHI in order to maintain overall system accuracy. The
input VREFLO, however, has no such requirement.
+15V SUPPLY
1µF
VREFHI
+5V
7
6
4
3
0.1µF
5
1
AD588
A3
R
DAC8420
B
+5V
–5V
DAC A
DAC B
DAC C
7
6
3
VOUTA
VOUTB
VOUTC
1
A1
R1
14
15
R4
A4
R2
R5
+15V
SUPPLY
+V
S
2
DIGITAL
CONTROLS
R3
R6
0.1µF
0.1µF
A2
DAC D
4
2
VOUTD
0.1µF
SYSTEM
GROUND
–V 16
S
5
9
10
8
12
11 13
10 11 12 14 15 16
DIGITAL INPUTS
9
8
–15V
SUPPLY
VREFLO
–5V
GND
–15V SUPPLY
Figure 33. 10 V Bipolar Reference Configuration Using the AD588
Rev. B | Page ꢀꢃ of 24
DAC8420
LD
One opto-isolated line ( ) can be eliminated from this circuit
by adding an inexpensive 4-bit TTL counter to generate the
load pulse for the DAC8420 after 16 clock cycles. The counter
is used to count the number of clock cycles loading serial data
to the DAC8420. After all 16 bits have been clocked into the
converter, the counter resets, and a load pulse is generated on
Clock 17. In either circuit, the serial interface of the DAC8420
provides a simple, low cost method of isolating the digital control.
For a single 5 V supply, VVREFHI is limited to at most 2.5 V, and
must always be at least 2.5 V less than the positive supply to
ensure linearity of the device. For these applications, the REF43
is an excellent low drift 2.5 V reference that consumes only
450 μA (max). It works well with the DAC8420 in a single 5 V
system as shown in Figure 34.
+5V SUPPLY
REF43
2
V
IN
+5V SUPPLY
HIGH VOLTAGE
ISOLATION
0.1µF
2.5V
4
6
GND
V
OUT
5V
5V
REG
VREFHI
0.1µF
5
1
POWER
DAC8420
DAC A
7
6
3
VOUTA
VOUTB
VOUTC
5V
10kΩ
+5V
REF43
2
4
V
IN
DAC B
DAC C
6
V
OUT
GND
LD
SCLK
SDI
5V
2.5V
5V
10kΩ
0.1µF
0.1µF
5
1
DIGITAL
CONTROLS
5V
10kΩ
VREFHI
CLR
VDD
15
16
14
12
11
10
DAC D
4
2
VOUTD
7
VOUTA
CLSEL
LD
DAC8420
CS
10 11 12 14 15 16
DIGITAL INPUTS
9
8
6
3
VOUTB
VOUTC
GND
VREFLO
5V
10kΩ
Figure 34. 5 V Single-Supply Operation Using REF43
CLK
SDI
2
VOUTD
ISOLATED DIGITAL INTERFACE
VREFLO VSS GND
Because the DAC8420 is ideal for generating accurate voltages
in process control and industrial applications, due to noise,
from the central controller; it may be necessary to isolate it
from the central controller. This can be easily achieved by using
opto-isolators, which are commonly used to provide electrical
isolation in excess of 3 kV. Figure 35 shows a simple 3-wire
interface scheme for controlling the clock, data, and load pulse.
4
8
9
Figure 35. Opto-lsolated 3-Wire Interface
CS
For normal operation,
is tied permanently low so that the
DAC8420 is always selected. The resistor and capacitor on the
CLR
pin provide a power-on reset with 10 ms time constant.
LD
The three opto-isolators are used for the SDI, CLK, and
lines.
Rev. B | Page ꢀ9 of 24
DAC8420
5V SUPPLY
REF43
VINA
5V
2
4
V
IN
5V SUPPLY
0.1µF
2.5V
0.1µF
6
GND
V
OUT
5V
604Ω
0.1µF
VREFHI
3
5
1
CMP04
VOUTA
VOUTB
VOUTC
DAC8420
5
4
7
6
DAC A
7
6
3
RED LED
5V
C1
C2
C3
2
1
OUT A
DAC B
DAC C
604Ω
9
8
RED LED
DIGITAL
CONTROLS
14
13
OUT B
VOUTD
DAC D
4
2
11
10
C4
12
10 11 12 14 15 16
DIGITAL INPUTS
9
8
GND
VREFLO
VSS
VINB
Figure 36. Dual Programmable Window Comparator
DUAL WINDOW COMPARATOR
PC2
CLSEL
PC1
PC0
CLR
CS
Often a comparator is needed to signal an out-of-range
warning. Combining the DAC8420 with a quad comparator
such as the CMP04 provides a simple dual window comparator
with adjustable trip points as shown in Figure 36. This circuit
can be operated with either a dual supply or a single supply. For
the A input channel, DAC B sets the low trip point, and DAC A
sets the upper trip point. The CMP04 has open-collector outputs
that are connected together in a wire-OR’ed configuration to
generate an out-of-range signal. For example, when VINA
goes below the trip point set by DAC B, Comparator C2 pulls
the output down, turning on the red LED. The output can also
be used as a logic signal for further processing.
MC68HC11*
DAC8420*
(PD5) SS
SCK
LD
CLK
SDI
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. MC68HC11 Microcontroller Interface
For correct operation, the MC68HC11 should be configured
such that its CPOL bit and CPHA bit are both set to 1. In this
configuration, serial data on MOSI of the MC68HC11 is valid
on the rising edge of the clock, which is the required timing for
the DAC8420. Data is transmitted in 8-bit bytes (MSB first),
with only eight rising clock edges occurring in the transmit
cycle. To load data to the input register of the DAC8420, PC0
is taken low and held low during the entire loading cycle. The
first eight bits are shifted in address first, immediately followed
by another eight bits in the second least-significant byte to load
the complete 16-bit word. At the end of the second byte load,
PC0 is then taken high. To prevent an additional advancing of
the internal shift register, SCK must already be asserted before
PC0 is taken high. To transfer the contents of the input shift
register to the DAC register, PD5 is then taken low, asserting the
MC68HC11 MICROCONTROLLER INTERFACING
Figure 37 shows a serial interface between the DAC8420 and
the MC68HC11 8-bit microcontroller. The SCK output of the
port outputs the serial data to load into the SDI input of the
DAC. The port lines (PD5, PC0, PC1, and PC2) provide the
controls to the DAC as shown.
LD
input of the DAC and completing the loading process. PD5
CLR
should return high before the next load cycle begins. The
input of the DAC8420 (controlled by the output PC1) provides
an asynchronous clear function.
Rev. B | Page 20 of 24
DAC8420
DAC8420 TO M68HC11 INTERFACE ASSEMBLY PROGRAM
* M68HC11 Register Definitions
PORTC EQU $1003 Port C control register
* Initialize SPI Interface
LDAA #$5F
STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
* Call update subroutine
BSR UPDATE Xfer 2 8-bit words to DAC-8420
JMP $E000 Restart BUFFALO
* Subroutine UPDATE
UPDATE PSHX Save registers X, Y, and A
PSHY
PSHA
* “0,0,0,0;0,CLSEL,CLR,CS”
DDRC EQU $1007 Port C data direction
PORTD EQU $1008 Port D data register
* “0,0,LD,SCLK;SDI,0,0,0”
DDRD EQU $1009 Port D data direction
SPCR EQU $1028 SPI control register
* “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
* “SPIF,WCOL,0,MODF;0,0,0,0”
* Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)
LDAA #$80 1,0,0,0;0,0,0,0
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
STAA SDI1 SDI1 is set to 80 (Hex)
* Enter Contents of SDI2 Data Register
LDAA #$00 0,0,0,0;0,0,0,0
STAA SDI2 SDI2 is set to 00 (Hex)
LDX #SDI1 Stack pointer at 1st byte to send via SDI
LDY #$1000 Stack pointer at on-chip registers
* Clear DAC output to zero
BCLR PORTC,Y $02 Assert CLR
BSET PORTC,Y $02 Deassert CLR
* Get DAC ready for data input
BCLR PORTC,Y $01 Assert CS
TFRLP LDAA 0,X Get a byte to transfer via SPI
STAA SPDR Write SDI data reg to start xfer
WAIT LDAA SPSR Loop to wait for SPIF
BPL WAIT SPIF is the MSB of SPSR
*
* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex)
* To select: DAC A – Set SDI1 to $0X
DAC B – Set SDI1 to $4X
DAC C – Set SDI1 to $8X
DAC D – Set SDI1 to $CX
SDI2 is encoded from 00 (Hex) to FF (Hex)
* DAC requires two 8-bit loads – Address + 12 bits
SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8”
SDI2 EQU $01 SDI packed byte 2
“DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
* Main Program
ORG $C000 Start of user’s RAM in EVB
INIT LDS #$CFFF Top of C page RAM
* Initialize Port C Outputs
*
(when SPIF is set, SPSR is negated)
LDAA #$07 0,0,0,0;0,1,1,1
INX
Increment counter to next byte for xfer
* CLSEL-Hi, CLR-Hi, CS-Hi
CPX #SDI2+ 1 Are we done yet ?
BNE TFRLP If not, xfer the second byte
* To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03)
* To reset DAC to MID-SCALE, set CLSEL-Hi ($07)
STAA PORTC Initialize Port C Outputs
LDAA #$07 0,0,0,0;0,1,1,1
STAA DDRC CLSEL, CLR, and CS are now enabled as outputs
* Initialize Port D Outputs
* Update DAC output with contents of DAC register
BCLR PORTD,Y 520 Assert LD
BSET PORTD,Y $20 Latch DAC register
BSET PORTC,Y $01 De-assert CS
PULA When done, restore registers X, Y & A
PULY
LDAA #$30 0,0,1,1;0,0,0,0
* LD-Hi,SCLK-Hi,SDI-Lo
PULX
STAA PORTD Initialize Port D Outputs
LDAA #$38 0,0,1,1;1,0,0,0
RTS
** Return to Main Program **
STAA DDRD LD,SCLK, and SDI are now enabled as outputs
Rev. B | Page 2ꢀ of 24
DAC8420
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 38. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.
0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Rev. B | Page 22 of 24
DAC8420
0.098 (2.49) MAX
9
0.005 (0.13) MIN
16
0.310 (7.87)
0.220 (5.59)
1
8
PIN 1
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 40. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
DACꢃ420EP
DACꢃ420EPZ2
Temperature Range
Package Description
Package Option
N-ꢀ6
N-ꢀ6
RW-ꢀ6
RW-ꢀ6
RW-ꢀ6
RW-ꢀ6
N-ꢀ6
N-ꢀ6
Q-ꢀ6
RW-ꢀ6
RW-ꢀ6
RW-ꢀ6
RW-ꢀ6
INL1 ( LSB)
0.5
0.5
0.5
0.5
0.5
0.5
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
−40°C to +ꢃ5°C
ꢀ6-Lead Plastic Dual In-Line Package [PDIP]
ꢀ6-Lead Plastic Dual In-Line Package [PDIP]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
ꢀ6-Lead Plastic Dual In-Line Package [PDIP]
ꢀ6-Lead Plastic Dual In-Line Package [PDIP]
ꢀ6-Lead Ceramic Dual In-Line Package [CERDIP]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
ꢀ6-Lead Standard Small Outline Package [SOIC_W]
DACꢃ420ES
DACꢃ420ES-REEL
DACꢃ420ESZ2
DACꢃ420ESZ-REEL2
DACꢃ420FP
DACꢃ420FPZ2
DACꢃ420FQ
DACꢃ420FS
DACꢃ420FS-REEL
DACꢃ420FSZ2
DACꢃ420FSZ-REEL2
ꢀ INL measured at VDD = +ꢀ5 V and VSS = −ꢀ5 V.
2 Z = RoHS Compliant Part.
Rev. B | Page 23 of 24
DAC8420
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00275-0-5/07(B)
Rev. B | Page 24 of 24
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