EVAL-AD1959EB [ADI]
PLL/Multibit DAC; PLL /多位DAC
| 型号： | EVAL-AD1959EB |
| 厂家： | 
ADI |
| 描述： | PLL/Multibit DAC |
| 文件： | 总8页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
PLL/Multibit ꢀ-ꢁ DAC
AD1959
FEATURES
5 V Stereo Audio DAC System
APPLICATIONS
DVD, CD, Home Theater Systems, Automotive Audio
Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
Accepts 16-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with Data Directed
Scrambling
Single-Ended Output for Easy Application
–94 dB THD + N
108 dB SNR and Dynamic Range
PRODUCT OVERVIEW
The AD1959 is a complete high-performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry with an on-board dual PLL clock generator.
Other features include an on-chip stereo attenuator and mute,
programmed through an SPI-compatible serial control port.
The AD1959 is fully compatible with all known DVD formats
including 96 kHz and 192 kHz sample frequencies and 24 bits.
It also is backwards-compatible by supporting 50 µs/15 µs
digital de-emphasis for “redbook” compact discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rates.
75 dB Stopband Attenuation
Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis and
Output Phase
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Input/Oscillator
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 384/256 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)
SCLK2: 512 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)/22.5792 MHz
Better than 100 ps RMS Clock Jitter
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
The AD1959 has a simple but flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1959 can be configured in left-justified, I2S, right-justified,
or DSP serial-port-compatible modes. It can support 16, 20,
and 24 bits in all modes. The AD1959 accepts serial audio data
in MSB first, two’s-complement format, and operates from a
single 5 V power supply. It is fabricated on a single monolithic
integrated circuit and housed in a 28-lead SSOP package for
operation over the temperature range –40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
LOOP
CLOCK
CONTROL DATA
INPUT
FILTERS OUTPUTS
XIN XOUT MCLK
2
3
3
AD1959
PLL
CIRCUIT
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
OSC
MULTIBIT
SIGMA-DELTA
MODULATOR
8 ꢂ F
INTERPOLATOR
OUTPUT
BUFFER
S
ATTEN/MUTE
DAC
L
SERIAL
DATA
INTERFACE
16-/20-/24-
BIT DIGITAL
DATA INPUT
ANALOG
OUTPUTS
3
MULTIBIT
SIGMA-DELTA
MODULATOR
8 ꢂ F
INTERPOLATOR
OUTPUT
BUFFER
S
ATTEN/MUTE
DAC
R
2
2
3
ANALOG SUPPLY
RESET
MUTE
ZERO FLAG
PLL SUPPLY
DIGITAL SUPPLY
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD1959–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature
Input Clock
Input Signal
25°C
12.288 MHz
996.11 Hz
–0.5 dB Full Scale
48 kHz
Input Sample Rate
Measurement Bandwidth
Word Width
20 Hz to 20 kHz
20 Bits
Load Capacitance
Load Impedance
Input Voltage HI
Input Voltage LO
100 pF
47 kΩ
3.5 V
0.8 V
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
24
Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
105
108
dB
dB
With A-Weighted Filter (Stereo)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Total Harmonic Distortion + Noise (Stereo)
PLL Performance
Master Clock Input Frequency
Generated System Clocks
SCLK0
SCLK1
SCLK2
Jitter (SCLK0 and SCLK1)
Analog Outputs
105
108
–94
dB
dB
dB
101
–91
125
27
MHz
33.8688
12.288
22.5792
85
MHz
MHz
MHz
ps rms
Single-Ended Output Range ( Full Scale)
Output Capacitance at Each Output Pin
VREF (FILTR)
3.17
V p-p
pF
V
2
2.44
+5
2.34
–5
2.39
2.0
Gain Error
%
Interchannel Gain Mismatch
Gain Drift
DC Offset
Out-of-Band Energy (0.5 × fS to 100 kHz)
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
De-Emphasis Gain Error
–0.15
0.015
150
–5
+0.15
250
+15
–90
dB
ppm/°C
mV
dB
dB
Degrees
–25
–120
0.1
0.1
dB
NOTES
Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (–40°C to +105°C )
Min
Typ
Max
Unit
Input Voltage HI (VIH) Except XIN
Input Voltage HI (VIH) XIN
2.2
2.7
V
V
Input Voltage LO (VIL)
0.8
10
10
V
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 1 mA Except XOUT
Low Level Output Voltage (VOL) IOL = 1 mA XOUT
Input Capacitance
µA
µA
V
V
V
2.0
0.4
1.2
20
pF
Specifications subject to change without notice.
–2–
REV. 0
AD1959
TEMPERATURE RANGE
Min
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
–40
–55
+105*
+150
NOTES
*105°C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85°C for 2-layer board, 2 oz. layers.
Specifications subject to change without notice.
POWER
Min
Typ
Max
Unit
Supplies
Voltage, Analog Digital PLL
Analog Current
Digital Current
PLL Current
4.50
5
5.50
42
34
V
36
28
27
mA
mA
mA
32
Dissipation
Operation – All Supplies
Operation – Analog Supply
Operation – Digital Supply
Operation – PLL Supply
455
180
140
135
540
mW
mW
mW
mW
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz)
Pass Band (kHz)
Stop Band (kHz)
Stopband Attenuation (dB)
Pass-Band Ripple (dB)
44.1
48
96
DC–20
24.1–328.7
26.23–358.28
56.9–327.65
117–327.65
75
75
75
60
0.0002
0.0002
0.0005
0/–0.04 (DC–21.8 kHz)
0/–0.5 (DC–65.4 kHz)
0/–1.5 (DC–87.2 kHz)
DC–21.8
DC–39.95
DC–87.2
192
Specifications subject to change without notice.
GROUP DELAY
Chip Mode
Group Delay Calculation
fS
Group Delay
Unit
INT8× Mode
INT4× Mode
INT2× Mode
24.625/fS
15.75/fS
14/fS
48 kHz
96 kHz
192 kHz
513
164
72.91
µs
µs
µs
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over –40°C to +105°C, AVDD = DVDD = 5.0 V 10%)
Min
Unit
tDMP
tDML
tDMH
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
tDDH
tRSTL
MCLK Period (FMCLK = 256 × FLRCLK)
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK HI Pulsewidth
BCLK LO Pulsewidth
BCLK Period
LRCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
SDATA Setup
SDATA Hold
RST LO Pulsewidth
54
15
10
7
12
60
20
20
15
10
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Specifications subject to change without notice.
–3–
REV. 0
AD1959
ABSOLUTE MAXIMUM RATINGS*
PACKAGE CHARACTERISTICS
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs . . . . . . . . . . DGND – 0.3 V to DVDD + 0.3 V
Analog Inputs . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to + 0.3 V
Reference Voltage . . . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
θ
θ
θ
JA (Thermal Resistance) Junction-to-Ambient
109.0°C/W Typ (2-Layer Board)
JA (Thermal Resistance) Junction-to-Ambient
78.58°C/W Typ (4-Layer Board—2 Signal, 2 Planes)
JA (Thermal Resistance) Junction-to-Case
39.0°C/W Typ
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1959 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature
Package Description
Package Option
AD1959YRS
AD1959YRSRL
EVAL-AD1959EB
–40°C to +105 °C
–40°C to +105 °C
28-Lead Small Outline Package
28-Lead Small Outline Package
Evaluation Board
RS-28
RS-28 on 13" Reels
PIN CONFIGURATION
CCLK
1
2
28
27
26
25
24
23
22
21
20
19
18
17
CDATA
MUTE
ZERO
FILTB
AVDD
OUTL
AGND1
FLTR
OUTR
AGND0
LF1
CLATCH
RESET
LRCLK
BCLK
3
4
5
6
SDATA
DVDD
DGND
SCLK0
MCLK
XOUT
AD1959
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
13
14
XIN
LF0
SCLK1
SCLK2
16 PGND
15
PVDD
–4–
REV. 0
AD1959
PIN FUNCTION DESCRIPTIONS
Description
Pin
Input/Output
Mnemonic
1
I
CCLK
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
2
3
I
I
CLATCH
RESET
Latch Input for Control Data.
Reset. The AD1959 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
4
5
I
I
LRCLK
BCLK
Left/Right Clock Input for Input Data. Must run continuously.
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
6
I
SDATA
Serial input, MSB first, containing two channels of 16/20/24 bits of two’s-
complement data per channel.
7
8
9
I
I
DVDD
DGND
SCLK0
MCLK
XOUT
XIN
SCLK1
SCLK2
PVDD
PGND
LF0
Digital Power Supply Connect to Digital 5 V Supply.
Digital Ground.
33.8688 MHz Clock Output.
27 MHz Master Clock Output/256 fS DAC Clock Input.
27 MHz Crystal Oscillator Output.
27 MHz Crystal Oscillator/External Clock Input.
256/384 fS Output.
512 fS/22.5792 MHz Output.
PLL Power Supply. Connect to PLL 5 V Supply.
PLL Ground.
PLL0 Loop Filter.
PLL1 Loop Filter.
O
I/O
O
I
O
O
10
11
12
13
14
15
16
17
18
19
20
21
LF1
AGND0
OUTR
FILTR
Analog Ground.
Right Channel Positive Line Level Analog Output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
O
O
voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.
22
23
24
25
26
I
O
AGND1
OUTL
AVDD
FILTB
ZERO
Analog Ground.
Left Channel Line Level Analog Output.
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection, Connect 10 µF Capacitor to AGND.
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
Serial control input, MSB first, containing 16 bits of unsigned data
per channel.
O
I
27
28
MUTE
I
CDATA
REV. 0
–5–
AD1959
27 MHz clock is buffered out to the MCLK pin. When set to
Input, the MCLK is the 256 fS master clock input for the DAC.
SCLK0 produces a 33.8688 MHz output, SCLK1 is intended
to be used as a master audio clock and will be a multiple of the
sample rate set in the PLL control register. It can be set to
256 fS or 384 fS using Bit 5 and to 512 fS or 768 fS, with Bit 4.
SCLK2 can be set to a constant 22.5792 MHz (512 × 44.1 kHz)
or 512 fS by Bit 3 of the PLL Control Register. Please note that
SCLK2 is intended to operate a DSP and does not meet the
jitter specifications stated under Analog Performance. All the
generated clocks can be set to 1/2 their nominal rate by setting
REF_Div2, Bit 8 in the PLL Control Register.
FUNCTIONAL DESCRIPTION
DAC
The AD1959 has two DAC channels arranged as a stereo pair
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 16384
linear steps. Digital inputs are supplied through a serial data input
pin, SDATA, a frame clock, LRCLK and a bit clock, BLCK.
Each analog output pin sits at a dc level of VREF, and swings
1.585 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high-frequency noise present on the output pins. The output
phase can be changed in an SPI control register to accommo-
date inverting and noninverting filters. Note that the use of op
amps with low slew rate or low bandwidth may cause high fre-
quency noise and tones to fold down into the audio band; care
should be exercised in selecting these components.
Reset
RESET will set the control registers to their default settings. The
chip should be reset on power-up. After reset is deasserted, the
part will come out of reset on the next rising LRCLK.
Serial Control Port
The FILTD and FILTR pins should be bypassed by external
capacitors to ground. The FILTD pin is used to reduce the noise
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin, FILTR (~2.39 V) can
be used to bias external op amps used to filter the output signals.
The AD1959 has an SPI-compatible control port to permit
programming the internal control registers for the PLL and DAC.
The DAC output levels may be independently programmed
by means of an internal digital attenuator adjustable in 16384
linear steps.
The DAC master clock frequency is 256 fS for the 32 kHz–48 kHz
range. For the 96 kHz range this is 128 fS. It is supplied inter-
nally from the PLL clock system when MCLK mode is set to
Output in the PLL Control Register. When the MCLK mode is
changed to Input, it must be supplied from an external source
connected to MCLK. The output from the 27 MHz PLL clock
is disabled in this case.
The SPI control port is a 3-wire serial control port. The format
is similar to the Motorola SPI format except the input data word
is 16 bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the PLL system or the
DAC. Figure 1 shows the format of the SPI signal. Note that the
CCLK can be gated or continuous, CLATCH should be low
during the 16 active clocks.
PLL Clock System
The PLL clock system operates from a 27 MHz master clock
supplied by the on-board crystal oscillator or an external source
connected to XIN. With the MCLK mode set to Output, the
CLATCH
CCLK
CDATA
D0
D15
D14
Figure 1. Format of SPI Signal
–6–
REV. 0
AD1959
POWER SUPPLY AND VOLTAGE REFERENCE
parallel combination of 10 µF and 100 nF The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog output signal pins. The current drawn
from the VREF pin should be limited to less than 50 µA.
The AD1959 is designed for five-volt supplies. Separate power
supply pins are provided for the analog, digital, and PLL sec-
tions. These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise. A
bulk aluminum electrolytic capacitor of at least 22 µF should
also be provided on the same PC board. For best performance it
is recommended that the analog supply be separate from the
digital and PLL supply. It is recommended that all supplies be
isolated by ferrite beads in series with each supply. It is expected
that the digital and PLL sections will be run from a common
supply but isolated from one another. It is important that the
analog supply be as clean as possible.
SERIAL DATA PORTS – DATA FORMAT
The DAC serial data input mode defaults to I2S. By changing
Bits 4 and 5 in the DAC control register, the mode can be
changed to RJ, DSP, or LJ. The word width defaults to 24 bits
but can be changed by programming Bits 8 and 9 in the DAC
Control Register.
Figure 2 shows the serial mode formats.
The internal voltage reference is brought out on Pin 21 (FILTR)
and should be bypassed as close as possible to the chip with a
LRCLK
BCLK
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB
LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
MSB
LSB
LRCLK
BCLK
RIGHT CHANNEL
MSB
LSB
MSB
LSB
SDATA
2
1 S MODE – 16 TO 24 BITS PER CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE – 16 TO 24 BITS PER CHANNEL
1/f
S
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT f EXCEPT FOR DSP MODE WHICH IS 2 ꢂ f
.
S
S
3. BCLK FREQUENCY IS NORMALLY 64 ꢂ LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 2. Stereo Serial Modes
REV. 0
–7–
AD1959
Table I. DAC Control Register
Bit 11:10
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
Bit 1:0
Interpolation
Factor
Serial Data
Width
Serial Data
Format
De-Emphasis
Filter
SPI Register
Address
Output Phase
Soft Mute
00 = 8×*
00 = 24 Bits*
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
0 = Noninverted*
1 = Inverted
0 = No Mute*
1 = Muted
00 = I2S*
00 = Right Justified
10 = DSP
11 = Left Justified
00 = None*
01 = 44.1 kHz
10 =32 kHz
01
01 = 4×
10 = 2×
11 = Not Allowed
11 = 48 kHz
*Default Setting.
Table II. DAC Volume Registers
Bit 1:0
B
it 15:2
Volume
SPI Register Address
14 Bits, Unsigned
14 Bits, Unsigned
00 = Left Volume
10 = Right Volume
Default is full volume.
Table III. PLL Control Register
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1:0
PLL2
Power-
Down
PLL1
Power-
Down
XTAL
Power-
Down
REF_Div2
Power-
Down
SPI
Register
Address
SCLK1
Select
SCLK2
Select
MCLK
Mode
fS
Double
0 = On*
0 = On*
0 = On*
0 = No Div* 00 = 48 kHz* 0 =256*
1 =384
0 = fS*
0 = 512 × 4.1 kHz* 0 = Output* 11
1 = Power- 1 = Power- 1 = Power- 1 = Div by 2 01 = Not
Down
1 = 2 × fS 1 = 512 × fS 1 = Input
Down
Down
Allowed
10 = 32 kHz
11 = 44.1 kHz
*
Default Setting.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Small Outline Package (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
0.212 (5.38)
0.205 (5.21)
0.311 (7.9)
0.301 (7.64)
PIN 1
14
1
0.078 (1.98)
0.068 (1.73)
0.07 (1.79)
0.066 (1.67)
8ꢃ
0ꢃ
0.03 (0.762)
0.022 (0.558)
0.0256 0.015 (0.38)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
(0.65)
0.010 (0.25)
BSC
–8–
REV. 0
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