EVAL-AD5520EB [ADI]
Per Pin Parametric Measurement Unit/Source Measure Unit; 每个引脚参数测量单元/源测量单元
| 型号： | EVAL-AD5520EB |
| 厂家： | 
ADI |
| 描述： | Per Pin Parametric Measurement Unit/Source Measure Unit |
| 文件： | 总20页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Per Pin Parametric
Measurement Unit/Source Measure Unit
AD5520
FEATURES
GENERAL DESCRIPTION
Force/Measure Functions
The AD5520 is a single channel per pin parametric measure-
Force Voltage/Current, Measure Current/Voltage
Force Current/Voltage, Measure Current/Voltage
Force/Measure Voltage Range ꢀ11 V
4 Programmable Force/Measure Current Ranges
ꢀ4 ꢁA, ꢀ40 ꢁA, ꢀ400 ꢁA, ꢀ4 mA
ment unit (PPMU) for use in semiconductor automatic test
equipment. The part is also suited for use as a source
measurement unit for instrumentation applications. It
contains programmable modes to force a pin voltage and
measure the corresponding current or force a current and
measure the voltage. The AD5520 can force/measure over a
±11 V range or currents up to ±4 mA with its on-board
force amplifier. An external amplifier is required for wider
current ranges. The device provides a force sense capability to
ensure accuracy at the tester pin. A guard output is also
available to drive the shield of a force/sense pair. The AD5520
is available in a 64-lead LQFP package.
Extended Current Ranges
ꢀ40 mA and ꢀ160 mA with External Driver
Clamp Circuitry and Window Comparators On Board
Guard Amplifier
64-Lead LQFP Package
APPLICATIONS
Automatic Test Equipment
Per Pin PMU, Shared Pin PMU, Device Power Supply
Instrumentation
Source Measure, Parametric Measurement, Precision
Measurement
FUNCTIONAL BLOCK DIAGRAM
AV
AV
CC
EE
AD5520
FOH
BW SELECT
FOH3
FOH2
FOH1
FOH0
FIN
MEASI5H
CLAMP
MEASI4H
MEASI3H
MEASI2H
MEASI1H
DETECT
CLH
CLL
MEASI0H
REFGND
G = 16
MEASIOUT
MEASIL
I
SENSE
INST AMP
GUARDIN
GUARD
V
MEASOUT
G = 1
SENSE
INST AMP
MEASVH
MEASVL
G = 1
MEASVOUT
COMPARATOR
CPH
CPOH
AGND
QM5
LOGICS
CPOH
CPL
QM4
CPCK
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(AVCC = +15 V ꢀ 5%, AVEE = –15 V ꢀ 5%, DVDD = 5 V ꢀ 10%, AGND = 0 V, REFGND = 0 V,
AD5520–SPECIFICATIONS DGND = 0 V. All specifications 0ꢁC to 70ꢁC, unless otherwise noted.)
Parameter
Min
Typ1 Max
Unit
Test Conditions/Comments
VOLTAGE FORCE MODE
Force Control Output Voltage Range
FOH Output Impedance
FOH0
Ϯ11
V
Ω
kΩ
kΩ
Ω
Ω
mV
%
RLOAD = 10 kΩ, CLOAD = 50 pF
70
2.5
3
500
60
FOH1
FOH2
FOH3
Input Offset Error
Gain Error
Ϯ1
Ϯ5
1
Ϯ1
Clamp Voltage Error2
% FS
of FIN
CURRENT MEASURE/FORCE
Set with external sense resistors
MODE0, RS = 125 kΩ
MODE1, RS = 12.5 kΩ
MODE2, RS = 12.5 kΩ
MODE3, RS = 125 Ω
FOH0
FOH1
FOH2
FOH3
4
40
400
4
µA
µA
µA
mA
CURRENT MEASURE MODE
High Sense Input Range, VMEASIxH
Linearity3
Ϯ11
Ϯ0.01
Ϯ3
V
% FSR
nA
+11 V > VFOL > –11 V
Input Bias Current
Ϯ1
50
Input Bias Current Drift1
Output Offset Error
pA/°C
mV
mV
mV
mV
%
µV/°C
mA
dB
Ϯ100
Ϯ100
Ϯ100
Ϯ100
MODE0
MODE1
MODE2
MODE3
Gain of 16
Gain Error
Ϯ0.1 Ϯ0.35
Gain Error Temperature Coefficient4
MEASIOUT Output Load Current
CMRR
30
Ϯ4
95
@ DC
CURRENT FORCE MODE
Input Offset Error
Ϯ10
1
Ϯ1
mV
%
% FS
With MODE0, MODE1, MODE2, MODE3
of FIN
Gain Error
Clamp Current Error2
VOLTAGE MEASURE MODE
Differential Input Range
Low Sense Input Voltage Range
Linearity3
Ϯ11
Ϯ100
V
mV
% FSR
mV
MEASVL
+11 V > VMEASVH to VMEASVL > –11 V
FIN = 0 V, Measured @ MEASVOUT
+0.005
Ϯ10
Input Offset Error
Ϯ5
Input Offset Error Temperature
Coefficient1
Ϯ15
Ϯ0.03 Ϯ0.15
2
Ϯ1
50
Ϯ4
73
mV/°C
%
mV/°C
nA
pA/°C
mA
dB
Gain Error
Gain of 1
@ DC
Gain Error Temperature Coefficient4
Input Bias Current
Ϯ3
Input Bias Current Drift4
MEASVOUT Output Load Current
CMRR4
AMPLIFIER SETTLING TIME4, 5
VSENSE Amp
ISENSE Amp
20
12
µs
µs
To 0.2%
To 0.2%
LOOP SETTLING4, 5
COMPIN2 = 100 pF
Settling to within 0.024% of 8 V step
MODE0
MODE1
MODE2, MODE3
MODE0
MODE1, MODE2, MODE3
MODE0, MODE1, MODE2, MODE3
450
285
170
2
1.8
5.75
600
390
240
2.5
2.4
8.7
µs
µs
µs
COMPIN1 = 1000 pF
COMPIN0 = 3000 pF
ms
ms
ms
–2–
REV. A
AD5520
Parameter
Min
Typ1 Max
Unit
Test Conditions/Comments
SLEW RATE4, 5
50
4.3
1.28
mV/µs
mV/µs
mV/µs
COMPIN2 = 100 pF
COMPIN1 = 1000 pF
COMPIN0 = 3000 pF
COMPARATOR
CPH, CPL Input Range
Input Offset
Ϯ11
Ϯ11
V
mV
VCPH > VCPL
Ϯ7
GUARD DRIVER
Output Voltage
V
Output Impedance
Output Offset Voltage
Load Current4
130
400
Ϯ4
Ω
Capacitive Load Only
mV
mA
µs
Output Settling Time4
0.5
2
100 pF Capacitive Load
ANALOG REFERENCE INPUTS
Force Control Input Range
Force Control Input Impedance
Clamp Control Input Range
Clamp Control Input Impedance
Comparator Threshold Input Range
Comparator Threshold Input Impedance
Input Capacitance4
Ϯ11
Ϯ11
Ϯ11
V
MΩ
V
MΩ
V
MΩ
pF
1
1
VCLH > VCLL
1
3
ANALOG MEASUREMENT OUTPUTS
Voltage Measure Output Impedance
Current Measure Output Impedance
Multiplexed Sense Output Impedance
Input Capacitance
2
3
1
Ω
Ω
kΩ
MEASIxH, MEASVH, FOHx
8
pF
LOGIC INPUTS
Input Current
Ϯ1
0.8
µA
V
V
All digital inputs together
Input Low Voltage, VINL
Input High Voltage, VIHL
Input Capacitance4
2.0
2.4
3
pF
LOGIC OUTPUTS
Output Low Voltage, VOL
Output High Voltage, VOH
4
0.4
V
V
ISINK = 2 mA
ISOURCE = 2 mA
4
POWER REQUIREMENTS
AVCC
+14.25 +15 +15.75
–14.25 –15 +15.75
V
V
For specific performance6
AVEE
Power Supply Rejection Ratio, PSRR1
FOH
–25
–16
–15
–55
–10
90
dB
dB
dB
dB
dB
dB
V
mA
mA
mA
100 kHz
500 kHz
1 MHz
100 kHz
500 kHz
MEASOUT
DC PSR
DVDD
IAVCC
IAVEE
IDVDD
5
12
12
0.5
Digital inputs at supply rails
NOTES
1Typical values are at 25°C and nominal supply, unless otherwise noted.
2Full-scale = 11 V.
3Full-scale range = 22 V.
4Guaranteed by design and characterization but not subject to production test.
5Force control amplifier dominates slew rate and settling time.
6Operational with 12 V supplies, force/measure range is reduced to 8.5 V.
Specifications subject to change without notice.
REV. A
–3–
AD5520
(AVCC = +15 V ꢀ 5%, AVEE = –15 V ꢀ 5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All
specifications 0ꢁC to 70ꢁC, unless otherwise noted.)
TIMING CHARACTERISTICS1, 2
DVDD
Parameter
5 V ꢀ 10%
3.3 V
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
0
30
40
0
550
320
450
150
100
240
150
100
320
0
200
70
40
560
320
500
800
440
240
500
440
320
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns min
CS Falling Edge to STB Falling Edge Setup Time
STB Pulse Width
STB Rising Edge to CS Rising Edge Setup Time
Data Setup Time
CS Falling Edge to CPCK Rising Edge Setup Time
CPCK Pulse Width
CPCK to STB Falling Edge Setup Time
STB Rising Edge to QMx, CLxDETECT Valid
STB Rising Edge to CPOH, CPOL Valid
Comparator Setup Time, MODE2, MODE3 settling
Comparator Hold Time
Comparator Output Delay Time
Comparator Strobe Pulse Width
t9
t10
t11
t12
t13
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
CS
t3
t1
t2
STB
t4
AMx, ACx, FSEL,
MSEL, CPSEL
t5
t6
t7
CPCK
t8
t9
QM4, QM5,
CLHDETECT,
CLLDETECT
CPOL, CPOH
Figure 1. Timing Diagram
t11
MEASVOUT
OR MEASIOUT
CPCK
CPOH, CPOL
t10
t13
t12
Figure 2. Comparator Timing
–4–
REV. A
AD5520
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature, (TJ max) . . . . . . . . . 150°C
AVCC to AVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 V
AVCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
AVEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Analog Inputs to AGND . . . . . AVCC + 0.3 V to AVEE – 0.3 V
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 47.8°C/W
JA
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
C
LH to CLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V
CPH to CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V
REFGND, DGND . . . . . . . . . AVCC + 0.3 V to AVEE – 0.3 V
ORDERING GUIDE
Temperature Range Package Description
0°C to 70°C
Model
Package Option
AD5520JST
AD5520JST-REEL 0°C to 70°C
EVAL-AD5520EB
64-Lead LQFP
64-Lead LQFP
ST-64-2
ST-64-2
Evaluation Board and Software
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5520 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. A
–5–
AD5520
PIN CONFIGURATION
64-Lead LQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
AV
EE_B
1
2
3
4
5
6
CPH
CPL
47
46
MEASI5H
MEASI4H
FOH3
DV
DD
45
44
43
42
41
40
39
38
37
36
35
34
33
CPOH
MEASI3H
FOH2
CPOL
CPCK
MEASI2H
FOH1
7
8
9
DGND
AD5520
CLHDETECT
CLLDETECT
(Not to Scale)
MEASI1H
FOH0
10
11
12
13
QM4
QM5
MEASI0H
MEASIL
MOE
CS
MEASVH
GUARD(NC)
14
15
STB
AC0
AC1
MEASVL
AV
16
CC_G
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
CPH
CPL
Description
1
2
Upper Comparator Threshold Voltage Input, CPH > CPL.
Lower Comparator Threshold Voltage Input, CPL < CPH.
Digital Supply Voltage.
3, 18
DVDD
4
5
6
CPOH
CPOL
CPCK
DGND
CLHDETECT
CLLDETECT
QM4
Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH.
Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL.
Logic Input. Used to initiate comparator sampling and update CPOH and CPOL.
Digital Ground.
Logic Output. When high, indicates upper clamp active. For details, see the Clamp Function section.
Logic Output. When high, indicates lower clamp active. For details, see the Clamp Function section.
7, 17
8
9
10
Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external
relay or switch. For details, see the High Current Ranges section.
11
QM5
Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external
relay or switch. For details, see the High Current Ranges section.
12
13
MOE
CS
Active Low MEASOUT Enable.
Active Low Logic Input. The device is selected when this pin is low. For details, see the Interface
section.
14
15
16
STB
AC0
AC1
Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for differ-
ent configurations. Rising edge of STB triggers sequence inputs. For details, see the Interface section.
Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors.
For details, see the Force Control Amplifier section.
Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors.
For details, see the Force Control Amplifier section.
–6–
REV. A
AD5520
PIN FUNCTION DESCRIPTIONS (continued)
Description
Pin No.
Mnemonic
19
AM2
Logic Input. Used in conjunction with AM1 and AM0 to select one of six current ranges or to enable
standby mode. For details, see the Current Ranges section.
20
21
22
23
24
25
AM1
Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable
standby mode. For details, see the Current Ranges section.
Logic Input. Used in conjunction with AM2 and AM1 to select one of six current ranges or to enable
standby mode. For details, see the Current Ranges section.
Logic Input. When high, device is in standby mode of operation. For details, see the Standby
Mode section.
Logic Input. Force mode select. Used to select between current or voltage force operation. For details,
see the Force Voltage or Force Current section.
Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or
MEASVOUT when low.
Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to
MEASIOUT when high. For details, see the Comparator Function and Strobing section.
AM0
STANDBY
FSEL
MSEL
CPSEL
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57, 59
58
60
61
62
63
64
AVEE
AVCC
AGND
AVEE_G
Most Negative Supply Voltage.
Most Positive Supply Voltage.
MEASx Input Ground.
Most Negative Supply Voltage.
Guard Output.
No Connect.
Guard Input.
Most Positive Supply Voltage.
DUT Voltage Sense Inputs (Low Sense).
No Connect.
DUT Voltage Sense Inputs (High Sense).
DUT Current Sense Inputs (Low Sense).
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
DUT Current Sense Inputs (High Sense).
Most Negative Supply Voltage.
GUARD
NC
GUARDIN
AVCC_G
MEASVL
GUARD(NC)
MEASVH
MEASIL
MEASI0H
FOH0
MEASI1H
FOH1
MEASI2H
FOH2
MEASI3H
FOH3
MEASI4H
MEASI5H
AVEE_B
FOH
AVCC_B
External Force Driver Control Voltage Output.
Most Positive Supply Voltage.
COMPOUT0
COMPOUT1
COMPOUT2
COMPIN0
COMPIN1
COMPIN2
REFGND
MEASOUT
MEASIOUT
MEASVOUT
FIN
Compensation Capacitor 0 Output.
Compensation Capacitor 1 Output.
Compensation Capacitor 2 Output.
Compensation Capacitor 0 Input.
Compensation Capacitor 1 Input.
Compensation Capacitor 2 Input.
Analog Input/Output Reference Ground.
Multiplexed DUT Voltage/Current Sense Output. For details, see the Measured Parameter section.
DUT Current Sense Output.
DUT Voltage Sense Output.
Force Control Voltage Input.
Upper Clamp Voltage Input CLH > CLL.
Lower Clamp Voltage CLL < CLH.
CLH
CLL
REV. A
–7–
AD5520–Typical Performance Characteristics
0.0030
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
0
V
V
= +15V
= –15V
V
V
= +15V
= –15V
DD
SS
DD
SS
MODE 3
MODE 3
0.0025
0.0020
0.0015
0.0010
0.0005
0
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
TEMPERATURE (ꢂC)
TEMPERATURE (ꢂC)
TPC 1. Voltage Sense Amplifier Linearity vs. Temperature
TPC 4. Current Sense Linearity vs. Temperature
80
140
V
V
= +15V
= –15V
DD
SS
V
V
= +15V
= –15V
I
CMRR
DD
SS
SENSE
70
60
50
40
30
20
10
0
T
= 25ꢂC
120
100
80
60
40
20
0
A
T
= 25ꢂC
A
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 2. Voltage Sense Amplifier CMRR vs. Frequency
TPC 5. Current Sense Amplifier CMRR vs. Frequency
10
5
0
C
= 0.1nF
0
–10
–20
–30
–40
–50
–60
COMP
–5
C
= 0.1nF
–10
–15
–20
–25
–30
–35
–40
COMP
C
= 1.0nF
COMP
C
= 1.0nF
COMP
C
= 3.3nF
10k
COMP
C
= 3.3nF
10k
COMP
V
V
T
= +15V
= –15V
V
V
T
= +15V
= –15V
DD
SS
DD
SS
= 25ꢂC
= 25ꢂC
A
A
100
1k
100k
100
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 3. Force Amplifier Bandwidth–MODE 0 (4 A)
TPC 6. Force Amplifier Bandwidth–MODE 1 (40 A)
–8–
REV. A
AD5520
0
–5
0
–5
V
V
= +15V
= –15V
DD
SS
V
V
= +15V
= –15V
DD
SS
T
= 25ꢂC
A
T
= 25ꢂC
A
C
= 0.1nF
COMP
–10
–15
–20
–25
–30
–35
–40
–45
–10
–15
–20
–25
–30
–35
–40
–45
C
= 0.1nF
COMP
C
= 1.0nF
COMP
C
= 1.0nF
COMP
C
= 3.3nF
COMP
C
= 3.3nF
COMP
100
1k
10k
100k
100
1k
10k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
TPC 7. Force Amplifier Bandwidth–MODE 2 (400 A)
TPC 10. Force Amplifier Bandwidth–MODE 3 (4 mA)
5
30
V
V
= +15V
= –15V
DD
SS
T
= 25ꢂC
A
0
–5
20
10
I
SENSE
–10
–15
–20
–25
0
V
SENSE
–10
–20
–30
V
V
= +15V
= –15V
DD
SS
T
= 25ꢂC
A
1
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 8. Guard Amplifier Bandwidth
TPC 11. Voltage Sense and Current Sense
Amplifier Bandwidths
20
10
0
–5
V
V
= +15V
= –15V
DD
SS
V
V
= +15V
= –15V
DD
SS
T
= 25ꢂC
A
T
= 25ꢂC
A
0
–10
–15
–20
–25
–30
–10
–20
–30
–40
–50
–60
100k
1M
10M
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 9. Current Sense Amplifier AC PSRR
TPC 12. Force Amplifier AC PSRR–MODE 3,
CCOMP = 100 pF
REV. A
–9–
AD5520
20
16
14
12
10
8
V
V
= +15V
= –15V
= 25ꢂC
DD
SS
10
T
A
V
CC
0
–10
–20
–30
–40
–50
6
4
2
V
DUT
0
–60
100k
–2
1M
10M
0
5
10
15
20
25
30
35
40
45
FREQUENCY (Hz)
TIME (ms)
TPC 13. Voltage Sense Amplifier AC PSRR
TPC 15. Power Up
700
9
8
7
6
5
4
3
2
1
0
COMPIN2 = 100pF
COMPIN1 = 1000pF
600
500
400
300
200
100
0
GUARD
COMPIN2 = 3000pF
V
SENSE
FOH
I
SENSE
100
–1
10
1k
FREQUENCY (Hz)
10k
100k
0
0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008
TIME (s)
TPC 14. Noise Spectral Density
TPC 16. Settling Time, Mode 2
–10–
REV. A
AD5520
THEORY OF OPERATION
DAC
The AD5520 is a single channel per pin parametric measurement
unit (PPMU) for use in semiconductor automatic test equip-
ment. It contains programmable modes to force a pin voltage and
measure the corresponding current (FVMI), force current mea-
sure voltage (FIMV), force current measure current (FIMI), and
force voltage measure voltage (FVMV). The PPMU can force or
measure a voltage from –11 V to +11 V. It can force or measure a
current over four ranges: 4 µA, 40 µA, 400 µA, and 4 mA. The
addition of an external driver allows two extended ranges.
FIN
FOHx
MEASIHx
MEASIL
G = 16
G = 1
MEASIOUT
MEASVOUT
R
S
MEASVH
MEASVL
DUT
The device provides a force sense capability to ensure accuracy
at the tester pin. A guard output is also available to drive the
shield of a force/sense pair.
Figure 3. PMU in Standby Mode
Force Voltage or Force Current
FSEL is an input that determines whether the PPMU forces a
voltage or current.
The AD5520 has an on-board window comparator that pro-
vides two bits of useful information, DUT too low or too high.
Also provided on the chip is clamp circuitry that will flag via
CLHDETECT and CLLDETECT if the voltage applied to
FIN or across the DUT has exceeded the voltage applied to
CLL and CLH.
Table II. FSEL Function
On chip is clamp circuitry that clamps the output of the force
amplifier if the voltage at MEASIOUT and MEASVOUT
exceeds CLL and CLH.
FSEL
Function
Low
Voltage Force and Current Clamp with
MEASIOUT Voltage
High
Current Force and Voltage Clamp with
MEASVOUT Voltage
INTERFACE
The AD5520 PPMU is controlled via a number of digital inputs,
which are discussed in detail in the following sections. All inputs
are TTL compatible. CS is used to select the device while STB
(active low input) latches data available on the other digital inputs
and updates any required digital outputs. The rising edge of STB
triggers sequence inputs. The remaining digital inputs control the
function of the PMU—which measure mode it is in, which com-
pensation capacitor is used, and the selected current range.
Measured Parameter
MEASOUT is a muxed output that tracks the sensed parameter,
MSEL connects it to the output of either the current sense
amplifier or the voltage sense amplifier, depending on which is
the measured parameter of interest.
The MEASOUT pin will be connected back to an ADC to
allow the measured value to be converted to a digital code.
Standby Mode
The AD5520 may be placed into standby mode via the standby
logic input. In this mode, the force amplifier is disconnected from
the force input (FIN), the switch in series with the force output
pins, FOHx, is opened, and the current measure amplifier is dis-
connected from the sense resistors. The voltage measure amplifier
is still connected across the DUT, so DUT voltage measure-
ments may still be made while in standby mode. Figure 3 shows
the configuration of the PMU while in standby mode.
Table III. MEASOUT Connected to
Voltage or Current
MSEL
Function
Low
High
MEASOUT = DUT Voltage
MEASOUT = DUT Current
The MEASOUT pin may also be made high impedance through
the MOEB logic input.
Table I. Standby Mode
STANDBY
Function
Table IV. MOEB Allows MEASOUT
to Go High Impedance
Low
High
Normal Force Mode
Standby Mode
MOEB
Function
Low
High
Enable MEASOUT Output
Hi-Z MEASOUT Output
REV. A
–11–
AD5520
Current Ranges
After CPSEL has selected which amplifier output is of interest,
logic input CPCK is used to initiate comparator sampling and
update the logic outputs CPOH and CPOL, indicating if the
voltages at MEASIOUT or MEASVOUT have exceeded volt-
ages set at CPL or CPH (thus providing DUT too high or DUT
too low information). A rising edge on STB is required to clock
the CPOH and CPOL data out.
A number of current ranges are possible with the AD5520. The
AM0, AM1, and AM2 pins are digital inputs used to establish
full-scale current range of the PMU.
Table V. Selection of Current Range
AM0 AM1 AM2 Function
Table VIII. CPCK Synchronous Logic Outputs
Low Low Low Current Range MODE0 (up to 4 µA)
High Low Low Current Range MODE1 (up to 40 µA)
Low High Low Current Range MODE2 (up to 400 µA)
High High Low Current Range MODE3 (up to 4 mA)
Low Low High Current Range MODE4 (External
Buffer Mode)
High Low High Current Range MODE5 (External
Buffer Mode)
Low High High Standby (same as STANDBY = High)
CPOH
Function
Low
High
MEASVOUT or MEASIOUT < CPH
MEASVOUT or MEASIOUT > CPH
CPOL
Function
Low
High
MEASVOUT or MEASIOUT > CPL
MEASVOUT or MEASIOUT < CPL
High High High Standby (same as STANDBY = High)
Clamp Function
Clamp circuitry is also included on chip, allowing the output of
the force amplifier to be clamped in the event of the voltage at
MEASIOUT and MEASVOUT exceeding CLL and CLH. The
clamp circuitry play their role in the event of a short or open
circuit. When in force current range, the voltage clamps protect
the DUT in the event of an open circuit. Likewise, when forcing
a voltage and a short circuit occurs, the current clamps will
protect the DUT in this case. The clamps also function to pro-
tect the DUT in the event of a transient voltage or current spike
that may occur when changing to a different operating mode or
when programming the device to a different current range.
RS Selection
The AD5520 is designed so that the voltage drop across each of
the RS resistors will be less than 500 mV when maximum current
is flowing through them. To support other current ranges, these
sense resistor values may be changed. A force amplifier can
drive a maximum of 6 mA. It is not recommended to increase
the maximum current above the nominal range.
The two external current ranges use an external buffer to drive the
required current. Our example uses 40 mA and 160 mA ranges.
These ranges can be changed to suit user requirements for a high
current range.
The digital output flags, which indicate a clamp limit has been
hit, are CLHDETECT for the upper clamp and CLLDETECT
output for the lower clamp.
Force Control Amplifier
The force control amplifier requires external capacitors connected
between the COMPOUTx and COMPINx pins. For stability
with large capacitance at the DUT, the largest capacitance value
(3000 pF) should be selected. The force control amplifier should
always contribute the dominant pole in the control loop. Set-
tling times will increase with larger capacitances. ACx inputs
select which external compensation capacitor is used.
Table IX. Clamp Detect Outputs
CLHDETECT
Function
Low
High
Upper Clamp Inactive
Upper Clamp Active
CLLDETECT
Function
Table VI. AC0, AC1 Compensation Capacitor Selection
AC0 AC1 Function
Low
High
Lower Clamp Inactive
Lower Clamp Active
Low Low
High Low
Select External Compensation Capacitor 0
Select External Compensation Capacitor 1
High Current Ranges
With the use of an external high current amplifier, two high
current ranges are possible. The current range values can be
selected as required in the application through appropriate
selection of the sense resistors connected between MEASI5H,
MEASI4H, and MEASIL. When one of these high current
ranges (MODE 4 or MODE 5) is selected via the AMx control
lines, the appropriate QM4 or QM5 output will be enabled.
These outputs can thus be used to control relays connected in
series with the high current amplifier as shown in Figure 8.
Low High Select External Compensation Capacitor 2
Comparator Function and Strobing
The AD5520 has an on-board window comparator that pro-
vides two bits of useful information, DUT too low or too high.
CPSEL is the digital input that controls this function, selecting
whether it should compare to the voltage sense or the current
sense amplifier.
Table VII. Comparator Function Select
Table X. High Current Range Logic Outputs
CPSEL
Function
QM4
QM5
Function
Low
High
Compare CPL, CPH to MEASVOUT
Compare CPL, CPH to MEASIOUT
High
Low
Low
High
Current Range MODE 4 Enable Output
Current Range MODE 5 Enable Output
–12–
REV. A
AD5520
CIRCUIT OPERATION
Force Voltage
the CLL and CLH levels to ensure the clamp voltages have not
been exceeded. Strobing CPCK and STB will provide information
about the voltage level with respect to the comparator levels,
CPH and CPL.
Most PMU measurements are performed while in force voltage
and measure current modes, for example, when the device is
used as a device power supply, or in continuity or leakage
testing. In the force voltage mode, the voltage at analog input
FIN is mapped directly to the voltage forced at the DUT.
FIN
FOHx
MEASIHx
When in force voltage and measure current modes, the maxi-
mum voltage applied to the input corresponds to the maximum
current outputs. Figure 4 shows the transfer function when forcing
a voltage.
G = 16
G = 1
VFIN
R
S
CLH
CLL
MEASIL
MEASVH
V
DUT
R
DUT
VCLL
VCLH
MEASVL
REFGNDI/V
R
ꢃ
DUT
ꢃ 16
V
CLH
R
S
V
V
VMEASVOUT
VMEASIOUT
V
V
< I
< I
ꢃ R ꢃ 16
V
V
> I
> I
ꢃ R ꢃ 16
S
V
CLH
CLL
> I
ꢃ R ꢃ 16
V
CLH
CLL
DUT
DUT
S
CLH
CLL
DUT
DUT
DUT
DUT
S
FIN
CONDITION
OUTPUT
ꢃ R ꢃ 16
ꢃ R ꢃ 16
V
< I
ꢃ R ꢃ 16
S
S
S
V
= V
CLH
V
= V
V
= V
FIN
DUT
DUT CLL
DUT
R
DUT
ꢃ 16
V
CLL
ꢃ
R
S
Figure 5. Voltage Force, Measure Current Mode
Force Current
In the force current mode, the voltage at FIN is now converted
to a current through the following relationship:
Force Current =VFIN /RSENSE
I
DUT
Figure 6 shows a simplified diagram of the PMU when in
force current mode. The control loop consists of the force
amplifier with the current sense amplifier making up the feed-
back path. In this case, voltage at the DUT is sensed across
the voltage measure amplifier (Gain = 1) and presented at
the MEASVOUT output.
V
CLH
ꢃ 16
R
S
V
CLH
V
FIN
FIN
V
CLH
V
CLL
FOHx
MEASIHx
R
ꢃ 16
S
G = 16
G = 1
VFIN
R
S
CLH
CLL
MEASIL
MEASVH
R
DUT
VCLL
VCLH
Figure 4. Voltage Force Transfer Function
Measure Current
MEASVL
REFGNDI/V
Figure 5 shows a simplified diagram of the PMU when in force
voltage mode. The control loop consists of the force amplifier
with the voltage sense amplifier making up the feedback path.
Current flowing through the DUT is measured by sensing the
current flowing through a selectable sense resistor, which is in
series with the DUT. The current sense amplifier (Gain = 16)
generates a voltage at its output, which is proportional to the
current flowing through the DUT. This voltage is compared to
V
V
VMEASVOUT
VMEASIOUT
V
< V
< V
V
> V
> V
V
V
> V
< V
CLH
CLL
DUT
DUT
CLH
CLL
DUT
DUT
CLH
CLL
DUT
DUT
CONDITION
OUTPUT
V
V
V
V
V
FIN
S
CLH
CLL
I
=
I
=
I
=
DUT
DUT
DUT
R
R
R
S
S
Figure 6. Current Force, Voltage Measure Mode
REV. A
–13–
AD5520
Figure 7 illustrates the transfer function of the current force mode.
external compensation capacitors are added. As mentioned, mak-
ing an accurate measurement in the fastest time while avoiding
overshoots and ringing is the key requirement in any ATE system.
This in itself provides challenges. The external compensation
capacitors set up different settling times or bandwidths on the force
control amplifier, and, while one compensation capacitor value
may suit one range, it may not suit other ranges. To optimize
measurement performance and speed, differences in signal behav-
ior on each range and frequency of use of each range need to be
taken into account.
I
DUT
V
CLH
R
DUT
V
FIN
When selecting a faster settling time, there is a trade-off between
the faster settling, overshoots, and ringing. A small compensa-
tion value will result in faster settling but may incur penalties in
overshoots or ringing at the DUT. Compensation capacitor
selection should be optimized to ensure minimum overshoots
while still giving good settling time performance.
V
CLL
R
DUT
While careful selection of the compensation capacitor is required
to minimize the settling time, another factor can greatly contribute
to the overall settling of the loop if the feedback loop is broken
in some manner and the force control amplifier goes to either
the positive or negative rails. There is a finite amount of time
required for the amplifier to recover from this condition, typi-
cally 85 µs, which adds to the settling of the loop. Ensuring that
the force control amplifier never goes into saturation is the best
solution. This solution can be helped by putting the device into
standby mode at any time the operating mode or range selection
is changed. In addition, ensure that the selected output range
can supply the required current needed by the DUT.
V
DUT
V
CLH
V
CLH
V
FIN
V
CLH
V
CLH
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
to the power supply and the ground return layout helps to ensure
the rated performance. The printed circuit board on which
the AD5520 is mounted should be designed so that the analog
and digital sections are separated and confined to certain areas
of the board. If the PMU is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device.
Figure 7. Current Force Transfer Function
Measure Voltage
A DUT voltage is tested via the voltage measure amplifier by a
window comparator to ensure that CPH and CPL levels are not
exceeded. In addition, the DUT voltage is automatically tested
against the voltage levels at the clamp, and clamp flags are
enabled if the DUT voltage exceeds either of the levels.
This PMU should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the pack-
age as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR, 1 µF to 10 µF, tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Short Circuit Protection
The AD5520 is designed to withstand a direct short circuit on
any of the amplifier outputs.
SETTLING TIME CONSIDERATIONS
Fast throughput is a key requirement in automatic test equipment
because it relates directly to the cost of manufacturing the DUT,
thus reducing the time required to make a DAC measurement is of
upmost importance. When taking measurements using a PMU, the
limiting factor is usually the time it takes the output to settle to the
required accuracy so a measurement can be taken. DUT capaci-
tance, measurement accuracy, and the design of the PMU are the
major contributors to this time. Figure 8 shows a simplified block
diagram of the AD5520 PMU. In brief, the device consists of a
force control amplifier, access to a number of selectable sense
resistors, a voltage measure instrumentation amplifier, and a
current measure instrumentation amplifier. To optimize the
performance of the device, there are also nodes provided where
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on oppo-
site sides of the board should run at right angles to each other.
This reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane while signal
traces are placed on the solder side.
–14–
REV. A
AD5520
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
required, an external amplifier must be used with relays to switch
in the different current ranges to the DUT. Other components
are also required to make the PMU function. The PMU requires
a number of discrete voltage levels: five DAC levels for each
PMU used in the system, two levels each for the comparator
and clamps, and one voltage level for the AD5520 force input
voltage. To utilize the information gathered from the DUT, an
ADC (such as the AD7665 16-Bit ADC) must be connected to
the MEASOUT pin to convert the measured current or voltage
to the digital world for analysis.
TYPICAL CONNECTION CIRCUIT FOR THE AD5520
Figure 8 shows the AD5520 connected as it would be in a typical
application. The external components required are three com-
pensation capacitors and six sense resistors, depending on how
many ranges are required. If high current ranges > 6 mA are
3000pF
1000pF
100pF
+15V –15V
AV
EE
AV
CC
AD5520
AD815
FOH
FOH3
BW SELECT
RELAY
FOH2
FOH1
FOH0
FIN
FORCE
AMPLIFIER
<؎11.5V
MEASI5H
CLAMP
DETECT
MEASI4H
MEASI3H
MEASI2H
3.126⍀
12.5⍀
125⍀
CLH
CLL
MEASI1H
MEASI0H
1.25k⍀
12.5k⍀
REFGND
125k⍀
G = 16
MEASIOUT
MEASIL
I
SENSE
INST AMP
GUARDIN
GUARD
MEASOUT
V
SENSE
G = 1
Յ؎11V
INST AMP
MEASVH
MEASVL
G = 1
DUT
MEASVOUT
COMPARATOR
CPH
AGND
QM5
<؎100mV
CPOH
LOGICS
QM4
CPOH
CPL
CPCK
Figure 8. Typical Configuration of the AD5520 as Used in an ATE Circuit
REV. A
–15–
AD5520
TYPICAL APPLICATION CIRCUIT
centronics connector to a PC. PC-based software to control the
AD5520 is provided as part of the evaluation kit. The evalua-
tion board schematic is shown in Figure 10. Note that VDD and
VSS must provide sufficient headroom for the force and measure
voltage range. In addition to the supply voltages for the evalua-
tion board, it is also necessary to provide the following voltage
levels for the clamp, comparator, and the force input pin—CLL,
CLH, CPL, CPH, and FIN. SMB connections are provided
for these voltage inputs. To use the evaluation board, it will also
be necessary to provide a DUT connected via the gold pins.
Figure 9 shows the AD5520 as it would be used in an ATE
system. This device could be used as a per pin parametric unit
in order to speed up the rate at which testing could be done. It
could also be used as a DUT power supply, as shown in the
application circuit. The central PMU shown in the block
diagram is usually a highly accurate PMU and is shared among a
number of pins in the tester. In general, many discrete levels are
required in an ATE system for the pin drivers, comparators,
clamps, and active loads. DAC devices, such as the AD5379, offer
a highly integrated solution for a number of these levels. The
AD5379 is a dense 40-channel DAC designed with high channel
requirements, like ATE in mind.
Both AGND and DGND inputs are provided on the board.
The AGND and DGND planes are connected at one location
close to the AD5520. It is recommended not to connect AGND
and DGND elsewhere in the system to avoid ground loop prob-
lems. REFGND is routed back to AGND at the power block to
maintain a clean ground reference for accurate measurements.
The flexible function of the AD5520 also makes it suited for use in
instrumentation applications such as source measure units. Source
measure units are programmable instruments capable of sourcing
and measuring voltage or current simultaneously. The AD5520
provides a more integrated solution in such equipment.
Each supply is decoupled to the relevant ground plane with
10 F and 0.1 F capacitors. The device supply pin is again
decoupled with a 10 F and 0.1 F capacitor pair to the relevant
ground plane.
EVALUATION BOARD FOR THE AD5520 PMU
A full featured evaluation kit is available for the AD5520. It
consists of an evaluation board with direct hookup via a 36-way
Care should be taken when replacing devices to ensure that
the pins line up correctly with the PCB pads.
CENTRAL PMU
DAC
GUARD AMP
PPMU
ADC
VCH
DAC
DAC
ADC
VTERM
DAC
VH
TIMING DATA
MEMORY
DEVICE UNDER
TEST (DUT)
DAC
RELAYS
50ꢄ COAX
TIMING
FORMATTER
DE-SKEW
DRIVER
VL
GENERATOR
DLL, LOGIC
VCL
GUARD
AMP
DAC
DAC
DAC
GND SENSE
DEVICE POWER
SUPPLIES
VTH
VTL
DAC
COMPARE
MEMORY
FORMATTER
DE-SKEW
COMP
ADC
DAC
ACTIVE LOAD
IOL
DAC
DAC
VCOM
DAC
IOH
Figure 9. Typical Application ATE Circuit
–16–
REV. A
AD5520
R L 2
– G Y 6 H R E L A
R L 1
R 7
R 6
– G Y 6 H R E L A
ꢄ
ꢄ
1 2 . R 4 5 ,
1 2 4 R 4 ,
1 . 2 R 4 3 k ,
1 2 . R 4 2 k ,
ꢄ
ꢄ
ꢄ
1 2 4 R k 1 ,
D [ 0 : 7 ]
Figure 10. Evaluation Board Schematic
–17–
REV. A
AD5520
OUTLINE DIMENSIONS
64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
0.75
0.60
0.45
12.00 BSC
1.60
MAX
SQ
64
49
1
48
SEATING
PLANE
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
10؇
6؇
2؇
1.45
1.40
1.35
0.20
0.09
VIEW A
7؇
3.5؇
0؇
16
33
0.15
0.05
17
32
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BCD
–18–
REV. A
AD5520
Revision History
Location
Page
10/03—Data Sheet changed from REV. 0 to REV. A.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. A
–19–
–20–
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