EVAL-AD5532EB [ADI]
32-Channel, 14-Bit Voltage-Output DAC; 32通道， 14位电压输出DAC
| 型号： | EVAL-AD5532EB |
| 厂家： | 
ADI |
| 描述： | 32-Channel, 14-Bit Voltage-Output DAC |
| 文件： | 总16页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Channel, 14-Bit
Voltage-Output DAC
a
AD5532*
GENERAL DESCRIPTION
FEATURES
High Integration: 32-Channel DAC in 12
؋
12 mm2 LFBGA Adjustable Voltage Output Range
Guaranteed Monotonic
The AD5532 is a 32-channel voltage-output 14-bit DAC with
an additional infinite sample-and-hold mode. The selected DAC
register is written to via the 3-wire serial interface and VOUT
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via address bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from VSS + 2 V to VDD – 2 V because
of the headroom of the output amplifier.
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Output Impedance
0.5 ⍀ (AD5532-1, AD5532-2)
500 ⍀ (AD5532-3)
1 k⍀ (AD5532-5)
Output Voltage Span
10 V (AD5532-1, AD5532-3, AD5532-5)
20 V (AD5532-2)
Infinite Sample-and-Hold Capability to ؎0.018% Accuracy
Temperature Range –40؇C to +85؇C
The device is operated with AVCC = 5 V 5%, DVCC = 2.7 V
to 5.25 V, VSS = –4.75 V to –16.5 V and VDD = 8 V to 16.5 V
and requires a stable +3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
APPLICATIONS
1. 32-channel, 14-bit DAC in one package, guaranteed
monotonic.
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
2. The AD5532 is available in a 74-lead LFBGA package with
a body size of 12 mm × 12 mm.
3. Droopless/Infinite Sample-and-Hold Mode.
Low Cost I/O
FUNCTIONAL BLOCK DIAGRAM
DV
AV
OFFS IN
V
V
SS
REF IN REF OUT
CC
CC
DD
AD5532
V
0
OUT
V
ADC
DAC
IN
TRACK/RESET
BUSY
V
31
OUT
MUX
DAC
DAC
DAC GND
AGND
OFFS OUT
DGND
INTERFACE
CONTROL
LOGIC
SER/PAR
ADDRESS INPUT REGISTER
WR
OFFSET SEL
A4–A0
CAL
SCLK
D
D
SYNC/ CS
IN
OUT
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(V = 8 V to 16.5 V, V = –4.75 V to –16.5 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to
5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from VSS + 2 V to VDD – 2 V. All outputs unloaded. All specifications TMIN
to TMAX unless otherwise noted.)
AD5532–SPECIFICATIONS
DD
SS
CC
CC
A Version2
Conditions/
Comments
Parameter1
AD5532-1/-3/-5
AD5532-2 Only
Unit
DAC DC PERFORMANCE
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset
14
0.39
1
90/170/250
3.52
2
14
0.39
1
180/350/500
7
2
Bits
% of FSR max
LSB max
mV min/typ/max
typ
0.15% typ
0.5% typ, Monotonic
See Figure 6
Gain
Full-Scale Error
% of FSR max
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage
Input Voltage Range3
Input Current
3.0
2.85/3.15
1
3.0
2.85/3.15
1
V
V min/max
µA max
< 1 nA typ
REF_OUT
Output Voltage
3
280
60
3
280
60
V typ
kΩ typ
ppm/°C typ
Output Impedance3
Reference Temperature Coefficient3
ANALOG OUTPUTS (VOUT 0–31)
Output Temperature Coefficient3, 4
DC Output Impedance3
AD5532-1
20
20
ppm/°C typ
0.5
500
1
0.5
Ω typ
Ω typ
kΩ typ
V min/max
kΩ min
AD5532-3
AD5532-5
Output Range
V
5
SS + 2/VDD – 2
VSS + 2 /VDD – 2
5
100 µA Output Load
Resistive Load3, 5
Capacitive Load3, 5
AD5532-1
500
15
40
500
pF max
nF max
nF max
mA typ
dB typ
dB typ
µV max
AD5532-3
AD5532-5
Short-Circuit Current3
DC Power-Supply Rejection Ratio3
10
10
–70
–70
250
–70
–70
250
VDD = +15 V 5%
V
SS = –15 V 5%
DC Crosstalk3
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient3, 4
DC Output Impedance3
Output Range
20
1.3
20
1.3
ppm/°C typ
kΩ typ
mV typ
50 to REF_IN–12
50 to REF_IN–12
Output Current
Capacitive Load
10
100
10
100
µA max
pF max
Source Current
DIGITAL INPUTS3
Input Current
Input Low Voltage
10
0.8
0.4
2.4
2.0
200
10
10
0.8
0.4
2.4
2.0
200
10
µA max
V max
V max
V min
V min
mV typ
5 µA typ
DVCC = 5 V 5%
DVCC = 3 V 10%
DVCC = 5 V 5%
DVCC = 3 V 10%
Input High Voltage
Input Hysteresis (SCLK and CS Only)
Input Capacitance
pF max
3
DIGITAL OUTPUTS (BUSY, DOUT
Output Low Voltage, DVCC = 5 V
Output High Voltage, DVCC = 5 V
Output Low Voltage, DVCC = 3 V
Output High Voltage, DVCC = 3 V
High Impedance Leakage Current
)
0.4
4.0
0.4
2.4
1
0.4
4.0
0.4
2.4
1
V max
V min
V max
V min
µA max
pF typ
Sinking 200 µA
Sourcing 200 µA
Sinking 200 µA
Sourcing 200 µA
D
OUT Only
High Impedance Output Capacitance
15
15
DOUT Only
–2–
REV. 0
AD5532
Conditions/
A Version2
Parameter1
AD5532-1/-3/-5
AD5532-2 Only
Unit
Comments
POWER REQUIREMENTS
Power-Supply Voltages
VDD
VSS
AVCC
DVCC
8/16.5
8/16.5
V min/max
V min/max
V min/max
V min/max
–4.75/–16.5
4.75/5.25
2.7/5.25
–4.75/–16.5
4.75/5.25
2.7/5.25
Power-Supply Currents6
IDD
15
15
15
15
mA max
mA max
10 mA typ.
All Channels Full-Scale
10 mA typ.
ISS
All Channels Full-Scale
26 mA typ
1 mA typ
AICC
33
1.5
280
33
1.5
280
mA max
mA max
mW typ
DICC
Power Dissipation6
VDD = 10 V, VSS = –5 V
AC CHARACTERISTICS3
Output Voltage Settling Time
22
10
1
30
20
1
µs max
µs max
nV-s typ
500 pF, 5 kΩ Load
Full-Scale Change
500 pF, 5 kΩ Load;
0 V–3 V Step
1 LSB Change Around
Major Carry
OFFS_IN Settling Time
Digital-to-Analog Glitch Impulse
Digital Crosstalk
5
5
nV-s typ
Analog Crosstalk
1
1
nV-s typ
Digital Feedthrough
0.2
0.2
nV-s typ
Output Noise Spectral Density @ 1 kHz
400
400
nV/(√Hz) typ
NOTES
5Ensure that you do not exceed TJ (max). See Maximum Ratings.
6Output unloaded.
1See Terminology.
2A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3Guaranteed by design and characterization, not production tested.
4AD780 as reference for the AD5532.
Specifications subject to change without notice.
SHA MODE
A Version2
Conditions/
Comments
Parameter1
AD5532-1/-3/-5
AD5532-2 Only
Unit
ANALOG CHANNEL
VIN to VOUT Nonlinearity3
0.018
0.018
% max
0.006% typ after Offset and
Gain Adjustment
Offset Error
Gain
50
100
6.88/7/7.12
mV max
min/typ/max
10 mV typ. See Figure 7
See Figure 7
3.46/3.52/3.6
ANALOG INPUT (VIN
Input Voltage Range
Input Lower Deadband
Input Upper Deadband
Input Current
)
0 to 3
70
0 to 3
70
V
Nominal Input Range
50 mV typ. Referred to VIN
See Figure 7
12 mV typ. Referred to VIN
See Figure 7
mV max
.
.
40
1
40
1
mV max
µA max
pF typ
100 nA typ.
V
IN Acquired on 1 Channel
Input Capacitance4
20
20
ANALOG INPUT (OFFS_IN)
Input Current
1
1
µA max
100 nA typ
AC CHARACTERISTICS
Output Settling Time4
Acquisition Time
3
16
5
3
16
5
µs max
µs max
nV-s typ
Output Unloaded
AC Crosstalk4
NOTES
1See Terminology.
2A version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3Input range 100 mV to 2.96 V.
4Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
–3–
REV. 0
AD5532
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Limit at TMIN, TMAX
Parameter1, 2
(A Version)
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
0
0
50
50
20
0
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
NOTES
1See Interface Timing Diagram.
2Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at TMIN, TMAX
Parameter1, 2
(A Version)
Unit
Conditions/Comments
3
fCLKIN
t1
t2
t3
t4
t5
t6
t74
t84
t9
t10
t11
14
28
28
10
50
10
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
DIN Setup Time
DIN Hold Time
5
SYNC Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to DOUT Valid
SCLK Falling Edge to DOUT High Impedance
10th SCLK Falling Edge to SYNC Falling Edge for Readback
24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write
20
60
400
400
NOTES
1See Serial Interface Timing Diagrams.
2Guaranteed by design and characterization, not production tested.
3In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMS
I
CS
200A
OL
TO
OUTPUT
PIN
1.6V
WR
C
50pF
L
I
200A
OH
A4–A0, CAL,
OFFS SEL
Figure 2. Load Circuit for DOUT Timing Specifications
Figure 1. Parallel Write (SHA Mode Only)
–4–
REV. 0
AD5532
SERIAL INTERFACE TIMING DIAGRAMS
t1
SCLK
1
2
3
4
5
6
7
8
9
10
t2
t3
SYNC
t4
t5
t6
D
IN
MSB
LSB
Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)
t1
2
SCLK
1
3
4
5
21
22
23
24
1
t2
t3
SYNC
t11
t4
t5
t6
D
IN
MSB
LSB
Figure 4. 24-Bit Write (DAC Mode)
t1
2
SCLK
1
3
4
5
6
7
8
9
10
11
12
13
14
10
t7
t2
SYNC
t10
t4
t8
t9
D
OUT
MSB
LSB
Figure 5. 14-Bit Read (Both Readback Modes)
–5–
REV. 0
AD5532
ABSOLUTE MAXIMUM RATINGS1, 2
Operating Temperature Range
(TA = 25°C unless otherwise noted)
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_ GND . . . . . . . . . . –0.3 V to +7 V
VIN to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V
VOUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
VOUT0–31 to VSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
OFFS_IN to AGND . . . . . . . . . .
VSS – 0.3 V to VDD + 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
ORDERING GUIDE
Output
Impedance
Output
Voltage Span
Package
Description
Package
Option
Model
Function
AD5532ABC-1
AD5532ABC-2
AD5532ABC-3
AD5532ABC-5
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
0.5 Ω typ
0.5 Ω typ
500 Ω typ
1 kΩ typ
10 V
20 V
10 V
10 V
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
BC-74
BC-74
BC-74
BC-74
AD5533ABC-1*
EVAL-AD5532EB
*Separate Data Sheet.
32-Channel SHA Only
Evaluation Board
0.5 Ω typ
10 V
74-Lead LFBGA
BC-74
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. 0
AD5532
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
1
2
3
4
5
6
7
8
9
10 11
74-Lead LFBGA Ball Configuration
LFBGA
Number
Ball
Name
LFBGA
Number
Ball
Name
LFBGA
Number
Ball
Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C6
N/C
A4
A2
A0
CS/SYNC
DVCC
SCLK
OFFSET_SEL
BUSY
TRACK/RESET
N/C
VO16
N/C
A3
A1
WR
DGND
DIN
C10
C11
D1
AVCC1
REF_OUT
VO20
DAC_GND2
AVCC2
OFFS_OUT
VO26
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
VO9
VO11
VO17
VO15
VO27
VSS3
VSS1
VSS4
VDD2
VO2
VO10
VO13
VO12
N/C
VO28
VO29
VO30
VDD3
VDD1
VDD4
VO31
VO0
D2
D10
D11
E1
E2
VO14
E10
E11
F1
AGND1
OFFS_IN
VO25
VO21
AGND2
VO6
VO24
VO8
VO5
VO3
VO23
VIN
VO4
VO7
VO22
VO19
VSS2
F2
F10
F11
G1
G2
G10
G11
H1
H2
H10
H11
J1
CAL
SER/PAR
DOUT
REF_IN
VO18
DAC_GND1
N/C
L10
L11
VO1
N/C
J2
J6
–7–
REV. 0
AD5532
PIN FUNCTION DESCRIPTION
Pin
Function
AGND (1–2)
AVCC (1–2)
Analog GND Pins.
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
VDD Supply Pins. Voltage range from 8 V to 16.5 V.
VSS Supply Pins. Voltage range from –4.75 V to –16.5 V.
Digital GND Pins.
V
V
DD (1–4)
SS (1–4)
DGND
DVCC
DAC_GND(1–2)
REF_IN
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for All the DACs.
Reference Voltage for Channels 0–31.
REF_OUT
Reference Output Voltage.
VOUT (0–31)
Analog Output Voltages from the 32 Channels.
VIN
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface: 5-Address Pins for 32 Channels. A4 = MSB of Channel Address. A0 = LSB.
Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously.
A4–A11, A02
CAL1
CS/SYNC
This pin is both the active low Chip Select pin for the parallel interface and the Frame Synchronization pin
for the serial interface.
Parallel Interface: Write pin. Active low. This is used in conjunction with the CS pin to address the device
WR1
using the parallel interface.
OFFSET_SEL1
SCLK2
Parallel Interface: Offset Select Pin. Active high. This is used to select the offset channel.
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in SHA mode).
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
2
DIN
DOUT
Output from the DAC Registers for readback. Data is clocked out on the rising edge of SCLK and is
valid on the falling edge of SCLK.
SER/PAR1
OFFS_IN
OFFS_OUT
BUSY
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the Offset Channel.
Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the
span.
This output tells the user when the input voltage is being acquired. It goes low during acquisition and
returns high when the acquisition operation is complete.
If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge
of TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low-going
pulse of between 50 ns and 150 ns to this pin. See section on RESET Function for further details.
TRACK/RESET2
NOTES
1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
OUTPUT
VOLTAGE
V
OUT
GAIN ERROR +
OFFSET ERROR
FULL-SCALE
ERROR RANGE
IDEAL
TRANSFER
FUNCTION
IDEAL GAIN
؋
REFIN IDEAL TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OFFSET
ERROR
OFFSET
RANGE
IDEAL GAIN
؋
50mV 70mV
2.96 3V
V
IN
0V
0
16k
DAC CODE
LOWER
DEADBAND
UPPER
DEADBAND
Figure 6. DAC Transfer Function (OFFS_IN = 0)
Figure 7. SHA Transfer Function
–8–
REV. 0
AD5532
Output Noise Spectral Density
TERMINOLOGY
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root Hertz).
It is measured by loading all DACs to midscale and measur-
DAC MODE
Integral Nonlinearity (INL)
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is expressed as a percentage of full-scale span.
ing noise at the output. It is measured in nV/(√Hz)1/2
.
Output Temperature Coefficient
This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.
Differential Nonlinearity (DNL)
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of 1 LSB maximum ensures
monotonicity.
DC Power-Supply Rejection Ratio
DC Power-Supply Rejection Ratio (PSRR) is a measure of the
change in analog output for a change in supply voltage (VDD and
VSS). It is expressed in dBs. VDD and VSS are varied 5%.
Offset
Offset is a measure of the output with all zeros loaded to the
DAC and OFFS_IN = 0. Since the DAC is lifted off the ground
by approximately 50 mV, this output will typically be:
DC Crosstalk
This the DC change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of all other DACs. It is expressed in µV.
VOUT = Gain × 50 mV
Full-Scale Error
SHA MODE
This is a measure of the output error with all 1s loaded to the
DAC. It is expressed as a percentage of full-scale range. See Fig-
ure 6. It is calculated as:
V
IN to VOUT Nonlinearity
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the VIN versus VOUT transfer
function. It is expressed as a percentage of the full-scale span.
Full-Scale Error = VOUT(Full-Scale) – (Ideal Gain × REFIN)
where
Offset Error
This is a measure of the output error when VIN = 70 mV. Ideally,
with VIN = 70 mV:
Ideal Gain = 3.52 for AD5532-1/-3/-5
Ideal Gain = 7 for AD5532-2
VOUT = (Gain × 70) – ((Gain – 1) × VOFFS_IN) mV
Output Settling Time
This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within 0.39%.
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal). It is expressed in mV and can be positive or
negative. See Figure 7.
OFFS_IN Settling Time
This is the time taken from a 0 V–3 V step change in input volt-
age on OFFS_IN until the output has settled to within 0.39%.
Gain Error
This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function expressed in mV.
See Figure 7. It is calculated as:
Digital-to-Analog Glitch Impulse
This is the area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as the
area of the glitch in nV-secs when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).
Gain Error = Actual Full-Scale Output – Ideal Full-Scale Output –
Offset Error
where
Ideal Full-Scale Output = Gain × 2.96 – ((Gain – 1) × VOFFS_IN
)
Digital Crosstalk
AC Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-secs.
This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.
Analog Crosstalk
Output Settling Time
This is the time taken from when BUSY goes high to when the
output has settled to 0.018%.
This the area of the glitch transferred to the output (VOUT) of
one DAC due to a full-scale change in the output (VOUT) of
another DAC. The area of the glitch is expressed in nV-secs.
Acquisition Time
Digital Feedthrough
This is the time taken for the VIN input to be acquired. It is the
length of time that BUSY stays low.
This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., CS/SYNC is high. It is specified in nV-secs and is mea-
sured with a worst-case change on the digital input pins, e.g.,
from all 0s to all 1s and vice versa.
–9–
REV. 0
–Typical Performance Characteristics
AD5532
1.0
0.2
0.1
5.325
5.315
5.305
5.295
5.285
5.275
1.0
V
= 3V
= 0V
DAC LOADED TO MIDSCALE
REFIN
0.8
0.6
V
= 3V
V
REFIN
OFFS_IN
OFFS_IN
= 25
V
= 0V
T
؇C
A
DNL MAX
INL MAX
0.5
0.0
0.4
0.2
0.0
0.0
INL MIN
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.5
–1.0
DNL MIN
–40
0
40
80
–40
0
40
80
0
2k 4k
6k 8k 10k 12k 14k 16k
DAC CODE
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 9. INL Error and DNL Error
vs. Temperature
Figure 10. VOUT vs. Temperature
Figure 8. Typical DNL Plot
10.0
5.309
5.308
5.307
5.306
5.305
5.304
3.535
3.530
3.525
3.520
T
V
V
= 25؇C
A
T
V
= 25؇C
A
= 3V
REFIN
= 3V
8.0
6.0
REFIN
= 0.5V
OFFS_IN
4.0
2.0
T
= 25؇C
5.303
5.302
5.301
A
V
V
= 3V
0.0
REFIN
= 0V
OFFS_IN
–2.0
6
4
2
0
–2
–4
–6
TIME BASE – 2s/DIV
TIME BASE – 50ns/DIV
SINK/SOURCE CURRENT – mA
Figure 11. VOUT Source and Sink
Capability
Figure 12. Full-Scale Settling Time
Figure 13. Major Code Transition
Glitch Impulse
0.0024
70k
T
V
V
= 25؇C
63791
T
= 25؇C
A
A
0.0020
0.0016
= 3V
V
V
V
= 3V
REFIN
60k
50k
40k
30k
20k
10k
0
REFIN
5V
= 0V
= 1.5V
OFFS_IN
IN
OFFS_IN
0.0012
= 0V
100
90
BUSY
0.0008
0.0004
V
0.0000
OUT
–0.0004
–0.0008
–0.0012
–0.0016
–0.0020
–0.0024
T
V
V
= 25؇C
A
= 3V
REFIN
= 0 1.5V
10
IN
0%
1545
5.2682
1V
2s
200
5.2670
5.2676
0.1
2.96
V
– V
V
– V
IN
OUT
Figure 16. SHA-Mode Repeatability
(64K Acquisitions)
Figure 14. VIN to VOUT Accuracy
After Offset and Gain Adjustment
(SHA Mode)
Figure 15. Acquisition Time and
Output Settling Time (SHA Mode)
–10–
REV. 0
AD5532
FUNCTIONAL DESCRIPTION
Reset Function
The AD5532 can be thought of as consisting of 32 DACs and
an ADC (for SHA mode) in a single package. In DAC mode a
14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (VOUT0–VOUT31).
The reset function on the AD5532 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple-
mented by applying a low-going pulse of between 50 ns and 150 ns
to the TRACK/RESET pin on the device. If the applied pulse is
less than 50 ns it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 150 ns this pin
adopts its track function on the selected channel, VIN is switched
to the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK.
To update a DAC’s output voltage the required DAC is addressed
via the serial port. When the DAC address and code have been
loaded the selected DAC converts the code.
On power-on, all the DACs, including the offset channel, are
loaded with zeros. The internal DAC outputs are at 50 mV
typical (negative full-scale). If the OFFS_IN pin is driven by
the on-board offset channel, the outputs VOUT0 to VOUT31 are
SHA Mode
In SHA mode the input voltage VIN is sampled and converted
into a digital word. The noninverting input to the output buffer
(gain and offset stage) is tied to VIN during the acquisition period
to avoid spurious outputs while the DAC acquires the correct
code. This is completed in 16 µs max. At this time the updated
DAC output assumes control of the output voltage. The output
voltage of the DAC is connected to the noninverting input of
the output buffer. Since the channel output voltage is effectively
the output of a DAC there is no droop associated with it. As
long as power is maintained to the device the output voltage will
remain constant until this channel is addressed again.
also at 50 mV on power-on since OFFS_IN = 50 mV, VOUT
=
(Gain × VDAC) –(Gain –1) × VOFFS_IN = 50 mV.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the 0 V–3 V
output of the DAC to a wider range. This is done by gaining up
the DAC output by 3.52/7 and offsetting the voltage by the
voltage on OFFS_IN pin.
AD5532-1/AD5532-3/AD5532-5:
Analog Input (SHA Mode)
VOUT = 3.52 × VDAC – 2.52 × VOFFS_IN
The equivalent analog input circuit is shown in Figure 17. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged
to the previously acquired voltage on that particular channel
so it must charge/discharge to the new level. It is essential that the
external source can charge/discharge this additional capaci-
tance within 1 µs–2 µs of channel selection so that VIN can be
acquired accurately. For this reason a low impedance source
is recommended.
AD5532-2:
V
OUT = 7 × VDAC – 6 × VOFFS_IN
V
V
DAC is the output of the DAC.
OFFS_IN is the voltage at the OFFS_IN pin.
The following table shows how the output range on VOUT relates
to the offset voltage supplied by the user:
Table I. Sample Output Voltage Ranges
VOFFS_IN
(V)
VDAC
(V)
VOUT
VOUT
ADDRESSED CHANNEL
(AD5532-1/-3/-5) (AD5532-2)
V
IN
0.5
1
0 to 3
0 to 3
–1.26 to +9.3
–2.52 to +8.04
Headroom Limited
–6 to +15
C2
7.5pF
C1
20pF
V
V
OUT is limited only by the headroom of the output amplifiers.
OUT must be within maximum ratings.
Offset Voltage Channel
The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset volt-
age channel on the device itself. The offset can be set up in
two ways. In SHA mode the required offset voltage is set up
on VIN and acquired by the offset channel. In DAC mode the
code corresponding to the offset value is loaded directly into
the offset DAC. This offset channel’s DAC output is directly
connected to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN
this offset voltage can be used as the offset voltage for the 32
output amplifiers. It is important to choose the offset so that
VOUT is within maximum ratings.
Figure 17. Analog Input Circuit
Large source impedances will significantly affect the performance
of the ADC. This may necessitate the use of an input buffer
amplifier.
TRACK Function (SHA Mode)
Normally in SHA mode of operation, TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, VIN is switched to
the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage the BUSY pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
VIN is free to change again without affecting this output value.
–11–
REV. 0
AD5532
PIN
DRIVER
V
1
OUT
OUTPUT
STAGE
DEVICE
UNDER
TEST
V
IN
ACQUISITION
CIRCUIT
CONTROLLER
DAC
BUSY
TRACK
AD5532
THRESHOLD
VOLTAGE
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
Figure 18. Typical ATE Circuit Using TRACK Input
DOUT line in a 14-bit serial format. The full acquisition time
must elapse before the DAC register data can be clocked out.
This is useful in an application where the user wants to ramp up
IN until VOUT reaches a particular level (Figure 18). VIN does
V
not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when VOUT has reached its
desired voltage is TRACK brought high. At this stage, the
acquisition of VIN begins.
4. Readback Mode
Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the DOUT line in a 14-bit serial format.
The user must allow 400 ns (min) between the last SCLK fall-
ing edge in the 10-bit write and the falling edge of SYNC in
the 14-bit readback. The serial write and read words can be
seen in Figure 19.
In the example shown, a desired voltage is required on the out-
put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on VIN through a DAC. TRACK is kept low
while the voltage on VIN ramps up so that VIN is not continu-
ally acquired. When the desired voltage is reached on the output
of the pin driver, the comparator output switches. The µC/µP
then knows what code is required to be input in order to obtain
the desired voltage at the DUT. The TRACK input is now
brought high and the part begins to acquire VIN. At this stage
BUSY goes low until VIN has been acquired. The output buffer
is then switched from VIN to the output of the DAC.
This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode this is useful in verification
of write cycles. In SHA mode readback is useful if the system
has been calibrated and the user wants to know what code in
the DAC corresponds to a desired voltage on VOUT. If the user
requires this voltage again, he can input the code directly to the
DAC register without going through the acquisition sequence.
MODES OF OPERATION
INTERFACES
Serial Interface
The SER/PAR pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:
The AD5532 can be used in four different modes of opera-
tion. These modes are set by two mode bits, the first two bits in
the serial word.
Table II. Modes of Operation
SYNC, DIN, SCLK
Mode Bit 1
Mode Bit 2
Operating Mode
Standard 3-wire interface pins. The SYNC pin is shared
with the CS function of the parallel interface.
0
0
1
1
0
1
0
1
SHA Mode
DAC Mode
Acquire and Readback
Readback
DOUT
Data Out pin for reading back the contents of the DAC
registers. The data is clocked out on the rising edge of SCLK
and is valid on the falling edge of SCLK.
1. DAC Mode
In this standard mode a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The
user must allow 400 ns (min) between successive writes in DAC
mode.
Mode Bits
There are four different modes of operation as described above.
Cal Bit
In DAC mode this is a test bit. When it is high it is used to load
all zeros or all ones to the 32 DACs simultaneously. In SHA mode
all 32 channels acquire VIN simultaneously when this bit is high.
In SHA mode the acquisition time is then 45 µs (typ) and accu-
racy may be reduced. This bit is set low for normal operation.
2. SHA Mode
In this mode a channel is addressed and that channel acquires
the voltage on VIN. This mode requires a 10-bit write (see Fig-
ure 21) to address the relevant channel (VOUT0–VOUT31, offset
channel or all channels) MSB is written first.
Offset_Sel Bit
If this is set high, the offset channel is selected and Bits A4–
A0 are ignored.
3. Acquire and Readback Mode
This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and VIN is acquired in 16 µs (max).
Following the acquisition, after the next falling edge of SYNC,
the data in the relevant DAC register is clocked out onto the
Test Bit
This must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
–12–
REV. 0
AD5532
MSB
LSB
0
0
CAL
0
OFFSET SEL
A4–A0
MODE BIT 1 MODE BIT 2
MODE BITS
TEST BIT
a. 10-Bit Input Serial Write Word (SHA Mode)
MSB
LSB
0
1
CAL
0
OFFSET SEL
A4–A0
DB13–DB0
TEST BIT
MODE BITS
b. 24-Bit Input Serial Write Word (DAC Mode)
MSB
LSB
A4–A0
MSB
LSB
1
0
CAL
OFFSET SEL
0
DB13–DB0
TEST BIT
MODE BITS
14-BIT DATA
10-BIT
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
SERIAL WORD
WRITTEN TO PART
c. Input Serial Interface (Acquire and Readback Mode)
MSB
LSB
A4–A0
MSB
LSB
1
1
CAL
OFFSET SEL
0
DB13–DB0
TEST BIT
MODE BITS
14-BIT DATA
10-BIT
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
SERIAL WORD
WRITTEN TO PART
d. Input Serial Interface (Readback Mode)
Figure 19. Serial Interface Formats
DB13–DB0
falling edge of the SYNC signal and on subsequent SCLK fall-
ing edges. During readback DIN is ignored. The serial interface
will not shift data in or out until it receives the falling edge of
the SYNC signal.
These are used to write a 14-bit word into the addressed DAC
register. Clearly, this is only valid when in DAC mode.
The serial interface is designed to allow easy interfacing to
most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI,
SPI, DSP56000, TMS320, and ADSP-21xx, without the need
for any glue logic. When interfacing to the 8051, the SCLK
must be inverted. The Microprocessor/Microcontroller Interface
section explains how to interface to some popular DSPs and
microcontrollers.
Parallel Interface (SHA Mode Only)
The SER/PAR bit must be tied low to enable the parallel inter-
face and disable the serial interface. The parallel interface is
controlled by 9 pins.
CS
Active low package select pin. This pin is shared with the SYNC
Figures 3, 4, and 5 show the timing diagram for a serial read and
write to the AD5532. The serial interface works with both a con-
tinuous and a noncontinuous serial clock. The first falling edge of
SYNC resets a counter that counts the number of serial clocks to
ensure the correct number of bits are shifted in and out of the
serial shift registers. Any further edges on SYNC are ignored until
the correct number of bits are shifted in or out. Once the correct
number of bits for the selected mode have been shifted in or out,
the SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the falling edge of SYNC.
function for the serial interface.
WR
Active low write pin. The values on the address pins are latched
on a rising edge of WR.
A4–A0
Five address pins (A4 = MSB of address, A0 = LSB). These are
used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel is
addressed. The address on A4–A0 is ignored in this case.
In readback, the first rising SCLK edge after the falling edge of
SYNC causes DOUT to leave its high impedance state and data
is clocked out onto the DOUT line and also on subsequent SCLK
rising edges. The DOUT pin goes back into a high impedance
state on the falling edge of the fourteenth SCLK. Data on the
DIN line is latched in on the first SCLK falling edge after the
Cal
When this pin is high, all 32 channels acquire VIN simultaneously.
The acquisition time is then 45 µs (typ) and accuracy may be
reduced.
–13–
REV. 0
AD5532
MICROPROCESSOR INTERFACING
AD5532 to ADSP-21xx Interface
The ADSP-21xx family of DSPs are easily interfaced to the
AD5532 without the need for extra logic.
AD5532*
MC68HC11*
MISO
PC7
D
OUT
SYNC
SCK
MOSI
SCLK
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5532 on the falling edge of its SCLK. In
readback 16 bits of data are clocked out of the AD5532 on each
rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. DIN is ignored. The valid 14 bits of data will be
centered in the 16-bit RX register when using this configuration.
The SPORT control register should be set up as follows:
D
IN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD5532 to MC68HC11 Interface
AD5532 to PIC16C6x/7x
The PIC16C6x/7x Synchronous Serial Port (SSP) is config-
ured as an SPI Master with the Clock Polarity bit = 0. This is
done by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual. In
this example I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5532. This microcontroller
transfers only eight bits of data during each serial transfer opera-
tion; therefore, two or three consecutive read/write operations
are needed depending on the mode. Figure 22 shows the connec-
tion diagram.
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR
IRFS
ITFS
= RFSR = 1, Frame Every Word
= 0, External Framing Signal
= 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data Words (SHA Mode Write)
SLEN = 0111, 3× 8-Bit Data Words (DAC Mode Write)
SLEN = 1111, 16-Bit Data Words (Readback Mode)
PIC16C6x/7x*
AD5532*
SCK/RC3
SCLK
SDO/RC5
SDI/RC4
RA1
D
OUT
Figure 20 shows the connection diagram.
D
IN
SYNC
ADSP-2101/
ADSP-2103*
AD5532*
DR
D
*ADDITIONAL PINS OMITTED FOR CLARITY
OUT
TFS
RFS
DT
SYNC
Figure 22. AD5532 to PIC16C6x/7x Interface
AD5532 to 8051
D
IN
SCLK
SCLK
The AD5532 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode
0. In this mode serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 23 shows how the 8051 is
connected to the AD5532. Because the AD5532 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5532
requires its data with the MSB first. Since the 8051 outputs the
LSB first, the transmit routine must take this into account.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. AD5532 to ADSP-2101/ADSP-2103 Interface
AD5532 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5532, the MOSI output drives the serial data line (DIN)
of the AD5532 and the MISO input is driven from DOUT. The
SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5532, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the fall-
ing edge of SCK. Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. In order to trans-
mit 10-data bits in SHA mode it is important to left-justify the
data in the SPDR register. PC7 must be pulled low to start a
transfer. It is taken high and pulled low again before any further
read/write cycles can take place. A connection diagram is shown in
Figure 21.
8051*
AD5532*
TxD
RxD
SCLK
D
OUT
D
IN
P1.1
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. AD5532 to 8051 Interface
–14–
REV. 0
AD5532
POWER SUPPLY DECOUPLING
APPLICATION CIRCUITS
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5532 is mounted should be designed so that the analog and
digital sections are separated, and confined to certain areas of
the board. If the AD5532 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device. For supplies with
multiple pins (VSS, VDD, AVCC) it is recommended to tie those pins
together. The AD5532 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), like the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching.
AD5532 in a Typical ATE System
The AD5532 is ideally suited for use in Automatic Test Equipment.
Several DACs are required to control pin drivers, comparators,
active loads and signal timing. Traditionally, sample-and-hold
devices were used in this application.
The AD5532 has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated and there is no
need for extra filtering to remove glitches. Overall a higher level
of integration is achieved in a smaller area (see Figure 24).
PARAMETRIC
SYSTEM BUS
MEASUREMENT
UNIT
DAC
DAC
DAC
ACTIVE
LOAD
STORED
DATA
AND INHIBIT
PATTERN
DRIVER
The power supply lines of the AD5532 should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching signals
such as clocks should be shielded with digital ground to avoid
radiating noise to other parts of the board, and should never be
run near the reference inputs. A ground line routed between
the DIN and SCLK lines will help reduce crosstalk between them
(not required on a multilayer board as there will be a separate
ground plane, but separating the lines will help). It is essential
to minimize noise on VIN and REFIN lines.
DAC
FORMATTER
DUT
DAC
PERIOD
GENERATION
AND
DAC
DAC
DELAY
TIMING
COMPARE
REGISTER
COMPARATOR
SYSTEM BUS
DACs
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.
Figure 24. AD5532 in an ATE System
Typical Application Circuit (SHA Mode)
The AD5532 can be used to set up voltage levels on 32 channels
as shown in the circuit below. An AD780 provides the 3 V refer-
ence for the AD5532, and for the AD5541 16-bit DAC. A simple
3-wire interface is used to write to the AD5541. The DAC output
is buffered by an AD820. It is essential to minimize noise on VIN
and REFIN when laying out this circuit.
AV
CC
AV
CC
DV V
CC SS
V
DD
V
AD820
IN
AD5541*
REF
CS
DIN
V
0–31
OUT
AD5532*
SCLK
OFFS_IN
OFFS_OUT
REFIN
AD780*
V
OUT
SCLK DIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Typical Application Circuit
–15–
REV. 0
AD5532
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
74-Lead LFBGA
(BC-74)
0.394 (10.00) BSC
0.472 (12.00) BSC
A1
11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
0.472
(12.00)
BSC
0.394
BOTTOM
VIEW
F (10.00)
TOP VIEW
0.039
(1.00)
BSC
BSC
G
H
J
K
L
0.039 (1.00) BSC
DETAIL A
DETAIL A
0.067
(1.70)
MAX
0.033
(0.85)
MIN
0.010
(0.25)
MIN
CONTROLLING DIMENSIONS
ARE IN MILLIMETERS
0.024 (0.60)
BSC
SEATING
PLANE
BALL DIAMETER
–16–
REV. 0
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