EVAL-AD5570EB [ADI]
True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output DAC; 真正的精度， 16位12 V / 15 V ，串行输入电压输出DAC
| 型号： | EVAL-AD5570EB |
| 厂家： | 
ADI |
| 描述： | True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output DAC |
| 文件： | 总24页 (文件大小：1039K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
True Accuracy, 16-Bit ± 1ꢀ ꢁV± 1± ꢁ,
Serial Input ꢁoltage Output DAC
AD±±70
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Full 16-bit performance
1 LSB max INL and DNL
Output voltage range up to 14 V
V
V
DGND
SS
DD
AD5570
POWER-ON
RESET
On-board reference buffers, eliminating the need for a
negative reference
REFGND
R
Controlled output during power-on
Temperature range of −40°C to +85°C/−40°C to +125°C
Settling time of 10 µs to 0.003%
16-BIT
DAC
V
OUT
R
R
AGND
AGNDS
Clear function to 0 V
R
DAC REGISTER
SHIFT REGISTER
LDAC
Asynchronous update of outputs (
Power-on reset
pin)
REFIN
LDAC
POWER-DOWN
CONTROL LOGIC
PD
Serial data output for daisy chaining
Data readback facility
SDIN
SCLK
SDO
SYNC
CLR
APPLICATIONS
Industrial automation
Automatic test equipment
Process control
Figure 1.
Data acquisition systems
General-purpose instrumentation
GENERAL DESCRIPTION
purposes. Data readback allows the user to read the contents of
the DAC register via the SDO pin.
The AD5570 is a single 16-bit serial input, voltage output DAC
that operates from supply voltages of 1ꢀ V up to 15 V.
Integral linearity (INL) and differential nonlinearity (DNL) are
accurate to 1 LSB. During power-up (when the supply voltages
are changing), VOUT is clamped to 0 V via a low impedance path.
LDAC
Features on the AD5570 include
update the output of the DAC. The device also has a power-
PD
, which may be used to
down pin ( ), which allows the DAC to be put into a low
CLR
power state, and a
to 0 V.
pin that allows the output to be cleared
The AD5570 DAC comes complete with a set of reference
buffers. The reference buffers allow a single, positive reference
to be used. The voltage on REFIN is gained up and inverted
internally to give the positive and negative reference for the
DAC core. Having the reference buffers on-chip eliminates the
need for external components such as inverters, precision
amplifiers, and resistors, thereby reducing the overall solution
size and cost.
The AD5570 is available in a 16-lead SSOP package.
PRODUCT HIGHLIGHTS
1. 1 LSB maximum INL and DNL.
ꢀ. Buffered voltage output up to 1ꢁ V.
3. Output controlled during power-up.
ꢁ. On-board reference buffers.
The AD5570 uses a versatile 3-wire interface that is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP® interface standards.
Data is presented to the part in the format of a 16-bit serial
word. Serial data is available on the SDO pin for daisy-chaining
5. Wide temperature range of −ꢁ0°C to +1ꢀ5°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD±±70
TABLE OF CONTENTS
Specifications..................................................................................... 3
CLR
CLEAR (
)............................................................................. 17
PD
Standalone Timing Characteristics ................................................ ꢁ
Daisy Chaining and Readback Timing Characteristics............... 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
General Description....................................................................... 16
DAC Architecture....................................................................... 16
Reference Buffers........................................................................ 16
Serial Interface ............................................................................ 16
Transfer Function ....................................................................... 17
Power-Down ( ) ..................................................................... 17
Power-On Reset.......................................................................... 17
Serial Data Output (SDO)......................................................... 17
Applications Information.............................................................. 19
Typical Operating Circuit ......................................................... 19
Layout Guidelines....................................................................... ꢀ0
Opto-Coupler Interface............................................................. ꢀ0
Microprocessor Interfacing....................................................... ꢀ0
Evaluation Board........................................................................ ꢀꢀ
Outline Dimensions....................................................................... ꢀꢁ
Ordering Guide .......................................................................... ꢀꢁ
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD±±70
SPECIFICATIONS
VDD = +11.ꢁ V to +16.5 V; VSS = −11.ꢁ V to −16.5 V; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ and CL = ꢀ00 pF to GND; all
specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A/W Grade1, 2
B/Y Grade2
Typ3
Min
Typ3
Max
Min
Max
Parameter
Unit
Test Conditions/Comments
ACCURACY
Resolution
Monotonicity
Relative Accuracy (INL)
*
*
16
16
Bits
Bits
LSB
LSB
LSB
±0.6
±0.6
*
±0.4
±0.4
±0.3
±1
+1.25
+1
At 25°C
±2
*
−1
−1
Differential Nonlinearity
(DNL)
*
Negative Full-Scale Error
Full-Scale Error
Bipolar Zero Error
Gain Error
Gain Temperature
Coefficient4
*
*
*
*
*
*
*
*
*
*
±0.ꢀ
±1.ꢁ
±0.ꢀ
±1.ꢁ
0.25
±±.5
± 6
±±.5
±±.5
±1.5
mV
mV
mV
mV
ppm
FSR/°C
REFERENCE INPUT
Reference Input Range4
*
*
*
*
*
*
*
4
4
5
5
5
±
±0.1
V
V
µA
With ±11.4 V supplies
With ±16.5 V supplies
Input Current
OUTPUT CHARACTERISTICS4
Output Voltage Range
*
*
*
*
*
*
*
VSS + 1.4 V
VSS + 2.5 V
VDD − 1.4 V
VDD − 2.5 V
16
13
±
V
V
µs
µs
µs
V/µs
nV-s
±11.4 V supplies
±16.5 V supplies
At 16 bits to ±0.5 LSB
To 0.003%
512 LSB code change
Measured from 10% to ꢀ0%
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch
Impulse
*
*
*
*
*
12
10
6
6.5
15
±12 V suppliesꢂ 1 LSB change
around the major carry
Bandwidth
*
*
*
*
*
*
20
25
ꢁ5
0.35
0.5
12
kHz
mA
nV/Hz
Ω
nV-s
s
Short Circuit Current
Output Noise Voltage Density
DAC Output Impedance4
Digital Feedthrough
WARMUP TIME5
f = 1 kHzꢂ midscale loaded
*
0.5
LOGIC INPUTS
Input Current
*
*
±0.1
0.ꢁ
µA
V
V
VINH, Input High Voltage
VINL, Input Low Voltage
CIN, Input Capacitance4
LOGIC OUTPUTS
VOL, Output Low Voltage
Floating-State Output
Capacitance
*
2
*
*
3
ꢁ
pF
*
0.4
V
pF
ISINK = 1 mA
Rev. 0 | Page 3 of 24
AD±±70
A/W Grade1, 2
B/Y Grade2
Typ3
Min
Typ3
Max
Min
Max
Parameter
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD/VSS
IDD
ISS
Power-Down Current
Power Supply Sensitivity6
*
*
*
*
±11.4
±16.5
5
5
V
4
mA
mA
µA
VOUT unloaded
VOUT unloaded
VOUT unloaded
±15 V supplies ±10%ꢂ
full scale loaded
3.5
16
0.1
*
*
*
LSB/V
Power Dissipation
100
mW
VOUT unloaded
1 Asterisk (*) = specifications same as B/Y grade.
2 Temperature range: A and B = −40°C to +ꢁ5°Cꢂ W and Y = –40°C to +125°C.
3 Typical specifications at ±12 V/±15 V, 25°C.
4 Guaranteed by design.
5 Warmup time is required for the device to reach thermal equilibrium, thus achieving rated performance.
6 Sensitivity of negative full-scale error and positive full-scale error to VDD, VSS variations.
Rev. 0 | Page 4 of 24
AD±±70
STANDALONE TIMING CHARACTERISTICS
VDD = +1ꢀ V 5ꢂ, VSS = −1ꢀ V 5ꢂ or VDD = +15 V 10ꢂ, VSS = −15 V 10ꢂ; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ;
and CL = ꢀ00 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
10
100
35
35
10
35
0
45
45
0
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
t5
t6
t±
tꢁ
tꢀ
t10
t11
t12
t13
50
0
LDAC falling edge to SYNC falling edge (no update)
LDAC rising edge to SYNC rising edge (no update)
CLR pulse width
0
20
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to ꢀ0% of VDD) and timed from a voltage level of (VIL +VIH)/2.
t1
SCLK
t2
t3
t8
t4
t7
SYNC
SDIN
t6
t5
DB15
DB0
t9
t10
1
LDAC
t11
t12
2
LDAC
t13
CLR
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
2. SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 5 of 24
AD±±70
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
VDD = +1ꢀ V 5ꢂ, VSS = −1ꢀ V 5ꢂ or VDD = +15 V 10ꢂ, VSS = −15 V 10ꢂ; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ,
and CL = ꢀ00 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
2
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
500
200
200
10
35
0
45
45
0
t5
t6
t±
tꢁ
tꢀ
t10
50
1
t14
200
Data delay on SDO
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to ꢀ0% of VDD) and timed from a voltage level of (VIL +VIH)/2.
SDOꢂ RPULLUP = 5 kΩ, CL = 15 pF.
1 With CL = 0 pF, t15 = 100 ns.
t1
SCLK
t3
t2
t4
t7
t8
SYNC
t10
1
LDAC
t9
2
LDAC
t6
t5
DB0
(N+1)
DB15
(N+1)
DB15 (N)
DB0 (N)
SDIN
SDO
t14
DB15
(N+1)
DB15 (N)
DB0 (N)
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE
2. SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Daisy-Chaining Timing Diagram
Rev. 0 | Page 6 of 24
AD±±70
t1
SCLK
SYNC
t2
t3
t8
t4
t7
t6
t5
DB15
(N+1)
DB0
(N+1)
SDIN
DB15 (N)
DB0 (N)
t10
LDAC
t9
t14
DB15 (N)
DB14 (N)
DB0 (N)
SDO
Figure 4. Readback Timing Diagram
Rev. 0 | Page ± of 24
AD±±70
ABSOLUTE MAXIMUM RATINGS
TA = ꢀ5°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Parameter
Rating
VDD to AGND, AGNDS, DGND
VSS to AGND, AGNDS, DGND
AGND, AGNDS to DGND
REFGND to AGND, ADNDS
REFIN to AGND, AGNDS
REFIN to REFGND
Digital Inputs to DGND
VOUT to AGND, AGNDS
SDO to DGND
−0.3 V, +1± V
+0.3 V, −1± V
−0.3 V to +0.3 V
VSS − 0.3 V to VDD + 0.3 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to +1± V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +6.5 V
−40°C to +125°C
−40°C to +125°C
−40°C to +ꢁ5°C
−65°C to +150°C
Operating Temperature Range:
W, Y Grades
A, B Grades
Storage Temperature Range
Maximum Junction Temperature
(TJ Max)
150°C
16-Lead SSOP Package
Power Dissipation
θJA Thermal Impedance
Lead Temperature (Soldering 10 s)
IR Reflow, Peak Temperature
(TJ max – TA)/θJA
13ꢀ°C/W
300°C
230°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page ꢁ of 24
AD±±70
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16 REFGND
15 REFIN
SS
V
DD
CLR
LDAC
SYNC
SCLK
SDIN
SDO
14 REFGND
AD5570
13
V
OUT
TOP VIEW
12 AGNDS
11 AGND
10 PD
(Not to Scale)
9
DGND
Figure 5. 16-Lead SSOP Pin Configuration (RS-16)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VSS
VDD
CLR
Negative Analog Supply Voltage. −12 V ± 5% to −15 V ± 10% for specified performance.
Positive Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance.
Level Sensitive, Active Low Input. A falling edge of CLR resets VOUT to AGND. The contents of the registers are
untouched.
4
5
LDAC
SYNC
Active Low Control Input. Transfers the contents of the input register to the DAC register. LDAC may be tied
permanently low, enabling the outputs to be updated on the rising edge of SYNC.
Active Low Control Input. This is the frame synchronization signal for the data. When SYNC goes low, it powers
on the SCLK and SDIN buffers and enables the input shift register. Data is transferred in on the falling edges of
the following 16 clocks.
6
±
ꢁ
SCLK
SDIN
SDO
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can
be transferred at rates of up to ꢁ MHz.
Serial Data Input. This device has a 16-bit register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Data Output. Can be used for daisy chaining a number of devices together or for reading back the data in
the shift register for diagnostic purposes. This is an open-drain outputꢂ it should be pulled to logic high with an
external pull-up resistor of ~5 kΩ.
ꢀ
DGND
PD
Digital Ground. Ground reference for all digital circuitry.
Active Low Control Input. Allows the DAC to be put into a power-down state.
Analog Ground. Ground reference for all analog circuitry.
Analog Ground Sense. This is normally tied to AGND.
Analog Output Voltage.
This pin should be tied to 0 V.
Voltage Reference Input. This is internally buffered before being applied to the DAC. For bipolar ±10 V output
range, REFIN is 5 V.
10
11
12
13
14
15
AGND
AGNDS
VOUT
REFGND
REFIN
16
REFGND
This pin should be tied to 0 V.
Rev. 0 | Page ꢀ of 24
AD±±70
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Output Voltage Settling Time
Relative accuracy or integral nonlinearity is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function.
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change.
Monotonicity
Slew Rate
A DAC is monotonic, if the output either increases or remains
constant for increasing digital inputs. The AD5570 is monotonic
over its full operating temperature range.
The slew rate of a device is a limitation in the rate of change of
output voltage. The output slewing speed of a voltage-output
D/A converter is usually limited by the slew rate of the amplifier
used at its output. Slew rate is measured from 10ꢂ to 90ꢂ of the
output signal and is given in V/µs.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the amount of charge in-
jected into the analog output when the input codes in the DAC
register change state. It is specified as the area of the glitch in
nV-s and is measured when the digital input code changes by
1 LSB at the major carry transition, that is, from code 0x7FFF to
0x8000.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is
the deviation in slope of the DAC transfer characteristic from
the ideal.
Bandwidth
The reference amplifiers within the DAC have a finite band-
width to optimize noise performance. To measure it, a sine
wave is applied to the reference input (REFIN), with full-scale
code loaded to the DAC. The bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with changes in temperature. It is expressed in
ppm/°C.
Digital Feedthrough
Negative Full-Scale Error / Zero Scale Error
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
Negative full-scale error is the error in the DAC output voltage
when all 0s are loaded into the DAC latch. Ideally, the output
voltage, with all 0s in the DAC latch, should be −ꢀ VREF
.
is held high, while the CLK and SDIN signals are toggled.
SYNC
Full-Scale Error
It is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa.
Full-scale error is the error in the DAC output voltage when all
1s are loaded to the DAC latch. Ideally the output voltage, with
all 1s loaded into the DAC latch, should be ꢀ VREF − 1 LSB.
Power Supply Sensitivity
Bipolar Zero Error
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
Bipolar zero error is the deviation of the analog input from the
ideal half-scale output of 0.0000 V when the inputs are loaded
with 0x8000.
Rev. 0 | Page 10 of 24
AD±±70
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.6
0.4
0.2
T
= 25°C
T = 25°C
A
A
0.8
0.6
0.4
0.2
V
/V = ±15V
V
/V = ±12V
DD SS
DD SS
REFIN = 5V
REFIN = 5V
0
0
–0.2
–0.2
–0.4
–0.6
–0.4
–0.6
–0.8
–1.0
–0.8
–1.0
0
10k
20k
30k
CODE
40k
50k
60k
0
10k
20k
30k
CODE
40k
50k
60k
Figure 6. Integral Nonlinearity vs. Code, VDD/VSS
=
15 V
Figure 9. Differential Nonlinearity vs. Code, VDD/VSS
=
12 V
1.0
1.0
0.8
0.6
0.4
0.2
V
/V = ±15V
T
V
= 25°C
DD SS
A
0.8
0.6
REFIN = 5V
/V = ±15V
DD SS
REFIN = 5V
0.4
0.2
0
0
–0.2
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–1.0
–0.8
–1.0
–40
–20
0
20
40
60
80
100
120
0
10k
20k
30k
CODE
40k
50k
60k
TEMPERATURE (°C)
Figure 7. Differential Nonlinearity vs. Code, VDD/VSS
= 15 V
Figure 10. Integral Nonlinearity vs. Temperature, 15 V Supplies
1.0
1.0
T
= 25°C
A
V
/V = ±15V
DD SS
0.8
0.6
0.4
0.2
V
/V = ±12V
DD SS
0.8
0.6
REFIN = 5V
REFIN = 5V
0.4
0.2
0
0
–0.2
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–1.0
–0.8
–1.0
0
10k
20k
30k
CODE
40k
50k
60k
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 8. Integral Nonlinearity vs. Code, VDD/VSS
=
12 V
Figure 11. Differential Nonlinearity vs. Temperature, 15 V Supplies
Rev. 0 | Page 11 of 24
AD±±70
1.0
0.8
0.6
1.0
0.8
0.6
0.4
V
/V = ±12V
T = 25°C
A
REFIN = 5V
DD SS
REFIN = 5V
0.4
0.2
0
0.2
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
–40
–20
0
20
40
60
80
100
120
11.4
12.0
13.0
14.0
15.0
16.0 16.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 12. Integral Nonlinearity vs. Temperature, 12 V Supplies
Figure 15. Differential Nonlinearity vs. Supply Voltage
1.0
2.0
1.5
V
/V = ±12V
V
/V = ±12V
DD SS
DD SS
0.8
0.6
REFIN = 5V
T = 25°C
A
0.4
0.2
0
1.0
0.5
–0.2
–0.4
0
–0.6
–0.8
–1.0
–0.5
–1.0
–40
–20
0
20
40
60
80
100
120
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
Figure 13. Differential Nonlinearity vs. Temperature, 12 V Supplies
Figure 16. Integral Nonlinearity Error vs. Reference Voltage, 12 V Supplies
1.0
0.5
T
= 25°C
V
/V = ±12V
DD SS
A
0.8
0.6
0.4
0.4
0.3
REFIN = 5V
T = 25°C
A
0.2
0.1
0
0.2
0
–0.2
–0.4
–0.6
–0.1
–0.2
–0.3
–0.8
–1.0
–0.4
–0.5
11.4
12.0
13.0
14.0
15.0
16.0 16.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 14. Integral Nonlinearity vs. Supply Voltage
Figure 17. Differential Nonlinearity Error vs. Reference Voltage,
12 V Supplies
Rev. 0 | Page 12 of 24
AD±±70
10.0
7.5
5.0
4.5
V
/V = ±15V OR ±12V
= 25°C
T = 25°C
A
REFIN = 5V
DD SS
T
A
|I
|
|
DD
5.0
2.5
4.0
3.5
|I
SS
3.0
0
2.5
2.0
–2.5
–5.0
11.4
12.4
13.4
14.4
/V (V)
15.4
16.4
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
REFERENCE VOLTAGE (V)
DD SS
Figure 18. TUE Error vs. Reference Voltage
Figure 21. IDD/ISS vs.VDD/VSS
2.0
1.5
1.0
25
20
15
10
5
V
/V = ±15V
= 25°C
T = 25°C
A
REFIN = 5V
DD SS
T
A
|I
|
DD IN POWER-DOWN
0.5
0
–0.5
–1.0
–1.5
–2.0
|I
|
SS IN POWER-DOWN
0
11.4
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
12.4
13.4
14.4
/I (V)
15.4
16.4
REFERENCE VOLTAGE (V)
I
DD SS
Figure 19. Integral Nonlinearity Error vs. Reference Voltage, 15 V Supplies
Figure 22. IDD/ISS in Power-Down vs. Supply Voltage
1.0
0
–1
–2
V
/V = ±15V
= 25°C
V
/V = ±12V OR ±15V
DD SS
DD SS
0.8
0.6
0.4
0.2
0
T
REFIN = 5V
A
–3
–4
–5
–0.2
–6
–7
–0.4
–0.6
–8
–9
–0.8
–1.0
–10
–40
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
–20
0
20
40
60
80
100
120
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 20. Differential Nonlinearity Error vs. Reference Voltage,
15 V Supplies
Figure 23. Offset Error vs. Temperature
Rev. 0 | Page 13 of 24
AD±±70
0
–1
–2
11.0
10.0
REFIN = 5V
8.0
V
/V = ±15V
DD SS
6.0
4.0
–3
–4
–5
2.0
V
/V = ±12V
DD SS
0
–6
–7
–8
–9
–2.0
–4.0
1µs/DIV
V
V
= +15V
= –15V
DD
–6.0
–8.0
SS
REFIN = 5V
= 25°C
T
A
–10.0
–10
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 24. Bipolar Zero Error vs. Temperature
Figure 27. Settling Time
40
10
0
REFIN = 5V
T
= 25°C
A
REFIN = 5V
35
30
6
V
/V = ±12V
DD SS
4
2
0
25
V
/V = ±15V
DD SS
20
15
10
5
V
/V = ±15V
DD SS
–2
–4
–6
–8
V
/V = ±12V
DD SS
0
–10
–40
0
1
2
3
4
5
6
7
8
9 9.4
–20
0
20
40
60
80
100
120
CAPACITANCE (nF)
TEMPERATURE (°C)
Figure 25. Gain Error vs. Temperature
Figure 28.14-Bit Settling Time vs. Load Capacitance
4.15
10.0000
9.9997
T
= 25°C
T
= 25°C
A
A
REFIN = 5V
REFIN = 5V
4.10
4.05
9.9994
9.9991
9.9988
9.9985
15V SUPPLIES
DECREASING
4.00
3.95
9.9982
9.9979
15V SUPPLIES
INCREASING
9.9976
9.9973
9.9970
9.9967
9.9964
9.9961
DECREASING
INCREASING
3.90
3.85
3.80
3.75
12V SUPPLIES
12V SUPPLIES
9.9958
9.9955
9.9952
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–10
–8
–6
–4
–2
0
2
4
6
8
10
V
(V)
SOURCE CURRENT (mA)
SINK CURRENT (mA)
LOGIC
SYNC
Figure 26. Supply Current vs. Logic Input Current for SCLK,
LDAC
, SDIN,
Figure 29. Source and Sink Capability of Output Amplifier
with Full Scale Loaded
and
Increasing and Decreasing
Rev. 0 | Page 14 of 24
AD±±70
–9.9973
T
= 25°C
V
V
= +15V
= –15V
A
DD
SS
REFIN = 5V
–9.9976
–9.9979
MIDSCALE LOADED
20µV/DIV
V
= 0V
REFIN
12V SUPPLIES
–9.9982
–9.9985
–9.9988
–9.9991
–9.9994
–9.9997
–10.0000
15V SUPPLIES
CH1 20µV/DIV
M 1.0Ωms 500kS/s 20µs/PT
A CH1 0.0V
–10
–8
–6
–4
–2
0
2
4
6
8
10
SOURCE CURRENT (mA)
SINK CURRENT (mA)
Figure 30. Source and Sink Capability of Output Amplifier
with Zero Scale Loaded
Figure 33. Peak-to-Peak Noise (100 kHz Bandwidth)
–0.05
V
V
= +15V
= –15V
DD
SS
REFIN = 5V
= 25°C
RAMP TIME = 100µs
–0.06
–0.07
–0.08
–0.09
–0.10
T
A
V
DD
V
SS
V
V
V
= +15V
= –15V
OUT
DD
SS
REFIN = 5V
= 25°C
T
A
7 FFF
→ 8000H
V /V = 10V/DIV
DD SS
V
= 10mV/DIV
OUT
1µs/DIV
100µs/DIV
Figure 31. Major Code Transition Glitch Energy, 15 V Supplies
Figure 34. VOUT vs. VDD/VSS on Power-Up
–0.022
–0.027
–0.032
–0.037
–0.042
–0.047
–0.052
–0.057
–0.062
V
V
= +12V
= –12V
DD
SS
REFIN = 5V
= 25°C
T
–0.067
–0.072
A
8000 → 7FFFH
1µs (DIV)
Figure 32. Major Code Transition Glitch Energy, 12 V Supplies
Rev. 0 | Page 15 of 24
AD±±70
GENERAL DESCRIPTION
The AD5570 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 11.ꢁ V to 16.5 V, and has a
buffered voltage output of up to 13.6 V. Data is written to the
AD5570 in a 16-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy
chaining or readback.
SERIAL INTERFACE
The AD5570 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 10 MHz and is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure ꢀ.
The AD5570 incorporates a power-on reset circuit, which
ensures that the DAC output powers up to 0 V. The device also
has a power-down pin, which reduces the typical current
consumption to 16 µA.
Upon power-up, the input shift register and DAC register are
loaded with midscale (0x8000). The DAC coding is straight
binary; all 0s produce an output of −ꢀ VREF; all 1s produce an
output of +ꢀ VREF − 1 LSB.
DAC ARCHITECTURE
The DAC architecture of the AD5570 consists of a 16-bit
current-mode segmented R-ꢀR DAC. The simplified circuit
diagram for the DAC section is shown in Figure 35.
The
input is a level-triggered input that acts as a frame
SYNC
The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
the 15 matched resistors to either AGND or IOUT. The remain-
ing 1ꢀ bits of the data word drive switches S0 to S11 of the
1ꢀ-bit R-ꢀR ladder network.
synchronization signal and chip enable.
must frame the
SYNC
serial word being loaded into the device. Data can be trans-
ferred into the device only while is low. To start the serial
SYNC
should be taken low, observing the
data transfer,
SYNC
to SCLK falling edge setup time, tꢁ. After
minimum
SYNC
R
R
R
goes low, serial data on SDIN is shifted into the device’s
SYNC
input shift register on the falling edges of SCLK.
taken high after the falling edge of the 16th SCLK pulse,
V
ref
may be
SYNC
2R
2R
2R
2R
2R
2R
2R
observing the minimum SCLK falling edge to
time, t7.
rising edge
SYNC
R/8
E15
E14
E1
S0
S11
S10
After the end of the serial data transfer, data is automatically
transferred from the input shift register to the input register of
the DAC.
V
OUT
AGND
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
12 BIT R-2R LADDER
When data has been transferred into the input register of the
DAC, the DAC register and DAC output can be updated by
taking LDAC low while SYNC is high.
Figure 35. DAC Ladder Structure
REFERENCE BUFFERS
The AD5570 operates with an external reference. The reference
input (REFIN) has an input range of up to 7 V. This input
voltage is then used to provide a buffered positive and negative
reference for the DAC core. The positive reference is given by
LDAC
Load DAC Input (
)
When data has been transferred into the input register of the
DAC, there are two ways in which the DAC register and DAC
output can be updated. Depending on the status of both
SYNC
+ VREF = 2 ×VREFIN
and
, one of two update modes is selected.
LDAC
while the negative reference to the DAC core is given by
LDAC
Synchronous
being clocked into the input shift register. The DAC output is
updated when is taken high. The update here occurs on
: In this mode,
is low while data is
LDAC
−VREF = 2 ×VREFIN
SYNC
the rising edge of
.
SYNC
These positive and negative reference voltages define the DAC
output range.
Rev. 0 | Page 16 of 24
AD±±70
LDAC
CLEAR (CLR)
Asynchronous
: In this mode,
is high while data is
LDAC
being clocked in. The DAC output is updated by taking
LDAC
has been taken high. The update now
is an active low digital input that allows the output to be
CLR
low any time after
SYNC
cleared to 0 V. When the
output stays at 0 V until
signal is brought back high, the
CLR
occurs on the falling edge of
.
LDAC
is brought low. The relationship
LDAC
between
and
is explained further in Table 7.
CLR
LDAC
Figure 36 shows a simplified block diagram of the input loading
circuitry.
Table 7. Relationships among
,
, and
LDAC
PD CLR
PD CLR LDAC Comments
OUTPUT
I/V AMPLIFIER
0
1
x
x
PD has priority over LDAC and CLR. The
output remains at 0 V through an internal
20 kΩ resistor. It is still possible to address
both the input register and DAC register
when the AD55±0 is in power-down.
Data is written to the input register and
DAC register. CLR has higher priority over
LDACꢂ therefore, the output is at 0 V.
16-BIT
DAC
V
REFIN
V
OUT
LDAC
SYNC
DAC
REGISTER
0
0
INPUT SHIFT
REGISTER
SDIN
SDO
1
1
1
0
1
1
1
0
1
Data is written to the input register only.
The output is at 0 V and remains at 0 V,
when CLR is taken back high.
Figure 36. Simplified Serial Interface Showing Input Loading Circuitry
Data is written to the input register and
the DAC register. The output is driven to
the DAC level.
Data is written to the input register only.
The output of the DAC register is
unchanged.
TRANSFER FUNCTION
Table 6 shows the ideal input code to output voltage relationship
for the AD5570.
Table 6. Binary Code Table
Digital Input
Analog Output
MSB
1111
1000
1000
0111
0000
LSB
VOUT
POWER-DOWN (PD)
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+2 VREF × (32,±6±/32,±6ꢁ)
+2 VREF × (1/32,±6ꢁ)
0 V
−2 VREF × (1/32,±6ꢁ)
−2 VREF
The power-down pin allows the user to place the AD5570 into a
power-down mode. When in this mode, power consumption is
at a minimum; the device consumes only 16 µA typically.
POWER-ON RESET
The AD5570 contains a power-on reset circuit that controls the
output during power-up and power-down. This is useful in
applications where the known state of the output of the DAC
during power-up is important. On power-up and power-down,
the output of the DAC, VOUT, is held at AGND.
The output voltage expression is given by
VOUT = −ꢀVREFIN + ꢁ × VREFIN [D / 65536]
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFIN is the reference voltage available at the REFIN pin.
Rev. 0 | Page 1± of 24
AD±±70
68HC11*
MOSI
AD5570*
SERIAL DATA OUTPUT (SDO)
SDIN
The serial data output (SDO) is the internal shift register’s
output. For the AD5570, SDO is an internal pull-down only; an
external pull-up resistor of ~5 kΩ to external logic high is
required. SDO pull-down is disabled when the device is in
power-down, thus saving current.
SCK
PC7
PC6
SCLK
SYNC
LDAC
V
LOGIC
MISO
SDO
R
R
R
The availability of SDO allows any number of AD5570s to be
daisy-chained together. It also allows for the contents of the
DAC register, or any number of DACs daisy-chained together,
to be read back for diagnostic purposes.
SDIN
AD5570*
SCLK
SYNC
LDAC
Daisy Chaining
This mode of operation is designed for multi-DAC systems,
where several AD5570s may be connected in cascade as shown
in Figure 37. This is done by connecting the control inputs in
parallel and then daisy chaining the SDIN and SDO I/Os of
each device. An external pull-up resistor of ~5 kΩ on SDO is
required when using the part in daisy-chain mode.
SDO
SDIN
AD5570*
SCLK
SYNC
LDAC
As before, when
goes low, serial data on SDIN is shifted
SYNC
into the input shift register on the falling edge of SCLK. If more
than 16 clock pulses are applied, the data ripples out of the shift
resister and appears on the SDO line. By connecting this line to
the SDIN input on the next AD5570 in the chain, a multi-DAC
interface may be constructed.
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. Daisy Chaining Using the AD5570
One data transfer cycle of 16 SCLK pulses is required for each
DAC in the system. Therefore, the total number of clock cycles
must equal 16 N, where N is the total number of devices in the
chain. The first data transfer cycle written into the chain
appears at the last DAC in the system on the final data transfer
cycle.
Readback
The AD5570 allows the data contained in the DAC register to
be read back, if required. As with daisy chaining, an external
pull-up resistor of ~5 kΩ on SDO is required. The data in the
DAC register is available on SDO on the falling edges of SCLK
when
is low. On the sixteenth SCLK edge, SDO is
SYNC
updated to repeat SDIN with a delay of 16 clock cycles.
When the serial transfer to all devices is complete,
should
SYNC
be taken high. This prevents any further data from being
clocked into the devices.
To read back the contents of the DAC register without writing
to the part,
should be taken low while LDAC is held high.
SYNC
A continuous SCLK source may be used, if it can be arranged
that is held low for the correct number of clock cycles.
Daisy-chaining readback is also possible through the SDO pin
of the last device in the DAC chain, because the DAC data
passes through the DAC chain with the appropriate latency.
SYNC
Alternatively, a burst clock containing the exact number of
clock cycles may be used and taken high some time later.
SYNC
The outputs of all the DACs in the system can be updated
simultaneously using the signal.
LDAC
Rev. 0 | Page 1ꢁ of 24
AD±±70
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
1
2
3
4
5
6
7
8
V
V
REFGND 16
REFIN 15
SS
DD
Figure 38 shows the typical operating circuit for the AD5570.
The only external component needed for this precision 16-bit
DAC is a single external positive reference. Because the device
incorporates reference buffers, it eliminates the need for a
negative reference, external inverters, precision amplifiers, and
resistors. This leads to an overall saving in both cost and board
space.
CLR
REFGND 14
LDAC
SYNC
SCLK
SDIN
SDO
V
13
OUT
AD5570
AGNDS 12
AGND 11
PD 10
2
3
6
OP177*
DGND
9
In the circuit below, VDD and VSS are both connected to 15 V,
but VDD and VSS can operate supplies from +11.ꢁ V to +16.5 V.
In Figure 38, AGNDS is connected to AGND, but the option of
Force/Sense is included on this device, if required by the user.
(OTHER CONNECTIONS OMITTED
FOR CLARITY)
*FOR OPTIMUM SETTLING TIME PERFORMANCE,
THE AD845 IS RECOMMENDED.
Figure 39. Driving AGND and AGNDS Using a Force/Sense Amplifier
0.1µF
–15V
10µF
1
2
3
4
5
6
7
8
V
V
REFGND 16
REFIN 15
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long term drift, and output voltage noise.
SS
DD
+15V
0.1µF
ADR435
10µF
CLR
REFGND 14
LDAC
SYNC
SCLK
SDIN
SDO
V
13
V
LDAC
SYNC
SCLK
SDIN
SDO
OUT
OUT
AD5570
AGNDS 12
AGND 11
PD 10
Initial accuracy on the output voltage of an external reference
could lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
specification is preferred. Also, choosing a reference with an
output trim adjustment, such as the ADRꢁꢀ5, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjust-
ment can also be used at temperature to trim out any error.
DGND
9
5kΩ
5V
Figure 38. Typical Operating Circuit
Long term drift (LTD) is a measure of how much the reference
drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
Force/Sense of AGND
Because of the extremely high accuracy of this device, system
design issues such as grounding and contact resistance are very
important. The AD5570, with 10 V output, has an LSB size of
305 µV. Therefore, series wiring and connector resistances of
very small values could cause voltage drops of an LSB. For this
reason, the AD5570 offers a Force/Sense output configuration.
The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight tempera-
ture coefficient specification should be chosen to reduce the
dependence of the DAC output voltage on ambient conditions.
Figure 39 shows how to connect the AD5570 to the Force/Sense
amplifier. Where accuracy of the output is important, an ampli-
fier such as the OP177 is ideal. The OP177 is ultraprecise with
offset voltages of 10 µV maximum at room temperature, and
offset drift of 0.1 µV/°C maximum. Alternative recommended
amplifiers are the OP1177 and the OP77. For applications where
optimization of the circuit for settling time is needed, the
AD8ꢁ5 is recommended.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important. Preci-
sion voltage references such as the ADRꢁ35 (XFET design)
produce low output noise in the 0.1 Hz to 10 Hz region.
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise.
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5570,
thought should be given to the selection of a precision voltage
reference. The AD5570 has just one reference input, REFIN.
This voltage on REFIN is used to provide a buffered positive
and negative reference for the DAC core. Therefore, any error in
the voltage reference is reflected in the output of the device.
Rev. 0 | Page 1ꢀ of 24
AD±±70
Table 8. Partial List of Precision References Recommended
for Use with the AD5570
OPTO-COUPLER INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD5570
makes it ideal for opto-isolated interfaces, because the number
of interface lines is kept to a minimum. Figure ꢁ0 shows a
ꢁ-channel isolated interface to the AD5570. To reduce the
number of opto-isolators, if the simultaneous updating of the
DAC is not required, the LDAC pin may be tied permanently
low. The DAC can then be updated on the rising edge of SYNC.
Initial
Accuracy
(mV max) (ppm typ)
Long-Term
Drift
Temp Drift
(ppm/
°C max)
0.1 Hz to
10 Hz Noise
(µV p-p typ)
Part No.
ADR435
ADR425
ADR021
ADR3ꢀ5
AD5ꢁ6
30
50
50
50
15
3
3.4
3.4
15
5
± 6
± 6
±5
±6
±2.5
3
3
25
10
4
1Available in SC±0 package.
LAYOUT GUIDELINES
V
CC
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5570 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5570 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
µCONTROLLER
CONTROL OUT
TO LDAC
TO SYNC
TO SCLK
TO SDIN
SYNC OUT
SERIAL CLOCK OUT
The AD5570 should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply located as close to the pack-
age as possible, ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESI) such as the common ceramic types,
which provide a low impedance path to ground at high frequen-
cies to handle transient currents due to internal logic switching.
SERIAL DATA OUT
OPTO-COUPLER
Figure 40. Opto-Isolated Interface
The power supply lines of the AD5570 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board, which has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line, because it
couples through to the DAC output.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5570 is via a serial bus
that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5570 requires a 16-bit
data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in, or it may be done
under the control of
may be read using the readback function.
. The contents of the DAC register
LDAC
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feed through the board. A microstrip
technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane, while signal traces are
placed on the solder side.
Rev. 0 | Page 20 of 24
AD±±70
V
AD5570 to MC68HC11 Interface
LOGIC
AD5570*
8xC51*
Figure ꢁ1 shows an example of a serial interface between the
AD5570 and the MC68HC11 microcontroller. The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1), clock polarity bit (CPOL = 0), and
the clock phase bit (CPHA = 1). The SPI is configured by
writing to the SPI control register (SPCR)—see the 68HC11
User Manual. SCK of the 68HC11 drives the SCLK of the
AD5570, the MOSI output drives the serial data line (DIN) of
the AD5570, and the MISO input is driven from SDO. The
RxD
SDO
DIN
TxD
SCLK
P3.3
P3.4
SYNC
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
is driven from one of the port lines, in this case PC7.
SYNC
Figure 42. AD5570 to 8051 Interface
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result, no glue
logic is required between this DAC and the microcontroller
interface.
When data is being transmitted to the AD5570, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 16-bit word, PC7 is not brought high
until the second 8-bit word has been transferred to the DAC’s
input shift register.
The 8051 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 16-bit word, SYNC (P3.3) must be left low after the
first eight bits are transferred. After the second byte has been
transferred, the P3.3 line is taken high. The DAC may be
MC68HC11*
AD5570*
MISO
SDO
updated using
via P3.ꢁ of the 8051.
LDAC
MOSI
SCLK
PC7
DIN
AD5570 to ADSP2101/ADSP2103
SCLK
An interface between the AD5570 and the ADSPꢀ101/
ADSPꢀ103 is shown in Figure ꢁ3. The ADSPꢀ101/ADSPꢀ103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSPꢀ101/ADSPꢀ103 are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length.
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5570 to MC68HC11 Interface
is controlled by the PC6 port output. The DAC can be
LDAC
updated after each ꢀ-byte transfer by bringing
low. This
LDAC
example does not show other serial lines for the DAC. If
were used, it could be controlled by port output PC5, for
example.
CLR
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
AD5570 to 8051 Interface
output is updated using the
pin via the DSP. Alterna-
LDAC
The AD5570 requires a clock synchronized to the serial data.
For this reason, the 8051 must be operated in Mode 0. In this
mode, serial data enters and exits through RxD, and a shift clock
is output on RxD.
tively, the
input could be tied permanently low, and then
LDAC
the update takes place automatically when
is taken high.
TFS
ADSP2101/
ADSP2103*
AD5570*
P3.3 and P3.ꢁ are bit programmable pins on the serial port and
DR
SDO
are used to drive
and
, respectively.
SYNC
LDAC
DT
DIN
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user must ensure that the data in the SBUF
register is arranged correctly, because the DAC expects MSB
first.
SCLK
SCLK
TFS
SYNC
LDAC
RFS
FO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 43. AD5570 to ADSP2101/ADSP2103 Interface
Rev. 0 | Page 21 of 24
AD±±70
AD5570 to PIC16C6x/7x
EVALUATION BOARD
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit set to 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
The AD5570 comes with a full evaluation board to aid designers
in evaluating the high performance of the part with a minimum
of effort. All that is required with the evaluation board is a
power supply, a PC, and an oscilloscope.
this example, I/O port RA1 is being used to pulse
and
SYNC
The AD5570 evaluation kit includes a populated, tested AD5570
printed circuit board. The evaluation board interfaces to the
parallel interface of the PC. Software is available with the
evaluation board, which allows the user to easily program the
AD5570. A schematic of the evaluation board is shown in
Figure ꢁ5. The software runs on any PC that has Microsoft
Windows® 95/98/ME/ꢀ000 installed.
enable the serial port of the AD5570. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
needed. Figure ꢁꢁ shows the connection diagram.
PIC16C6x/7x*
AD5570*
SDI/RC4
SDO/RC5
SCLK/RC3
RA1
SDO
An application note is available that gives full details on
operating the evaluation board.
DIN
SCLK
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. AD5570 to PIC16C6x/7x Interface
Rev. 0 | Page 22 of 24
AD±±70
0 3 7 6 0 - 0 - 0 4 3
L K 5
F
R E
R E F I N
N D R E F G
N D R E F G
N D A G
N D S A G
V D D
V S S
R E F I N
G N
D
G D N
D
V D D
L K 4
Figure 45. Evaluation Board Schematic
Rev. 0 | Page 23 of 24
AD±±70
OUTLINE DIMENSIONS
6.50
6.20
5.90
16
9
8
5.60
5.30
5.00
8.20
7.80
7.40
1
1.85
1.75
1.65
2.00 MAX
0.25
0.09
8°
4°
0°
0.95
0.75
0.55
0.38
0.22
0.05 MIN
SEATING
PLANE
0.65
BSC
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-150AC
Figure 46. 16-Lead Shrink Small Outline Package [SSOP]
(RS-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD55±0ARS
AD55±0ARS-REEL
AD55±0ARS-REEL±
AD55±0BRS
AD55±0BRS-REEL
AD55±0BRS-REEL±
AD55±0WRS
AD55±0WRS-REEL
AD55±0WRS-REEL±
AD55±0YRS
AD55±0YRS-REEL
AD55±0YRS-REEL±
Eval-AD55±0EB
Temperature Range
Package Description
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
Evaluation Board
Package Option
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
−40 °C to +ꢁ5 °C
−40 °C to +ꢁ5 °C
−40 °C to +ꢁ5 °C
−40 °C to +ꢁ5 °C
−40 °C to +ꢁ5 °C
−40 °C to +ꢁ5 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03760–0–11/03(0)
Rev. 0 | Page 24 of 24
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明