EVAL-AD5620EB [ADI]
Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23; 单， 12位/ 14位/ 16位属于nanoDAC用5ppm的/ C片内基准采用SOT -23
| 型号： | EVAL-AD5620EB |
| 厂家： | 
ADI |
| 描述： | Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 |
| 文件： | 总24页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single, 12-/14-/16-Bit nanoDAC™ with
5 ppm/°C On-Chip Reference in SOT-23
AD5620/AD5640/AD5660
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
V
DD
Low power, single nanoDACs
AD5660: 16 bits
AD5640: 14 bits
REFOUT
GND
1.25/2.5V
REF
AD5620/AD5640/AD5660
POWER-ON
RESET
V
V
FB
AD5620: 12 bits
12-bit accuracy guaranteed
On-chip, 1.25 V/2.5 V, 5 ppm/°C reference
Tiny 8-lead SOT-23/MSOP packages
Power-down to 480 nA @ 5 V, 200 nA @ 3 V
3 V/5 V single power supply
Guaranteed 16-bit monotonic by design
Power-on reset to zero/midscale
3 power-down functions
REF(+)
OUTPUT
BUFFER
DAC
REGISTER
OUT
16-BIT
DAC
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
SYNC SCLK DIN
Figure 1.
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5620/AD5640/AD5660, members of the nanoDAC
family of devices, are low power, single, 12-/14-/16-bit, buffered
voltage-out DACs and are guaranteed monotonic by design.
The AD5620/AD5640/AD5660-1 parts include an internal,
1.25 V, 5 ppm/°C reference, giving a full-scale output voltage
range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include
an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output
voltage range of 5 V. The reference associated with each part is
available at the VREFOUT pin.
PRODUCT HIGHLIGHTS
1. 12-/14-/16-bit nanoDAC—12-bit accuracy guaranteed.
2. On-chip, 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 8-lead SOT-23 and 8-lead MSOP packages.
4. Power-on reset to 0 V or midscale.
The parts incorporate a power-on reset circuit to ensure that the
DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2)
or midscale (AD5620-3 and AD5660-3) and remains there until
a valid write takes place. The parts contain a power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
while in power-down mode. The power consumption is
2.5 mW at 5 V, reducing to 1 μW in power-down mode.
5. 10 μs settling time.
RELATED DEVICE
Part No.
Description
AD5662
2.7 V to 5.5 V, 16-bit DAC in SOT-23, external
reference
The AD5620/AD5640/AD5660 on-chip precision output
amplifier allows rail-to-rail output swing to be achieved. For
remote sensing applications, the output amplifier’s inverting
input is available to the user. The AD5620/AD5640/AD5660 use
a versatile 3-wire serial interface that operates at clock rates up
to 30 MHz and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5620/AD5640/AD5660
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 17
Serial Interface............................................................................ 17
Input Shift Register .................................................................... 18
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Related Device................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5620/AD5640/AD5660-2-3 .................................................. 3
AD5620/AD5640/AD5660-1...................................................... 5
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
D/A Section................................................................................. 17
Resistor String............................................................................. 17
Internal Reference ...................................................................... 17
Interrupt .......................................................................... 18
SYNC
Power-On Reset.......................................................................... 19
Power-Down Modes .................................................................. 19
Microprocessor Interfacing....................................................... 19
Applications..................................................................................... 21
Using an REF19x as a Power Supply for the
AD5620/AD5640/AD5660 ....................................................... 21
Bipolar Operation Using the AD5660..................................... 21
Using the AD5660 as an Isolated, Programmable,
4 to 20 mA Process Controller ................................................. 21
Using the AD5620/AD5640/AD5660
with a Galvanically Isolated Interface...................................... 22
Power Supply Bypassing and Grounding................................ 22
Outline Dimensions....................................................................... 23
AD5620 Ordering Guide........................................................... 23
AD5640 Ordering Guide........................................................... 24
AD5660 Ordering Guide........................................................... 24
REVISION HISTORY
9/05—Rev. 0 to Rev. A
Changes to Specifications................................................................ 5
Changes to Outline Dimensions................................................... 23
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5620/AD5640/AD5660
SPECIFICATIONS
AD5620/AD5640/AD5660-2-3
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE2
A Grade1 B Grade1 C Grade1 Unit
Conditions/Comments
AD5660
Resolution
16
±32
±1
16
±16
±1
16
±16
±1
Bits min
LSB max
LSB max
Relative Accuracy
Differential Nonlinearity
AD5640
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
±±
±1
14
±4
±1
14
±4
±1
Bits min
LSB max
LSB max
Relative Accuracy
Differential Nonlinearity
AD5620
Resolution
12
±6
±1
2
12
±1
±1
2
12
±1
±1
2
Bits min
LSB max
LSB max
mV typ
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Guaranteed monotonic by design
All 0s loaded to DAC register
10
10
10
mV max
mV max
% FSR typ
% FSR max
% FSR max
μV/°C typ
ppm typ
dB typ
Offset Error
±10
−0.15
−1
±1.5
±2
±10
−0.15
−1
±1.5
±2
±10
−0.15
−1
±1.5
±2
Full-Scale Error
All 1s loaded to DAC register
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS3
Output Voltage Range
±2.5
−75
±2.5
−75
±2.5
−75
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
0
0
0
V min
VDD
±
10
1.5
2
VDD
±
10
1.5
2
VDD
±
10
1.5
2
V max
μs typ
μs max
V/μs typ
nF typ
Output Voltage Settling Time
¼ to ¾ scale change settling to ±2 LSB
RL = 2 kΩ; 0 pF < CL < 200 pF
¼ to ¾ scale
Slew Rate
Capacitive Load Stability
RL = ∞
10
±0
45
5
0.1
0.5
30
5
10
±0
45
5
0.1
0.5
30
5
10
±0
45
5
0.1
0.5
30
5
nF typ
RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
nV/√Hz typ
μV p-p typ
nV-s typ
nV-s typ
Ω typ
DAC code = midscale, 10 kHz
DAC code = midscale
1 LSB change around major carry
mA typ
μs typ
VDD = 5 V
Power-Up Time
Coming out of power-down mode; VDD = 5 V
REFERENCE OUTPUT
Output Voltage
2.495
2.505
±10
2.495
2.505
±10
2.495
2.505
±5
±20
2.±
V min
V max
ppm/°C typ
ppm/°C max
kΩ typ
At ambient
Reference TC3
Output Impedance
2.±
2.±
Rev. A | Page 3 of 24
AD5620/AD5640/AD5660
Parameter
LOGIC INPUTS3
A Grade1 B Grade1 C Grade1 Unit
Conditions/Comments
Input Current
±2
0.±
2
±2
0.±
2
±2
0.±
2
μA max
V max
V min
All digital inputs
VDD = 5 V
VDD = 5 V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
3
3
3
pF typ
4.5
5.5
4.5
5.5
4.5
5.5
V min
V max
All digital inputs at 0 V or VDD
DAC active and excluding load current
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
0.55
1
0.55
1
0.55
1
mA typ
mA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
0.4±
1
0.4±
1
0.4±
1
μA typ
μA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
1 Temperature range is −15°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 12± to Code 16256); AD5620 (Code 32 to Code 4064). Output
unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to VDD.
3 Guaranteed by design and characterization; not production tested.
Rev. A | Page 4 of 24
AD5620/AD5640/AD5660
AD5620/AD5640/AD5660-1
VDD1 = 2.7 V to 3.3 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE3
A Grade2 B Grade2 C Grade2 Unit
Conditions/Comments
AD5660
Resolution
16
±32
±1
16
±16
±1
16
±16
±1
Bits min
LSB max
LSB max
Relative Accuracy
Differential Nonlinearity
AD5640
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
±±
±1
14
±4
±1
14
±4
±1
Bits min
LSB max
LSB max
Relative Accuracy
Differential Nonlinearity
AD5620
Resolution
12
±6
±1
2
12
±1
±1
2
12
±1
±1
2
Bits min
LSB max
LSB max
mV typ
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Guaranteed monotonic by design
All 0s loaded to DAC register
±
±9
±
±9
±
±9
mV max
mV max
% FSR typ
% FSR max
% FSR max
μV/°C typ
ppm typ
dB typ
Offset Error
Full-Scale Error
±0.15
±0.±5
±0.±5
±2
±2.5
−60
±0.15
±0.±5
±0.±5
±2
±2.5
−60
±0.15
±0.±5
±0.±5
±2
±2.5
−60
All 1s loaded to DAC register
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS4
Output Voltage Range
Of FSR/°C
DAC code = midscale; VDD = 3 V ± 10%
0
0
V min
VDD
±
10
1.5
2
VDD
±
10
1.5
2
VDD
±
10
1.5
2
V max
μs typ
μs max
V/μs typ
nF typ
Output Voltage Settling Time
¼ to ¾ scale change settling to ±2 LSB
RL = 2 kΩ; 0 pF < CL < 200 pF
¼ to ¾ scale
Slew Rate
Capacitive Load Stability
RL = ∞
10
±0
20
5
0.1
0.5
30
5
10
±0
20
5
0.1
0.5
30
5
10
±0
20
5
0.1
0.5
30
5
nF typ
RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
nV/√Hz typ
μV p-p typ
nV-s typ
nV-s typ
Ω typ
DAC code = midscale, 10 kHz
DAC code = midscale
1 LSB change around major carry
mA typ
μs typ
VDD = 3 V
Power-Up Time
Coming out of power-down mode; VDD = 3 V
REFERENCE OUTPUT
Output Voltage
1.247
1.253
±10
1.247
1.253
±10
1.247
1.253
±5
±25
2.±
V min
V max
ppm/°C typ
ppm/°C max
kΩ typ
At ambient
Reference TC4
Output Impedance
2.±
2.±
Rev. A | Page 5 of 24
AD5620/AD5640/AD5660
Parameter
LOGIC INPUTS4
A Grade2 B Grade2 C Grade2 Unit
Conditions/Comments
Input Current
±1
0.±
2
±1
0.±
2
±1
0.±
2
μA max
V max
V min
All digital inputs
VDD = 3 V
VDD = 3 V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
3
3
3
pF max
2.7
3.3
2.7
3.3
2.7
3.3
V min
V max
All digital inputs at 0 V or VDD
DAC active and excluding load current
IDD (Normal Mode)
VDD = 2.7 V to 3.3 V
VDD = 2.7 V to 3.3 V
IDD (All Power-Down Modes)
VDD = 2.7 V to 3.3 V
VDD = 2.7 V to 3.3 V
0.55
0.65
0.55
0.65
0.55
0.65
mA typ
mA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
0.2
0.25
0.2
0.25
0.2
0.25
μA typ
μA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
1 Part is functional with VDD up to 5.5 V.
2 Temperature range is −15°C to +105°C, typical at +25°C.
3 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 12± to Code 16256); AD5620 (Code 32 to Code 4064). Output
unloaded.
4 Guaranteed by design and characterization; not production tested.
Rev. A | Page 6 of 24
AD5620/AD5640/AD5660
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
DD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
V
Table 3.
Limit at TMIN, TMAX
VDD = 3.6 V to 5.5 V
Parameter
VDD = 2.7 V to 3.6 V
Unit
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
1
t1
50
13
13
13
5
33
13
13
13
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
t3
t4
t5
t6
t7
t±
t9
t10
4.5
0
4.5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
50
13
0
33
13
0
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
t10
t1
t9
SCLK
t2
t8
t3
t7
t4
SYNC
DIN
t6
t5
MSB
LSB
LSB = DB0
MSB = DB23 FOR AD5660;
MSB = DB15 FOR AD5620/AD5640
Figure 2. Serial Write Operation
Rev. A | Page 7 of 24
AD5620/AD5640/AD5660
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VOUT to GND
VFB to GND
VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−15°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
SOT-23 Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
SnPb
119°C/W
141°C/W
44°C/W
240°C
260°C
Pb-Free
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page ± of 24
AD5620/AD5640/AD5660
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
GND
DIN
DD
AD5620/
AD5640/
AD5660
V
1
2
3
4
8
7
6
5
GND
DIN
DD
V
REFOUT
AD5620/
AD5640/
V
REFOUT
V
SCLK
SYNC
FB
TOP VIEW
AD5660
V
SCLK
SYNC
FB
(Not to Scale)
TOP VIEW
(Not to Scale)
V
OUT
V
OUT
Figure 3. SOT-23 Pin Configuration
Figure 4. MSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
VDD
VREFOUT
VFB
VOUT
SYNC
Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND.
Reference Voltage Output.
Feedback Connection for the output amplifier. VFB should be connected to VOUT for normal operation.
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24th clock cycle for the AD5660 and the 16th clock cycle for
AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the DAC.
6
7
±
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16 -bit shift register.
Data is clocked into the register on the falling edge of the serial clock input.
GND
Ground Reference Point for all circuitry on the part.
Rev. A | Page 9 of 24
AD5620/AD5640/AD5660
TYPICAL PERFORMANCE CHARACTERISTICS
10
1.0
0.8
0.6
0.4
0.2
V
V
= 5V
V
V
= 5V
DD
TARE=FO25U°TC
DD
8
6
4
2
= 2.5V
= 2.5V
TARE=FO25U°TC
0
0
–2
–0.2
–4
–6
–0.4
–0.6
–8
–0.8
–1.0
–10
CODE
CODE
Figure 5. INL—AD5660-2/AD5660-3
Figure 8. DNL—AD5660-2/AD5660-3
4
0.5
0.4
0.3
0.2
0.1
V
V
= 5V
V
V
= 5V
DD
TARE=FO25U°TC
DD
= 2.5V
= 2.5V
TARE=FO25U°TC
3
2
1
0
0
–0.1
–1
–2
–0.2
–0.3
–3
–4
–0.4
–0.5
CODE
CODE
Figure 6. INL—AD5640-2/AD5640-3
Figure 9. DNL—AD5640-2/AD5640-3
1.0
0.20
0.15
0.10
0.05
V
V
= 5V
V
V
= 5V
DD
TARE=FO25U°TC
DD
= 2.5V
= 2.5V
0.8
0.6
0.4
0.2
TARE=FO25U°TC
0
–0.2
–0.4
–0.6
0
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000 1500 2000 2500 3000
CODE
3500 4000
0
500
1000 1500 2000 2500 3000
CODE
3500 4000
Figure 7. INL—AD5620-2/AD6520-3
Figure 10. DNL—AD5620-2/AD6520-3
Rev. A | Page 10 of 24
AD5620/AD5640/AD5660
10
1.0
V
V
= 3V
V
V
= 3V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
8
6
= 1.25V
0.8
0.6
= 1.25V
T
T
A
A
4
0.4
2
0.2
0
0
–2
–4
–6
–0.2
–0.4
–0.6
–8
–0.8
–1.0
–10
CODE
CODE
Figure 11. INL—AD5660-1
Figure 14. DNL—AD5660-1
4
3
0.5
0.4
V
V
= 3V
V
V
= 3V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
= 1.25V
= 1.25V
T
T
A
A
0.3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–1
–2
–3
–4
–0.4
–0.5
CODE
CODE
Figure 12. INL—AD5640-1
Figure 15. DNL—AD5640-1
1.0
0.8
0.20
0.15
0.10
0.05
0
V
V
= 3V
V
V
= 3V
DD
REFOUT
DD
= 1.25V
= 1.25V
REFOUT
= 25°C
T
= 25°C
T
A
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
Figure 13. INL—AD5620-1
Figure 16. DNL—AD5620-1
Rev. A | Page 11 of 24
AD5620/AD5640/AD5660
10
200
180
160
140
120
100
80
V
T
= 5V
= 25°C
MAX INL
DD
8
A
V
= 5V
DD
6
4
2
MAX DNL
MIN DNL
0
–2
60
–4
–6
40
V
= 3.3V
DD
–8
20
0
MIN INL
65
–10
–15
5
25
45
85
105
TEMPERATURE (°C)
I
(mA)
DD
Figure 17. INL Error and DNL Error vs. Temperature
Figure 20. IDD Histogram
0.5
0.50
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
V
= 5V
DD
0.40
0.30
0.20
0.10
0
0.4
0.3
0.2
0.1
GAIN ERROR
V
V
= 3V
DD
= 1.25V
REFOUT
0
–0.1
–0.10
–0.20
–0.30
–0.2
–0.3
FULL-SCALE ERROR
V
V
= 5V
DD
= 2.5V
–2
REFOUT
–0.4
–0.5
–0.40
–0.50
–15
5
25
45
65
85
105
–10
–8
–6
–4
0
2
4
6
8
10
TEMPERATURE (°C)
CURRENT (mA)
Figure 18. Gain Error and Full-Scale Error vs. Temperature
Figure 21. Headroom at Rails vs. Source and Sink
2.5
6.00
5.00
4.00
3.00
2.00
1.00
V
= 5V
V
V
T
= 5V
DD
DD
REFOUT
FULL SCALE
= 2.5V
= 25°C
1.5
0.5
A
ZERO-CODE ERROR
3/4 SCALE
MIDSCALE
1/4 SCALE
–0.5
–1.5
OFFSET ERROR
–2.5
–3.5
0
ZERO SCALE
–1.00
–15
5
25
45
65
85
105
–30
–20
–10
0
10
20
30
TEMPERATURE (°C)
CURRENT (mA)
Figure 22. Source and Sink Capability—AD5660-2/AD5660-3
Figure 19. Zero-Code and Offset Error vs. Temperature
Rev. A | Page 12 of 24
AD5620/AD5640/AD5660
4.00
3.00
2.00
1.00
V
V
= 3V
DD
REFOUT
= 1.25V
T
= 25°C
A
FULL SCALE
V
= 5V
DD
= 25°C
3/4 SCALE
MIDSCALE
1/4 SCALE
T
A
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
V
= 909mV/DIV
OUT
0
ZERO SCALE
1
–1.00
–30
–20
–10
0
10
20
30
TIME BASE = 4μs/DIV
CURRENT (mA)
Figure 26. Full-Scale Settling Time, 5 V
Figure 23. Source and Sink Capability—AD5660-1
0.7
0.6
0.5
0.4
V
V
= 5V
= 3V
DD
DD
T
A
= 25°C
V
DD
1
2
V
REF
0.3
0.2
V
OUT
0.1
0
3
512
10512
20512
30512
CODE
40512
50512
60512
CH1 2.00V CH2 2.00V
CH3 100mV
M40.0ms
CH1
Figure 24. Supply Current vs. Code
Figure 27. Power-On Reset to 0 V—AD5660-2
1400
1200
1000
800
T
A
= 25°C
V
DD
1
2
V
= 5V
DD
V
REF
600
400
V
= 3V
DD
V
OUT
200
0
3
CH1 2.00V CH2 2.00V
CH3 200mV
M20.0μs
CH1
1.88V
0
1
2
3
4
5
V
(V)
LOGIC
Figure 28. Power-On Reset to Midscale—AD5660-3
Figure 25. Supply Current vs. Logic Input Voltage
Rev. A | Page 13 of 24
AD5620/AD5640/AD5660
1.250800
1.250600
1.250400
1.250200
V
DD
1.250000
1.249800
1.249600
1
2
V
REF
1.249400
1.249200
1.249000
1.248800
V
V
= 3V
= 1.25V
= 25°C
DD
REFOUT
T
A
V
OUT
13nS/SAMPLE NUMBER
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
3
1.248600
1.248400
GLITCH IMPULSE = 0.284nV-s
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
CH1 1.20V CH2 1.00V
CH3 100mV
M100μs
CH1
1.87V
Figure 32. Digital-to-Analog Glitch Impulse—AD5660-1
Figure 29. Power-On Reset to 0 V—AD5660-1
2.500250
V
= 5V
DD
V
= 3V
DD
2.500200
2.500150
2.500100
SCLK
T = 25°C
A
20nS/SAMPLE NUMBER
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH = 0.06nV-s
1
2.500050
2.500000
2.499950
2.499900
2.499850
2.499800
2.499750
3
2.499700
2.499650
2.499600
V
OUT
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
CH1 2.00V
M1.00μs
CH2
520mV
CH3 50.0mV
Figure 33. Digital Feedthrough
Figure 30. Exiting Power-Down to Midscale
16
14
12
10
8
2.501250
2.501000
2.500750
2.500500
2.500250
T
= 25°C
A
V
= 3V
DD
2.500000
2.499750
2.499500
2.499250
2.499000
2.498750
V
= 5V
DD
V
V
= 5V
DD
REFOUT
= 25°C
= 2.5V
T
A
13nS/SAMPLE NUMBER
6
2.498500
2.498250
2.498000
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
GLITCH IMPULSE = 0.497nV-s
4
0
1
2
3
4
5
6
7
8
9
10
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
CAPACITANCE (nF)
Figure 34. Settling Time vs. Capacitive Load
Figure 31. Digital-to-Analog Glitch Impulse—AD5660-2/AD5660-3
Rev. A | Page 14 of 24
AD5620/AD5640/AD5660
800
700
600
500
V
V
= 5V
T = 25°C
A
MIDSCALE LOADED
DD
REFOUT
= 25°C
= 2.5V
T
A
DAC LOADED WITH MIDSCALE
1
400
300
200
V
V
= 5V
DD
REFOUT
= 2.5V
100
0
V
V
= 3V
DD
REFOUT
= 1.25V
1000
100
10000
FREQUENCY (Hz)
100000
1000000
5s/DIV
Figure 35. 0.1 Hz to 10 Hz Output Noise—AD5660-2/AD5660-3
Figure 37. Noise Spectral Density
V
V
= 3V
DD
REFOUT
= 25°C
= 1.25V
T
A
DAC LOADED WITH MIDSCALE
1
4s/DIV
Figure 36. 0.1 Hz to 10 Hz Output Noise—AD5660-1
Rev. A | Page 15 of 24
AD5620/AD5640/AD5660
TERMINOLOGY
Relative Accuracy
Offset Error
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. Figure 5 through Figure 7 show typical INL vs. code.
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear region of
the transfer function. Offset error is measured on the AD5660
with Code 512 loaded into the DAC register. It can be negative
or positive.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. Figure 8 through Figure 10 show typical DNL vs. code.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
the change in VDD for the full-scale output of the DAC. It is
measured in dB. VREF is held at 2.5 V, and VDD is varied by 10%.
Zero-Code Error
Output Voltage Settling Time
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5620/AD5640/AD5660, because the output of the DAC
cannot go below 0 V. It is due to a combination of the offset
errors in the DAC and the output amplifier. Zero-code error is
expressed in mV. Figure 19 shows a plot of zero-code error vs.
temperature.
This indicates the amount of time for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change. It
is measured from the 24th falling edge of SCLK.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 31 and Figure 32.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 18 shows a plot of full-
scale error vs. temperature.
Digital Feedthrough
Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s or vice versa.
Gain Error
This is a measurement of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(voltage per √Hz). It is measured by loading the DAC to
midscale and measuring noise at the output. It is measured
in nV/√Hz. Figure 37 shows a plot of noise spectral density.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.
Rev. A | Page 16 of 24
AD5620/AD5640/AD5660
THEORY OF OPERATION
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
D/A SECTION
The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS
process. The architecture consists of a string DAC followed by an
output buffer amplifier. The parts include an internal 1.25 V/2.5 V,
5 ppm/°C reference that is internally gained up by 2. Figure 38
shows a block diagram of the DAC architecture.
INTERNAL REFERENCE
The AD5620/AD5640/AD5660-1 parts include an internal,
1.25 V, 5 ppm/°C reference, giving a full-scale output voltage of
2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an
internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output
voltage of 5 V. The reference associated with each part is
available at the VREFOUT pin. A buffer is required if the reference
output is used to drive external loads. It is recommended that a
100 nF capacitor is placed between the reference output and
GND for reference stability.
V
DD
R
V
FB
R
REF (+)
RESISTOR
STRING
V
DAC REGISTER
OUT
REF (–ٛ)
OUTPUT
AMPLIFIER
GND
Figure 38. DAC Architecture
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. This output
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The inverting input of the
output amplifier is available to the user, allowing for remote
sensing. This VFB pin must be connected to VOUT for normal
operation. It can drive a load of 2 kΩ in parallel with 1,000 pF
to GND. Figure 21 shows the source and sink capabilities of the
output amplifier. The slew rate is 1.5 V/μs with a ¼ to ¾ full-
scale settling time of 10 μs.
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = 2×VREFOUT ×
2N
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
0 to 4,095 for AD5620 (12 bit)
0 to 16,383 for AD5640 (14 bit)
0 to 65,535 for AD5660 (16 bit)
N is the DAC resolution.
SERIAL INTERFACE
The AD5620/AD5640/AD5660 have a 3-wire serial interface
(
, SCLK, and DIN) that is compatible with SPI, QSPI, and
SYNC
R
R
MICROWIRE interface standards as well as most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the
line low.
SYNC
TO OUTPUT
R
Data from the DIN line is clocked into the 16-bit shift register
(AD5620/AD5640) or the 24-bit shift register (AD5660) on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5620/AD5640/AD5660 compatible
with high speed DSPs. On the 16th falling clock edge (AD5620/
AD5640) or the 24th falling clock edge (AD5660), the last data
bit is clocked in and the programmed function is executed, that
is, a change in the DAC register contents and/or a change in the
AMPLIFIER
R
R
mode of operation is executed. At this stage, the
line can
SYNC
be kept low or be brought high. In either case, it must be brought
high for a minimum of 33 ns before the next write sequence so
that a falling edge of
can initiate the next write sequence.
SYNC
Figure 39. Resistor String
Because the
buffer draws more current when VIN = 2 V
SYNC
RESISTOR STRING
than it does when VIN = 0.8 V,
should be idled low between
SYNC
write sequences for even lower power operation of the parts. As
is mentioned previously, however, must be brought high
The resistor string section is shown in Figure 39. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
SYNC
again just before the next write sequence.
Rev. A | Page 17 of 24
AD5620/AD5640/AD5660
INPUT SHIFT REGISTER
AD5620/AD5640
INTERRUPT
SYNC
In a normal write sequence for the AD5660, the
line is
SYNC
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if is brought
The input shift register is 16 bits wide for the AD5620/AD5640
(see Figure 40 and Figure 41). The first two bits are control bits
that control which mode of operation the part is in (normal
mode or any of the three power-down modes). The next
14/12 bits, respectively, are the data bits. These are transferred
to the DAC register on the 16th falling edge of SCLK.
SYNC
high before the 24th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs—see Figure 43.
Similarly, in a normal write sequence for the AD5620/AD5640,
AD5660
the
line is kept low for at least 16 falling edges of SCLK,
SYNC
and the DAC is updated on the 16th falling edge. However, if
is brought high before the 16th falling edge, this acts as
The input shift register is 24 bits wide for the AD5660 (see
Figure 42). The first six bits are don’t care bits. The next two are
control bits that control which mode of operation the part is in
(normal mode or any of the three power-down modes). For a more
complete description of the various modes, see the Power-Down
Modes section. The next 16 bits are the data bits. These are
transferred to the DAC register on the 24th falling edge of SCLK.
SYNC
an interrupt to the write sequence.
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DATA BITS
Figure 40. AD5620 Input Register Contents
DB15 (MSB)
DB0 (LSB)
PD1
PD0 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
Figure 41. AD5640 Input Register Contents
DB23 (MSB)
DB0 (LSB)
X
X
X
X
X
X
PD1 PD0 D15 D14
D13 D12
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
Figure 42. AD5660 Input Register Contents
SCLK
SYNC
DIN
MSB
LSB
MSB
LSB
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16TH/24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH/24TH FALLING EDGE
SYNC
Figure 43.
Interrupt Facility
Rev. A | Page 1± of 24
AD5620/AD5640/AD5660
POWER-ON RESET
The AD5620/AD5640/AD5660 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5620/AD5640/AD5660-1-2 DAC output powers up to
0 V, and the AD5620/AD5660-3 DAC output powers up to
midscale. The output remains at this level until a valid write
sequence is made to the DAC, which is useful in applications
where it is important to know the state of the DAC output while
it is in the process of powering up.
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 44. Output Stage During Power-Down
POWER-DOWN MODES
The bias generator, output amplifier, reference, resistor string,
and other associated linear circuitry are all shut down when
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 5 μs for VDD = 5 V and VDD = 3 V.
See Figure 23.
The AD5620/AD5640/AD5660 have four separate modes of
operation. These modes are software-programmable by setting
two bits in the control register. Table 6 and Table 7 show how
the state of the bits corresponds to the operating mode of the
device.
Table 6. Modes of Operation for the AD5660
DB17
DB16
AD5660 Operating Mode
Normal operation
Power-down modes:
1 kΩ to GND
100 kΩ to GND
Three-state
MICROPROCESSOR INTERFACING
AD5660-to-Blackfin® ADSP-BF53x Interface
0
0
Figure 45 shows a serial interface between the AD5660 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multi-
processor communications. Using SPORT0 to connect to the
AD5660, the setup for the interface is as follows: DT0PRI drives
the DIN pin of the AD5660, while TSCLK0 drives the SCLK of
0
1
1
1
0
1
Table 7. Modes of Operation for the AD5620/AD5640
DB15
DB14
AD5620/AD5640 Operating Mode
Normal operation
Power-down modes:
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
the part and
is driven from TFS0.
SYNC
0
1
1
1
0
1
1
ADSP-BF53x
AD56601
TFS0
DTOPRI
TSCLK0
SYNC
DIN
When both bits are set to 0, the part works normally with its
normal power consumption of 550 μA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA
at 5 V (200 nA at 3 V). Not only does the supply current fall,
but the output stage is internally switched from the output of
the amplifier to a resistor network of known values. The
advantage is that the output impedance of the part is known
while the part is in power-down mode. There are three options:
the output is connected internally to GND through a
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 45. AD5660-to-Blackfin ADSP-BF53x Interface
1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-
stated). The output stage is shown in Figure 44.
Rev. A | Page 19 of 24
AD5620/AD5640/AD5660
occur in the transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data LSB first; however, the AD5660 requires
its data with the MSB as the first bit received. The 80C51/80L51
transmit routine should take this into account.
AD5660-to-68HC11/68L11 Interface
Figure 46 shows a serial interface between the AD5660 and the
68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives
the SCLK of AD5660, and the MOSI output drives the serial
data line of the DAC. The
signal is derived from a port line
SYNC
(PC7). The set-up conditions for correct operation of this
interface are as follows: The 68HC11/68L11 should be con-
figured so that its CPOL bit is 0, and its CPHA bit is 1. When
AD56601
1
80C51/80L51
data is being transmitted to the DAC, the
line is taken
SYNC
low (PC7). When the 68HC11/68L11 is configured in this way,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
AD5660, PC7 is left low after the first eight bits are transferred, a
second serial write operation is performed to the DAC, and PC7
is taken high at the end of this procedure.
P3.3
TxD
RxD
SYNC
SCLK
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. AD5660-to-80C51/80L51 Interface
AD5660-to-MICROWIRE Interface
1
68HC11/68L11
AD56601
Figure 48 shows an interface between the AD5660 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5660 on the rising edge of the SK.
PC7
SYNC
SCLK
DIN
SCK
MOSI
AD56601
1
MICROWIRE
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. AD5660-to-68HC11/68L11 Interface
CS
SK
SO
SYNC
SCLK
DIN
AD5660-to-80C51/80L51 Interface
Figure 47 shows a serial interface between the AD5660 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5660,
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. AD5660-to-MICROWIRE Interface
and RxD drives the serial data line of the part. The
signal
SYNC
is again derived from a bit-programmable pin on the port. In
this case, Port Line P3.3 is used. When data is to be transmitted
to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit
data only in 8-bit bytes; therefore, only eight falling clock edges
Rev. A | Page 20 of 24
AD5620/AD5640/AD5660
APPLICATIONS
R2
10kΩ
USING AN REF19x AS A POWER SUPPLY FOR THE
AD5620/AD5640/AD5660
+5V
R1
10kΩ
+5V
Because the supply current required by the AD5620/AD5640/
AD5660 is extremely low, an alternative option is to use a REF19x
voltage reference (REF195 for 5 V or REF193 for 3 V) to supply
the required voltage to the part—see Figure 49. This is especially
useful if the power supply is quite noisy or if the system supply
voltages are at some value other than 5 V or 3 V, for example, 15 V.
The REF19x outputs a steady supply voltage for the AD5620/
AD5640/AD5660. If the low dropout REF195 is used, the current
it needs to supply to the AD5660 is 500 μA. This is with no load
on the output of the DAC. When the DAC output is loaded, the
REF195 also must supply the current to the load. The total current
required (with a 5 kΩ load on the DAC output) is
AD820/
±5V
OP295
V
FB
V
V
DD
OUT
10μF
0.1μF
AD5660
–5V
3-WIRE
SERIAL
INTERFACE
Figure 50. Bipolar Operation with the AD5660
USING THE AD5660 AS AN ISOLATED,
PROGRAMMABLE, 4 TO 20 mA PROCESS
CONTROLLER
500 μA + (5 V/5 kΩ) = 1.5 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 3 ppm (15 μV) for the 1.5 mA
current drawn from it. This corresponds to a 0.197 LSB error
for the AD5660.
In many process-control system applications, 2-wire current
transmitters are used to transmit analog signals through noisy
environments. These current transmitters use a zero-scale signal
current of 4 mA to power the signal conditioning circuitry of
the transmitter. The full-scale output signal in these transmitters
is 20 mA. The converse approach to process control can also be
used, in which a low-power, programmable current source is
used to control remotely located sensors or devices in the loop.
15V
5V
REF195
SYNC
A circuit that performs this function is shown in Figure 51.
Using the AD5660 as the controller, the circuit provides a
programmable output current of 4 to 20 mA, proportional to
the digital code of the DAC. Biasing for the controller is provided
by the ADR02 and requires no external trim for two reasons: first,
the ADR02’s tight initial output voltage tolerance, and second,
the low supply current consumption of both the AD8627 and
the AD5660. The entire circuit, including optocouplers, consumes
less than 3 mA from the total budget of 4 mA. The AD8627
regulates the output current to satisfy the current summation
at the noninverting node of the AD8627.
3-WIRE
SERIAL
INTERFACE
V
= 0V TO 5V
OUT
SCLK
DIN
AD5660
Figure 49. REF195 as the Power Supply to the AD5660
BIPOLAR OPERATION USING THE AD5660
The AD5660 is designed for single-supply operation, but a
bipolar output range is also possible using the circuit in
Figure 50. Figure 50 gives an output voltage range of 5 V.
Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
IOUT = 1/R7 (VDAC × R3/R1 + VREF × R3/R2)
The output voltage for any input code can be calculated as
For the values shown in Figure 51,
D
65536
R1+ R2
R1
R2
R1
⎡
⎤
⎛
⎜
⎝
⎞ ⎛
⎠ ⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
IOUT = 0.2435 μA × D + 4 mA
VO = VDD
×
×
−V
×
⎟ ⎜
DD
⎢
⎥
⎣
⎦
where D = 0 ≤ D ≤ 65,535, giving a full-scale output current of
20 mA when the AD5660’s digital code equals 0xFFFF.
where D represents the input code in decimal (0 to 65,535).
When VDD = 5 V, R1 = R2 = 10 kΩ,
Offset trim at 4 mA is provided by P2, and P1 provides the circuit
gain trim at 20 mA. These two trims do not interact because
the noninverting input of the AD8627 is at virtual ground. The
Schottky diode, D1, is required in this circuit to prevent loop
supply power-on transients from pulling the noninverting input
of the AD8627 more than 300 mV below its inverting input.
Without this diode, such transients could cause phase reversal
10×D
65536
⎛
⎜
⎝
⎞
⎟
⎠
V =
−5 V
O
This results in an output voltage range of 5 V, with 0x0000
corresponding to a −5 V output and 0xFFFF corresponding to a
+5 V output.
Rev. A | Page 21 of 24
AD5620/AD5640/AD5660
of the AD8627 and possible latch-up of the controller. The loop
supply voltage compliance of the circuit is limited by the maximum
applied input voltage to the ADR02 and is from 12 V to 40 V.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5620/
AD5640/AD5660 should have separate analog and digital
sections, each having its own area of the board. If the AD5620/
AD5640/AD5660 are in a system where other devices require
an AGND-to-DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5620/AD5640/AD5660.
ADR02
V
LOOP
12V TO 36V
R2
18.5kΩ
P2
4mA
ADJUST
SERIAL
LOAD
Q1
2N3904
R1
4.7kΩ
P1
AD5660
AD8627
20mA
R6
3.3kΩ
ADJUST
D1
4–20mA
R3
1.5kΩ
RL
R7
100Ω
The power supply to the AD5620/AD5640/AD5660 should be
bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should be as close as physically possible to the device, with the
0.1 μF capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the
0.1 μF capacitor has a low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 μF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
Figure 51. Programmable 4 to 20 mA Process Controller
USING THE AD5620/AD5640/AD5660 WITH A
GALVANICALLY ISOLATED INTERFACE
For process-control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from hazardous
common-mode voltages that might occur in the area where
the DAC is functioning. The iCoupler® provides isolation in
excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire
serial logic interface; therefore, the ADuM1300 3-channel
digital isolator provides the required isolation (see Figure 52).
The power supply to the part also must be isolated, which is
done by using a transformer. On the DAC side of the trans-
former, a 5 V regulator provides the 5 V supply required for the
AD5620/AD5640/AD5660.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other components with
fast switching digital signals should be shielded from other
parts of the board by digital ground. Avoid crossover of digital
and analog signals if possible. When traces cross on opposite
sides of the board, ensure that they run at right angles to each
other to reduce feedthrough effects on the board. The best
board layout technique is the microstrip technique, where the
component side of the board is dedicated to the ground plane
only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
5V
REGULATOR
10μF
0.1μF
POWER
V
DD
VOA
VOB
SCLK
V1A
V1B
SCLK
SYNC
ADuM1300
AD56x0
V
OUT
SDI
VOC
V1C
DIN
DATA
GND
Figure 52. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface
Rev. A | Page 22 of 24
AD5620/AD5640/AD5660
OUTLINE DIMENSIONS
3.20
3.00
2.80
2.90 BSC
8
1
7
2
6
3
5
4
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
PIN 1
0.65 BSC
1.95
BSC
1.30
1.15
0.90
0.95
0.85
0.75
1.10 MAX
1.45 MAX
0.22
0.08
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.15 MAX
SEATING
PLANE
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 53. 8-Lead Small Outline Transistor Package [SOT-23]
Figure 54. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
(RJ-8)
Dimensions shown in millimeters
Dimensions shown in millimeters
AD5620 ORDERING GUIDE
Package
Package
Power-On
Internal
Model
Temp. Range
Description
Option
Branding
D2K
D2K
D2L
D2L
D2H
D2H
D2J
Reset to Code
Accuracy
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
Reference
1.25 V
1.25 V
2.5 V
AD5620ARJ-1500RL7
AD5620ARJ-1REEL7
AD5620ARJ-2500RL7
AD5620ARJ-2REEL7
AD5620BRJ-1500RL7
AD5620BRJ-1REEL7
AD5620BRJ-2500RL7
AD5620BRJ-2REEL7
AD5620CRM-1
AD5620CRM-1REEL7
AD5620CRM-2
AD5620CRM-2REEL7
AD5620CRM-3
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
Evaluation Board
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RM-±
RM-±
RM-±
RM-±
RM-±
RM-±
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Midscale
2.5 V
1.25 V
1.25 V
2.5 V
D2J
2.5 V
D2M
D2M
D2N
D2N
D2P
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
AD5620CRM-3REEL7
EVAL-AD5620EB
D2P
2.5 V
Rev. A | Page 23 of 24
AD5620/AD5640/AD5660
AD5640 ORDERING GUIDE
Package
Description
Package
Option
Power-On
Branding Reset to Code
Internal
Reference
Model
Temp. Range
Accuracy
±± LSB INL
±± LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
AD5640ARJ-2500RL7
AD5640ARJ-2REEL7
AD5640BRJ-1500RL7
AD5640BRJ-1REEL7
AD5640BRJ-2500RL7
AD5640BRJ-2REEL7
AD5640CRM-1
AD5640CRM-1REEL7
AD5640CRM-2
AD5640CRM-2REEL7
EVAL-AD5640EB
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
Evaluation Board
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
D2T
D2T
D2Q
D2Q
D2R
D2R
D2U
D2U
D2V
D2V
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
2.5 V
2.5 V
1.25 V
1.25 V
2.5 V
RJ-±
2.5 V
RM-±
RM-±
RM-±
RM-±
1.25 V
1.25 V
2.5 V
2.5 V
AD5660 ORDERING GUIDE
Package
Description
Package
Option
Power-On
Branding Reset to Code Accuracy
Internal
Reference
Model
Temp. Range
AD5660ARJ-1500RL7
AD5660ARJ-1REEL7
AD5660ARJ-2500RL7
AD5660ARJ-2REEL7
AD5660ARJ-3500RL7
AD5660ARJ-3REEL7
AD5660BRJ-1500RL7
AD5660BRJ-1REEL7
AD5660BRJ-2500RL7
AD5660BRJ-2REEL7
AD5660BRJ-3500RL7
AD5660BRJ-3REEL7
AD5660CRM-1
AD5660CRM-1REEL7
AD5660CRM-2
AD5660CRM-2REEL7
AD5660CRM-3
AD5660CRM-3REEL7
EVAL-AD5660EB
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
−15°C to +105°C
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead SOT-23
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
±-Lead MSOP
Evaluation Board
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RM-±
RM-±
RM-±
RM-±
RM-±
RM-±
D30
D30
D31
D31
D32
D32
D2X
D2X
D2Y
D2Y
D2Z
D2Z
D33
D33
D34
D34
D35
D35
Zero
Zero
Zero
Zero
Midscale
Midscale
Zero
Zero
Zero
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
Zero
Midscale
Midscale
Zero
Zero
Zero
Zero
Midscale
Midscale
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04539–0–9/05(A)
Rev. A | Page 24 of 24
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