EVAL-AD5663REBZ [ADI]
Dual 12-/14-/16-Bit nanoDAC with 5 ppm/ C On-Chip Reference; 双12位/ 14位/ 16位属于nanoDAC 5 PPM / C片参考
| 型号： | EVAL-AD5663REBZ |
| 厂家： | 
ADI |
| 描述： | Dual 12-/14-/16-Bit nanoDAC with 5 ppm/ C On-Chip Reference |
| 文件： | 总32页 (文件大小：967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-/14-/16-Bit nanoDAC® with
5 ppm/°C On-Chip Reference
Data Sheet
AD5623R/AD5643R/AD5663R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
/V
DD
REFIN REFOUT
Low power, smallest pin-compatible, dual nanoDAC
AD5663R: 16 bits
1.25V/2.5V
REFERENCE
LDAC
AD5643R: 14 bits
AD5623R: 12 bits
User-selectable external or internal reference
External reference default
INPUT
DAC
STRING
DAC A
V
V
A
SCLK
SYNC
DIN
BUFFER
OUT
OUT
REGISTER
REGISTER
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
B
BUFFER
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
10-lead MSOP and 3 mm × 3 mm LFCSP
2.7 V to 5.5 V power supply
AD5623R/AD5643R/AD5663R
POWER-ON
RESET
POWER-DOWN
LOGIC
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
LDAC CLR
GND
Figure 1.
Table 1. Related Devices
Serial interface up to 50 MHz
Part No.
Description
LDAC
CLR
functions
Hardware
and
AD5663
2.7 V to 5.5 V, dual 16-bit nanoDAC, with external
reference
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5623R/AD5643R/AD5663R, members of the nanoDAC
family, are low power, dual 12-, 14-, and 16-bit buffered voltage-
out digital-to-analog converters (DAC) that operate from a single
2.7 V to 5.5 V supply and are guaranteed monotonic by design.
The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.
The AD5623R/AD5643R/AD5663R use a versatile, 3-wire serial
interface that operates at clock rates up to 50 MHz, and they are
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing to be achieved.
The AD5623R/AD5643R/AD5663R have an on-chip reference.
The AD5623R-3/AD5643R-3/AD5663R-3 have a 1.25 V, 5 ppm/°C
reference, giving a full-scale output of 2.5 V; and the AD5623R-5/
AD5643R-5/AD5663R-5 have a 2.5 V, 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-chip reference is off at
power-up, allowing the use of an external reference; and all
devices can be operated from a single 2.7 V to 5.5 V supply.
The internal reference is turned on by writing to the DAC.
PRODUCT HIGHLIGHTS
1. Dual 12-, 14-, and 16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 10-lead MSOP and 10-lead, 3 mm ×
3 mm LFCSP.
The parts incorporate a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 480 nA at 5 V
and provides software-selectable output loads while in power-
down mode.
4. Low power; typically consumes 0.6 mW at 3 V and
1.25 mW at 5 V.
5. 4.5 μs maximum settling time for the AD5623R.
Rev. F
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Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5623R/AD5643R/AD5663R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 20
Internal Reference ...................................................................... 20
External Reference ..................................................................... 20
Serial Interface ............................................................................ 20
Input Shift Register .................................................................... 21
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5623R-5/AD5643R-5/AD5663R-5....................................... 3
AD5623R-3/AD5643R-3/AD5663R-3....................................... 5
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 7
Timing Diagram ........................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
Digital-to-Analog Section ......................................................... 20
Resistor String............................................................................. 20
SYNC
Interrupt .......................................................................... 21
Power-On Reset.......................................................................... 22
Software Reset............................................................................. 22
Power-Down Modes .................................................................. 22
LDAC
Function .......................................................................... 23
Internal Reference Setup ........................................................... 24
Microprocessor Interfacing....................................................... 25
Applications Information .............................................................. 26
Using a Reference as a Power Supply....................................... 26
Bipolar Operation Using the AD5663R .................................. 26
Using the AD5663R with a Galvanically Isolated Interface . 26
Power Supply Bypassing and Grounding................................ 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 29
REVISION HISTORY
2/13—Rev. E to Rev. F
4/10—Rev. A to Rev. B
Changes to Table 14........................................................................ 23
Updated Outline Dimensions....................................................... 28
4/12—Rev. D to Rev. E
12/06—Rev. 0 to Rev. A
Changes to Table 2............................................................................ 3
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide .......................................................... 29
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................5
Changes to Figure 3...........................................................................9
Changes to Ordering Guide .......................................................... 28
4/11—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 29
4/06—Revision 0: Initial Version
6/10—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 28
Rev. F | Page 2 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
SPECIFICATIONS
AD5623R-5/AD5643R-5/AD5663R-5
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade1
Typ
B Grade1
Typ
Parameter
Min
Max
Min
Max
Unit
Conditions/Comments
STATIC PERFORMANCE2
AD5663R
Resolution
16
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5643R
±±
±16
±1
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5623R
±2
±4
±0.5
Resolution
Bits
LSB
LSB
mV
mV
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
±1
±2
±1
+10
±10
±1
±0.5
±1
±0.25
+10
±10
±1
Guaranteed monotonic by design
All 0s loaded to DAC register
+2
±1
−0.1
+2
±1
−0.1
Full-Scale Error
% of
FSR
All 1s loaded to DAC register
Gain Error
±1.5
±1.5
% of
FSR
Zero-Scale Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
±2
±2.5
−100
±2
±2.5
−100
µV/°C
ppm
dB
Of FSR/°C
DAC code = midscale ; VDD = 5 V ±
10%
DC Crosstalk (External Reference)
DC Crosstalk (Internal Reference)
10
10
µV
Due to full-scale output change;
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change;
RL = 2 kΩ to GND or VDD
10
5
25
10
5
25
µV/mA
µV
µV
20
10
20
10
µV/mA
µV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
μs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode;
VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
170
26
200
VDD
170
26
200
VDD
µA
V
kΩ
VREF = VDD = 5.5 V
0.75
0.75
Rev. F | Page 3 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
A Grade1
Typ
B Grade1
Typ
Parameter
Min
Max
Min
Max
Unit
Conditions/Comments
At ambient
REFERENCE OUTPUT
Output Voltage
Reference Temperature Coefficient3
2.495
2.505 2.495
2.505
±10
V
±10
±10
7.5
±5
±10
7.5
ppm/°C MSOP package models
ppm/°C LFCSP package models
kΩ
Output Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage (VINL
Input High Voltage (VINH
Pin Capacitance
±2
0.±
2
±2
0.±
µA
V
V
pF
pF
All digital inputs
VDD = 5 V
VDD = 5 V
DIN, SCLK, and SYNC
LDAC and CLR
)
)
2
3
3
19
19
POWER REQUIREMENTS
VDD
4.5
5.5
4.5
5.5
V
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
0.25
0.±
0.45
1
0.25
0.±
0.45
1
mA
mA
IDD (All Power-Down Modes)5
VDD = 4.5 V to 5.5 V
0.4±
1
0.4±
1
µA
VIH = VDD and VIL = GND
1 Temperature range: A, B grade = −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 12± to Code 16,256), and AD5623R (Code 32 to Code 4064).
Output unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 Both DACs powered down.
Rev. F | Page 4 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
AD5623R-3/AD5643R-3/AD5663R-3
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Grade1
Parameter
Min
Typ
Max
Unit
Conditions/Comments
STATIC PERFORMANCE2
AD5663R
Resolution
16
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5643R
±±
±16
±1
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5623R
±2
±4
±0.5
Resolution
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
Full-Scale Error
±0.5
±1
LSB
LSB
mV
mV
% of FSR
% of FSR
µV/°C
ppm
dB
±0.25
+10
±10
±1
Guaranteed monotonic by design
All 0s loaded to DAC register
+2
±1
−0.1
All 1s loaded to DAC register
Gain Error
±1.5
Zero-Scale Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk (External Reference)
±2
±2.5
−100
10
Of FSR/°C
DAC code = midscale; VDD = 3 V ± 10%
Due to full-scale output change;
RL = 2 kΩ to GND or VDD
µV
10
5
µV/mA
µV
Due to load current change
Due to powering down (per channel)
DC Crosstalk (Internal Reference)
25
µV
Due to full-scale output change;
RL = 2 kΩ to GND or VDD
20
10
µV/mA
µV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
V
Capacitive Load Stability
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
DC Output Impedance
Short Circuit Current
Power-Up Time
VDD = 3 V
Coming out of power-down mode; VDD = 3 V
REFERENCE INPUTS
Reference Current
170
26
200
VDD
µA
V
kΩ
VREF = VDD = 3.6 V
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
0.75
1.247
1.253
±15
V
At ambient
MSOP package models
LFCSP package models
Reference Temperature Coefficient3
±5
±10
7.5
ppm/°C
ppm/°C
kΩ
Output Impedance
Rev. F | Page 5 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
B Grade1
Typ
Parameter
LOGIC INPUTS3
Min
Max
Unit
Conditions/Comments
Input Current
±2
0.±
µA
V
V
pF
pF
All digital inputs
VDD = 3 V
VDD = 3 V
DIN, SCLK, and SYNC
LDAC and CLR
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
2
3
19
POWER REQUIREMENTS
VDD
2.7
3.6
V
IDD (Normal Mode)4
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
200
±00
425
900
µA
µA
0.2
1
µA
VIH = VDD and VIL = GND
1 Temperature range: B grade = −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 12± to Code 16,256), and AD5623R (Code 32 to Code 4064).
Output unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 Both DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2
Min
Typ
Max
Unit
Conditions/Comments3
Output Voltage Settling Time
AD5623R
AD5643R
3
3.5
4
4.5
5
7
µs
µs
µs
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±2 LSB
AD5663R
Slew Rate
1.±
10
0.1
−90
0.1
1
4
1
4
340
−±0
120
100
15
V/µs
nV-s
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
Analog Crosstalk
1 LSB change around major carry
VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
External reference
Internal reference
External reference
Internal reference
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
VREF = 2 V ± 0.1 V p-p
dB
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
μV p-p
Output Noise
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range: A, B grade = −40°C to +105°C, typical at +25°C.
Rev. F | Page 6 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
DD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
V
Table 5.
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
Parameter
Unit
Conditions/Comments
2
t1
ns min
SCLK cycle time
t2
t3
t4
t5
t6
t7
t8
t9
t10
9
9
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
13
5
5
0
15
13
0
LDAC pulse width low
t11
t12
t13
t14
t15
10
15
5
ns min
ns min
ns min
ns min
ns max
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
0
300
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
t10
t1
t9
SCLK
t2
t8
t3
t4
t7
SYNC
t6
t5
DIN
1
DB23
DB0
t14
t11
LDAC
t12
2
LDAC
t13
CLR
t15
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. F | Page 7 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to GND
VOUT to GND
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VREFIN/VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
−40°C to +105°C
−65°C to +150°C
150°C
ESD CAUTION
(TJ max − TA)/θJA
LFCSP Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
61°C/W
142°C/W
43.7°C/W
260(+0/−5)°C
Rev. F | Page ± of 32
Data Sheet
AD5623R/AD5643R/AD5663R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
10
9
V
V
A
B
V
V
/V
OUT
REFIN REFOUT
AD5623R/
AD5643R/
AD5663R
TOP VIEW
(Not to Scale)
OUT
DD
8
GND
DIN
7
LDAC
CLR
SCLK
SYNC
6
NOTE:
EXPOSED PAD TIED TO GND ON
LFCSP PACKAGE.
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
VOUT
VOUT
GND
A
B
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground. Reference point for all circuitry on the part.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
LDAC
5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are
ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.
The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during
a write sequence, the write is aborted.
6
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
7
SCLK
DIN
VDD
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with
a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
±
9
10
VREFIN/VREFOUT Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output
pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
Rev. F | Page 9 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
10
V
T
= V = 5V
REF
V
= V = 5V
DD
= 25°C
DD
= 25°C
REF
0.8
0.6
0.4
0.2
8
T
A
A
6
4
2
0
–2
–4
0
–0.2
–0.4
–0.6
–6
–8
–0.8
–1.0
–10
0
10k
20k
30k
CODE
40k
50k
60k
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
Figure 7. DNL—AD5663R, External Reference
Figure 4. INL—AD5663R, External Reference
0.5
4
V
= V = 5V
REF
V
T
= V = 5V
REF
DD
= 25°C
DD
= 25°C
T
0.4
0.3
0.2
0.1
A
A
3
2
1
0
0
–0.1
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0
2.5k
5.0k
7.5k
CODE
10.0k
12.5k
15.0k
0
2.5k
5.0k
7.5k
CODE
10.0k
12.5k
15.0k
Figure 8. DNL—AD5643R, External Reference
Figure 5. INL—AD5643R, External Reference
1.0
0.20
0.15
0.10
0.05
0
V
= V = 5V
REF
V
= V = 5V
REF
DD
= 25°C
DD
= 25°C
T
T
0.8
0.6
A
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
0
0.5k
1.0k
1.5k
2.0k
CODE
2.5k
3.0k
3.5k
4.0k
CODE
Figure 6. INL—AD5623R, External Reference
Figure 9. DNL—AD5623R, External Reference
Rev. F | Page 10 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
10
1.0
0.8
0.6
0.4
0.2
V
V
= 5V
V
= 5V
DD
DD
REFOUT
= 25°C
8
6
4
2
= 2.5V
V
= 2.5V
REFOUT
T
T = 25°C
A
A
0
0
–2
–0.2
–4
–6
–0.4
–0.6
–8
–0.8
–1.0
–10
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
Figure 10. INL—AD5663R-5
Figure 13. DNL—AD5663R-5
4
0.5
0.4
0.3
0.2
0.1
V
V
= 5V
V
V
= 5V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
= 2.5V
= 2.5V
3
2
T
T
A
A
1
0
0
–0.1
–1
–2
–0.2
–0.3
–3
–4
–0.4
–0.5
CODE
CODE
Figure 11. INL—AD5643R-5
Figure 14. DNL—AD5643R-5
1.0
0.20
0.15
0.10
0.05
V
V
= 5V
V
V
= 5V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
= 2.5V
= 2.5V
0.8
0.6
0.4
0.2
T
T
A
A
0
–0.2
–0.4
–0.6
0
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
CODE
CODE
Figure 12. INL—AD5623R-5
Figure 15. DNL—AD5623R-5
Rev. F | Page 11 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
10
1.0
V
V
T
= 3V
V
V
T
= 3V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
8
6
= 1.25V
0.8
0.6
= 1.25V
A
A
4
0.4
2
0.2
0
0
–2
–4
–6
–0.2
–0.4
–0.6
–8
–0.8
–1.0
–10
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
Figure 16. INL—AD5663R-3
Figure 19. DNL—AD5663R-3
4
3
0.5
0.4
V
V
= 3V
V
= 3V
DD
DD
REFOUT
= 25°C
= 1.25V
V
= 1.25V
REFOUT
T = 25°C
A
T
A
0.3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–1
–2
–3
–4
–0.4
–0.5
CODE
CODE
Figure 17. INL—AD5643R-3
Figure 20. DNL—AD5643R-3
1.0
0.8
0.20
0.15
0.10
0.05
0
V
V
= 3V
DD
REFOUT
= 25°C
V
V
= 3V
DD
REFOUT
= 25°C
= 1.25V
= 1.25V
T
A
T
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
CODE
CODE
Figure 18. INL—AD5623R-3
Figure 21. DNL—AD5623R-3
Rev. F | Page 12 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
8
0
–0.02
–0.04
–0.06
–0.08
V
= 5V
DD
6
MAX INL
V
= V = 5V
REF
DD
4
2
GAIN ERROR
MAX DNL
MIN DNL
0
–0.10
–0.12
–2
–4
–6
–8
–0.14
–0.16
FULL-SCALE ERROR
MIN INL
100
–0.18
–0.20
–40
–20
0
20
40
60
80
120
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. INL Error and DNL Error vs. Temperature
Figure 25. Gain Error and Full-Scale Error vs. Temperature
10
8
1.5
MAX INL
1.0
ZERO-SCALE ERROR
6
V
= 5V
DD
= 25°C
0.5
0
4
T
A
2
MAX DNL
MIN DNL
0
–0.5
–1.0
–1.5
–2.0
–2.5
–2
–4
–6
OFFSET ERROR
MIN INL
4.25
–8
–10
0.75
1.25
1.75
2.25
2.75
3.25
(V)
3.75
4.75
–40
–20
0
20
40
60
80
100
V
REF
TEMPERATURE (°C)
Figure 23. INL Error and DNL Error vs. VREF
Figure 26. Zero-Scale Error and Offset Error vs. Temperature
8
6
1.0
MAX INL
T
A
= 25°C
0.5
4
2
GAIN ERROR
0
MAX DNL
MIN DNL
FULL-SCALE ERROR
–0.5
0
–2
–4
–6
–8
–1.0
MIN INL
–1.5
–2.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
DD
V
DD
Figure 24. INL Error and DNL Error vs. Supply
Figure 27. Gain Error and Full-Scale Error vs. Supply
Rev. F | Page 13 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
1.0
0.5
T
= 25°C
A
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
0.4
0.3
0.5
0
ZERO-SCALE ERROR
0.2
V
V
= 3V
0.1
DD
REFOUT
–0.5
–1.0
–1.5
= 1.25V
0
–0.1
–0.2
–0.3
V
V
= 5V
DD
–2.0
–2.5
= 2.5V
–2
REFOUT
OFFSET ERROR
–0.4
–0.5
2.7
3.2
3.7
4.2
(V)
4.7
5.2
–10
–8
–6
–4
0
2
4
6
8
10
V
DD
CURRENT (mA)
Figure 28. Zero-Scale Error and Offset Error vs. Supply
Figure 31. Headroom at Rails vs. Source and Sink
6
5
4
3
2
1
V
= 5.5V
DD
= 25°C
V
V
= 5V
DD
FULL SCALE
T
A
= 2.5V
REFOUT
= 25°C
8
6
4
2
0
T
A
3/4 SCALE
MIDSCALE
1/4 SCALE
0
ZERO SCALE
–1
–30
0.230
0.235
0.240
0.245
0.250
0.255
–20
–10
0
10
20
30
I
(mA)
DD
CURRENT (mA)
Figure 29. IDD Histogram with External Reference
Figure 32. AD56x3R-5 Source and Sink Capability
4
3
2
1
5
4
3
2
1
0
V
V
= 3V
DD
REFOUT
= 25°C
V
= 5.5V
DD
= 25°C
= 1.25V
T
A
T
A
FULL SCALE
3/4 SCALE
MIDSCALE
1/4 SCALE
0
ZERO SCALE
–1
–30
0.78
0.80
0.82
(mA)
0.84
–20
–10
0
10
20
30
I
DD
CURRENT (mA)
Figure 33. AD56x3R-3 Source and Sink Capability
Figure 30. IDD Histogram with Internal Reference
Rev. F | Page 14 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
0.30
SYNC
T
= 25°C
A
V
V
= V
= V
= 5V
= 3V
DD
REFIN
0.25
0.20
0.15
0.10
1
3
SLCK
DD
REFIN
V
OUT
V
= 5V
DD
0.05
0
2
–40
–20
0
20
40
60
80
100
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
TEMPERATURE (°C)
Figure 34. Supply Current vs. Temperature
Figure 37. Exiting Power-Down to Midscale
2.538
V
= V = 5V
REF
DD
= 25°C
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
T
A
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
V
T
= V = 5V
REF
DD
= 25°C
A
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
V
= 909mV/DIV
OUT
1
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
TIME BASE = 4µs/DIV
Figure 35. Full-Scale Settling Time, 5 V
Figure 38. Digital-to-Analog Glitch Impulse (Negative)
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
V
= V = 5V
REF
DD
= 25°C
V
= V = 5V
REF
DD
= 25°C
T
A
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
V
DD
1
2
MAX(C2)*
420.0mV
V
OUT
CH2 500mV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
CH1 2.0V
M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
Figure 36. Power-On Reset to 0 V
Figure 39. Analog Crosstalk, External Reference
Rev. F | Page 15 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
2.496
2.494
2.492
2.490
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
2.468
2.466
V
V
= 3V
DD
REFOUT
= 25°C
= 1.25V
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
DD
REFOUT
= 25°C
2.464
2.462
2.460
2.458
2.456
= 2.5V
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
4s/DIV
Figure 40. Analog Crosstalk, Internal Reference
Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
800
T
= 25°C
A
MIDSCALE LOADED
700
600
500
400
300
200
V
= V = 5V
REF
DD
= 25°C
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
DD
REFOUT
= 2.5V
100
0
V
V
= 3V
DD
REFOUT
= 1.25V
1k
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
100
10k
FREQUENCY (Hz)
1M
10M
Figure 41. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 44. Noise Spectral Density, Internal Reference
–20
V
= 5V
DD
= 25°C
V
V
= 5V
DD
REFOUT
= 25°C
T
A
–30
–40
= 2.5V
DAC LOADED WITH FULL SCALE
= 2V ± 0.3V p-p
T
A
V
REF
DAC LOADED WITH MIDSCALE
–50
–60
–70
1
–80
–90
–100
2k
4k
6k
8k
10k
5s/DIV
FREQUENCY (Hz)
Figure 42. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Figure 45. Total Harmonic Distortion
Rev. F | Page 16 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
16
V
= V
DD
REF
= 25°C
T
A
14
12
10
8
CLR
3
V
= 3V
DD
V
A
OUT
V
= 5V
DD
V
B
OUT
6
4
4
2
0
1
2
3
4
5
6
7
8
9
10
CH2 1.0V
CH4 1.0V
M200ns A CH3
1.10V
CH3 5.0V
CAPACITANCE (nF)
Figure 46. Settling Time vs. Capacitive Load
CLR
Figure 48.
Pulse Activation Time
5
0
V
= 5V
DD
= 25°C
T
A
–5
–10
–15
–20
–25
–30
–35
–40
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 47. Multiplying Bandwidth
Rev. F | Page 17 of 32
AD5623R/AD5643R/AD5663R
TERMINOLOGY
Data Sheet
Relative Accuracy or Integral Nonlinearity (INL)
DC Power Supply Rejection Ratio (PSRR)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 5.
PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It
is measured in dB. VREF is held at 2 V, and VDD is varied by
10%.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot is shown in
Figure 9.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a 1/4 to 3/4
full-scale input change and is measured from the 24th falling
edge of SCLK.
Digital-to-Analog Glitch Impulse
Zero-Scale Error
The impulse injected into the analog output when the input
code in the DAC register changes state. It is normally specified
as the area of the glitch in nV-s and is measured when the
digital input code is changed by 1 LSB at the major carry
transition (0x7FFF to 0x8000). See Figure 38.
Zero-scale error is the measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-scale error is always positive in
the AD56x3R because the output of the DAC cannot go below
0 V. It is due to a combination of the offset errors in the DAC
and the output amplifier. Zero-scale error is expressed in mV.
A plot of zero-scale error vs. temperature is shown in Figure 26.
Digital Feedthrough
A measure of the impulse injected into the analog output of the
DAC from the digital inputs of the DAC, digital feedthrough is
measured when the DAC output is not updated. It is specified
in nV-s, and it is measured with a full-scale code change on the
data bus, that is, from all 0s to all 1s and vice versa.
Full-Scale Error
Full-scale error is the measurement of the output error when
full-scale code (0xFFFF) is loaded into the DAC register. Ideally,
the output should be VDD − 1 LSB. Full-scale error is expressed
in percent of full-scale range. A plot of full-scale error vs.
temperature is shown in Figure 25.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
Gain Error
LDAC
is not being updated (that is,
decibels (dB).
is high). It is expressed in
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
Noise Spectral Density
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. A plot of noise
spectral density is shown in Figure 44.
Zero-Scale Error Drift
Zero-scale error drift is the measurement of the change in zero-
scale error with a change in temperature. It is expressed in
microvolts/°C (µV/°C).
Gain Temperature Coefficient
DC Crosstalk
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in (ppm
of full-scale range)/°C.
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in microvolts (μV).
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD56x3R
with code 512 loaded in the DAC register. It can be negative or
positive.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in microvolts/
milliamps (μV/mA).
Rev. F | Page 1± of 32
Data Sheet
AD5623R/AD5643R/AD5663R
Digital Crosstalk
Multiplying Bandwidth
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed
in nanovolts-second (nV-s).
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Analog Crosstalk
Total Harmonic Distortion (THD)
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa) while keeping LDAC
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measurement of the harmonics present on the DAC output.
It is measured in decibels (dB).
LDAC
high. Then pulse
low and monitor the output of the DAC
whose digital code was not changed. The area of the glitch is
expressed in nanovolts-second (nV-s).
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
LDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolts-second (nV-s).
Rev. F | Page 19 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
THEORY OF OPERATION
DIGITAL-TO-ANALOG SECTION
R
The AD5623R/AD5643R/AD5663R DAC is fabricated on
a CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. Figure 49 shows a block
diagram of the DAC architecture.
R
R
TO OUTPUT
AMPLIFIER
V
DD
OUTPUT
AMPLIFIER
(GAIN = +2)
REF (+)
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
R
R
GND
Figure 49. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
Figure 50. Resistor String
D
INTERNAL REFERENCE
VOUT VREFIN
2N
The AD5623R/AD5643R/AD5663R on-chip reference is off at
power-up and is enabled via a write to a control register. See the
Internal Reference Setup section for details.
The ideal output voltage when using the internal reference is
given by
D
The AD56x3R-3 has a 1.25 V, 5 ppm/°C reference, giving a full-
scale output of 2.5 V. The AD56x3R-5 has a 2.5 V, 5 ppm/°C
reference, giving a full-scale output of 5 V. The internal refer-
ence associated with each part is available at the VREFOUT pin.
A buffer is required if the reference output is used to drive
external loads. When using the internal reference, it is
recommended that a 100 nF capacitor be placed between
reference output and GND for reference stability.
VOUT 2VREFOUT
2N
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 4095 for AD5623R (12-bit)
0 to 16,383 for AD5643R (14-bit)
0 to 65,535 for AD5663R (16-bit)
EXTERNAL REFERENCE
N is the DAC resolution.
The VREFIN pins on the AD56x3R-3 and the AD56x3R-5 allows
the use of an external reference if the application requires it.
The on-chip reference is off at power-up, and this is the default
condition. The AD56x3R-3 and the AD56x3R-5 can be operated
from a single 2.7 V to 5.5 V supply.
RESISTOR STRING
The resistor string section is shown in Figure 50. It is simply a
string of resistors, each of Value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
SERIAL INTERFACE
The AD5623R/AD5643R/AD5663R have a 3-wire serial interface
SYNC
(
, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards, as well as with most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can drive
a load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 31.
The slew rate is 1.8 V/μs with a 1/4 to 3/4 full-scale settling time
of 10 μs.
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5623R/AD5643R/AD5663R compatible
with high speed DSPs. On the 24th falling clock edge, the last
data bit is clocked in and the programmed function is executed,
for example, a change in DAC register contents and/or a change
in the mode of operation.
Rev. F | Page 20 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
SYNC
At this stage, the
line can be kept low or be brought high.
Table 8. Command Definition
In either case, it must be brought high for a minimum of 15 ns
before the next write sequence, so that a falling edge of
can initiate the next write sequence.
C2
C1
C0
Command
SYNC
0
0
0
0
0
1
Write to Input Register n
Update DAC Register n
0
1
0
Write to Input Register n, update all
(software LDAC)
SYNC
Because the
buffer draws more current when VIN = 2 V
SYNC
than it does when VIN = 0.8 V,
should be idled low between
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Write to and update DAC Channel n
Power down DAC (power up)
Reset
write sequences for even lower power operation. As mentioned
previously, it must, however, be brought high again just before
the next write sequence.
LDAC register setup
INPUT SHIFT REGISTER
Internal reference setup (on/off)
The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t cares. The next three are Command Bit C2 to
Command Bit C0 (see Table 8), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see Table 9), and, finally, the
16-, 14-, and 12-bit data-word.
Table 9. Address Command
A2
A1
A0
ADDRESS (n)
DAC A
DAC B
Reserved
Reserved
All DACs
0
0
0
0
0
1
0
1
0
The data-word comprises the 16-, 14-, and 12-bit input codes,
followed by zero, two, or four don’t care bits, for the AD5663R,
AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,
and Figure 53). The data bits are transferred to the DAC register
on the 24th falling edge of SCLK.
0
1
1
1
1
1
SYNC
INTERRUPT
SYNC
In a normal write sequence, the
least 24 falling edges of SCLK, and the DAC is updated on the
SYNC
line is kept low for at
24th falling edge. However, if
is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 54).
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D3
D1
D4
D2
D0
D3
D1
X
D2
D0
X
D1
D0
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 51. AD5663R Input Shift Register Contents
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
X
X
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 52. AD5643R Input Shift Register Contents
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
X
X
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 53. AD5623R Input Shift Register Contents
SCLK
SYNC
DIN
DB23
DB0
DB23
DB0
INVALID WRITE SEQUENCE:
TH
VALID WRITE SEQUENCE, OUTPUT UPDATES
TH
SYNC HIGH BEFORE 24 FALLING EDGE
ON THE 24 FALLING EDGE
SYNC
Figure 54.
Interrupt Facility
Rev. F | Page 21 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
Again, to select which combination of DAC channels to power
up, set the corresponding bits (Bit DB1 and Bit DB0) to 1. See
Table 13 for contents of the input shift register during power-
down/power-up operation.
POWER-ON RESET
The AD5623R/AD5643R/AD5663R contain a power-on reset
circuit that controls the output voltage during power-up. The
AD5623R/AD5643R/AD5663R DACs output power up to 0 V,
and the output remains there until a valid write sequence is
made to the DACs. This is useful in applications where it is
important to know the state of the output of the DACs while
The DAC output powers up to the value in the input register
LDAC
LDAC
while
is low. If
is high, the DAC ouput powers up
to the value held in the DAC register before power-down.
LDAC
they are in the process of powering up. Any events on
CLR
or
during power-on reset are ignored.
Table 11. Modes of Operation
DB5
DB4
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
SOFTWARE RESET
0
0
The AD5623R/AD5643R/AD5663R contain a software reset
function. Command 101 is reserved for the software reset
function (see Table 8). The software reset command contains
two reset modes that are software-programmable by setting bit
DB0 in the control register. Table 10 shows how the state of the
bit corresponds to the mode of operation of the device. Table 12
shows the contents of the input shift register during the
software reset mode of operation.
0
1
1
1
0
1
When both Bit DB1 and Bit DB2 are set to 0, the part works
normally, with its normal power consumption of 250 µA at 5 V.
However, for the three power-down modes, the supply current
falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. The outputs can
either be connected internally to GND through a 1 kΩ or 100 kΩ
resistor or left open-circuited (three-state) (see Figure 55).
Table 10. Software Reset Modes
DB0
0
Registers Reset to Zero
DAC register
Input register
DAC register
Input register
1 (Power-on Reset)
LDAC register
Power-down register
Internal reference setup register
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN MODES
The AD5623R/AD5643R/AD5663R contain four separate
modes of operation. Command 100 is reserved for the power-
down function (see Table 8). These modes are software-
programmable by setting Bit DB5 and Bit DB4 in the control
register. Table 11 shows how the state of the bits corresponds to
the mode of operation of the device. Any or all DACs (DAC B
and DAC A) can be powered down to the selected mode by
setting the corresponding two bits (Bit DB1 and Bit DB0) to 1.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 55. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string,
and other associated linear circuitry are shut down when
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time
to exit power-down is typically 4 µs for both VDD = 5 V and
VDD = 3 V (see Figure 37).
By executing the same Command 100, any combination of DACs
can be powered up by setting Bit DB5 and Bit DB4 to normal
operation mode.
Table 12. 24-Bit Input Shift Register Contents for Software Reset Command
MSB
LSB
DB23 to DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
DB0
x
1
0
1
x
x
x
x
1/0
Don’t care
Command bits (C2 to C0)
Address bits (A2 to A0)
Don’t care
Determines software reset mode
Rev. F | Page 22 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
Table 13. 24-Bit Input Shift Register Contents of Power Up/Down Function
MSB
LSB
DB23 to
DB22
DB15 to
DB21 DB20 DB19 DB18 DB17 DB16 DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
1
0
0
x
x
x
x
PD1
PD0
x
x
DAC B
DAC A
Don’t
care
Command bits (C2 to C0) Address bits (A2 to A0)
Don’t care
Don’t
care
Power-down
mode
Don’t care
Power down/Power up
channel selection;
set bit to 1 to select
channel
LDAC
Table 14. 24-Bit Input Shift Register Contents for
Setup Command
MSB
LSB
DB23 to
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB2
DB1
DAC B
DB0
x
1
1
0
x
x
x
x
DAC A
Don’t care
Command bits (C2 to C0)
Address bits (A3 to A0)
Don’t care
Don’t care
Set DAC to 0 or 1 for required
mode of operation
LDAC
LDAC FUNCTION
Asynchronous
The AD5623R/AD5643R/AD5663R DACs have double-
buffered interfaces consisting of two banks of registers: input
registers and DAC registers. The input registers are connected
directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC registers contain the digital code
used by the resistor strings.
The outputs are not updated at the same time that the input
LDAC
registers are updated with the contents of the input register.
registers are written to. When
goes low, the DAC
LDAC
The
the hardware
which combination of channels to simultaneously update when
LDAC LDAC
register gives the user full flexibility and control over
LDAC
pin. This register allows the user to select
the hardware
register to 0 for a DAC channel means that the update of this
LDAC
pin is executed. Setting the
bit
LDAC
Access to the DAC registers is controlled by the
pin.
pin is high, the DAC registers are latched and
the input registers can change state without affecting the
LDAC
LDAC
When the
channel is controlled by the
pin. If this bit is set to 1, this
channel synchronously updates; that is, the DAC register is
updated after new data is read in, regardless of the state of the
contents of the DAC registers. When
is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
LDAC
LDAC
pin. It effectively sees the
pin as being pulled low.
LDAC
See Table 15 for the
register mode of operation. This
flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
LDAC
low when writing to the other DAC input register, all
outputs will update simultaneously.
LDAC
Writing to the DAC using Command 110 loads the 2-bit
register [DB1:DB0]. The default for each channel is 0; that is,
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
LDAC
the
DAC register is updated, regardless of the state of the
pin. See Table 14 for contents of the input shift register during
LDAC
pin works normally. Setting the bits to 1 means the
LDAC
LDAC
LDAC
since the last time
was brought low. Normally, when
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5623R/AD5643R/
AD5663R, the DAC register updates only if the input register
has changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.
the
register setup command.
LDAC
Table 15.
Bits
Register Mode of Operation
LDAC
Pin
Operation
LDAC
LDAC
(DB1 to DB0)
The outputs of all DACs can be simultaneously updated, using
0
1/0
Determined by LDAC pin
LDAC
the hardware
pin.
1
x = don’t care The DAC registers are updated
after new data is read in on the
falling edge of the 24th SCLK
pulse.
LDAC
Synchronous
The DAC registers are updated after new data is read in on the
LDAC
falling edge of the 24th SCLK pulse.
low or pulsed as shown in Figure 2.
can be permanently
Rev. F | Page 23 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
Table 16. Reference Setup Register
INTERNAL REFERENCE SETUP
Internal Reference
Setup Register (DB0)
The on-chip reference is off at power-up by default. This
reference can be turned on or off by setting a software
programmable bit, DB0, in the control register. Table 16 shows
how the state of the bit corresponds to the mode of operation.
Command 111 is reserved for setting up the internal reference
(see Table 8). See Table 16 for the contents of the input shift
register during the internal reference setup command.
Action
Reference off (default)
0
1
Reference on
Table 17. 32-Bit Input Shift Register Contents for Reference Setup Function
MSB
LSB
DB23 to DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1 DB0
x
1
1
1
x
x
x
x
1/0
Don’t care
Command bits (C2 to C0)
Address bits (A2 to A0)
Don’t care
Reference
setup register
Rev. F | Page 24 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
transferred, and a second serial write operation is performed to
the DAC. PC7 is taken high at the end of this procedure.
MICROPROCESSOR INTERFACING
AD5623R/AD5643R/AD5663R to Blackfin® ADSP-BF53X
Interface
AD5623R/AD5643R/AD5663R to 80C51/80L51 Interface
Figure 56 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the Blackfin ADSP-BF53X micro-
processor. The ADSP-BF53X processor family incorporates two
dual-channel synchronous serial ports, SPORT1 and SPORT0,
for serial and multiprocessor communications. Using SPORT0
to connect to the AD5623R/AD5643R/AD5663R, the setup for
the interface is as follows: DT0PRI drives the DIN pin of the
AD5623R/AD5643R/AD5663R, while TSCLK0 drives the
Figure 58 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the 80C51/80L51 microcontroller.
The setup for the interface is as follows: TxD of the 80C51/
80L51 drives SCLK of the AD5623R/AD5643R/AD5663R,
SYNC
and RxD drives the serial data line of the part. The
signal
is again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5623R/AD5643R/AD5663R, P3.3 is taken low. The 80C51/
80L51 transmit data in 8-bit bytes only; thus, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this cycle.
SYNC
SCLK of the parts. The
is driven from TFS0.
1
AD5643R/
AD5663R1
ADSP-BF53x
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5623R/AD5643R/AD5663R must receive data
with the MSB first. The 80C51/80L51 transmit routine should
take this into account.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 56. AD5623R/AD5643R/AD5663R to Blackfin ADSP-BF53X Interface
AD5623R/AD5643R/AD5663R to 68HC11/68L11
Interface
1
AD5643R/
AD5663R1
SYNC
SCLK
DIN
80C51/80L51
P3.3
TxD
RxD
Figure 57 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5623R/
AD5643R/AD5663R, and the MOSI output drives the serial
data line of the DAC.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 58. AD5623R/AD5643R/AD5663R to 80C512/80L51 Interface
1
AD5643R/
AD5663R1
SYNC
SCLK
DIN
68HC11/68L11
AD5623R/AD5643R/AD5663R to MICROWIRE Interface
PC7
SCK
Figure 59 shows an interface between the AD5623R/AD5643R/
AD5663R and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5623R/AD5643R/AD5663R on the rising edge of the SK.
MOSI
1
ADDITIONAL PINS OMITTED FOR CLARITY.
1
AD5643R/
AD5663R1
MICROWIRE
Figure 57. AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface
CS
SYNC
SCLK
DIN
SYNC
The
signal is derived from a port line (PC7). The setup
SK
SO
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
line is taken low (PC7). When the 68HC11/68L11 is
Figure 59. AD5623R/AD5643R/AD5663R to MICROWIRE Interface
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. To load data to the AD5623R/
AD5643R/AD5663R, PC7 is left low after the first eight bits are
Rev. F | Page 25 of 32
AD5623R/AD5643R/AD5663R
Data Sheet
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
Because the supply current required by the AD5623R/AD5643R/
AD5663R is extremely low, an alternative option is to use a
voltage reference to supply the required voltage to the parts (see
Figure 60). This is especially useful if the power supply is quite
noisy or if the system supply voltages are at some value other
than 5 V or 3 V, for example, 15 V. The voltage reference outputs
a steady supply voltage for the AD5623R/AD5643R/ AD5663R.
If the low dropout REF195 is used, it must supply 500 µA of
current to the AD5623R/AD5643R/AD5663R, with no load on
the output of the DAC. When the DAC output is loaded, the
REF195 also needs to supply the current to the load. The total
current required (with a 5 kΩ load on the DAC output) is
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
AD820/
±5V
OP295
V
V
OUT
DD
10µF
0.1µF
AD5663R
–5V
THREE-WIRE
SERIAL
INTERFACE
Figure 61. Bipolar Operation with the AD5663R
500 µA + (5 V/5 kΩ) = 1.25 mA
USING THE AD5663R WITH A
GALVANICALLY ISOLATED INTERFACE
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 µV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.196 LSB error.
In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5663R uses a 3-wire serial logic interface, so
the ADuM1300 3-channel digital isolator provides the required
isolation (see Figure 62). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5663R.
15V
5V
REF195
V
DD
SYNC
SCLK
DIN
THREE-WIRE
SERIAL
INTERFACE
AD5623R/
AD5643R/
AD5663R
V
= 0V TO 5V
OUT
Figure 60. REF195 as Power Supply to the AD5623R/AD5643R/AD5663R
5V
BIPOLAR OPERATION USING THE AD5663R
REGULATOR
10µF
0.1µF
POWER
The AD5663R has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 61. The circuit gives an output voltage range of 5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
V
DD
SCLK
V
V
V
V
OA
SCLK
IA
ADuM1300
AD5663R
The output voltage for any input code can be calculated as
follows:
V
SDI
OUT
SYNC
V
IB
OB
OC
D
65,536
R1+ R2
R1
R2
R1
V
DATA
DIN
IC
V = V
×
×
− V
×
O
DD
DD
GND
where D represents the input code in decimal (0 to 65,535).
With VDD = 5 V, R1 = R2 = 10 kΩ,
Figure 62. AD5663R with a Galvanically Isolated Interface
10 × D
65,536
V =
− 5 V
O
Rev. F | Page 26 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
This 0.1 µF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5663R
should have separate analog and digital sections, each having its
own area of the board.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique, where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
If the AD5663R is in a system where other devices require an
AGND-to-DGND connection, the connection should be made at
one point only. This ground point should be as close as possible
to the AD5663R.
The power supply to the AD5663R should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be located as
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor
have low effective series resistance (ESR) and effective series
inductance (ESI), which is found, for example, in common
ceramic types of capacitors.
Rev. F | Page 27 of 32
AD5623R/AD5643R/AD5663R
OUTLINE DIMENSIONS
Data Sheet
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
6
10
PIN 1 INDEX
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
5
1
PIN 1
INDICATOR
TOP VIEW
BOTTOM VIEW
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 63. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm x 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 64. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. F | Page 28 of 32
Data Sheet
AD5623R/AD5643R/AD5663R
ORDERING GUIDE
Internal
Reference
Package
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
Package Description
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead MSOP
Option
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
CP-10-9
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
Branding
D±5
D±5
D±6
D±5
D±5
D±6
D±6
DKB
DKP
DKP
D±1
D±1
D7Q
D7Q
D7S
AD5623RBCPZ-3R2
AD5623RBCPZ-3REEL7
AD5623RBCPZ-5REEL7
AD5623RBRMZ-3
AD5623RBRMZ-3REEL7
AD5623RBRMZ-5
AD5623RBRMZ-5REEL7
AD5623RACPZ-5REEL7
AD5623RARMZ-5REEL7
AD5623RARMZ-5
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±2 LSB INL
±2 LSB INL
±2 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
1.25 V
1.25 V
2.5 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5V
2.5V
10-Lead MSOP
AD5643RBRMZ-3
AD5643RBRMZ-3REEL7
AD5643RBRMZ-5
AD5643RBRMZ-5REEL7
AD5663RBCPZ-3R2
AD5663RBCPZ-3REEL7
AD5663RBCPZ-5REEL7
AD5663RBRMZ-3
AD5663RBRMZ-3REEL7
AD5663RBRMZ-5
AD5663RBRMZ-5REEL7
EVAL-AD5663REBZ
1.25 V
1.25 V
2.5 V
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
2.5 V
1.25 V
1.25 V
2.5 V
1.25 V
1.25 V
2.5 V
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
D7S
D7H
D7S
D7S
D7H
D7H
2.5 V
10-Lead MSOP
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. F | Page 29 of 32
AD5623R/AD5643R/AD5663R
NOTES
Data Sheet
Rev. F | Page 30 of 32
Data Sheet
NOTES
AD5623R/AD5643R/AD5663R
Rev. F | Page 31 of 32
AD5623R/AD5643R/AD5663R
NOTES
Data Sheet
©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05858-0-2/13(F)
Rev. F | Page 32 of 32
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