EVAL-AD5667REBZ [ADI]
Dual, 12-/14-/16-Bit nanoDACs® with 5 ppm/°C On-Chip Reference, I2C® Interface; 双通道， 12位/ 14位/ 16位nanoDACs® 5 PPM / ° C片参考， I 2 C接口
| 型号： | EVAL-AD5667REBZ |
| 厂家： | 
ADI |
| 描述： | Dual, 12-/14-/16-Bit nanoDACs® with 5 ppm/°C On-Chip Reference, I2C® Interface |
| 文件： | 总32页 (文件大小：1546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, 12-/14-/16-Bit nanoDACs® with
5 ppm/°C On-Chip Reference, I2C® Interface
AD5627R/AD5647R/AD5667R, AD5627/AD5667
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
V
/V
DD
GND
REFIN REFOUT
Low power, smallest pin-compatible, dual nanoDACs
AD5627R/AD5647R/AD5667R
12-/14-/16-bit
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
AD5627/AD5667
AD5627R/AD5647R/AD5667R
1.25V/2.5V REF
BUFFER
BUFFER
ADDR
SCL
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
V
A
B
OUT
OUT
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
12-/16-bit
External reference only
V
SDA
POWER-ON
RESET
POWER-DOWN
LOGIC
3 mm x 3 mm LFCSP and 10-lead MSOP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
LDAC CLR
Figure 1. AD5627R/AD5647R/AD5667R
V
V
REFIN
DD
GND
LDAC
CLR
functions
Hardware
and
AD5627/AD5667
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
BUFFER
BUFFER
ADDR
SCL
INPUT
DAC
STRING
DAC A
V
V
A
B
OUT
REGISTER
REGISTER
APPLICATIONS
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
OUT
SDA
Process control
POWER-ON
RESET
POWER-DOWN
LOGIC
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
LDAC CLR
Figure 2. AD5627/AD5667
GENERAL DESCRIPTION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667
members of the nanoDAC family are low power, dual, 12-, 14-,
16-bit buffered voltage-out DACs with/without on-chip
reference. All devices operate from a single 2.7 V to 5.5 V
supply, are guaranteed monotonic by design, and have an I2C-
compatible serial interface.
software-selectable output loads while in power-down mode.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The on-chip precision output amplifier enables rail-to-rail
output swing.
The AD56x7R/AD56x7 use a 2-wire I2C-compatible serial
interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.
The AD5627R/AD5647R/AD5667R have an on-chip reference.
The AD56x7RBCPZ have a 1.25 V, 5 ppm/°C reference, giving a
full-scale output range of 2.5 V; the AD56x7RBRMZ have a
2.5 V, 5 ppm/°C reference, giving a full-scale output range of 5
V. The on-chip reference is off at power-up, allowing the use of
an external reference. The internal reference is enabled via a
software write. The AD5667 and AD5627 require an external
reference voltage to set the output range of the DAC.
Table 1. Related Devices
Part No.
Description
AD5663
2.7 V to 5.5 V, dual 16-bit DAC,
external reference, SPI® interface
AD5623R/AD5643R/AD5663R
2.7 V to 5.5 V, dual 12-, 14-, 16-bit
DACs, internal reference,
SPI interface
The AD56x7R/AD56x7 incorporate a power-on reset circuit
that ensures the DAC output powers up to 0 V, and remains
there until a valid write takes place. The part contains a per-
channel power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
AD5625R/AD5645R/AD5665R,
AD5625/AD5665
2.7 V to 5.5 V, quad 12-, 14-, 16-bit
DACs, with/without internal
reference, I2C interface
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD5627R/AD5647R/AD5667R, AD5627/AD5667
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface............................................................................ 21
Write Operation.......................................................................... 21
Read Operation........................................................................... 21
High Speed Mode....................................................................... 21
Input Shift Register .................................................................... 23
Multiple Byte Operation............................................................ 23
Broadcast Mode.......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
I2C Timing Specifications............................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
D/A Section................................................................................. 20
Resistor String............................................................................. 20
Output Amplifier........................................................................ 20
Internal reference........................................................................ 20
External reference....................................................................... 20
LDAC
Function .......................................................................... 23
Power-Down Modes .................................................................. 25
Power-On Reset and Software Reset ....................................... 26
CLR
Clear Pin (
).......................................................................... 26
Internal Reference Setup (R Versions) .................................... 26
Application Information................................................................ 27
Using a Reference as a Power Supply for the
AD56x7R/AD56x7..................................................................... 27
Bipolar Operation Using the AD56x7R/AD56x7 .................. 27
Power Supply Bypassing and Grounding................................ 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 29
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min
Typ
±±
Max
Unit
Conditions/Comments1
STATIC PERFORMANCE2
AD5667R/AD5667
Resolution
Relative Accuracy
Differential Nonlinearity
AD5647R
16
Bits
LSB
LSB
±12
±1
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5627R/AD5627
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
±2
±4
±0.5
Bits
LSB
LSB
mV
mV
±0.5
±1
±0.25
10
±10
±1
Guaranteed monotonic by design
All 0s loaded to DAC register
2
±1
−0.1
Offset Error
Full-Scale Error
% of FSR All 1s loaded to DAC register
Gain Error
±1.5
% of FSR
μV/°C
ppm
dB
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk (External Reference)
±2
±2.5
−100
15
Of FSR/°C
DAC code = midscale ; VDD = 5 V ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
μV
10
±
μV/mA
μV
Due to load current change
Due to powering down (per channel)
DC Crosstalk (Internal Reference)
25
μV
Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
20
10
μV/mA
μV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
V
Capacitive Load Stability
2
nF
nF
Ω
mA
μs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
110
50
130
VDD
μA
V
kΩ
VREF = VDD = 5.5 V
0.75
REFERENCE OUTPUT
(LFCSP_WD PACKAGE)
Output Voltage
Reference TC3
Output Impedance
REFERENCE OUTPUT (MSOP PACKAGE)
Output Voltage
Reference TC3
Output Impedance
1.247
1.253
V
At ambient
At ambient
±10
7.5
ppm/°C
kΩ
2.495
2.505
±10
V
±5
7.5
ppm/°C
kΩ
Rev. 0 | Page 3 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Parameter
Min
Typ
Max
Unit
Conditions/Comments1
LOGIC INPUTS (ADDR, CLR, LDAC)3
IIN, Input Current
±1
0.15 × VDD
μA
V
V
pF
pF
V
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
0.±5 × VDD
0.1 × VDD
2
20
ADDR
CLR, LDAC
VHYST, Input Hysteresis
LOGIC INPUTS (SDA, SCL)
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
LOGIC OUTPUTS (OPEN-DRAIN)
VOL, Output Low Voltage
±1
0.3 × VDD
μA
V
V
pF
V
0.7 × VDD
0.1 × VDD
2
2
0.4
0.6
±1
V
V
μA
pF
ISINK = 3 mA
ISINK = 6 mA
Floating-State Leakage Current
Floating-State Output Capacitance
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)4
VIH = VDD, VIL = GND
Internal reference off
Internal reference off
Internal reference on
Internal reference on
VIH = VDD, VIL = GND
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
0.4
0.5
mA
mA
mA
mA
μA
0.35
0.95
0.±
0.45
1.15
0.95
1
IDD (All Power-Down Modes)5
0.4±
1 Temperature range: B grade: −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5567R/AD5667 (Code 512 to Code 65,024); AD5647R (Code 12± to Code 16,256); AD5627R/AD5627 (Code 32 to
Code 4064). Output unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down.
Rev. 0 | Page 4 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2
Min
Typ
Max
Unit
Conditions/Comments3
Output Voltage Settling Time
AD5627R/AD5627
AD5647R
AD5667R/AD5667
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
3
3.5
4
1.±
15
0.1
−90
0.1
1
4
1
4
340
−±0
120
100
15
4.5
5
7
μs
μs
μs
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±2 LSB
V/μs
nV-s
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
1 LSB change around major carry transition
VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Analog Crosstalk
External reference
Internal reference
External reference
Internal reference
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
VREF = 2 V ± 0.1 V p-p
dB
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
μV p-p
Output Noise
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
Rev. 0 | Page 5 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 4.
Parameter Conditions2
Min Max Unit Description
3
fSCL
Standard mode
100
400
3.4
kHz
kHz
MHz
MHz
ꢀs
ꢀs
ns
ns
ꢀs
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
1.7
t1
4
0.6
Fast mode
High speed mode, CB = 100 pF 60
High speed mode, CB = 400 pF 120
t2
Standard mode
Fast mode
4.7
1.3
ꢀs
High speed mode, CB = 100 pF 160
High speed mode, CB = 400 pF 320
ns
ns
t3
t4
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
250
100
10
0
ns
ns
ns
ꢀs
tSU;DAT, data setup time
tHD;DAT, data hold time
3.45
0.9
0
ꢀs
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF 10
High speed mode, CB = 400 pF 20
Standard mode
0
0
70
150
ns
ns
ꢀs
ꢀs
ns
ꢀs
ꢀs
ns
ꢀs
ꢀs
ꢀs
ꢀs
t5
t6
4.7
0.6
160
4
0.6
160
4.7
1.3
4
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
t7
t±
tBUF, bus free time between a stop and a start condition
tSU;STO, setup time for a stop condition
0.6
160
ns
t9
1000 ns
300
±0
160
300
300
±0
160
1000 ns
300
40
±0
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
ns
ns
ns
ns
ns
ns
ns
t10
t11
t11A
Fast mode
High speed mode, CB = 100 pF 10
High speed mode, CB = 400 pF 20
Standard mode
Fast mode
ns
ns
ns
High speed mode, CB = 100 pF 10
High speed mode, CB = 400 pF 20
Standard mode
1000 ns
tRCL1, rise time of SCL signal after a repeated start condition and after
an acknowledge bit
Fast mode
High speed mode, CB = 100 pF 10
High speed mode, CB = 400 pF 20
300
±0
160
ns
ns
ns
Rev. 0 | Page 6 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Parameter Conditions2
Min Max Unit Description
t12
Standard mode
Fast mode
High speed mode, CB = 100 pF 10
High speed mode, CB = 400 pF 20
Standard mode
Fast mode
300
300
40
ns
ns
ns
ns
ns
ns
ns
ns
tFCL, fall time of SCL signal
±0
t13
10
LDAC pulse width low
10
10
300
High speed mode
Standard mode
t14
Falling edge of 9th SCL clock pulse of last byte of valid write to LDAC
falling edge
Fast mode
300
30
20
20
20
0
ns
ns
ns
ns
ns
ns
ns
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
t15
CLR pulse width low
4
tSP
50
10
Pulse width of spike suppressed
High speed mode
0
1 See Figure 3. High speed mode timing specification applies only to the AD5627RBRMZ-2/AD5627BRMZ-2REEL7 and AD5667RBRMZ-2/AD5667BRMZ-2REEL7.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
t11
t12
t6
t2
t6
SCL
SDA
t1
t3
t5
t10
t8
t4
t9
t7
P
S
S
P
t14
t13
LDAC*
CLR
t15
*ASYNCHRONOUS LDAC UPDATE MODE.
Figure 3. 2-Wire Serial Interface Timing Diagram
Rev. 0 | Page 7 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
VDD to GND
VOUT to GND
VREFIN/VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range, Industrial
Storage Temperature Range
Junction Temperature (TJ maximum)
Power Dissipation
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
ESD CAUTION
(TJ max − TA)/θJA
θJA Thermal Impedance
LFCSP_WD Package (4-Layer Board)
MSOP Package
61°C/W
150.4°C/W
260°C ± 5°C
Reflow Soldering Peak Temperature, Pb-Free
Rev. 0 | Page ± of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
10
1
2
3
4
5
10
V
A
V
V
A
V
/V
OUT
REFIN
OUT
REFIN REFOUT
AD5627/
AD5667
AD5627R/
AD5647R/
AD5667R
TOP VIEW
(Not to Scale)
9
9
V
B
V
V
B
V
OUT
DD
OUT
DD
8
8
GND
SDA
GND
SDA
7
7
LDAC
CLR
SCL
LDAC
CLR
SCL
TOP VIEW
(Not to Scale)
6
6
ADDR
ADDR
EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE.
EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE.
Figure 4. AD5627/AD5667 Pin Configuration
Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration
Table 6. Pin Function Descriptions
Pin
No.
Mnemonic Description
1
2
3
4
VOUT
VOUT
GND
A
B
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows
simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.
LDAC
5
CLR
Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored.
When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits
clear code mode on the falling edge of the 9th clock pulse of the last byte of valid write. If CLR is activated during a
write sequence, the write is aborted. If CLR is activated during high speed mode the part will exit high speed mode.
6
7
±
ADDR
SCL
SDA
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
9
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 ꢀF capacitor in parallel with a 0.1 ꢀF capacitor to GND.
10
VREFIN/VREFOUT The AD56x7R have a common pin for reference input and reference output. When using the internal reference, this is
the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is
as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD56x7
has a reference input pin only.
Rev. 0 | Page 9 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
10
V
T
= V
= 5V
V
T
= V = 5V
REF
DD
REF
DD
= 25°C
= 25°C
A
0.8
0.6
0.4
0.2
8
A
6
4
2
0
–2
–4
0
–0.2
–0.4
–0.6
–6
–8
–0.8
–1.0
–10
0
10k
20k
30k
CODE
40k
50k
60k
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
Figure 9. AD5667 DNL, External Reference
Figure 6. AD5667 INL, External Reference
4
0.5
V
= V = 5V
REF
DD
= 25°C
V
= V
= 5V
DD
REF
T
A
0.4
0.3
0.2
0.1
T = 25°C
A
3
2
1
0
0
–0.1
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0
2500
5000
7500
CODE
10000
12500
15000
0
2500
5000
7500
CODE
10000
12500
15000
Figure 7. AD5647R INL, External Reference
Figure 10. DNL AD5647R, External Reference
1.0
0.20
0.15
0.10
0.05
0
V
= V
= 25°C
= 5V
V
= V = 5V
REF
DD
REF
DD
T = 25°C
A
T
0.8
0.6
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
0
500
1000
1500 2000
CODE
2500 3000 3500 4000
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
Figure 8. AD5627 INL, External Reference
Figure 11. AD5627 DNL, External Reference
Rev. 0 | Page 10 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
1.0
10
8
V
V
= 5V
V
V
= 5V
DD
DD
0.8
0.6
0.4
0.2
= 2.5V
= 2.5V
REFOUT
REFOUT
TA = 25°C
TA = 25°C
6
4
2
0
0
–0.2
–2
–0.4
–0.6
–4
–6
–0.8
–1.0
–8
–10
CODE
CODE
Figure 15. AD5667R DNL, 2.5 V Internal Reference
Figure 12. AD5667R INL, 2.5 V Internal Reference
4
0.5
0.4
0.3
0.2
0.1
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REFOUT
REFOUT
3
2
TA = 25°C
TA = 25°C
1
0
0
–0.1
–1
–2
–0.2
–0.3
–3
–4
–0.4
–0.5
CODE
CODE
Figure 13. AD5647R INL, 2.5 V Internal Reference
Figure 16. AD5647R DNL, 2.5 V Internal Reference
1.0
0.20
0.15
0.10
0.05
V
= 5V
V
V
= 5V
DD
DD
V
T
= 2.5V
0.8
0.6
0.4
0.2
= 2.5V
REFOUT
= 25°C
REFOUT
TA = 25°C
A
0
–0.2
–0.4
–0.6
0
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000
1500 2000 2500 3000
CODE
3500 4000
0
500
1000
1500 2000 2500 3000
CODE
3500 4000
Figure 14. AD5627R INL, 2.5 V Internal Reference
Figure 17. AD5627R DNL, 2.5 V Internal Reference
Rev. 0 | Page 11 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
10
1.0
V
V
= 3V
= 1.25V
= 25°C
V
V
= 3V
DD
REFOUT
DD
REFOUT
= 25°C
8
6
0.8
0.6
= 1.25V
T
T
A
A
4
0.4
2
0.2
0
0
–2
–4
–6
–0.2
–0.4
–0.6
–8
–0.8
–1.0
–10
CODE
CODE
Figure 18. AD5667R INL,1.25 V Internal Reference
Figure 21. AD5667R DNL,1.25 V Internal Reference
4
3
0.5
0.4
0.3
0.2
0.1
0
V
V
= 3V
= 1.25V
= 25°C
V
V
T
= 3V
= 1.25V
= 25°C
A
DD
REFOUT
DD
REFOUT
T
A
2
1
0
–0.1
–0.2
–0.3
–1
–2
–3
–4
–0.4
–0.5
CODE
CODE
Figure 19. AD5647R INL, 1.25 V Internal Reference
Figure 22. AD5647R DNL,1.25 V Internal Reference
1.0
0.8
0.20
0.15
0.10
0.05
0
V
V
= 3V
= 1.25V
= 25°C
V
V
T
= 3V
= 1.25V
= 25°C
A
DD
REFOUT
DD
REFOUT
T
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
Figure 20. AD5627R INL,1.25 V Internal Reference
Figure 23. AD5627R DNL, 1.25 V Internal Reference
Rev. 0 | Page 12 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
8
6
0
V
= 5V
DD
–0.02
–0.04
–0.06
–0.08
MAX INL
V
= V = 5V
REF
DD
GAIN ERROR
4
2
MAX DNL
MIN DNL
0
–0.10
–0.12
–2
–4
–6
–8
–0.14
–0.16
FULL-SCALE ERROR
MIN INL
80
–0.18
–0.20
–40
–20
0
20
40
60
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. INL Error and DNL Error vs. Temperature
Figure 27. Gain Error and Full-Scale Error vs. Temperature
10
8
1.5
MAX INL
1.0
ZERO-SCALE ERROR
6
0.5
0
V
= 5V
DD
= 25°C
4
T
A
2
MAX DNL
MIN DNL
–0.5
–1.0
–1.5
–2.0
–2.5
0
–2
–4
–6
OFFSET ERROR
MIN INL
4.25
–8
–10
0.75 1.25
1.75
2.25
2.75
3.25
(V)
3.75
4.75
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
REF
Figure 28. Zero-Scale Error and Offset Error vs. Temperature
Figure 25. INL and DNL Error vs. VREF
8
6
1.0
MAX INL
0.5
T
= 25°C
A
4
2
GAIN ERROR
0
MAX DNL
MIN DNL
FULL-SCALE ERROR
–0.5
0
–2
–4
–6
–8
–1.0
MIN INL
–1.5
–2.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
V
DD
DD
Figure 26. INL and DNL Error vs. Supply
Figure 29. Gain Error and Full-Scale Error vs. Supply
Rev. 0 | Page 13 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
0.5
1.0
T
= 25°C
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
A
0.4
0.3
0.5
0
ZERO-SCALE ERROR
0.2
V
V
= 3V
0.1
DD
REFOUT
–0.5
–1.0
–1.5
= 1.25V
0
–0.1
–0.2
–0.3
V
V
= 5V
DD
= 2.5V
–2
REFOUT
–2.0
–2.5
OFFSET ERROR
–0.4
–0.5
2.7
3.2
3.7
4.2
(V)
4.7
5.2
–10
–8
–6
–4
0
2
4
6
8
10
V
CURRENT (mA)
DD
Figure 30. Zero-Scale Error and Offset Error vs. Supply
Figure 33. Headroom at Rails vs. Source and Sink
6
18
16
14
12
10
8
V
V
= 3.6V
= 5.5V
DD
DD
V
V
= 5V
= 2.5V
= 25°C
DD
REFOUT
FULL SCALE
5
4
3
2
1
T
A
3/4 SCALE
MIDSCALE
1/4 SCALE
6
4
0
ZERO SCALE
2
–1
–30
0
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
–20
–10
0
10
20
30
I
(mA)
CURRENT (mA)
DD
Figure 34. AD56x7R with 2.5 V Reference, Source and Sink Capability
Figure 31. IDD Histogram with External Reference
14
12
10
8
4
V
V
= 3.6V
= 5.5V
DD
V
V
= 3V
= 1.25V
= 25°C
DD
REFOUT
V
= 1.25V
REFOUT
DD
T
A
3
2
1
FULL SCALE
3/4 SCALE
MIDSCALE
1/4 SCALE
V
= 2.5V
REFOUT
6
4
0
ZERO SCALE
2
–1
–30
0
–20
–10
0
10
20
30
CURRENT (mA)
I
(mA)
DD
Figure 32. IDD Histogram with Internal Reference
Figure 35. AD56x7R with 1.25 V Reference, Source and Sink Capability
Rev. 0 | Page 14 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
A
V
= 5V, V = 2.5V
REFOUT
DD
V
= V
= 25°C
= 5V
DD
REF
T
A
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
V
= V = 5V
REF
DD
V
= 909mV/DIV
OUT
1
512
10512
20512
30512
CODE
40512
50512
60512
TIME BASE = 4µs/DIV
Figure 36. Supply Current vs. Code
Figure 39. Full-Scale Settling Time, 5 V
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= V
= 25°C
= 5V
DD
REF
T
A
V
DD
1
2
MAX(C2)
420.0mV
V
OUT
T
= 25°C
A
CH1 2.0V
CH2 500mV
M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
3.7
4.2
4.7
5.2
2.7
3.2
SUPPLY VOLTAGE (V)
Figure 37. Supply Current vs. Supply Voltage
Figure 40. Power-On Reset to 0 V
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
SYNC
SLCK
V
= V
REFIN
= 5V
= 3V
DD
1
3
V
= V
REFIN
DD
V
OUT
V
= 5V
DD
2
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 38. Supply Current vs. Temperature
Figure 41. Exiting Power-Down to Midscale
Rev. 0 | Page 15 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
2.538
V
T
= V
= 25°C
= 5V
V
T
= V = 5V
REF
DD
REF
DD
= 25°C
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
A
A
DAC LOADED WITH MIDSCALE
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
1
4s/DIV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 42. Digital-to-Analog Glitch Impulse (Negative)
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
V
V
= 5V
V
= V = 5V
REF
DD
REFOUT
= 25°C
DD
= 25°C
= 2.5V
T
A
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
DAC LOADED WITH MIDSCALE
1
0
50
100 150 200 250 300 350 400 450 512
SAMPLE NUMBER
5s/DIV
Figure 43. Analog Crosstalk, External Reference
Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
2.496
2.494
2.492
2.490
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
2.468
2.466
2.464
2.462
2.460
2.458
2.456
V
V
= 3V
DD
REFOUT
= 25°C
= 1.25V
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
DD
REFOUT
= 25°C
= 2.5V
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
4s/DIV
Figure 47. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference
Figure 44. Analog Crosstalk, Internal Reference
Rev. 0 | Page 16 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
800
700
600
500
400
300
200
16
T
= 25°C
V
= V
DD
= 25°C
A
REF
MIDSCALE LOADED
T
A
14
12
10
8
V
= 3V
DD
V
= 5V
DD
V
V
= 5V
DD
REFOUT
= 2.5V
6
4
V
V
= 3V
100
0
DD
REFOUT
= 1.25V
1k
100
10k
FREQUENCY (Hz)
100k
1M
0
1
2
3
4
5
6
7
8
9
10
CAPACITANCE (nF)
Figure 48. Noise Spectral Density, Internal Reference
Figure 50. Settling Time vs. Capacitive Load
–20
–30
–40
5
0
V
T
= 5V
= 25°C
V
T
= 5V
DD
A
DD
= 25°C
A
DAC LOADED WITH FULL SCALE
= 2V ± 0.3V p-p
V
REF
–5
–10
–15
–20
–25
–30
–35
–40
–50
–60
–70
–80
–90
–100
2k
4k
6k
8k
10k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 49. Total Harmonic Distortion
Figure 51. Multiplying Bandwidth
Rev. 0 | Page 17 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 42).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of 1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero scale (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5667R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in %
of full-scale range (FSR).
Output Noise Spectral Density
Output noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density. It is measured by loading the DAC to midscale
and measuring noise at the output. It is measured in nV/√Hz. A
plot of noise spectral density can be seen in Figure 48.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed in % of FSR.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in ꢀV.
Zero-Code Error Drift
Zero-code error drift is a measurement of the change in zero-
code error with a change in temperature. It is expressed in μV/°C.
Gain Temperature Coefficient
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Digital Crosstalk
Offset Error
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in nV-s.
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5667R
with code 512 loaded in the DAC register. It can be negative or
positive.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dB. VREF is held at 2 V and VDD is varied by 10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge of
the stop condition.
Rev. 0 | Page 1± of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Analog Crosstalk
Multiplying Bandwidth
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa), then executing a
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
LDAC
software
and monitoring the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
LDAC
to all 1s and vice versa) with
low while monitoring the
output of the victim channel that is at midscale. The energy of
the glitch is expressed in nV-s.
Rev. 0 | Page 19 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
THEORY OF OPERATION
D/A SECTION
R
The AD56x7R/AD56x7 DACs are fabricated on a CMOS
process. The architecture consists of a string DAC followed by
an output buffer amplifier. Figure 52 shows a block diagram of
the DAC architecture.
R
R
TO OUTPUT
AMPLIFIER
V
DD
OUTPUT
AMPLIFIER
GAIN = +2
REF (+)
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
R
R
GND
Figure 52. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
Figure 53. Resistor String
INTERNAL REFERENCE
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = VREFIN
×
2N
The AD5627R/AD5647R/AD5667R feature an on-chip
reference. Versions without the R suffix require an external
reference. The on-chip reference is off at power-up and is
enabled via a write to a control register. See the Internal
Reference Setup section for details.
The ideal output voltage when using the internal reference is
given by
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = 2×VREFOUT
×
2N
Versions packaged in a 10-lead LFCSP package have a 1.25 V
reference, giving a full-scale output of 2.5 V. These parts can be
operated with a VDD supply of 2.7 V to 5.5 V. Versions packaged
in a 10-lead MSOP package have a 2.5 V reference, giving a full-
scale output of 5 V. The parts are functional with a VDD supply
of 2.7 V to 5.5 V, but with a VDD supply of less than 5 V, the
output is clamped to VDD. See the Ordering Guide for a full list
of models. The internal reference associated with each part is
available at the VREFOUT pin.
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 4095 for AD5627R/AD5627 (12-bit).
0 to 16,383 for AD5647R (14-bit).
0 to 65,535 for AD5667R/AD5667 (16-bit).
N is the DAC resolution.
RESISTOR STRING
A buffer is required if the reference output is used to drive
external loads. When using the internal reference, it is
recommended that a 100 nF capacitor be placed between the
reference output and GND for reference stability.
The resistor string is shown in Figure 53. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
EXTERNAL REFERENCE
The AD5627/AD5667 require an external reference, which is
applied at the VREFIN pin. The VREFIN pin on the AD56x7R allows
the use of an external reference if the application requires it.
The default condition of the on-chip reference is off at power-
up. All devices can be operated from a single 2.7 V to 5.5 V supply.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can drive
a load of 2 kꢁ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 33
and Figure 34. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale
settling time of 7 μs.
Rev. 0 | Page 20 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
SERIAL INTERFACE
WRITE OPERATION
The AD56x7R/AD56x7 have 2-wire I2C-compatible serial
interfaces (refer to I2C-Bus Specification, Version 2.1, January 2000,
available from Philips Semiconductor). The AD56x7R/AD56x7
can be connected to an I2C bus as a slave device, under the control
of a master device. See Figure 3 for a timing diagram of a
typical write sequence.
When writing to the AD56x7R/AD56x7, the user must begin
W
with a start command followed by an address byte (R/ = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD56x7R/AD56x7 requires two
bytes of data for the DAC and a command byte that controls
various DAC functions. Three bytes of data must therefore be
written to the DAC, the command byte followed by the most
significant data byte and the least significant data byte, as
shown in Figure 54. All these data bytes are acknowledged by
the AD56x7R/AD56x7. A stop condition follows.
The AD56x7R/AD56x7 support standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) data transfer modes.
High speed operation is only available on select models. See
the Ordering Guide for a full list of models. Support is not
provided for 10-bit addressing and general call addressing.
READ OPERATION
The AD56x7R/AD56x7 each have a 7-bit slave address. The five
MSBs are 00011 and the two LSBs (A1, A0) are set by the state
of the ADDR address pin. The facility to make hardwired
changes to ADDR allows the user to incorporate up to three of
these devices on one bus, as outlined in Table 7.
When reading data back from the AD56x7R/AD56x7, the user
begins with a start command followed by an address byte
W
(R/ = 1), after which the DAC acknowledges that it is
prepared to transmit data by pulling SDA low. Three bytes of
data are then read from the DAC, which are acknowledged by
the master, as shown in Figure 55. A stop condition follows.
Table 7. Device Address Selection
HIGH SPEED MODE
ADDR Pin Connection
A1
0
1
A0
0
0
VDD
The AD5627RBRMZ and the AD5667RBRMZ offer high speed
serial communication with a clock frequency of 3.4 MHz. See
the Ordering Guide for details.
No Connection
GND
1
1
High speed mode communication commences after the master
addresses all devices connected to the bus with the Master Code
00001XXX to indicate that a high speed mode transfer is to
begin (see Figure 56). No device connected to the bus is
permitted to acknowledge the high speed master code.
Therefore, the code is followed by a no acknowledge. The
master must then issue a repeated start followed by the device
address. The selected device then acknowledges its address.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the 9th clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to, or read from, its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
All devices continue to operate in high speed mode until the
master issues a stop condition. When the stop condition is
issued, the devices return to standard/fast mode. The part also
CLR
returns to standard/fast mode when
part is in high speed mode.
is activated while the
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the 9th clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, and then high during the 10th
clock pulse to establish a stop condition.
Rev. 0 | Page 21 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
1
9
1
9
SCL
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
SDA
ACK. BY
AD56x7
ACK. BY
AD56x7
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
STOP BY
MASTER
ACK. BY
AD56x7
ACK. BY
AD56x7
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 54. I2C Write Operation
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK. BY
AD56x7
ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
STOP BY
MASTER
ACK. BY
MASTER
NO ACK.
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 55. I2C Read Operation
FAST MODE
HIGH-SPEED MODE
1
9
1
9
SCL
SDA
0
0
0
0
1
X
X
X
0
0
0
1
1
A1
A0
R/W
NO ACK
SR
START BY
MASTER
ACK. BY
AD56x7
HS-MODE
MASTER CODE
SERIAL BUS
ADDRESS BYTE
Figure 56. Placing the AD5627RBRMZ-2/AD5667RBRMZ-2 in High Speed Mode
Rev. 0 | Page 22 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
INPUT SHIFT REGISTER
Table 9. DAC Address Command
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure 3.
The 8 MSBs make up the command byte. DB23 is reserved and
should always be set to 0 when writing to the device. DB22 (S)
is used to select multiple byte operation The next three bits are
the command bits (C2, C1, C0) that control the mode of operation
of the device. See Table 8 for details. The last 3 bits of first byte
are the address bits (A2, A1, A0). See Table 9 for details. The
rest of the bits are the 16-, 14-, 12-bit data word. The data word
comprises the 16-, 14-, 12-bit input code followed by two or four
don’t cares for the AD5647R and the AD5627R/AD5627,
respectively (see Figure 59 through Figure 61).
A2
A1
A0
ADDRESS (n)
0
0
1
0
0
1
0
1
1
DAC A
DAC B
Both DACs
LDAC FUNCTION
The AD56x7R/AD56x7 DACs have double-buffered interfaces
consisting of two banks of registers, input registers and DAC
registers. The input registers are connected directly to the input
shift register, and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The
DAC registers contain the digital codes used by the resistor strings.
LDAC
Access to the DAC registers is controlled by the
pin.
pin is high, the DAC registers are latched and
the input registers can change state without affecting the
LDAC
MULTIPLE BYTE OPERATION
LDAC
When the
Multiple byte operation is supported on the AD56x7R/AD56x7.
A 2-byte operation is useful for applications that require fast
DAC updating and do not need to change the command byte.
The S bit (DB22) in the command register can be set to 1 for 2-
byte mode of operation (see Figure 57). For standard 3-byte
and 4-byte operation, the S bit (DB22) in the command byte
should be set to 0 (see Figure 58).
contents of the DAC registers. When
is brought low,
however, the DAC registers become transparent and the contents
of the input registers are transferred to them. The double-
buffered interface is useful if the user requires simultaneous
updating of all DAC outputs. The user can write to one of the
LDAC
input registers individually and then, by bringing
low
when writing to the other DAC input register, all outputs
update simultaneously.
BROADCAST MODE
Broadcast addressing is supported on the AD56x7R/AD56x7.
Broadcast addressing can be used to synchronously update or
power down multiple AD56x7R/AD56x7 devices. Using the
broadcast address, the AD56x7R/AD56x7 responds regardless of
the states of the address pins. Broadcast is supported only in write
mode. The AD56x7R/AD56x7 broadcast address is 00010000.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
LDAC
LDAC
since the last time
was brought low. Normally, when
is brought low, the DAC registers are filled with the contents of the
input registers. In the case of the AD56x7R/AD56x7, the DAC
register updates only if the input register has changed since the
last time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
Table 8. Command Definition
C2 C1 C0 Command
0
0
0
0
0
1
0
1
0
Write to input register n
Update DAC register n
Write to input register n, update all
The outputs of all DACs can be simultaneously updated, using
LDAC
the hardware
pin.
(software LDAC)
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Write to and update DAC channel n
Power up/power down
Reset
LDAC register setup
Internal reference setup (on/off )
Rev. 0 | Page 23 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
BLOCK 1
BLOCK 2
BLOCK n
S = 1
S = 1
S = 1
SLAVE
ADDRESS
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT
BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE
MOST SIGNIFICANT LEAST SIGNIFICANT
STOP
DATA BYTE
DATA BYTE
Figure 57. Multiple Block Write with Initial Command Byte Only (S = 1)
BLOCK 1
BLOCK 2
BLOCK n
S = 0
S = 0
S = 0
SLAVE
ADDRESS
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT
BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT
STOP
BYTE
DATA BYTE
DATA BYTE
Figure 58. Multiple Block Write with Command Byte in Each Block (S = 0)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R
S
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 59. AD5667R/AD5667 Input Shift Register (16-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R
S
C2
C1
C0
A2
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 60. AD5647R Input Shift Register (14-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R
S
C2
C1
C0
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 61. AD5627R/AD5627 Input Shift Register (12-Bit DAC)
Rev. 0 | Page 24 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
amplifier, as shown in Table 11. Bit DB1and Bit DB0 determine
to which DAC or DACs the power-up/down command is
applied. Setting one of these bits to 1 applies the power-up/down
state defined by DB5 and DB4 to the corresponding DAC. If a
bit is 0, the state of the DAC is unchanged. Figure 65 shows the
contents of the input shift register for the power up/down
command.
LDAC
Synchronous
LDAC
The DAC registers are updated after new data is read in.
can be permanently low or pulsed.
LDAC
Asynchronous
The outputs are not updated at the same time that the input
LDAC
registers are written to. When
registers are updated with the contents of the input register.
LDAC
goes low, the DAC
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 400 μA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 kꢁ or 100 kꢁ resistor, or left
open-circuited (three-state) as shown in Figure 62.
The
the hardware
which combination of channels to simultaneously update when
LDAC LDAC
register gives the user full flexibility and control over
LDAC
pin. This register allows the user to select
the hardware
register to 0 for a DAC channel means that the update of this
LDAC
pin is executed. Setting the
bit
channel is controlled by the
pin. If this bit is set to 1, this
channel synchronously updates, that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC
LDAC
pin. It effectively sees the
pin as being pulled low.
LDAC
See Table 10 for the
register mode of operation. This
Table 11. Modes of Operation for the AD56x7R/AD56x7
flexibility is useful in applications when the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
DB5
DB4
Operating Mode
0
0
Normal operation
Power-down modes
0
1
1
1
0
1
1 kΩ pull-down to GND
100 kΩ pull-down to GND
Three-state, high impedance
LDAC
Writing to the DAC using Command 110 loads the 2-bit
register [DB1:DB0]. The default for each channel is 0, that is,
LDAC
the
DAC register is updated, regardless of the state of the
pin. See Figure 63 for contents of the input shift register during
LDAC
pin works normally. Setting the bits to 1 means the
LDAC
the
Table 10.
register setup command.
LDAC
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
Register Mode of Operation:
Load DAC Register
LDAC Bits
(DB1 to DB0)
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
LDAC Pin
1/0
LDAC Operation
0
Determined by LDAC pin.
Figure 62. Output Stage During Power-Down
1
x = don’t care The DAC registers are updated
after new data is read in.
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 μs for VDD = 5 V.
POWER-DOWN MODES
Command 100 is reserved for the power-up/down function.
The power-up/down modes are programmed by setting Bit
DB5 and Bit DB4. This defines the output state of the DAC
R
0
S
X
C2
1
C1
1
C0
0
A2
A2
A1
A1
A0
A0
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DACB DACA
DAC ADDRESS
(DON’T CARE)
COMMAND
DON’T CARE
DON’T CARE
DAC SELECT
(0 = LDAC PIN ENABLED)
LDAC
Figure 63.
Setup Command
Rev. 0 | Page 25 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
POWER-ON RESET AND SOFTWARE RESET
CLEAR PIN (CLR)
The AD56x7R/AD56x7 contain a power-on reset circuit that
controls the output voltage during power-up. The device powers
up to 0 V and the output remains powered up at this level until
a valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up. Any
The AD56x7R/AD56x7 has an asynchronous clear input. The
CLR
CLR
LDAC
input is falling-edge sensitive. While
is low, all
CLR
pulses are ignored. When
is activated, zero scale is loaded
to all input and DAC registers. This clears the output to 0 V. The
part exits clear code mode on the on the falling edge of the 9th
CLR
clock pulse of the last byte of valid write. If
is activated
CLR
LDAC CLR
events on
or
during power-on reset are ignored.
during a write sequence, the write is aborted. If
is activated
There is also a software reset function. Command 101 is the
software reset command. The software reset command contains
two reset modes that are software programmable by setting Bit
DB0 in the input shift register.
during high speed mode, the part exits high speed mode to
standard/fast mode.
INTERNAL REFERENCE SETUP (R VERSIONS)
The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
setting DB0 in the input shift register. Table 13 shows how the
state of the bit corresponds to the mode of operation. See Figure 66
for the contents of the input shift register during the internal
reference setup command.
Table 12 shows how the state of the bit corresponds to the
software reset modes of operation of the devices. Figure 64
shows the contents of the input shift register during the
software reset mode of operation.
Table 12. Software Reset Modes for the AD56x7R/AD56x7
DB0
Registers reset to zero
Table 13. Reference Setup Command
0
DAC register
Input shift register
DAC register
Input shift register
LDAC register
DB0
Action
0
1
Internal reference off (default)
Internal reference on
1 (Power-On Reset)
Power-down register
Internal reference setup register
X
0
S
X
C2
1
C1
0
C0
1
A2
X
A1
X
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RST
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DAC ADDRESS
(DON’T CARE)
COMMAND
DON’T CARE
DON’T CARE
Figure 64. Software Reset Command
R
0
S
X
C2
C1
0
C0
A2
X
A1
X
A0
X
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
X
X
X
X
X
X
X
X
X
X
PD1 PD0
X
X
DACB DACA
DAC ADDRESS
(DON’T CARE)
POWER-
COMMAND
DON’T CARE
DON’T CARE
DON’T CARE
DOWN MODE
DAC SELECT
(1 = DAC SELECTED)
Figure 65. Power Up/Down Command
R
0
S
X
C2
C1
1
C0
1
A2
X
A1
X
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
REF
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DAC ADDRESS
(DON’T CARE)
COMMAND
DON’T CARE
DON’T CARE
Figure 66. Reference Setup Command
Rev. 0 | Page 26 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
APPLICATION INFORMATION
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD56x7R/AD56x7
R2 = 10kΩ
+5V
R1 = 10kΩ
Because the supply current required by the AD56x7R/AD56x7 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the part (see Figure 67). This is
especially useful if the power supply is quite noisy, or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD56x7R/AD56x7. If the low dropout REF195 is
used, it must supply 450 μA of current to the AD56x7R/AD56x7
with no load on the output of the DAC. When the DAC output is
loaded, the REF195 also needs to supply the current to the load.
The total current required (with a 5 kΩ load on the DAC
output) is
V
±5V
O
AD820/
OP295
V
V
OUT
+5V
10µF
DD
0.1µF
AD5627R/
AD5647R/
AD5667R/
AD5627/
AD5667
–5V
GND SCL SDA
2-WIRE
SERIAL
INTERFACE
Figure 68. Bipolar Operation with the AD56x7R/AD56x7
POWER SUPPLY BYPASSING AND GROUNDING
450 μA + (5 V/5 kΩ) = 1.45 mA
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD56x7R/AD56x7
should have separate analog and digital sections, each having its
own area of the board. If the AD56x7R/AD56x7 are in a system
where other devices require an AGND to DGND connection, the
connection should be made at one point only. This ground point
should be as close as possible to the AD56x7R/AD56x7.
The load regulation of the REF195 is typically 2 ppm/mA,
resulting in a 2.9 ppm (14.5 μV) error for the 1.45 mA current
drawn from it. This corresponds to a 0.191 LSB error.
15V
5V
REF195
V
DD
SCL
SDA
AD5627R/
AD5647R/
AD5667R/
AD5627/
AD5667
GND
V
= 0V TO 5V
2-WIRE
SERIAL
INTERFACE
OUT
The power supply to the AD56x7R/AD56x7 should be bypassed
with 10 μF and 0.1 μF capacitors. The capacitors should be
located as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitor should be
the tantalum bead type. It is important that the 0.1 μF capacitor
have low effective series resistance (ESR) and effective series
inductance (ESI), for example, common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
Figure 67. REF195 as Power Supply to the AD56x7R/AD56x7
BIPOLAR OPERATION USING THE
AD56x7R/AD56x7
The AD56x7R/AD56x7 has been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 68. The circuit gives an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achieved
using an AD820 or an OP295 as the output amplifier.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.
The output voltage for any input code can be calculated as
follows:
⎡
⎤
⎥
⎦
D
65,536
R1+ R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VO = VDD
×
×
−V
×
DD
⎢
⎝
⎠
⎣
where D represents the input code in decimal (0 to 65535).
With VDD = 5 V, R1 = R2 = 10 kΩ,
10×D
65,536
⎛
⎜
⎞
⎟
VO
=
− 5 V
⎝
⎠
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
Rev. 0 | Page 27 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
OUTLINE DIMENSIONS
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm x 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
10
6
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 70. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. 0 | Page 2± of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
ORDERING GUIDE
Temperature
Range
On-Chip
Reference Speed
Max I2C
Package
Description
Package
Option
Model
Accuracy
Branding
DA1
DA1
DA1
DA1
D9J
AD5627BCPZ-R21
AD5627BCPZ-REEL71
AD5627BRMZ1
AD5627BRMZ-REEL71
AD5627RBCPZ-R21
AD5627RBCPZ-REEL71
AD5627RBRMZ-11
AD5627RBRMZ-1REEL71 −40°C to +105°C ±1 LSB INL
AD5627RBRMZ-21
−40°C to +105°C ±1 LSB INL
AD5627RBRMZ-2REEL71 −40°C to +105°C ±1 LSB INL
AD5647RBCPZ-R21
AD5647RBCPZ-REEL71
AD5647RBRMZ1
AD5647RBRMZ-REEL71
AD5667BCPZ-R21
AD5667BCPZ-REEL71
AD5667BRMZ1
AD5667BRMZ-REEL71
AD5667RBCPZ-R21
AD5667RBCPZ-REEL71
AD5667RBRMZ-11
AD5667RBRMZ-1REEL71 −40°C to +105°C ±12 LSB INL 2.5 V
AD5667RBRMZ-21
−40°C to +105°C ±12 LSB INL 2.5 V
−40°C to +105°C ±1 LSB INL
−40°C to +105°C ±1 LSB INL
−40°C to +105°C ±1 LSB INL
−40°C to +105°C ±1 LSB INL
−40°C to +105°C ±1 LSB INL
−40°C to +105°C ±1 LSB INL
−40°C to +105°C ±1 LSB INL
None
None
None
None
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
3.4 MHz
3.4 MHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
3.4 MHz
3.4 MHz
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
CP-10 -9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
RU-14
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
D9J
DA7
DA7
DA±
DA±
D9G
D9G
D9G
D9G
D9Z
D9Z
D9Z
D9Z
D±X
D±X
DA5
DA5
DA6
DA6
10-Lead MSOP
−40°C to +105°C ±4 LSB INL
−40°C to +105°C ±4 LSB INL
−40°C to +105°C ±4 LSB INL
−40°C to +105°C ±4 LSB INL
1.25 V
1.25 V
2.5 V
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
RU-14
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
2.5 V
10-Lead MSOP
−40°C to +105°C ±12 LSB INL None
−40°C to +105°C ±12 LSB INL None
−40°C to +105°C ±12 LSB INL None
−40°C to +105°C ±12 LSB INL None
−40°C to +105°C ±12 LSB INL 1.25 V
−40°C to +105°C ±12 LSB INL 1.25 V
−40°C to +105°C ±12 LSB INL 2.5 V
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
AD5667RBRMZ-2REEL71 −40°C to +105°C ±12 LSB INL 2.5 V
EVAL-AD5667REBZ1
10-Lead MSOP
Evaluation Board
1 Z = Pb-free part.
Rev. 0 | Page 29 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
NOTES
Rev. 0 | Page 30 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
NOTES
Rev. 0 | Page 31 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06342-0-1/07(0)
Rev. 0 | Page 32 of 32
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