EVAL-AD7152EBZ [ADI]
12-Bit Capacitance-to-Digital Converter; 12位电容至数字转换器
| 型号： | EVAL-AD7152EBZ |
| 厂家： | 
ADI |
| 描述： | 12-Bit Capacitance-to-Digital Converter |
| 文件： | 总24页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Capacitance-to-Digital Converter
AD7152/AD7153
GENERAL DESCRIPTION
FEATURES
Capacitance-to-digital converters
Interfaces to floating sensors
The AD7152/AD7153 are 12-bit sigma-delta (Σ-Δ) capacitance-to-
digital converters (CDCs). The capacitance to be measured
Resolution down to 0.25 fF (that is, up to 12 ENOB)
Linearity: 0.05%
is connected directly to the device inputs. The architecture
features inherent high resolution (12-bit no missing codes,
up to 12-bit effective resolution) and high linearity (±±.±5ꢀ).
The AD7152/AD7153 have four capacitance input ranges per
operation mode, ±±.25 pꢁ to ±2 pꢁ in differential mode and
±.5 pꢁ to 4 pꢁ in single-ended mode.
Common-mode (not changing) capacitance up to 5 pF
Four capacitance ranges selectable per operation mode
0.25 pF to 2 pF in differential mode
0.5 pF to 4 pF in single-ended mode
Tolerant of parasitic capacitance to ground up to 50 pF
Conversion time per channel: 5 ms, 20 ms, 50 ms, and 60 ms
Internal clock oscillator
The AD7152/AD7153 can accept up to 5 pꢁ common-mode
capacitance (not changing), which can be balanced by a
programmable on-chip, digital-to-capacitance converter
(CAPDAC).
2-wire serial interface (I2C-compatible)
Power
The AD7153 has one capacitance input channel, while the
AD7152 has two channels. Each channel can be configured
as single-ended or differential. The AD7152/AD7153 are
designed for floating capacitive sensors.
2.7 V to 3.6 V single-supply operation
100 μA current consumption
Operating temperature: −40°C to +85°C
10-lead MSOP package
The AD7152/AD7153 have a 2-wire, I2C®-compatible serial
interface. Both parts can operate with a single power supply
from 2.7 V to 3.6 V. They are specified over the temperature
range of −4±°C to +85°C and are available in a 1±-lead MSOP
package.
APPLICATIONS
Automotive, industrial, and medical systems for
Pressure measurement
Position sensing
Level sensing
Flowmeters
Humidity sensing
FUNCTIONAL BLOCK DIAGRAMS
VDD
VDD
AD7152
AD7153
CAP+
CAP–
CAP+
CLOCK
VOLTAGE
CLOCK
VOLTAGE
CAP–
GENERATOR REFERENCE
GENERATOR REFERENCE
CIN1(+)
CIN1(–)
EXC1
CIN1(+)
CIN1(–)
EXC1
SDA
SCL
SDA
SCL
2
2
I C
SERIAL
INTERFACE
I C
12-BIT Σ-Δ
MODULATOR
12-BIT Σ-Δ
MODULATOR
MUX
MUX
SERIAL
INTERFACE
CIN2(+)
CIN2(–)
EXC2
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
EXCITATION
EXCITATION
GND
GND
Figure 1.
Figure 2.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD7152/AD7153
TABLE OF CONTENTS
Features .............................................................................................. 1
Configuration Register .............................................................. 16
CAPDAC POS Register............................................................. 17
CAPDAC NEG Register............................................................ 17
Configuration2 Register............................................................ 17
Circuit Description......................................................................... 18
Capacitance-to-Digital Converter (CDC) .............................. 18
Excitation Source........................................................................ 18
CAPDAC ..................................................................................... 19
Single-Ended Capacitive Input................................................. 19
Differential Capacitive Input .................................................... 20
Parasitic Capacitance to Ground.............................................. 20
Parasitic Resistance to Ground................................................. 20
Parasitic Parallel Resistance ...................................................... 21
Parasitic Serial Resistance ......................................................... 21
Input EMC Protection ............................................................... 21
Power Supply Decoupling and Filtering.................................. 21
Capacitive Gain Calibration ..................................................... 21
Capacitive System Offset Calibration...................................... 21
Typical Application Diagram.................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Serial Interface ................................................................................ 11
Write Operation.......................................................................... 11
Read Operation........................................................................... 11
AD7152/AD7153 Reset ............................................................. 12
General Call................................................................................. 12
Register Map.................................................................................... 13
Status Register............................................................................. 14
Data Registers ............................................................................. 15
Offset Calibration Registers...................................................... 15
Gain Calibration Registers ........................................................ 15
CAP Setup Registers .................................................................. 16
REVISION HISTORY
5/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD7152/AD7153
SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = ± V; −4±°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Min Typ
Max Unit1
Test Conditions/Comments
CAPACITIVE INPUT
Capacitive Input Ranges
±2
±±
±0.ꢀ
±0.2ꢀ
4
2
±
0.ꢀ
pF
pF
pF
pF
pF
pF
pF
pF
Differential mode
Single-ended mode
Gain Matching Between Ranges
Integral Nonlinearity (INL)2
No Missing Codes2
±3
% of FS
% of FS
Bits
Bits
Bits
±0.0ꢀ
±2
±0
±2
Resolution, p-p2, 3
2ꢀ°C, VDD = 3.3 V, 4 pF range
2ꢀ°C, VDD = 3.3 V, 4 pF range
Resolution Effective2, 3
Absolute Error4
±20
fF
2ꢀ°C, VDD = 3.3 V, after system offset
calibration, ±2 pF range
System Offset Calibration Rangeꢀ, 6
Offset Deviation over Temperature2
40
ꢀ
% of FSR
fF
±
Single-ended mode, CIN and EXC
pins disconnected, see Figure 8
0.3
±
fF
Differential mode, CIN and EXC
pins disconnected
Gain Error7
0.ꢀ
0.4
ꢀ0
±0
20
% of FSR
% of FSR
pF
MΩ
kΩ
fF/V
dB
dB
2ꢀ°C, VDD = 3.3 V
See Figure 7
See Figure 9 and Figure ±0
See Figure ±3
See Figure ±6
Gain Deviation over Temperature2
Allowed Capacitance, CIN to GND2
Allowed Resistance, CIN to GND2
Allowed Serial Resistance2
Power Supply Rejection DC
Normal-Mode Rejection2
0.3
2
See Figure ±7
−70
−70
−70
ꢀ0 Hz ± ± Hz, conversion time = 60 ms
60 Hz ± ± Hz, conversion time = ꢀ0 ms
AD7±ꢀ2 only
Channel-to-Channel Isolation2
CAPDAC
dB
Full Range
Resolution8
ꢀ
6.2ꢀ
200
pF
fF
ꢀ-bit CAPDAC
See Figure ±8 and Figure ±9
Single-ended mode
Differential Nonlinearity (DNL)2
Offset Deviation over Temperature2
EXCITATION
0.2ꢀ LSB
% of CAPDAC FSR
0.3
Frequency
Voltage
30.9 32
±VDD/2
32.8 kHz
V
Allowed Capacitance, EXC to GND2
SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current (SCL)
OPEN-DRAIN OUTPUT (SDA)
Output Low Voltage, VOL
300
pF
See Figure ±± and Figure ±2
±.ꢀ
V
V
μA
0.8
±ꢀ
±0.±
0.4
ꢀ
V
I
SINK = −6.0 mA
Output High Leakage Current, IOH
POWER SUPPLY MONITOR
Threshold Voltage, VDD
0.±
μA
VOUT = VDD
2.4ꢀ
2.6ꢀ
V
Rev. 0 | Page 3 of 24
AD7152/AD7153
Parameter
Min Typ
Max Unit1
Test Conditions/Comments
POWER REQUIREMENTS
VDD-to-GND Voltage
Current, IDD
2.7
±00
±
3.6
±20
ꢀ
V
VDD = 3.3 V, nominal
9
μA
μA
μA
9
Current Power-Down Mode, IDD
Temperature ≤ 2ꢀ°C
Temperature = 8ꢀ°C
3
±0
± Capacitance units: ± pF = ±0−±2 F; ± fF = ±0−±ꢀ F; ± aF = ±0−±8 F.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Except Channel 2 in differential mode. To achieve the specified performance in differential mode, the I2C interface must be idle during the capacitance conversion to
prevent signal coupling from the SCL pin to the adjacent CIN2(−) pin.
4
Factory calibrated. The absolute error includes factory gain calibration error and integral nonlinearity error all at 2ꢀ°C. At different temperatures, compensation for
gain drift over temperature is required.
ꢀ Specification is not production tested but guaranteed by design.
6 A system offset calibration is effectively a conversion; therefore, the offset error is of the order of the conversion noise. This applies after calibration at the temperature,
capacitive input range, and applied VDD of interest. The capacitive input offset can be reduced using a system offset calibration. Large offsets should be removed using
CAPDACs.
7 The gain error is factory calibrated at 2ꢀ°C. At different temperatures, compensation for gain drift over temperature is required.
8
The CAPDAC resolution is five bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can
further reduce the CIN offset or the unchanging CIN component.
9 Digital inputs equal to VDD or GND.
Rev. 0 | Page 4 of 24
AD7152/AD7153
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = ± V; Input Logic ± = ± V; Input Logic 1 = VDD; −4±°C to +85°C, unless otherwise noted.
Table 2.
Parameter
SERIAL INTERFACE±, 2
Min Typ Max Unit Test Conditions/Comments
See Figure 3.
SCL Frequency
0
0.6
±.3
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
0.3
0.3
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Set-Up Time (Start Condition), tSU;STA
Data Set-Up Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Conditions, tBUF
0.6
0.6
0.±
0.6
0.0±
±.3
After this period, the first clock is generated.
Relevant for repeated start condition.
)
± Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the ±0% and 90% points. Timing reference points at ꢀ0% for inputs and outputs;
output load = ±0 pF.
tR
tF
tLOW
tHD;STA
SCL
SDA
tHIGH
tSU;STA
tSU;STO
tHD;STA
tHD;DAT
tSU;DAT
tBUF
S
P
S
P
Figure 3. Serial Interface Timing Diagram
Rev. 0 | Page ꢀ of 24
AD7152/AD7153
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Positive Supply Voltage, VDD to GND
Voltage on Any Input or Output Pin to GND
ESD Rating (ESD Association Human
Body Model, Sꢀ.±)
Rating
−0.3 V to +3.9 V
−0.3 V to VDD + 0.3 V
4 kV
ESD Rating (Field-Induced Charged
Device Model)
7ꢀ0 V
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−40°C to +8ꢀ°C
−6ꢀ°C to +±ꢀ0°C
±ꢀ0°C
MSOP
θJA Thermal Impedance-to-Air
θJC Thermal Impedance-to-Case
Reflow Soldering (Pb-Free)
Peak Temperature
206°C/W
44°C/W
260 (+0/−ꢀ)°C
Time at Peak Temperature
±0 sec to 40 sec
Rev. 0 | Page 6 of 24
AD7152/AD7153
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND
VDD
1
2
3
4
5
10 SDA
GND
VDD
1
2
3
4
5
10 SDA
9
8
7
6
SCL
NC
AD7153
TOP VIEW
(Not to Scale)
9
8
7
6
SCL
CIN1(–)
CIN1(+)
NC
AD7152
TOP VIEW
(Not to Scale)
CIN1(–)
CIN1(+)
EXC2
CIN2(–)
CIN2(+)
EXC1
NC
EXC1
NC = NO CONNECT
Figure 4. AD7152 Pin Configuration
Figure 5. AD7153 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
±
2
GND
VDD
Ground Pin.
Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example, in
combination with a ±0 μF tantalum and a 0.± μF multilayer ceramic capacitor.
3
CIN±(–)
CDC Negative Capacitive Input of Channel ±. If not used, this pin can be left as an open circuit or connected to
GND. This pin is internally disconnected in single-ended CDC configuration.
4
ꢀ
CIN±(+)
EXC2/NC
CDC Positive Capacitive Input of Channel ±. If not used, this pin can be left as an open circuit or connected to GND.
AD7±ꢀ2: CDC Excitation Output for Channel 2. The measured capacitance is connected between one of the EXC
pins and one of the CIN pins. If not used, these pins should be left as an open circuit.
AD7±ꢀ3: No Connect. This pin must be left as an open circuit.
6
7
EXC±
CDC Excitation Output for Channel ±. The measured capacitance is connected between one of the EXC pins and
one of the CIN pins. If not used, these pins should be left as an open circuit.
AD7±ꢀ2: CDC Positive Capacitive Input of Channel 2. If not used, this pin can be left as an open circuit or
connected to GND.
CIN2(+)/NC
AD7±ꢀ3: No Connect. This pin must be left as an open circuit.
8
CIN2(–)/NC
AD7±ꢀ2: CDC Negative Capacitive Input of Channel 2. If not used, this pin can be left as an open circuit or
connected to GND. This pin is internally disconnected in single-ended CDC configuration.
AD7±ꢀ3: No Connect. This pin must be left as an open circuit.
9
SCL
Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if one is not already
provided in the system.
±0
SDA
Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if one is not
provided elsewhere in the system.
Rev. 0 | Page 7 of 24
AD7152/AD7153
TYPICAL PERFORMANCE CHARACTERISTICS
0.05
2
0
0.04
0.03
0.02
0.01
0
–2
3pF
9pF
–4
–6
0.01
0.02
0.03
0.04
0.05
–8
–10
–12
–2
–1
0
1
2
0
50
100
150
200
250
300
350
CAPACITANCE (pF)
CAP LOAD TO GND (pF)
Figure 6. Capacitance Input Integral Nonlinearity,
VDD = 3.3 V, See Figure 34
Figure 9. Capacitance Input Error vs. Capacitance Between CIN and GND;
Single-Ended Mode, CIN(+) to EXC = 3 pF and 9 pF, VDD = 3.3 V
0.20
2
2pF
TC ≈ 28ppm/°C
0.15
0.10
0
8pF
–2
–4
0.05
0.00
–0.05
–0.10
–0.15
–0.20
–0.25
–6
–8
–10
–12
0
50
100
150
200
250
300
350
50
25
0
25
50
75
100
TEMPERATURE (°C)
CAP LOAD TO GND (pF)
Figure 7. Capacitance Input Gain Drift vs. Temperature,
DD = 3.3 V, Range = 2 pF
Figure 10. Capacitance Input Error vs. Capacitance Between CIN and GND,
Differential Mode, CIN(+) to EXC = 2 pF and 8 pF,
V
CIN(−) to EXC = 0 pF and 6 pF, VDD = 3.3 V
0.4
0.2
0.3
0.2
0.1
0
0
–0.1
–0.2
–0.3
–0.2
–0.4
–50
–25
0
25
50
75
100
0
50
100
150
200
250
300
350
TEMPERATURE (°C)
CAP LOAD TO GND (pF)
Figure 8. Capacitance Input Offset Drift vs. Temperature,
DD = 3.3 V, CIN and EXC Pins Open Circuit
Figure 11. Capacitance Input Error vs. Capacitance Between EXC and GND,
Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V
V
Rev. 0 | Page 8 of 24
AD7152/AD7153
10
0
0.3
0.2
–10
–20
–30
–40
–50
0.1
0
–0.1
–0.2
–0.3
0
50
100
150
200
250
300
350
1
10
100
1000
CAP LOAD TO GND (pF)
PARALLEL RESISTANCE (MΩ)
Figure 12. Capacitance Input Error vs. Capacitance Between EXC and GND,
Differential Mode, CIN(+) to EXC = 8 pF,
Figure 15. Capacitance Input Error vs. Parasitic Parallel Resistance
Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V
CIN(−) to EXC = 6 pF, VDD = 3.3 V
2
0
0
3pF
–5
–2
–4
–6
–8
–10
–10
9pF
–15
–20
–25
–30
0
20
40
60
80
100
1
10
100
1000
SERIAL RESISTANCE (kΩ)
RESISTANCE CIN TO GROUND (MΩ)
Figure 13. Capacitance Input Error vs. Parasitic Resistance CIN to GND,
Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V
Figure 16. Capacitance Input Error vs. Serial Resistance,
Single-Ended Mode, CIN(+) to EXC = 3 pF and 9 pF, VDD = 3.3 V
0.6
0.4
0.2
0.0
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
0
–0.2
–0.4
–0.6
1
10
100
1000
2.6
2.8
3.0
3.2
3.4
3.6
3.8
RESISTANCE EXC TO GROUND (MΩ)
VDD (V)
Figure 14. Capacitance Input Error vs. Parasitic Resistance EXC to GND,
Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V
Figure 17. Capacitance Input Power Supply Rejection (PSR),
Differential Mode; CIN(+) to EXC = 1.9 pF
Rev. 0 | Page 9 of 24
AD7152/AD7153
30
0
–20
–40
–60
–80
20
10
0
–10
–20
–30
0
5
10
15
20
25
30
0
50
100
150
INPUT SIGNAL FREQUENCY (Hz)
CAPDAC CODE
Figure 18. CAPDAC(+) Differential Nonlinearity (DNL)
Figure 20. Capacitance Channel Frequency Response,
Conversion Time = 60 ms
30
20
0
–20
–40
–60
–80
10
0
–10
–20
–30
0
5
10
15
20
25
30
0
50
100
150
INPUT SIGNAL FREQUENCY (Hz)
CAPDAC CODE
Figure 21. Capacitance Channel Frequency Response,
Conversion Time = 50 ms
Figure 19. CAPDAC(−) Differential Nonlinearity (DNL)
Rev. 0 | Page ±0 of 24
AD7152/AD7153
SERIAL INTERFACE
A stop condition is defined by a low-to-high transition on SDA
while SCL remains high. If a stop condition is ever encountered
by the AD7152/AD7153, it returns to its idle condition and the
address pointer is reset to Address ±x±±.
The AD7152/AD7153 support an I2C-compatible, 2-wire serial
interface. The two wires on the I2C bus are called SCL (clock)
and SDA (data). These two wires carry all addressing, control,
and data information one bit at a time over the bus to all connected
peripheral devices. The SDA wire carries the data, while the
SCL wire synchronizes the sender and receiver during the
data transfer. I2C devices are classified as either master or slave
devices. A device that initiates a data transfer message is called a
master; a device that responds to this message is called a slave.
If a data byte is transmitted after the register address pointer
byte, the AD7152/AD7153 load this byte into the register that
is currently addressed by the address pointer register. The parts
send an acknowledge and the address pointer autoincrementer
automatically increments the address pointer register to the
next internal register address. Thus, subsequent transmitted
data bytes are loaded into sequentially incremented addresses.
To control the AD7152/AD7153 via the bus, the following
protocol must be followed. The master initiates a data transfer
by establishing a start condition, defined by a high-to-low
transition on SDA while SCL remains high. This indicates that
the start byte follows. This 8-bit start byte is made up of a 7-bit
address plus an R/W bit indicator.
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond
exactly as previously outlined for a start condition, that is, a
repeated start condition is treated the same as a start condition.
When a master device issues a stop condition, it relinquishes
control of the bus, allowing another master device to take
control. Hence, a master wanting to retain control of the bus
issues successive start conditions known as repeated start
conditions.
All peripherals connected to the bus respond to the start
condition and shift in the next 8 bits (7-bit address and an
R/W bit). The bits arrive MSB first. The peripheral that
recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. An exception to this
is the general call address, which is described in the General
Call section. The idle condition is where the device monitors
the SDA and SCL lines waiting for the start condition and the
correct address byte. The R/W bit determines the direction of
the data transfer. A Logic ± LSB in the start byte means that the
master writes information to the addressed peripheral. In this
case, the device becomes a slave receiver. A Logic 1 LSB in the
start byte means that the master reads information from the
addressed peripheral. In this case, the device becomes a slave
transmitter. In all instances, the AD7152/AD7153 act as a
standard slave device on the I2C bus.
READ OPERATION
When a read is selected in the start byte, the register that is
currently addressed by the address pointer is transmitted onto
the SDA line by the AD7152/AD7153. The regulator is then
clocked out by the master device, and the AD7152/AD7153
await an acknowledge from the master.
If an acknowledge is received from the master, the address
autoincrementer automatically increments the address pointer
register and outputs the next addressed register content onto
the SDA line for transmission to the master. If no acknowledge
is received, the AD7152/AD7153 return to the idle state and the
address pointer is not incremented.
The autoincrementer of the address pointers allows block data
to be written or read from the starting address and subsequent
incremental addresses.
The start byte address is Address ±x9± for a write and Address
±x91 for a read.
WRITE OPERATION
In continuous conversion mode, autoincrementer of the address
pointers should be used for reading a conversion result; that is,
the three data bytes should be read using one multibyte read
transaction rather than three separate single-byte transactions.
The single-byte data read transaction may result in the data
bytes from two different results being mixed.
When a write is selected, the byte following the start byte is
always the register address pointer (subaddress) byte, which
points to one of the internal registers on the AD7152/AD7153.
The address pointer byte is automatically loaded into the
address pointer register and acknowledged by the AD7152/
AD7153. After the address pointer byte acknowledge, a stop
condition, a repeated start condition, or another data byte can
follow from the master.
Rev. 0 | Page ±± of 24
AD7152/AD7153
The user can also access any unique register (address) on a
one-to-one basis without having to update all the registers.
However, the address pointer register contents cannot be read.
AD7152/AD7153 RESET
To reset the AD7152/AD7153 without having to reset the entire
I2C bus, an explicit reset command is provided. This command
uses a particular address pointer word as a command word to
reset the part and upload all default settings. The AD7152/
AD7153 do not respond to the I2C bus commands (no acknowl-
edge) during the default values upload for approximately 15± μs
(maximum 2±± μs).
If an incorrect address pointer location is accessed, or if the user
allows the autoincrementer to exceed the required register
address, apply the following requirements:
•
In read mode, the AD7152/AD7153 continue to output
various internal register contents until the master device
issues a no acknowledge, start, or stop condition. The
contents of the address pointers autoincrementer are reset
to point to the status register at Address ±x±± when a stop
condition is received at the end of a read operation. This
allows the status register to be read (polled) continually
without having to constantly write to the address pointer.
The reset command address word is ±xBꢁ.
GENERAL CALL
When a master issues a slave address consisting of seven ±s with
the eighth bit (R/W bit) set to ±, this is called the general call
address. The general call address is for addressing every device
connected to the I2C bus. The AD7152/AD7153 acknowledge
this address and read the following data byte.
•
In write mode, the data for the invalid address is not
loaded into the registers of the AD7152/AD7153, but
an acknowledge is issued by the AD7152/AD7153.
If the second byte is ±x±6, the AD7152/AD7153 are reset,
completely uploading all default values. The AD7152/AD7153
do not respond to the I2C bus commands (no acknowledge)
during the default values upload for approximately 15± μs
(maximum 2±± μs).
The AD7152/AD7153 do not acknowledge any other general
call commands.
SDA
SCL
S
1 to 7
ADDR
8
9
1 to 7
8
9
1 to 7
DATA
8
9
P
SUBADDRESS
START
ACK
ACK
ACK
STOP
R/W
Figure 22. Bus Data Transfer
WRITE
SEQUENCE
S
S
SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
DATA
A(S)
A(S)
DATA
P
LSB = 1
READ
SEQUENCE
A(M)
A(M)
P
SLAVE ADDR A(S)
SUB ADDR A(S)
S
SLAVE ADDR A(S)
DATA
DATA
Figure 23. Write and Read Sequences
Table 5. I2C Abbreviation
Abbreviation
Definition
Start bit
S
P
Stop bit
A(S)
A(M)
A(S)
A(M)
ACK
R/W
Acknowledge by slave
Acknowledge by master
No acknowledge by slave
No acknowledge by master
Acknowledge
Read/write
Rev. 0 | Page ±2 of 24
AD7152/AD7153
REGISTER MAP
The master can write to or read from all of the registers except
the address pointer register, which is a write-only register. The
address pointer register determines which register the next read
or write operation accesses. All communications with the part
through the bus start with an access to the address pointer
register. After the part has been accessed over the bus and a
read/write operation is selected, the address pointer register is
set up. The address pointer register determines from or to which
register the operation takes place. A read/write operation is
performed from/to the target address, which then increments to
the next address until a stop command on the bus is performed.
Table 6. Register Summary
Subaddress
Default
Register Name
Dec Hex
Access Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value
0x03
0x00
0x00
0x00
0x00
0x80
0x00
0x80
0x00
0xXX
0xXX
Status
0
1
2
3
4
5
6
7
8
9
10
0x00
0x01
0x02
0x03
0x04
R
R
R
R
R
PWDN
Unused Unused
Unused Unused C1C2
Channel 1 data, high byte
Channel 1 data, low byte
Channel 2 data, high byte
Channel 2 data, low byte
RDY2
RDY1
Channel 1 Data MSB
Channel 1 Data LSB
Channel 2 Data MSB1
Channel 2 Data LSB
Channel 1 Offset MSB
Channel 1 Offset LSB
Channel 2 Offset MSB1
Channel 2 Offset LSB1
Channel 1 Gain MSB
Channel 1 Gain LSB
0x05 R/W
0x06 R/W
0x07 R/W
0x08 R/W
0x09 R/W
0x0A R/W
Channel 1 offset calibration coefficient, high byte
Channel 1 offset calibration coefficient, low byte
Channel 2 offset calibration coefficient, high byte
Channel 2 offset calibration coefficient, low byte
Channel 1 gain coefficient, high byte, factory calibrated
Channel 1 gain coefficient, low byte, factory calibrated
Channel 1 Setup
Channel 2 Gain MSB1
Channel 2 Gain LSB1
Channel 2 Setup1
Configuration
11
12
13
14
15
16
17
18
26
0x0B R/W
0x0C R/W
0x0D R/W
Range 1
Range 0 CAPDIFF Unused Unused
0x00
0xXX
0xXX
0x00
0x00
0x00
0x00
0x00
Channel 2 gain coefficient, high byte, factory calibrated
Channel 2 gain coefficient, low byte, factory calibrated
0x0E
0x0F
R/W
R/W
Range 1 Range 0 CAPDIFF Unused Unused
Unused
Unused
Unused Unused
Ch1en
Ch2en
MD2
MD1
MD0
Reserved
0x10 R/W
0x11 R/W
0x12 R/W
0x1A R/W
CAPDAC POS
DACPen Unused Unused
DACNen Unused Unused
DACP Bits[4:0] value
DACN Bits[4:0] value
CAPDAC NEG
Configuration2
Unused
Unused OSR1
OSR0
Unused Unused Unused Unused 0x00
1 AD7152 only.
Rev. 0 | Page 13 of 24
AD7152/AD7153
STATUS REGISTER
Address 0x00
Read Only
Default Value 0x03
This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished
conversion.
Table 7. Status Register Bit Map
Bit
Bit 7
PWDN
0
Bit 6
Unused
0
Bit 5
Unused
0
Bit 4
Unused
0
Bit 3
Unused
0
Bit 2
C±C2
0
Bit 1
RDY2
±
Bit 0
RDY±
±
Mnemonic
Default
Table 8. Status Register Bit Descriptions
Bit
Mnemonic Description
7
PWDN
PWDN = ± indicates that the VDD voltage level is below 2.4ꢀ V typically or part is in power-down mode
Not used, always read 0
6 to 3 N/A
2
C±C2
C±C2 = 0 indicates that the last conversion performed was from Channel ±, C±C2 = ± indicates that the last
conversion performed was from Channel 2
±
0
RDY2
RDY±
RDY2 = 0 indicates that a conversion on the Channel 2 has been finished and new unread data is available (AD7±ꢀ2 only)
RDY± = 0 indicates that a conversion on the Channel ± has been finished and new unread data is available
Rev. 0 | Page ±4 of 24
AD7152/AD7153
Therefore, to prevent incorrect data reading through the
DATA REGISTERS
serial interface, the two bytes of a data register should be
read sequentially using the register address pointer auto-
increment feature of the serial interface.
Address 0x01, Address 0x02 for Channel 1
Address 0x03, Address 0x04 (AD7152 Only) Channel 2
16 Bits, Read-Only, Default Value 0x0000
Data from the last complete capacitance-to-digital conversion
reflects the capacitance on the input. Only the 12 MSBs of the
data registers are used for the CDC result. The 4 LSBs are
always ±, as shown in ꢁigure 24.
OFFSET CALIBRATION REGISTERS
Address 0x05, Address 0x06 for Channel 1,
Address 0x07, Address 0x08 for Channel 2 (AD7152 Only)
16 Bits Read/Write, Default Value 0x8000
MSB
DATA HIGH
DATA LOW
LSB
The offset calibration registers hold the zero-scale calibration
coefficients.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
12-BIT CDC RESULT
0
The zero-scale calibration coefficient digitally maps the zero
capacitance on the CDC input to the zero-scale data code.
The coefficient can be used for compensation of the AD7152/
AD7153 internal offset as well as the system level offset within
specified offset calibration limits.
Figure 24. CDC Data Register
The AD7152/AD7153 are factory gain calibrated and map the
CDC full-scale raw data range of ±x3±±± to ±xCꢁꢁ±ꢁ to a CDC
full-scale data register range of ±x±±±± to ±xꢁꢁꢁ± (see Table 9).
Users can set the coefficient by executing the offset calibration
after connecting the zero-scale capacitance to the system input.
Alternatively, the coefficient value can be written to the offset
calibration register(s) by the host software, for example, values
stored in a host nonvolatile memory.
Table 9. AD7152/AD7153 Capacitance-to-Data Mapping
Input Capacitance (4 pF range)
Data Reg
0x0000
0x8000
0xFFF0
Differential Mode
Single-Ended Mode
Zero scale (0 pF)
Midscale (2 pF)
Negative full scale (–2 pF)
Zero scale (0 pF)
Positive full scale (+2 pF)
Note that there is a difference between code mapping in differ-
ential and single-ended input mode. In differential mode, the
nominal zero-scale calibration coefficient value is a power-on
default, ±x8±±±. In single–ended mode, the nominal zero-scale
calibration coefficient value is ±x3±±±.
Full scale (4 pF)
The data register output in differential mode is internally
calculated using the following equation:
Data Reg = (Code – (Offset Reg – ±x8±±±)) × Gain + ±x8±±± (1)
The difference means that before using the single-ended mode
(or any time when changing between modes afterwards), the
user should either perform offset calibration with capacitance
close to ± pꢁ connected to the input or write the offset calibra-
tion register(s) value(s) close to ±x8±±± for differential mode or
value close to ±x3±±± for single-ended mode.
The input capacitance can be calculated from the output data
using the following equation:
Data Reg − ±x8±±±
C(pꢁ) =
× Input Range
(2)
(3)
(4)
±xꢁꢁꢁ±
The data register output in single-ended mode is internally
calculated using the following equation:
On the AD7152, the two capacitive channels have individual
offset registers and each channel can be calibrated individually.
Data Reg = (Code − (Offset Reg − ±x3±±±)) × Gain
The input capacitance can be calculated from the output data
using the following equation:
GAIN CALIBRATION REGISTERS
Address 0x09, Address 0x0A for Channel1
Address 0x0C, Address 0x0D for Channel 2 (AD7152 only)
16 Bits Read/Write, Default Value 0xXXXX
Data Reg
±xꢁꢁꢁ±
C(pꢁ) =
× Input Range
The capacitive gain calibration registers hold the capacitive
channel full-scale factory calibration coefficient. The gain
calibration factor can be calculated using the following
equation:
where Input Range = 4 pꢁ, 2 pꢁ, 1 pꢁ, or ±.5 pꢁ.
A data register is updated after a finished conversion on the
capacitive channel, with one exception: when the serial interface
read operation from the data register is in progress, the data
register is not updated and the new capacitance conversion
result is lost.
216 + Gain Reg
Gain =
(5)
216
On the AD7152, the two capacitive channels each have a gain
register, which allows the part to gain calibrate each channel
individually.
The stop condition on the serial interface is considered to be the
end of the read operation.
Rev. 0 | Page ±ꢀ of 24
AD7152/AD7153
CAP SETUP REGISTERS
Address 0x0B for Channel 1
Address 0x0E Channel 2 (AD7152 Only)
Default Value 0x00
Table 10. CAP Setup Register Bit Map
Bit
Bit 7
Range ±
0
Bit 6
Range 0
0
Bit 5
CAPDIFF
0
Bit 4
Unused
0
Bit 3
Unused
0
Bit 2
Unused
0
Bit 1
Unused
0
Bit 0
Unused
0
Mnemonic
Default
Table 11. CAP Setup Register Bit Descriptions
Bit
Mnemonic
Description
7
Range ±
Capacitive input range and mode setup
6
Range 0
Capacitive Input Range
ꢀ
CAPDIFF
Range 1
Range 0
CAPDIFF = 1 (Differential Mode)
CAPDIFF = 0 (Single-Ended Mode)
0
0
±
±
0
±
0
±
±± pF
2 pF
±0.2ꢀ pF
±0.ꢀ pF
±2 pF
0.ꢀ pF
0.2ꢀ pF
4 pF
4 to 0 N/A
These bits must be 0 for proper operation
CONFIGURATION REGISTER
Address Pointer 0x0F
Default Value 0x00
Table 12. Configuration Register Bit Map
Bit
Bit 7
Unused
0
Bit 6
Unused
0
Bit 5
Unused
0
Bit 4
Ch±en
0
Bit 3
Ch2en
0
Bit 2
MD2
0
Bit 1
MD±
0
Bit 0
MD0
0
Mnemonic
Default
Table 13. Configuration Register Bit Descriptions
Bit Mnemonic Description
7 to ꢀ N/A These bits must be 0 for proper operation
4
3
2
±
0
Ch±en
Ch2en = ± enables Channel ± for single conversion, continuous conversion, or calibration
Ch2en = ± enables Channel 2 for single conversion, continuous conversion, or calibration
Converter mode of operation setup
Ch2en
MD2
MD±
MD0
MD2
MD1
MD0
Mode
0
0
0
0
±
±
±
±
0
0
±
±
0
0
±
±
0
±
0
±
0
±
0
±
Idle
Continuous conversion
Single conversion
Power-down
N/A
Capacitance system offset calibration
Capacitance system gain calibration
N/A
Rev. 0 | Page ±6 of 24
AD7152/AD7153
CAPDAC POS REGISTER
Address 0x11
Default Value 0x00
Table 14. Status Register Bit Map
Bit
Bit 7
DACPen
0
Bit 6
Unused
0
Bit 5
Unused
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Default
DACP – Bits[4:0] Value
0x00
Table 15. Status Register Bit Descriptions
Bit
Mnemonic
Description
7
DACPen
DACPen = ± connects the capacitive DAC POS to the positive capacitive input
These bits must be 0 for proper operation
6 to ꢀ N/A
4 to 0 DACP
DACP value, Code 0x00 = 0 pF, Code 0x±F = full range
CAPDAC NEG REGISTER
Address 0x12
Default Value 0x00
Table 16. Status Register Bit Map
Bit
Bit 7
DACNen
0
Bit 6
Unused
0
Bit 5
Unused
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Default
DACN – Bit[4:0] Value
0x00
Table 17. Status Register Bit Descriptions
Bit
Mnemonic
Description
7
DACNen
DACNen = ± connects the capacitive DAC NEG to the positive capacitive input
These bits must be 0 for proper operation
6 to ꢀ N/A
4 to 0 DACN
DACN value, Code 0x00 = 0 pF, Code 0x±F = full range
CONFIGURATION2 REGISTER
Address 0x1A,
Default Value 0x00
Table 18. Configuration2 Register Bit Map
Bit
Bit 7
Unused
0
Bit 6
Unused
0
Bit 5
OSR±
0
Bit 4
OSR0
0
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Default
0
0
0
0
Table 19. Configuration2 Register Bit Descriptions
Bit
Mnemonic
Description
These bits must be 0 for proper operation
Capacitive channel digital filter setup; conversion time/update rate setup per channel
7 to 6
ꢀ
4
N/A
OSR±
OSR0
OSR1
OSR0
Conversion Time (ms)
Update Rate (Hz)
0
0
±
±
0
±
0
±
ꢀ
200
ꢀ0
20
20
ꢀ0
60
±6.7
3 to 0
N/A
These bits must be 0 for proper operation
Rev. 0 | Page ±7 of 24
AD7152/AD7153
CIRCUIT DESCRIPTION
VDD
CAPACITANCE-TO-DIGITAL CONVERTER (CDC)
AD7152
CAP+
CAP–
ꢁigure 27 shows the CDC simplified functional diagram. The
measured capacitance CX is connected between the excitation
source and the Σ-Δ modulator input. A square-wave excitation
signal is applied on the CX during the conversion and the mod-
ulator continuously samples the charge going through the CX.
The digital filter processes the modulator output, which is a
stream of ±s and 1s containing the information in ± and 1
density. The data from the digital filter is scaled, applying the
calibration coefficients, and the final result can be read through
the serial interface. The AD7152/AD7153 are designed for
floating capacitive sensors. Therefore, both CX plates have to
be isolated from ground.
CLOCK
GENERATOR REFERENCE
VOLTAGE
CIN1(+)
CIN1(–)
EXC1
SDA
SCL
2
I C
12-BIT Σ-Δ
MODULATOR
MUX
SERIAL
INTERFACE
CIN2(+)
CIN2(–)
EXC2
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
EXCITATION
GND
Figure 25. AD7152 Block Diagram
VDD
CAPACITANCE-TO-DIGITAL CONVERTER
(CDC)
AD7153
CAP+
CLOCK
CLOCK
VOLTAGE
CAP–
GENERATOR
GENERATOR REFERENCE
DATA
CIN1(+)
CIN1(–)
EXC1
CIN
SDA
SCL
2
12-BIT Σ-Δ
MODULATOR
DIGITAL
FILTER
I C
12-BIT Σ-Δ
MODULATOR
MUX
SERIAL
INTERFACE
C
X
EXC
EXCITATION
EXCITATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
Figure 27. CDC Simplified Block Diagram
GND
EXCITATION SOURCE
Figure 26. AD7153 Block Diagram
The AD7152/AD7153 have one excitation source. ꢁor the
AD7152, the excitation source is switched between the
excitation pins, EXC1 and EXC2, depending on which
channel performs a conversion.
The core of the AD7152/AD7153 is a precision converter
consisting of a second-order modulator (Σ-Δ or charge-
balancing) and a third-order digital filter.
In addition to the converter, the AD7152/AD7153 integrate a
multiplexer, an excitation source, and CAPDACs for the capaci-
tive inputs, a voltage reference, a complete clock generator, a
control and calibration logic, and an I2C-compatible serial
interface.
The AD7153 has one capacitive input, while the AD7152 has
two capacitive inputs. ꢁor the AD7152, the modulator input and
the excitation source are multiplexed between the converting
channel. All other features and specifications are identical for
both parts.
Rev. 0 | Page ±8 of 24
AD7152/AD7153
CAPDAC
SINGLE-ENDED CAPACITIVE INPUT
The CDC full-scale input range of the AD7152/AD7153 can
be set to ±±.25 pꢁ, ±±.5 pꢁ, ± 1 pꢁ, and ±2 pꢁ in differential
mode or ±.5 pꢁ, 1 pꢁ, 2 pꢁ, and 4 pꢁ in single-ended mode.
ꢁor simplicity, the following text and figures use the maximum
full scale of ±2 pꢁ and +4 pꢁ.
When configured for a single-ended mode (the CAPDIꢁꢁ bit in
the Channel 1 Setup or Channel 2 Setup registers is set to ±), the
AD7152/AD7153 CIN(−) pin is disconnected internally. The
CDC (without using the CAPDACs) can measure positive input
capacitance in the range of ± pꢁ to 4 pꢁ (see ꢁigure 29).
The parts can accept a higher capacitance on the input and the
common-mode or offset capacitance (unchanging component)
can be balanced by programmable on-chip CAPDACs.
CAPDAC(+)
OFF
0x0000 ... 0xFFF0
DATA
CIN(+)
CIN(–)
0pF TO 4pF
CDC
CAPDIFF = 0
CAPDAC(+)
CIN(+)
CAPDAC(–)
OFF
C
DATA
CDC
X
CIN(–)
0pF TO 4pF
EXC
CAPDAC(–)
C
C
Y
X
Figure 29. CDC Single-Ended Input Mode
EXC
The CAPDAC can be used for programmable shifting of the
input range.
Figure 28. Using a CAPDAC
ꢁigure 3± shows how to shift the input range up to 9 pꢁ absolute
value of capacitance connected to the CIN(+) using
the CAPDAC(+) only.
The CAPDAC can be understood as a negative capacitance
connected internally to the CIN pin. There are two independent
CAPDACs, one connected to the CIN(+) and the second
connected to the CIN(–).
CAPDAC(+)
5pF
In differential mode, the relationship between the capacitance
input and output data can be expressed as
0x0000 ... 0xFFF0
DATA
CIN(+)
CIN(–)
0pF TO 4pF
CDC
CAPDIFF = 0
DATA ≈ (CX − CAPDAC(+)) − (CY − CAPDAC(−))
In single-ended mode, the relationship between the capacitance
input and output data can be expressed as
CAPDAC(–)
OFF
C
X
5pF TO 9pF
DATA ≈ CX −(CAPDAC(+) + CAPDAC(−))
EXC
The CAPDACs have a 5-bit resolution each, monotonic transfer
function, are well matched to each other, and have a defined
temperature coefficient. The CAPDAC full range (absolute
value) is not factory calibrated and can vary up to ±2±ꢀ with
the manufacturing process (see the Specifications section,
ꢁigure 18, and ꢁigure 19).
Figure 30. Using CAPDAC in Single-Ended Mode
ꢁigure 31 shows how to shift the input range up to 14 pꢁ
absolute value of capacitance connected to the CIN(+) using
both CAPDAC(+) and CAPDAC(−).
The CAPDACs are shared by the two capacitive channels on the
AD7152. If the CAPDACs need to be set individually, the host
controller software should reload the CAPDAC values to the
AD7152 before executing a conversion on a different channel.
CAPDAC(+)
5pF
0x0000 ... 0xFFF0
DATA
CIN(+)
CIN(–)
0pF TO 4pF
CDC
CAPDIFF = 0
CAPDAC(–)
5pF
C
X
10pF TO 14pF
EXC
Figure 31. Using CAPDAC in Single-Ended Mode
Rev. 0 | Page ±9 of 24
AD7152/AD7153
DIFFERENTIAL CAPACITIVE INPUT
PARASITIC CAPACITANCE TO GROUND
When configured for differential mode (the CAPDIꢁꢁ bit in the
Channel 1 Setup or Channel 2 Setup registers is set to 1), the
CDC measures the difference between positive and negative
capacitance input.
C
GND1
DATA
CIN
CDC
Each of the two input capacitances, CX and CY, between the
EXC and CIN pins must be less than 2 pꢁ (without using the
CAPDACs) or must be less than 9 pꢁ and balanced by the
CAPDACs. Balancing by the CAPDACs means that both
CX − CAPDAC(+) and CY − CAPDAC(−) are less than 2 pꢁ.
C
X
C
GND2
EXC
If the unbalanced capacitance between the EXC and CIN pins
is higher than 2 pꢁ, the CDC introduces a gain error, an offset
error, and nonlinearity error (see ꢁigure 32, ꢁigure 33, and
ꢁigure 34).
Figure 35. Parasitic Capacitance to Ground
The CDC architecture used in the AD7152/AD7153 measures
CX connected between the EXC pin and the CIN pin. In theory,
any capacitance, CGND, to ground should not affect the CDC
result (see ꢁigure 35).
CAPDAC(+)
OFF
0x0000 ... 0xFFF0
DATA
CIN(+)
CIN(–)
The practical implementation of the circuitry in the chip
implies certain limits and the result is gradually affected by
capacitance to ground. See the allowed capacitance to GND
in the Specifications table and, ꢁigure 9 through ꢁigure 12.
± 2pF
CDC
CAPDIFF = 1
CAPDAC(–)
OFF
PARASITIC RESISTANCE TO GROUND
C
C
Y
X
0pF TO 4pF 0pF TO 4pF
EXC
Figure 32. CDC Differential Input Mode
R
GND1
DATA
CIN
CDC
CAPDAC(+)
5pF
C
X
0x0000 ... 0xFFF0
DATA
CIN(+)
R
GND2
± 2pF
CDC
EXC
CAPDIFF = 1
CIN(–)
Figure 36. Parasitic Resistance to Ground
CAPDAC(–)
5pF
C
C
The CDC result can be affected by a leakage current from
the CX to ground; therefore, the CX should be isolated from
the ground. The influence of the leakage current varies with
the power supply voltage (see ꢁigure 36).
Y
X
4pF TO 6pF
(5 ± 1pF)
EXC
4pF TO 6pF
(5 ± 1pF)
Figure 33. Using CAPDAC in Differential Mode
A higher leakage current to ground results in a gain error,
an offset error, and a nonlinearity error (see ꢁigure 13 and
ꢁigure 14).
CAPDAC(+)
5pF
0x0000 ... 0xFFF0
DATA
CIN(+)
CIN(–)
± 2pF
CDC
CAPDIFF = 1
CAPDAC(–)
5pF
C
X
C
Y
5pF
3pF TO 7pF
(5 ± 2pF)
EXC
Figure 34. Using CAPDAC in Differential Mode
Rev. 0 | Page 20 of 24
AD7152/AD7153
Some applications may require an additional input filter for
improving electromagnetic compatibility (EMC). Any input
filter must be carefully designed, considering the balance between
the system capacitance performance and system electromagnetic
immunity.
PARASITIC PARALLEL RESISTANCE
DATA
CIN
CDC
ꢁigure 39 shows one of the possible input circuit configurations
significantly improving the system immunity against high fre-
quency noise and slightly affecting the AD7152 performance in
terms of additional gain and offset error.
C
R
P
X
EXC
POWER SUPPLY DECOUPLING AND FILTERING
1kΩ
V
DD
Figure 37. Parasitic Parallel Resistance
0.1µF
10µF
1kΩ 1kΩ
The CDC measures the charge transfer between the EXC pin
and CIN pin. Any resistance connected in parallel to the meas-
ured capacitance CX (see ꢁigure 37), such as the parasitic
resistance of the sensor, also transfers charge. Therefore, the
parallel resistor is seen as an additional capacitance in the
output data causing a capacitive input error (see ꢁigure 15).
SDA
SCL
CDC
GND
Figure 40. AD7152/AD7153 VDD Decoupling and Filtering
PARASITIC SERIAL RESISTANCE
The AD7152 has good dc and low frequency power supply
rejection but may be sensitive to higher frequency ripple and
noise, specifically around the excitation frequency and its
harmonics. ꢁigure 4± shows a possible circuit configuration
for improving the system immunity against ripple and noise
coupled to the AD7152 via the power supply.
R
S1
DATA
CIN
CDC
C
X
Because the serial interface is connected to the other circuits in
the system, it is better to connect the pull-up resistors on the
other side of the VDD filter than to connect to the AD7152.
R
S2
EXC
CAPACITIVE GAIN CALIBRATION
Figure 38. Parasitic Serial Resistance
The gain of the AD7152/AD7153 is factory calibrated for the
full scale of 4 pꢁ in the production for each part individually.
The factory gain coefficient is stored in a one-time program-
mable (OTP) memory and is copied to the capacitive gain
registers at power-up or after reset.
The CDC result is affected by a resistance in series with the
measured capacitance. The total serial resistance, which refers
to RS1 and RS2 in ꢁigure 38, should be less than 2± kΩ for the
specified performance (see ꢁigure 16).
INPUT EMC PROTECTION
The gain can be changed by executing a capacitance gain
calibration mode, for which an external full-scale capacitance
needs to be connected to the capacitance input, or by writing a
user value to the capacitive gain register. This change is tempo-
rary and the factory gain coefficient can be reloaded after
power-up or reset. The part is tested and specified only for
use with the default factory calibration coefficient.
R1
R2
CIN
C1
C2
C
CDC
GND
X
R3
EXC
C3
CAPACITIVE SYSTEM OFFSET CALIBRATION
Figure 39. AD7152/AD7153 EMC Protection
The capacitive offset is dominated by the parasitic offset in the
application, such as the initial capacitance of the sensor, any
parasitic capacitance of tracks on the board, and the capacitance
of any other connections between the sensor and the CDC.
Therefore, the AD7152/AD7153 are not factory calibrated for
capacitive offset. The user should calibrate the system capacitance
offset in the application.
Rev. 0 | Page 2± of 24
AD7152/AD7153
The offset register of the AD7152/AD7153 allows for offset
calibration over the full capacitive input range. However, the
user must ensure that the offset to be removed is within 4±ꢀ of
the full scale range; this can be achieved by using the CAPCAC
to perform a coarse offset calibration and use the system offset
calibration then to compensate for an offset within the 4±ꢀ of
full-scale range pꢁ of the CAPDAC.
calibration coefficient value should be stored by the host
controller and reloaded as part of the AD7152/AD7153 setup.
Note that the AD7152/AD7153 zero scale for differential mode
is around ±x8±±±; therefore, the offset register also needs a
value of around ±x8±±±, where the zero scale in single-ended
mode is ±x±±±±, with a required offset register value of ±x3±±±.
ꢁor more detailed information, see the Data Registers section.
The offset calibration register is reloaded by the default value
±x8±±± at power-on or after reset. Therefore, if the offset
calibration is not repeated after each system power-up, the
TYPICAL APPLICATION DIAGRAM
V
1kΩ
3.3V
SUPPLY
ADP1720-3.3
0.1µF
10µF
1µF
1µF
VDD
R1
R3
R2
C1
CIN1(+)
C2
1kΩ 1kΩ
AD7153
SDA
HOST
SYSTEM
SCL
R4
C3
CIN1(–)
C4
GND
C
C
SENS2
SENS1
10kΩ
EXC1
47pF
GND
Figure 41. Basic Application Diagram for a Differential Capacitive Sensor
Rev. 0 | Page 22 of 24
AD7152/AD7153
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
6
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 42. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
Package Description
Package Option
Branding
CꢀP
CꢀP
CꢀQ
CꢀQ
AD7±ꢀ2BRMZ±
AD7±ꢀ2BRMZ-REEL±
AD7±ꢀ3BRMZ±
AD7±ꢀ3BRMZ-REEL±
EVAL-AD7±ꢀ2EBZ±
±0-Lead Mini Small Outline Package [MSOP]
±0-Lead Mini Small Outline Package [MSOP]
±0-Lead Mini Small Outline Package [MSOP]
±0-Lead Mini Small Outline Package [MSOP]
Evaluation Board
RM-±0
RM-±0
RM-±0
RM-±0
± Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
AD7152/AD7153
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07450-0-5/08(0)
Rev. 0 | Page 24 of 24
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