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EVAL-AD7452CB3 [ADI]

Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23; 差分输入， 555 kSPS的12位ADC，采用8引脚SOT- 23
EVAL-AD7452CB3
型号： EVAL-AD7452CB3
厂家： ADI    ADI
描述：

Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23
差分输入， 555 kSPS的12位ADC，采用8引脚SOT- 23
文件： 总28页 (文件大小：2583K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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V
DD  
V
V
IN+  
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
T/H  
IN–  
V
REF  
SCLK  
SDATA  
AD7452  
CONTROL LOGIC  
CS  
GND  
t1  
CS  
tCONVERT  
t2  
t3  
B
t5  
1
2
3
4
5
13  
14  
t6  
15  
16  
SCLK  
t8  
t7  
DB10  
t4  
tQUIET  
THREE-STATE  
0
0
0
0
DB11  
DB2  
DB1  
DB0  
SDATA  
4 LEADING ZEROS  
1.6mA  
I
OL  
TO OUTPUT  
PIN  
1.6V  
C
L
25pF  
200  
A
I
OH  
V
1
2
3
4
8
7
6
5
V
V
V
DD  
REF  
IN+  
IN–  
SCLK  
SDATA  
CS  
AD7452  
TOP VIEW  
(Not to Scale)  
GND  
0
75  
70  
65  
60  
55  
8192 POINT FFT  
fSAMPLE = 555kSPS  
fIN = 100kSPS  
SINAD = 71.7dB  
THD = –82dB  
V
= 4.75V  
V
= 5.25V  
DD  
DD  
–20  
–40  
SFDR = –83dB  
V
= 3.6V  
DD  
V
= 2.7V  
DD  
–60  
–80  
–100  
–120  
–140  
0
100  
200  
277  
10  
100  
277  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
1.0  
0.8  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
0.6  
0.4  
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
V
DD  
= 3V  
–80  
–90  
V
DD  
= 5V  
–100  
10  
100  
1000  
FREQUENCY (kHz)  
10000  
0
1024  
2048  
3072  
4096  
CODE  
1.0  
0.8  
0
–20  
100mV p-p SINE WAVE ON V  
DD  
NO DECOUPLING ON V  
DD  
0.6  
0.4  
–40  
0.2  
0
–60  
V = 3V  
DD  
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
V
= 5V  
DD  
–80  
–100  
–120  
0
1024  
2048  
3072  
4096  
0
100 200 300 400 500 600 700 800 900 1000  
SUPPLY RIPPLE FREQUENCY (kHz)  
CODE  
3.0  
2.0  
1.5  
2.5  
2.0  
1.5  
1.0  
1.0  
0.5  
POSITIVE INL  
NEGATIVE INL  
POSITIVE DNL  
NEGATIVE DNL  
0
0.5  
0
–0.5  
–1.5  
–2.0  
–0.5  
–1.0  
0
0.5  
1.0  
1.5  
(V)  
2.0 2.2  
2.5  
0
0.5  
1.0  
1.5  
2.0  
(V)  
2.5  
3.0  
3.5  
2.5  
3.5  
V
V
REF  
REF  
2.5  
2.0  
8
7
6
5
4
3
2
1.5  
1.0  
V
= 5V  
DD  
POSITIVE DNL  
0.5  
0
V
= 3V  
DD  
–0.5  
–1.0  
NEGATIVE DNL  
1.5  
1
0
0
0.5  
1.0  
2.0 2.2  
0
0.5  
1.0  
1.5  
2.0  
(V)  
2.5  
3.0  
3.5  
V
(V)  
V
REF  
REF  
5
4
12.0  
11.5  
11.0  
10.5  
10.0  
9.5  
V
= 3V  
DD  
3
V
= 5V  
DD  
2
1
POSITIVE INL  
0
NEGATIVE INL  
–1  
–2  
–3  
9.0  
8.5  
8.0  
–4  
–5  
7.5  
7.0  
3.5  
0
0.5  
1.0  
1.5  
2.0  
(V)  
2.5  
3.0  
0
0.5  
1.0  
1.5  
2.0  
(V)  
2.5  
3.0  
V
V
REF  
REF  
10,000  
9,000  
8,000  
7,000  
6,000  
5,000  
4,000  
3,000  
2,000  
1,000  
0
V
= V  
IN–  
IN+  
10,000 CONVERSIONS  
fS = 555kSPS  
10,000  
CODES  
2044  
2045  
2046  
2047  
2048  
2049  
CODE  
CAPACITIVE  
DAC  
C
B
A
S
V
V
IN+  
SW1  
CONTROL  
LOGIC  
SW3  
A
B
SW2  
IN–  
C
S
V
REF  
COMPARATOR  
CAPACITIVE  
DAC  
1LSB = 2  
V
/4096  
REF  
011...111  
011...110  
CAPACITIVE  
DAC  
000...001  
000...000  
111...111  
C
B
A
S
V
V
IN+  
SW1  
CONTROL  
LOGIC  
SW3  
100...010  
100...001  
100...000  
SW2  
A
B
IN–  
C
S
V
REF  
+ V  
REF  
– 1LSB  
1LSB  
0 LSB  
–V  
REF  
COMPARATOR  
ANALOG INPUT  
(V –V  
CAPACITIVE  
DAC  
)
IN+ IN–  
3V/5V  
SUPPLY  
0.1  
F
10  
F
SERIAL  
INTERFACE  
V
DD  
V
V
REF  
p-p  
V
CM*  
CM*  
SCLK  
SDATA  
CS  
IN+  
AD7452  
4.5  
4.0  
C/  
P
REF  
p-p  
V
IN–  
GND  
V
REF  
3.25V  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
2V/2.5V  
V
REF  
COMMON-MODE RANGE  
0.1  
F
*CM IS THE COMMON-MODE VOLTAGE.  
1.75V  
0.5  
0
0
0.5  
1.0  
1.5  
2.0  
(V)  
2.5  
3.0  
3.5  
V
REF  
2.5  
2.0  
1.5  
1.0  
0.5  
0
2V  
V
REF  
p-p  
V
IN+  
AD7452  
COMMON-MODE RANGE  
V
REF  
p-p  
V
IN–  
COMMON-  
MODE  
VOLTAGE  
1V  
0
0.25  
0.50  
0.75  
1.00  
(V)  
1.25  
1.50  
1.75  
2.00  
V
REF  
REFERENCE = 2V  
V
IN–  
COMMON-MODE (CM)  
2V p-p  
CM  
= 1V  
MIN  
CM  
= 4V  
MAX  
V
IN+  
REFERENCE = 2.5V  
V
IN–  
COMMON-MODE (CM)  
2.5V p-p  
CM  
= 1.25V  
MIN  
CM  
= 3.75V  
MAX  
V
IN+  
0
–20  
T
V
= 25°C  
A
= 5V  
DD  
–40  
R
IN  
= 1k  
R
= 510  
IN  
–60  
–80  
R
= 300  
IN  
R
IN  
= 10  
–100  
10  
100  
INPUT FREQUENCY (kHz)  
277  
V
DD  
D
C2  
R1  
V
IN+  
D
C1  
–50  
–55  
–60  
T
= 25°C  
A
V
DD  
–65  
–70  
–75  
–80  
–85  
–90  
D
D
C2  
R1  
V
IN–  
C1  
V
= 2.7V  
DD  
V
DD  
= 3.6V  
V
= 5.25V  
DD  
V
DD  
= 4.75V  
100  
10  
277  
INPUT FREQUENCY (kHz)  
3.75V  
2.5V  
1.25V  
R
1
F
R
R
*
*
S
R
1
G
V
IN+  
C*  
C*  
V
R
OCM  
+2.5V  
GND  
–2.5V  
AD8138  
AD7452  
51  
2
G
S
V
IN–  
V
REF  
3.75V  
2.5V  
R
2
F
1.25V  
EXTERNAL  
(2.5V)  
*MOUNT AS CLOSE TO THE AD7452 AS POSSIBLE  
AND ENSURE HIGH PRECISION Rs AND Cs ARE USED.  
V
REF  
R
R
–50 ; C–1nF  
S
1 = R 1 = R 2 = 499 ; R 2 = 523  
G
F
F
G
220  
2
V
p-p  
REF  
V+  
390  
V
DD  
V
REF  
GND  
27  
V–  
V
V
IN+  
220  
220  
AD7452  
IN–  
V
V+  
REF  
27  
A
V–  
0.1  
F
10k  
EXTERNAL  
V
REF  
220  
2
V
p-p  
REF  
3.75V  
2.5V  
1.25V  
V+  
390  
220  
V
DD  
GND  
27  
R
R
V–  
V
IN+  
V
V
IN+  
220  
220  
C
AD7452  
AD7452  
R
IN–  
V
V
IN–  
V+  
REF  
V
REF  
3.75V  
2.5V  
A
27  
V–  
1.25V  
0.1  
F
10k  
20k  
EXTERNAL  
(2.5 V)  
EXTERNAL  
V
V
REF  
REF  
V
DD  
AD7452*  
AD780  
OPSEL  
V
REF  
NC  
1
2
3
4
8
7
6
5
NC  
NC  
V
V
DD  
IN  
2.5V  
TEMP  
GND  
V
OUT  
0.1  
F
10nF  
0.1  
F
0.1 F  
NC  
TRIM  
NC = NO CONNECT  
*ADDITIONAL PINS OMITTED FOR CLARITY  
5V  
2.5V  
0V  
R
+2.5V  
0V  
–2.5V  
R
R
V
IN  
V
V
IN+  
R
AD7452  
V
IN–  
REF  
0.1  
F
EXTERNAL  
(2.5V)  
V
REF  
CS  
10ns  
t2  
tCONVERT  
t5  
1
2
3
4
5
13  
14  
t6  
15  
16  
SCLK  
t8  
tQUIET  
12.5(1/F  
)
tACQUISITION  
SCLK  
1/THROUGHPUT  
CS  
SCLK  
1
2
10  
THREE-STATE  
SDATA  
CS  
SCLK  
SDATA  
1
10  
16  
4 LEADING ZEROS + CONVERSION RESULT  
tPOWER-UP  
PART BEGINS  
TO POWER UP  
THIS PART IS FULLY POWERED  
UP WITH V FULLY ACQUIRED  
IN  
CS  
SCLK  
A
1
10  
16  
1
10  
16  
SDATA  
INVALID DATA  
VALID DATA  
100  
10  
V
DD  
= 5V  
1
V
DD  
= 3V  
0.1  
0.01  
0
50  
100  
150  
200  
250  
300  
350  
THROUGHPUT (kSPS)  
TMS320C5x/  
C54x*  
ADSP-21xx*  
AD7452*  
AD7452*  
SCLK  
CLKx  
SCLK  
SCLK  
CLKR  
DR  
DR  
SDATA  
CS  
SDATA  
CS  
RFS  
TFS  
FSx  
FSR  
*ADDITIONAL PINS REMOVED FOR CLARITY  
*ADDITIONAL PINS REMOVED FOR CLARITY  
DSP56xxx*  
AD7452*  
SCLK  
SCLK  
SRD  
SDATA  
SR2  
CS  
*ADDITIONAL PINS REMOVED FOR CLARITY  
2.90 BSC  
8
1
7
2
6
3
5
4
1.60 BSC  
PIN 1  
2.80 BSC  
0.65 BSC  
1.95  
BSC  
1.30  
1.15  
0.90  
1.45 MAX  
0.22  
0.08  
0.60  
0.45  
0.30  
8°  
4°  
0°  
0.38  
0.22  
0.15 MAX  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-178BA  

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