EVAL-AD7887CB [ADI]
+2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC; +2.7 V至5.25 V，微功耗，双通道， 125 kSPS时， 12位ADC，采用8引脚uSOIC
| 型号： | EVAL-AD7887CB |
| 厂家： | 
ADI |
| 描述： | +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC |
| 文件： | 总16页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+2.7 V to +5.25 V, Micropower, 2-Channel,
a
125 kSPS, 12-Bit ADC in 8-Lead SOIC
AD7887
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Specified for VDD of +2.7 V to +5.25 V
Flexible Pow er/ Throughput Rate Managem ent
Shutdow n Mode: 1 A Max
One/ Tw o Single-Ended Inputs
AD7887
AIN0
I/P
MUX
T/H
Serial Interface: SPI™/ QSPI™/ MICROWIRE™/ DSP
Com patible
8-Lead Narrow SOIC and SOIC Packages
V
/
REF
AIN1
2.5V
REF
COMP
V
/AIN1
REF
APPLICATIONS
SOFTWARE
CONTROL
LATCH
V
BUF
DD
Battery-Pow ered System s (Personal Digital Assistants,
Medical Instrum ents, Mobile Com m unications)
Instrum entation and Control System s
High Speed Modem s
GND
CHARGE
REDISTRIBUTION
DAC
SAR + ADC
CONTROL LOGIC
GENERAL D ESCRIP TIO N
The AD7887 is a high speed, low power, 12-bit ADC that oper-
ates from a single +2.7 V to +5.25 V power supply. The AD7887
is capable of 125 kSPS throughput rate. T he input track-and-
hold acquires a signal in 500 ns and features a single-ended
sampling scheme. The output coding for the AD7887 is straight
binary and the part is capable of converting full power signals up to
2.5 MHz.
SPORT
DIN
SCLK
CS
DOUT
CMOS construction ensures low power dissipation of typically
2 mW for normal operation and 3 µW in power-down mode.
T he part is available in an 8-lead, 0.15-inch-wide narrow body
SOIC and an 8-lead µSOIC package.
T he AD7887 can be configured for either dual or single chan-
nel operation, via the on-chip Control Register. T here is a
default single-channel mode that allows the AD7887 to be
operated as a read-only ADC. In single-channel operation,
there is one analog input (AIN0) with the VREF/AIN1 pin as-
suming its VREF function. T his VREF pin allows the user access
to the part’s internal +2.5 V reference, or the VREF pin can be
overdriven by an external reference to provide the reference
voltage for the part. T his external reference voltage has a range
P RO D UCT H IGH LIGH TS
1. Smallest 12-bit dual/single-channel ADC; 8-lead µSOIC
package.
2. Lowest power 12-bit dual/single-channel ADC.
3. Flexible power management options including automatic
power-down after conversion.
of +2.5 V to VDD. The analog input range on AIN0 is 0 to +VREF
.
In dual-channel operation, the VREF/AIN1 pin assumes its AIN1
4. Read-Only ADC capability.
function, providing a second analog input channel. In this case,
the reference voltage for the part is provided via the VDD pin. As
a result, the input voltage range on both the AIN0 and AIN1
5. Analog input range from 0 V to VREF
.
6. Versatile serial I/O port (SPI/QSPI/MICROWIRE/DSP
compatible).
inputs is 0 to VDD
.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1999
(V = +2.7 V to +5.25 V, V = +2.5 V External/Internal Reference unless otherwise
DD
REF
1
noted, fSCLK = 2 MHz; T = T to T , unless otherwise noted.)
AD7887–SPECIFICATIONS
A
MIN
MAX
P aram eter
A Version1 B Version1 Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE
Signal to Noise + Distortion
Ratio2, 3 (SNR)
71
–80
–80
71
–80
–80
dB typ
dB typ
dB typ
fIN = 10 kHz Sine Wave, fSAMPLE = 125 kSPS
fIN = 10 kHz Sine Wave, fSAMPLE = 125 kSPS
fIN = 10 kHz Sine Wave, fSAMPLE = 125 kSPS
T otal Harmonic Distortion2 (T HD)
Peak Harmonic or Spurious Noise2
Intermodulation Distortion2 (IMD)
Second Order T erms
–80
–80
–80
2.5
–80
–80
–80
2.5
dB typ
dB typ
dB typ
MHz typ
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 125 kSPS
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 125 kSPS
fIN = 25 kHz
@ 3 dB
T hird Order T erms
Channel-to-Channel Isolation2
Full Power Bandwidth
DC ACCURACY
Resolution
Any Channel
12
±2
±2
±3
±4
±6
0.5
±2
±1
±6
2
12
±1
±1
±3
±4
±6
0.5
±2
±1
±6
2
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
LSB max
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB max
LSB typ
LSB max
Guaranteed No Missing Codes to 11 Bits (A Grade)
VDD = 5 V, Dual-Channel Mode
VDD = 3 V, Dual-Channel Mode
Single-Channel Mode
Offset Error Match2
Gain Error2
Dual-Channel Mode
Single-Channel Mode, External Reference
Single-Channel Mode, Internal Reference
Gain Error Match2
ANALOG INPUT
Input Voltage Ranges
Leakage Current
0 to VREF
±5
20
0 to VREF
±5
20
Volts
µA max
pF typ
Input Capacitance
REFERENCE INPUT /OUT PUT
REFIN Input Voltage Range
Input Impedance
2.5/VDD
10
2.5/VDD
10
V min/max
kΩ typ
Functional from 1.2 V
Very High Impedance If Internal Reference Disabled
REFOUT Output Voltage
REFOUT T empco
2.45/2.55
±50
2.45/2.55
±50
V min/max
ppm/°C typ
LOGIC INPUT S
Input High Voltage, VINH
2.4
2.1
0.8
±1
10
2.4
2.1
0.8
±1
10
V min
V min
V max
µA max
pF max
VDD = +4.75 V to +5.25 V
VDD = +2.7 V to +3.6 V
VDD = +2.7 V to +5.25 V
T ypically 10 nA, VIN = 0 V or VDD
Input Low Voltage, VINL
Input Current, IIN
4
Input Capacitance, CIN
LOGIC OUT PUT S
Output High Voltage, VOH
ISOURCE = 200 µA
VDD = +2.7 V to +5.25 V
ISINK = 200 µA
VDD – 0.5
VDD – 0.5
V min
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
0.4
±1
10
0.4
±1
10
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RAT E
T hroughput T ime
16
16
SCLK Cycles Conversion T ime + Acquisition T ime 125 kSPS
with 2 MHz Clock
SCLK Cycles
T rack/Hold Acquisition T ime2
Conversion T ime
1.5
14.5
1.5
14.5
SCLK Cycles 7.25 µs (2 MHz Clock)
–2–
REV. B
AD7887
P aram eter
A Version1 B Version1 Units
Test Conditions/Com m ents
POWER REQUIREMENT S
VDD
+2.7/+5.25 +2.7/+5.25 V min/max
IDD
Normal Mode5 (Mode 2)
Static
700
700
850
700
450
120
12
210
1
2
3.5
2.1
5
3
1.05
630
µA max
µA typ
µA typ
µA typ
µA typ
Operational (fSAMPLE = 125 kSPS) 850
700
Internal Reference Enabled
Internal Reference Disabled
fSAMPLE = 50 kSPS
fSAMPLE = 10 kSPS
fSAMPLE = 1 kSPS
VDD = +2.7 V to +5.25 V
VDD = +2.7 V to +3.6 V
VDD = +4.75 V to +5.25 V
VDD = +5 V
VDD = +3 V
VDD = +5 V
VDD = +3 V
VDD = +5 V
Using Standby Mode (Mode 4)
450
Using Shutdown Mode (Modes 1, 3) 120
12
µA typ
Standby Mode6
210
1
2
3.5
2.1
5
3
1.05
630
µA max
µA max
µA max
mW max
mW max
µW max
µW max
mW max
µW max
Shutdown Mode6
Normal Mode Power Dissipation
Shutdown Power Dissipation
Standby Power Dissipation
VDD = +3 V
NOT ES
1T emperature ranges as follows: A, B Versions: –40°C to +125°C.
2See T erminology.
3SNR calculation includes distortion and noise components.
4Sample tested @ +25°C to ensure compliance.
5All digital inputs @ GND except CS @ VDD. No load on the digital outputs. Analog inputs @ GND.
6SCLK @ GND when SCLK off. All digital inputs @ GND except for CS @ VDD. No load on the digital outputs. Analog inputs @ GND.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW
θJA T hermal Impedance . . . . . . . . . . . . . . 157°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9°C/W (µSOIC)
θJC T hermal Impedance . . . . . . . . . . . . . . . 56°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74°C/W (µSOIC)
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 kV
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to AGND . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to AGND . . . . –0.3 V to VDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ±10 mA
Operating T emperature Range
Commercial
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2T ransient currents of up to 100 mA will not cause SCR latch-up.
A, B Versions . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage T emperature Range . . . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
O RD ERING GUID E
Linearity Error (LSB)1
Model
P ackage O ptions2
Branding
AD7887AR
AD7887ARM
±2
±2
±1
SO-8
RM-8
SO-8
AD7887AR
C5A
AD7887BR
AD7887BR
EVAL-AD7887CB3
EVAL-CONT ROL BOARD4
Evaluation Board
Controller Board
NOT ES
1Linearity error here refers to integral linearity error.
2SO = SOIC; RM = µSOIC.
3T his can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONT ROL BOARD for evaluation/demonstration purposes.
4T his board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
–3–
REV. B
AD7887
TIMING SPECIFICATIONS
1
Lim it at TMIN, TMAX
(A, B Versions)
+4.75 V to +5.25 V +2.7 V to +3.6 V
P aram eter
Units
D escription
2
fSCLK
2
2
MHz max
tCONVERT
tACQ
14.5 tSCLK
1.5 tSCLK
10
30
75
20
20
0.4 tSCLK
14.5 tSCLK
1.5 tSCLK
10
60
100
20
20
0.4 tSCLK
T hroughput T ime = tCONVERT + tACQ = 16 tSCLK
CS to SCLK Setup T ime
Delay from CS Until DOUT T hree-State Disabled
Data Access T ime after SCLK Falling Edge
Data Setup T ime Prior to SCLK Rising Edge
Data Valid to SCLK Hold T ime
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to DOUT High Impedance
Power-Up T ime from Shutdown
t1
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs typ
3
t23
t3
t4
t5
t6
t7
0.4 tSCLK
80
5
0.4 tSCLK
80
5
4
t8
t9
NOT ES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 volts.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
Specifications subject to change without notice.
I
200A
OL
TO
OUTPUT
PIN
+1.6V
C
L
50pF
200A
I
OH
Figure 1. Load Circuit for Digital Output Tim ing Specifications
–4–
REV. B
AD7887
P IN CO NFIGURATIO N
1
2
3
4
8
7
6
5
SCLK
DOUT
DIN
CS
AD7887
TOP VIEW
(Not to Scale)
V
DD
GND
AIN1/V
AIN0
REF
P IN FUNCTIO N D ESCRIP TIO NS
P in
No.
P in
Mnem onic
Function
1
CS
Chip Select. Active low logic input. T his input provides the dual function of initiating conversions on the
AD7887 and also frames the serial data transfer. When the AD7887 operates in its default mode, the CS pin
also acts as the shutdown pin such that with the CS pin high, the AD7887 is in its power-down mode.
2
3
VDD
Power Supply Input. T he VDD range for the AD7887 is from +2.7 V to +5.25 V. When the AD7887 is con-
figured for two-channel operation, this pin also provides the reference source for the part.
GND
Ground Pin. T his pin is the ground reference point for all circuitry on the AD7887. In systems with separate
AGND and DGND planes, these planes should be tied together as close as possible to this GND pin. Where
this is not possible, this GND pin should connect to the AGND plane.
4
AIN1/VREF
Analog Input 1/Voltage Reference Input. In single-channel mode, this pin becomes the reference input/
output. In this case, the user can either access the internal +2.5 V reference or overdrive the internal refer-
ence with the voltage applied to this pin. T he reference voltage range for an externally-applied reference is
+1.2 V to VDD. In two-channel mode, this pin provides the second analog input channel AIN1. T he input
voltage range on AIN1 is 0 to VDD
Analog Input 0. In single-channel mode, this is the analog input and the input voltage range is 0 to VREF. In
dual-channel mode, it has an analog input range of 0 to VDD
.
5
6
AIN0
DIN
.
Data In. Logic Input. Data to be written to the AD7887’s Control Register is provided on this input and is
clocked into the register on the rising edge of SCLK (see Control Register section). T he AD7887 can be
operated as a single-channel read-only ADC by tying the DIN line permanently to GND.
7
8
DOUT
SCLK
Data Out. Logic Output. T he conversion result from the AD7887 is provided on this output as a serial data
stream. T he bits are clocked out on the falling edge of the SCLK input. T he data stream consists of four
leading zeros followed by the 12 bits of conversion data, which is provided MSB first.
Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing serial
data to the Control Register. T his clock input is also used as the clock source for the AD7887’s conversion
process.
REV. B
–5–
AD7887
TERMINO LO GY
P eak H ar m onic or Spur ious Noise
Integr al Nonlinear ity
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
T his is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. T he end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
D iffer ential Nonlinear ity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Inter m odulation D istor tion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
O ffset Er r or
T his is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.
O ffset Er r or Match
T his is the difference in Offset Error between any two channels.
Gain Er r or
T his is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1.5 LSB) after the
offset error has been adjusted out.
T he AD7887 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. T he calculation of the intermodulation distortion is as
per the T HD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Gain Er r or Match
T his is the difference in Gain Error between any two channels.
Tr ack/H old Acquisition Tim e
T he track/hold amplifier returns into track mode at the end of
conversion. T rack/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Channel-to-Channel Isolation
Signal to (Noise + D istor tion) Ratio
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 25 kHz sine wave signal to the nonselected input channel
and determining how much that signal is attenuated in the se-
lected channel. T he figure given is the worst case across both
channels for the AD7887.
T his is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. T he signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. T he
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. T he theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
P SR (P ower Supply Rejection)
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power-supply voltage from the nominal value.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
T hus for a 12-bit converter, this is 74 dB.
Total H ar m onic D istor tion
T otal harmonic distortion (T HD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7887, it is defined
as:
V22 +V32 +V42 +V52 +V62
THD (dB) = 20 log
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
–6–
REV. B
AD7887
CO NTRO L REGISTER
T he Control Register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising
edge of SCLK. T he data is transferred on the DIN line at the same time as the conversion result is read from the part. T his requires
16 serial clocks for every data transfer. Only the information provided on the first eight rising clock edges (after CS falling edge) is
loaded to the Control Register. MSB denotes the first bit in the data stream. T he bit functions are outlined in T able I. T he contents
of the Control Register on power up is all zeros.
Table I. Control Register
MSB
D O NTC
ZERO
REF
SIN/D UAL
CH
ZERO
P M1
P M0
Bit
Mnem onic
Com m ent
7
DONT C
Don’t Care. T he value written to this bit of the Control Register is a don’t care, i.e., it doesn’t matter if
the bit is 0 or 1.
6
5
ZERO
REF
A zero must be written to this bit to ensure correct operation of the AD7887.
Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip
reference is disabled.
4
3
SIN/DUAL
Single/Dual Bit. T his bit determines whether the AD7887 operates in single-channel or dual-channel
mode. A 0 in this bit selects single-channel operation and the AIN1/VREF pin assumes its VREF function.
A 1 in this bit selects dual-channel mode and the reference voltage for the ADC is internally connected
to VDD and the AIN1/VREF pin assumes its AIN1 function as the second analog input channel. T o
obtain best performance from the AD7887, the internal reference should be disabled when operating in
the dual channel mode, i.e., REF = 1.
CH
Channel Bit. When the part is selected for dual-channel mode, this bit determines which channel will be
converted for the next conversion. A 0 in this bit selects the AIN0 input while a 1 in this bit selects the
AIN1 input. In single-channel mode, this bit should always be 0.
2
ZERO
A zero must be written to this bit to ensure correct operation of the AD7887.
1, 0
PM1, PM0
Power Management Bits. T hese two bits decode the mode of operation of the AD7887 as described
below.
Table II. P ower Managem ent O ptions
Mode
P M1
P M0
0
0
Mode 1. In this mode, the AD7887 enters shutdown if the CS input is 1 and is in full power mode when
CS is 0. T hus the part comes out of shutdown on the falling edge of CS and enters shutdown on the
rising edge of CS.
0
1
1
1
0
1
Mode 2. In this mode, the AD7887 is always fully powered up, regardless of the status of any of the logic
inputs.
Mode 3. In this mode, the AD7887 automatically enters shutdown mode at the end of each conversion,
regardless of the state of CS.
Mode 4. In this standby mode, portions of the AD7887 are powered down but the on-chip reference
voltage remains powered up. T his mode is similar to Mode 3, but allows the part to power up much
faster. T he REF bit should be 0 to ensure the on-chip reference is enabled.
REV. B
–7–
AD7887
P ERFO RMANCE CURVES
Figure 2 shows a typical FFT plot for the AD7887 at 125 kHz
sample rate and 10 kHz input frequency.
–75
–77
–79
–81
V
= +5.5V/+2.7V
DD
100mV p-p SINE WAVE ON V
DD
REF = 2.488V EXT REFERENCE
IN
0
4096 POINT FFT
SAMPLING
125kSPS
= 10kHz
SNR = 71dB
–83
–85
–87
–10
–30
–50
f
IN
–89
–91
–93
–70
–90
64.15
2.65
12.85
23.15
33.65
43.85
54.35
INPUT FREQUENCY – kHz
Figure 4. PSRR vs. Frequency
CIRCUIT INFO RMATIO N
–110
T he AD7887 is a fast, low power, 12-bit, single supply, single-
channel/dual-channel A/D converter. T he part can be operated
from a +3 V (+2.7 V to +3.6 V) supply or from a +5 V (+4.75 V to
+5.25 V) supply. When operated from either a +5 V or +3 V
supply, the AD7887 is capable of throughput rates of 125 kSPS
when provided with a 2 MHz clock.
Figure 2. Dynam ic Perform ance
Figure 3 shows the SNR vs. Frequency for a 5 V supply with a
5 V external reference.
T he AD7887 provides the user with an on-chip track/hold, A/D
converter, reference and serial interface housed in an 8-lead
package. T he serial clock input accesses data from the part and
also provides the clock source for the successive approximation
A/D converter. T he part can be configured for single-channel or
dual-channel operation. When configured as a single-channel
part, the analog input range is 0 to VREF (where the externally-
applied VREF can be between +1.2 V and VDD). When the
AD7887 is configured for two input channels, the input range is
73.0
V
= 5V
DD
5V EXT REFERENCE
72.5
72.0
determined by internal connections to be 0 to VDD
.
71.5
71.0
If single-channel operation is required, the AD7887 can be
operated in a read-only mode by tying the DIN line permanently to
GND. For applications where the user wants to change the
mode of operation or wants to operate the AD7887 as a dual-
channel A/D converter, the DIN line can be used to clock data
into the part’s control register.
10.89
21.14
31.59
42.14
0.15
INPUT FREQUENCY – kHz
Figure 3. SNR vs. Input Frequency
Figure 4 shows the power supply rejection ratio versus fre-
quency for the part. T he power supply rejection ratio is defined
as the ratio of the power in the ADC output at frequency f to
the power of a full-scale sine wave applied to the ADC of fre-
quency fS:
CO NVERTER O P ERATIO N
T he AD7887 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. Figures 5
and 6 show simplified schematics of the ADC. Figure 5 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in position A, the comparator is held in a balanced condition
and the sampling capacitor acquires the signal on AIN.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fS in ADC full-scale input. Here a 100 mV peak-to-peak
sine wave is coupled onto the VDD supply. Both the +2.7 V and
+5.5 V supply performances are shown.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
AIN
CONTROL
LOGIC
SW1
B
ACQUISITION
PHASE
AGND
SW2
COMPARATOR
(REF IN/REF OUT)/2
Figure 5. ADC Acquisition Phase
–8–
REV. B
AD7887
When the ADC starts a conversion (see Figure 6), SW2 will
open and SW1 will move to Position B causing the comparator
to become unbalanced. T he control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced the conversion is complete. T he control logic generates
the ADC output code. Figure 7 shows the ADC transfer function.
SUPPLY +2.7V
TO +5.25V
10F
0.1F
SERIAL
INTERFACE
V
DD
AD7887
AIN1
SCLK
0V TO V
DD
C/P
INPUT
DOUT
DIN
AIN2
GND
CHARGE
REDISTRIBUTION
DAC
CS
SAMPLING
CAPACITOR
A
V
IN
Figure 8. Typical Connection Diagram
Analog Input
CONTROL
LOGIC
SW1
B
CONVERSION
PHASE
SW2
AGND
COMPARATOR
Figure 9 shows an equivalent circuit of the analog input structure
of the AD7887. T he two diodes D1 and D2 provide ESD pro-
tection for the analog inputs. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 200 mV. T his will cause these diodes to become forward
biased and start conducting current into the substrate. 20 mA is
the maximum current these diodes can conduct without causing
irreversible damage to the part. However, it is worth noting that
a small amount of current (1 mA) being conducted into the
substrate due to an overvoltage on an unselected channel can
cause inaccurate conversions on a selected channel. T he capaci-
tor C1 in Figure 9 is typically about 4 pF and can primarily be
attributed to pin capacitance. T he resistor R1 is a lumped
component made up of the on resistance of a multiplexer and a
switch. T his resistor is typically about 100 Ω. T he capacitor C2
is the ADC sampling capacitor and typically has a capacitance
of 20 pF.
REF IN/REF OUT/2
Figure 6. ADC Conversion Phase
AD C TRANSFER FUNCTIO N
T he output coding of the AD7887 is straight binary. T he de-
signed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). T he LSB size is = VREF/4096. T he
ideal transfer characteristic for the AD7887 is shown in Figure 7.
111...111
111...110
111...000
1LSB = V
/4096
REF
Note: T he analog input capacitance seen when in track mode is
typically 38 pF while in hold mode it is typically 4 pF.
011...111
000...010
000...001
000...000
V
DD
+V
– 1.5LSB
0.5LSB
REF
D1
C2
0V
ANALOG INPUT
20pF
R1
V
IN
Figure 7. Transfer Characteristic
TYP ICAL CO NNECTIO N D IAGRAM
C1
4pF
D2
CONVERSION PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
Figure 8 shows a typical connection diagram for the AD7887.
T he GND pin is connected to the analog ground plane of the
system. T he part is in dual-channel mode so VREF is internally
connected to a well decoupled VDD pin to provide an analog
input range of 0 V to VDD. T he conversion result is output in a
16-bit word with four leading zeros followed by the MSB of the
12-bit result. For applications where power consumption is of
concern, the automatic power-down at the end of conversion
should be used to improve power performance. See Modes of
Operation section of the data sheet.
Figure 9. Equivalent Analog Input Circuit
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the relevant analog input pin. In applications
where harmonic distortion and signal to noise ratio are critical,
the analog input should be driven from a low impedance source.
Large source impedances will significantly affect the ac perfor-
mance of the ADC. T his may necessitate the use of an input
buffer amplifier. T he choice of the op amp will be a function of
the particular application.
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. T he maximum
source impedance will depend on the amount of total harmonic
distortion (T HD) that can be tolerated. T he T HD will increase
REV. B
–9–
AD7887
as the source impedance increases and performance will degrade.
Figure 10 shows a graph of the total harmonic distortion versus
analog input signal frequency for different source impedances.
PM1 = PM0 = 0, the part will enter shutdown on the rising
edge of CS and power up from shutdown on the falling edge of
CS. If CS is brought high during the conversion in this mode,
the part will immediately enter shutdown.
–65
P ower -Up Tim es
THD vs. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
T he AD7887 has an approximate 1 µs power-up time when
powering up from standby or when using an external reference.
When VDD is first connected the AD7887 will power up in
Mode 1, i.e., PM1 = PM0 = 0. T he part is put into shutdown
on the rising edge of CS in this mode. A subsequent power-up
from shutdown will take approximately 5 µs. T he AD7887
wake-up time is very short in the autostandby mode so it is
possible to wake-up the part and carry out a valid conversion in
the same read/write operation.
V
= 5V
DD
–70
–75
5V EXT REFERENCE
R
= 1k⍀, C = 100pF
IN
IN
R
= 50⍀, C = 2.2nF
IN
IN
–80
–85
–90
P O WER VS. TH RO UGH P UT RATE
By operating the AD7887 in autoshutdown, autostandby mode
or Mode 1, the average power consumption of the AD7887
decreases at lower throughput rates. Figure 12 shows how, as
the throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
R
= 10⍀, C = 10nF
IN
IN
0.15
10.89
21.14
31.59
42.14
49.86
INPUT FREQUENCY – kHz
Figure 10. THD vs. Analog Input Frequency
O n-Chip Refer ence
For example if the AD7887 is operated in a continuous sam-
pling mode with a throughput rate of 10 kSPS and a SCLK of
2 MHz (VDD = 5 V), and if PM1 = 1 and PM0 = 0, i.e., the
device is in autoshutdown mode, and the on-chip reference is
used, the power consumption is calculated as follows. The power
dissipation during normal operation is 3.5 mW (VDD = 5 V). If
the power-up time is 5 µs, and the remaining conversion plus
acquisition time is 15.5 tSCLK, i.e., approximately 7.75 µs, (see
Figure 15a), the AD7887 can be said to dissipate 3.5 mW for
12.75 µs during each conversion cycle. If the throughput rate is
10 kSPS, the cycle time is 100 µs and the average power dissi-
pated during each cycle is (12.75/100) × (3.5 mW) = 446.25 µW.
If VDD = 3 V, SCLK = 2 MHz and the device is again in auto-
shutdown mode using the on-chip reference, then the power
dissipation during normal operation is 2.1 mW. T he AD7887
can now be said to dissipate 2.1 mW for 12.75 µs during each
conversion cycle. With a throughput rate of 10 kSPS, the aver-
age power dissipated during each cycle is (12.75/100) × (2.1 mW)
= 267.75 µW. Figure 12 shows the Power vs. T hroughput Rate
for automatic shutdown with both 5 V and 3 V supplies.
T he AD7887 has an on-chip 2.5 V reference. T his reference can
be enabled or disabled by clearing or setting the REF bit in the
control register respectively. If the on-chip reference is to be
used externally in a system then it must be buffered before it is
applied elsewhere. If an external reference is applied to the
device, then the internal reference is automatically overdriven.
However, it is advised to disable the internal reference by setting
the REF bit in the control register when an external reference is
applied in order to obtain optimum performance from the de-
vice. When the internal reference is disabled, SW1 in Figure 11
will open and the input impedance seen at the AIN1/VREF pin is
the input impedance of the reference buffer, which is in the
region of gigaohms. When the internal reference is enabled the
input impedance seen at the pin is typically 10 kΩ. When the
AD7887 is operated in two-channel mode, the reference is taken
from VDD internally and not from the on-chip 2.5 V reference.
AIN1/V
REF
SW1
10k⍀
10
2.5V
Figure 11. On-Chip Reference Circuitry
V
= 5V
DD
SCLK = 2MHz
1
P O WER-D O WN O P TIO NS
T he AD7887 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate.
V
= 3V
DD
SCLK = 2MHz
0.1
T he power management options are selected by programming
the power management bits (i.e., PM1 and PM0) in the control
register. T able II summarizes the available options. When the
power management bits are programmed for either of the auto
power-down modes, the part will enter power-down mode on
the 16th rising SCLK edge after the falling edge of CS. T he
first falling SCLK edge after the CS falling edge will cause the
part to power up again. When the AD7887 is in Mode 1, i.e.,
0.01
0
10
20
30
40
50
THROUGHPUT – kSPS
Figure 12. Power vs. Throughput
–10–
REV. B
AD7887
MO D ES O F O P ERATIO N
falling edge and second SCLK rising edge by up to 5 µs without
affecting the speed of the rest of the serial clock. T herefore, the
user will need to write to the Control Register to exit this mode
and (by writing PM1 = 0 and PM0 = 1) put the part into Mode
2, i.e., normal mode. A second conversion will then need to be
initiated when the part is powered-up to get a conversion result.
T he write operation which takes place in conjunction with this
second conversion can put the part back into Mode 1 and the
part will go into power-down mode when CS returns high.
T he AD7887 has a number of different modes of operation.
T hese are designed to provide flexible power management op-
tions. T hese options can be chosen to optimize the power dissi-
pation/throughput rate ratio for differing application requirements.
The modes of operation are controlled by the PM1 and PM0 bits
of the Control Register as previously outlined. For read-only
operation of the AD7887, the default mode of all 0s in the Con-
trol Register can be set up by tying the DIN line permanently
low.
Mode 2 (P M1 = 0, P M0 = 1)
Mode 1 (P M1 = 0, P M0 = 0)
In this mode of operation, the AD7887 remains fully powered
up regardless of the status of the CS line. It is intended for
fastest throughput rate performance as the user does not have to
worry about the 5 µs power-up time previously mentioned.
Figure 14 shows the general diagram of the operation of the
AD7887 in this mode.
T his mode allows the user to control the powering down of the
part via the CS pin. Whenever CS is low, the AD7887 is fully
powered up; whenever CS is high, the AD7887 is in full shut-
down. When CS goes from high to low, all on-chip circuitry
starts to power up. It takes approximately, 5 µs for the AD7887
internal circuitry to be fully powered up. As a result, a conver-
sion (or sample-and-hold acquisition) should not be initiated
during this 5 µs.
T he data presented to the AD7887 on the DIN line during the
first eight clock cycles of the data transfer are loaded to the
Control Register. T o continue to operate in this mode, the user
must ensure that PM1 is loaded with 0 and PM0 is loaded with
1 on every data transfer.
Figure 13 shows a general diagram of the operation of the AD7887
in this mode. T he input signal is sampled on the second rising
edge of SCLK following the CS falling edge. T he user should
ensure that 5 µs elapses between the falling edge of CS and the
second rising edge of SCLK. In microcontroller applications,
this is readily achievable by driving the CS input from one of the
port lines and ensuring that the serial data read (from the micro-
controllers serial port) is not initiated for 5 µs. In DSP applica-
tions, where the CS is generally derived from the serial frame
synchronization line, it is usually not possible to separate the CS
T he falling edge of CS initiates the sequence and the input
signal is sampled on the second rising edge of the SCLK input.
Sixteen serial clock cycles are required to complete the conver-
sion and access the conversion result. Once a data transfer is
complete (CS has returned high), another conversion can be
initiated immediately by bringing CS low again.
THE PART POWERS UP ON CS
THE PART POWERS DOWN ON CS
FALLING EDGE AS PM1 AND PM0 = 0
RISING EDGE AS PM1 AND PM0 = 0
CS
16
1
SCLK
4 LEADING ZEROS + CONVERSION RESULT
DOUT
DIN
DATA IN
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE
Figure 13. Mode 1 Operation
THE PART REMAINS POWERED UP
AT ALL TIMES AS
PM1 = 0 AND PM0 = 1
CS
16
1
SCLK
DOUT
DIN
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE
Figure 14. Mode 2 Operation
–11–
REV. B
AD7887
Mode 3 (P M1 = 1, P M0 = 0)
part into Mode 2. A second conversion will then need to be
initiated when the part is powered up to get a conversion result, as
shown in Figure 15b. The write operation that takes place in
conjunction with this second conversion can put the part back
into Mode 3 and the part will go into power-down mode when
the conversion sequence ends.
In this mode, the AD7887 automatically enters its full shutdown
mode at the end of every conversion. It is similar to Mode 1
except that the status of CS does not have any effect on the
power-down status of the AD7887.
Figure 15a shows the general diagram of the operation of the
AD7887 in this mode. On the first falling SCLK edge after CS
goes low, all on-chip circuitry starts to power up. It takes ap-
proximately, 5 µs for the AD7887 internal circuitry to be fully
powered up. As a result, a conversion (or sample-and-hold
acquisition) should not be initiated during this 5 µs. T he input
signal is sampled on the second rising edge of SCLK following
the CS falling edge. T he user should ensure that 5 µs elapses
between the first falling edge of SCLK and the second rising
edge of SCLK after the CS falling edge as shown in Figure 15a.
In microcontroller applications (or with a slow serial clock) this
is readily achievable by driving the CS input from one of the
port lines and ensuring that the serial data read (from the micro-
controller’s serial port) is not initiated for 5 µs. However, for
higher speed serial clocks it will not be possible to have a 5 µs
delay between powering up and the first rising edge of the SCLK.
T herefore, the user will need to write to the Control Register to
exit this mode and (by writing PM1 = 0 and PM0 = 1) put the
Mode 4 (P M1 = 1, P M0 = 1)
In this mode, the AD7887 automatically enters a standby (or
sleep) mode at the end of every conversion. In this standby
mode, all on-chip circuitry, apart from the on-chip reference, is
powered down. T his mode is similar to Mode 3 but in this case,
the power-up time is much shorter as the on-chip reference
remains powered up at all times.
Figure 16 shows the general diagram of the operation of the
AD7887 in this mode. On the first falling SCLK edge after CS
goes low, the AD7887 comes out of standby. T he AD7887
wake-up time is very short in this mode so it is possible to wake-
up the part and carry out a valid conversion in the same read/
write operation. T he input signal is sampled on the second
rising edge of SCLK following the CS falling edge. At the end of
conversion (last rising edge of SCLK) the part automatically
enters its standby mode.
THE PART ENTERS
THE PART POWERS UP FROM
SHUTDOWN ON SCLK FALLING EDGE AS
PM1 = 1 AND PM0 = 0
SHUTDOWN AT THE END OF
CONVERSION AS PM1 = 1 AND PM0 = 0
CS
16
16
1
2
1
SCLK
t10 = 5s
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
DOUT
DIN
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
CONTROL REGISTER DATA IS LOADED ON THE
FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0
PM1 = 1 AND PM0 = 0 TO KEEP THE
PART IN THIS MODE
Figure 15a. Mode 3 Operation
THE PART ENTERS
SHUTDOWN AT THE END
OF CONVERSION AS
PM1 = 1 AND PM0 = 0
THE PART ENTERS
SHUTDOWN AT THE END OF
CONVERSION AS PM1 = 1
AND PM0 = 0
THE PART BEGINS TO POWER
UP FROM SHUTDOWN
THE PART REMAINS POWERED UP
AS PM1 = 0 AND PM0 = 1
CS
8
16
8
16
1
1
1
8
16
SCLK
4 LEADING ZEROS
4 LEADING ZEROS
4 LEADING ZEROS
DOUT
DIN
+ CONVERSION RESULT
+ CONVERSION RESULT
+ CONVERSION RESULT
DATA IN
DATA IN
DATA IN
CONTROL REGISTER DATA IS LOADED ON
THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0
PM1 = 0 AND PM0 = 1 TO PLACE
THE PART IN NORMAL MODE
PM1 = 1 AND PM0 = 0 TO PLACE
THE PART BACK IN MODE 3
Figure 15b. Mode 3 Operation
–12–
REV. B
AD7887
THE PART POWERS UP
FROM STANDBY ON SCLK
FALLING EDGE AS PM1 = 1
AND PM0 = 1
THE PART ENTERS
STANDBY AT THE END OF
CONVERSION AS
PM1 = 1 AND PM0 = 1
CS
16
16
1
1
SCLK
4 LEADING ZEROS + CONVERSION RESULT
4 LEADING ZEROS + CONVERSION RESULT
DOUT
DIN
DATA IN
DATA IN
CONTROL REGISTER DATA IS LOADED ON
THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 1
PM1 = 1 AND PM0 = 1 TO KEEP
THE PART IN THIS MODE
Figure 16. Mode 4 Operation
SERIAL INTERFACE
write the channel address for the next conversion while the
present conversion is in progress.
Figure 17 shows the detailed timing diagrams for serial interfac-
ing to the AD7887. T he serial clock provides the conversion
clock and also controls the transfer of information to and from
the AD7887 during conversion.
Writing of information to the Control Register takes place on the
first eight rising edges of SCLK in a data transfer. T he Control
Register is always written to when a data transfer takes place.
However, the AD7887 can be operated in a read-only mode by
tying DIN low, thereby loading all 0s to the Control Register
every time. When operating the AD7887 in write/read mode, the
user must be careful to always set up the correct information on
the DIN line when reading data from the part.
CS initiates the data transfer and conversion process. For some
modes, the falling edge of CS wakes up the part. In all cases, it
gates the serial clock to the AD7887 and puts the on-chip track/
hold into track mode. T he input signal is sampled on the second
rising edge of the SCLK input after the falling edge of CS. Thus,
the first one and one-half clock cycles after the falling edge of
CS are when the acquisition of the input signal takes place. T his
time is denoted as the acquisition time (tACQ). In modes where
the falling edge of CS wakes up the part, the acquisition time
must allow for the wake-up time of 5 µs. T he on-chip track/hold
goes from track mode to hold mode on the second rising edge of
SCLK and a conversion is also initiated on this edge. T he con-
version process takes a further fourteen and one-half SCLK
cycles to complete. T he rising edge of CS will put the bus back
into three-state. If CS is left low a new conversion will be initiated.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7887. In applications
where the first serial clock edge, following CS going low, is a
falling edge, this edge clocks out the first leading zero. T hus, the
first rising clock edge on the SCLK clock has the first leading
zero provided. In applications where the first serial clock edge,
following CS going low, is a rising edge, the first leading zero
may not be set up in time for the processor to read it correctly.
However, subsequent bits are clocked out on the falling edge of
SCLK so that they are provided to the processor on the follow-
ing rising edge. T hus, the second leading zero is clocked out on
the falling edge subsequent to the first rising edge. T he final bit
in the data transfer is valid on the sixteenth rising edge, having
being clocked out on the previous falling edge.
In dual-channel operation, the input channel that is sampled is
the one that was selected in the previous write to the Control
Register. T hus, in dual-channel operation the user must write
ahead the channel for conversion. In other words, the user must
tACQ
tCONVERT
CS
t6
t1
16
1
2
3
4
5
6
15
SCLK
DOUT
t8
t2
t7
t3
THREE-
STATE
THREE-
STATE
4 LEADING ZEROS
DB11
DB10
DB9
DB0
t4
t5
ZERO
REF
SIN/DUAL
CH
ZERO
PM1
PM0
DONTC
DIN
Figure 17. Serial Interface Tim ing Diagram
REV. B
–13–
AD7887
MICRO P RO CESSO R INTERFACING
T he T imer registers etc., are loaded with a value that will pro-
vide an interrupt at the required sample interval. When an inter-
rupt is received, a value is transmitted with T FS/DT (ADC
control word). T he T FS is used to control the RFS and hence
the reading of data. T he frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
T FS is given (i.e., AX0 = T X0), the state of the SCLK is
checked. T he DSP will wait until the SCLK has gone High,
Low and High before transmission will start. If the timer and
SCLK values are chosen such that the instruction to transmit
occurs on or near the rising edge of SCLK, the data may be
transmitted or it may wait until the next clock edge.
T he serial interface on the AD7887 allows the part to be directly
connected to a range of many different microprocessors. T his
section explains how to interface the AD7887 with some of the
more common microcontroller and DSP serial interface protocols.
AD 7887 to TMS320C5x
T he serial interface on the T MS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7887.
T he CS input allows easy interfacing with an inverter between
the serial clock of the T MS320C5x and the AD7887 being the
only glue logic required. T he serial port of the T MS320C5x is
set up to operate in burst mode with internal CLKX (T X serial
clock) and FSX (T X frame sync). T he serial port control regis-
ter (SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1 and T XM = 1. T he connection diagram is shown in
Figure 18.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3
then a SCLK of 2 MHz is obtained, and 8 master clock periods
will elapse for every 1 SCLK period. If the timer registers are
loaded with the value 803, then 100.5 SCLKs will occur be-
tween interrupts and subsequently between transmit instruc-
tions. T his situation will result in nonequidistant sampling as
the transmit instruction is occurring on an SCLK edge. If the
number of SCLKs between interrupts is a whole integer number
of N, equidistant sampling will be implemented by the DSP.
TMS320C5x*
AD7887*
CLKX
CLKR
DR
SCLK
DOUT
DIN
DT
ADSP-21xx*
AD7887*
CS
FSX
FSR
SCLK
SCLK
DR
DOUT
DIN
DT
*ADDITIONAL PINS OMITTED FOR CLARITY
RFS
TFS
CS
Figure 18. Interfacing to the TMS320C5x
AD 7887 to AD SP -21xx
*ADDITIONAL PINS OMITTED FOR CLARITY
T he ADSP-21xx family of DSPs are easily interfaced to the
AD7887 with an inverter between the serial clock of the ADSP-
21xx and the AD7887. This is the only glue logic required. T he
SPORT control register should be set up as follows:
Figure 19. Interfacing to the ADSP-21xx
AD 7887 to D SP 56xxx
T he connection diagram in Figure 20 shows how the AD7887
can be connected to the SSI (Synchronous Serial Interface) of
the DSP56xxx family of DSPs from Motorola. T he SSI is oper-
ated in Synchronous Mode (SYN bit in CRB = 1) with inter-
nally generated 1-bit clock period frame sync for both T X and
RX (Bits FSL1 =1 and FSL0 =0 in CRB). Set the word length
to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An inverter
is also necessary between the SCLK from the DSP56xxx and
the SCLK pin of the AD7887 as shown in Figure 20.
T FSW = RFSW = 1, Alternate Framing
INVRFS = INVT FS = 1, Active Low Frame Signal
DT YPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 1, Internal Serial Clock
T FSR = RFSR = 1, Frame Every Word
IRFS = 0
IT FS = 1
T he connection diagram is shown in Figure 19. T he ADSP-
21xx has the T FS and RFS of the SPORT tied together, with
T FS set as an output and RFS set as an input. T he DSP oper-
ates in Alternate Framing Mode and the SPORT control regis-
ter is set up as described. T he Frame synchronization signal
generated on the T FS is tied to CS and as with all signal pro-
cessing applications equidistant sampling is necessary. In this
example however, the timer interrupt is used to control the
sampling rate of the ADC and under certain conditions, equi-
distant sampling may not be achieved.
DSP56xxx*
AD7887*
SCLK
SCK
DOUT
DIN
SRD
STD
SC2
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the DSP56xxx
–14–
REV. B
AD7887
AD 7887 to MC68H C11
AP P LICATIO N H INTS
Gr ounding and Layout
T he AD7887 has very good immunity to noise on the power
supplies as can be seen in Figure 4. However, care should still
be taken with regard to grounding and layout.
T he Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MST R = 1), Clock Polarity Bit
(CPOL) = 1 and the Clock Phase Bit (CPHA) = 1. T he SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 user manual. T he serial transfer will take place as two
8-bit operations. A connection diagram is shown in Figure 21.
T he printed circuit board that houses the AD7887 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. T his facilitates the use of
ground planes that can be easily separated. A minimum etch
technique is generally best for ground planes as it gives the best
shielding. Digital and analog ground planes should be joined in
only one place, as close as possible to the GND pin of the
AD7887. If the AD7887 is in a system where multiple devices
require AGND-to-DGND connections, the connection should
still be made at one point only, a star ground point, which should
be established as close as possible to the AD7887.
MC68HC11*
AD7887*
SCLK/PD4
MISO/PD2
MOSI/PD3
SCLK
DOUT
DIN
PA0
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Avoid running digital lines under the device as these will couple
noise onto the die. T he analog ground plane should be allowed
to run under the AD7887 to avoid noise coupling. T he power
supply lines to the AD7887 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. T races on opposite sides of the board should
run at right angles to each other. T his will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Figure 21. Interfacing to the MC68HC11
AD 7887 to 8051
It is possible to implement a serial interface using the data ports
on the 8051. T his allows a full duplex serial transfer to be
implemented. T he technique involves “bit-banging” an I/O port
(e.g., P1.0) to generate a serial clock and using two other I/O ports
(e.g., P1.1 and P1.2) to shift data in and out—see Figure 22.
8051*
AD7887*
P1.0
P1.1
P1.2
P1.3
SCLK
DOUT
DIN
CS
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum in parallel with 0.1 µF
capacitors to AGND. T o achieve the best from these decoupling
components, they must be placed as close as possible to the
device, ideally right up against the device.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing to the 8051 Using I/O Ports
AD 7887 to P IC16C6x/7x
Evaluating the AD 7887 P er for m ance
T he PIC16C6x Synchronous Serial Port (SSP) is configured as
an SPI Master with the Clock Polarity Bit = 1. T his is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
Figure 23 shows the hardware connections needed to interface
to the PIC16C6x/7x. In this example I/O port RA1 is being used
to pulse CS. T his microcontroller only transfers eight bits of
data during each serial transfer operation. Therefore two consecu-
tive read/write operations are needed.
T he recommended layout for the AD7887 is outlined in the
evaluation board for the AD7887. T he evaluation board pack-
age includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the EVAL-CONT ROL BOARD. T he EVAL-CON-
T ROL BOARD can be used in conjunction with the AD7887
Evaluation board, as well as many other Analog Devices evalua-
tion boards ending in the CB designator, to demonstrate/
evaluate the ac and dc performance of the AD7887.
T he software allows the user to perform ac (fast Fourier trans-
form) and dc (histogram of codes) tests on the AD7887.
PIC16C6x/7x*
SCK/RC3
AD7887*
SCLK
SDI/RC4
SDO/RC5
RA1
DOUT
DIN
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing to the PIC16C6x/7x
REV. B
–15–
AD7887
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead Narrow Body (SO IC)
(SO -8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
8-Lead SO IC
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33؇
0.018 (0.46)
0.008 (0.20)
27؇
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
–16–
REV. B
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