EVAL-ADCMP605BCPZ1 [ADI]
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators; 轨到轨，速度非常快， 2.5 V至5.5 V ，单电源LVDS比较器
| 型号： | EVAL-ADCMP605BCPZ1 |
| 厂家： | 
ADI |
| 描述： | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| 文件： | 总16页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply LVDS Comparators
ADCMP604/ADCMP605
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
CCO
Fully specified rail to rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
Low glitch LVDS-compatible output stage
1.6 ns propagation delay
37 mW at 2.5 V
Shutdown pin
V
CCI
(ADCMP605 ONLY)
V
NONINVERTING
INPUT
P
Q OUTPUT
Q OUTPUT
ADCMP604/
ADCMP605
LVDS
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB
V
INVERTING
INPUT
N
−40°C to +125°C operation
LE/HYS INPUT
APPLICATIONS
(ADCMP605
ONLY)
S
INPUT
DN
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
Figure 1.
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
to +6 V input signal range. Split input/output supplies, with no
sequencing restrictions on the ADCMP605, support a wide
input signal range with greatly reduced power consumption.
The ADCMP604 and ADCMP605 are very fast comparators
fabricated on Analog Devices, Inc.’s, proprietary XFCB2
process. This family of comparators is exceptionally versatile
and easy to use. Features include an input range from VEE − 0.5
V to VCC + 0.2 V, low noise, LVDS-compatible output drivers,
and TTL/CMOS latch inputs with adjustable hysteresis and/or
shutdown inputs.
The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
High speed latch and programmable hysteresis features are also
provided in a unique single-pin control option.
The devices offer 1.5 ns propagation delays with 1 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
The ADCMP604 is available in a 6-lead SC70 package. The
ADCMP605 is available in a 12-lead LFCSP.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.5 V
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADCMP604/ADCMP605
TABLE OF CONTENTS
Features .............................................................................................. 1
Power/Ground Layout and Bypassing..................................... 10
LVDS-Compatible Output Stage.............................................. 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance........................................................... 10
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 11
Crossover Bias Points................................................................. 12
Minimum Input Slew Rate Requirement................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Application Information................................................................ 10
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADCMP604/ADCMP605
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 3.0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Voltage Range
Common-Mode Range
Differential Voltage
Offset Voltage
Bias Current
Offset Current
Capacitance
VP, VN
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
−0.5
−0.2
VCC + 0.2
VCC + 0.2
VCC
+5.0
+5.0
V
V
V
VOS
IP, IN
−5.0
−5.0
−2.0
mV
μA
μA
pF
kΩ
kΩ
dB
dB
2
2.0
CP, CN
1
Resistance, Differential Mode
Resistance, Common Mode
Active Gain
−0.1 V to VCC
−0.5 V to VCC + 0.5 V
200
100
750
370
62
7500
4000
AV
CMRR
Common-Mode Rejection Ratio
VCCI = 2.5 V, VCCO = 2.5 V,
50
50
V
CM = −0.2 V to +2.7 V
VCCI = 2.5 V, VCCO = 5.5 V,
RHYS = ∞
dB
mV
Hysteresis
< 0.1
+0.4
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP605 Only)
VIH
VIL
LIH
IOL
Hysteresis is shut off
Latch mode guaranteed
VIH = VCCO + 0.2 V
VIL = 0.4 V
2.0
−0.2
−6
VCC
+0.8
+6
V
V
μA
mA
−0.1
+0.1
HYSTERESIS MODE AND TIMING
(ADCMP605 Only)
Hysteresis Mode Bias Voltage
Minimum Resistor Value
Hysteresis Current
Latch Setup Time
Latch Hold Time
Latch-to-Output Delay
Latch Minimum Pulse Width
SHUTDOWN PIN CHARACTERISTICS
(ADCMP605 Only)
VIH
Current sink -1ꢀA
Hysteresis = 120 mV
Hysteresis = 120 mV
VOD = 50 mV
VOD = 50 mV
VOD = 50 mV
1.145
55
−20
1.25
1.35
110
−10
V
kΩ
μA
ns
ns
ns
ns
tS
tH
−2
2.7
20
24
tPLOH, tPLOL
tPL
VOD = 50 mV
Comparator is operating
Shutdown guaranteed
VIH = VCC
2.0
−0.2
−6
VCCO
+0.6
+6
V
V
μA
mA
ns
ns
VIL
IIH
IOL
+0.4
VIL = 0 V
−0.1
Sleep Time
Wake-Up Time
tSD
tH
10% output swing
VOD = 50 mV, output valid
VCCO = 2.5 V to 5.5 V
RLOAD = 100 Ω
RLOAD = 100 Ω
RLOAD = 100 Ω
1.4
25
DC OUTPUT CHARACTERISTICS
Differential Output Voltage Level
∆VOD
Common-Mode Voltage
Peak-to-Peak Common-Mode Output
VOD
∆VOD
VOC
245
350
445
50
1.375
50
mV
mV
V
1.125
VOC(p-p)
RLOAD = 100 Ω
mV
Rev. 0 | Page 3 of 16
ADCMP604/ADCMP605
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AC PERFORMANCE1
Rise Time /Fall time
Propagation Delay
tR, tF
tPD
10% to 90%
600
1.6
3.0
70
ps
ns
ns
ps
VCC = 2.5 V to 5.5 V, VOD = 50 mV
VCC = 2.5 V , VOD = 10 mV
VCC = 2.5 V to 5.5 V
Propagation Delay Skew—Rising to
Falling Transition
tPINSKEW
Propagation Delay Skew—Q to QB
Overdrive Dispersion
Common-Mode Dispersion
Input Bandwidth
VCC = 2.5 V to 5.5 V
10 mV < VOD < 125 mV
VCM = −0.2 V to VCC + 0.2 V
70
ps
ns
ps
MHz
ns
1.6
250
500
1.3
Minimum Pulse Width
PWMIN
VCC = 2.5 V to 5.5 V
PWOUT = 90% of PWIN
POWER SUPPLY
Input Supply Voltage Range
Output Supply Voltage Range
Positive Supply Differential (ADCMP605) VCCI − VCCO
VCCI − VCCO
Positive Supply Current
(ADCMP604)
Input Section Supply Current
(ADCMP605)
VCCI
VCCO
2.5
2.5
−3
5.5
5.5
+3
+5.5
21
V
V
V
V
Operating
Nonoperating
VCC = 2.5 V to 5.5 V
−5.5
IVCC
15
1
mA
IVCCI
IVCCO
VCCI = 2.5 V to 5.5 V
VCCO = 2.5 V to 5.5 V
3
mA
Output Section Supply Current
(ADCMP605)
Power Dissipation
15
22
2.75
50
mA
mA
mW
mW
dB
PD
VCC = 2.5 V
VCC = 5.5 V
VCCI = 2.5 V to 5.5 V
VCCI = 2.5 V to 5.5 V
VCCI = 2.5 V to 5.5 V
37
91
110
Power Supply Rejection Ratio
Shutdown Mode ICCI
Shutdown Mode ICCO
PSRR
−50
160
−30
650
+30
μA
μA
1 VIN = 100 mV square input at 50 MHz, VOD = 50 mV, VCM = 1.25 V, VCCI = VCCO = 2.5 V, unless otherwise noted.
Rev. 0 | Page 4 of 16
ADCMP604/ADCMP605
TIMING INFORMATION
Figure 2 illustrates the ADCMP604/ADCMP605 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
LATCH ENABLE
tS
tPL
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
N
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol Timing
Description
tPDH
tPDL
tPLOH
tPLOL
tH
Input to output high
delay
Input to output low
delay
Latch enable to output
high delay
Latch enable to output
low delay
Propagation delay measured from the time the input signal crosses the reference ( the input offset
voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference ( the input offset
voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to
the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to
the 50% point of an output high-to-low transition.
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input signal must
remain unchanged to be acquired and held at the outputs.
tPL
Minimum latch enable
pulse width
Minimum time that the latch enable signal must be high to acquire an input signal change.
tS
Minimum setup time
Output rise time
Output fall time
Minimum time before the negative transition of the latch enable signal occurs that an input signal
change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the 20% and 80%
points.
Amount of time required to transition from a high to a low output as measured at the 20% and 80%
points.
tR
tF
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
Rev. 0 | Page 5 of 16
ADCMP604/ADCMP605
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltages
Input Supply Voltage (VCCI to GND)
Output Supply Voltage
(VCCO to GND)
−0.5 V to +6.0 V
−0.5 V to +6.0 V
Positive Supply Differential
−6.0 V to +6.0 V
(VCCI − VCCO
)
THERMAL RESISTANCE
Input Voltages
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Input Voltage
−0.5 V to VCCI + 0.5 V
(VCCI + 0.5 V)
50 mA
Differential Input Voltage
Maximum Input/Output Current
Shutdown Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Output Current
Table 4. Thermal Resistance
Package Type
ADCMP604 6-lead SC70
1
θJA
426
62
Unit
°C/W
°C/W
−0.5 V to VCCO + 0.5 V
50 mA
ADCMP605 12-lead LFCSP
1 Measurement in still air.
−0.5 V to VCCO + 0.5 V
50 mA
50 mA
ESD CAUTION
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +125°C
150°C
−65°C to +150°C
Rev. 0 | Page 6 of 16
ADCMP604/ADCMP605
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
Q
1
2
3
6
5
4
Q
V
9
8
7
V
EE
V
1
ADCMP604
CCO
V
/V
TOP VIEW
ADCMP605
TOP VIEW
(Not to Scale)
EE
CCI CCO
LE/HYS
V
2
3
CCI
(Not to Scale)
S
V
DN
EE
V
V
P
N
Figure 3. ADCMP604 Pin Configuration
Figure 4. ADCMP605 Pin Configuration
Table 5. ADCMP604 (SC70-6) Pin Function Descriptions
Pin No.
Mnemonic
Description
1
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater
than the analog voltage at the inverting input, VN.
2
3
4
5
6
VEE
VP
VN
VCCI/VCCO
Q
Negative Supply Voltage.
Noninverting Analog Input.
Inverting Analog Input.
Input Section Supply/Output Section Supply. VCCI and VCCO shared pin.
Q
Inverting Output. is at logic low if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN.
Table 6. ADCMP605 (LFCSP-12) Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
VCCO
VCCI
VEE
Output Section Supply.
Input Section Supply.
Negative Supply Voltage.
4
VP
Noninverting Analog Input.
5
VEE
Negative Supply Voltage.
6
VN
Inverting Analog Input.
7
8
9
SDN
LE/HYS
VEE
Shutdown. Drive this pin low to shut down the device.
Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch.
Negative Supply Voltage.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, if the comparator is in compare mode.
Negative Supply Voltage.
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN, if the comparator is in compare mode.
11
12
VEE
Q
Heat Sink
Paddle
VEE
The metallic back surface of the package is electrically connected to VEE. It can be left floating because
Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the
application board if improved thermal and/or mechanical stability is desired.
Rev. 0 | Page 7 of 16
ADCMP604/ADCMP605
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
800
1.60
1.50
600
400
OUTPUT HI
OUTPUT VCM
OUTPUT LO
1.40
1.30
1.20
V
= 2.5V
V
= 5.5V
CC
CC
200
0
–200
–400
1.10
1.00
0.90
–600
–800
–1
0
1
2
3
4
5
6
7
2.4
2.9
3.4
3.9
4.4
(V)
4.9
5.4
5.9
LE/HYS PIN (V)
V
CC
Figure 5. LE/HYS I/V Curve
Figure 8. Output Level vs. VCC
200
150
100
850
800
750
700
V
= 2.5V
V
= 5.5V
CC
CC
+125°C
50
0
650
600
550
500
+25°C
–40°C
–50
–100
–150
450
400
–1
0
1
2
3
PIN (V)
4
5
6
7
2.40 2.80 3.20 3.60 4.00 4.40 4.80 5.20 5.60 6.00
S
V
(Volts)
DN
CCO
Figure 9. Output Rise/Fall Time vs. VCCO
Figure 6. SDN I/V Curve
250
200
150
10
8
+125°C
+25°C
–40°C
6
4
2
0
–2
100
50
0
–4
–6
V
= 2.5V
CC
–8
V
= 5.5V
CC
–10
–1.0 –0.5
50
100
150
200
250
300
350
400
450
500
0.0
0.5
1.0
1.5
CC
2.0
2.5
3.0
3.5
V
AT V = 2.5V
HYSTERESIS RESISTOR (kΩ)
CM
Figure 10. Hysteresis vs. RHYS
Figure 7. Input Bias Current vs. Input Common-Mode Voltage
Rev. 0 | Page 8 of 16
ADCMP604/ADCMP605
350
300
250
200
0.44
0.43
0.42
+125°C
ADCMP605 - OUTPUT SWING V
V
CC
S
+25°C
0.41
0.40
0.39
0.38
150
100
50
–40°C
–14
0.37
0.36
0
0
–2
–4
–6
–8
–10
–12
–16 –18
2.4
3.4
4.4
(V)
5.4
HYS PIN CURRENT (µA)
V
CC
Figure 14. Output Swing vs. VCC
Figure 11. Hysteresis vs. Pin Current
3.5
3.0
2.5
1.425V
Q
2.0
1.5
1.0
PROPAGATION
DELAY
Q
925.0mV
1.000ns/DIV
0
10
20
30
40
50
60
70
80
90
100
OVER DRIVE (mV)
Figure 12 . Propagation Delay vs. Input Overdrive
Figure 15. 50 MHz Output Voltage Waveform VCCO = 2.5 V
1.6
1.5
1.4
1.3
1.543V
Q
PROPAGATION
DELAY RISE ns
PROPAGATION
DELAY FALL ns
Q
1.043V
1.000ns/DIV
–0.6 –0.2
0.2
0.6
1.0
1.4
CC
1.8
2.2
2.6
3.0
V
AT V (2.5V)
CM
Figure 13. Propagation Delay vs. Input Common Mode
Figure 16. 50 MHz Output Voltage Waveform VCCO = 5.5 V
Rev. 0 | Page 9 of 16
ADCMP604/ADCMP605
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
USING/DISABLING THE LATCH FEATURE
The ADCMP604/ADCMP605 comparators are very high speed
devices. Despite the low noise output stage, it is essential to use
proper high speed design techniques to achieve the specified
performance. Because comparators are uncompensated
amplifiers, feedback in any phase relationship is likely to cause
oscillations or undesired hysteresis. Of critical importance is the
use of low impedance supply planes, particularly the output
supply plane (VCCO) and the ground plane (GND). Individual
supply planes are recommended as part of a multilayer board.
Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
The latch input is designed for maximum versatility. It can
safely be left floating or it can be driven low by any standard
TTL/CMOS device as a high speed latch. In addition, the pin
can be operated as a hysteresis control pin with a bias voltage of
1.25 V nominal and an input resistance of approximately
7000 Ω. This allows the comparator hysteresis to be easily
controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin disables all hysteresis.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected in
parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the VCC pin. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
of the latch pin is approximately 1.1 V regardless of VCC
.
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse-
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals. Higher impedances encourage undesired
coupling.
If the package allows, and the input and output supplies have
been connected separately (VCCI ≠ VCCO), be sure to bypass each
of these supplies separately to the GND plane. Do not connect a
bypass capacitor between these supplies. It is recommended
that the GND plane separate the VCCI and VCCO planes when the
circuit board layout is designed to minimize coupling between
the two supplies to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output supplies
are used. If the input and output supplies are connected
together for single-supply operation (VCCI = VCCO), then
coupling between the two supplies is unavoidable; however,
careful board placement can help keep output return currents
away from the inputs.
COMPARATOR PROPAGATION DELAY
DISPERSION
The ADCMP604/ADCMP605 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to VCCI − 1 V. Propagation delay dispersion is the
variation in propagation delay that results from a change in the
degree of overdrive or slew rate (how far or how fast the input
signal is driven past the switching threshold).
LVDS-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance is only
achieved by keeping parasitic capacitive loads at or below the
specified minimums. The outputs of the ADCMP604 and
ADCMP605 are designed to directly drive any standard LVDS-
compatible input.
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 17
and Figure 18).
Rev. 0 | Page 10 of 16
ADCMP604/ADCMP605
The ADCMP604 and ADCMP605 dispersion is typically < 1.6 ns
as the overdrive varies from 10 mV to 125 mV. This specification
applies to both positive and negative signals because each the
ADCMP604 and ADCMP605 have substantially equal delays for
positive-going and negative-going inputs and very low output
skews.
OUTPUT
V
OH
500mV OVERDRIVE
V
OL
INPUT VOLTAGE
10mV OVERDRIVE
INPUT
0
–V
2
+V
2
H
H
V
± V
OS
N
Figure 19. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.
DISPERSION
Q/Q OUTPUT
Figure 17. Propagation Delay—Overdrive Dispersion
INPUT VOLTAGE
1V/ns
V
± V
OS
N
10V/ns
The ADCMP605 comparator offers a programmable hysteresis
feature that significantly improves accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND, varies the amount of hysteresis
in a predictable and stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes hysteresis. The
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 20 illustrates the amount of
hysteresis applied as a function of external resistor value.
Figure 11 illustrates hysteresis as a function of current.
DISPERSION
Q/Q OUTPUT
Figure 18. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with Hysteresis is shown in Figure 19. As the input
voltage approaches the threshold (0.0 V, in this example) from
below the threshold region in a positive direction, the
comparator switches from low to high when the input crosses
+VH/2. The new switching threshold becomes −VH/2. The
comparator remains in the high state until the threshold, −VH/2,
is crossed from below the threshold region in a negative direction.
In this manner, noise or feedback output signals centered on
0.0 V input cannot cause the comparator to switch states unless it
exceeds the region bounded by VH/2.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7 kΩ 20% throughout the
hysteresis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability,
reduced component count, and maximum versatility. An
external bypass capacitor is not recommended on the HYS pin
because it would likely degrade the jitter performance of the
device and impair the latch function. As described in the
Using/Disabling the Latch Feature section, hysteresis control
need not compromise the latch function.
Rev. 0 | Page 11 of 16
ADCMP604/ADCMP605
250
some predetermined point in the common-mode range, a
crossover occurs. At this point, normally VCC/2, the direction of
the bias current reverses and there are changes in measured offset
voltages and currents.
200
150
100
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PC Board
design practice, as discussed in the Optimizing Performance
section, these comparators should be stable at any input slew
rate with no hysteresis. Broadband noise from the input stage is
observed in place of the violent chattering seen with most other
high speed comparators. With additional capacitive loading or
poor bypassing, oscillation is observed. This oscillation is due to
the high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PC board. In many
applications, chattering is not harmful.
V
= 2.5V
CC
50
0
V
= 5.5V
CC
50
100
150
200
250
300
350
400
450
500
HYSTERESIS RESISTOR (kΩ)
Figure 20. Hysteresis vs. RHYS Control Resistor
CROSSOVER BIAS POINTS
Rail-to-rail inputs of this type, in both op amps and
comparators, have a dual front-end design. Certain devices are
active near the VCC rail and others are active near the VEE rail. At
Rev. 0 | Page 12 of 16
ADCMP604/ADCMP605
TYPICAL APPLICATION CIRCUITS
2.5V
2.5V TO 5V
0.1µF
10kΩ
INPUT
2kΩ
CMOS
OUTPUT
LVDS
OUTPUT
2kΩ
ADCMP604
82pF
ADCMP605
0.1µF
LE/HYS
Figure 21. Self-Biased, 50% Slicer
10kΩ
CONTROL
VOLTAGE
0V TO 2.5V
150kΩ
150kΩ
Figure 24 . Voltage-Controlled Oscillator
2.5V TO 3.3V
LVDS
100Ω
LVDS
ADCMP604
2.5V
Figure 22. LVDS to Repeater
LVDS
PWM
ADCMP604
OUTPUT
INPUT
1.25V
±50mV
2.5V TO 5V
INPUT
1.25V
REF
10kΩ
ADCMP605
10kΩ
ADCMP601
LE/HYS
DIGITAL
INPUT
74VHC
1G07
LE/HYS
10kΩ
82pF
150kΩ
100kΩ
CONTROL
VOLTAGE
0V TO 2.5V
150kΩ
Figure 25. Oscillator and Pulse-Width Modulator
Figure 23. Hysteresis Adjustment with Latch
2.5V TO 5V
ADCMP605
LE/HYS
DIGITAL
INPUT
74AHC
1G07
HYSTERESIS
CURRENT
10kΩ
Figure 26. Hysteresis Adjustment with Latch
Rev. 0 | Page 13 of 16
ADCMP604/ADCMP605
OUTLINE DIMENSIONS
0.75
0.55
0.35
2.20
2.00
1.80
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
10 11
12
4
0.45
1
9
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
INDICATOR
TOP
VIEW
2.75
BSC SQ
8
7
2
3
6
5
EXPOSED PAD
(BOTTOM VIEW)
PIN 1
1.30 BSC
0.25 MIN
0.50
BSC
0.65 BSC
0.80 MAX
0.65 TYP
12° MAX
1.00
0.90
0.70
0.40
0.10
1.00
0.85
0.80
1.10
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
0.30
0.23
0.18
0.46
0.36
0.26
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
*
COMPLIANT TOJEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package (SC70)
Figure 28. 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
(KS-6)
Dimensions shown in millimeters
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Package
Model
Range
Package Description
Option
Branding
ADCMP604BKSZ-R21
ADCMP604BKSZ-REEL71
ADCMP604BKSZ-RL1
ADCMP605BCPZ-WP1
ADCMP605BCPZ-R21
ADCMP605BCPZ-R71
EVAL-ADCMP605BCPZ1
1 Z = Pb-free part.
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
Evaluation Board
KS-6
KS-6
KS-6
G0Q
G0Q
G0Q
G0K
G0K
G0K
CP-12-1
CP-12-1
CP-12-1
Rev. 0 | Page 14 of 16
ADCMP604/ADCMP605
NOTES
Rev. 0 | Page 15 of 16
ADCMP604/ADCMP605
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05916-0-10/06(0)
Rev. 0 | Page 16 of 16
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