EVAL-ADF7024DB2Z [ADI]
Easy to Use, Low Power, Sub GHz, ISM/SRD, FSK/GFSK, Transceiver IC;
| 型号： | EVAL-ADF7024DB2Z |
| 厂家： | 
ADI |
| 描述： | Easy to Use, Low Power, Sub GHz, ISM/SRD, FSK/GFSK, Transceiver IC ISM频段 |
| 文件： | 总24页 (文件大小：603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Easy to Use, Low Power, Sub GHz,
ISM/SRD, FSK/GFSK, Transceiver IC
ADF7024
Data Sheet
Receiver performance
FEATURES
Highly linear: −11.5 dBm input IP3
Blocking: 76 dB at 10 MHz offset
Receiver sensitivity, bit error rate (BER)
−111 dBm at 9.6 kbps
−105 dBm at 100 kbps
Low power: 12.8 mA in Rx
Radio frequency (RF) bands: 431 MHz to 435 MHz and
862 MHz to 928 MHz
Data rates supported: 9.6 kbps, 38.4 kbps, 50 kbps,
100 kbps, 200 kbps, and 300 kbps
Modulation: two-level frequency (FSK) and Gaussian
frequency (GFSK) shift keying
2.2 V to 3.6 V power supply
Transmitter performance
High efficiency power amplifier (PA): 23.3 mA in Tx at 10 dBm
Output power range: −20 dBm to +13.5 dBm
Output power resolution: 0.5 dB
Low power mode performance
0.33 μA in PHY_SLEEP mode (Deep Sleep Mode 1)
0.75 μA in PHY_SLEEP mode (32 kHz RC oscillator active)
11.75 μA autonomous Rx sniff using SWM, 300 kbps
Supported regulations
Ultralow power sleep modes for long battery life
Simple serial port interface (SPI) control interface
Fast radio state transitions
Automatic frequency control (AFC) and automatic gain
control (AGC)
Digital received signal strength indication (RSSI)
Fully integrated low noise RF synthesizer and transmit
(Tx)/receive (Rx) switch
Image rejection calibration (U.S. Patent 8,238,865 and
U.S. Patent 8,358,993)
ETSI EN 300 220
FCC Part 15.231, Part 15.247, Part 15.249
Integrated packet management support
Insertion/detection of preamble/sync word/cyclic
redundancy check (CRC)
Manchester and 8-bit/10-bit data encoding and decoding
Data whitening
240-byte packet buffer for Tx/Rx data
Smart wake mode (SWM)
Autonomous carrier sense, packet sniffing, and reception
Integrated battery alarm and temperature sensor
Integrated RC oscillator
APPLICATIONS
Wireless sensor networks (WSNs)
Home and building automation
ꢀ
sset tracking
Process and building control
Industrial control
Internet of Things (IoT)
On-chip, 8-bit analog-to-digital converter (ADC)
5 mm × 5 mm, 32-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
IRQ
LNA
IRQ_GP3
RFI_P
RFI_N
CTRL
LOW IF
RECEIVER
DIGITAL
BASEBAND,
PACKET
CS
MISO
SCLK
MOSI
SPI
ADF7024
SYNTHESIZER
TRANSMITTER
HANDLER,
AND
MEMORY
RFO
PA
GPx
GPx
TEMPERATURE BATTERY
32kHz
SMART WAKE
26MHz
OSC
BIAS
SENSOR
MONITOR RC OSC CONTROLLER
2
CREGx RBIAS
XOSC26P,
XOSC26N
Figure 1.
Rev. B
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ADF7024
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 21
SPI Interface................................................................................ 21
Radio Control ............................................................................. 21
Memory Map .............................................................................. 21
Radio Blocks ............................................................................... 21
Radio Profiles.............................................................................. 22
Packet Management................................................................... 22
Smart Wake Modes .................................................................... 22
Typical Application Circuit........................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
RF and Synthesizer Specifications.............................................. 4
Transmitter Specifications........................................................... 5
Receiver Specifications ................................................................ 6
Timing and Digital Specifications.............................................. 8
Auxilary Block Specifications ..................................................... 9
General Specifications ............................................................... 10
Timing Specifications ................................................................ 11
Absolute Maximum Ratings.......................................................... 12
ESD Caution................................................................................ 12
REVISION HISTORY
7/15—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 3
Changes to Theory of Operation Section.................................... 21
Changes to Radio Profiles Section ............................................... 22
Changes to Typical Application Circuit Section......................... 23
7/14—Rev. 0 to Rev. A
Changes to Adjacent Channel Rejection Parameter.................... 6
Changes to Table 11........................................................................ 21
Updated Outline Dimensions....................................................... 24
6/14—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADF7024
GENERAL DESCRIPTION
The ADF7024 is an ultralow power, integrated transceiver for
use in the license-free ISM bands at 433 MHz, 868 MHz, and
915 MHz. Its ease of use and high performance make it suitable
for a wide variety of wireless applications. The ADF7024 is
suitable for operation under the European ETSI EN 300-220
regulation, the North American FCC Part 15 regulation, and
other similar regulatory standards.
specifications. The RF synthesizer comprises a voltage controlled
oscillator (VCO), a low noise fractional-N phase-locked loop
(PLL) and a loop filter, all of which are fully integrated and
automatically calibrated. This agile frequency synthesizer
facilitates the implementation of frequency-hopping spread
spectrum (FHSS) systems.
The smart wake mode (SWM) allows the ADF7024 to wake up
autonomously from sleep using the internal wake-up timer without
intervention from the host processor. This functionality allows
carrier sense, packet sniffing, and packet reception while the host
processor is in sleep, thereby reducing overall system current
consumption.
The ADF7024 can operate under a number of predefined radio
profiles. For each radio profile, optimized register settings are
provided for the ADF7024 radio. This ensures that the RF
communication layer works seamlessly, allowing the user to
concentrate on the protocol and system level design and
prototyping. The radio profiles cover common data rate and
modulation options. There are six radio profiles in total, as
shown in Table 1.
The ADF7024 eases the processing burden of the host processor
by integrating the lower layers of a typical communication protocol
stack. The host processor can configure the ADF7024 using a
simple command-based protocol over a standard 4-wire SPI
interface. A single-byte command transitions the radio between
states or performs a radio function.
The ADF7024 operates with a power supply range of 2.2 V to
3.6 V and has very low power consumption in both Tx and Rx
modes, enabling long lifetimes in battery-operated systems while
maintaining excellent RF performance.
A complete wireless solution can be built using a small number
of external discrete components and a host processor (typically
a microcontroller).
The low IF receiver minimizes power consumption and provides
excellent sensitivity. The receiver is exceptionally linear and,
therefore, is very resilient to the presence of interferers in spectrally
noisy environments. The highly efficient transmitter has
programmable output power up to 13.5 dBm and automatic
power amplifier (PA) ramping to meet transient spurious
For more information, see the ADF7024 Hardware Reference
Manual, UG-698, which is only available as part of the ADF7024
design resource package.
Table 1. Radio Profiles
Radio
Profile
Data Rate
(kbps)
Frequency Deviation IF Bandwidth
Typical Channel
Spacing (kHz)
Modulation (kHz)
(kHz)
100
100
100
100
200
300
RF Range (MHz)
862 to 928
431 to 435, 862 to 928
862 to 928
862 to 928
862 to 928
A
B
C
D
E
9.6
38.4
50
100
200
300
FSK/GFSK
FSK/GFSK
FSK/GFSK
FSK/GFSK
FSK/GFSK
FSK/GFSK
9.6
20
25
25
50
75
200
200
200
200
400
600
F
862 to 928
Rev. B | Page 3 of 24
ADF7024
Data Sheet
SPECIFICATIONS
VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at
VDD = 3 V, TA = 25°C.
RF AND SYNTHESIZER SPECIFICATIONS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
Frequency Ranges
862
431
928
435
MHz
MHz
All radio profiles
Radio Profile B only
PHASE-LOCKED LOOP (PLL)
Channel Frequency Resolution
Phase Noise (In-Band)
Phase Noise at Offset
1 MHz
2 MHz
10 MHz
VCO Calibration Time
Synthesizer Settling Time
396.7
−88
Hz
dBc/Hz
10 kHz offset, PA output power = 10 dBm, RF = 868 MHz
−126
−131
−142
142
dBc/Hz
dBc/Hz
dBc/Hz
μs
PA output power = 10 dBm, RF = 868 MHz
PA output power = 10 dBm, RF = 868 MHz
PA output power = 10 dBm, RF = 868 MHz
56
μs
Frequency synthesizer settles to within 5 ppm of the
target frequency within this time following the VCO
calibration in transmit and receive
CRYSTAL OSCILLATOR
Crystal Frequency
Recommended Load Capacitance
Maximum Crystal ESR
Pin Capacitance
26
MHz
pF
Ω
pF
μs
Parallel load resonant crystal
7
18
1800
2.1
310
388
26 MHz crystal with 18 pF load capacitance
Capacitance for XOSC26P and XOSC26N
26 MHz crystal with 7 pF load capacitance
26 MHz crystal with 18 pF load capacitance
Start-Up Time
μs
SPURIOUS EMISSIONS
Integer Boundary Spurious
910.1 MHz
−39
−79
dBc
dBc
Radio Profile A, integer boundary spur at 910 MHz (26 MHz ×
35), inside synthesizer loop bandwidth
Radio Profile A, integer boundary spur at 910 MHz (26 MHz ×
35), outside synthesizer loop bandwidth
911.0 MHz
Reference Spurious
868 MHz/915 MHz
Clock Related Spur Level
−80
−60
dBc
dBc
Radio Profile A
Measured in a span of 350 MHz, RF = 868.95 MHz, PA output
power = 10 dBm, VDD = 3.6 V
Rev. B | Page 4 of 24
Data Sheet
ADF7024
TRANSMITTER SPECIFICATIONS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DATA RATE
Radio Profile A
Radio Profile B
Radio Profile C
Radio Profile D
Radio Profile E
Radio Profile F
9.6
38.4
50
100
200
300
kbps
kbps
kbps
kbps
kbps
kbps
FSK/GFSK FREQUENCY DEVIATION
Radio Profile A
Radio Profile B
Radio Profile C
Radio Profile D
9.6
20
25
25
50
75
0.5
kHz
kHz
kHz
kHz
kHz
kHz
Radio Profile E
Radio Profile F
GAUSSIAN FILTER BANDWITH TIME (BT)
POWER AMPLIFIER
Maximum Power1
Minimum Power
Transmit Power
Not programmable
13.5
−20
dBm
dBm
Programmable, separate PA and LNA match2
Variation vs. Temperature
Variation vs. VDD
Flatness
0.5
1
1
dB
dB
dB
dB
−40°C to +85°C, RF = 868 MHz
2.2 V to 3.6 V, RF = 868 MHz
902 MHz to 928 MHz and 863 MHz to 870 MHz
−20 dBm to +13.5 dBm, programmable in 60 steps
868 MHz, unfiltered conductive, PA output power = 10 dBm
Programmable Step Size
HARMONICS
0.5
Second Harmonic
Third Harmonic
All Other Harmonics
OPTIMUM PA LOAD IMPEDANCE
PA Output in Transmit Mode
fRF = 915 MHz
−15.1
−29.3
−47.6
dBc
dBc
dBc
50.8 + j10.2
45.5 + j12.1
46.8 + j19.9
Ω
Ω
Ω
fRF = 868 MHz
fRF = 433 MHz
PA Output in Receive Mode
fRF = 915 MHz
fRF = 868 MHz
9.4 − j124
9.5 − j130.6
11.9 −
j260.1
Ω
Ω
Ω
fRF = 433 MHz
1 Measured as the maximum unmodulated power.
2 A combined single-ended PA and LNA match can reduce the maximum achievable output power by as much as 1 dB.
Rev. B | Page 5 of 24
ADF7024
Data Sheet
RECEIVER SPECIFICATIONS
Table 4.
Parameter
INPUT SENSITIVITY, BIT ERROR RATE (BER)1
Min
Typ
Max
Unit
Test Conditions/Comments
BER = 10−3, LNA and PA matched separately2
Radio Profile A
Radio Profile B
Radio Profile C
Radio Profile D
Radio Profile E
Radio Profile F
−111
dBm
dBm
dBm
dBm
dBm
dBm
9.6 kbps
38.4 kbps
50 kbps
100 kbps
200 kbps
300 kbps
−107.5
−107.4
−105
−103
−100.5
INPUT SENSITIVITY, PACKET ERROR RATE
(PER)3
At PER = 1%, LNA and PA matched separately,2 packet
length = 128 bits
Radio Profile A
Radio Profile B
Radio Profile C
Radio Profile D
Radio Profile E
−110.6
−106
−104.1
−102.6
−99.1
−97.9
dBm
dBm
dBm
dBm
dBm
dBm
9.6 kbps
38.4 kbps
50 kbps
100 kbps
200 kbps
300 kbps
Radio Profile F
LNA AND MIXER, INPUT IP3
Receiver local oscillator (LO) frequency (fLO) = 914.8 MHz,
fSOURCE1 = fLO + 0.4 MHz, fSOURCE2 = fLO + 0.7 MHz
LNA Gain
Minimum
Maximum
−11.5
−12.2
dBm
dBm
LNA AND MIXER, INPUT IP2
fLO = 920.8 MHz, fSOURCE1 = fLO + 1.1 MHz, fSOURCE2
fLO + 1.3 MHz
=
Gain
Maximum LNA, Maximum Mixer
Minimum LNA, Minimum Mixer
18.5
27
dBm
dBm
LNA AND MIXER, 1 dB COMPRESSION
POINT
RF = 915 MHz
Gain
Maximum LNA, Maximum Mixer
Minimum LNA, Minimum Mixer
ADJACENT CHANNEL REJECTION
CW Interferer
−21.9
−21
dBm
dBm
Wanted signal 3 dB above the input sensitivity level
(BER = 10−3), CW interferer power level increased until
BER = 10−3, image calibrated
200 kHz Channel Spacing
400 kHz Channel Spacing
600 kHz Channel Spacing
Modulated Interferer
41
40
41
dB
dB
dB
Radio Profile B, RF = 433 MHz
Radio Profile E
Radio Profile F
Wanted signal 3 dB above the input sensitivity level
(BER = 10−3), modulated interferer with the same
modulation as the wanted signal; interferer power level
increased until BER = 10−3, image calibrated
200 kHz Channel Spacing
400 kHz Channel Spacing
600 kHz Channel Spacing
CO-CHANNEL REJECTION
37
34
35
−4
dB
dB
dB
dB
Radio Profile B, RF = 433 MHz
Radio Profile E
Radio Profile F
Desired signal 10 dB above the input sensitivity level
(BER = 10−3), Radio Profile B, RF = 868 MHz
Rev. B | Page 6 of 24
Data Sheet
ADF7024
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
BLOCKING
Desired signal 3 dB above the input sensitivity level
(BER = 10−3), carrier wave interferer, power level increased
until BER = 10−3, Radio Profile B
RF = 433 MHz
2 MHz
68
76
dB
dB
10 MHz
RF = 868 MHz
2 MHz
66
74
dB
dB
10 MHz
RF = 915 MHz
2 MHz
66
74
dB
dB
10 MHz
BLOCKING, ETSI EN 300 220
Measurement procedure as per ETSI EN 300-220-1 V2.3.1;
desired signal 3 dB above the ETSI EN 300-220 reference
sensitivity level of −99 dBm, Radio Profile B, unmodulated
interferer
2 MHz
10 MHz
−28
−20.5
75
dBm
dBm
dB
WIDEBAND INTERFERENCE REJECTION
RF = 868 MHz, swept from 10 MHz to 100 MHz either
side of the RF
IMAGE CHANNEL ATTENUATION
Measured as image attenuation at the IF filter output,
carrier wave interferer at 400 kHz below the channel
frequency, 100 kHz IF filter bandwidth
868 MHz, 915 MHz
433 MHz
36/45
40/54
dB
dB
Uncalibrated/calibrated
Uncalibrated/calibrated
AFC
Accuracy
1
kHz
RSSI
Range at Input
Linearity
Absolute Accuracy
MAXIMUM RF INPUT LEVEL
LNA INPUT IMPEDANCE, DIFFERENTIAL
Receive Mode
−97 to −26
2
3
dBm
dB
dB
12
dBm
fRF = 915 MHz
fRF = 868 MHz
fRF = 433 MHz
75.9 − j32.3
78.0 − j32.4
95.5 − j23.9
Ω
Ω
Ω
Transmit Mode
fRF = 915 MHz
fRF = 868 MHz
7.6 + j9.2
7.7 + j8.6
7.9 + j4.6
Ω
Ω
Ω
fRF = 433 MHz
RX SPURIOUS EMISSIONS4
Maximum < 1 GHz
Maximum > 1 GHz
−66
−62
dBm
dBm
At antenna input, unfiltered conductive
At antenna input, unfiltered conductive
1 Sensitivity measured with FSK modulation.
2 Sensitivity for combined Tx/Rx matching network case is typically 1 dB less than separate Tx/Rx matching networks.
3 Sensitivity measured with FSK modulation and AFC disabled.
4 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Rev. B | Page 7 of 24
ADF7024
Data Sheet
TIMING AND DIGITAL SPECIFICATIONS
Table 5.
Parameter
Symbol Min
Typ Max
Unit Test Conditions/Comments
Rx AND Tx TIMING PARAMETERS
PHY_ON to PHY_RX (on
CMD_PHY_RX)
PHY_ON to PHY_TX (on
CMD_PHY_TX)
300
296
μs
μs
Includes VCO calibration and synthesizer settling
Includes VCO calibration and synthesizer settling, does
not include PA ramp-up
LOGIC INPUTS
Input Voltage
High
VINH
0.7 × VDD
V
Low
VINL
0.2 × VDD
V
Input Current
IINH/IINL
CIN
±±
±0
µA
pF
Input Capacitance
LOGIC OUTPUTS
Output Voltage
High
Low
GPx Rise/Fall
GPx Load
Maximum Output Current
ATB OUTPUTS
VOH
VOL
VDD − 0.4
V
V
ns
pF
mA
IOH = 500 µA
IOL = 500 µA
0.4
5
±0
5
Used for external PA and LNA control
ADCIN_ATB3 and ATB4
Output High Voltage, VOH
Output Low Voltage, VOL
Maximum Output Current
GP5_ATB± and ATB2
Output High Voltage, VOH
Output Low Voltage, VOL
Maximum Output Current
±.8
0.±
0.5
V
V
mA
VDD
0.±
5
V
V
mA
Rev. B | Page 8 of 24
Data Sheet
ADF7024
AUXILARY BLOCK SPECIFICATIONS
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
32 kHz RC OSCILLATOR
Frequency
Frequency Accuracy
Frequency Drift
32.768
±.5
kHz
%
After calibration
After calibration at 25°C
Temperature Coefficient
Voltage Coefficient
Calibration Time
0.±4
4
±.25
%/°C
%/V
ms
WAKE-UP CONTROLLER (WUC)
Hardware Timer
Wake-Up Period
Firmware Timer
6± × ±0−6
±
±.3± × ±05
2±6
sec
Wake-Up Period
Hardware Firmware counter counts of the number of
periods
hardware wake-up cycles, resolution of ±6 bits
ADC
Resolution
DNL
INL
Conversion Time
Input Capacitance
BATTERY MONITOR
Absolute Accuracy
Alarm Voltage Set Point
Alarm Voltage Step Size
Start-Up Time
8
Bits
LSB
LSB
µs
±±
±±
±
VDD from 2.2 V to 3.6 V, TA = 25°C
VDD from 2.2 V to 3.6 V, TA = 25°C
±2.4
pF
±45
62
mV
V
mV
µs
±.7
2.7
5-bit resolution
When enabled
±00
Current Consumption
TEMPERATURE SENSOR
Range
Resolution
Accuracy of Temperature Readback
30
µA
−40
+85
°C
°C
°C
0.3
−4 to +7
With averaging
Temperature range = −40°C to +85°C
(calibrated at 25°C)
±4
±3
°C
°C
Temperature range = −36°C to +84°C
(calibrated at 25°C)
Temperature range = −±2°C to +79°C
(calibrated at 25°C)
Rev. B | Page 9 of 24
ADF7024
Data Sheet
GENERAL SPECIFICATIONS
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TEMPERATURE RANGE, TA
VOLTAGE SUPPLY
VDD
−40
+85
°C
2.2
3.6
V
Applied to VDDBAT± and VDDBAT2
TRANSMIT CURRENT CONSUMPTION
In the PHY_TX state, PA matched to 50 Ω, separate PA and
LNA match
433 MHz
−±0 dBm
0 dBm
±0 dBm
8.7
mA
mA
mA
mA
±2.2
23.3
32.±
±3.5 dBm
868 MHz/9±5 MHz
−±0 dBm
0 dBm
±0 dBm
±3.5 dBm
±0.3
±3.3
24.±
32.±
mA
mA
mA
mA
POWER MODES
PHY_SLEEP (Deep Sleep Mode 2)
PHY_SLEEP (Deep Sleep Mode ±)
PHY_SLEEP (RC Oscillator Active)
PHY_OFF
0.±8
0.33
0.75
±
µA
µA
µA
mA
Sleep mode, memory not retained
Sleep mode, memory retained
WUC active, RC oscillator running, memory retained
Device in PHY_OFF state, 26 MHz oscillator running, digital
and synthesizer regulators active, all register values retained
PHY_ON
±
mA
mA
Device in PHY_ON state, 26 MHz oscillator running, digital,
synthesizer, VCO, and RF regulators active, baseband filter
calibration performed, all register values retained
PHY_RX
±2.8
Device in PHY_RX state
SMART WAKE MODE
Average current consumption
2±.78
±±.75
µA
µA
Autonomous reception every ± sec, with receive dwell
time of ±.25 ms, using RC oscillator, Radio Profile B
Autonomous reception every ± sec, with receive dwell
time of 0.5 ms, using RC oscillator, Radio Profile F
Rev. B | Page ±0 of 24
Data Sheet
ADF7024
TIMING SPECIFICATIONS
VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VGND = GND = 0 V, T A = TMIN to TMAX, unless otherwise noted.
Table 8. SPI Interface Timing
Parameter
Limit
Unit
Test Conditions/Comments
CS low to SCLK setup time
SCLK high time
SCLK low time
SCLK period
SCLK falling edge to MISO delay
MOSI to SCLK rising edge setup time
MOSI to SCLK rising edge hold time
SCLK falling edge to CS hold time
CS high time
t2
85
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
µs typ
ns max
ns max
µs max
t3
t4
t5
t6
t7
t8
t9
85
85
±70
±0
5
5
85
t±±
t±2
t±3
t±4
t±5
270
3±0
20
20
25
CS low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, TA = 25°C
SCLK rise time
SCLK fall time
Initialization time; do not issue a command during this time; alternatively, poll the status
word and wait for the CMD_READY bit to go high
Timing Diagrams
CS
t11
t2
t3 t4
t5
t13
t14
t9
SCLK
MISO
t6
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 0
X
BIT 7
t8
t7
MOSI
7
6
5
4
3
2
1
0
7
7
Figure 2. SPI Interface Timing
CS
t9
t15
7
6
5
4
3
2
1
0
SCLK
t12
t6
MISO
X
SPI STATE
SLEEP
WAKE UP
SPI READY
CS
)
Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready t12 After the Falling Edge of
Rev. B | Page ±± of 24
ADF7024
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Connect the exposed pad of the LFCSP to ground.
This device is a high performance, RF integrated circuit with an
ESD rating of <2 kV; it is ESD sensitive. Take proper precautions
for handling and assembly.
Table 9.
Parameter
Rating
VDDBAT±, VDDBAT2 to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Maximum Junction Temperature
LFCSP θJA Thermal Impedance
Reflow Soldering
−0.3 V to +3.96 V
ESD CAUTION
−40°C to +85°C
−65°C to +±25°C
±50°C
26°C/W
Peak Temperature
Time at Peak Temperature
260°C
40 sec
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page ±2 of 24
Data Sheet
ADF7024
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CREGRF1
RBIAS
CREGRF2
RFI_P
RFI_N
RFO
VDDBAT2
NC
1
2
3
4
5
6
7
8
24 CS
23
22 SCLK
21 MISO
MOSI
ADF7024
TOP VIEW
(Not to Scale)
20
19
IRQ_GP3
GP2
EPAD
18 GP1
17 GP0
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. CONNECT THE EXPOSED PAD TO GND.
Figure 4. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
±
CREGRF±
Regulator Voltage for RF. For regulator stability and noise rejection, place a 220 nF capacitor between this
pin and ground.
2
3
RBIAS
CREGRF2
External Bias Resistor. Place a 36 kΩ resistor with 2% tolerance between this pin and ground.
Regulator Voltage for RF. For regulator stability and noise rejection, place a 220 nF capacitor between this
pin and ground.
4
5
6
7
8
9
RFI_P
RFI_N
RFO
VDDBAT2
NC
CREGVCO
LNA Positive Input in Receive Mode.
LNA Negative Input in Receive Mode.
PA Output.
Power Supply Pin 2. Place decoupling capacitors to the ground plane as close as possible to this pin.
No Connect. Do not connect to this pin.
Regulator Voltage for the VCO. For regulator stability and noise rejection, place a 220 nF capacitor between
this pin and ground.
±0
±±
VCOGUARD
CREGSYNTH
Guard/Screen for VCO. Connect this pin to Pin 9.
Regulator Voltage for the Synthesizer. For regulator stability and noise rejection, place a 220 nF capacitor
between this pin and ground.
±2
±3
CWAKEUP
XOSC26P
External Capacitor for Wake-Up Control. Place a ±50 nF capacitor between this pin and ground.
Crystal Oscillator, Positive. Connect the 26 MHz reference crystal between this pin and XOSC26N. If an
external reference is connected to XOSC26N, leave this pin open circuited.
±4
XOSC26N
Crystal Oscillator, Negative. Connect the 26 MHz reference crystal between this pin and XOSC26P.
Alternatively, an external 26 MHz reference signal can be ac-coupled to this pin.
±5
±6
DGUARD
CREGDIG±
Internal Guard/Screen for the Digital Circuitry. Connect this pin to Pin ±6, CREGDIG±.
Regulator Voltage for Digital Section of the Chip. For regulator stability and noise rejection, place a 220 nF
capacitor between this pin and ground.
±7
±8
±9
20
2±
22
23
24
GP0
GP±
GP2
IRQ_GP3
MISO
SCLK
MOSI
CS
Digital GPIO Pin 0.
Digital GPIO Pin ±.
Digital GPIO Pin 2.
Interrupt Request/Digital GPIO Test Pin 3.
Serial Port Master Input/Slave Output.
Serial Port Clock.
Serial Port Master Output/Slave Input.
Chip Select (Active Low). A pull-up resistor of ±00 kΩ to VDD is recommended to prevent the host processor
from inadvertently waking the ADF7024 from sleep.
25
GP4
Digital GPIO Test Pin 4.
Rev. B | Page ±3 of 24
ADF7024
Data Sheet
Pin No. Mnemonic
Description
26
CREGDIG2
Regulator Voltage for Digital Section of the Chip. For regulator stability and noise rejection, place a 220 nF
capacitor between this pin and ground.
27
28
29
30
3±
32
GP5_ATB±
ATB2
VDDBAT±
ADCIN_ATB3
ATB4
Digital GPIO Test Pin 5/Analog Test Pin ±.
Analog Test Pin 2.
Digital Power Supply Pin One. Place decoupling capacitors to the ground plane as close as possible to this pin.
Analog-to-Digital Converter Input/Analog Test Pin 3.
Analog Test Pin 4.
ADC Reference Output. Place a 220 nF capacitor between this pin and ground for adequate noise rejection.
Exposed Package Pad. Connect the exposed pad to GND.
ADCVREF
EPAD
Rev. B | Page ±4 of 24
Data Sheet
ADF7024
TYPICAL PERFORMANCE CHARACTERISTICS
16
40
35
30
25
20
15
10
5
–40°C, 3.6V
–40°C, 3.0V
–40°C, 3.6V
–40°C, 1.8V
+25°C, 3.6V
+25°C, 1.8V
+85°C, 3.6V
+85°C, 1.8V
12
8
–40°C, 2.4V
+25°C, 3.6V
+25°C, 3.0V
+25°C, 2.4V
+85°C, 3.6V
+85°C, 3.0V
+85°C, 2.4V
4
0
–4
–8
–12
–16
–20
0
–20
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
PA_LEVEL
–16
–12
–8
–4
0
4
8
12
16
PA OUTPUT POWER (dBm)
Figure 5. Output Power vs. PA_LEVEL Setting, Temperature,
and VDD at 433 MHz
Figure 8. Supply Current vs. PA Output Power, Temperature, and VDD at 433 MHz
(Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness)
16
35
–40°C, 3.6V
–40°C, 3.6V
–40°C, 3.0V
–40°C, 2.4V
+25°C, 3.6V
+25°C, 3.0V
+25°C, 2.4V
+85°C, 3.6V
+85°C, 3.0V
+85°C, 2.4V
–40°C, 1.8V
+25°C, 3.6V
12
8
30
+25°C, 1.8V
+85°C, 3.6V
+85°C, 1.8V
25
4
20
15
10
5
0
–4
–8
–12
–16
–20
0
–20
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
PA_LEVEL
–16
–12
–8
–4
0
4
8
12
16
OUTPUT POWER (dBm)
Figure 6. Output Power vs. PA_LEVEL Setting, Temperature, and VDD at
868 MHz
Figure 9. Supply Current vs. Output Power, Temperature, and VDD at 868 MHz
(Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness)
16
40
–40°C, 3.6V
–40°C, 3.6V
–40°C, 3.0V
–40°C, 1.8V
12
+25°C, 3.6V
+25°C, 1.8V
+85°C, 3.6V
+85°C, 1.8V
–40°C, 2.4V
35
30
25
20
15
10
5
+25°C, 3.6V
+25°C, 3.0V
8
+25°C, 2.4V
+85°C, 3.6V
4
0
+85°C, 3.0V
+85°C, 2.4V
–4
–8
–12
–16
–20
0
–20
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
PA_LEVEL
–16
–12
–8
–4
0
4
8
12
16
OUTPUT POWER (dBm)
Figure 10. Supply Current vs. Output Power, Temperature, and VDD at
915 MHz (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for
Robustness)
Figure 7. Output Power vs. PA_LEVEL Setting, Temperature,
and VDD at 915 MHz
Rev. B | Page ±5 of 24
ADF7024
Data Sheet
10
5
0
3.6V, –40°C
1.8V, –40°C
3.6V, +85°C
1.8V, +85°C
0
–5
–10
–20
–30
–40
–50
–60
OUTPUT POWER (FUNDAMENTAL)
OUTPUT POWER IDEAL
P1dB
–10
–15
–20
–25
–30
–35
–40
P1dB = –21dBm
–250 –200 –150 –100 –50
0
50
100 150 200 250
–40
–35
–30
–25
–20
–15
FREQUENCY OFFSET (kHz)
LNA INPUT POWER (dBm)
Figure 14. LNA/Mixer 1 dB Compression Point, VDD = 3.0 V, Temperature =
25°C, RF = 915 MHz, LNA Gain = Low, Mixer Gain = Low
Figure 11. Transmit Spectrum at 868 MHz, FSK, Radio Profile B, (Minimum
Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness)
20
10
3.6V, –40°C
1.8V, –40°C
3.6V, +85°C
OUTPUT POWER (FUNDAMENTAL)
OUTPUT POWER IDEAL
P1dB
0
15
1.8V, +85°C
–10
10
–20
–30
–40
–50
–60
5
0
–5
P1dB = –21.9dBm
–25
–10
–40
–35
–30
–20
–15
–250 –200 –150 –100 –50
0
50
100 150 200 250
LNA INPUT POWER (dBm)
FREQUENCY OFFSET (kHz)
Figure 12. Transmit Spectrum at 868 MHz, GFSK, Radio Profile B, (Minimum
Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness)
Figure 15. LNA/Mixer 1 dB Compression Point, VDD = 3.0 V, Temperature =
25°C, RF = 915 MHz, LNA Gain = High, Mixer Gain = High
15
10
5
10
0
–10
–20
–30
–40
–50
–60
3.6V, +25°C
0
1.8V, +25°C
3.6V, +85°C
–5
1.8V, +85°C
3.6V, –40°C
1.8V, –40°C
–10
–15
–20
–25
–30
–35
–40
–45
IIP3 = –11.5dBm
–70
–80
–90
–100
–110
–120
–130
FUNDAMENTAL TONE
IM3 TONE
FUNDAMENTAL 1/1 SLOPE FIT
IM3 3/1 SLOPE FIT
–50
–45
–40
–35
–30
–25
–20
–15
–10
LNA INPUT POWER (dBm)
FREQUENCY OFFSET (kHz)
Figure 16. LNA/Mixer IIP3, VDD = 3.0 V, Temperature = 25°C, RF = 915 MHz,
LNA Gain = Low, Mixer Gain = Low, Source 1 Frequency =
Figure 13. Transmit Spectrum at 928 MHz, GFSK, Radio Profile F, (Minimum
Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness)
915 MHz + 0.4 MHz, Source 2 Frequency = 915 MHz + 0.7 MHz
Rev. B | Page 16 of 24
Data Sheet
ADF7024
80
70
60
50
40
30
20
10
0
20
10
0
MODULATED
INTERFERER
CARRIER WAVE
INTERFERER
–10
–20
–30
–40
–50
–60
–70
–80
–90
IIP3 = –12.2dBm
FUNDAMENTAL TONE
IM3 TONE
FUNDAMENTAL 1/1 SLOPE FIT
IM3 3/1 SLOPE FIT
–10
–50
–45
–40
–35
–30
–25
–20
–15
–10
LNA INPUT POWER (dBm)
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
Figure 17. LNA/Mixer IIP3, VDD = 3.0 V, Temperature = 25°C, RF = 915 MHz,
LNA Gain = High, Mixer Gain = High, Source 1 Frequency =
Figure 20. Receiver Wideband Blocking at 433 MHz, Radio Profile B
915 MHz + 0.4 MHz, Source 2 Frequency = 915 MHz + 0.7 MHz
10
80
70
60
100kHz
200kHz
300kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
50
MODULATED
INTERFERER
40
CARRIER WAVE
INTERFERER
30
20
10
0
–10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY OFFSET (MHz)
BLOCKER FREQUENCY OFFSET (MHz)
Figure 18. IF Filter Profile vs. IF Bandwidth, VDD = 3.0 V, Temperature = 25°C
Figure 21. Receiver Wideband Blocking at 868 MHz, Radio Profile D
10
70
60
50
1.8V, –40°C
2.4V, –40°C
3.0V, –40°C
3.6V, –40°C
1.8V, +25°C
2.4V, +25°C
3.0V, +25°C
3.6V, +25°C
1.8V, +85°C
2.4V, +85°C
3.0V, +85°C
3.6V, +85°C
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
40
MODULATED
INTERFERER
30
CARRIER WAVE
INTERFERER
20
10
0
–10
–20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY OFFSET (MHz)
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
Figure 19. IF Filter Profile vs. VDD and Temperature, 100 kHz IF Filter Bandwidth
(Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness)
Figure 22. Receiver Wideband Blocking at 868 MHz, Radio Profile F
Rev. B | Page 17 of 24
ADF7024
Data Sheet
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
MODULATED
INTERFERER
CARRIER WAVE
INTERFERER
–10
–20
–60 –50 –40 –30 –20 –10
0
10 20 30 40 50 60
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
BLOCKER FREQUENCY OFFSET (MHz)
Figure 26. Receiver Wideband Blocking at 868 MHz, Radio Profile B,
Measured as per ETSI EN 300 220
Figure 23. Receiver Wideband Blocking at 915 MHz, Radio Profile D
60
55
50
45
40
35
30
25
20
15
10
5
70
60
50
40
MODULATED
INTERFERER
30
CARRIER WAVE
INTERFERER
20
10
0
0
–5
–10
–10
–20
CW INTERFERER
MODULATED INTERFERER
–15
–20
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
Figure 24. Receiver Wideband Blocking at 915 MHz, Radio Profile F
Figure 27. Receiver Close-In Blocking at 915 MHz, Radio Profile D,
Image Calibrated
60
55
50
45
40
35
30
25
20
15
10
5
70
60
50
40
30
20
+25°C 1.8V
+25°C 3.0V
+25°C 3.6V
+85°C 1.8V
+85°C 3.0V
+85°C 3.6V
–40°C 1.8V
–40°C 3.0V
–40°C 3.6V
10
0
0
–5
–10
–10
–20
CW INTERFERER
–15
MODULATED INTERFERER
–20
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
–60 –50 –40 –30 –20 –10
0
10 20 30 40 50 60
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
INTERFERER FREQUENCY OFFSET (MHz)
Figure 28. Receiver Close-In Blocking at 915 MHz, Radio Profile E, Image
Calibrated
Figure 25. Receiver Wideband Blocking vs. VDD and Temperature,
915 MHz, Radio Profile F
Rev. B | Page ±8 of 24
Data Sheet
ADF7024
60
55
50
45
40
35
30
25
20
15
10
5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100kHz BW
200kHz BW
300kHz BW
0
–5
–10
CW INTERFERER
MODULATED INTERFERER
–15
–20
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
OFFSET FROM LO FREQUENCY (MHz)
Figure 32. IF Filter Profile with Calibrated Image vs. IF Filter Bandwidth,
921 MHz, VDD = 3.0 V, Temperature = 25°C
Figure 29. Receiver Close-In Blocking at 915 MHz, Radio Profile F, Image
Calibrated
–98
0
915MHz, –40°C
915MHz, +25°C
915MHz, +85°C
868MHz, –40°C
868MHz, +25°C
868MHz, +85°C
CALIBRATED
UNCALIBRATED
–10
–99
–100
–101
–102
–103
–104
–20
–30
–40
–50
–60
–70
–80
–90
1.8
3.0
(V)
3.6
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
V
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
DD
Figure 30. Image Attenuation with Calibrated and Uncalibrated Images,
915 MHz, IF Filter Bandwidth = 100 kHz, VDD = 3.0 V, Temperature = 25°C
Figure 33. Receiver Sensitivity (Bit Error Rate at 10−3) vs. VDD, Temperature,
and RF Frequency, Radio Profile F, FSK, (Minimum Recommended VDD
2.2 V, 1.8 V Operation Shown for Robustness)
=
0
100
9.6kbps
CALIBRATED
UNCALIBRATED
38.4kbps
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
90
50kbps
100kbps
80
70
60
50
40
30
20
10
0
200kbps
300kbps
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)
APPLIED RECEIVER POWER (dBm)
Figure 31. Image Attenuation with Calibrated and Uncalibrated Images,
433 MHz, IF Filter Bandwidth = 100 kHz, VDD = 3.0 V, Temperature = 25°C
Figure 34. Packet Error Rate vs. RF Input Power and Radio Profile (Data Rate), FSK,
928 MHz, Preamble Length = 64 Bits, VDD = 3.0 V, Temperature = 25°C
Rev. B | Page ±9 of 24
ADF7024
Data Sheet
–96.0
–96.5
–97.0
–97.5
–98.0
–98.5
–99.0
–99.5
–100.0
6
4
300kbps
200kbps
100kbps
50kbps
38.4kbps
9.6kbps
+25°C
2
+85°C
–40°C
0
–2
–4
–6
1.8
3.6
–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20
INPUT POWER (dBm)
V
(V)
DD
Figure 35. Receiver Sensitivity (Packet Error Rate at 1%) vs. VDD
Temperature, and RF, Radio Profile F, FSK, (Minimum Recommended
,
Figure 37. Mean RSSI Error (via Automatic End of Packet RSSI Measurement)
vs. RF Input Power and Data Rate, RF = 868 MHz, GFSK, 100 RSSI
Measurements at Each Input Power Level
V
DD = 2.2 V, 1.8 V Operation Shown for Robustness)
–20
–30
10
8
80
70
60
50
MEAN ACCURACY
–40
6
–50
4
40
–60
2
30
–70
0
20
10
–80
–2
–4
–6
–8
–10
ERROR
0
–90
–10
–20
–30
–40
IDEAL RSSI
MEAN RSSI
MEAN RSSI ERROR
MAX POSITIVE RSSI ERROR
MAX NEGATIVE RSSI ERROR
–100
–110
–120
–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
INPUT POWER (dBm)
APPLIED TEMPERATURE (°C)
Figure 36. RSSI (via CMD_GET_RSSI) vs. RF Input Power, 868 MHz, GFSK,
Radio Profile B, IF Bandwidth = 100 kHz, 100 RSSI Measurements at Each
Power Level
Figure 38. Typical Accuracy Range of Temperature Sensor vs. Applied
Temperature, Calibration Performed at 25°C
Rev. B | Page 20 of 24
Data Sheet
ADF7024
THEORY OF OPERATION
For detailed information on the operation of the ADF7024, see
the ADF7024 Hardware Reference Manual, UG-698, which is
only available as part of the ADF7024 design resource package.
MEMORY MAP
The ADF7024 memory map is shown in Figure 40. Each memory
space consists of 8-bit registers with an address length of 11 bits.
SPI INTERFACE
The ADF7024 is equipped with a 4-wire SPI interface, using the
0x3FF
CS
SCLK, MISO, MOSI, and
pins. The ADF7024 always acts as
AUXILIARY REGISTERS
256 BYTES
a slave to the host processor. The SPI interface allows the host
processor to perform the following operations on the ADF7024:
0x300
NOT USED
0x13F
Read and write to the ADF7024 memory spaces.
Issue commands to the ADF7024.
Read back the status of the ADF7024.
CONFIGURATION REGISTERS
64 BYTES
0x100
0x0FF
Wake the ADF7024 from the PHY_SLEEP state.
Figure 39 shows a typical connection diagram between the
processor and the ADF7024. The diagram also shows the
direction of the signal flow for each pin.
PACKET RAM
240 BYTES
0x010
NOT RETAINED IN PHY_SLEEP
RETAINED IN PHY_SLEEP
0x00F
AUXILIARY RAM
16 BYTES
0x000
GPIO
SCLK
MOSI
MISO
IRQ
CS
SCLK
MOSI
MISO
Figure 40. Memory Map
HOST
PROCESSOR
ADF7024
Configuration Registers
IRQ_GP3
The configuration registers consist of 64 bytes of memory space
used to configure the operation of the ADF7024. The radio profile
registers form part of this memory space. The configuration
registers are retained in the PHY_SLEEP radio state.
Figure 39. Host Processor Interface
The status word of the ADF7024 is returned over the MISO
automatically each time a byte is transferred over the MOSI.
The status word contains the current ADF7024 state, the interrupt
status and flags to indicate that the ADF7024 is ready to accept a
new SPI memory access command or a radio control command.
Auxiliary Registers
The auxiliary registers consist of 256 bytes of memory space
used for auxiliary radio functions or observation of the radio
blocks of the ADF7024.
RADIO CONTROL
Packet RAM
The ADF7024 has five radio states designated as PHY_SLEEP,
PHY_OFF, PHY_ON, PHY_RX, and PHY_TX, as described in
Table 11. The host processor can transition the ADF7024 between
states by issuing single-byte, radio control commands over the
SPI interface.
The packet RAM memory consists of 240 bytes of memory for
storage of data from valid received packets and packet data to
be transmitted.
Auxiliary RAM
Table 11. Radio States
The auxiliary RAM memory is reserved for use by the ADF7024.
Current
RADIO BLOCKS
State
(Typical) Conditions
Frequency Synthesizer
PHY_SLEEP
(Deep Sleep
Mode 2)
PHY_SLEEP
(Deep Sleep
Mode 1)
PHY_SLEEP
(WUC
enabled)
PHY_OFF
PHY_ON
PHY_TX
PHY_RX
0.18 μA
0.33 μA
0.75 μA
Wake-up timer off, configuration
registers not retained, entered by
issuing CMD_HW_RESET
Wake-up timer off, configuration
registers retained
A fully integrated RF synthesizer is used to generate both the
transmit signal and the local oscillator (LO) signal of the
receiver. A high speed, fully automatic calibration scheme
ensures that the frequency and amplitude characteristics of the
VCO are maintained over temperature, supply voltage, and process
variations. The receive and transmit synthesizer bandwidths are
automatically and independently configured to achieve optimum
phase noise and settling time.
Wake-up timer on using the 32 kHz
RC oscillator, configuration
registers retained
1.0 mA
1.0 mA
24.1 mA
12.8 mA
10 dBm, 868 MHz
Rev. B | Page 21 of 24
ADF7024
Data Sheet
Crystal Oscillator
PACKET MANAGEMENT
A 26 MHz crystal oscillator operating in parallel mode must be
connected between the XOSC26P and XOSC26N pins to provide
a reference for the ADF7024. Two parallel loading capacitors
are required for oscillation at the correct frequency. Their values
are dependent upon the crystal specification.
The ADF7024 includes comprehensive transmit and receive
packet management capabilities and can be configured for use
with a wide variety of packet-based radio protocols. There are
240 bytes of dedicated packet RAM available to store, transmit,
and receive packets. In transmit mode, a preamble, sync word,
and CRC can be added by the ADF7024 to the payload data
stored in the packet RAM. In addition, all packet data after the
sync word can be optionally whitened, Manchester encoded, or 8-
bit/10-bit encoded on transmission and decoded on reception.
Transmitter
The ADF7024 supports binary frequency shift keying (FSK) and
binary level Gaussian filtered FSK (GFSK) modulation. For GFSK
modulation, the Gaussian filter uses a fixed BT of 0.5.
In receive mode, the ADF7024 can qualify received packets
based on preamble detection, sync word detection, or CRC
validation and generate an interrupt on the IRQ_GP3 pin. On
reception of a valid packet, the received payload data is loaded to
packet RAM memory.
The ADF7024 PA has a single-ended output that can deliver up
to 13.5 dBm of output power. The output power can be set with
a typical resolution of 0.5 dB. The PA has built-in up and down
ramping, which reduces spectral splatter.
Receiver
SMART WAKE MODES
The ADF7024 is based on a fully integrated, low IF receiver
architecture. The differential LNA is followed by a quadrature
downconversion mixer that converts the RF signal to the IF
frequency of 200 kHz (for IF filter bandwidths of 100 kHz and
200 kHz) or 300 kHz (for IF filter bandwidths of 300 kHz). The
IF filter bandwidth is configured to 100 kHz, 200 kHz, or 300 kHz,
depending on the radio profile selected. The bandwidth and center
frequency of the IF filter are calibrated automatically.
The ADF7024 can be configured to operate in a broad range of
energy sensitive applications where battery lifetime is critical.
This includes support for applications where the ADF7024 is
required to operate in a fully autonomous mode or applications
where the host processor controls the transceiver during low power
mode operation. These low power modes are implemented using a
hardware WUC, a firmware timer, and the SWM functionality.
The combination of the low power WUC, the firmware timer,
and the SWM allows the ADF7024 to wake up autonomously
from sleep without intervention from the host processor. This
functionality allows carrier sense, packet sniffing, and packet
reception while the host processor is in sleep, thereby dramatically
reducing overall system current consumption. The SWM can
then wake the host processor on an interrupt condition.
The IF filter gives excellent interference suppression of adjacent
and neighboring channels while also suppressing the image
channel. The ADF7024 is capable of providing improved
receiver image rejection performance by the use of a fully
integrated image rejection calibration system.
A correlator demodulator is used for demodulation. An
oversampled digital clock and data recovery (CDR) PLL is used
to resynchronize the received bit stream to a local clock.
RADIO PROFILES
The ADF7024 radio profiles provide a set of optimized register
settings for the ADF7024 radio. There are six radio profiles in
total, as shown in Table 1. The profiles cover common data rates
and modulation options. For further information on the ADF7024
radio profiles, see the ADF7024 Hardware Reference Manual,
UG-698, which is only available as part of the ADF7024 design
resource package.
Rev. B | Page 22 of 24
Data Sheet
ADF7024
TYPICAL APPLICATION CIRCUIT
Figure 41 shows a typical application circuit for the ADF7024. All
external components required for operation of the device,
excluding supply decoupling capacitors, are shown. This example
circuit uses a combined transmit and receive match. The bottom
of the LFCSP has an exposed pad that must be soldered to
ground on the PCB. The component values for the matching
and harmonic filtering are dependent on the RF band and the
matching topology. For more information, see the ADF7024
Hardware Reference Manual, UG-698, which is only available as
part of the ADF7024 design resource package.
V
DD
220nF
220nF
V
DD
220nF
220nF
100kΩ
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CS
CREGRF1
RBIAS
CREGRF2
RFI_P
GPIO
36kΩ
COMBINED
TX/RX
MOSI
SCLK
MISO
MOSI
SCLK
MISO
MATCH
IRQ_GP3
GP2
IRQ
RFI_N
ADF7024
HARMONIC FILTER
RFO
GND PAD
ANTENNA
CONNECTION
GP1
VDD
VDDBAT2
NC
GP0
220nF
220nF
220nF
150nF
26MHz CRYSTAL
Figure 41. Typical ADF7024 Application Circuit Diagram
Rev. B | Page 23 of 24
ADF7024
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
3.45
3.30 SQ
3.15
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option
CP-32-±3
CP-32-±3
ADF7024BCPZ
−40°C to +85°C
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
ADF7024BCPZ-RL
EVAL-ADF7XXXMB4Z
EVAL-ADF7024DB±Z
EVAL-ADF7024DB2Z
EVAL-ADF7024DB3Z
EVAL-ADF7024DB4Z
Evaluation Board (Motherboard)
Evaluation Board (RF Daughter Board, 862 MHz to 928 MHz, Separate Match)
Evaluation Board (RF Daughter Board, 862 MHz to 928 MHz, Combined Match)
Evaluation Board (RF Daughter Board, 43± MHz to 435 MHz, Separate Match)
Evaluation Board (RF Daughter Board, 43± MHz to 435 MHz, Combined Match)
± Z =RoHS Compliant Part.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12027-0-7/15(B)
Rev. B | Page 24 of 24
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