EVAL-ADM1075EBZ_技术文档

−48 V Hot Swap Controller and Digital

Power Monitor with PMBus Interface

Data Sheet

ADM1075

FEATURES

PRODUCT HIGHLIGHTS

Constant power foldback for FET SOA protection

Precision (<1.0%) current and voltage measurement

Controls inrush and faults for negative supply voltages

Suitable for wide input range due to internal shunt regulator

25 mV/50 mV full-scale sense voltage

Fine tune current limit to allow use of standard sense resistor

Soft start inrush current limit profiling

1% accurate UVH and OV pins, 1.5% accurate UVL pin

PMBus/I²C interface for control, telemetry, and fault

recording

1. Constant Power Foldback.

Maximum FET power set by a PLIM resistor divider. This

eases complexity when designing to maintain FET SOA.

2. Adjustable Current Limit.

The current limit is adjustable via the ISET pin allowing for

the use of a standard value sense resistor.

3. 12-Bit ADC.

Accurate voltage, current, and power measurements. Also

enables calculation of energy consumption over time.

4. PMBus/I²C Interface.

PMBus fast mode compliant interface used to read back

status and data registers and set warning and fault limits.

5. Fault Recording.

Latched status registers provide useful debugging infor-

mation to help trace faults in high reliability systems.

6. Built-In Soft Start.

28-lead LFCSP and TSSOP

−40°C to 105°C junction temperature (T_J) operating range

APPLICATIONS

Telecommunication and data communication equipment

Central office switching

−48 V distributed power systems

Negative power supply control

High availability servers

Soft start capacitor controls inrush current profile with

di/dt control.

FUNCTIONAL BLOCK DIAGRAM

–48V RTN (0V)

12V

R

DROP

SPLYGD

SHDN

RESTART

5V

VIN

3.3V

2.8V

...etc.

GND

LATCH

V

CC AND

POWER

ACCUMULATOR

VEE

REFERENCE

GENERATOR

GPO1/ALERT1/CONV

GPO2/ALERT2

SDAO

DC-TO-DC

CONVERTER

DIGITAL

AND

PMBUS

C

UVH

UVL

LOAD

POWER

MULTIPLIER

UNDERVOLTAGE

AND

OVERVOLTAGE

DETECTOR

SDAI

SCL

OV

12-BIT ADC

ADR

ADC_AUX

ADC_V

PWRGD

DRAIN

FET POWER

FOLDBACK

CONTROL

PLIM

VCAP

ISET

SDA_ISO

SCL_ISO

ADuM1250

FAULT TIMER

GATE CONTROL

CURRENT LIMIT

VEE

N-FET

GATE

SENSE+

SENSE–

R

SENSE

VEE_G

TIMER

SS

VEE

–48V

Figure 1.

Rev. A

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Tel: 781.329.4700 www.analog.com

ADM1075

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

ADM1075 Information Commands........................................ 31

Status Commands ...................................................................... 31

GPO and Alert Pin Setup Commands .................................... 32

Power Monitor Commands ...................................................... 32

Warning Limit Setup Commands............................................ 33

PMBus Direct Format Conversion .......................................... 34

Voltage and Current Conversion Using LSB Values.............. 35

ADM1075 Alert Pin Behavior ...................................................... 36

Faults and Warnings .................................................................. 36

Generating an Alert ................................................................... 36

Handling/Clearing an Alert...................................................... 36

SMBus Alert Response Address ............................................... 37

Example Use of SMBus Alert Response Address................... 37

Digital Comparator Mode......................................................... 37

PMBus Command Reference........................................................ 38

Register Details ............................................................................... 39

Operation Command Register ................................................. 39

Clear Faults Register .................................................................. 39

PMBus Capability Register ....................................................... 39

IOUT OC Warn Limit Register................................................ 39

VIN OV Warn Limit Register................................................... 39

VIN UV Warn Limit Register................................................... 39

PIN OP Warn Limit Register.................................................... 40

Status Byte Register.................................................................... 40

Status Word Register.................................................................. 40

IOUT Status Register ................................................................. 41

Input Status Register .................................................................. 41

Manufacturing Specific Status Register................................... 42

Read EIN Register...................................................................... 43

Read VIN Register...................................................................... 43

Read IOUT Register................................................................... 43

Read PIN Register ...................................................................... 43

PMBus Revision Register .......................................................... 43

Manufacturing ID Register ....................................................... 44

Manufacturing Model Register ................................................ 44

Manufacturing Revision Register............................................. 44

Peak IOUT Register ................................................................... 44

Peak VIN Register...................................................................... 45

Peak VAUX Register .................................................................. 45

Power Monitor Control Register.............................................. 45

Applications....................................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description......................................................................... 4

Specifications..................................................................................... 5

Serial Bus Timing ......................................................................... 9

Absolute Maximum Ratings.......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Description ............................ 11

Typical Performance Characteristic............................................. 13

Theory of Operation ...................................................................... 20

Powering the ADM1075............................................................ 20

Current Sense Inputs.................................................................. 21

Current Limit Reference............................................................ 21

Setting the Current Limit (ISET) ............................................. 22

Soft Start ...................................................................................... 22

Constant Power Foldback (PLIM) ........................................... 22

TIMER ......................................................................................... 23

Hot Swap Fault Retry ................................................................. 24

Fast Response to Severe Overcurrent ...................................... 24

UV and OV ................................................................................. 24

PWRGD

....................................................................................... 25

DRAIN......................................................................................... 25

SPLYGD

....................................................................................... 25

......................................................................................... 25

........................................................................................... 25

LATCH

SHDN

RESTART

..................................................................................... 25

FET Health .................................................................................. 26

Power Monitor............................................................................ 26

Isolation ....................................................................................... 26

PMBus Interface ............................................................................. 28

Device Addressing...................................................................... 28

SMBus Protocol Usage............................................................... 28

Packet Error Checking............................................................... 28

SMBus Message Formats........................................................... 29

Group Commands...................................................................... 30

Hot Swap Control Commands ................................................. 31

Rev. A | Page 2 of 52

Data Sheet

ADM1075

Power Monitor Configuration Register ...................................45

ALERT1 Configuration Register...............................................46

ALERT2 Configuration Register...............................................47

IOUT WARN2 Limit Register...................................................48

Device Configuration Register..................................................48

Power Cycle Register ..................................................................49

Peak PIN Register .......................................................................49

Read PIN_EXT Register.............................................................49

Read EIN_EXT Register ............................................................49

Read VAUX Register...................................................................50

VAUX OV Warn Limit Register................................................50

VAUX UV Warn Limit Register................................................50

VAUX Status Register.................................................................50

Outline Dimensions........................................................................51

Ordering Guide ...........................................................................51

REVISION HISTORY

4/12—Rev. 0 to Rev. A

Added 28-Lead LFCSP ...................................................... Universal

Changes to Features Section and Product Highlights Section....1

Change to Test Conditions/Comments column for GATE

Pin Parameter ....................................................................................4

Changes to ADC Conversion Time comments in Table 1...........8

Changes to Table 4 ..........................................................................10

Added Figure 4; Renumbered Sequentially; and changes to

Table 5...............................................................................................11

Changes to Current Limit Reference Section..............................21

Changes to Voltage and Current Conversion Using LSB

Values Section..................................................................................35

Changes to Table 8 ..........................................................................38

Changes to Table 20 ........................................................................43

Changes to Table 25 through Table 27 .........................................44

Changes to Table 32 ........................................................................45

Changes to Table 38 and Table 39.................................................49

Changes to Outline Dimensions and Ordering Guide...............51

10/11—Revision 0: Initial Version

Rev. A | Page 3 of 52

ADM1075

Data Sheet

GENERAL DESCRIPTION

The ADM1075 is a full feature, negative voltage, hot swap control-

ler with constant power foldback and high accuracy digital current

and voltage measurement that allows boards to be safely inserted

and removed from a live −48 V backplane. The part provides

precise and robust current limiting and protection against both

transient and nontransient short circuits and overvoltage and

undervoltage conditions. The ADM1075 typically operates from

a negative voltage of −35 V to −80 V and, due to shunt regulation,

has excellent voltage transient immunity. The operating range of

the part is flexible due to the shunt regulator, and the part can be

powered directly by a 10 V rail to save shunt power dissipation

(see the Powering the ADM1075 section for more details).

The ADM1075 has separate UVx and OV pins for undervoltage

and overvoltage detection. The FET is turned off if a nontransient

voltage less than the undervoltage threshold (typically −35 V) is

detected on the UVx pins or if greater than the overvoltage

threshold (typically −80 V) is detected on the OV pin. The

operating voltage range of the ADM1075 is programmable via

resistor networks on the UVx and OV pins. The hysteresis levels

on the overvoltage detectors can also be altered by selecting the

appropriate resistors. There are two separate UVx pins to allow

accurate programming of hysteresis.

In the case of a short circuit, the ADM1075 has a fast response

circuit to detect and respond adequately to this event. If the

sense voltage exceeds 1.5 times the normal current limit, a high

current (750 mA minimum) gate pull-down switch is activated

to shut down the MOSFET as quickly as possible. There is a

default internal glitch filter of 900 ns. If a longer filter time or

different severe overcurrent limit is required, these parameters

can be adjusted via the PMBus™ interface.

A full-scale current limit of 25 mV or 50 mV can be selected by

choosing the appropriate model. The maximum current limit is

set by the combination of the sense resistor, R_SENSE, and the input

voltage on the ISET pin, using external resistors. This allows fine

tuning of the trip voltage so that standard sense resistors can be

used. Inrush current is limited to this programmable value by

controlling the gate drive of an external N-channel FET. A built-

in soft start function allows control of the inrush current profile by

an external capacitor on the soft start (SS) pin.

The ADM1075 also includes a 12-bit ADC to provide digital

measurement of the voltage and load current. The current is

measured at the output of the internal current sense amplifier

and the voltage from the ADC_V input. This data can be read

across the PMBus interface.

An external capacitor on the TIMER pin determines the maxi-

mum allowed on-time for when the system is in current limit.

This is based on the safe operating area (SOA) limits of the

MOSFET. A constant power foldback scheme is used to control

the power dissipation in the MOSFET during power-up and

fault conditions. The ADM1075 regulates the current dynami-

cally to ensure that the power in the MOSFET is within SOA

limits as V_DSchanges. After the timer has expired, the device

shuts down the MOSFET. The level of this power, along with

the TIMER regulation time, can be set to ensure that the

MOSFET remains within the SOA limits.

The PMBus interface allows a controller to read current, voltage,

and power measurements from the ADC. Measurements can be

initiated by a PMBus command or can be set up to run continu-

ously. The user can read the latest conversion data whenever it

is required. A power accumulator is also provided to report

total power consumed in a user specified period (total energy).

Up to four unique I²C addresses can be created, depending on

the configuration of the ADR pin.

ALERT1

ALERT2

outputs can

The GPO1/

/CONV and GPO2/

The ADM1075 employs a limited consecutive retry scheme

be used as a flag to warn a microcontroller or FPGA of one or

more fault/warning conditions becoming active. The fault type

and level is programmed across the PMBus, and the user can

select which faults/warnings activate the alert.

LATCH

SHDN

when the

pin is tied to the

pin. In this mode,

if the load current reaches the limit, the FET gate is pulled low

after the timer expires and retries after a cooling period for

seven attempts only. If the fault remains, the device latches off,

and the MOSFET is disabled until a manual restart is initiated.

Alternatively, the ADM1075 can be set to retry only once by

Other functions include

PWRGD

•

output, which can be used to enable a power

LATCH

SHDN

isolating the

pin from the

pin. The part can

module (the DRAIN and GATE pins are monitored to

determine when the load capacitance is fully charged)

also be configured to retry an infinite number of times with a

10 second interval between restarts by connecting the GPO2

SHDN

•

input to manually disable the GATE drive

RESTART

pin to the

pin.

input to remotely initiate a 10 second shutdown

Rev. A | Page 4 of 52

Data Sheet

ADM1075

SPECIFICATIONS

VEE = −48 V, V_SENSE= (V_SENSE+− V_SENSE−) = 0 mV, shunt regulation current = 10 mA, T_J= −40°C to +105°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

SYSTEM SUPPLY

Voltage Transient Immunity

Typical Operating Voltage

SHUNT REGULATOR

−200

V

−80

11.5

−35

13

Determined by external component, R_SHUNT

Operating Supply Voltage Range, VIN

12.3

V

Shunt regulation voltage, I_IN= 5.5 mA to 30 mA,

maximum I_INdependent on T_A, θ_JA(see the Powering the

ADM1075 section)

Quiescent Supply Current

Undervoltage Lockout, V_{UVLO_RISING}

Undervoltage Lockout Hysteresis

Power Directly Without Shunt

UV PINS—UNDERVOLTAGE DETECTION

Undervoltage Rising Threshold, V_UVH

Undervoltage Falling Threshold, V_UVL

Total Undervoltage Hysteresis

Undervoltage Fault Filter

UV Propagation Delay

5.5

9.2

600

11.5

mA

V

mV

V

VIN = 13 V

9.2

0.99

0.887

1.0

0.9

100

1.01

0.913

V

mV

μs

nA

When UVL and UVH are tied together

UV low to GATE pull-down active

3.5

7.5

8

50

5

1

UVL/UVH Input Current

OV PIN—OVERVOLTAGE DETECTION

Overvoltage Rising Threshold, V_OVR

Overvoltage Hysteresis Current

Overvoltage Fault Filter

OV Propagation Delay

OV Input Current

0.99

4.3

1.75

1.0

5

1.01

5.7

3.75

4

V

μA

μs

nA

2

1

OV high to GATE pull-down active

50

GATE PIN

Gate Voltage High

Gate Voltage Low

Pull-Up Current

Pull-Down Current (Regulation)

Pull-Down Current (UV/OV/OC)

Pull-Down Current (Severe OC)

Pull-Down On-Time (Severe OC)

Gate Hold-Off Resistance

SENSE+, SENSE−

11

12

10

13

100

−30

V

I_GATE= −1.0 μA

I_GATE= 100 μA

V_GATE= 0 V to 8 V; V_SS= 2 V

V_GATE≥ 2 V

V_GATE≥ 6 V

mV

μA

mA

μs

−50

100

5

750

8

10

1500

2000

16

20

Ω

0 V ≤ VIN ≤ 9.2 V

SENSE+, SENSE− Input Current, I_SENSEx

100

1

ꢀA

V_SENSE≤ 65 mV for ADM1075-1, per individual pin;

V_SENSE≤ 130 mV for ADM1075-2, per individual pin

I_ΔSENSEx= I_SENSE+− I_SENSE−

SENSE+, SENSE− Input Imbalance, I_ΔSENSEx

VCAP

Internally Regulated Voltage, V_VCAP

ISET

ISET Reference Select Threshold, V_ISETRSTH

ISET Internal Reference, V_CLREF

Gain of Current Sense Amplifier, AV_CSAMP

ISET Input Current, I_ISET

2.66

1.35

2.7

2.74

1.65

V

0 ≤ I_VCAP≤ 100 ꢀA; C_VCAP= 1 ꢀF

1.5

1

50/25

V

V/V

nA

If V_ISET> V_ISETRSTHan internal 1 V reference (V_CLREF) is used

Accuracies included in total sense voltage accuracies

V_ISET≤ VCAP

100

ADM1075-1 ONLY (GAIN = 50)

Hot Swap Sense Voltage

Hot Swap Sense Voltage Current Limit,

V_SENSECL

19.4

20

20.6

mV

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

24.5

19.5

14.5

25

20

15

25.5

20.5

15.5

mV

V_ISET= 1.25 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

V_ISET= 1.0 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

V_ISET= 0.75 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

Rev. A | Page 5 of 52

ADM1075

Data Sheet

Parameter

Min

9.4

4.5

1.4

0.6

Typ

10

5

2

0.75

Max

11.0

5.7

2.6

0.95

Unit Test Conditions/Comments

Constant Power Active

mV

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0.2 V

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0.4 V

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 1.2 V

Circuit breaker voltage, V_CB= V_SENSECL− V_CBOS

Circuit Breaker Offset, V_CBOS

Severe Overcurrent

Activates high current gate pull-down

Voltage Threshold, V_SENSEOC

23

28

38

43

25

30

40

45

27

32

42

47

mV

V_ISET> 1.65 V; V_SS≥ 2 V; optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; default at power-up

V_ISET> 1.65 V; V_SS≥ 2 V; optional select through PMBus

Response Time

Glitch Filter Duration

50

200

900

10.7

57

ns

μs

ns

μs

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

default at power-up

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

default at power-up

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 18 mV to 52 mV;

optional select through PMBus

500

6.2

44

Total Response Time

180

610

7

300

950

13

45

60

ADM1075-2 ONLY (GAIN = 25)

Hot Swap Sense Voltage

Hot Swap Sense Voltage Current Limit,

V_SENSECL

39.2

40

40.8

mV

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

49.2

39.2

29.2

19

9.2

3

50

40

30

20

10

4

50.8

40.8

30.8

21.9

11.2

5.0

mV

V_ISET= 1.25 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

V_ISET= 1.0 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

V_ISET= 0.75 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0 V

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0.2 V

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 0.4 V

V_ISET> 1.65 V; V_GATE= 3 V; I_GATE= 0 ꢀA; V_SS≥ 2 V; V_PLIM= 1.2 V

Circuit breaker voltage, V_CB= V_SENSECL− V_CBOS

Constant Power Active

Circuit Breaker Offset, V_CBOS

Severe Overcurrent

1.1

1.5

1.9

Activates high current gate pull-down

Voltage Threshold, V_SENSEOC1

46

56

76

86

50

60

80

90

54

64

84

94

mV

V_ISET> 1.65 V; V_SS≥ 2 V; optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; default at power-up

V_ISET> 1.65 V; V_SS≥ 2 V; optional select through PMBus

Response Time

Glitch Filter Duration

50

200

900

10.7

57

ns

μs

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

default at power-up

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

optional select through PMBus

400

6.2

44

Rev. A | Page 6 of 52

Data Sheet

ADM1075

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

Total Response Time

180

300

ns

μs

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

default at power-up

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

optional select through PMBus

V_ISET> 1.65 V; V_SS≥ 2 V; V_SENSEstep from 36 mV to 104 mV;

optional select through PMBus

610

7

950

13

45

60

SOFT START

SS Pull-Up Current, I_SS

Default V_SENSECLLimit

−11.5

0.6

−10

1.25

−8.5

1.9

μA

mV

V_SS= 0V

When V_SENSEreaches this level, I_SSis enabled, ramping;

V_SS= 0 V; ADM1075-1 only (gain = 50)

1.2

2.5

3.8

mV

μA

When V_SENSEreaches this level, I_SSis enabled, ramping;

V_SS= 0 V; ADM1075-2 only (gain = 25)

V_SS= 1 V

SS Pull-Down Current

100

TIMER

Timer Pull-Up Current (POR), I_TIMERUPPOR

Timer Pull-Up Current (OC Fault), I_TIMERUPFLT

Timer Pull-Down Current (Retry), I_TIMERDNRT

Timer Retry/OC Fault Current Ratio

Timer Pull-Down Current (Hold), I_TIMERDNHOLD

Timer High Threshold, V_TIMERH

Timer Low Threshold, V_TIMERL

PLIM

−4

−63

1.7

−3

−60

2

3.33

100

1.0

−2

−57

2.3

μA

%

μA

V

Initial power-on reset; V_TIMER= 0.5 V

Overcurrent fault; 0.05 V ≤ V_TIMER≤ 1 V

After a fault when GATE is off; V_TIMER= 0.5 V

Defines the limits of the autoretry duty cycle

Holds TIMER at 0 V when inactive; V_TIMER= 0.5 V

0.98

0.03

1.02

0.07

0.05

V

PLIM Active Threshold

Input Current, I_PLIM

Minimum Current Clamp, V_ICLAMP

0.08

75

0.09

100

0.1

100

125

V

nA

mV

V_ISET> 1.65 V

V_PLIM≤ 1 V

V_PLIM= 1.2 V; V_{SENSE_IMIN}= (V_ICLAMP÷ gain) = minimum

allowed current control

DRAIN

PWRGD

1.9

1.1

2

2.1

V

I_DRAIN≤ 50 μA

DRAIN Voltage at Which

ADC_AUX/ADC_V

Input Current

Asserts

100

nA

0 V ≤ V_ADC≤ 1.5 V

SHDN

Input High Voltage, V_IH

Input Low Voltage, V_IL

Glitch Filter

V

μs

μA

0.8

1

8

Internal Pull-Up Current

Pull-up to VIN

RESTART

Input High Voltage, V_IH

Input Low Voltage, V_IL

Glitch Filter

1.1

V

μs

μA

1

8

Internal Pull-Up Current

SPLYGD

Output Low Voltage, V_{OL_LATCH}

0.4

1.5

100

1

V

nA

μA

I_SPLYGD= 1 mA

I_SPLYGD= 5 mA

Leakage Current

SPLYGD

pin disabled

V_SPLYGD≤ 2 V;

SPLYGD

V_SPLYGD≤ 14 V;

pin disabled

LATCH

Output Low Voltage, V_{OL_LATCH}

0.4

1.5

100

1

V

nA

μA

I_LATCH= 1 mA

I_LATCH= 5 mA

Leakage Current

LATCH

V_LATCH≤ 2 V;

pin disabled

LATCH

V_LATCH≤ 14 V;

pin disabled

ALERT1

GPO1/ /CONV PIN

Output Low Voltage, V_{OL_GPO1}

0.4

1.5

V

I_GPO= 1 mA

I_GPO= 5 mA

Rev. A | Page 7 of 52

ADM1075

Data Sheet

Parameter

Min

Typ

Max

100

1

Unit Test Conditions/Comments

Leakage Current

nA

μA

V

V_GPO≤ 2 V; GPO disabled

V_GPO= 14 V; GPO disabled

Configured as CONV pin

Input High Voltage, V_IH

Input Low Voltage, V_IL

Glitch Filter

1.1

0.8

V

μs

1

ALERT2

GPO2/

Output Low Voltage, V_{OL_GPO2}

0.4

1.5

100

1

V

nA

μA

I_GPO= 1 mA

I_GPO= 5 mA

V_GPO≤ 2 V; GPO disabled

V_GPO= 14 V; GPO disabled

Leakage Current

PWRGD

Output Low Voltage, V_{OL_PWRGD}

0.4

1.5

V

I_PWRGD= 1 mA

I_PWRGD= 5 mA

VIN That Guarantees Valid Output

Leakage Current

1

V

nA

I_SINK= 100 ꢀA; V_{OL_PWRGD}= 0.4 V

100

1

PWRGD

V_PWRGD≤ 2 V;

active

PWRGD

μA

V_PWRGD= 14 V;

active

CURRENT AND VOLTAGE MONITORING

Current Sense Absolute Error (ADM1075-1)

25 mV input range; 128 sample averaging (unless

otherwise noted)

−0.01

0.05

0.07

0.04

0.7

0.85

%

V_SENSE= 25 mV

V_SENSE= 20 mV

V_SENSE= 20 mV; 16 sample averaging

V_SENSE= 20 mV; 1 sample averaging

V_SENSE= 15 mV

V_SENSE= 10 mV

V_SENSE= 5 mV

V_SENSE= 2.5 mV

0.85

2.8

1.0

1.4

2.7

5.9

Current Sense Absolute Error (ADM1075-2)

50 mV input range; 128 sample averaging (unless

otherwise noted)

−0.03

−0.04

0.65

0.7

1.35

0.75

0.9

1.7

3.0

+0.8

%

V_SENSE= 50 mV

V_SENSE= 40 mV

V_SENSE= 40 mV; 16 sample averaging

V_SENSE= 40 mV; 1 sample averaging

V_SENSE= 30 mV

V_SENSE= 20 mV

V_SENSE= 10 mV

V_SENSE= 5 mV

0.6 V ≤ V_ADC≤ 1.5 V

ADC_V/ADC_AUX Absolute Accuracy

ADC Conversion Time

−0.8

1 sample of voltage and current; from command

received to valid data in register

191

263

219

301

μs

VAUX disabled

VAUX enabled

16 samples of voltage and current averaged; from

command received to valid data in register

2.830

3.987

3.243

4.568

ms

VAUX disabled

VAUX enabled

128 samples of voltage and current averaged; from

command received to valid data in register

22.54

31.79

14

25.83

36.43

ms

μs

VAUX disabled (default on power-up)

VAUX enabled

Power Multiplication Time

Rev. A | Page 8 of 52

Data Sheet

ADM1075

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

ADR PIN

See Table 6

Address Set to 00

Input Current for Address 00

Address Set to 01

Address Set to 10

Address Set to 11

Input Current for Address 11

0

0.8

V

Connect to VEE

V_ADR= 0 V to 0.8 V

Resistor to VEE

No connect state; maximum leakage current allowed

Connect to VCAP

−40

135

−1

2.1

−22

150

ꢀA

kΩ

ꢀA

V

165

+1

3

10

ꢀA

V_ADR= 2.0 V to VCAP; must not exceed the maximum

allowable current draw from VCAP

SERIAL BUS DIGITAL INPUTS (SDAI/SDAO, SCL)

Input High Voltage, V_IH

1.1

V

Input Low Voltage, V_IL

Output Low Voltage, V_OL

Input Leakage, I_LEAK-PIN

0.8

0.4

+10

+5

5.5

400

V

I_OL= 4 mA, SDAO only

−10

−5

2.7

ꢀA

V

pF

ns

Device is not powered

3 V to 5 V 10%

Nominal Bus Voltage, V_DD

Capacitive Load per Bus Segment, C_BUS

Capacitance for SDAI, SDAO, or SCL Pin, C_PIN

Input Glitch Filter, t_SP

5

0

50

SERIAL BUS TIMING

Table 2.

Parameter

Description

Min

Typ

Max

Unit Test Conditions/Comments

f_SCLK

t_BUF

Clock frequency

Bus free time

400

kHz

μs

ns

μs

ns

1.3

0.6

300

100

1.3

0.6

20

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_SU;DAT

t_LOW

Start hold time

Start setup time

Stop setup time

SDA¹hold time

SDA¹setup time

SCL low time

900

t_HIGH

SCL high time

t_R

SCL, SDA¹rise time

SCL, SDA¹fall time

SCL, SDA¹output fall time

300

250

2

t_F

t_OF

20

20 + 0.1 × C_BUS

¹SDAI and SDAO tied together.

²t_R= (V_IL(MAX)– 0.15) to (V_IH3V3+ 0.15) and t_F= 0.9 V_DDto (V_IL(MAX)– 0.15); where V_IH3V3= 2.1 V, and V_DD= 3.3 V.

t_LOW

t_R

t_F

V

IH

SCL

SDA

V

IL

t_SU;STA

t_SU;DAT

t_SU;STO

t_HD;DAT

t_HD;STA

t_HIGH

V

IH

V

IL

t_BUF

P

S

P

Figure 2. Serial Bus Timing Diagram

Rev. A | Page 9 of 52

ADM1075

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

VIN Pin to VEE

−0.3 V to +14 V

−0.3 V to +4 V

UVL Pin to VEE

UVH Pin to VEE

OV Pin to VEE

−0.3 V to +4 V

ADC_V Pin to VEE

ADC_AUX Pin to VEE

SS Pin to VEE

−0.3 V to +4 V

−0.3 V to (VCAP + 0.3 V)

−0.3 V to +4 V

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

TIMER Pin to VEE

VCAP Pin to VEE

ISET Pin to VEE

SPLYGD Pin to VEE

LATCH Pin to VEE

RESTART Pin to VEE

SHDN Pin to VEE

PWRGD Pin to VEE

DRAIN Pin to VEE

SCL Pin to VEE

−0.3 V to +4 V

Table 4. Thermal Resistance

−0.3 V to +18 V

−0.3 V to (VCAP + 0.3 V)

−0.3 V to +6.5 V

−0.3 V to (VCAP + 0.3 V)

−0.3 V to +18 V

1

Package Type

28-Lead TSSOP

28-Lead LFCSP

θ_JA

68

35

θ_JC

20

4

Unit

°C/W

¹Measured on JEDEC 4-layer board in still air.

ESD CAUTION

SDAI Pin to VEE

SDAO Pin to VEE

ADR Pin to VEE

GPO1/

GPO2/

/CONV Pin to VEE

Pin to VEE

ALERT1

−0.3 V to +18 V

ALERT2

PLIM Pin to VEE

GATE Pin to VEE

SENSE+ Pin to VEE

SENSE− Pin to VEE

VEE to VEE_G

Continuous Current into Any Pin

Storage Temperature Range

Operating Junction Temperature

Range

−0.3 V to +4 V

−0.3 V to +18 V

−0.3 V to +4 V

−0.3 V to +0.3 V

10 mA

−65°C to +125°C

−40°C to +105°C

Lead Temperature, Soldering (10 sec)

Junction Temperature

300°C

150°C

Rev. A | Page 10 of 52

Data Sheet

ADM1075

PIN CONFIGURATION AND FUNCTION DESCRIPTION

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DRAIN

VEE_G

2

GATE

VIN

3

SENSE+

SENSE–

VEE

UVH

4

UVL

5

OV

ADM1075

TOP VIEW

(Not to Scale)

21 SENSE–

OV

PLIM

1

2

3

4

5

6

7

6

20 VEE

PLIM

VCAP

ADC_V

ISET

SS

SPLYGD

ADC_AUX

PWRGD

SCL

19 SPLYGD

VCAP

ADC_V

ISET

7

ADM1075

TOP VIEW

(Not to Scale)

18 ADC_AUX

17 PWRGD

16 SCL

8

9

SS

10

11

12

13

14

SDAI

TIMER

15 SDAI

TIMER

LATCH

ADR

SDAO

GPO2/ALERT2

GPO1/ALERT1/CONV

RESTART

SHDN

NOTES

1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE BOARD TO

IMPROVE THERMAL DISSIPATION. THE EXPOSED PAD CAN BE

CONNECTED TO VEE.

Figure 4. LFCSP Pin Configuration

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic

Description

Connect to the drain pin of the FET through a resistor. The current in this resistor is used to

determine the V_DSof the MOSFET. This is used for

1

25

DRAIN

.

PWRGD

2

3

4

5

6

7

26

27

28

1

VIN

Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via a shunt resistor. A

1 μF capacitor to VEE is recommended on the VIN pin.

Undervoltage Rising Input Pin. An external resistor divider is used from the supply to this pin to

allow an internal comparator to detect if the supply is under the UVH limit.

Undervoltage Falling Input Pin. An external resistor divider is used from the supply to this pin to

allow an internal comparator to detect if the supply is under the UVL limit.

Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an

internal comparator to detect if the supply is above the OV limit.

The voltage on this pin is proportional to the V_DSvoltage of the FET. As the PLIM voltage changes,

the current limit automatically adjusts to maintain constant power across the FET.

A capacitor with a value of 1 μF or greater should be placed on this pin to maintain good accuracy.

This is an internal regulated supply. This pin can be used as a reference to program the ISET pin

voltage.

UVH

UVL

OV

2

PLIM

VCAP

3

8

9

4

5

ADC_V

ISET

This pin is used to read back the input voltage using the internal ADC. It can be connected to the OV

string or a separate divider.

This pin allows the current limit threshold to be programmed. The default limit is set when this pin is

connected directly to VCAP. Alternatively, using a resistor divider from VCAP, the current limit can be

adjusted to achieve a user defined sense voltage. An external reference can also be used.

10

6

7

SS

A capacitor is used on this pin to set the inrush current soft start ramp profile. The voltage on the

soft start pin controls the current sense voltage limit, allowing control over the inrush current

profile.

Timer Pin. An external capacitor, C_TIMER, sets an initial timing cycle delay and a fault delay. The GATE

pin turns off when the voltage on the TIMER pin exceeds the upper threshold.

This pin signals the device latching off after an overcurrent fault. This pin is also used to configure

the desired retry scheme. See the Hot Swap Fault Retry section for additional details.

PMBus Address Pin. This pin can be tied low, tied to VCAP, left floating, or tied low through a resistor

to set four different PMBus addresses.

11

12

13

TIMER

8

9

LATCH

ADR

Rev. A | Page 11 of 52

ADM1075

Data Sheet

Pin No.

TSSOP LFCSP Mnemonic

Description

14

Drive this pin low to shut down the gate. Internal weak pull-up to VIN.

10

SHDN

This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for

additional details.

15

16

Falling Edge Triggered 10 sec Automatic Restart. The gate remains off for 10 seconds, and then

powers back up. Internal weak pull-up to VIN. This pin is also used to configure the desired retry

scheme. See the Hot Swap Fault Retry section for additional details.

General-Purpose Digital Output (GPO1).

Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or

warning conditions have been detected.

11

12

RESTART

GPO1/

/CONV

ALERT1

Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC

sampling cycle begins.

This pin defaults to indicate FET health mode at power-up. There is no internal pull-up on this pin.

17

13

General-Purpose Digital Output (GPO2).

GPO2/

ALERT2

Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or

warning conditions have been detected.

This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for

further details. This pin defaults to indicate a seven-attempt fail at power-up.

There is no internal pull-up on this pin.

18

19

20

21

14

15

16

17

SDAO

SDAI

SCL

PMBus Serial Data Output. This is a split version of the SDA for easy use with optocouplers.

PMBus Serial Data Input. This is a split version of the SDA for easy use with optocouplers.

PMBus Clock Pin. Open-drain input requires an external resistive pull-up.

Power-Good Signal. This pin is used to indicate that the FET is no longer in the linear region and

PWRGD

capacitors are fully charged. See the

section for details on assert and deassert.

PWRGD

22

23

18

19

20

21

ADC_AUX

SPLYGD

VEE

This pin is used to read back a voltage using the internal ADC.

This pin asserts low when the supply is within the UV and OV limits set by the UVx and OV pins.

24

25

Chip Ground Pin. Must connect to –VIN rail (lowest potential).

SENSE−

Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets

the analog current limit. The hot swap operation controls the external FET gate to maintain the

(V_SENSE+− V_SENSE−) sense voltage. This pin also connects to the VEE node, but should be routed

separately.

26

27

28

22

23

SENSE+

GATE

Positive Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets

the analog current limit. The hot swap operation controls the external FET gate to maintain the

(V_SENSE+− V_SENSE−) sense voltage. This pin also connects to the FET source node.

Gate Output Pin. This pin is the gate drive of an external N-channel FET. It is driven by the FET drive

controller. The FET drive controller regulates to a maximum load current by regulating the GATE pin.

GATE is held low while the supply is out of the voltage range.

Chip Ground Pin. Must connect to –VIN rail (lowest potential). The PCB layout should configure this

pin as the gate pull-down return.

Exposed Pad. Solder the exposed pad to the board to improve thermal dissipation. The exposed pad

can be connected to VEE.

24

VEE_G

EPAD

Rev. A | Page 12 of 52

Data Sheet

ADM1075

TYPICAL PERFORMANCE CHARACTERISTIC

5.0

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

RISING

FALLING

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

Figure 5. I_INvs. Temperature

Figure 8. UVLO vs. Temperature

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

10

9

8

I

= 30mA

= 5.5mA

IN

I

IN

7

6

5

4

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

Figure 6. VIN vs. Temperature

Figure 9. V_GATELow vs. Temperature (I_GATE= 100 μA)

100

10

1

14

12

10

8

+105°C

+85°C

+25°C

–40°C

0µA

5µA

6

4

2

0.1

0

–40

1

2

3

4

5

6

7

8

9

10 11 12 13

–20

0

20

40

60

80

100

120

VIN (V)

TEMPERATURE (°C)

Figure 7. I_INvs. VIN

Figure 10. V_GATEHigh vs. Temperature

Rev. A | Page 13 of 52

ADM1075

Data Sheet

50

45

40

35

30

25

20

15

10

5

14

12

10

8

6

4

2

0

2

4

6

8

10

12

14

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

V

(V)

GATE

Figure 11. I_GATEPull-Down vs. Temperature

Figure 14. I_GATEPull-Up vs. V_GATE

12

10

8

0

–2

–4

–6

–8

6

–10

–12

–14

–16

–18

–20

4

2

0

2

4

6

8

10

12

14

–50 –35 –20 –5

10

25

40

55

70

85 100 115

V

(V)

GATE

TEMPERATURE (°C)

Figure 12. I_GATEPull-Down vs. V_GATE

Figure 15. SS Pull-Up Current vs. Temperature

0

–5

0

–10

–20

–30

–40

–50

–60

–70

–80

–10

–15

–20

–25

–30

–35

–40

–45

–50

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

Figure 13. I_GATEPull-Up vs. Temperature

Figure 16. I_TIMERPull-Up vs. Temperature

Rev. A | Page 14 of 52

Data Sheet

ADM1075

200

180

160

140

120

100

80

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

60

40

20

0

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

Figure 20. PLIM Threshold vs. Temperature

Figure 17. I_TIMERPOR Pull-Up vs. Temperature

200

180

160

140

120

100

80

6

5

4

3

2

1

0

60

40

20

0

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

Figure 18. I_TIMERRetry Pull-Down vs. Temperature

Figure 21. PLIM Current Clamp vs. Temperature

3.0

2.5

2.0

1.5

1.0

0.5

0

1000

800

600

400

200

0

HIGH

LOW

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

Figure 19. TIMER Threshold vs. Temperature

Figure 22. VCAP vs. Temperature (I_VCAP= 100 μA)

Rev. A | Page 15 of 52

ADM1075

Data Sheet

16

14

12

10

8

UVH

UVL

1000

800

600

400

200

0

6

4

2

0

–40

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 23. UVx Threshold vs. Temperature

Figure 26. Restart Time vs. Temperature

1000

900

800

700

600

500

400

300

200

100

0

1000

800

600

400

200

0

900ns GLITCH FILTER

200ns GLITCH FILTER

–50 –35 –20 –5

10

25

40

55

70

85 100 115

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

Figure 24. OV Threshold vs. Temperature

Figure 27. Severe OC Response vs. Temperature

60000

50000

40000

30000

20000

10000

0

100

80

57.5µs GLITCH FILTER

60

40

20

SENSE–

SENSE+

0

–20

–40

–60

–80

10.7µs GLITCH FILTER

–100

0

–50 –35 –20 –5

10

25

40

55

70

85 100 115

20

40

60

80

(mV)

100

120

V

TEMPERATURE (°C)

SENSE

Figure 25. I_SENSEvs. V_SENSE

Figure 28. Severe OC Response vs. Temperature

Rev. A | Page 16 of 52

Data Sheet

ADM1075

50

45

40

35

30

25

20

15

10

5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

ADM1075-2 +85°C

ADM1075-2 +25°C

ADM1075-2 –40°C

ADM1075-1 +85°C

ADM1075-1 +25°C

ADM1075-1 –40°C

ISET = 1.65V

ISET = 1.25V

ISET = 1.0V

ISET = 0.75V

ISET = 0.25V

ISET = 0.125V

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

(V)

–50 –35 –20 –5

10

25

40

55

70

85 100 115

TEMPERATURE (°C)

V

PLIM

Figure 29. Circuit Breaker Offset vs. Temperature, ADM1075-1

Figure 32. V_SENSECLvs. PLIM

2.0

1.8

1.6

1.4

1.2

1.0

25

20

15

10

5

0.8

ISET = 1.65V

ISET = 1.25V

ISET = 1.0V

ISET = 0.75V

ADM1075-1

0.6

0.4

ISET = 0.25V

ISET = 0.125V

ADM1075-2

0.2

0

–50 –35 –20 –5

10

25

40

55

70

85 100 115

0

0.5

1.5

1.0

ISET (V)

TEMPERATURE (°C)

Figure 33. Worst-Case Hot Swap V_SENSEAccuracy vs. ISET

Figure 30. Circuit Breaker Offset vs. Temperature, ADM1075-2

60

50

40

30

20

10

0

50

45

ADM1075-2

40

35

30

25

ADM1075-1

20

ADM1075-2

15

10

5

ADM1075-1

0

0.5

1.0

1.5

–50 –35 –20 –5

10

25

40

55

70

85 100 115

ISET (V)

TEMPERATURE (°C)

Figure 34. Typical Hot Swap V_SENSECLvs. ISET

Figure 31. V_SENSECLvs. Temperature, ISET = 1.65 V

Rev. A | Page 17 of 52

ADM1075

Data Sheet

50

45

40

35

30

25

20

15

10

5

140

120

100

80

225%

200%

225%

200%

150%

125%

150%

60

125%

40

ISET UNDEFINED

IN GREY AREA

20

0

0.25

–50 –35 –20 –5

10

25

40

55

70

85 100 115

0.45

0.65

0.85

1.05

1.25

1.45

1.65

TEMPERATURE (°C)

ISET (V)

Figure 38. Severe OC Threshold vs. ISET, ADM1075-2

Figure 35. Severe OC Threshold vs. Temperature, ADM1075-1, ISET = 1.65 V

7

6

5

4

3

2

1

0

100

225%

90

200%

80

70

ADM1075-1

150%

60

125%

50

40

30

20

10

0

ADM1075-2

0

10

20

30

40

50

60

–50 –35 –20 –5

10

25

40

55

70

85 100 115

SENSE VOLTAGE (mV)

TEMPERATURE (°C)

Figure 39. Worst-Case Current Sense Power Monitor Error vs. Current Sense

Voltage (V_SENSE

Figure 36. Severe OC Threshold vs. Temperature, ADM1075-2, ISET = 1.65 V

)

70

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

60

225%

50

PWRGD

GPO1

200%

GPO2

40

30

20

10

0

150%

LATCH

SPLYGD

125%

ISET UNDEFINED

IN GREY AREA

0.25

0.45

0.65

0.85

1.05

1.25

1.45

1.65

0

1

2

3

4

5

6

7

8

9

10

ISET (V)

I

(mA)

OL

Figure 37. Severe OC Threshold vs. ISET, ADM1075-1

Figure 40. V_OLvs. I_OL

Rev. A | Page 18 of 52

Data Sheet

ADM1075

11 DECODE

10 DECODE

00 DECODE

3.0

01 DECODE

2.5

2.0

1.5

1.0

0.5

0

–25

–20

–15

–10

(µA)

–5

0

5

I

ADR

Figure 41. V_ADRvs. I_ADR

Rev. A | Page 19 of 52

ADM1075

Data Sheet

THEORY OF OPERATION

When circuit boards are inserted into a live backplane,

discharged supply bypass capacitors draw large transient

currents from the backplane power bus as they charge. Such

transient currents can cause permanent damage to connector

pins, as well as dips on the backplane supply that can reset other

boards in the system.

For example, the maximum shunt current with a TSSOP device

at 80°C maximum ambient can be calculated as

105°C − 80°C

68°C/W ×13 V

I_{SHUNT _ MAX}

=

= 28 mA

Tolerance of supplies and resistors should also be accounted for

to ensure that the shunt current is always within the desired range.

The ADM1075 is intended to control the powering on and off

of a board in a controlled manner, allowing the board to be

removed from, or inserted into, a live backplane by protecting it

from excess currents. The ADM1075 can reside either on the

backplane or on the removable board.

Care must be taken to ensure that the power rating of the shunt

resistor is sufficient. The power may be as high as 2 W at

extreme supply conditions. Multiple shunt resistors can be used

in series or in parallel to share power between resistors.

P_{R_SHUNT}=VI = (V_{IN _MAX}−V_{SHUNT _ MIN})×I_MAX

A minimal load current requirement is assumed when charging

the load capacitance. If the load current is too large relative to

the regulation current, it may not be possible to charge the load

where:

V

_{IN _MAX}−V_{SHUNT_MIN}

PWRGD

capacitance. The

pin can be used to disable the load

I_MAX

=

until the load capacitance is fully charged.

R_SHUNT

POWERING THE ADM1075

The power dissipation in the shunt resistor can be saved if a

suitable voltage rail is available to power the chip directly. This

voltage rail must be well regulated to ensure that it is always

greater than the UVLO threshold but less than the minimum

shunt regulation voltage. The power directly without shunt

specification in Table 1 shows the limits this voltage rail must

meet. Note that this voltage is referenced to VEE.

The ADM1075 typically operates from a negative supply of

−35 V to −80 V and can tolerate transient voltages of up to

−200 V. The VINpin is a positive supply pin with respect to

chip ground. It is a current-driven supply and is shunt regulated

to 12 V internally. It should be connected to the most positive

supply terminal (usually −48 V RTN or 0 V) through a dropper

resistor. The resistor should be chosen such that it always

supplies enough current to overcome the maximum quiescent

supply current of the chip while not exceeding the maximum

allowable shunt current. After the system supply range has been

established, an appropriate value for the dropper resistor can be

calculated.

The VIN pin provides the majority of the bias current for the

device. The remainder of the current needed to control the gate

drive and to best regulate the V_GSvoltage is supplied by the

SENSE pins. The VEE and SENSE− pins are connected to the

same voltage rail, although through separate traces to prevent

accuracy loss in the sense voltage measurement (see Figure 42).

–48V RTN

V_{IN _ MAX}−V_{SHUNT _ MIN}

R_{SHUNT _ MIN}

=

I_{SHUNT _ MAX}

R

SHUNT

C

LOAD

VIN

V_{IN _ MIN}−V_{SHUNT _ MAX}

1µF

VEE

R_{SHUNT _ MAX}

=

I_{SHUNT _ MIN}

GATE

Q1

R

where:

_{IN_MIN}and V_{IN_MAX}are the supply voltage extremes (that is, 35 V,

80 V).

ADM1075

SENSE+

SENSE–

V

SENSE

V

_{SHUNT_MIN}and V_{SHUNT_MAX}are the shunt regulator voltage data

sheet specifications (see Table 1).

VEE

I

_{SHUNT_MIN}is the maximum quiescent supply current (minimum

Figure 42. Powering the ADM1075

shunt current).

I

_{SHUNT_MAX}is the maximum shunt input current.

The available shunt current range should be wide enough to

accommodate most telecommunication input voltage ranges.

In an application where a wider input voltage range is possible,

some external circuitry may be required to meet the shunt

regulation current specifications. The applications diagram in

Figure 43 shows an example of such a circuit, using a Zener

diode and a bipolar junction transistor (BJT) device as an

external pre-regulator on the −48 V supply. This ensures that

the shunt regulation current is always within specification even

at the extremes of supply voltage.

_{SHUNT_MAX}can be calculated based on the maximum ambient

temperature (T_A(MAX)) in the application, the maximum junction

temperature (T_J(MAX)= 105°C), and the θ_JAvalue of the package

from Table 4. Worst-case internal power is at VIN_(MAX)from

Table 1.

T

_J(MAX)−T_A(MAX)

I_{SHUNT _ MAX}

=

θ_JA×VIN_(MAX)

Rev. A | Page 20 of 52

Data Sheet

ADM1075

–48V RTN

VIN

Rb1 = 100kΩ

Rb2 = 640Ω

ADM1075

Q1

GATE

18V

TO

75V

C

Ib = 6µA TO 33µA

11V

IN

10.3V (5.5mA TO 10mA)

SENSE+

SENSE–

BIAS

CURRENT

R

= 15Ω

DROP

C

LOAD

VIN

–48V

1µF

VEE

GATE

VEE

Q

1

Figure 45. Connection of Multiple Sense Resistors to SENSE Pins

ADM1075

SENSE+

SENSE–

R

SENSE

CURRENT LIMIT REFERENCE

The current limit reference voltage determines the load current

level to which the ADM1075 limits the current during an

overcurrent event. This is the reference voltage to which the

gained up current sense voltage is compared to determine if the

limit is reached. This current limit voltage, shown in Figure 46,

is then converted to a gate current to regulate the GATE pin.

VEE

Figure 43. Wide Input Supply Range

CURRENT SENSE INPUTS

The load current is monitored by measuring the voltage drop

across an external sense resistor, R_SENSE. An internal current

sense amplifier provides a gain of 25 or 50 (depending on the

model) to the voltage drop detected across R_SENSE. The result is

compared to an internal reference and detects when an

overcurrent condition occurs.

I_GATE=V_{CURR _ LIM}× g_m

where g_m, the gate transconductance, = 660 μS.

An internal current limit reference selector block continuously

compares the ISET, soft start, and foldback (derived from PLIM)

voltages, determines which is the lowest at any given time, and

uses it as the current limit reference. This ensures that the

programmed current limit, ISET, is used in normal operation

and the soft start and foldback features reduce the current limit

when required.

VIN

ADM1075

GATE

Q1

OVER-

CURRENT

SENSE+

SENSE–

R

+

–

×25/50

–

SENSE

The foldback and soft start voltages change during different

stages of operation and are clamped to a lower level of 100 mV

(typical) to prevent zero current flow due to the current limit

being too low.

1V REF

VEE

Figure 44. Hot-Swap Current Sense Amplifier

PLIM

ADM1075

The SENSE inputs can be connected to multiple parallel sense

resistors, which can affect the voltage drop detected by the

ADM1075. The current flowing through the sense resistors

creates an offset, resulting in reduced accuracy. To achieve

better accuracy, averaging resistors should be used to sum the

sense nodes of each sense resistor, as shown in Figure 45. The

typical value for the averaging resistors is 10 Ω. The value of the

averaging resistors is chosen to be much greater than the trace

resistance between the sense resistor terminals and the inputs to

the ADM1075. This greatly reduces the effects of differences in

the trace resistances.

GATE

DRIVE

GATE

LOGIC

CURRENT

TIMEOUT

LIMIT

VOLTAGE

REF

ISET

SELECT

–

+

1.0V

VCAP

CURRENT

LIMIT

SENSE+

SENSE–

+

×25/50

–

CURRENT

LIMIT

10µA

CONTROL

FLB

( = 0.1/PLIM)

SS

VEE

Figure 46. Current Limit Reference Selection

Rev. A | Page 21 of 52

ADM1075

Data Sheet

V

Assuming V_ISETequals the voltage on the ISET pin, the resistor

divider should be sized to set the ISET voltage as follows:

FLB

SS

V_ISET= (V_SENSE× 50) for ADM1075-1 or

V_ISET= (V_SENSE× 25) for ADM1075-2

1V

ISET

where V_SENSEis the sense voltage limit. The VCAP rail can also

be used as the pull-up supply for setting the I²C address. The

VCAP pin should not be used for any other purpose. To

guarantee accuracy specifications, care must be taken to not

load the VCAP pin by more than 100 μA.

CURRENT LIMIT

REFERENCE

SOFT START

0.1V

A capacitor connected to the SS pin determines the inrush

current profile. Before the FET is enabled, the output voltage of

the current limit reference selector block is clamped at 100 mV.

This, in turn, holds the current limit reference at approximately

2 mV for the ADM1075-1 or 4 mV for the ADM1075-2. When

the FET is requested to turn on, the SS pin is held at ground

until the voltage between the SENSE+ and SENSE− pins

(V_SENSE) reaches the circuit breaker voltage, V_CB.

t

Figure 47. Interaction of Soft Start, Foldback, and ISET Current Limits

SETTING THE CURRENT LIMIT (ISET)

The maximum current limit is partially determined by selecting

a sense resistor to match the current sense voltage limit on the

controller for the desired load current. However, as currents

become larger, the sense resistor value becomes smaller and

resolution can be difficult to achieve when selecting the appropri-

ate sense resistor value. The ADM1075 provides an adjustable

sense voltage limit to deal with this issue. The device allows the

user to program the required current sense voltage limit from

15 mV to 25 mV for the ADM1075-1 and from 30 mV to 50 mV

for the ADM1075-2.

V

_CB= V_SENSECL− V_CBOS

When the load current generates a sense voltage equal to V_CB, a

10 μA current source is enabled, which charges the SS capacitor

and results in a linear ramping voltage on the SS pin. The

current limit reference also ramps up accordingly, allowing the

regulated load current to ramp up, while avoiding sudden

transients during power-up. The SS capacitor value is given by

The default value of 20 mV/40 mV is achieved by connecting

the ISET pin directly to the VCAP pin (VCAP > 1.65 V ISET

reference select threshold). This configures the device to use an

internal 1 V reference, which equates to 20 mV/40 mV at the

sense inputs (see Figure 48(a)).

I

_SS×t

C_SS

=

V_ISET

where I_SS= 10 μA, and t is the SS ramp time.

For example, a 10 nF capacitor gives a soft start time of 1 ms.

VCAP

Note that the SS voltage may intersect with the PLIM or

foldback (FLB) voltage, and the current limit reference may

change to follow PLIM (see Figure 47). This has minimal

impact on startup because the output voltage rises at a similar

rate to SS.

C1

R1

ISET

ADM1075

(PARTIAL)

ADM1075

(PARTIAL)

CONSTANT POWER FOLDBACK (PLIM)

Foldback is a method that actively reduces the current limit as

the voltage drop across the FET increases. It keeps the power

across the FET below the programmed value during power-up,

overcurrent, or short-circuit events. This allows a smaller FET

to be used, resulting in significant cost savings. The foldback

method employed is a constant power foldback scheme, meaning

power in the FET is held constant regardless of the V_DSof the

FET. This simplifies the task of ensuring that the FET is always

operating within the SOA region.

R2

VEE

(A)

(B)

Figure 48. (a) Fixed 20 mV/40 mV Current Sense Limit

(b) Adjustable 15 mV to 50 mV Current Sense Limit

To set the sense voltage in the 15 mV to 50 mV range, a resistor

divider is used to apply a reference voltage to the ISET pin (see

Figure 48(b)). The VCAP pin has a 2.7 V internally generated

voltage that can be used to set a voltage at the ISET pin.

The ADM1075 detects the voltage drop across the FET by

monitoring the voltage on the drain of the FET (via the PLIM

pin). The device relies on the principle that the source of the

FET is at the most negative expected supply voltage, and the

magnitude of the drain voltage is relative to that of the V_DSof

the FET. Using a resistor divider from the drain of the FET to

Rev. A | Page 22 of 52

Data Sheet

ADM1075

1000

100

10

the PLIM pin, the relationship of V_DSto V_PLIMcan be controlled.

The foldback voltage, V_FLB, is the input to the current limit

reference selector block and is defined as

1µs

10µs

V_FLB= 0.1/V_PLIM

100µs

1ms

The resistor divider should be designed to generate a V_FLB

voltage equal to I_SETwhen the V_DSof the FET (and thus V_PLIM

)

rises above the desired power level. If I_SET= 1 V, V_PLIMneeds to

be 0.1 V at the point where constant power takes over (V_FLB

MAX 200W

POWER

10ms

DC

=

DISSIPATION

I_SET). For example, to generate a 200 W constant power limit at

10 A current limit, the maximum V_DSis required to be 20 V at

the current limit. Therefore, the resistor divider must be 200:1

to generate a 0.1 V PLIM voltage at V_DS= 20 V. As V_PLIM

continues to increase, the current limit reference follows V_FLB

because it is now the lowest voltage input to the current limit

reference selector block. This results in a reduction of the

current limit, and, therefore, the regulated load current. To

prevent complete current flow restriction, a clamp becomes

active when the current limit reference reaches 100 mV. The

current limit cannot drop below this level. This 200 W constant

power example is illustrated in terms of FET SOA and real

scope plots in Figure 49 and Figure 50.

1

20V × 10A = 200W

60V × 3.33A = 200W

0.1

1

10

(V)

100

1000

V

DS

Figure 49. FET SOA

CURRENT LIMIT ADJUSTING

GATE

I

IN

3,4

VIN

When V_FLBhas control of the current limit reference, the

regulation current through the FET is

V

DS

200W CONSTANT POWER

I_D= V_FLB/(Gain × R_SENSE

)

where I_Dis the external FET drain current, and Gain is the sense

amplifier gain.

1,2

M1

I_D= 0.1/(V_PLIM× Gain × R_SENSE

)

Figure 50. 200 W Constant Power Scope Plot, CH1 = VIN; CH2 = V_DS

CH3 = GATE; CH4 = System Current; M1 = FET Power

;

I_D= 0.1/(V_DS× D × Gain × R_SENSE

)

where D is the resistor divider factor on PLIM.

TIMER

Therefore, the FET power is calculated as

The TIMER pin handles several timing functions with an

external capacitor, C_TIMER. There are two comparator thresholds:

V_TIMERH(1.0 V) and V_TIMERL(0.05 V). The four timing current

sources are a 3 ꢀA pull-up, a 60 ꢀA pull-up, a 2 ꢀA pull-down,

and a 100 ꢀA pull-down.

P

_FET= I_D× V_DS= 0.1/(D × Gain × R_SENSE)

Because P_FETdoes not have any dependency on V_DS, it remains

constant. Therefore, the FET power for a given system can be

set by adjusting the divider (D) driving the PLIM pin.

These current and voltage levels, together with the value of

C_TIMERchosen by the user, determine the initial timing cycle

time, the fault current limit time, and the hot swap retry duty

cycle. The TIMER capacitor value is determined using the

following equation:

The limits to the constant power system are when V_FLB> I_SET(or

1 V if V_ISET> V_ISETRSTH) or when V_FLB< 100 mV (100 mV max

clamp on V_CLREF). With an I_SETvoltage of 1 V, this gives a 10:1

foldback current range.

C_TIMER= (t_ON× 60 ꢀA)/V_TIMERH

where t_ONis the time that the FET is allowed to spend in

regulation. The choice of C_TIMERis based on matching this time

with the SOA requirements of the FET. Foldback can be used

here to simplify selection.

When V_INis connected to the backplane supply, the internal

supply of the ADM1075 must be charged up. A very short time

later when the internal supply is fully up and above the undervolt-

age lockout voltage (UVLO), the device comes out of reset.

During this first short reset period, the GATE and TIMER pins

are both held low. The ADM1075 then goes through an initial

Rev. A | Page 23 of 52

ADM1075

Data Sheet

timing cycle. The TIMER pin is pulled up with 3 ꢀA. When the

TIMER reaches the V_TIMERHthreshold (1.0 V), the first portion

of the initial cycle is complete. The 100 ꢀA current source then

pulls down the TIMER pin until it reaches V_TIMERL(0.05 V). The

initial cycle duration is related to C_TIMERby the following

equation:

The part can also be configured to autoretry an infinite number

of times with a 10 second cooling period between each retry.

LATCH RESTART

Connecting

to

means that the part makes

one hot swap attempt between each cooling period. Connecting

LATCH SHDN ALERT2 RESTART

to and GPO2/ to

means

that the part makes seven hot swap attempts between each

cooling period.

V

_TIMERH×C_TIMER(V_TIMERH−V_TIMERL)×C_TIMER

t_INITIAL

=

+

The duty cycle of the automatic retry cycle is set by the ratio of

2 μA/60 μA, which approximates to being on ~4% of the time.

The value of the timer capacitor determines the on time of this

cycle, which is calculated as follows:

3ꢀA

100ꢀA

For example, a 470 nF capacitor results in a power-up delay of

approximately 160 ms. Provided the UV and OV detectors are

inactive when the initial timing cycle terminates, the device is

ready to start a hot swap operation.

t

_ON= V_TIMERH× (C_TIMER/60 ꢀA)

_OFF= (V_TIMERH− V_TIMERL) × (C_TIMER/2 ꢀA)

When the voltage across the sense resistor reaches the circuit

breaker trip voltage, V_CB, the 60 μA timer pull-up current is

activated, and the gate begins to regulate the current at the current

limit. This initiates a ramp-up on the TIMER pin. If the sense

voltage falls below this circuit breaker trip voltage before the

TIMER pin reaches V_TIMERH(1.0 V), the 60 μA pull-up is

disabled, and the 2 μA pull-down is enabled.

A 470 nF capacitor on the TIMER pin gives ~8 ms of on time

(for example, to meet 10 ms SOA), and ~220 ms off time.

FAST RESPONSE TO SEVERE OVERCURRENT

The ADM1075 features a very fast detection circuit that quickly

responds to severe overcurrent events such as short circuits.

Such an event may cause catastrophic damage if not controlled

very quickly. A fast response circuit ensures that the ADM1075

detects an overcurrent event at approximately 150% of the normal

current limit (ISET) and responds and controls the current

within 1 μs in most cases. The severe overcurrent threshold

and glitch filter times are digitally programmable through the

PMBus. The threshold can be selected as 125%, 150%, 200%, or

225% of the normal current limit, and the glitch filter time can

be set to 200 ns, 900 ns, 10.7 ꢀs, or 57 ꢀs. This sets a maximum

response time of 300 ns, 950 ns, 13 ꢀs, or 60 ꢀs.

The circuit breaker trip voltage is not the same as the hot swap

sense voltage current limit. There is a small circuit breaker

offset, V_CBOS, which means that the timer actually starts a short

time before the current reaches the defined current limit.

However, if the overcurrent condition is continuous and the

sense voltage remains above the circuit breaker trip voltage, the

60 μA pull-up remains active and the FET remains in regulation.

This allows the TIMER pin to reach V_TIMERHand initiate the

GATE shutdown. The

pin is pulled low immediately.

LATCH

In latch-off mode, the TIMER pin is switched to the 2 μA pull-

LATCH

UV AND OV

down when it reaches the V_TIMERHthreshold. The

The ADM1075 monitors the supply voltage for undervoltage

(UV) and overvoltage (OV) conditions. The OV pin is con-

nected to the input of an internal voltage comparator, and its

voltage level is internally compared with a 1 V voltage reference.

The user can program the value of the OV hysteresis by varying

the top resistor of the resistor divider on the pin. This

impedance in combination with the 5 ꢀA OV hysteresis current

(current turned on after OV trips) sets the OV hysteresis

voltage.

remains low. While the TIMER pin is being pulled down, the

hot swap controller is kept off and cannot be turned back on.

When the voltage on the TIMER pin goes below the V_TIMERL

threshold, the hot swap controller can be reenabled by toggling

the UVx pin or by using the PMBus OPERATION command to

toggle the ON bit from on to off and then on again.

HOT SWAP FAULT RETRY

The ADM1075 turns off the FET after an overcurrent fault.

With the default pin configuration, the part latches off after an

R_TOP+ R_BOTTOM

OV_RISING= OV_THRESHOLD

×

R_BOTTOM

LATCH

overcurrent fault and

can then be reset by either a power cycling event or a low signal

SHDN RESTART

goes active low. This condition

OV_FALLING≈ OV_RISING−(R_TOP×5 ꢀA)

to either the

input or

input. It can also be

The UV detector is split into two separate pins, UVH and UVL.

The voltage on the UVH pin is compared internally to a 1 V

reference, whereas the UVL pin is compared to a 0.9 V reference.

Therefore, if the pins are tied together, the UV hysteresis is 100 mV.

The hysteresis can be adjusted by placing a resistor between

UVL and UVH.

reset by toggling the UVx pin, using the PMBus operation

command or the PMBus power cycle command.

LATCH

SHDN

pin, the part

If the

pin is connected to the

makes seven attempts to hot swap before latching off. In this

mode, the part uses the TIMER pin to time a delay between

each attempt. In this way, a large load capacitance can be

charged using consecutive current limit periods.

Figure 51 illustrates the positive voltage monitoring input

connection. An external resistor network divides the supply

voltage for monitoring. An undervoltage event is detected when

Rev. A | Page 24 of 52

Data Sheet

ADM1075

the voltage connected to the UVL pin falls below 0.9 V, and the

gate is shut down using the 10 mA pull-down device. The fault

is cleared after UVH pin rises above 1.0 V.

pin is used by the power-good circuitry to determine when

PWRGD

pin to limit current on the pin to 50 ꢀA. A 2 MΩ resistor is

suitable to limit the current in most cases.

can be asserted. A resistor is required on the DRAIN

Similarly, when an overvoltage event occurs and the voltage on

the OV pin exceeds 1 V, the gate is shut down using the 10 mA

pull-down device.

SPLYGD

The

output indicates when the input supply is within

–48V RTN (0V)

the programmed voltage window. This is an open-drain output.

An external pull-up resistor is required on this pin.

R

SHUNT

C1

LATCH

VIN

UVH

+

–

LATCH

The

output signals that the device has latched off after

1V

GATE

ENABLE

LOGIC

Q1

an overcurrent fault. This pin is also used to configure the

desired retry scheme. See the Hot Swap Fault Retry section for

additional details.

UVL

OV

+

–

0.9V

1V

SENSE+

SENSE–

–

+

R

SENSE

ADM1075

SHDN

VEE

SHDN

The

pin is a level-triggered input that allows the user to

command a shutdown of the hot swap function. When this

input is set low, the GATE output is switched to VEE to turn the

FET off. This pin has an internal pull-up of approximately 8 μA,

allowing it to be driven by an open-drain pull-down output or a

push-pull output. The input threshold is ~1 V.

–48V

Figure 51. Undervoltage and Overvoltage Supply Monitoring

The maximum rating on the UVH pin is 4 V and the UVH

threshold is 1 V. This limits the maximum input voltage to

minimum input voltage ratio to 4:1. For example, if the UVH

threshold is set at 20 V, the maximum input voltage is 80 V so

as not to exceed the maximum ratings of the pin. If a wider

input range is required, some protection circuitry is required

on the UV pins to limit them to less than 4 V.

This pin is also used to configure the desired retry scheme. See

the Hot Swap Fault Retry section for additional details.

SHDN

Care should be taken if using the

pin as an on/off pin.

low always turns off the gate. However,

high again turns on hot swap only if there have

been less than seven faults/shutdown events within a 10 second

SHDN

Pulling the

SHDN

taking

PWRGD

As shown in Figure 52, the

DRAIN pin voltage. It is an open-drain output that pulls low

when the voltage on DRAIN is less than 2 V and the GATE pin

voltage is near its 12 V rail (power good). When a fault occurs

or hot swap is turned off, the open-drain pull-down is disabled,

The

output indicates the status of the output voltage.

PWRGD

ALERT2

period. The retry scheme is configured to set GPO2/

output is derived from the

SHDN

low after seven faults. The

ALERT2

pin cannot clear the GPO2/

fault. The retry counter is cleared after 10 seconds of

power good. Therefore, this is not an issue if there is never

SHDN

going to be more than seven

period.

events within a 10 second

PWRGD

allowing

to go high (power bad).

is guaran-

teed to be in a valid state for V_IN≥ 1 V.

The UVH or UVL pin may work better as a system on/off pin if

required. Toggling the UVx pin clears any faults (including

I

=

DRAIN

FET

DRAIN

50µA MAX

ALERT2

GPO2/

low after seven retry attempts). A switch

R

DRAIN DRAIN

shorting UVH or UVL to VEE works as an on/off switch.

DIODE CLAMPS

DRAIN TO 2V

RESTART

2V

S

R

Q

RESTART

The

pin is a falling edge triggered input that allows

11V

PWRGD

the user to command a 10 second automatic restart. When this

input is set low, the gate turns off for 10 seconds, and then powers

back up. The pin is falling edge triggered; therefore, holding

GATE

HOT SWAP

DISABLE

SIGNAL

RESTART

low for more than 10 seconds generates only one

restart. This pin has an internal pull-up of approximately 8 μA,

allowing it to be driven by an open-drain pull-down output or a

push-pull output. The input threshold is ~1 V.

PWRGD

Figure 52. Generation of

Signal

DRAIN

Because the source of the FET is always at or near the most

negative system supply, the drain voltage is a close approxima-

tion to the V_DSof the FET. When the voltage at the DRAIN pin

is less than 2 V, it is assumed the FET is turned on. The DRAIN

This pin is also used to configure the desired retry scheme. See

the Hot Swap Fault Retry section for additional details.

Rev. A | Page 25 of 52

ADM1075

Data Sheet

command when the stop condition appears on the bus. In this

way, several devices can be triggered to sample at the same time.

FET HEALTH

The ADM1075 features a method of detecting a shorted pass

FET. The FET health status can be used to generate an alert on

ALERT1

When the GPO1/

/CONV pin is set to the convert

ALERT1

ALERT2

the GPO1/ /CONV and GPO2/

pins. By default,

ALERT1

(CONV) mode, an external hardware signal can be used to

trigger the single-shot sampling of one or more parts at the

same time.

at power-up, an alert is generated on GPO1/

the FET health status indicates a bad FET is present. FET health

is considered bad if all of the following conditions are true:

/CONV if

Each time a current sense and input voltage measurement is

taken, a power calculation is performed, multiplying the two

measurements together. This can be read from the device using

the READ_PIN command, returning the input power.

•

The ADM1075 is holding the FET off, for example, during

the initial power-on cycle time.

V_SENSE> 2 mV for the ADM1075-1 and 4 mV for the

ADM1075-2.

At the same time, the calculated power value is added to a

power accumulator register that may increment a rollover

counter if the value exceeds the maximum accumulator value,

and that also increments a power sample counter.

V_GATE< ~1 V.

POWER MONITOR

The ADM1075 features an integrated ADC that accurately

measures the current sense voltage and the ADC_V voltage.

It can also optionally monitor the ADC_AUX voltage. The

measured input voltage (ADC_V) and the current being

delivered to the load are multiplied to give a power value that

can be read back. Each power value is also added to an accumula-

tor that can be read back to allow an external device to calculate

the energy consumption of the load.

The power accumulator and power sample counter are read

back using the same READ_EIN command to ensure that the

accumulated value and sample count are from the same point in

time. The bus host reading the data assigns a timestamp to show

when the data is read. By calculating the time difference

between consecutive uses of READ_EIN and determining the

delta in power consumed, it is possible for the host to determine

the total energy consumed over that period.

The PEAK_IOUT, PEAK_VIN, and PEAK_VAUX commands

can be used to read the highest peak current or voltage since the

value was last cleared.

ISOLATION

Isolation is usually required in −48 V systems because there can

be a large voltage difference between different ground planes in

the system. The ADM1075 is referenced to −48 V, whereas the

MCU is usually referenced to 0 V. In almost all cases, the I²C

signals must be isolated. Any other ADM1075 digital input and

output signals that go to or come from the MCU must also be

isolated.

An averaging function is provided for voltage and current that

allows a number of samples to be averaged by the ADM1075.

This function reduces the need for postprocessing of sampled

data by the host processor. The number of samples that can be

averaged is 2^N, where N is in the range of 0 to 7.

The power monitor current sense amplifier is bipolar and can

measure both positive and negative currents. It has two input

ranges and can be selected using the PMBus interface. The

input ranges are 25 mV and 50 mV.

Analog Devices, Inc., provide a range of digital isolators using

iCoupler® technology. iCoupler technology is based on chip

scale transformers rather than the LEDs and photodiodes used

in optocouplers. The ADuM1250 is a dual I²C isolator and can

be used in conjunction with the ADM1075 for I²C isolation.

The two basic modes of operation for the power monitor are

single shot and continuous. In single-shot mode, the power

monitor samples the input voltage and current a number of

times, depending on the averaging value selected by the user.

The ADM1075 returns a single value corresponding to the

average voltage and current measured. When configured for

continuous mode, the power monitor continuously samples

voltage and current, making the most recent sample available

to be read. The ADC runs in continuous mode by default at

power-up.

–48V SIDE

(PRIMARY)

ISOLATED SIDE

(SECONDARY)

ADuM1250

VDD1

100nF

5V

VDD1

VDD2

5V_ISO

10kΩ

100nF

SDA_ISO

SDA

SDA2

SCL2

GND2

SCL2

SCL1

GND1

10kΩ

GND_ISO

–48V

SCL_ISO

SCL

–48V

GND_ISO

The single-shot mode can be triggered in a number of ways.

The simplest is by selecting the single-shot mode using the

PMON_CONFIG command and writing to the CONVERT bit

using the PMON_CONTROL command. The CONVERT bit

can also be written as part of a PMBus group command. Using a

group command allows multiple devices to be written to as part

of the same I²C bus transaction, with all devices executing the

Figure 53. ADuM1250 I²C Isolation

In cases where more digital signals need to be isolated, the

ADuM3200 is a dual-channel digital isolator whereas the

ADuM5404 is a quad-channel isolator with isoPower®, an

integrated, isolated dc-to-dc converter.

The ADuM1250 and ADuM3200 must be powered from both

the primary and secondary sides. The ADuM5404 only needs to

Rev. A | Page 26 of 52

Data Sheet

ADM1075

be powered from the secondary side and can provide power

across the isolation barrier via the integrated dc-to-dc

If a voltage rail is available on the primary side (3.3 V or 5 V

referenced to VEE), that can be used to power the chip directly.

Otherwise, the ADM1075 shunt voltage and/or the −48 V

supply can be regulated down to power the part. A simple

emitter follower circuit achieves this, as shown in Figure 54.

converter. Therefore, the ADuM5404 can be used to power the

primary side of the ADuM1250 if both are used on the board.

Some extra care is required if using the ADuM5404 to power

the ADuM3200. If the power at the secondary side is enabled by

the ADM1075, the isoPower solution may not work. Because

isoPower is unpowered in this case, the ADuM3200 outputs are

12V (SHUNT)

–48V RTN

1kΩ

0.33W

20kΩ

SHDN

in an undefined state. If the

input comes from the

ADuM3200, it may be held low, and the ADM1075 never turns

on the FET or enables power at the secondary side.

6V

20k

isoPower uses high frequency switching elements to transfer

power through its transformer. Special precautions must be

taken during printed circuit board (PCB) layout to meet

emissions standards. See the AN-0971 Application Note for

board layout recommendations.

5V AUX

1µF

–48V

Figure 54. Powering iCoupler from −48 V Supply

Powering the iCouplers from the secondary side is usually

straightforward because there is often a suitable voltage rail

available. However, there is not always a suitable voltage rail

available on the primary side (−48 V side). If the ADuM5404 is

not used on the system, the ADuM1250 can be powered on the

primary side in a number of different ways.

Rev. A | Page 27 of 52

ADM1075

Data Sheet

PMBus INTERFACE

The I²C bus is a common, simple serial bus used by many devices

to communicate. It defines the electrical specifications, the bus

timing, the physical layer, and some basic protocol rules.

SMBus PROTOCOL USAGE

All I²C transactions on the ADM1075 are performed using

SMBus defined bus protocols. The following SMBus protocols

are implemented by the ADM1075:

SMBus is based on I²C and aims to provide a more robust and

fault-tolerant bus. Functions such as bus timeout and packet

error checking are added to help achieve this robustness, along

with more specific definitions of the bus messages used to read

and write data to devices on the bus.

PMBus is layered on top of SMBus and, in turn, on I²C. Using the

SMBus defined bus messages, PMBus defines a set of standard

commands that can be used to control a device that is part of a

power chain.

•

Send byte

Receive byte

Write byte

Read byte

Write word

Read word

Block read

PACKET ERROR CHECKING

The ADM1075 command set is based upon the PMBus™ Power

System Management Protocol Specification, Part I and Part II,

Revision 1.2. This version of the standard is intended to provide

a common set of commands for communicating with dc-to-dc

type devices. However, many of the standard PMBus commands

can be mapped directly to the functions of a hot swap controller.

The ADM1075 PMBus interface supports the use of the packet

error checking (PEC) byte that is defined in the SMBus standard.

The PEC byte is transmitted by the ADM1075 during a read

transaction or sent by the bus host to the ADM1075 during a

write transaction. The ADM1075 supports the use of PEC with

all the SMBus protocols that it implements.

Part I and Part II of the PMBus standard describe the basic

commands and how they can be used in a typical PMBus setup.

The following sections describe how the PMBus standard and

the ADM1075 specific commands are used.

The use of the PEC byte is optional. The bus host can decide

whether to use the PEC byte with the ADM1075 on a message-

by-message basis. There is no need to enable or disable PEC in

the ADM1075.

DEVICE ADDRESSING

The PEC byte is used by the bus host or the ADM1075 to detect

errors during a bus transaction, depending on whether the trans-

action is a read or a write. If the host determines that the PEC

byte read during a read transaction is incorrect, it can decide to

repeat the read if necessary. If the ADM1075 determines that the

PEC byte sent during a write transaction is incorrect, it ignores

the command (does not execute it) and sets a status flag.

The ADM1075 is available in two models: the ADM1075-1 and

ADM1075-2. The PMBus address is seven bits in size. The

upper five bits (MSBs) of the address word are fixed and are

different for each model, as follows:

•

ADM1075-1: Base address is 00100xx (0x10)

ADM1075-2: Base address is 00110xx (0x18)

The ADM1075-1 and ADM1075-2 have a single ADR pin that

is used to select one of four possible addresses for a given

model. The ADR pin connection selects the lowest two bits

(LSBs) of the 7-bit address word (see Table 6).

Within a group command, the host can choose to send or not

send a PEC byte as part of the message to the ADM1075.

Table 6. PMBus Addresses and ADR Pin Connection

Value of Address LSBs

ADR Pin Connection

00

01

10

11

Connect to VEE

150 kΩ resistor to VEE

No connection (floating)

Connect to VCAP

Rev. A | Page 28 of 52

Data Sheet

ADM1075

R = read bit

SMBus MESSAGE FORMATS

W

= write bit

A = acknowledge bit (0)

Figure 55 to Figure 63 show all the SMBus protocols supported

by the ADM1075, along with the PEC variant. In these figures,

unshaded cells indicate that the bus host is actively driving the

bus; shaded cells indicate that the ADM1075 is driving the bus.

A

= acknowledge bit (1)

“A” represents the ACK (acknowledge) bit. The ACK bit is typi-

cally active low (Logic 0) if the transmitted byte is successfully

received by a device. However, when the receiving device is the

bus master, the acknowledge bit for the last byte read is a Logic 1,

Figure 55 to Figure 63 use the following abbreviations:

S = start condition

Sr = repeated start condition

P = stop condition

A

.

indicated by

S

SLAVE ADDRESS

W

A

DATA BYTE

A

P

PEC

A

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 55. Send Byte and Send Byte with PEC

S

SLAVE ADDRESS

R

A

DATA BYTE

A

P

PEC

A

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 56. Receive Byte and Receive Byte with PEC

S

SLAVE ADDRESS

W

A

COMMAND CODE

A

DATA BYTE

A

P

PEC

A

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 57. Write Byte and Write Byte with PEC

R

DATA BYTE

A

P

S

SLAVE ADDRESS

W

A

COMMAND CODE

A

SLAVE ADDRESS

Sr

A

PEC

A

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 58. Read Byte and Read Byte with PEC

A

DATA BYTE HIGH

A

P

S

SLAVE ADDRESS

W

A

COMMAND CODE

A

DATA BYTE LOW

S

W

PEC

A

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 59. Write Word and Write Word with PEC

DATA BYTE LOW

A

S

SLAVE ADDRESS

DATA BYTE HIGH

W

P

A

COMMAND CODE

A

Sr

SLAVE ADDRESS

R

A

SLAVE ADDRESS

DATA BYTE HIGH

W

COMMAND CODE

A

Sr

SLAVE ADDRESS

PEC

A

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 60. Read Word and Read Word with PEC

Rev. A | Page 29 of 52

ADM1075

Data Sheet

BYTE COUNT = N

A

S

SLAVE ADDRESS

DATA BYTE 1

W

A

COMMAND CODE

A

Sr

SLAVE ADDRESS

DATA BYTE N

R

A

DATA BYTE 2

A

P

S

SLAVE ADDRESS

DATA BYTE 1

COMMAND CODE

SLAVE ADDRESS

DATA BYTE N

R

DATA BYTE 2

A

PEC

A

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 61. Block Read and Block Read with PEC

ONE OR MORE DATA BYTES

S

DEVICE 1 ADDRESS

DEVICE 2 ADDRESS

DEVICE N ADDRESS

W

A

COMMAND CODE 1

COMMAND CODE 2

COMMAND CODE N

A

LOW DATA BYTE

A

HIGH DATA BYTE

A

ONE OR MORE DATA BYTES

Sr

LOW DATA BYTE

A

HIGH DATA BYTE

A

ONE OR MORE DATA BYTES

LOW DATA BYTE

A

HIGH DATA BYTE

P

MASTER TO SLAVE

SLAVE TO MASTER

Figure 62. Group Command

ONE OR MORE DATA BYTES

S

DEVICE 1 ADDRESS

DEVICE 2 ADDRESS

DEVICE N ADDRESS

W

A

COMMAND CODE 1

COMMAND CODE 2

COMMAND CODE N

A

LOW DATA BYTE

A

HIGH DATA BYTE

A

PEC 1

PEC 2

PEC N

A

ONE OR MORE DATA BYTES

Sr

LOW DATA BYTE

A

HIGH DATA BYTE

ONE OR MORE DATA BYTES

LOW DATA BYTE

A

HIGH DATA BYTE

P

A

MASTER TO SLAVE

SLAVE TO MASTER

Figure 63. Group Command with PEC

A group command differs from a nongroup command in that,

after the data is written to one slave device, a repeated start

condition is put on the bus followed by the address of the next

slave device and data. This continues until all the devices have

been written to, at which point the stop condition is put on the

bus by the master device.

GROUP COMMANDS

The PMBus standard defines what are known as group

commands. Group commands are single bus transactions that

send commands or data to more than one device at the same

time. Each device is addressed separately, using its own address;

there is no special group command address. A group command

transaction can contain only write commands that send data to

a device. It is not possible to use a group command to read data

from devices.

The format of a group command and a group command with

PEC is shown in Figure 63.

Each device that is written to as part of the group command

does not immediately execute the command written. The device

must wait until the stop condition appears on the bus. At that

point, all devices execute their commands at the same time.

From an I²C protocol point of view, a normal write command

consists of the following:

•

I²C start condition

Slave address bits and a write bit (followed by ACK from

the slave device)

Using a group command, it is possible, for example, to turn

multiple PMBus devices on or off at the same time. In the case

of the ADM1075, it is also possible to issue a power monitor

command that initiates a conversion, causing multiple ADM1075

devices to sample together at the same time. This is analogous

•

One or more data bytes (each of which is followed by ACK

from the slave device)

I²C stop condition to end the transaction

ALERT1

to connecting the GPO1/

/CONV pins together and

configuring the pin in the convert (CONV) mode to drive the

power monitor sampling.

Rev. A | Page 30 of 52

Data Sheet

ADM1075

POWER_CYCLE Command

HOT SWAP CONTROL COMMANDS

The POWER_CYCLE command can be used to request that

the ADM1075 be turned off for ~10 seconds and then back on.

This command can be useful if the processor that controls the

ADM1075 is also powered off when the part is turned off. This

command allows the processor to request that the ADM1075 turn

off and back on again as part of a single command.

OPERATION Command

The GATE pin that drives the FET is controlled by a dedicated

hot swap state machine. The UVH, UVL, and OV input pins,

along with the TIMER and SS pins and the current sense, all

feed into the state machine and control when and how strongly

the gate is turned off.

ADM1075 INFORMATION COMMANDS

CAPABILITY Command

It is also possible to control the hot swap GATE output using

commands over the PMBus interface. The OPERATION com-

mand can be used to request the hot swap output to turn on.

However, if the UV pin indicates that the input supply is less

than required, the hot swap output is not turned on, even if the

OPERATION command indicates that the output should be

enabled.

The CAPABILITY command can be used by host processors

to determine the I²C bus features supported by the ADM1075.

The features reported are the maximum bus speed and whether

the device supports the packet error checking (PEC) byte and

the SMBAlert reporting function.

If the OPERATION command is used to disable the hot swap

output, the GATE pin is held low, even if all hot swap state

machine control inputs indicate that it can be enabled.

PMBUS_REVISION Command

The PMBUS_REVISION command reports the version of Part I

and Part II of the PMBus standard.

The default state of the OPERATION command ON bit is 1;

therefore, the hot swap output is always enabled when the

ADM1075 comes out of UVLO. If the ON bit is never changed,

the UV input is the hot swap master on/off control signal.

MFR_ID, MFR_MODEL, and MFR_REVISION Commands

The MFR_ID, MFR_MODEL, and MFR_REVISION

commands return ASCII strings that can be used to facilitate

detection and identification of the ADM1075 on the bus.

By default, at power-up, the OPERATION command is disabled

and must be enabled using the DEVICE_CONFIG command.

This prevents inadvertent shutdowns of the hot swap controller

by software.

These commands are read using the SMBus block read message

type. This message type requires that the ADM1075 return a

byte count corresponding to the length of the string data that is

to be read back.

If the ON bit is set to 0 while the UV signal is high, the hot swap

output is turned off. If the UV signal is low or if the OV signal is

high, the hot swap output is already off and the status of the ON

bit has no effect.

STATUS COMMANDS

The ADM1075 provides a number of status bits that are used

to report faults and warnings from the hot swap controller and

the power monitor. These status bits are located in six different

registers that are arranged in a hierarchy. The STATUS_BYTE

and STATUS_WORD commands provide eight bits and 16 bits

of high level information, respectively. The STATUS_BYTE and

STATUS_WORD commands contain the most important status

bits, as well as pointer bits that indicate whether any of the four

other status registers need to be read for more detailed status

information.

If the ON bit is set to 1, the hot swap output is requested to turn

on. If the UV signal is low or if the OV signal is high, setting the

ON bit to 1 has no effect, and the hot swap output remains off.

It is possible to determine at any time whether the hot swap output

is enabled using the STATUS_BYTE or the STATUS_WORD

command (see the Status Commands section).

The OPERATION command can also be used to clear any latched

faults in the status registers. To clear latched faults, set the ON

bit to 0, and then reset it to 1.

In the ADM1075, a particular distinction is made between

faults and warnings. A fault is always generated by the hot swap

controller and is defined by hardware component values. Three

events can generate a fault.

DEVICE_CONFIG Command

The DEVICE_CONFIG command is used to configure certain

settings within the ADM1075, for example, to modify the

duration of the severe overcurrent glitch filter and to set the trip

threshold. This command is also used to configure the polarity

of the second IOUT current warnings.

•

Overcurrent condition that causes the hot swap timer to

time out

•

Overvoltage condition on the OV pin

Undervoltage condition on the UVx pin

At power-up, the OPERATION command is disabled, and

the ADM1075 responds with a NACK if the OPERATION

command is received. To allow use of the OPERATION

command, the OPERATION_CMD_EN bit must be set

using the DEVICE_CONFIG command.

When a fault occurs, the hot swap controller always takes some

action, usually to turn off the GATE pin, which is driving the

FET. A fault can also generate an SMBAlert on one or both of

ALERTx

the GPOx/

pins.

Rev. A | Page 31 of 52

ADM1075

Data Sheet

All warnings in the ADM1075 are generated by the power

monitor sampling voltage and current and then comparing

these measurements to the threshold values set by the various

limit commands. A warning has no effect on the hot swap

controller, but it may generate an SMBAlert on one or both of

GPO AND ALERT PIN SETUP COMMANDS

Two multipurpose pins are provided on the ADM1075:

ALERT1 ALERT2

GPO1/

The GPO1/

/CONV and GPO2/

ALERT1

.

ALERT2

/CONV and GPO2/

pins have

two output modes of operation. These pins can be configured

independently over the PMBus as general-purpose digital

outputs. They can both be configured to generate an SMBAlert

when one or more fault/warning status bits become active in the

PMBus status registers. For an example of how to configure these

pins to generate an SMBAlert and how to respond and clear the

condition, see the Example Use of SMBus Alert Response

Address section.

ALERTx

the GPOx/

output pins.

When a fault or warning status bit is set, it always means that the

status condition—fault or warning—is active or was active at

some point in the past. When a fault or warning bit is set, it is

latched until it is explicitly cleared using either the OPERATION

or the CLEAR_FAULTS command. Some other status bits are

live, that is, they always reflect a status condition and are never

latched.

ALERT1

The GPO1/

/CONV pin can also be configured as an

STATUS_BYTE and STATUS_WORD Commands

input (CONV) to drive the power monitor in single-shot run

mode and to control when a power monitor ADC sampling

cycle begins. This function can be used to synchronize sampling

across multiple ADM1075 devices, if required.

The STATUS_BYTE and STATUS_WORD commands can

be used to obtain a snapshot of the overall part status. These

commands indicate whether it is necessary to read more

detailed information using the other status commands.

ALERT1_CONFIG and ALERT2_CONFIG Commands

The low byte of the word returned by the STATUS_WORD

command is the same byte returned by the STATUS_BYTE

command. The high byte of the word returned by the STATUS_

WORD command provides a number of bits that can be used to

determine which of the other status commands must be issued

to obtain all active status bits.

Using combinations of bit masks, the ALERT1_CONFIG and

ALERT2_CONFIG commands can be used to select the status

bits that, when set, generate an SMBAlert signal to a processor.

They can also be used to set a GPO mode on the pin, so that it

is under software control. If this mode is set, the SMBAlert

masking bits are ignored.

STATUS_INPUT Command

On the ADM1075, one of the inputs can also be configured

as a hardware-based convert control signal. If this mode is set,

the GPO and SMBAlert masking bits are ignored.

The STATUS_INPUT command returns a number of bits

relating to voltage faults and warnings and power warnings on

the input supply.

POWER MONITOR COMMANDS

STATUS_IOUT Command

The ADM1075 provides a high accuracy, 12-bit current and

voltage power monitor. The power monitor can be configured

in a number of different modes of operation and can run in

either continuous mode or single-shot mode with a number

of different sample averaging options.

The STATUS_IOUT command returns a number of bits

relating to current faults and warnings on the output supply.

STATUS_VAUX Command

The STATUS_VAUX command returns a number of bits

relating to current faults and warnings on the output supply.

The power monitor can measure the following:

STATUS_MFR_SPECIFIC Command

•

Input voltage (VIN)

Output current (IOUT)

Auxiliary voltage (VAUX)

The STATUS_MFR_SPECIFIC command is a standard PMBus

command, but the contents of the byte returned is specific to

the ADM1075.

The following quantities are then calculated:

CLEAR_FAULTS Command

•

Input power (PIN)

Input energy (EIN)

The CLEAR_FAULTS command is used to clear fault and

warnings bits when they are set. Fault and warnings bits are

latched when they are set. In this way, a host can read the bits

any time after the fault or warning condition occurs and

determine which problem actually occurred.

PMON_CONFIG Command

The power monitor can run in a number of different modes with

different input voltage range settings. The PMON_CONFIG

command is used to set up the power monitor.

If the CLEAR_FAULTS command is issued and the fault or warn-

ing condition is no longer active, the status bit is cleared. If the

condition is still active—for example, if an input voltage is below

the undervoltage threshold of the UV pin—the CLEAR_FAULTS

command attempts to clear the status bit, but that status bit is

immediately set again.

Rev. A | Page 32 of 52

Data Sheet

ADM1075

The settings that can be configured are as follows:

These registers can be read back using one of two commands,

depending on the level of accuracy required for the energy

accumulator and the desire to limit the frequency of reads from

the ADM1075.

•

Single-shot or continuous sampling

Enable VAUX sampling

Current input range

A bus host can read these values, and, using some difference

calculations, determine the amount of energy consumed since

the last read and the number of samples in that time. The bus

host, using an external real-time clock, can then determine the

power used in the last time period.

Current and voltage sample averaging

Modifying the power monitor settings while the power monitor

is sampling is not recommended because it may cause spurious

data or warnings to be generated.

PMON_CONTROL Command

To avoid the loss of data, the bus host must read at a rate that

ensures the rollover counter does not wrap around more than

once and, if it does wrap around, that the next rollover value is

less than the previous one.

Power monitor sampling can be initiated via software or via

hardware, as follows:

•

PMON_CONTROL command. This command can be

used with single-shot or continuous mode.

The READ_EIN command returns the top 16 bits of the energy

accumulator, the lower eight bits of the rollover counter, and the

full 24 bits of the sample counter.

ALERT1

•

GPO1/

/CONV pin. If this pin is configured for

convert mode, an external hardware signal can be used to

take this pin high, triggering the single-shot sampling of

one or more parts together.

The READ_EIN_EXT command returns the full 24 bits of the

energy accumulator, the full 16 bits of the rollover counter, and

the full 24 bits of the sample counter. The use of the longer

rollover counter means that the time interval between reads of

the part to ensure that no data is lost can be increased from

seconds to minutes.

READ_VIN, READ_VAUX, and READ_IOUT Commands

The ADM1075 power monitor measures the voltage developed

across the sense resistor to provide a current measurement. The

input voltage from the ADC_V pin is always measured, and the

user can choose whether or not to measure the output voltage

present on the ADC_AUX pin as well.

PEAK_IOUT, PEAK_VIN, PEAK_VAUX, and PEAK_PIN

Commands

In addition to the standard PMBus commands for reading

voltage and current, the ADM1075 provides commands that

can report the maximum peak voltage, current, or power value

since the peak value was last cleared.

READ_PIN, READ_PIN_EXT, READ_EIN, and

READ_EIN_EXT Commands

The VIN input voltage (12-bit) and IOUT current (12-bit)

measurement values are multiplied by the ADM1075 to give the

input power value. This is done using fixed point arithmetic and

produces a 24-bit value. It is assumed that the numbers are of

the 12.0 format, meaning there is no fractional part. It should

be noted that only positive IOUT values are used to avoid

returning a negative power.

The peak values are updated only after the power monitor has

sampled and averaged the current and voltage measurements.

Individual peak values are cleared by writing a 0 value with the

corresponding commands.

WARNING LIMIT SETUP COMMANDS

This 24-bit value can be read from the ADM1075 using the

READ_PIN_EXT command, where the most significant bit

(MSB) is always a zero because PIN_EXT is a twos complement

binary value that is always positive.

The ADM1075 power monitor can monitor a number of

different warning conditions simultaneously and report any

current or voltage values that exceed the user-defined

thresholds using the status commands.

The 16 most significant bits of the 24-bit value are used as the

value for input power (PIN). The MSB of the 16-bit PIN word is

always zero because PIN is a twos complement binary value that

is always positive.

All comparisons performed by the power monitor require the

measured voltage or current value to be strictly greater or less

than the threshold value.

At power-up, all threshold limits are set to either minimum

scale (for undervoltage or undercurrent conditions) or to

maximum scale (for overvoltage, overcurrent or overpower

conditions). This effectively disables the generation of any

status warnings by default; warning bits are not set in the status

registers until the user explicitly sets the threshold values.

Each time a power calculation is performed, the 24-bit power

value is added to a 24-bit energy accumulator register. This is a

twos complement representation as well; therefore, the MSB is

always zero. Each time this energy accumulator register rolls

over from 0x7FFFFF to 0x000000, a 16-bit rollover counter is

incremented. The rollover counter is straight binary, with a

maximum value of 0xFFFF before it rolls over.

VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT

Commands

There is also a 24-bit straight binary power sample counter that

is incremented by one each time a power value is calculated and

added to the energy accumulator.

The VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT

commands are used to set the OV and UV thresholds on the

input voltage, as measured at the ADC_V pin.

Rev. A | Page 33 of 52

ADM1075

Data Sheet

VAUX_OV_WARN_LIMIT and VAUX_UV_WARN_LIMIT

Commands

The sense resistor value used in the calculations to obtain the

coefficients is expressed in milliohms. The m coefficients are

defined as 2-byte twos complement numbers in the PMBus stand-

ard; therefore, the maximum positive value that can be represented

is 32,767. If the m value is greater than that, and is to be stored

in PMBus standard form, the m coefficients should be divided

by 10, and the R coefficient increased by a value of 1. For example,

if performing a power calculation on the ADM1075-1 with a

10 mꢁ sense resistor, the m coefficient is 8549, and the R

coefficient is 0.

The VAUX_OV_WARN_LIMIT and VAUX_UV_WARN_

LIMIT commands are used to set the OV and UV thresholds

on the output voltage, as measured at the ADC_VAUX pin on

the ADM1075.

PIN_OP_WARN_LIMIT Command

The PIN_OP_WARN_LIMIT command is used to set the

overpower (OP) threshold for the power measurement register.

IOUT_OC_WARN_LIMIT Command

Example 1

The IOUT_OC_WARN_LIMIT command is used to set the

overcurrent (OC) threshold for the current flowing through the

sense resistor.

IOUT_OC_WARN_LIMIT requires a current limit value

expressed in direct format.

If the required current limit is 10 A, and the sense resistor is

2 mꢁ, the first step is to determine the voltage coefficient. For

an ADM1075-1, this is simply m = 806 × 2, giving 1612.

IOUT_WARN2_LIMIT Command

The IOUT_WARN2_LIMIT command provides a second

current warning threshold that can be programmed. The

polarity of this warning can be set to overcurrent or

undercurrent using the DEVICE_CONFIG command.

Using Equation 1, and expressing X, in units of amps,

Y = ((1612 × 10) + 20,475) × 10⁻¹

Y = 3659.5 = 3660 (rounded up to integer form)

PMBus DIRECT FORMAT CONVERSION

Writing a value of 3660 with the IOUT_OC_WARN_LIMIT

command sets an overcurrent warning at 10 A.

The ADM1075 uses the PMBus direct format internally to

represent real-world quantities such as voltage, current, and

power values. A direct format number takes the form of a

2-byte, twos complement binary integer value.

Example 2

The READ_IOUT command returns a direct format value of 3341,

representing the current flowing through a sense resistor of 1 mꢁ.

It is possible to convert between direct format value and real-world

quantities using the following equations. Equation 1 converts from

real-world quantities to PMBus direct values, and Equation 2

converts PMBus direct format values to real-world values.

To convert this value to the current flowing, use Equation 2,

with m = 806 × 1 (for the ADM1075-1):

X = 1/806 × (3341 × 10¹– 20,475)

Y = (mX + b) × 10^R

X = 1/m × (Y × 10^−R− b)

(1)

(2)

X = 16.05 A

This means that when READ_IOUT returns a value of 3341,

16.05 A is flowing in the sense resistor.

where:

Y is the value in PMBus direct format.

X is the real-world value.

m is the slope coefficient, a 2-byte, twos complement integer.

b is the offset, a 2-byte, twos complement integer.

R is a scaling exponent, a 1-byte, twos complement integer.

Note the following:

•

The same calculations that are used to convert power

values also apply to the energy accumulator value returned

by the READ_EIN command because the energy

accumulator is a summation of multiple power values.

The same equations are used for voltage, current, and power

conversions, the only difference being the values of the m, b,

and R coefficients used.

•

The READ_PIN_EXT and READ_EIN_EXT commands

return 24-bit extended precision versions of the 16-bit

values returned by READ_PIN and READ_EIN. The direct

format values must be divided by 256 prior to being con-

verted with the coefficients shown in Table 7.

Table 7 lists all the coefficients required for the ADM1075. The

coefficients shown are dependent on the value of the external

sense resistor used in a given application. This means that an

additional calculation must be performed to take the sense

resistor value into account to obtain the coefficients for a

specific sense resistor value. The resistor divider scaling factor

on VIN/VAUX also needs to be taken into account when

performing a voltage or power calculation (see Example 4).

Rev. A | Page 34 of 52

Data Sheet

ADM1075

Table 7. PMBus Conversion to Real-World Coefficients

Current (A)

ADM1075-2

Power (W)—Resistor Scaled

Coefficient

Voltage (V)

ADM1075-1

806 × R_SENSE

20,475

ADM1075-1

ADM1075-2

m

b

R

27,169

0

−1

404 × R_SENSE

20,475

−1

8549 × R_SENSE

4279 × R_SENSE

0

−1

0

−1

Example 3

To convert an ADC code to current in amperes, the following

formulas can be used:

The READ_VIN command returns a direct format value of 1726.

The ADC_V pin is shorted to the OV pin, which is connected

to the input supply via an 820 kΩ/11 kΩ resistor divider.

V

_SENSE= LSB_xmV× (I_ADC− 2048)

_OUT= V_SENSE/(R_SENSE× 0.001)

where:

I

To convert this value to the input voltage, use Equation 2

X = 1/27,169 × (1726 × 10¹– 0)

X = 0.635 V

V

_SENSE= (V_SENSE+) − (V_SENSE−).

LSB_25mV= 12.4 μV.

LSB_50mV= 24.77 μV.

This corresponds to 0.635 V at the ADC_V pin. To obtain the

input voltage, this must be amplified by the resistor divider ratio,

I

_ADCis the 12-bit ADC code.

I_OUTis the measured current value in amperes.

X = 0.635 V × (820 kΩ + 11 kΩ)/11 kΩ = 47.99 V

R

_SENSEis the value of the sense resistor in milliohms.

Example 4

To convert an ADC code to a voltage, the following formula can

be used:

The PIN_OP_WARN_LIMIT command requires a power limit

value expressed in direct format.

V_M= LSB_INPUTV× (V_ADC+ 0.5)

If the required power limit is 350 W and the sense resistor is

1 mꢁ, the first step is to determine the m coefficient. Assuming

an ADM1075-1 device, m = 8549 × 1 = 8549. The resistor

divider on VIN scales down the power limit referenced to the

ADC input. Assuming a 49 kꢁ and 1 kꢁ resistor divider on

VIN, this gives a scaling factor of 0.02.

where:

V_Mis the measured value in volts.

V

_ADCis the 12-bit ADC code.

LSB_INPUTV= 368 ꢀV.

To convert a current in amperes to a 12-bit value, the following

formulas can be used (round the result to the nearest integer):

Using Equation 1,

V

_SENSE= I_A× R_SENSE× 0.001

_CODE= 2048 + (V_SENSE/LSB_xmV

where:

_SENSE= (V_SENSE+) − (V_SENSE−).

I_Ais the current value in amperes.

_SENSEis the value of the sense resistor in milliohms.

_CODEis the 12-bit ADC code.

Y = (8549 × (350 × 0.02)) × 10⁻¹

I

)

Y = 5984.3 = 5984 (rounded to the nearest integer)

Writing a value of 5984 with the PIN_OP_WARN_LIMIT

command sets an overpower warning at 350 W.

V

R

VOLTAGE AND CURRENT CONVERSION USING

LSB VALUES

I

LSB_25mV= 12.4 μV.

LSB_50mV= 24.77 μV.

The direct format voltage and current values returned by the

READ_VIN, READ_VAUX, and READ_IOUT commands, and

the corresponding peak versions are the actual data output

directly from the ADM1075 ADC. Because the voltages and

currents are a 12-bit ADC output code, they can also be

converted to real-world values with knowledge of the size of the

LSB on the ADC.

To convert a voltage to a 12-bit value, the following formula can

be used (round the result to the nearest integer):

V

_CODE= (V_A/LSB_INPUTV) − 0.5

where:

V

_CODEis the 12-bit ADC code.

The m, b, and R coefficients defined for the PMBus conversion

are required to be whole integers by the standard and have

therefore been rounded off slightly. Using this alternative

method, with the exact LSB values, can provide slightly more

accurate numerical conversions.

V_Ais the voltage value in volts.

LSB_INPUTV= 368 ꢀV.

Rev. A | Page 35 of 52

ADM1075

Data Sheet

ADM1075 ALERT PIN BEHAVIOR

The ADM1075 provides a very flexible alert system, whereby

one or more fault/warning conditions can be indicated to an

external device.

ALERTx

By default, at power-up, the open-drain GPOx/

outputs are high impedance; therefore, the pins can be pulled

high through resistors. No faults or warnings are enabled on the

ALERT2

GPO2/

pin at power-up; the user must explicitly enable

FAULTS AND WARNINGS

the faults or warnings to be monitored. The FET health bad

warning is active by default on the GPO1/

at power-up.

A PMBus fault on the ADM1075 is always generated due to an

analog event and causes a change in state in the hot swap output,

turning it off. The three defined fault sources are as follows:

ALERT1

/CONV pin

Any one or more of the faults and warnings listed in the Faults

and Warnings section can be enabled and cause an alert, making

the corresponding GPOx/

•

Undervoltage (UV) event detected on the UVH and UVL

pins

ALERTx

pin active. By default, the

pin is low.

ALERT1

•

Overvoltage (OV) event detected on the OV pin

Overcurrent (OC) event that causes a hot swap timeout

ALERTx

active state of a GPOx/

For example, to use GPO1/

IOUT OC warning from the ADC, the followings steps must be

performed:

/CONV to monitor the

Faults are continuously monitored, and, as long as power is

applied to the device, they cannot be disabled. When a fault

occurs, a corresponding status bit is set in one or more

STATUS_xxx registers.

1. Set a threshold level with the IOUT_OC_WARN_LIMIT

command.

2. Set the IOUT_OC_WARN_EN1 bit in the

ALERT1_CONFIG register

A value of 1 in a status register bit field always indicates a fault

or warning condition. Fault and warning bits in the status

registers are latched when set to 1. To clear a latched bit to 0—

provided that the fault condition is no longer active—use the

CLEAR_FAULTS command or use the OPERATION command

to turn the hot swap output off and then on again.

3. Start the power monitor sampling on IOUT.

If an IOUT sample is taken that is above the configured

IOUT OC value, the GPO1/

ALERT1

/CONV pin is taken

low, signaling an interrupt to a processor.

HANDLING/CLEARING AN ALERT

When faults/warnings are configured on the GPOx/

the pins become active to signal an interrupt to the processor.

(These pins are active low, unless inversion is enabled.) The

The latched status registers provide fault recording functionality.

In the event of a fault, the HS_SHUTDOWN_CAUSE bits in

the manufacturing specific status register (0x80) can be used to

identify the fault source (UV, OV, or OC). Other status registers

can also be checked for more fault and warning information.

ALERTx

pins,

A warning is less severe than a fault and never causes a change

in the state of the hot swap controller. The eight sources of a

warning are defined as follows:

ALERTx

GPOx/

signal performs the function of an SMBAlert.

ALERTx

Note that the GPOx/

dently of each other, but they are always made inactive together.

pins can become active indepen-

•

CML: a communications error occurred on the I²C bus

HS timer was active (HSTA): the current regulation was

active but does not necessarily shut the system down

IOUT OC warning from the ADC

A processor can respond to the interrupt in one of two basic ways:

•

If there is only one device on the bus, the processor can

simply read the status bytes and issue a CLEAR_FAULTS

command to clear all the status bits, which causes the

•

IOUT Warning 2 from the ADC

ALERTx

deassertion of the GPOx/

line. If there is a persistent

VIN UV warning from the ADC

fault—for example, an undervoltage on the input—the status

bits remain set after the CLEAR_FAULTS command is

executed because the fault has not been removed. However,

VIN OV warning from the ADC

VAUX UV warning from the ADC

VAUX OV warning from the ADC

ALERTx

the GPOx/

line is not pulled low unless a new fault/

PIN OP warning from the ADC

warning becomes active. If the cause of the SMBAlert is a

power monitor generated warning and the power monitor

is running continuously, the next sample generates a new

SMBAlert after the CLEAR_FAULTS command is issued.

If there are many devices on the bus, the processor can issue

an SMBus alert response address command to find out

which device asserted the SMBAlert line. The processor

can read the status bytes from that device and issue a

CLEAR_FAULTS command.

GENERATING AN ALERT

A host device can periodically poll the ADM1075 using the

status commands to determine whether a fault/warning is

active. However, this polling is very inefficient in terms of

software and processor resources. The ADM1075 has two

•

ALERTx

GPOx/

interrupts to a host processor, GPO1/

ALERT2

output pins that can be used to generate

ALERT1

/CONV and

GPO2/

.

Rev. A | Page 36 of 52

Data Sheet

ADM1075

4. If there are no other active alerts from devices with lower

SMBus ALERT RESPONSE ADDRESS

2

ALERT1

I C addresses, this device makes the GPO1/

/CONV

The SMBus alert response address (ARA) is a special address

that can be used by the bus host to locate any devices that need

to talk to it. A host typically uses a hardware interrupt pin to

monitor the SMBus alert pins of a number of devices. When the

host interrupt occurs, the host issues a message on the bus using

the SMBus receive byte or receive byte with PEC protocol.

ALERT2

or GPO2/

pin inactive (high) during the NACK

bit period after it sends its address to the host processor.

ALERT1 ALERT2

pin stays

5. If the GPO1/

/CONV or GPO2/

low, the host processor must continue to issue SMBus alert

response address commands to devices to find out the

addresses of all devices whose status it must check.

The special address used by the host is 0x0C. Any devices that

have an SMBAlert signal return their own 7-bit address as the

seven MSBs of the data byte. The LSB value is not used and can

be either 1 or 0. The host reads the device address from the

received data byte and proceeds to handle the alert condition.

ALERT1

6. The ADM1075 continues to operate with the GPO1/

/

ALERT2

CONV or GPO2/

pin inactive and the contents of

the status bytes unchanged until the host reads the status

bytes and clears them, or until a new fault occurs. That is, if

a status bit for a fault/warning that is enabled on the

More than one device may have an active SMBAlert signal and

attempt to communicate with the host. In this case, the device

with the lowest address dominates the bus and succeeds in

transmitting its address to the host. The device that succeeds

disables its SMBusAlert signal. If the host sees that the SMBus

alert signal is still low, it continues to read addresses until all

devices that need to talk to it have successfully transmitted their

addresses.

ALERT1

ALERT2

GPO1/

/CONV or GPO2/

pin and that

was not already active (equal to 1) goes from 0 to 1, a new

alert is generated, causing the GPO1/

ALERT2

ALERT1

pin to become active again.

/CONV or

GPO2/

DIGITAL COMPARATOR MODE

ALERT1

ALERT2

/CONV and GPO2/

The GPO1/

pins can be

configured to indicate if a user defined threshold for voltage,

current, or power is being exceeded. In this mode, the output

pin is live and is not latched when a warning threshold is

exceeded. In effect, the pin acts as a digital comparator where

the threshold is set using the warning limit threshold commands.

EXAMPLE USE OF SMBus ALERT RESPONSE

ADDRESS

The full sequence of steps that occurs when an SMBAlert is

generated and cleared is as follows:

The ALERTx_CONFIG command is used, as for the SMBAlert

configuration, to select the specific warning threshold to be

1. A fault or warning is enabled using the ALERT1_CONFIG

command, and the corresponding status bit for the fault or

warning goes from 0 to 1, indicating that the fault/warning

has just become active.

ALERT1

ALERT2

/CONV or GPO2/

monitored. The GPO1/

then indicates if the measured value is above or below the

threshold.

ALERT1

ALERT2

2. The GPO1/

/CONV or GPO2/

becomes active (low) to signal that an SMBAlert is active.

3. The host processor issues an SMBus alert response address

to determine which device has an active alert.

Rev. A | Page 37 of 52

ADM1075

Data Sheet

PMBus COMMAND REFERENCE

Register addresses are in hexadecimal format.

Table 8. PMBus Command Summary

Command Code

Command Name

SMBus Transaction Type

Read/write byte

Send byte

Number of Data Bytes

Reset

0x01

OPERATION

1

0x00

0x03

CLEAR_FAULTS

CAPABILITY

0

Not applicable

0xB0

0x19

Read byte

1

0x4A

0x57

IOUT_OC_WARN_LIMIT

VIN_OV_WARN_LIMIT

VIN_UV_WARN_LIMIT

PIN_OP_WARN_LIMIT

STATUS_BYTE

Read/write word

Read byte

2

0x0FFF

2

0x0FFF

0x58

2

0x0000

0x7FFF

0x6B

0x78

2

1

0x00

0x79

STATUS_WORD

STATUS_IOUT

Read word

2

0x0000

0x00

0x7B

0x7C

0x80

Read byte

1

STATUS_INPUT

STATUS_MFR_SPECIFIC

READ_EIN

Read byte

1

0x00

Read byte

1

0x00

0x86

Block read

1 (byte count) + 6 (data)

0x06000000000000

0x0000

0x22

0x88

READ_VIN

Read word

2

0x8C

0x97

READ_IOUT

Read word

2

READ_PIN

Read word

2

0x98

PMBUS_REVISION

MFR_ID

Read byte

1

0x99

Block read

1 (byte count) + 3 (data)

0x03 + ASCII “ADI”

0x9A

0x9B

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xF6

MFR_MODEL

Block read

1 (byte count) + 9 (data)

0x09 + ASCII “ADM1075-1” or “ADM1075-2”

MFR_REVISION

PEAK_IOUT

Block read

1 (byte count) + 1 (data)

0x01 + ASCII “1”

Read/write word

Read/write byte

Read/write word

Read/write byte

Send byte

2

0x0000

PEAK_VIN

2

0x0000

PEAK_VAUX

2

0x0000

PMON_CONTROL

PMON_CONFIG

ALERT1_CONFIG

ALERT2_CONFIG

IOUT_WARN2_LIMIT

DEVICE_CONFIG

POWER_CYCLE

PEAK_PIN

1

0x01

1

0x8F for ADM1075-1; 0x97 for ADM1075-2

2

0x8000

2

0x0004

2

0x0000

1

0x00

0

Not applicable

0x0000

Read/write word

Block read

2

READ_PIN_EXT

READ_EIN_EXT

READ_VAUX

1 (byte count) + 3 (data)

0x03000000

0x080000000000000000

0x0000

Block read

1 (byte count) + 8 (data)

Read word

2

1

VAUX_OV_WARN_LIMIT

VAUX_UV_WARN_LIMIT

STATUS_VAUX

Read/write word

Read byte

0x0FFF

0x0000

0x00

Rev. A | Page 38 of 52

Data Sheet

ADM1075

REGISTER DETAILS

OPERATION COMMAND REGISTER

Address: 0x01, Reset: 0x00, Name: OPERATION

Table 9. Bit Descriptions for OPERATION

Bits

Bit Name

Settings

Description

Reset

Access

7

ON

Hot swap enable.

0x0

RW

0

1

Hot swap output disabled.

Hot swap output enabled.

Always reads as 0000000.

[6:0]

RESERVED

0x0

R

CLEAR FAULTS REGISTER

Address: 0x03, Send Byte, No Data, Name: CLEAR_FAULTS

PMBUS CAPABILITY REGISTER

Address: 0x19, Reset: 0xB0, Name: CAPABILITY

Table 10. Bit Descriptions for CAPABILITY

Bits

Bit Name

Settings

Description

Reset

0x1

Access

7

PEC_SUPPORT

MAX_BUS_SPEED

SMBALERT_SUPPORT

Always reads as 1. Packet error checking (PEC) is supported.

Always reads as 01. Maximum supported bus speed is 400 kHz.

R

[6:5]

4

0x01

0x1

Always reads as 1. Device supports SMBAlert and alert response

address (ARA).

[3:0]

RESERVED

Always reads as 0000.

0x0000

R

IOUT OC WARN LIMIT REGISTER

Address: 0x4A, Reset: 0x0FFF, Name: IOUT_OC_WARN_LIMIT

Table 11. Bit Descriptions for IOUT_OC_WARN_LIMIT

Bits

[15:12] RESERVED

[11:0] IOUT_OC_WARN_LIMIT

Bit Name

Settings

Description

Reset

0x0

Access

R

Always reads as 0000.

Overcurrent threshold for the IOUT measurement through the sense

resistor, expressed in ADC codes.

0xFFF

RW

VIN OV WARN LIMIT REGISTER

Address: 0x57, Reset: 0x0FFF, Name: VIN_OV_WARN_LIMIT

Table 12. Bit Descriptions for VIN_OV_WARN_LIMIT

Bits

[15:12] RESERVED

[11:0] VIN_OV_WARN_LIMIT

Bit Name

Settings

Description

Reset

0x0

Access

R

Always reads as 0000.

Overvoltage threshold for the ADC_V pin measurement, expressed

in ADC codes.

0xFFF

RW

VIN UV WARN LIMIT REGISTER

Address: 0x58, Reset: 0x0000, Name: VIN_UV_WARN_LIMIT

Table 13. Bit Descriptions for VIN_UV_WARN_LIMIT

Bits

[15:12] RESERVED

[11:0] VIN_UV_WARN_LIMIT

Bit Name

Settings

Description

Reset

Access

R

Always reads as 0000.

0x0

Undervoltage threshold for the ADC_V pin measurement, expressed 0x0

in ADC codes.

RW

Rev. A | Page 39 of 52

ADM1075

Data Sheet

PIN OP WARN LIMIT REGISTER

Address: 0x6B, Reset: 0x7FFF, Name: PIN_OP_WARN_LIMIT

Table 14. Bit Descriptions for PIN_OP_WARN_LIMIT

Bits

Bit Name

Settings

Description

Reset

Access

R

15

RESERVED

Always reads as 0.

0x0

[14:0]

PIN_OP_WARN_LIMIT

Overpower threshold for the PMBus power measurement, expressed 0x7FFF

in ADC codes.

RW

STATUS BYTE REGISTER

Address: 0x78, Reset: 0x00, Name: STATUS_BYTE

Table 15. Bit Descriptions for STATUS_BYTE

Bits

7

Bit Name

Settings

Description

Reset

0x0

Access

RESERVED

Always reads as 0.

R

6

HOTSWAP_OFF

Live register.

0x0

0

The hot swap gate drive output is enabled.

1

The hot swap gate drive output is disabled, and the GATE pin is

pulled down. This can be due to, for example, an overcurrent fault

that causes the ADM1075 to latch off, an undervoltage condition on

the UVx pin, or the use of the OPERATION command to turn the

output off.

5

4

RESERVED

Always reads as 0.

0x0

R

IOUT_OC_FAULT

Latched register.

0

1

No overcurrent output fault detected.

The hot swap controller detected an overcurrent condition and the

time limit set by the capacitor on the TIMER pin has elapsed, causing

the hot swap gate drive to shut down.

3

VIN_UV_FAULT

Latched register.

0x0

R

0

1

No undervoltage input fault detected on the UVH/UVL pins.

An undervoltage input fault was detected on the UVH/UVL pins.

Always reads as 0.

2

1

RESERVED

0x0

R

CML_FAULT

Latched register.

0

1

No communications error detected on the I²C/PMBus interface.

An error was detected on the I²C/PMBus interface. Errors detected

are unsupported command, invalid PEC byte, and incorrectly

structured message.

0

NONE_OF_THE_ABOVE

Live register.

0x0

R

0

1

No other active status bit to be reported by any other status

command.

Active status bits are waiting to be read by one or more status

commands.

STATUS WORD REGISTER

Address: 0x79, Reset: 0x0000, Name: STATUS_WORD

Table 16. Bit Descriptions for STATUS_WORD

Bits

15

Bit Name

Settings

Description

Reset

0x0

Access

RESERVED

Always reads as 0.

R

14

IOUTPOUT_STATUS

Live register.

0x0

0

1

There are no active status bits to be read by STATUS_IOUT.

There are one or more active status bits to be read by STATUS_IOUT.

Rev. A | Page 40 of 52

Data Sheet

ADM1075

Bits

Bit Name

Settings

Description

Reset

Access

13

INPUT_STATUS

Live register.

0x0

R

0

1

There are no active status bits to be read by STATUS_INPUT.

There are one or more active status bits to be read by STATUS_INPUT.

Live register.

12

11

MFR_STATUS

PGB_STATUS

0x0

R

0

1

There are no active status bits to be read by STATUS_MFR_SPECIFIC.

There are one or more active status bits to be read by

STATUS_MFR_SPECIFIC.

Live register.

0x0

0

1

The voltage on the DRAIN pin is above the required threshold,

indicating that output power is considered good. This bit is the

PWRGD

logical inversion of the

pin on the part.

The voltage on the DRAIN pin is below the required threshold,

indicating that output power is considered bad.

[10:8]

[7:0]

RESERVED

Always reads as 000.

0x0

R

STATUS_BYTE

This byte is the same as the byte returned by the STATUS_BYTE

command.

IOUT STATUS REGISTER

Address: 0x7B, Reset: 0x00, Name: STATUS_IOUT

Table 17. Bit Descriptions for STATUS_IOUT

Bits

Bit Name

Settings

Description

Reset

Access

7

IOUT_OC_FAULT

Latched register.

0x0

R

0

1

No overcurrent output fault detected.

The hot swap controller detected an overcurrent condition and the

time limit set by the capacitor on the TIMER pin has elapsed, causing

the hot swap gate drive to shut down.

6

5

RESERVED

Always reads as 0.

Latched register.

0x0

R

IOUT_OC_WARN

0

1

No overcurrent condition on the output supply detected by the

power monitor using the IOUT_OC_WARN_LIMIT command.

An overcurrent condition was detected by the power monitor using

the IOUT_OC_WARN_LIMIT command.

[4:0]

RESERVED

Always reads as 00000.

0x0

R

INPUT STATUS REGISTER

Address: 0x7C, Reset: 0x00, Name: STATUS_INPUT

Table 18. Bit Descriptions for STATUS_INPUT

Bits

Bit Name

Settings

Description

Reset

Access

7

VIN_OV_FAULT

Latched register.

0x0

R

0

1

No overvoltage detected on the OV pin.

An overvoltage was detected on the OV pin.

Latched register.

6

5

VIN_OV_WARN

VIN_UV_WARN

0x0

R

0

1

No overvoltage condition on the input supply detected by the

power monitor.

An overvoltage condition on the input supply was detected by the

power monitor.

Latched register.

0

1

No undervoltage condition on the input supply detected by the

power monitor.

An undervoltage condition on the input supply was detected by the

power monitor.

Rev. A | Page 41 of 52

ADM1075

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

4

VIN_UV_FAULT

Latched register.

0x0

R

0

1

No undervoltage detected on the UVx pin.

An undervoltage was detected on the UVx pin.

Always reads as 000.

[3:1]

0

RESERVED

0x0

R

PIN_OP_WARN

Latched register.

0

1

No overpower condition on the input supply detected by the power

monitor.

An overpower condition on the input supply was detected by the

power monitor.

MANUFACTURING SPECIFIC STATUS REGISTER

Address: 0x80, Reset: 0x00, Name: STATUS_MFR_SPECIFIC

Table 19. Bit Descriptions for STATUS_MFR_SPECIFIC

Bits

Bit Name

Settings

Description

Reset

Access

7

FET_HEALTH_BAD

Latched register.

0x0

R

0

1

FET behavior appears to be as expected.

FET behavior suggests that the FET may be shorted.

Live register.

6

5

4

3

UV_CMP_OUT

OV_CMP_OUT

VAUX_STATUS

HS_INLIM_FAULT

0x0

R

0

1

Input voltage to UVx pin is above threshold.

Input voltage to UVx pin is below threshold.

Live register.

Input voltage to OV pin is below threshold.

Input voltage to OV pin is above threshold.

Latched register.

There are no active status bits to be read by STATUS_VAUX.

There are one or more active status bits to be read by STATUS_VAUX.

Latched register.

0

1

0

1

0

1

The ADM1075 has not actively limited the current into the load.

The ADM1075 has actively limited current into the load. This bit

differs from the IOUT_OC_FAULT bit in that the HS_INLIM bit is set

immediately, whereas the IOUT_OC_FAULT bit is not set unless the

time limit set by the capacitor on the TIMER pin elapses.

[2:1]

HS_SHUTDOWN_CAUSE

Latched register.

0x0

R

00 The ADM1075 is either enabled and working correctly, or has been

shut down using the OPERATION command.

01 An IOUT_OC_FAULT condition occurred that caused the ADM1075

to shut down.

10 A VIN_UV_FAULT condition occurred that caused the ADM1075 to

shut down.

11 A VIN_OV_FAULT condition occurred that caused the ADM1075 to

shut down.

0

IOUT_WARN2

Latched register.

0x0

R

0

1

No overcurrent condition on the output supply detected by the

power monitor using the IOUT_WARN2_LIMIT command.

An undercurrent or overcurrent condition on the output supply was

detected by the power monitor using the IOUT_WARN2_LIMIT

command. The polarity of the threshold condition is set by the

IOUT_WARN2_OC_SELECT bit using the DEVICE_CONFIG command.

Rev. A | Page 42 of 52

Data Sheet

ADM1075

READ EIN REGISTER

Address: 0x86, Reset: 0x06, 0x0000, 0x00, 0x000000, Name: READ_EIN

Table 20. Bit Descriptions for READ_EIN

Byte

Bit Name

Settings

Description

Reset

0x6

Access

[0]

BYTE_COUNT

Always reads as 0x06, the number of data bytes that the block read

command should expect to read.

R

[2:1]

ENERGY_COUNT

Energy accumulator value in direct format. Byte 2 is the high byte, and 0x0

Byte 1 is the low byte. Internally, the energy accumulator is a 24-bit

value, but only the most significant 16 bits are returned with this

command. Use the READ_EIN_EXT to access the nontruncated version.

R

[3]

ROLLOVER_COUNT

SAMPLE_COUNT

Number of times that the energy count has rolled over, from 0x7FFF to 0x0

0x0000. This is a straight 8-bit binary value.

R

[6:4]

This is the total number of PIN samples acquired and accumulated in

the energy count accumulator. Byte 6 is the high byte, Byte 5 is the

middle byte, and Byte 4 is the low byte.

0x0

READ VIN REGISTER

Address: 0x88, Reset: 0x0000, Name: READ_VIN

Table 21. Bit Descriptions for READ_VIN

Bits

[15:12] RESERVED

[11:0] READ_VIN

Bit Name

Settings

Description

Reset

0x0

Access

Always reads as 0000.

R

Input voltage from the ADC_V pin measurement, expressed in ADC

codes.

0x0

READ IOUT REGISTER

Address: 0x8C, Reset: 0x0000, Name: READ_IOUT

Table 22. Bit Descriptions for READ_IOUT

Bits

[15:12] RESERVED

[11:0] READ_IOUT

Bit Name

Settings

Description

Reset

0x0

Access

Always reads as 0000.

R

Output current measurement through the sense resistor.

0x0

READ PIN REGISTER

Address: 0x97, Reset: 0x0000, Name: READ_PIN

Table 23. Bit Descriptions for READ_PIN

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

READ_PIN

Input power from the VIN × IOUT calculation.

0x0

R

PMBus REVISION REGISTER

Address: 0x98, Reset: 0x22, Name: PMBUS_REVISION

Table 24. Bit Descriptions for PMBUS_REVISION

Bits

[7:4]

[3:0]

Bit Name

Settings

Description

Reset

0x2

Access

PMBUS_P1_REVISION

PMBUS_P2_REVISION

Always reads as 0010, PMBus Specification Part I, Revision 1.2.

Always reads as 0010, PMBus Specification Part II, Revision 1.2.

R

0x2

0000 Rev1.0.

0001 Rev1.1.

0010 Rev1.2.

Rev. A | Page 43 of 52

ADM1075

Data Sheet

MANUFACTURING ID REGISTER

Address: 0x99, Reset: 0x03 + ASCII “ADI”, Name: MFR_ID

Table 25. Bit Descriptions for MFR_ID

Byte

Bit Name

Settings

Description

Reset

Access

0

BYTE_COUNT

Always reads as 0x03, the number of data bytes that the block read

command should expect to read.

0x3

R

1

2

3

CHARACTER1

CHARACTER2

CHARACTER3

Always reads as 0x41 = “A”.

Always reads as 0x44 = “D”.

Always reads as 0x49 = “I”.

0x41

0x44

0x49

R

MANUFACTURING MODEL REGISTER

Address: 0x9A, Reset: 0x09 + ASCII “ADM1075-x”, Name: MFR_MODEL

Table 26. Bit Descriptions for MFR_MODEL

Byte

Bit Name

Settings

Description

Reset

Access

0

BYTE_COUNT

Always reads as 0x03, the number of data bytes that the block read

command should expect to read.

0x9

R

1

2

3

4

5

6

7

8

9

CHARACTER1

CHARACTER2

CHARACTER3

CHARACTER4

CHARACTER5

CHARACTER6

CHARACTER7

CHARACTER8

CHARACTER9

Always reads as 0x41 = “A”.

Always reads as 0x44 = “D”.

Always reads as 0x4D = “M”.

Always reads as 0x31 = “1”.

Always reads as 0x30 = “0”.

Always reads as 0x37 = “7”.

Always reads as 0x35 = “5”.

Always reads as 0x2D = “-”.

0x41

0x44

0x4D

0x31

0x30

0x37

0x35

0x2D

R

Always reads as 0x31 = “1” for ADM1075-1.

Always reads as 0x32 = “2” for ADM1075-2.

0x31 or

0x32

MANUFACTURING REVISION REGISTER

Address: 0x9B, Reset: 0x01 + ASCII “1”, Name: MFR_REVISION

Table 27. Bit Descriptions for MFR_REVISION

Byte

Bit Name

Settings

Description

Reset

Access

0

BYTE_COUNT

Always reads as 0x01, the number of data bytes that the block read

command should expect to read.

0x1

R

1

CHARACTER1

Always reads as 0x31, Revision 1 of ADM1075.

0x31

R

PEAK IOUT REGISTER

Address: 0xD0, Reset: 0x0000, Name: PEAK_IOUT (writing 0x0000 clears the peak value)

Table 28. Bit Descriptions for PEAK_IOUT

Bits

[15:12] RESERVED

[11:0] PEAK_IOUT

Bit Name

Settings

Description

Reset

0x0

Access

Always reads as 0000.

R

Returns the peak IOUT current since the register was last cleared.

0x0

Rev. A | Page 44 of 52

Data Sheet

ADM1075

PEAK VIN REGISTER

Address: 0xD1, Reset: 0x0000, Name: PEAK_VIN (writing 0x0000 clears the peak value)

Table 29. Bit Descriptions for PEAK_VIN

Bits

[15:12] RESERVED

[11:0] PEAK_VIN

Bit Name

Settings

Description

Reset

Access

Always reads as 0000.

0x0

R

Returns the peak VIN voltage since the register was last cleared.

PEAK VAUX REGISTER

Address: 0xD2, Reset: 0x0000, Name: PEAK_VAUX (writing 0x0000 clears the peak value)

Table 30. Bit Descriptions for PEAK_VAUX

Bits

[15:12] RESERVED

[11:0] PEAK_VAUX

Bit Name

Settings

Description

Reset

0x0

Access

Always reads as 0000.

R

Returns the peak VAUX voltage since the register was last cleared.

0x0

POWER MONITOR CONTROL REGISTER

Address: 0xD3, Reset: 0x01, Name: PMON_CONTROL

Table 31. Bit Descriptions for PMON_CONTROL

Bits

[7:1]

0

Bit Name

RESERVED

CONVERT

Settings

Description

Reset

0x0

Access

R

Always reads as 0000000.

0x1

RW

0

1

Power monitor is not running.

Default. Starts the sampling of current and voltage with the power

monitor. In single-shot mode, this bit clears itself after one complete cycle.

In continuous mode, this bit must be written to 0 to stop sampling.

POWER MONITOR CONFIGURATION REGISTER

Address: 0xD4, Reset: 0x8F, Name: PMON_CONFIG

Table 32. Bit Descriptions for PMON_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

7

PMON_MODE

0x1

RW

0

1

This setting selects single-shot sampling mode.

Default. This setting selects continuous sampling mode.

6

VAUX_ENABLE

0x0

RW

0

1

Default. The power monitor samples the input voltage on ADC_V and

IOUT.

The power monitor also samples the voltage on the ADC_AUX pin.

Always reads as 0.

5

RESERVED

IRANGE

0x0

R

[4:3]

0x1 or

0x2

00 Reserved.

01 Sets current sense range to 25 mV. Default for ADM1075-1.

10 Sets current sense range to 50 mV. Default for ADM1075-2.

11 Reserved.

[2:0]

AVERAGING

0x7

RW

000 Disables sample averaging for current and voltage.

001 Sets sample averaging for current and voltage to two samples.

010 Sets sample averaging for current and voltage to four samples.

011 Sets sample averaging for current and voltage to eight samples.

100 Sets sample averaging for current and voltage to 16 samples.

101 Sets sample averaging for current and voltage to 32 samples.

110 Sets sample averaging for current and voltage to 64 samples.

111 Default. Sets sample averaging for current and voltage to 128 samples.

Rev. A | Page 45 of 52

ADM1075

Data Sheet

ALERT1 CONFIGURATION REGISTER

Address: 0xD5, Reset: 0x8000, Name: ALERT1_CONFIG

Table 33. Bit Descriptions for ALERT1_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

15

FET_HEALTH_BAD_EN1

0x1

RW

0

1

Disables generation of SMBAlert when the FET_HEALTH_BAD bit

is set.

Default. Generates SMBAlert when the FET_HEALTH_BAD bit is

set. This bit is active from power-up so that a FET problem can be

detected and flagged immediately without the need for software

to set this bit.

14

13

12

11

10

9

IOUT_OC_FAULT_EN1

VIN_OV_FAULT_EN1

VIN_UV_FAULT_EN1

CML_ERROR_EN1

0x0

RW

0

1

Default. Disables generation of SMBAlert when the

IOUT_OC_FAULT bit is set.

Generates SMBAlert when the IOUT_OC_FAULT bit is set.

0

1

Default. Disables generation of SMBAlert when the

VIN_OV_FAULT bit is set.

Generates SMBAlert when the VIN_OV_FAULT bit is set.

0

1

Default. Disables generation of SMBAlert when the

VIN_UV_FAULT bit is set.

Generates SMBAlert when the VIN_UV_FAULT bit is set.

0

1

Default. Disables generation of SMBAlert when the CML_FAULT

bit is set.

Generates SMBAlert when the CML_ FAULT bit is set.

IOUT_OC_WARN_EN1

IOUT_WARN2_EN1

VIN_OV_WARN_EN1

VIN_UV_WARN_EN1

VAUX_OV_WARN_EN1

VAUX_UV_WARN_EN1

HS_INLIM_EN1

0

1

Default. Disables generation of SMBAlert when the

IOUT_OC_WARN bit is set.

Generates SMBAlert when the IOUT_OC_WARN bit is set.

0

1

Default. Disables generation of SMBAlert when the IOUT_WARN2

bit is set.

Generates SMBAlert when the IOUT_WARN2 bit is set.

8

0

1

Default. Disables generation of SMBAlert when the

VIN_OV_WARN bit is set.

Generates SMBAlert when the VIN_OV_WARN bit is set.

7

0

1

Default. Disables generation of SMBAlert when the

VIN_UV_WARN bit is set.

Generates SMBAlert when the VIN_UV_WARN bit is set.

6

0

1

Default. Disables generation of SMBAlert when the

VAUX_OV_WARN bit is set.

Generates SMBAlert when the VAUX_OV_WARN bit is set.

5

0

1

Default. Disables generation of SMBAlert when the

VAUX_UV_WARN bit is set.

Generates SMBAlert when the VAUX_UV_WARN bit is set.

4

0

1

Default. Disables generation of SMBAlert when the

HS_INLIM_FAULT bit is set.

Generates SMBAlert when the HS_INLIM_FAULT bit is set.

Rev. A | Page 46 of 52

Data Sheet

ADM1075

Bits

Bit Name

Settings

Description

Reset

Access

3

PIN_OP_WARN_EN1

0x0

RW

0

1

Default. Disables generation of SMBAlert when the

PIN_OP_WARN bit is set.

Generates SMBAlert when the PIN_OP_WARN bit is set.

[2:1]

GPO1_MODE

0x0

RW

00 Default. GPO1 is configured to generate SMBAlerts.

01 GPO1 can be used a general-purpose digital output pin. The

GPO1_INVERT bit is used to change the output state.

10 GPO1 is configured as a convert (CONV) input pin.

11 This is digital comparator mode. The output pin now reflects the

live status of the warning or fault bit selected for the output. In

effect, this is a nonlatched SMBAlert.

0

GPO1_INVERT

0x0

RW

0

1

Default. In GPO mode, the GPO1 pin is active low.

In GPO mode, the GPO1 pin is active high.

ALERT2 CONFIGURATION REGISTER

Address: 0xD6, Reset: 0x0004, Name: ALERT2_CONFIG

Table 34. Bit Descriptions for ALERT2_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

15

FET_HEALTH_BAD_EN2

0x0

RW

0

1

Default. Disables generation of SMBAlert when the

FET_HEALTH_BAD bit is set.

Generates SMBAlert when the FET_HEALTH_BAD bit is set. This bit

is active from power-up so that a FET problem can be detected

and flagged immediately without the need for software to set

this bit.

14

13

12

11

10

9

IOUT_OC_FAULT_EN2

VIN_OV_FAULT_EN2

VIN_UV_FAULT_EN2

CML_ERROR_EN2

0x0

RW

0

1

Default. Disables generation of SMBAlert when the

IOUT_OC_FAULT bit is set.

Generates SMBAlert when the IOUT_OC_FAULT bit is set.

0

1

Default. Disables generation of SMBAlert when the

VIN_OV_FAULT bit is set.

Generates SMBAlert when the VIN_OV_FAULT bit is set.

0

1

Default. Disables generation of SMBAlert when the

VIN_UV_FAULT bit is set.

Generates SMBAlert when the VIN_UV_FAULT bit is set.

0

1

Default. Disables generation of SMBAlert when the CML_FAULT

bit is set.

Generates SMBAlert when the CML_ FAULT bit is set.

IOUT_OC_WARN_EN2

IOUT_WARN2_EN2

VIN_OV_WARN_EN2

0

1

Default. Disables generation of SMBAlert when the

IOUT_OC_WARN bit is set.

Generates SMBAlert when the IOUT_OC_WARN bit is set.

0

1

Default. Disables generation of SMBAlert when the IOUT_WARN2

bit is set.

Generates SMBAlert when the IOUT_WARN2 bit is set.

8

0

1

Default. Disables generation of SMBAlert when the

VIN_OV_WARN bit is set.

Generates SMBAlert when the VIN_OV_WARN bit is set.

Rev. A | Page 47 of 52

ADM1075

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

7

VIN_UV_WARN_EN2

VAUX_OV_WARN_EN2

VAUX_UV_WARN_EN2

HS_INLIM_EN2

0x0

RW

0

1

Default. Disables generation of SMBAlert when the

VIN_UV_WARN bit is set.

Generates SMBAlert when the VIN_UV_WARN bit is set.

6

0x0

0x2

RW

0

1

Default. Disables generation of SMBAlert when the

VAUX_OV_WARN bit is set.

Generates SMBAlert when the VAUX_OV_WARN bit is set.

5

0

1

Default. Disables generation of SMBAlert when the

VAUX_UV_WARN bit is set.

Generates SMBAlert when the VAUX_UV_WARN bit is set.

4

0

1

Default. Disables generation of SMBAlert when the

HS_INLIM_FAULT bit is set.

Generates SMBAlert when the HS_INLIM_FAULT bit is set.

3

PIN_OP_WARN_EN2

GPO2_MODE

0

1

Default. Disables generation of SMBAlert when the

PIN_OP_WARN bit is set.

Generates SMBAlert when the PIN_OP_WARN bit is set.

[2:1]

00 GPO2 is configured to generate SMBAlerts.

01 GPO2 can be used a general-purpose digital output pin. The

GPO2_INVERT bit is used to change the output state.

10 Default. GPO2 is configured as a retry fail output.

11 This is digital comparator mode. The output pin now reflects the

live status of the warning or fault bit selected for the output. In

effect, this is a nonlatched SMBAlert.

0

GPO2_INVERT

0x0

RW

0

1

Default. In GPO mode, the GPO2 pin is active low.

In GPO mode, the GPO2 pin is active high.

IOUT WARN2 LIMIT REGISTER

Address: 0xD7, Reset: 0x0000, Name: IOUT_WARN2_LIMIT

Table 35. Bit Descriptions for IOUT_WARN2_LIMIT

Bits

[15:12] RESERVED

[11:0] IOUT_WARN2_LIMIT

Bit Name

Settings

Description

Reset

0x0

Access

R

Always reads as 0000.

Threshold for the IOUT measurement through the sense resistor,

expressed in ADC codes. This value can be either an undercurrent

or overcurrent, depending on the state of the

IOUT_WARN2_OC_SELECT bit set using the DEVICE_CONFIG

command.

0x0

RW

DEVICE CONFIGURATION REGISTER

Address: 0xD8, Reset: 0x00, Name: DEVICE_CONFIG

Table 36. Bit Descriptions for DEVICE_CONFIG

Bits

[7:6]

5

Bit Name

Settings

Description

Reset

0x00

0x0

Access

R

RESERVED

Always reads as 00.

Enable operation command.

OPERATION_CMD_ENABLE

RW

0

1

The OPERATION command is disabled, and the ADM1075 issues a

NACK if the command is received. This setting provides some

protection against a card accidentally turning itself off

The OPERATION command is enabled, and the ADM1075

responds to it.

Rev. A | Page 48 of 52

Data Sheet

ADM1075

Bits

Bit Name

Settings

Description

Reset

Access

4

IOUT_WARN2_OC_SELECT

Sets IOUT Warning 2 limit to OC or UC.

Configures IOUT_WARN2_LIMIT as an undercurrent threshold

Configured IOUT_WARN2_LIMIT as an overcurrent threshold

Sets severe OC trip threshold.

0x0

RW

0

1

[3:2]

[1:0]

OC_TRIP_SELECT

OC_FILT_SELECT

0x0

RW

00 125%.

01 150%. Default.

10 200%.

11 225%.

Sets severe OC filter time.

0x0

00 200 ns.

01 900 ns. Default.

10 10.7 μs.

11 57 μs.

POWER CYCLE REGISTER

Address: 0xD9, Send Byte, No Data, Name: POWER_CYCLE

PEAK PIN REGISTER

Address: 0xDA, Reset: 0x0000, Name: PEAK_PIN (writing 0x0000 clears the peak value)

Table 37. Bit Descriptions for PEAK_PIN

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

PEAK_PIN

Returns the peak input power since the register was last cleared.

0x0

R

READ PIN_EXT REGISTER

Address: 0xDB, Reset: 0x03, 0x000000, Name: READ_PIN_EXT

Table 38. Bit Descriptions for READ_PIN_EXT

Byte

Bit Name

Settings

Description

Reset

Access

[0]

BYTE_COUNT

Always reads as 0x03, the number of data bytes that the block

read command should expect to read.

0x3

R

[3:1]

READ_PIN_EXT

This is the result of the VIN × IOUT calculation that has not been

truncated. Byte 3 is the high byte, Byte 2 is the middle byte, and

Byte 1 is the low byte.

0x0

R

READ EIN_EXT REGISTER

Address: 0xDC, Reset: 0x08, 0x000000, 0x0000, 0x000000, Name: READ_EIN_EXT

Table 39. Bit Descriptions for READ_EIN_EXT

Byte

Bit Name

Settings

Description

Reset

Access

[0]

BYTE_COUNT

Always reads as 0x08, the number of data bytes that the block

read command should expect to read.

0x8

R

[3:1]

[5:4]

[8:6]

ENERGY_EXT

This is the 24-bit energy accumulator in direct format. Byte 3 is

the high byte, Byte 2 is the middle byte, and Byte 1 is the low

byte.

0x0

R

ROLLOVER_EXT

SAMPLE_COUNT

Number of times that the energy count has rolled over, from

0x7FFF to 0x0000. This is a straight 16-bit binary value. Byte 5 is

the high byte, Byte 4 is the low byte.

This is the total number of PIN samples acquired and

accumulated in the energy count accumulator. Byte 8 is the high

byte, Byte 7 is the middle byte, and Byte 6 is the low byte.

Rev. A | Page 49 of 52

ADM1075

Data Sheet

READ VAUX REGISTER

Address: 0xDD, Reset: 0x0000, Name: READ_VAUX

Table 40. Bit Descriptions for READ_VAUX

Bits

[15:12] RESERVED

[11:0] READ_VAUX

Bit Name

Settings

Description

Reset

0x0

Access

Always reads as 0000.

R

Output voltage from the ADC_AUX pin measurement, expressed in

ADC codes.

0x0

VAUX OV WARN LIMIT REGISTER

Address: 0xDE, Reset: 0x0FFF, Name: VAUX_OV_WARN_LIMIT

Table 41. Bit Descriptions for VAUX_OV_WARN_LIMIT

Bits

[15:12] RESERVED

[11:0] VAUX_OV_WARN_LIMIT

Bit Name

Settings

Description

Reset

0x0

Access

R

Always reads as 0000.

Overvoltage threshold for the ADC_AUX pin measurement,

expressed in ADC codes.

0xFFF

RW

VAUX UV WARN LIMIT REGISTER

Address: 0xDF, Reset: 0x0000, Name: VAUX_UV_WARN_LIMIT

Table 42. Bit Descriptions for VAUX_UV_WARN_LIMIT

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:12] RESERVED

Always reads as 0000.

[11:0]

VAUX_UV_WARN_LIMIT

Undervoltage threshold for the ADC_AUX pin measurement,

expressed in ADC codes.

0x0

RW

VAUX STATUS REGISTER

Address: 0xF6, Reset: 0x00, Name: STATUS_VAUX

Table 43. Bit Descriptions for STATUS_VAUX

Bits

Bit Name

Settings

Description

Reset

Access

7

VAUX_OV_WARN

Latched register.

0x0

R

0

1

No overvoltage condition was detected on the ADC_AUX pin by the

power monitor using the VAUX_OV_WARN_LIMIT command.

An overvoltage condition was detected on the ADC_AUX pin by the

power monitor using the VAUX_OV_WARN_LIMIT command.

6

VAUX_UV_WARN

RESERVED

Latched register.

No undervoltage condition was detected on the ADC_AUX pin by

the power monitor using the VAUX_UV_WARN_LIMIT command.

An undervoltage condition was detected on the ADC_AUX pin by

the power monitor using the VAUX_UV_WARN_LIMIT command.

0x0

R

0

1

[5:0]

Always reads as 000000.

Rev. A | Page 50 of 52

Data Sheet

ADM1075

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

15

4.50

4.40

4.30

6.40 BSC

1

14

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

8°

0°

0.75

0.60

0.45

0.30

0.19

0.20

0.09

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 64. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

0.30

0.25

0.18

5.10

5.00 SQ

4.90

PIN 1

INDICATOR

PIN 1

INDICATOR

22

28

21

1

0.50

BSC

EXPOSED

PAD

3.40

3.30 SQ

3.20

15

7

14

8

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-3.

Figure 65. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-28-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range²

−40°C to +85°C

Package Description

Package Option

ADM1075-1ACPZ

ADM1075-1ACPZ-RL7

ADM1075-1ARUZ

ADM1075-1ARUZ-RL7

ADM1075-2ACPZ

ADM1075-2ACPZ-RL7

ADM1075-2ARUZ

ADM1075-2ARUZ-RL7

EVAL-ADM1075EBZ

28-Lead LFCSP_WQ (25 mV full-scale V_SENSE

)

CP-28-6

RU-28

28-Lead TSSOP (25 mV full-scale V_SENSE

)

RU-28

28-Lead LFCSP_WQ (50 mV full-scale V_SENSE

)

CP-28-6

RU-28

28-Lead TSSOP (50 mV full-scale V_SENSE

Evaluation Board

)

RU-28

¹Z = RoHS Compliant Part.

²Operating junction temperature is −40°C to +105°C.

Rev. A | Page 51 of 52

ADM1075

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D09312-0-4/12(A)

Rev. A | Page 52 of 52


型号：	EVAL-ADM1075EBZ
厂家：	ADI
描述：	â48 V Hot Swap Controller and Digital â ???? 48 V热插拔控制器和数字控制器
文件：	总52页 (文件大小：745K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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