EVAL-ADM1192EBZ [ADI]
Digital Power Monitor with Clear Pin and ALERT Output; 数字电源监控与复位引脚和报警输出型号: | EVAL-ADM1192EBZ |
厂家: | ADI |
描述: | Digital Power Monitor with Clear Pin and ALERT Output |
文件: | 总20页 (文件大小:419K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Digital Power Monitor
with Clear Pin and ALERT Output
ADM1192
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Powered from 3.15 V to 26 V
Precision current sense amplifier
Precision voltage input
ADM1192
SDA
V
VCC
0
12-bit ADC for current and voltage readback
ALERT output allows basic P-channel FET hot swap
up to 26 V
SETV input for setting overcurrent alert threshold
Programmable overcurrent filtering via TIMER pin
CLRB input pin
2
12-BIT
ADC
SCL
ADR
I C
I
1
A
SENSE
MUX
CURRENT
SENSE
AMPLIFIER
I2C fast mode-compliant interface (400 kHz maximum)
10-lead MSOP
ALERT
ALERT
SETV
COMPARATOR
APPLICATIONS
GND
CLRB
TIMER
Power monitoring/power budgeting
Central office equipment
Figure 1.
Telecommunications and data communications equipment
PCs/servers
3.15V TO 26V
R
SENSE
GENERAL DESCRIPTION
The ADM1192 is an integrated current sense amplifier that
offers digital current and voltage monitoring via an on-chip
12-bit analog-to-digital converter (ADC), communicated
through an I2C® interface.
VCC
SENSE
ALERT
CONTROLLER
INTERRUPT
P = VI
ADM1192
SDA
SDA
SCL
SETV
SCL
An internal current sense amplifier measures voltage across the
sense resistor in the power path via the VCC pin and the SENSE pin.
CLRB
CLRB
TIMER
ADR
GND
A 12-bit ADC can measure the current seen in the sense resistor
and in the supply voltage on the VCC pin. An industry-standard
I2C interface allows a controller to read current and voltage
data from the ADC. Measurements can be initiated by an I2C
command. Alternatively, the ADC can run continuously, and
the user can read the latest conversion data whenever it is
required. Up to four unique I2C addresses can be created,
depending on the way the ADR pin is connected.
Figure 2. Applications Diagram
The ALERT output can be used as a flag to warn a micro-
controller or field programmable gate array (FPGA) of an
overcurrent condition. ALERT outputs of multiple ADM1192
devices can be tied together and used as a combined alert.
A SETV pin is also included. A voltage applied to this pin is
internally compared with the output voltage on the current sense
amplifier. The output of the SETV comparator asserts when the
current sense amplifier output exceeds the SETV voltage. This
event is detected at the ALERT block. The ALERT block then
charges up the external TIMER capacitor with a fixed current.
When this timing cycle is complete, the ALERT output asserts.
A basic P-channel FET hot swap circuit can be implemented
with the ALERT output. The value of the TIMER capacitor
should be set so that the charging time of this capacitor is much
longer than the period during which a higher than nominal
inrush current may be flowing.
The ADM1192 is packaged in a 10-lead MSOP.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2008 Analog Devices, Inc. All rights reserved.
ADM1192
TABLE OF CONTENTS
Features .............................................................................................. 1
Identifying the ADM1192 on the I2C Bus............................... 10
General I2C Timing.................................................................... 10
Write and Read Operations........................................................... 12
Quick Command........................................................................ 12
Write Command Byte................................................................ 12
Write Extended Command Byte .............................................. 13
Read Voltage and/or Current Data Bytes................................ 14
Applications Information.............................................................. 16
ALERT Output............................................................................ 16
SETV Pin ..................................................................................... 16
Kelvin Sense Resistor Connection ........................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Voltage and Current Readback ..................................................... 10
Serial Bus Interface..................................................................... 10
REVISION HISTORY
2/08—Rev. A to Rev. B
Changes to Figure 2.......................................................................... 1
Changed VVCC to VCC Throughout ................................................. 3
Added ADC Conversion Time Parameter .................................... 3
Changes to Input Current for 00 Decode, IADRLOW, Parameter ... 4
Changes to Input Current for 11 Decode, IADRHIGH, Parameter... 4
Added Endnote 2.............................................................................. 4
Changes to Figure 6.......................................................................... 7
Changes to Figure 17........................................................................ 9
Changes to General I2C Timing Section, Step 3......................... 10
Changes to Table 5.......................................................................... 10
Changes to Quick Command Section ......................................... 12
Changes to Figure 21...................................................................... 12
Changes to Table 7.......................................................................... 12
Changes to Write Extended Command Byte Section................ 13
Changes to Figure 23...................................................................... 13
Changes to Table 9 and Table 11................................................... 13
Changes to Converting ADC Codes to Voltage and
4/07—Rev. 0 to Rev. A
Changes to Table 5.......................................................................... 10
Changes to Figure 18 and Figure 19............................................. 11
Changes to Figure 23...................................................................... 13
Changes to Figure 25 and Figure 26............................................. 14
Added Applications Information Heading ................................. 16
9/06—Revision 0: Initial Version
Current Readings Section......................................................... 14
Changes to Figure 27...................................................................... 16
Rev. B | Page 2 of 20
ADM1192
SPECIFICATIONS
VCC = 3.15 V to 26 V, TA = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit Conditions
VCC PIN
Operating Voltage Range, VCC
Supply Current, ICC
Undervoltage Lockout, VUVLO
Undervoltage Lockout Hysteresis, VUVLOHYST
MONITORING ACCURACY1
Current Sense Absolute Accuracy
3.15
26
2
V
mA
V
mV
1.7
2.8
80
VCC rising
0°C to +70°C
0°C to +85°C
−40°C to +85°C
−1.45
−1.8
+1.45
+1.8
%
%
%
%
%
%
%
%
%
%
%
%
mV
VSENSE = 75 mV
VSENSE = 50 mV
VSENSE = 25 mV
VSENSE = 12.5 mV
VSENSE = 75 mV
VSENSE = 50 mV
VSENSE = 25 mV
VSENSE = 12.5 mV
VSENSE = 75 mV
VSENSE = 50 mV
VSENSE = 25 mV
VSENSE = 12.5 mV
−2.8
+2.8
−5.7
+5.7
−1.5
+1.5
−1.8
+1.8
−2.95
−6.1
+2.95
+6.1
−1.95
−2.45
−3.85
−6.7
+1.95
+2.45
+3.85
+6.7
VSENSE for ADC Full Scale2
Voltage Sense Accuracy
105.84
0°C to +70°C
−0.85
+0.85
%
VCC = 3.0 V to 5.5 V (low range)
VCC = 10.8 V to 16.5 V (high range)
VCC = 3.0 V to 5.5 V (low range)
−0.9
−0.85
+0.9
+0.85
%
%
0°C to +85°C
−0.9
−0.9
−1.15
+0.9
+0.9
+1.15
%
%
%
VCC = 10.8 V to 16.5 V (high range)
VCC = 3.0 V to 5.5 V (low range)
VCC = 10.8 V to 16.5 V (high range)
−40°C to +85°C
VCC for ADC Full Scale3
Low Range (VRANGE = 1)
High Range (VRANGE = 0)
CLRB PIN
6.65
26.52
V
V
Logic Low Threshold, VCLRBL
Input Current for Logic Low Input, ICLRBL
Logic High Threshold, VCLRBH
Input Current for Logic High Input, ICLRBH
ADC CONVERSION TIME4
0.8
6
V
−40
1.6
−22
μA
mV
μA
μs
VCLRB = 0 V to 0.8 V
VCLRB = 1.6 V to 5.5 V
3
150
SENSE PIN
Input Current, ISENSE
−1
+1
μA
VSENSE = VCC
Rev. B | Page 3 of 20
ADM1192
Parameter
Min
Typ
Max
Unit Conditions
SETV PIN
Overcurrent Trip Threshold
98
49.5
100
50
102
50.5
mV
mV
VSETV = 1.8 V
VSETV = 0.9 V
Overcurrent Trip Gain, VSETV/(VCC − VSENSE
Input Current, ISETVLEAK
Glitch Filter, tSETVGLITCH
)
18
VSETV = 0.9 V to 1.9 V
VSETV = 0.9 V to 1.9 V
−1
+1
μA
μs
3
TIMER PIN
Pull-Up Current (Overcurrent Fault), ITIMERUPOC
Pull-Down Current, ITIMERDN
Pin Threshold High, VTIMERH
ALERT PIN
−46
−62
100
1.3
−78
μA
μA
V
(18.125 × VSENSE) > VSETV, VTIMER = 1 V
Normal operation, VTIMER = 1 V
TIMER rising
1.275
1.325
Output Low Voltage, VALERTOL
0.05
1
0.1
1.5
+1
V
mA
μA
IALERT = −100 μA
IALERT = −2 mA
VALERT = VCC; ALERT asserted
Input Current, IALERT
ADR PIN
−1
Set Address to 00, VADRLOWV
Set Address to 01, RADRLOWZ
0
80
0.8
160
V
kΩ
Low state
Resistor to ground state, load pin with
specified resistance for 01 decode
120
Set Address to 10, IADRHIGHZ
−0.3
+0.3
5.5
μA
Open state, maximum load allowed on
ADR pin for 10 decode
High state
Set Address to 11, VADRHIGHV
2
V
Input Current for 00 Decode, IADRLOW
−40
−25
3
μA
VADR = 0 V to 0.8 V
Input Current for 11 Decode, IADRHIGH
6
μA
VADR = 2.0 V to 5.5 V
I2C TIMING
Low Level Input Voltage, VIL
High Level Input Voltage, VIH
Low Level Output Voltage on SDA, VOL
Output Fall Time on SDA from VIHMIN to VILMAX
Maximum Width of Spikes Suppressed by
Input Filtering on SDA Pin and SCL Pin
0.3 VBUS
V
V
V
ns
ns
0.7 VBUS
0.4
250
250
IOL = 3 mA
CBUS = bus capacitance from SDA to GND
20 + 0.1 CBUS
50
Input Current, II, on SDA/SCL When Not
Driving a Logic Low Output
Input Capacitance on SDA/SCL
SCL Clock Frequency, fSCL
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for Repeated Start Condition, tSU;STA
SDA Output Data Hold Time, tHD;DAT
Setup Time for a Stop Condition, tSU;STO
Bus Free Time Between a Stop and a Start
Condition, tBUF
−10
+10
400
μA
5
pF
kHz
ns
ns
ns
ns
ns
ns
600
1300
600
100
600
900
400
1300
Capacitive Load for Each Bus Line
pF
1 Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
2 This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see the
specifications for the Current Sense Absolute Accuracy parameter).
3 These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see the
specifications for the Voltage Sense Accuracy parameter).
4 Time between the receipt of the command byte and the actual ADC result being placed in the register.
Rev. B | Page 4 of 20
ADM1192
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VCC Pin
30 V
SENSE Pin
TIMER Pin
CLRB Pin
SETV Pin
30 V
Table 3. Thermal Resistance
Package Type
10-Lead MSOP
−0.3 V to +6 V
−0.3 V to +6 V
30 V
θJA
Unit
137.5
°C/W
ALERT Pin
SDA Pin, SCL Pin
ADR Pin
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
30 V
ESD CAUTION
−0.3 V to +6 V
−0.3 V to +6 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 5 of 20
ADM1192
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
SENSE
SETV
1
2
3
4
5
10 ALERT
9
8
7
6
CLRB
ADR
SDA
SCL
ADM1192
TOP VIEW
(Not to Scale)
GND
TIMER
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
VCC
Positive Supply Input Pin. The operating supply voltage range is 3.15 V to 26 V. An undervoltage lockout (UVLO)
circuit resets the ADM1192 when a low supply voltage is detected.
2
SENSE
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across
a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.
3
SETV
Input Pin. The voltage driven onto this pin is compared with the output of the internal current sense amplifier.
The lower the voltage on the SETV, the lower the current level that causes the ALERT output to assert.
4
5
GND
TIMER
Chip Ground Pin.
Timer Input Pin. An external capacitor, CTIMER, sets the timing period for masking overcurrent conditions. This
timing period should be sufficient to allow the inrush current to completely charge up the load without
tripping an overcurrent fault. This makes the device robust against false triggering due to current transients.
I2C Clock Pin. Open-drain input; requires an external resistive pull-up.
I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I2C
addresses.
6
7
8
SCL
SDA
ADR
9
CLRB
Clear Pin. A latched overcurrent condition can be cleared by pulling this pin low.
10
ALERT
Alert Output Pin. Active high, open-drain configuration. This pin asserts high when an overcurrent condition
is present. The level at which an overcurrent condition is detected depends on the voltage on the SETV pin.
Rev. B | Page 6 of 20
ADM1192
TYPICAL PERFORMANCE CHARACTERISTICS
1000
900
800
700
600
500
400
300
200
100
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2046
2047
2048
2049
2050
0
4
8
12
16
(V)
20
24
28
CODE
V
CC
Figure 4. Supply Current vs. Supply Voltage
Figure 7. ADC Noise with Current Channel, Midcode Input, and 1000 Reads
1000
900
800
700
600
500
400
300
200
100
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
779
780
781
782
783
–40
–20
0
20
40
60
80
CODE
TEMPERATURE (°C)
Figure 8. ADC Noise with 14:1 Voltage Channel, 5 V Input, and 1000 Reads
Figure 5. Supply Current vs. Temperature
1000
900
800
700
600
500
400
300
200
100
0
00 DECODE
01 DECODE
10 DECODE 11 DECODE
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3078
3079
3080
3081
3082
–35
–30
–25
–20
–15
–10
–5
0
5
10
CODE
I
(µA)
ADR
Figure 6. Address Pin Voltage vs. Address Pin Current
for Four Addressing Options on Each Address Pin
Figure 9. ADC Noise with 7:1 Voltage Channel, 5 V Input, and 1000 Reads
Rev. B | Page 7 of 20
ADM1192
4
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
3
2
1
0
–1
–2
–3
–4
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 10. INL for ADC
Figure 13. ALERT Output Low Voltage vs. Temperature @ 1 mA
1.0
0.8
0.6
0.4
0.2
0
4
3
2
1
0
–1
–2
–3
–4
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
(V)
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
V
CC
Figure 11. DNL for ADC
Figure 14. ALERT Output Low Voltage vs. Supply Voltage @ 1 mA
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
(mA)
V
SETV
I
LOAD
Figure 12. Overcurrent Limit Threshold vs. SETV Pin Voltage
Figure 15. ALERT Output Low Voltage vs. Load Current
Rev. B | Page 8 of 20
ADM1192
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
HIGH
HIGH
3
5
7
9
11
13
15
(V)
17
19
21
23
25
–40
–20
0
20
40
60
80
V
TEMPERATURE (°C)
CC
Figure 17. Timer Threshold vs. Temperature
Figure 16. Timer Threshold vs. Supply Voltage
Rev. B | Page 9 of 20
ADM1192
VOLTAGE AND CURRENT READBACK
The ADM1192 contains the components to allow voltage and
current readback over an I2C bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be instructed
to convert voltage and/or current at any time during operation
via an I2C command. When all conversions are complete, the
voltage and/or current values can be read back with 12-bit
accuracy in two or three bytes.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period of
this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
W
it or written to it. If the R/ bit is 0, the master writes to
W
the slave device. If the R/ bit is 1, the master reads from
the slave device.
SERIAL BUS INTERFACE
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-to-high
transition when the clock is high can be interpreted as a
stop signal.
Control of the ADM1192 is carried out via the serial system
management bus (I2C). This interface is compatible with the I2C
fast mode (400 kHz maximum). The ADM1192 is connected to
this bus as a slave device, under the control of a master device.
IDENTIFYING THE ADM1192 ON THE I2C BUS
The ADM1192 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The five MSBs of the address are set to 01011; the two LSBs are
determined by the state of the ADR pin. There are four config-
urations available on the ADR pin that correspond to four I2C
addresses for the two LSBs (see Table 5). This scheme allows four
ADM1192 devices to operate on a single I2C bus.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write, or it can be
a register address that tells the slave where subsequent data
is to be written.
GENERAL I2C TIMING
Because data can flow in only one direction, as defined by
Figure 18 and Figure 19 show timing diagrams for general write
and read operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I2C protocol operates as follows:
W
the R/ bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
1. The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains high.
This indicates that a data stream is to follow. All slave periph-
erals connected to the serial bus respond to the start condition
and shift in the next eight bits, consisting of a 7-bit slave
3. When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a
no acknowledge. The master then takes the data line low
during the SCL low period before the 10th clock pulse, and
then high during the 10th clock pulse to assert a stop condition.
W
address (MSB first) plus an R/ bit that determines the
direction of the data transfer, that is, whether data is written
to or read from the slave device (0 = write, 1 = read).
Table 5. Setting I2C Addresses via the ADR Pin
Base Address
ADR Pin State
ADR Pin Logic State
Address in Binary1
0101100X
0101101X
0101110X
Address in Hex
0x58
0x5A
0x5C
0x5E
01011
Ground
00
01
10
11
Resistor to ground
Floating
High
0101111X
1 X = don’t care.
Rev. B | Page 10 of 20
ADM1192
9
9
1
1
SCL
SDA
0
0
ADRA ADRB R/W
D7
D6
D5
1
D4
D3
D2
D1
D0
1
1
1
ACKNOWLEDGE BY
SLAVE
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
FRAME 2
SLAVE ADDRESS
COMMAND CODE
1
9
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
STOP
BY
MASTER
ACKNOWLEDGE BY
SLAVE
ACKNOWLEDGE BY
SLAVE
FRAME 3
DATA BYTE
FRAME N
DATA BYTE
Figure 18. General I2C Write Timing Diagram
9
9
1
1
SCL
SDA
0
0
ADRA ADRB R/W
D7
D6
D5
1
D4
D3
D2
D1
D0
1
1
1
ACKNOWLEDGE BY
SLAVE
ACKNOWLEDGE BY
MASTER
START BY MASTER
FRAME 1
FRAME 2
SLAVE ADDRESS
DATA BYTE
1
9
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
STOP
BY
MASTER
ACKNOWLEDGE BY
MASTER
NO ACKNOWLEDGE
FRAME 3
DATA BYTE
FRAME N
DATA BYTE
Figure 19. General I2C Read Timing Diagram
tHD;STA
tLOW
tR
tF
SCL
tHIGH
tSU;STA
tSU;STO
tHD;STA
tSU;DAT
tHD;DAT
SDA
tBUF
S
P
P
S
Figure 20. Serial Bus Timing Diagram
Rev. B | Page 11 of 20
ADM1192
WRITE AND READ OPERATIONS
The I2C specification defines several protocols for different
types of read and write operations. The operations used in the
ADM1192 are discussed in this section. Table 6 shows the
abbreviations used in the command diagrams (see Figure 21
to Figure 26).
WRITE COMMAND BYTE
In the write command byte operation, the master device sends
a command byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
write bit (low).
Table 6. I2C Abbreviations
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB = 1 indicates an
extended register write (see the Write Extended Command
Byte section).
5. The slave asserts an acknowledge on SDA.
6. The master asserts a stop condition on SDA to end the
transaction.
Abbreviation
Condition
Start
Stop
Read
Write
S
P
R
W
A
N
Acknowledge
No acknowledge
1
2
3
4
5
6
QUICK COMMAND
SLAVE
ADDRESS
COMMAND
BYTE
S
W A
A
P
The quick command operation allows the master to check if the
slave is present on the bus, as follows:
Figure 22. Write Command Byte
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master asserts a stop condition on SDA to end the
transaction.
The seven LSBs of the command byte are used to configure and
control the ADM1192. Table 7 provides details of the function
of each bit.
1
2
3
4
SLAVE
ADDRESS
S
W A
P
Figure 21. Quick Command
Table 7. Command Byte Operations
Bit Default Name Function
LSB, set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1192 asserts an acknowledge and returns all 0s in the returned data.
Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
C0
C1
0
0
V_CONT
V_ONCE
C2
C3
C4
0
0
0
I_CONT
I_ONCE
VRANGE
Set to convert current continuously. If readback is attempted before the first conversion is complete,
the ADM1192 asserts an acknowledge and returns all 0s in the returned data.
Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1 voltage
divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the VCC pin for
an ADC full-scale result is 26.52 V for VRANGE = 0 and 6.65 V for VRANGE = 1.
C5
C6
0
0
N/A
Unused.
STATUS_RD Status Read. When this bit is set, the data byte read back from the ADM1192 is the status byte. This contains
the status of the device alerts. See Table 15 for full details of the status byte.
Rev. B | Page 12 of 20
ADM1192
WRITE EXTENDED COMMAND BYTE
7. The slave asserts an acknowledge on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:
1
2
3
4
5
6
7
8
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
write bit (low).
EXTENDED
COMMAND
BYTE
SLAVE
REGISTER
ADDRESS
S
W A
A
A
P
ADDRESS
Figure 23. Write Extended Byte
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends the register address byte. The MSB of this
byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Table 8). All other bits should be set to 0.
5. The slave asserts an acknowledge on SDA.
6. The master sends the extended command byte (refer to
Table 9, Table 10, and Table 11).
Table 9, Table 10, and Table 11 provide the details of each
extended register.
Table 8. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0 Extended Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
ALERT_EN
ALERT_TH
CONTROL
Table 9. ALERT_EN Register Operations
Bit
Default Name
Function
0
1
0
0
EN_ADC_OC1
EN_ADC_OC4
LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the
ALERT_TH register.
2
3
4
1
0
0
EN_OC_ALERT Enables the OC_ALERT register. If an overcurrent condition is present and the TIMER pin charges to 1.3 V, the
OC_ALERT register captures and latches this condition.
EN_OFF_ALERT Enables an alert if the hot swap operation is turned off by an operation that writes the SWOFF bit high.
This allows a software override of the ALERT output and turns on a P-channel FET controlled by ALERT.
CLEAR
Clears the OC_ALERT and ADC_ALERT status bits in the status register. The value of these bits can
immediately change if the source of the alert is not cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.
Table 10. ALERT_TH Register Operations
Bit
Default
Function
[7:0] FF
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
value corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
Default Name
Function
0
0
SWOFF
LSB, forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. B | Page 13 of 20
ADM1192
For cases where the master is reading voltage only or current
only, two data bytes are read and Step 7 and Step 8 are not required.
READ VOLTAGE AND/OR CURRENT DATA BYTES
Depending on how the device is configured, ADM1191 can be
set up to provide information in three ways after a conversion
(or conversions): voltage and current readback, voltage only
readback, and current only read back. See the Write Command
Byte section for more details.
1
2
3
4
5
6
7
8
9 10
SLAVE
ADDRESS
S
R
A
DATA 1
A
DATA 2
A
DATA 3
N
P
Figure 24. Three-Byte Read from ADM1192
Voltage and Current Readback
1
2
3
4
5
6
7
8
The ADM1192 digitizes both voltage and current. Three bytes
are read back in the format shown in Table 12.
SLAVE
ADDRESS
S
R
A
DATA 1
A
DATA 2
N
P
Table 12. Voltage and Current Readback Format
Figure 25. Two-Byte Read from ADM1192
Byte Contents B7
B6
B5 B4 B3 B2 B1 B0
Converting ADC Codes to Voltage and Current Readings
1
2
3
Voltage
MSBs
Current
MSBs
V11 V10 V9 V8 V7 V6 V5 V4
Equation 1 and Equation 2 can be used to convert ADC codes
representing voltage and current from the ADM1175 12-bit
ADC into actual voltage and current values.
I11
V3
I10
V2
I9
I8
I7
I6
I2
I5
I1
I4
I0
LSBs
V1 V0 I3
Voltage = (VFULLSCALE/4096) × Code
where:
FULLSCALE = 6.65 V (7:2 range) or 26.52 V (14:1 range).
(1)
Voltage Readback
V
The ADM1192 digitizes voltage only. Two bytes are read back in
the format shown in Table 13.
Code is the ADC voltage code read from the device
(Bit V11 to Bit V0).
Current = ((IFULLSCALE/4096) × Code)/Sense Resistor
(2)
Table 13. Voltage Only Readback Format
where:
Byte Contents
B7 B6 B5 B4 B3 B2 B1 B0
Voltage MSBs V11 V10 V9 V8 V7 V6 V5 V4
Voltage LSBs V3 V2 V1 V0
I
FULLSCALE = 105.84 mV.
Code is the ADC current code read from the device
1
2
0
0
0
0
(Bit I11 to Bit I0).
Current Readback
Read Status Register
The ADM1192 digitizes current only. Two bytes are read back
in the format shown in Table 14.
A single register of status data can also be read from the
ADM1192 as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives the status byte.
Table 14. Current Only Readback Format
Byte Contents
B7 B6 B5 B4 B3 B2 B1 B0
1
2
Current MSBs I11 I10 I9 I8 I7 I6
Current LSBs I3 I2 I1 I0
I5
0
I4
0
0
0
5. The master asserts an acknowledge on SDA.
The following series of events occurs when the master receives
three bytes (voltage and current data) from the slave device:
1
2
3
4
5
SLAVE
ADDRESS
STATUS
BYTE
S
R
A
A
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
read bit (high).
Figure 26. Status Read from ADM1192
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives the first data byte.
5. The master asserts an acknowledge on SDA.
6. The master receives the second data byte.
7. The master asserts an acknowledge on SDA.
8. The master receives the third data byte.
9. The master asserts a no acknowledge on SDA.
10. The master asserts a stop condition on SDA, and the
transaction ends.
Table 15 shows the ADM1192 STATUS registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 (the
CLEAR bit) of the ALERT_EN register.
Rev. B | Page 14 of 20
ADM1192
Table 15. Status Byte Operations
Bit Name
Function
0
1
2
ADC_OC
An ADC-based overcurrent comparison has been detected on the last three conversions.
ADC_ALERT An ADC-based overcurrent trip has occurred, causing the alert. Cleared by writing to Bit 4 of the ALERT_EN register.
OC
An overcurrent condition is present (that is, the output of the current sense amplifier is greater than the voltage on the
SETV input).
3
OC_ALERT
An overcurrent condition has caused the ALERT block to latch a fault, and the ALERT output has asserted. Cleared by
writing to Bit 4 of the ALERT_EN register.
4
5
OFF_STATUS Set to 1 by writing to the SWOFF bit of the CONTROL register.
OFF_ALERT
An alert has been caused by the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.
Rev. B | Page 15 of 20
ADM1192
APPLICATIONS INFORMATION
ALERT OUTPUT
SETV PIN
The ALERT output is an open-drain pin with 30 V tolerance.
There are two uses for this output.
The SETV pin allows the user to adjust the current level that
trips the ALERT output. The output of the current sense amplifier
is compared with the voltage driven onto the SETV pin. If the
current sense amplifier output is higher than the SETV voltage,
the output of the comparator asserts. By driving a different voltage
onto the SETV pin, the ADM1192 detects an overcurrent condition
at a different current level, with a gain of 18. See Figure 12 for
an illustration of this relationship.
Overcurrent Flag
The ALERT pin can be connected to the general-purpose logic
input of a controller. During normal operation, the ADM1192
drives this output low. When an overcurrent condition occurs,
the output asserts high. An external pull-up resistor should
be used.
I
LOAD
R
SENSE
3.15V TO 26V
R
SENSE
VCC
SENSE
ADM1192
VCC
SENSE
ALERT
CONTROLLER
INTERRUPT
P = VI
A
CURRENT
SENSE
ADM1192
AMPLIFIER
SDA
SDA
SCL
SETV
SCL
APPLIED
VOLTAGE
ALERT
CLRB
ALERT
CLRB
SETV
TIMER
60µA
COMPARATOR
ADR
GND
Figure 27. Using the ALERT Output as an Interrupt
TIMER
1.3V
Implementing a Basic Hot Swap Circuit
A basic P-channel FET hot swap circuit can be created. The
ALERT output should be connected to the GATE pin of a P-
channel FET connected in series with the power path. A pull-up
from GATE to source ensures that the P-channel FET GATE is
pulled up and the device held off as soon as power is applied.
When the ADM1192 powers up, the GATE is pulled low by the
ALERT output. A capacitor on the TIMER pin determines the
slew rate of the GATE pin at startup. Note that if a current fault
occurs during the operation, the ALERT output asserts high,
turning off the P-channel FET.
Figure 29. SETV Operation
When the output of the SETV comparator asserts, this tells the
ALERT block to begin charging the external TIMER capacitor
with a 60 μA charging current. When the voltage on the TIMER
capacitor reaches 1 V, the charging cycle is complete. The ALERT
output then asserts (goes high). Different values of TIMER
capacitor generate different time delays between current faults
occurring and the ALERT output asserting. When using the
ALERT output to implement a hot swap circuit, the TIMER
capacitor should be chosen to generate a large enough startup
delay to allow the maximum inrush current to completely
charge up the load without tripping an ALERT fault.
3.15V TO 26V
R
P-CHANNEL FET
SENSE
VCC
SENSE
ALERT
CONTROLLER
P = VI
ADM1192
SDA
SDA
SCL
SETV
SCL
CLRB
CLRB
TIMER
ADR
GND
Figure 28. P-Channel FET Hot Swap Implementation
Rev. B | Page 16 of 20
ADM1192
SENSE RESISTOR
KELVIN SENSE RESISTOR CONNECTION
When using a low value sense resistor for high current measure-
ment, the problem of parasitic series resistance can arise. The
lead resistance can be a substantial fraction of the rated resistance,
making the total resistance a function of lead length. This problem
can be avoided by using a Kelvin sense connection. This type of
connection separates the current path through the resistor and
the voltage drop across the resistor. Figure 30 shows the correct
way to connect the sense resistor between the VCC pin and the
SENSE pin of the ADM1192.
CURRENT
FLOW FROM
SUPPLY
CURRENT
FLOW TO
LOAD
KELVIN SENSE TRACES
VCC
SENSE
ADM1192
Figure 30. Kelvin Sense Connections
Rev. B | Page 17 of 20
ADM1192
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
6
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 31. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1192-1ARMZ-R71 −40°C to +85°C
EVAL-ADM1192EBZ1
Temperature Range
Package Description
10-Lead MSOP
Evaluation Board
Package Option
Branding
RM-10
M5M
1 Z = RoHS Compliant Part.
Rev. B | Page 18 of 20
ADM1192
NOTES
Rev. B | Page 19 of 20
ADM1192
NOTES
Purchase of licensed I2C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05754-0-2/08(B)
Rev. B | Page 20 of 20
相关型号:
EVAL-ADM3052EBZ
Isolated CAN Transceiver with Integrated High Voltage, Bus-Side, Linear Regulator
ADI
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