EVAL-ADM3252EEBZ [ADI]
Isolated, Dual Channel, RS-232 Line Driver/Receiver; 隔离，双通道， RS - 232线路驱动器/接收器
| 型号： | EVAL-ADM3252EEBZ |
| 厂家： | 
ADI |
| 描述： | Isolated, Dual Channel, RS-232 Line Driver/Receiver |
| 文件： | 总16页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated, Dual Channel, RS-232 Line
Driver/Receiver
Data Sheet
ADM3252E
FEATURES
FUNCTIONAL BLOCK DIAGRAM
10µF
C1
0.1µF
16V
C3
0.1µF
10V
C2
0.1µF
16V
C4
0.1µF
16V
2.5 kV fully isolated (power and data) RS-232 transceiver
isoPower integrated, isolated dc-to-dc converter
Operational from single 3.3 V or 5 V supply
460 kbps data rate
0.1µF
C1+ C1– V+
V
C2+ C2– V–
VOLTAGE
ISO
ADM3252E
2 × Tx and 2 × Rx channels
VOLTAGE
DOUBLER
INVERTER
Meets EIA/TIA-232E specifications
ESD protection to IEC 1000-4-2 (801.2) on RINx and TOUTx pins
Contact discharge: 8 kV
V
CC
RECT
REG
OSC
Air gap discharge: 15 kV
0.1 μF charge pump capacitors
R
R
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
R
T
*
IN1
R
T
OUT1
T
IN1
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals (pending)
UL recognition
2500 V rms for 1 minute per UL 1577
VDE certificate of conformity
OUT1
R
*
R
OUT2
IN2
T
T
IN2
T
OUT2
IEC 60747-5-2 (VDE 0884, Part 2)
GND
GND
ISO
VIORM = 560 V peak
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUTS.
CSA Component Acceptance Notice #5A
Operating temperature range: −40°C to +85°C
44-ball chip scale package ball grid array (CSP_BGA)
Figure 1.
APPLICATIONS
Isolated RS-232 interface
High noise data communications
Industrial communications
Industrial/telecommunications diagnostic ports
Medical equipment
isoPower technology in the ADM3252E uses high frequency
GENERAL DESCRIPTION
switching elements to transfer power through its transformer.
Special care must be taken during printed circuit board (PCB)
layout to meet emissions standards. Refer to the AN-0971
Application Note, Recommendations for Control of Radiated
Emissions with isoPower Devices, for details on board layout
considerations.
The ADM3252E is a high speed, 2.5 kV, fully isolated, dual-
channel RS-232/V.28 transceiver device that is operational from
a single 3.3 V or 5 V power supply. Because of high ESD protection
on the RIN1, RIN2, TOUT1, and TOUT2 pins, the ADM3252E is ideally
suited for operation in electrically harsh environments or where
RS-232 cables are frequently plugged and unplugged.
The ADM3252E conforms to the EIA/TIA-232E and ITU-T V.28
specifications and operates at data rates of up to 460 kbps. Four
external 0.1 μF charge pump capacitors are used for the voltage
doubler/inverter, permitting operation from a single 3.3 V or 5 V
supply. The ADM3252E is available in a 44-ball, chip scale
package ball grid array (CSP_BGA) and is specified over the
−40°C to +85°C temperature range.
The ADM3252E provides four independent isolation channels
using the integrated and isolated power of isoPower™. There is
no requirement to use a separate isolated dc-to-dc converter. Chip
scale transformer iCoupler® technology from Analog Devices, Inc.,
is used for both the isolation of the logic signals and the integrated
dc-to-dc converter. The result is a total isolation solution.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
ADM3252E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Charge Pump Voltage Converter ............................................. 11
3.3 V Logic to EIA/TIA-232E Transmitter ............................. 11
EIA/TIA-232E to 3.3 V Logic Receiver................................... 11
High Baud Rate........................................................................... 11
Applications Information .............................................................. 12
PCB Layout ................................................................................. 12
Start-Up Behavior....................................................................... 12
DC Correctness and Magnetic Field Immunity..................... 13
Power Considerations................................................................ 13
Thermal Analysis ....................................................................... 14
Insulation Lifetime..................................................................... 14
Packaging and Ordering Information ......................................... 15
Outline Dimensions................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Package Characteristics ............................................................... 4
Regulatory Information (Pending) ............................................ 4
Insulation and Safety-Related Specifications............................ 5
Absolute Maximum Ratings ....................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 10
Isolation of Power and Data...................................................... 10
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
ADM3252E
SPECIFICATIONS
All voltages are relative to their respective grounds, all minimum/maximum specifications apply over the entire recommended operating
range, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC CHARACTERISTICS
VCC Operating Voltage Range
UVLO Threshold
Rising
Falling
Input Supply Current, ICC
3.0
3.3
5.5
V
2.7
2.3
20
45
35
V
V
mA
mA
mA
V
Undervoltage lockout
35
75
60
No load
RL = 3 kΩ, VCC = 3.0 V to 5.5 V
RL = 3 kΩ, VCC = 3.3 V
IISO = 0 μA
VISO Output
3.3
VISO Maximum Load Current, IISO(MAX)
LOGIC
15
mA
Transmitter Inputs, TIN1 and TIN2
Logic Input Current
Logic Input Threshold
Low
−10
+0.01
+10
μA
0.3 × VCC
V
V
High
0.7 × VCC
Receiver Outputs, ROUT1 and ROUT2
Logic High Output
VCC − 0.2
VCC − 0.5
VCC
VCC − 0.3
0.0
V
V
V
V
IROUTH = −20 μA
IROUTH = −4 mA
IROUTH = 20 μA
IROUTH = 4 mA
Logic Low Output
0.1
0.4
0.2
RS-232
Receiver Inputs, RIN1 and RIN2
EIA-232 Input
Voltage Range1
Threshold Low
Threshold High
Hysteresis
−30
0.8
+30
2.0
7
V
V
V
V
1.0
1.5
0.45
5
Resistance
3
kΩ
Transmitter Outputs, TOUT1 and TOUT2
Output Voltage Swing (RS-232)
Transmitter Output Resistance
Output Short-Circuit Current (RS-232)
TIMING CHARACTERISTICS
Maximum Data Rate
Receiver Propagation Delay
tPHL
5.0
300
5.2
15
V
Ω
mA
RL = 3 kΩ to GND
VCC = 0 V, VISO = 0 V
460
kbps
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF
RL = 3 kΩ, CL = 1000 pF
0.4
0.4
0.3
30
1
1
1.2
μs
μs
μs
ns
tPLH
Transmitter Propagation Delay
Transmitter Skew
Receiver Skew
Transition Region Slew Rate
300
10
ns
V/μs
Measured from +3 V to −3 V or −3 V to +3 V,
VCC = +3.3 V, RL = 3 kΩ, CL = 1000 pF, TA = 25°C
Rev. 0 | Page 3 of 16
ADM3252E
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time, tR/tF (10% to 90%)
Common-Mode Transient Immunity
Logic High Output2
2.5
ns
CL = 15 pF, CMOS signal levels
25
25
kV/μs VCM = 1 kV, transient magnitude = 800 V
kV/μs VCM = 1 kV, transient magnitude = 800 V
Mbps
Logic Low Output2
Refresh Rate
1.0
1 Guaranteed by design.
2 VCM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common-mode voltage is slewed. The common-mode voltage slew
rates apply to both rising and falling common-mode edges.
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
PACKAGE CHARACTERISTICS
Resistance (Input-to-Output)
Capacitance (Input-to-Output)
RI-O
CI-O
1012
2.2
Ω
pF
f = 1 MHz
Input Capacitance
IC Junction-to-Air Thermal Resistance
CI
θJA
4.0
40
pF
°C/W
REGULATORY INFORMATION (PENDING)
Table 3.
UL
CSA
VDE
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component Acceptance
Notice #5A
Certified according to IEC 60747-5-2 (VDE 0884
Part 2):2003-012
Single Protection, 2500 V rms
Isolation Voltage
Testing was conducted per CSA 60950-1-07 and
IEC 60950-1 2nd ed. at 2.5 kV rated voltage
Basic insulation, 560 V peak
Basic insulation at 400 V rms (565 V peak)
working voltage
1 In accordance with UL 1577, each ADM3252E is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 15 µA).
2 In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADM3252E is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial
discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval.
Rev. 0 | Page 4 of 16
Data Sheet
ADM3252E
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Symbol Value Unit
Test Conditions
INSULATION AND SAFETY
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
7.6
V rms
mm
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
L(I01)
L(I02)
Minimum External Tracking (Creepage)
7.6
mm
Minimum Internal Gap (Internal Clearance)
0.017 mm
Distance through insulation
Tracking Resistance (Comparative Tracking
Index)
CTI
>175
V
Isolation Group
llla
Rev. 0 | Page 5 of 16
ADM3252E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VCC, VISO
V+
V−
−0.3 V to +6 V
(VCC − 0.3 V) to +13 V
−13 V to +0.3 V
Input Voltages
TIN1, TIN2
−0.3 V to (VCC + 0.3 V)
30 V
RIN1, RIN2
Output Voltages
TOUT1, TOUT2
ROUT1, ROUT2
15 V
ESD CAUTION
−0.3 V to (VCC + 0.3 V)
Short-Circuit Duration
TOUT1, TOUT2
Power Dissipation
Operating Temperature Range
Industrial
Storage Temperature
Pb-Free Temperature (Soldering, 30 sec)
Storage Temperature Prior to Soldering
Continuous
750 mW
−40°C to +85°C
−65°C to +150°C
260°C
30°C/60% RH max for
168 hours (MSL3)
Bake Temperature (If Required)
125°C + 5°C/−0°C for
48 hours
Rev. 0 | Page 6 of 16
Data Sheet
ADM3252E
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
NC
V
V
V
DNC
V+
A
B
C
D
E
F
CC
CC
ISO
ISO
ISO
V
V
V
CC
GND
C1+
GND
GND
GND
GND
GND
GND
T
T
GND
GND
GND
IN1
OUT1
ISO
ISO
ISO
ADM3252E
GND
C1–
TOP VIEW
(Not to Scale)
T
T
IN2
OUT2
BALLS IN COLUMN 3 TO
COLUMN 9 REMOVED
FOR ISOLATION
GND
C2+
C2–
G
H
J
R
R
GND
GND
GND
GND
OUT1
IN1
ISO
ISO
ISO
ISO
GND GND
V–
R
R
GND
OUT2
IN2
K
L
NC GND
DNC
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description
A1, L1
A2, B1, B2
NC
VCC
No Connect. These pins are left unconnected.
Power Supply Input. A 10 μF and a 0.1 μF decoupling capacitor are required between VCC and ground.
The device requires a voltage between 3.0 V and 5.5 V.
A10, B10, C10
VISO
Supply Voltage for Isolator Secondary Side. A 10 μF and a 0.1 μF decoupling capacitor are required
between VISO and ground.
A11, L11
B11
DNC
V+
Do Not Connect. Do not connect or route anything through these pins.
Internally Generated Positive Supply.
C1, C2, D2, E1, E2,
F2, G1, G2, H2, J1,
J2, K2, L2
GND
Ground Reference for Logic Side.
C11, E11, G10, G11
C1+, C1−,
C2−, C2+
Positive and Negative Connections for Charge Pump Capacitors. External Capacitors C1 and C2 are
connected between these pins; a 0.1 μF capacitor is recommended, but larger capacitors of up to 10 μF
can be used.
D1
TIN1
Transmitter (Driver) Input 1. A logic low on this input generates a high on TOUT1; a logic high on this
input generates a low on TOUT1. This pin accepts TTL/CMOS levels. This is a high impedance input pin;
therefore, it should not be left floating.
D10, E10, F10, H10, GNDISO
J10, K10, L10
Ground Reference for Isolated RS-232 Side.
D11
F1
TOUT1
TIN2
Transmitter (Driver) Output 1. This pin outputs RS-232 signal levels.
Transmitter (Driver) Input 2. A logic low on this input generates a high on TOUT2; a logic high on this
input generates a low on TOUT2. This pin accepts TTL/CMOS levels. This is a high impedance input pin;
therefore, it should not be left floating.
F11
H1
H11
TOUT2
ROUT1
RIN1
Transmitter (Driver) Output 2. This pin outputs RS-232 signal levels.
Receiver Output 1. This pin outputs CMOS logic levels.
Receiver Input 1. A logic low on this input generates a high on ROUT1; a logic high on this input generates a
low on ROUT1. This input pin accepts RS-232 signal levels and has an internal 5 kΩ pull-down resistor.
J11
K1
K11
V−
ROUT2
RIN2
Internally Generated Negative Supply.
Receiver Output 2. This pin outputs CMOS logic levels.
Receiver Input 2. A logic low on this input generates a high on ROUT2; a logic high on this input generates a
low on ROUT2. This input pin accepts RS-232 signal levels and has an internal 5 kΩ pull-down resistor.
Rev. 0 | Page 7 of 16
ADM3252E
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
30
120
100
80
60
40
20
0
R
= 3kΩ
L
25
V
= 3.3V
V
= 3.3V (1nF)
CC
CC
20
15
10
5
V
= 5V (1nF)
CC
V
= 5V
CC
V
= 3.3V (220pF)
CC
V
= 5V (220pF)
CC
0
0
100
200
300
400
500
1.2
5.5
–50
–25
0
25
50
75
100
DATA RATE (kbps)
TEMPERATURE (°C)
Figure 6. Supply Current vs. Data Rate
Figure 3. Supply Current vs. Temperature, No Load
8
6
70
65
60
55
50
45
40
35
30
R
= 3kΩ
L
HIGH
460kbps
1Mbps
4
V
= 3.3V
CC
2
0
–2
–4
–6
–8
V
= 5V
CC
1Mbps
LOW
460kbps
0
0.2
0.4
0.6
0.8
1.0
–50
–25
0
25
50
75
100
LOAD CAPACITANCE (nF)
TEMPERATURE (°C)
Figure 7. Transmit Output vs. Load Capacitance
Figure 4. Supply Current vs. Temperature, RL = 3 kΩ, CL = 1 nF
8
6
120
100
80
60
40
20
0
Tx OUTPUT HIGH, NO LOAD
R
= 3kΩ
L
460kbps (3.3V)
230kbps (3.3V)
Tx OUTPUT HIGH, R = 3kΩ
L
4
2
0
460kbps (5V)
230kbps (5V)
–2
–4
–6
–8
Tx OUTPUT LOW, R = 3kΩ
L
Tx OUTPUT LOW, NO LOAD
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
V
(V)
LOAD CAPACITANCE (nF)
CC
Figure 5. Supply Current vs. Load Capacitance
Figure 8. Transmit Output vs. VCC
Rev. 0 | Page 8 of 16
Data Sheet
ADM3252E
4
T
/T
(2V/DIV)
IN1 IN2
3
2
1
0
T
T
/R
(5V/DIV)
(5V/DIV)
OUT1 IN1
RISING
/R
OUT2 IN2
FALLING
R
R
(2V/DIV)
OUT1
(2V/DIV)
OUT2
TIME (1µs/DIV)
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
CC
Figure 9. Transmitter Input Threshold vs. VCC
Figure 12. 460 kbps Data Transmission, Driver Outputs Tied to
Receiver Inputs
3.0
2.5
2.0
1.5
1.0
0.5
0
NO LOAD
INPUT RISING
FULLY LOADED RS-232
INPUT FALLING
2
CH2 1.00V
M500µs
A
CH2
340mV
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 10. Receiver Input Threshold vs. Temperature
Figure 13. Typical Output Voltage Start-Up Transient, VCC = 3.3 V
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2 Tx INPUTS @ 460kbps
3kΩ, 1nF LOADS
NO LOAD
FULLY LOADED RS-232
2
CH2 1.00V
M500µs
A
CH2
340mV
0
20
40
60
80
100
LOAD CURRENT (mA)
Figure 11. VISO vs. VISO Load Current
Figure 14. Typical Output Voltage Start-Up Transient, VCC = 5 V
Rev. 0 | Page 9 of 16
ADM3252E
Data Sheet
THEORY OF OPERATION
10µF
C1
0.1µF
16V
C3
0.1µF
10V
C2
0.1µF
16V
C4
0.1µF
16V
0.1µF
C1+ C1– V+
V
C2+ C2– V–
VOLTAGE
ISO
ADM3252E
VOLTAGE
DOUBLER
INVERTER
V
CC
RECT
REG
OSC
R
R
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
R
*
IN1
R
T
OUT1
T
T
IN1
OUT1
R
*
R
OUT2
IN2
T
T
IN2
T
OUT2
GND
GND
ISO
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUTS.
Figure 15. Functional Block Diagram
The ADM3252E is a high speed, 2.5 kV, fully isolated, dual-
channel RS-232 transceiver device that operates from a single
power supply.
Similarly, the receiver input (RINx) accepts RS-232 signal levels
referenced to isolated ground (GNDISO). The RINx input is
inverted and coupled across the isolation barrier to appear at
the ROUTx pin, referenced to logic ground (GND).
The internal circuitry consists of the following main sections:
The digital signals are transmitted across the isolation barrier
using iCoupler technology. Chip scale transformer windings
couple the digital signals magnetically from one side of the
barrier to the other. Digital inputs are encoded into waveforms
that are capable of exciting the primary transformer of the winding.
At the secondary winding, the induced waveforms are decoded
into the binary value that was originally transmitted.
3.0V TO 5.5V
• Isolation of power and data
• Charge pump voltage converter
• 3.3 V logic to EIA/TIA-232E transmitter
• EIA/TIA-232E to 3.3 V logic receiver
ISOLATION OF POWER AND DATA
The ADM3252E incorporates a dc-to-dc converter section,
which works on principles that are common to most power
supply designs. VCC power is supplied to an oscillating circuit
that switches current into a chip scale air core transformer. Power
is transferred to the secondary side where it is rectified to a high
dc voltage. The power is then linearly regulated to 3.3 V and
supplied to the secondary side data section and to the VISO pin.
V
V
CC
ISO
V+
C3
0.1µF
10V
10µF 0.1µF
0.1µF
10µF
+
+
ADM3252E
C1+
C1–
C1
0.1µF
16V
R
R
T
CMOS OUTPUT
CMOS OUTPUT
CMOS INPUT
CMOS INPUT
OUT1
OUT2
EIA/TIA-232E OUTPUT
EIA/TIA-232E OUTPUT
EIA/TIA-232E INPUT
EIA/TIA-232E INPUT
T
T
OUT1
OUT2
Because the oscillator runs at a constant high frequency
independent of the load, excess power is internally dissipated
in the output voltage regulation process. Limited space for
transformer coils and components adds to the internal power
dissipation. This results in low power conversion efficiency.
IN1
IN2
R
T
IN1
R
IN2
C2+
C2
+
0.1µF
16V
ISOLATION
BARRIER
C2–
V–
C4
The transmitter input (TINx) accepts TTL/CMOS input levels.
The driver input signal that is applied to the TINx pins is
referenced to logic ground (GND). It is coupled across the
isolation barrier, inverted, and then appears at the transceiver
section, referenced to isolated ground (GNDISO).
0.1µF
16V
+
GND
GND
ISO
Figure 16. Typical Operating Circuit
Rev. 0 | Page 10 of 16
Data Sheet
ADM3252E
CHARGE PUMP VOLTAGE CONVERTER
3.3 V LOGIC TO EIA/TIA-232E TRANSMITTER
The charge pump voltage converter consists of a 200 kHz
oscillator and a switching matrix. The converter generates a
6.6 V supply from the 3.3 V input level. This is achieved in
two stages by using a switched capacitor technique, as shown
in Figure 17 and Figure 18.
The transmitter driver converts the 3.3 V logic input levels
into RS-232 output levels. When driving an RS-232 load with
VCC = 3.3 V, the output voltage swing is typically 6.6 V.
EIA/TIA-232E TO 3.3 V LOGIC RECEIVER
The receiver is an inverting level shifter that accepts the RS-232
input level and translates it into a 3.3 V logic output level. The
input has an internal 5 kΩ pull-down resistor to ground and is
protected against overvoltages of up to 30 V. An unconnected
input is pulled to 0 V by the internal 5 kΩ pull-down resistor,
resulting in a Logic 1 output level for an unconnected input or
for an input connected to GND. The receiver has a Schmitt
trigger input with a hysteresis level of 0.1 V. This ensures error
free reception for both a noisy input and for an input with slow
transition times.
S1
S3
V
V+ = 2V
ISO
ISO
+
+
C1
C3
S2
S4
V
GND
ISO
INTERNAL
OSCILLATOR
Figure 17. Charge Pump Voltage Doubler
S1
S3
V+
GND
FROM
VOLTAGE
DOUBLER
ISO
+
+
C2
C4
S2
S4
V– = –(V+)
GND
ISO
HIGH BAUD RATE
INTERNAL
OSCILLATOR
The ADM3252E offers high slew rates, permitting data trans-
mission at rates well in excess of the EIA/TIA-232E specifications.
Higher data rates are possible when running at reduced RS-232
capacitive load levels. A smaller capacitive load, in effect, limits
the cable length. See Figure 7 for transmit output voltage levels
at 1 Mbps and Figure 19 for a scope plot at 1 Mbps.
Figure 18. Charge Pump Voltage Inverter
In the first stage, the 3.3 V input supply is doubled to 6.6 V using
C1 as the charge storage element. In the second stage, the +6.6 V
level is inverted to generate −6.6 V using C2 as the storage element.
In Figure 17, C3 is connected between V+ and VISO, but it is
equally effective if C3 is connected between V+ and GNDISO
.
Use Capacitor C3 and Capacitor C4 to reduce the output ripple.
Their values are not critical and can be increased, if needed.
Larger capacitors (up to 10 µF) can be used in place of C1, C2,
C3, and C4.
Tx INPUT
1
2
Tx OUTPUT
R
C
= 3kΩ
= 470pF
L
L
CH1 2.00V CH2 2.00V
M400ns
A
CH2
680mV
Figure 19. Scope Plot, 1 Mbps Operation
Rev. 0 | Page 11 of 16
ADM3252E
Data Sheet
APPLICATIONS INFORMATION
The power supply section of the ADM3252E uses a 180 MHz
PCB LAYOUT
oscillator frequency to pass power through its chip scale
transformers. Operation at these high frequencies may raise
concerns about radiated emissions and conducted noise. PCB
layout and construction are very important tools for controlling
radiated emissions. Refer to the AN-0971 Application Note,
Recommendations for Control of Radiated Emissions with isoPower
Devices, for extensive guidance on radiation mechanisms and
board layout considerations.
The ADM3252E requires no external circuitry for its logic
interfaces. Power supply bypassing is required at the input
and output supply pins (see Figure 20). Bypass capacitors are
conveniently connected between Pin B1 and Pin C1 for VCC and
between Pin C10 and Pin D10 for VISO
.
A1 BALL
CORNER
0.1µF
11 10
9
8
7
6
5
4
3
2
1
VIA TO GND
ISO
A
B
C
D
E
F
C3
START-UP BEHAVIOR
0.1µF
The ADM3252E does not contain a soft start circuit. Therefore,
the start-up current and voltage behavior must be taken into
account when designing with this device.
C1
C2
C4
G
H
J
When power is applied to VCC, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached (approximately 2.7 V). The switching circuit drives
the maximum available power to the output until it reaches the
regulation voltage, which is where PWM control begins. The
amount of current and the time required to reach regulation
voltage depends on the load and the VCC slew rate.
VIA TO GND
ISO
K
L
Figure 20. Recommended Printed Circuit Board Layout
To suppress noise and reduce ripple, a parallel combination of at
least two capacitors is recommended. The recommended capacitor
values are 0.1 µF and 10 µF for both VCC and VISO. The smaller
capacitor must have a low ESR; best practice suggests use of a
ceramic capacitor. Do not exceed 2 mm for the total lead length
between both ends of the low ESR capacitor and the input power
supply pin.
With a fast VCC slew rate (200 µs or less), the peak current draws
up to 100 mA/V of VCC. The input voltage goes high faster than
the output can turn on; therefore, the peak current is proportional
to the maximum input voltage.
With a slow VCC slew rate (in the millisecond range), the input
voltage is not changing quickly when VCC reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VCC is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit.
Because it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipating into
the PCB through the ground pins. If the device is used at high
ambient temperatures, take care to provide a thermal path from
the ground pins to the PCB ground plane. The board layout in
Figure 20 shows enlarged pads for the GND and GNDISO pins.
The BGA balls are also grouped together to simplify layout and
routing. To significantly reduce the temperature inside the chip,
implement multiple vias from each of the pads to the ground
plane. The dimensions of the expanded pads are at the discre-
tion of the designer and the available board space.
When powering up the device, do not limit the current available
to the VCC power pin to less than 300 mA. The ADM3252E device
may not be able to drive the output to the regulation point if a
current limiting device clamps the VCC voltage during startup.
As a result, the ADM3252E device can draw large amounts of
current at low voltage for extended periods of time.
The output voltage of the ADM3252E device exhibits VISO
overshoot to approximately 4 V during startup (see Figure 13
and Figure 14). If this overshoot could potentially damage compo-
nents attached to VISO, a voltage limiting device, such as a Zener
diode, can be used to clamp the voltage.
In applications involving high common-mode transients,
ensure that board coupling across the isolation barrier is
minimized. Furthermore, design the board layout such that
any coupling that does occur equally affects all pins on a given
component side.
Rev. 0 | Page 12 of 16
Data Sheet
ADM3252E
For example, at a magnetic field frequency of 1 MHz, the
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is approximately
50% of the sensing threshold and does not cause a faulty output
transition. Similarly, if such an event occurs during a transmitted
pulse (and is of the worst-case polarity), the received pulse is
reduced from >1.0 V to 0.75 V, which is still well above the
0.5 V sensing threshold of the decoder.
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the trans-
former. The decoder is bistable and is, therefore, either set or
reset by the pulses, indicating input logic transitions.
In the absence of logic transitions at the input for more than
1 µs, periodic sets of refresh pulses (indicative of the correct
input state) are sent to ensure dc correctness at the output. If the
decoder receives no internal pulses for more than approximately
5 µs, the input side is assumed to be unpowered or nonfunctional,
in which case the isolator output is forced to a default state by
the watchdog timer circuit. This situation should occur in the
ADM3252E during power-up and power-down operations only.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the trans-
formers. Figure 22 expresses these allowable current magnitudes
as a function of frequency for selected distances. As shown in
Figure 22, the ADM3252E is extremely immune and can be
affected only by extremely large currents operated at high
frequency very close to the component. For example, at a
magnetic field frequency of 1 MHz, a 0.5 kA current placed
5 mm away from the ADM3252E is required to affect the
operation of the component.
The limitation on the ADM3252E magnetic field immunity is
set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to falsely set or reset
the decoder. The following analysis defines the conditions
under which this can occur.
1K
DISTANCE = 1m
The pulses at the transformer output have an amplitude of >1.0 V.
The decoder has a sensing threshold of about 0.5 V, thus estab-
lishing a 0.5 V margin in which induced voltages can be tolerated.
The voltage induced across the receiving coil is given by
100
10
DISTANCE = 100mm
2
V = (−dβ/dt)∑πrn ; n = 1, 2, … , N
1
where:
DISTANCE = 5mm
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
0.1
0.01
Given the geometry of the receiving coil internally and an
imposed requirement that the induced voltage be, at most, 50%
of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 21.
100
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 22. Maximum Allowable Current
for Various Current-to-ADM3252E Spacings
Note that in the presence of strong magnetic fields and high
frequencies, any loops formed by PCB traces may induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
10
1
POWER CONSIDERATIONS
0.1
The ADM3252E power input, data input channels on the primary
side, and data channels on the secondary side are all protected from
premature operation by undervoltage lockout (UVLO) circuitry.
Below the minimum operating voltage, the power converter holds
its oscillator inactive and all input channel drivers and refresh cir-
cuits are idle. Outputs remain in a high impedance state to prevent
transmission of undefined states during power-up and power-
down operations.
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 21. Maximum Allowable External Magnetic Flux Density
Rev. 0 | Page 13 of 16
ADM3252E
Data Sheet
During the application of power to VCC, the primary side circuitry
(logic side) is held idle until the UVLO preset voltage is reached.
At that time, the data channels are initialized to their default
low output states until they receive data pulses from the
secondary side (RS-232 side).
side inputs and the outputs are set to their default low value
before the secondary power reaches UVLO.
THERMAL ANALYSIS
The ADM3252E device consists of five internal die attached to a
PCB laminate. For the purposes of thermal analysis, the device is
treated as a thermal unit with the highest junction temperature
reflected in the θJA value from Table 2. By following the recommen-
dations in the PCB Layout section, thermal resistance to the PCB
decreases, thereby allowing increased thermal margin at high
ambient temperatures.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in the default low state because no
data comes from the secondary side inputs until secondary side
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insula-
tion degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADM3252E.
The secondary VISO voltage is below its UVLO limit at this point,
and the secondary side is not generating a regulation control
signal. The primary side power oscillator can free run under
these conditions, supplying the maximum amount of power to
the secondary side.
As the secondary side voltage rises to its regulation setpoint,
a large inrush current transient is present at VCC. Upon reaching
the regulation point, the regulation control circuit produces the
regulation control signal that modulates the oscillator on the
primary side. The VCC current is then reduced and it is propor-
tional to the load current. The duration of the inrush current
depends on the VISO loading conditions and on the current and
voltage available at the VCC pin.
The insulation lifetime of the ADM3252E depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 23, Figure 24, and Figure 25 illustrate these different
isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. In the
case of unipolar ac or dc voltage, the stress on the insulation is
significantly lower.
As the secondary side converter begins to accept power from
the primary side, the VISO voltage starts to rise. When the
secondary side UVLO is reached, the secondary side outputs
are initialized to their default low state until data is received
from the corresponding primary side input. It can take up to
1 µs after the secondary side is initialized for the state of the
output to correlate to the primary side input.
RATED PEAK VOLTAGE
0V
Figure 23. Bipolar AC Waveform
Secondary side inputs sample their states and transmit them to
the primary side. Outputs are valid about 1 µs after the secondary
side becomes active.
RATED PEAK VOLTAGE
Because the rate of charge on the secondary side power supply
is dependent on three factors: loading conditions, the input voltage,
and the selected output voltage level, take care that the design
allows the converter sufficient time to stabilize before valid data
is required.
0V
Figure 24. Unipolar AC Waveform
RATED PEAK VOLTAGE
When power is removed from VCC, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
0V
Figure 25. DC Waveform
The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is
reached and the outputs are placed in their high impedance
state, or the outputs detect a lack of activity from the primary
Rev. 0 | Page 14 of 16
Data Sheet
ADM3252E
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
12.10
A1 BALL
CORNER
12.00 SQ
11.90
A1 BALL
CORNER
11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
10.00
BSC SQ
G
1.00
H
J
K
L
1.00
REF
TOP VIEW
DETAIL A
BOTTOM VIEW
1.55
1.44
1.35
1.03
0.96
0.89
DETAIL A
0.70 REF
0.26 REF
0.48 NOM
0.43 MIN
0.70
0.60
0.50
COPLANARITY
0.20
SEATING
PLANE
BALL DIAMETER
COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1.
Figure 26. 44-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-44-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
Package Description
44-Ball CSP_BGA
Evaluation Board
Package Option
BC-44-1
ADM3252EABCZ
EVAL-ADM3252EEBZ
1 Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
ADM3252E
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10515-0-4/12(0)
Rev. 0 | Page 16 of 16
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