EVAL-ADuC7020QSZ [ADI]
Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU; 精密模拟微控制器， 12位模拟I / O ， ARM7TDMI MCU
| 型号： | EVAL-ADuC7020QSZ |
| 厂家： | 
ADI |
| 描述： | Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU |
| 文件： | 总104页 (文件大小：1747K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Analog Microcontroller, 12-Bit
Analog I/O, ARM7TDMI MCU
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
On-chip peripherals
FEATURES
UART, 2× I2C® and SPI serial I/O
Up to 40-pin GPIO port1
4× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
3-phase, 16-bit PWM generator1
Programmable logic array (PLA)
External memory interface, up to 512 kB1
Power
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 16 ADC channels1
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
Up to 4 DAC outputs available1
On-chip voltage reference
On-chip temperature sensor ( 3°C)
Voltage comparator
Specified for 3 V operation
Active mode: 11 mA @ 5 MHz, 40 mA @ 41.78 MHz
Packages and temperature range
From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP1
Fully specified for –40°C to +125°C operation
Tools
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator ( 3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Low cost QuickStart™ development system
Full third-party support
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
Software-triggered in-circuit reprogrammability
FUNCTIONAL BLOCK DIAGRAM
12-BIT
DAC
DAC0
DAC1
DAC2
1MSPS
ADC0 TO ADC4,
ADC12 TO ADC14
MUX
12-BIT ADC
12-BIT
DAC
ADuC7019
ADC15
TEMP
SENSOR
12-BIT
DAC
CMP0
CMP1
BAND GAP
REF
CMP
OUT
V
REF
3-PHASE
OSC
PWM
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
XCLKO
(SEE NOTE 1)
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
POR
2
UART, SPI, I C
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 1.
1 Depending on part model. See Ordering Guide for more information.
Rev. F
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2005-2013 Analog Devices, Inc. All rights reserved.
www.analog.com
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Calibration................................................................................... 50
Temperature Sensor ................................................................... 50
Band Gap Reference................................................................... 50
Nonvolatile Flash/EE Memory ..................................................... 51
Programming.............................................................................. 51
Security ........................................................................................ 52
Flash/EE Control Interface ....................................................... 52
Execution Time from SRAM and Flash/EE............................ 54
Reset and Remap........................................................................ 54
Other Analog Peripherals.............................................................. 56
DAC.............................................................................................. 56
Power Supply Monitor............................................................... 57
Comparator................................................................................. 57
Oscillator and PLL—Power Control........................................ 58
Digital Peripherals.......................................................................... 61
3-Phase PWM............................................................................. 61
Description of the PWM Block................................................ 62
General-Purpose Input/Output................................................ 67
Serial Port Mux........................................................................... 70
UART Serial Interface................................................................ 70
Serial Peripheral Interface......................................................... 74
I2C-Compatible Interfaces......................................................... 76
Programmable Logic Array (PLA)........................................... 80
Processor Reference Peripherals................................................... 83
Interrupt System......................................................................... 83
Timers.......................................................................................... 84
External Memory Interfacing ................................................... 89
Hardware Design Considerations ................................................ 93
Power Supplies............................................................................ 93
Grounding and Board Layout Recommendations................. 94
Clock Oscillator.......................................................................... 94
Power-On Reset Operation....................................................... 95
Typical System Configuration .................................................. 95
Development Tools......................................................................... 96
PC-Based Tools........................................................................... 96
In-Circuit Serial Downloader................................................... 96
Outline Dimensions....................................................................... 97
Ordering Guide ........................................................................ 101
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Detailed Block Diagram .............................................................. 9
Specifications................................................................................... 10
Timing Specifications ................................................................ 13
Absolute Maximum Ratings.......................................................... 20
ESD Caution................................................................................ 20
Pin Configurations and Function Descriptions ......................... 21
ADuC7019/ADuC7020/ADuC7021/ADuC7022 .................. 21
ADuC7024/ADuC7025 ............................................................. 25
ADuC7026/ADuC7027 ............................................................. 28
ADuC7028................................................................................... 31
ADuC7029................................................................................... 33
Typical Performance Characteristics ........................................... 35
Terminology .................................................................................... 38
ADC Specifications .................................................................... 38
DAC Specifications..................................................................... 38
Overview of the ARM7TDMI Core............................................. 39
Thumb Mode (T)........................................................................ 39
Long Multiply (M)...................................................................... 39
EmbeddedICE (I) ....................................................................... 39
Exceptions ................................................................................... 39
ARM Registers ............................................................................ 39
Interrupt Latency........................................................................ 40
Memory Organization ................................................................... 41
Memory Access........................................................................... 41
Flash/EE Memory....................................................................... 41
SRAM........................................................................................... 41
Memory Mapped Registers....................................................... 41
ADC Circuit Overview .................................................................. 45
Transfer Function ....................................................................... 45
Typical Operation ....................................................................... 46
MMRs Interface.......................................................................... 46
Converter Operation.................................................................. 48
Driving the Analog Inputs ........................................................ 49
Rev. F | Page 2 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
REVISION HISTORY
Updated Outline Dimensions........................................................91
Changes to Ordering Guide...........................................................94
5/13—Rev. E to Rev. F
Changes to Figure 1...........................................................................1
Added Figure 2 to Figure 10; Renumbered Sequentially.............4
Changes to Figure 19; Added Figure 20 .......................................21
Changes to EPAD Note in Figure 21 and Figure 22..................... 22
Changes to EPAD Note in Table 11.................................................... 23
Changes to EPAD Note in Figure 23 ............................................25
Changes to EPAD Note in Table 12 ..............................................26
Changes to Table 14 ........................................................................31
Changes to Table 15 ........................................................................33
Changes to Table 82 ........................................................................68
Added Table 83, Figure 73, Figure 74, Following Text, and
Table 84; Renumbered Sequentially..............................................69
Changes to Bit 2 Description, Table 98 ........................................71
Changes to Table 101 ......................................................................72
Changes to Timer2 (Wake-Up Timer) Section ...........................87
Changes to Figure 94 ......................................................................95
Updated Outline Dimensions........................................................97
Changes to Ordering Guide.........................................................101
12/09—Rev. B to Rev. C
Added ADuC7029 Part ..................................................... Universal
Added Table Numbers and Renumbered Tables............... Universal
Changes to Figure Numbers ............................................. Universal
Changes to Table 1 ............................................................................6
Changes to Figure 3 .........................................................................9
Changes to Table 3 and Figure 4 ...................................................10
Changes to Table 10 ........................................................................16
Changes to Figure 55 ......................................................................53
Changes to Serial Peripheral Interface Section ...........................69
Changes to Table 137......................................................................73
Changes to Figure 71 and Figure 72 .............................................85
Changes to Figure 73 and Figure 74 .............................................86
Updated Outline Dimensions........................................................91
Changes to Ordering Guide...........................................................94
3/07—Rev. A to Rev. B
Added ADuC7028 Part ..................................................... Universal
Updated Format ................................................................. Universal
Changes to Figure 2 ..........................................................................5
Changes to Table 1 ............................................................................6
Changes to ADuC7026/ADuC7027 Section ...............................23
Changes to Figure 21 ......................................................................28
Changes to Figure 32 Caption.......................................................30
Changes to Table 14 ........................................................................35
Changes to ADC Circuit Overview Section................................38
Changes to Programming Section ................................................44
Changes to Flash/EE Control Interface Section..........................45
Changes to Table 24 ........................................................................47
Changes to RSTCLR Register Section..........................................48
Changes to Figure 52 ......................................................................49
Changes to Figure 53 ......................................................................50
Changes to Comparator Section ...................................................50
Changes to Oscillator and PLL—Power Control Section..........51
Changes to Digital Peripherals Section........................................54
Changes to Interrupt System Section ...........................................75
Changes to Timers Section ............................................................76
Changes to External Memory Interfacing Section .....................80
Added IOVDD Supply Sensitivity Section.....................................84
Changes to Ordering Guide...........................................................90
7/12—Rev. D to Rev. E
Changed SCLOCK to SCLK When Refering to SPI Clock,
SPIMISO to MISO when Refering to SPI MISO, SPIMOSI to
MOSI when Refering to SPI MOSI, and SPICSL to
CS
when
Refering to SPI Chip Select...............................................Universal
Changes to Table 4, Table 5, and Figure 5....................................11
Changes to Endnote 1 in Table 6 and Figure 6............................12
Changes to Table 7 and Figure 7 ...................................................13
Changes to Table 8 and Figure 8 ...................................................14
Changes to Table 9 and Figure 9 ...................................................15
Changed EPAD Note in Figure 12 and Table 11 .........................18
Changed EPAD Note in Figure 13 and Table 12 .........................21
Changes to Bit 6 in Table 18...........................................................43
Changes to Example Source Code (External Crystal Selection)
Section and Example Source Code (External Clock Selection)
Section ...............................................................................................55
Changes to Serial Peripheral Interface Section ...........................69
Changes to SPICON[10] and SPICON[9] Descriptions in
Table 123............................................................................................70
Changes to Timer Interval Down Equation and Added Timer
Interval Up Equation ......................................................................79
Added Hour:Minute:Second:1/128 Format Section...................80
Changes to Table 189 ......................................................................84
Removed CP-40-10 Package..........................................................92
Changes to Ordering Guide...........................................................96
1/06—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................6
Added the Flash/EE Memory Reliability Section .......................43
Changes to Table 30 ........................................................................52
Changes to Serial Peripheral Interface .........................................66
Changes to Ordering Guide...........................................................90
5/11—Rev. C to Rev. D
Changes to Table 4 ..........................................................................11
Changes to Table 105 ......................................................................67
10/05—Revision 0: Initial Version
Rev. F | Page 3 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
GENERAL DESCRIPTION
The devices operate from an on-chip oscillator and a PLL
The ADuC7019/20/21/22/24/25/26/27/28/29 are fully integrated,
1 MSPS, 12-bit data acquisition systems incorporating high
performance multichannel ADCs, 16-bit/32-bit MCUs, and
Flash®/EE memory on a single chip.
generating an internal high frequency clock of 41.78 MHz
(UCLK). This clock is routed through a programmable clock
divider from which the MCU core clock operating frequency
is generated. The microcontroller core is an ARM7TDMI®,
16-bit/32-bit RISC machine, which offers up to 41 MIPS peak
performance. Eight kilobytes of SRAM and 62 kilobytes of
nonvolatile Flash/EE memory are provided on-chip. The
ARM7TDMI core views all memory and registers as a single
linear array.
The ADC consists of up to 12 single-ended inputs. An additional
four inputs are available but are multiplexed with the four DAC
output pins. The four DAC outputs are available only on certain
models (ADuC7020, ADuC7026, ADuC7028, and ADuC7029).
However, in many cases where the DAC outputs are not present,
these pins can still be used as additional ADC inputs, giving a
maximum of 16 ADC input channels. The ADC can operate in
single-ended or differential input mode. The ADC input voltage
is 0 V to VREF. A low drift band gap reference, temperature sensor,
and voltage comparator complete the ADC peripheral set.
On-chip factory firmware supports in-circuit serial download
via the UART or I2C serial interface port; nonintrusive emulation
is also supported via the JTAG interface. These features are
incorporated into a low cost QuickStart™ development system
supporting this MicroConverter® family.
Depending on the part model, up to four buffered voltage
output DACs are available on-chip. The DAC output range is
programmable to one of three voltage ranges.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. When
operating at 41.78 MHz, the power dissipation is typically
120 mW. The ADuC7019/20/21/22/24/25/26/27/28/29 are
available in a variety of memory models and packages (see
Ordering Guide).
12-BIT
DAC0
DAC
ADC0 TO ADC4,
ADC12 TO ADC15
1MSPS
12-BIT ADC
MUX
12-BIT
ADuC7020
DAC1
DAC
TEMP
SENSOR
12-BIT
DAC2
DAC
CMP0
CMP1
BAND GAP
REF
12-BIT
DAC3
DAC
CMP
OUT
V
REF
3-PHASE
PWM
OSC
XCLKI
ARM7TDMI-BASED MCU WITH
AND PLL
ADDITIONAL PERIPHERALS
XCLKO
(SEE NOTE 1)
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
POR
2
UART, SPI, I C
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 2.
Rev. F | Page 4 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
12-BIT
DAC0
DAC
ADC0 TO ADC7,
ADC12 TO ADC13
1MSPS
12-BIT ADC
MUX
12-BIT
ADuC7021
DAC1
DAC
TEMP
SENSOR
CMP0
CMP1
BAND GAP
REF
CMP
OUT
V
REF
3-PHASE
PWM
OSC
XCLKI
ARM7TDMI-BASED MCU WITH
AND PLL
ADDITIONAL PERIPHERALS
XCLKO
(SEE NOTE 1)
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
POR
2
UART, SPI, I C
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 3.
1MSPS
MUX
ADC0 TO ADC9
12-BIT ADC
ADuC7022
TEMP
SENSOR
CMP0
CMP1
BAND GAP
REF
CMP
OUT
V
REF
3-PHASE
PWM
OSC
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
XCLKO
(SEE NOTE 1)
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
PSM
POR
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
JTAG
2
UART, SPI, I C
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 4.
Rev. F | Page 5 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
12-BIT
DAC
DAC0
DAC1
ADC0 TO ADC9,
ADC12, ADC13
1MSPS
12-BIT ADC
MUX
12-BIT
DAC
ADuC7024
TEMP
SENSOR
CMP0
CMP1
BAND GAP
REF
CMP
OUT
V
REF
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
3-PHASE
OSC
PWM
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
XCLKO
(SEE NOTE 1)
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
POR
2
UART, SPI, I C
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 5.
ADC0 TO ADC9,
ADC12, ADC13
1MSPS
MUX
12-BIT ADC
ADuC7025
TEMP
SENSOR
CMP0
CMP1
BAND GAP
REF
CMP
OUT
V
REF
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
3-PHASE
PWM
OSC
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
XCLKO
(SEE NOTE 1)
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
POR
2
UART, SPI, I C
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 6.
Rev. F | Page 6 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
12-BIT
DAC0
DAC
1MSPS
MUX
ADC0 TO ADC15
12-BIT ADC
12-BIT
ADuC7026
DAC1
DAC2
DAC3
DAC
TEMP
SENSOR
12-BIT
DAC
CMP0
CMP1
BAND GAP
REF
12-BIT
DAC
CMP
OUT
V
REF
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
OSC
3-PHASE
XCLKI
ARM7TDMI-BASED MCU WITH
AND PLL
PWM
ADDITIONAL PERIPHERALS
XCLKO
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
EXT. MEMORY
INTERFACE
POR
2
UART, SPI, I C
Figure 7.
1MSPS
12-BIT ADC
MUX
ADC0 TO ADC15
ADuC7027
TEMP
SENSOR
CMP0
CMP1
BAND GAP
REF
CMP
OUT
V
REF
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
OSC
3-PHASE
PWM
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
XCLKO
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
POR
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
EXT. MEMORY
INTERFACE
2
UART, SPI, I C
Figure 8.
Rev. F | Page 7 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
12-BIT
DAC
DAC0
DAC1
DAC2
DAC3
1MSPS
ADC0 TO ADC7,
ADC12 TO ADC15
MUX
12-BIT ADC
12-BIT
DAC
ADuC7028
TEMP
SENSOR
12-BIT
DAC
CMP0
CMP1
BAND GAP
REF
12-BIT
DAC
CMP
OUT
V
REF
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
OSC
3-PHASE
PWM
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
XCLKO
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
POR
2
UART, SPI, I C
Figure 9.
12-BIT
DAC
DAC0
DAC1
DAC2
DAC3
1MSPS
ADC0 TO ADC6,
ADC12 TO ADC15
MUX
12-BIT ADC
12-BIT
DAC
ADuC7029
TEMP
SENSOR
12-BIT
DAC
CMP0
CMP1
BAND GAP
REF
12-BIT
DAC
CMP
OUT
V
REF
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
OSC
3-PHASE
PWM
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PLA
GPIO
JTAG
PSM
POR
4 GENERAL-
PURPOSE TIMERS
SERIAL I/O
RST
2
UART, SPI, I C
Figure 10.
Rev. F | Page 8 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
DETAILED BLOCK DIAGRAM
8
72 71 67 73 74
53 26 25 54
28 27 37
75 70 69
12-BIT
ADuC7026*
10 DAC0*/ADC12
11 DAC1*/ADC13
12 DAC2*/ADC14
13 DAC3*/ADC15
VOLTAGE
BUF
BUF
BUF
BUF
ADC0 77
ADC1 78
OUTPUT DAC
12-BIT SAR
ADC 1MSPS
ADC
CONTROL
ADC2/CMP0 79
ADC3/CMP1 80
12-BIT
VOLTAGE
OUTPUT DAC
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
1
2
3
4
5
6
7
DAC
CONTROL
12-BIT
VOLTAGE
MUX
OUTPUT DAC
12-BIT
VOLTAGE
OUTPUT DAC
ADC11 76
ADCNEG
TEMP
SENSOR
29 P3.0/AD0/PWM0 /PLAI[8]
H
9
62kB FLASH/EE
(31k × 16 BITS)
30 P3.1/AD1/PWM0 /PLAI[9]
L
31 P3.2/AD2/PWM1 /PLAI[10]
H
32 P3.3/AD3/PWM1 /PLAI[11]
L
ARM7TDMI
3-PHASE
PWM
8192 BYTES USER RAM
(2k × 32 BITS)
MUX
38 P3.4/AD4/PWM2 /PLAI[12]
H
CMP
/IRQ
WAKE-UP/
RTC TIMER
MCU
CORE
DAC
OUT
39 P3.5/AD5/PWM2 /PLAI[13]
L
BM/P0.0/CMP
/PLAI[7]/MS0 20
OUT
46 P3.6/AD6/PWM
47 P3.7/AD7/PWM
/PLAI[14]
/PLAI[15]
TRIP
POWER SUPPLY
MONITOR
DOWNLOADER
SYNC
V
68
V
REF
REF
OSC
BAND GAP
REFERENCE
44 XCLKO
45 XCLKI
PROG. CLOCK
DIVIDER
PLL
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
2
SPI/I C SERIAL
INTERFACE
UART
SERIAL PORT
P4.6/AD14/PLAO[14] 18
P4.7/AD15/PLAO[15] 19
PROG. LOGIC
ARRAY
40 IRQ0/P0.4/PWM
41 IRQ1/P0.5/ADC
/PLAO[1]/MS1
/PLAO[2]/MS2
TRIP
INTERRUPT
POR
21
CONTROLLER
BUSY
SERIAL PORT MULTIPLEXER
55 56 63 64 65 66 62 61 60 59 58 57 52 51
42
14 15 23 22 34
49 50 17 33 35 36 48 24 16
* SEE ORDERING GUIDE FOR
FEATURE AVAILABILITY ON
DIFFERENT MODELS.
Figure 11.
Rev. F | Page 9 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
SPECIFICATIONS
Data Sheet
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
ADC Power-Up Time
DC Accuracy1, 2
Eight acquisition clocks and fADC/2
5
μs
Resolution
Integral Nonlinearity
12
Bits
LSB
LSB
LSB
LSB
LSB
0.6
1.0
0.5
+0.7/−0.6
1
1.5
2.5 V internal reference
1.0 V external reference
2.5 V internal reference
1.0 V external reference
ADC input is a dc voltage
Differential Nonlinearity3, 4
+1/−0.9
DC Code Distribution
ENDPOINT ERRORS5
Offset Error
Offset Error Match
Gain Error
1
1
2
1
2
5
LSB
LSB
LSB
LSB
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
(PHSN)
fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS
Includes distortion and noise components
69
−78
−75
dB
dB
dB
Channel-to-Channel Crosstalk
ANALOG INPUT
−80
dB
Measured on adjacent channels
Input Voltage Ranges
Differential Mode
6
VCM VREF/2
V
Single-Ended Mode
Leakage Current
Input Capacitance
0 to VREF
6
V
µA
pF
1
20
During ADC acquisition
ON-CHIP VOLTAGE REFERENCE
Output Voltage
0.47 µF from VREF to AGND
2.5
V
Accuracy
5
mV
ppm/°C
dB
Ω
ms
TA = 25°C
TA = 25°C
Reference Temperature Coefficient
Power Supply Rejection Ratio
Output Impedance
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT
Input Voltage Range
DAC CHANNEL SPECIFICATIONS
DC Accuracy7
40
75
70
1
0.625
AVDD
V
RL = 5 kΩ, CL = 100 pF
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error8
12
2
Bits
LSB
LSB
mV
%
1
15
1
Guaranteed monotonic
2.5 V internal reference
Gain Error Mismatch
ANALOG OUTPUTS
0.1
%
% of full scale on DAC0
Output Voltage Range_0
Output Voltage Range_1
Output Voltage Range_2
Output Impedance
0 to DACREF
0 to 2.5
0 to DACVDD
2
V
V
V
Ω
DACREF range: DACGND to DACVDD
Rev. F | Page 10 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
10
20
µs
nV-sec
1 LSB change at major carry (where maximum
number of bits simultaneously changes in the
DACxDAT register)
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis4, 6
15
1
mV
µA
V
pF
mV
AGND
2
AVDD − 1.2
15
7
3
Hysteresis turned on or off via the CMPHYST bit in
the CMPCON register
100 mV overdrive and configured with CMPRES = 11
Response Time
µs
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage TC
780
−1.3
3
mV
mV/°C
°C
Accuracy
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
2.79
3.07
2.5
V
V
%
V
Two selectable trip points
Power Supply Trip Point Accuracy
POWER-ON-RESET
GLITCH IMMUNITY ON RESET PIN4
WATCHDOG TIMER (WDT)
Timeout Period
Of the selected nominal trip point voltage
2.36
50
µs
0
512
sec
FLASH/EE MEMORY
Endurance9
Data Retention10
10,000
20
Cycles
Years
TJ = 85°C
DIGITAL INPUTS
Logic 1 Input Current
Logic 0 Input Current
All digital inputs excluding XCLKI and XCLKO
VIH = IOVDD or VIH = 5 V
VIL = 0 V; except TDI on
0.2
−40
1
−60
µA
µA
ADuC7019/20/21/22/24/25/29
−80
10
−120
0.8
µA
pF
VIL = 0 V; TDI on ADuC7019/20/21/22/24/25/29
Input Capacitance
LOGIC INPUTS3
VINL, Input Low Voltage
VINH, Input High Voltage
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage11
CRYSTAL INPUTS XCLKI and XCLKO
Logic Inputs, XCLKI Only
VINL, Input Low Voltage
VINH, Input High Voltage
XCLKI Input Capacitance
XCLKO Output Capacitance
INTERNAL OSCILLATOR
All logic inputs excluding XCLKI
V
V
2.0
2.4
All digital outputs excluding XCLKO
ISOURCE = 1.6 mA
ISINK = 1.6 mA
V
V
0.4
1.1
1.7
20
20
V
V
pF
pF
kHz
%
32.768
3
24
%
TA = 0°C to 85°C range
Rev. F | Page 11 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
MCU CLOCK RATE
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
Using an External Clock
326
41.78
kHz
CD12 = 7
MHz
MHz
MHz
CD12 = 0
0.05
0.05
44
41.78
TA = 85°C
TA = 125°C
START-UP TIME
Core clock = 41.78 MHz
At Power-On
From Pause/Nap Mode
130
24
3.06
1.58
1.7
ms
ns
µs
ms
ms
CD12 = 0
CD12 = 7
From Sleep Mode
From Stop Mode
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
Element Propagation Delay
POWER REQUIREMENTS13, 14
Power Supply Voltage Range
12
2.5
ns
ns
From input pin to output pin
AVDD to AGND and IOVDD to IOGND 2.7
Analog Power Supply Currents
AVDD Current
3.6
25
V
200
400
3
µA
µA
µA
ADC in idle mode; all parts except ADuC7019
ADC in idle mode; ADuC7019 only
DACVDD Current15
Digital Power Supply Current
IOVDD Current in Normal Mode
Code executing from Flash/EE
CD12 = 7
7
10
15
45
30
400
1000
mA
mA
mA
mA
µA
11
40
25
250
600
CD12 = 3
CD12 = 0 (41.78 MHz clock)
CD12 = 0 (41.78 MHz clock)
TA = 85°C
IOVDD Current in Pause Mode
IOVDD Current in Sleep Mode
µA
TA = 125°C
Additional Power Supply Currents
ADC
2
0.7
700
mA
mA
µA
@ 1 MSPS
@ 62.5 kSPS
per DAC
DAC
ESD TESTS
2.5 V reference, TA = 25°C
HBM Passed Up To
FCIDM Passed Up To
4
0.5
kV
kV
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Apply to all ADC input channels.
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 59. Based on external ADC
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 DAC linearity is calculated using a reduced code range of 100 to 3995.
8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF
.
9 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
11 Test carried out with a maximum of eight I/Os set to a low output level.
12 See the POWCON register.
13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
14 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
15 On the ADuC7019/20/21/22, this current must be added to the AVDD current.
Rev. F | Page 12 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
TIMING SPECIFICATIONS
Table 2. External Memory Write Cycle
Parameter
CLK1
Min
Typ
Max
Unit
UCLK
tMS_AFTER_CLKH
tADDR_AFTER_CLKH
tAE_H_AFTER_MS
tAE
tHOLD_ADDR_AFTER_AE_L
tHOLD_ADDR_BEFORE_WR_L
tWR_L_AFTER_AE_L
tDATA_AFTER_WR_L
tWR
tWR_H_AFTER_CLKH
tHOLD_DATA_AFTER_WR_H
tBEN_AFTER_AE_L
tRELEASE_MS_AFTER_WR_H
0
4
4
8
ns
ns
½ CLK
(XMxPAR[14:12] + 1) × CLK
½ CLK + (!XMxPAR[10]) × CLK
(!XMxPAR[8]) × CLK
½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK
8
0
12
4
ns
ns
(XMxPAR[7:4] + 1) × CLK
(!XMxPAR[8]) × CLK
½ CLK
(!XMxPAR[8] + 1) × CLK
1 See Table 78.
CLK
CLK
tMS_AFTER_CLKH
MSx
AE
tWR_L_AFTER_AE_L
tAE_H_AFTER_MS
tWR
tRELEASE_MS_AFTER_WR_H
tAE
tWR_H_AFTER_CLKH
WS
RS
tHOLD_DATA_AFTER_WR_H
tHOLD_ADDR_AFTER_AE_L
tHOLD_ADDR_BEFORE_WR_L
tADDR_AFTER_CLKH
9ABC
tDATA_AFTER_WR_L
AD[16:1]
FFFF
5678
9ABE
1234
tBEN_AFTER_AE_L
BLE
BHE
A16
Figure 12. External Memory Write Cycle (See Table 78)
Rev. F | Page 13 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 3. External Memory Read Cycle
Parameter
CLK1
Min
Typ
Max
Unit
1/MD clock
ns typ × (POWCON[2:0] + 1)
tMS_AFTER_CLKH
tADDR_AFTER_CLKH
tAE_H_AFTER_MS
tAE
tHOLD_ADDR_AFTER_AE_L
tRD_L_AFTER_AE_L
tRD_H_AFTER_CLKH
tRD
4
4
8
16
ns
ns
½ CLK
(XMxPAR[14:12] + 1) × CLK
½ CLK + (! XMxPAR[10] ) × CLK
½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
0
4
(XMxPAR[3:0] + 1) × CLK
tDATA_BEFORE_RD_H
tDATA_AFTER_RD_H
tRELEASE_MS_AFTER_RD_H
16
8
ns
+ (! XMxPAR[9]) × CLK
1 × CLK
1 See Table 78.
CLK
ECLK
MSx
tMS_AFTER_CLKH
tAE_H_AFTER_MS
tRELEASE_MS_AFTER_RD_H
tAE
tRD_L_AFTER_AE_L
AE
WS
tRD
tRD_H_AFTER_CLKH
RS
tDATA_BEFORE_RD_H
tDATA_AFTER_RD_H
tADDR_AFTER_CLKH
AD[16:1] FFFF
2348
XXXX CDEF XX
234A
XX
89AB
tHOLD_ADDR_AFTER_AE_L
BHE
BLE
A16
Figure 13. External Memory Read Cycle (See Table 78)
Rev. F | Page 14 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 4. I2C Timing in Fast Mode (400 kHz)
Slave
Max
Master
Typ
Parameter
Description
Min
200
100
300
100
0
100
100
1.3
Unit
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
tL
tH
SCL low pulse width1
1360
1140
SCL high pulse width1
Start condition hold time
Data setup time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
740
400
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
Pulse width of spike suppressed
400
200
300
300
50
tF
tSUP
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67.
Table 5. I2C Timing in Standard Mode (100 kHz)
Slave
Master
Typ
Parameter
Description
Min
Max
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
tL
tH
SCL low pulse width1
4.7
4.0
4.0
250
0
4.7
4.0
4.7
SCL high pulse width1
Start condition hold time
Data setup time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
Data hold time
3.45
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
1
300
tF
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67.
tBUF
tSUP
tR
MSB
tF
SDA (I/O)
MSB
LSB
ACK
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
2–7
8
9
1
SCL (I)
tL
tSUP
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 14. I2C Compatible Interface Timing
Rev. F | Page 15 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 6. SPI Master Mode Timing (Phase Mode = 1)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLK low pulse width1
SCLK high pulse width1
Data output valid after SCLK edge
Data input setup time before SCLK edge2
Data input hold time after SCLK edge2
Data output fall time
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
tDAV
tDSU
tDHD
tDF
tDR
tSR
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
Data output rise time
SCLK rise time
SCLK fall time
tSF
1 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
MOSI
MISO
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 15. SPI Master Mode Timing (Phase Mode = 1)
Rev. F | Page 16 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 7. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLK low pulse width1
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
SCLK high pulse width1
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge2
Data input hold time after SCLK edge2
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
25
75
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
1 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
MOSI
MISO
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 16. SPI Master Mode Timing (Phase Mode = 0)
Rev. F | Page 17 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 8. SPI Slave Mode Timing (Phsae Mode = 1)
Parameter
Description
CS to SCLK edge1
Min
Typ
Max
Unit
tCS
(2 × tHCLK) + (2 × tUCLK
)
ns
tSL
tSH
SCLK low pulse width2
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high pulse width2
Data output valid after SCLK edge
Data input setup time before SCLK edge1
Data input hold time after SCLK edge1
Data output fall time
tDAV
tDSU
tDHD
tDF
tDR
tSR
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
Data output rise time
SCLK rise time
SCLK fall time
CS high after SCLK edge
tSF
tSFS
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
2 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67.
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
MISO
MOSI
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 17. SPI Slave Mode Timing (Phase Mode = 1)
Rev. F | Page 18 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 9. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
Description
CS to SCLK edge1
Min
Typ
Max
Unit
tCS
(2 × tHCLK) + (2 × tUCLK
)
ns
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width2
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high pulse width2
Data output valid after SCLK edge
Data input setup time before SCLK edge1
Data input hold time after SCLK edge1
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after CS edge
CS high after SCLK edge
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
25
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
2 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67.
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MOSI
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 18. SPI Slave Mode Timing (Phase Mode = 0)
Rev. F | Page 19 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ABSOLUTE MAXIMUM RATINGS
AGND = REFGND = DACGND = GNDREF, TA = 25°C, unless
otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 10.
Parameter
Rating
AVDD to IOVDD
AGND to DGND
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +6 V
−0.3 V to +5.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
IOVDD to IOGND, AVDD to AGND
Digital Input Voltage to IOGND
Digital Output Voltage to IOGND
VREF to AGND
Analog Inputs to AGND
Analog Outputs to AGND
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Operating Temperature Range, Industrial –40°C to +125°C
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
40-Lead LFCSP
49-Ball CSP_BGA
64-Lead LFCSP
64-Ball CSP_BGA
64-Lead LQFP
80-Lead LQFP
–65°C to +150°C
150°C
26°C/W
80°C/W
24°C/W
75°C/W
47°C/W
38°C/W
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec)
RoHS Compliant Assemblies
(20 sec to 40 sec)
240°C
260°C
Rev. F | Page 20 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADuC7019/ADuC7020/ADuC7021/ADuC7022
ADC3/CMP1
ADC4
1
2
3
4
5
6
7
8
9
30 P1.3/SPM3/PLAI[3]
29 P1.4/SPM4/PLAI[4]/IRQ2
28 P1.5/SPM5/PLAI[5]/IRQ3
27 P1.6/SPM6/PLAI[6]
GNDREF
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
TMS
ADuC7019
26 P1.7/SPM7/PLAO[0]
25 XCLKI
TOP VIEW
(Not to Scale)
24 XCLKO
23 P0.7/ECLK/XCLK/SPM8/PLAO[4]
22 P2.0/SPM9/PLAO[5]/CONVSTART
21 IRQ1/P0.5/ADCBUSY/PLAO[2]
TDI
BM/P0.0/CMPOUT/PLAI[7] 10
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED FOR MECHANICAL PURPOSES AND LEFT UNCONNECTED.
Figure 19. 40-Lead LFCSP_VQ Pin Configuration (ADuC7019)
1
2
30
29
28
ADC3/CMP1
ADC4
P1.3/SPM3/PLAI[3]
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
GNDREF
3
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
TMS
4
5
6
27 P1.6/SPM6/PLAI[6]
26 P1.7/SPM7/PLAO[0]
25 XCLKI
ADuC7020
TOP VIEW
(Not to Scale)
7
24 XCLKO
23 P0.7/ECLK/XCLK/SPM8/PLAO[4]
22 P2.0/SPM9/PLAO[5]/CONVSTART
8
9
TDI
BM/P0.0/CMPOUT/PLAI[7]
10
IRQ1/P0.5/ADCBUSY/PLAO[2]
21
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED FOR MECHANICAL PURPOSES AND LEFT UNCONNECTED.
Figure 20. 40-Lead LFCSP_WQ Pin Configuration (ADuC7020)
Rev. F | Page 21 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ADC4
ADC5
ADC6
ADC7
1
2
3
4
5
6
7
8
9
30 P1.3/SPM3/PLAI[3]
29 P1.4/SPM4/PLAI[4]/IRQ2
28 P1.5/SPM5/PLAI[5]/IRQ3
27 P1.6/SPM6/PLAI[6]
26 P1.7/SPM7/PLAO[0]
25 XCLKI
PIN 1
INDICATOR
GND
REF
ADuC7021
DAC0/ADC12
TOP VIEW
DAC1/ADC13
TMS
24 XCLKO
(Not to Scale)
23 P0.7/ECLK/XCLK/SPM8/PLAO[4]
TDI
22 P2.0/SPM9/PLAO[5]/CONV
START
BM/P0.0/CMP
/PLAI[7] 10
21 IRQ1/P0.5/ADC
/PLAO[2]
OUT
BUSY
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED FOR MECHANICAL PURPOSES AND LEFT UNCONNECTED.
Figure 21. 40-Lead LFCSP_VQ Pin Configuration (ADuC7021)
ADC5
1
2
3
4
5
6
7
8
9
30 P1.2/SPM2/PLAI[2]
29 P1.3/SPM3/PLAI[3]
28 P1.4/SPM4/PLAI[4]/IRQ2
27 P1.5/SPM5/PLAI[5]/IRQ3
26 P1.6/SPM6/PLAI[6]
25 P1.7/SPM7/PLAO[0]
24 XCLKI
PIN 1
INDICATOR
ADC6
ADC7
ADC8
ADC9
ADuC7022
GNDREF
TMS
TDI
TOP VIEW
(Not to Scale)
23 XCLKO
BM/P0.0/CMPOUT/PLAI[7]
P0.6/T1/MRST/PLAO[3] 10
22 P0.7/ECLK/XCLK/SPM8/PLAO[4]
21 P2.0/SPM9/PLAO[5]/CONVSTART
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED FOR MECHANICAL PURPOSES AND LEFT UNCONNECTED.
Figure 22. 40-Lead LFCSP_VQ Pin Configuration (ADuC7022)
Rev. F | Page 22 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 11. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No.
7019/7020 7021 7022 Mnemonic
Description
38
39
40
1
37
38
39
40
36
37
38
39
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/
Comparator Negative Input.
2
‒
‒
‒
‒
‒
3
1
2
40
1
ADC4
ADC5
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
3
4
2
3
4
5
6
ADC6
ADC7
ADC8
ADC9
GNDREF
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
‒
‒
5
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from IOGND and DGND.
4
5
6
7
6
7
‒
‒
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.
‒
‒
‒
‒
DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor
must be connected between this pin and AGND/Single-Ended or
Differential Analog Input 15 (see Figure 53).
8
8
7
TMS
Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOVDD. In some cases, an external
pull-up resistor (~100K) is also required to ensure that the part does not
enter an erroneous state.
9
10
9
10
8
9
TDI
Test Data In, JTAG Test Port Input. Debug and download access.
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter
serial download mode if BM is low at reset and execute code if BM is
pulled high at reset through a 1 kΩ resistor/General-Purpose Input and
Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
11
12
11
12
10
11
P0.6/T1/MRST/PLAO[3]
TCK
Multifunction Pin. Driven low after reset. General-Purpose Output Port 0.6/
Timer1 Input/Power-On Reset Output/Programmable Logic Array Output
Element 3.
Test Clock, JTAG Test Port Input. Debug and download access. This pin has
an internal pull-up resistor to IOVDD. In some cases an external pull-up
resistor (~100K) is also required to ensure that the part does not enter an
erroneous state.
13
14
15
13
14
15
12
13
14
TDO
IOGND
IOVDD
Test Data Out, JTAG Test Port Output. Debug and download access.
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage
Regulator.
16
16
15
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 µF capacitor to DGND only.
17
18
17
18
16
17
DGND
P0.3/TRST/ADCBUSY
Ground for Core Logic.
General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/
ADCBUSY Signal Output.
19
20
19
20
18
19
RST
Reset Input, Active Low.
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-
Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable
Logic Array Output Element 1.
21
21
20
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-
Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable
Logic Array Output Element 2.
Rev. F | Page 23 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Pin No.
7019/7020 7021 7022 Mnemonic
Description
22
22
21
P2.0/SPM9/PLAO[5]/CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/
Programmable Logic Array Output Element 5/Start Conversion Input Signal
for ADC.
23
23
22
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/
Output for External Clock Signal/Input to the Internal Clock Generator
Circuits/UART/ Programmable Logic Array Output Element 4.
24
25
24
25
23
24
XCLKO
XCLKI
Output from the Crystal Oscillator Inverter.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits.
26
27
28
26
27
28
25
26
27
P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART,
SPI/Programmable Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART,
SPI/Programmable Logic Array Input Element 6.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART,
SPI/Programmable Logic Array Input Element 5/External Interrupt
Request 3, Active High.
P1.5/SPM5/PLAI[5]/IRQ3
29
29
28
P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART,
SPI/Programmable Logic Array Input Element 4/External Interrupt
Request 2, Active High.
30
31
32
33
34
35
30
31
32
33
29
30
31
32
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
P4.2/PLAO[10]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART,
I2C1/Programmable Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART,
I2C1/Programmable Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART,
I2C0/Programmable Logic Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/
Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0.
General-Purpose Input and Output Port 4.2/Programmable Logic Array
Output Element 10.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor
when using the internal reference.
‒
‒
34
33
VREF
36
37
35
36
34
35
AGND
AVDD
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
0
0
0
EP
Exposed Pad. The pin configuration for the ADuC7019/ADuC7020/
ADuC7021/ADuC7022 has an exposed pad that must be soldered for
mechanical purposes and left unconnected.
Rev. F | Page 24 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
ADuC7024/ADuC7025
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
1
2
3
4
5
6
7
8
9
48 P1.2/SPM2/PLAI[2]
47 P1.3/SPM3/PLAI[3]
46 P1.4/SPM4/PLAI[4]/IRQ2
45 P1.5/SPM5/PLAI[5]/IRQ3
44 P4.1/PLAO[9]
PIN 1
INDICATOR
ADuC7024/
43 P4.0/PLAO[8]
GND
42 IOV
REF
DD
ADuC7025
ADCNEG
DAC0/ADC12
DAC1/ADC13 10
TMS 11
TDI 12
P4.6/PLAO[14] 13
P4.7/PLAO[15] 14
41 IOGND
40 P1.6/SPM6/PLAI[6]
39 P1.7/SPM7/PLAO[0]
TOP VIEW
(Not to Scale)
38 P3.7/PWM
37 P3.6/PWM
36 XCLKI
/PLAI[15]
/PLAI[14]
SYNC
TRIP
35 XCLKO
BM/P0.0/CMP /PLAI[7] 15
OUT
34 P0.7/ECLK/XCLK/SPM8/PLAO[4]
P0.6/T1/MRST/PLAO[3] 16
33 P2.0/SPM9/PLAO[5]/CONV
START
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED FOR MECHANICAL PURPOSES AND LEFT UNCONNECTED.
Figure 23. 64-Lead LFCSP_VQ Pin Configuration (ADuC7024/ADuC7025)
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
1
2
3
4
5
6
7
8
9
48 P1.2/SPM2/PLAI[2]
47 P1.3/SPM3/PLAI[3]
46 P1.4/SPM4/PLAI[4]/IRQ2
45 P1.5/SPM5/PLAI[5]/IRQ3
44 P4.1/PLAO[9]
PIN 1
INDICATOR
ADuC7024/
43 P4.0/PLAO[8]
GND
42 IOV
REF
DD
ADuC7025
ADCNEG
DAC0/ADC12
DAC1/ADC13 10
TMS 11
TDI 12
P4.6/PLAO[14] 13
P4.7/PLAO[15] 14
41 IOGND
40 P1.6/SPM6/PLAI[6]
39 P1.7/SPM7/PLAO[0]
TOP VIEW
(Not to Scale)
38 P3.7/PWM
37 P3.6/PWM
36 XCLKI
/PLAI[15]
/PLAI[14]
SYNC
TRIP
35 XCLKO
BM/P0.0/CMP
/PLAI[7] 15
P0.6/T1/MRST/PLAO[3] 16
34 P0.7/ECLK/XCLK/SPM8/PLAO[4]
OUT
33 P2.0/SPM9/PLAO[5]/CONV
START
Figure 24. 64-Lead LQFP Pin Configuration (ADuC7024/ADuC7025)
Rev. F | Page 25 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 12. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP)
Pin No. Mnemonic
Description
1
2
3
4
5
6
7
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
GNDREF
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
8
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
9
DAC0/ADC12
DAC1/ADC13
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not present
on the ADuC7025.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not present
on the ADuC7025.
10
11
12
13
14
15
TMS
TDI
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In. Debug and download access
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at
reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/General-Purpose Input
and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7.
P4.6/PLAO[14]
P4.7/PLAO[15]
BM/P0.0/CMPOUT/PLAI[7]
16
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-
On Reset Output/Programmable Logic Array Output Element 3.
17
18
19
20
21
TCK
TDO
IOGND
IOVDD
LVDD
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
22
23
DGND
P3.0/PWM0H/PLAI[8]
Ground for Core Logic.
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic
Array Input Element 8.
24
25
26
P3.1/PWM0L/PLAI[9]
P3.2/PWM1H/PLAI[10]
P3.3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic
Array Input Element 9.
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic
Array Input Element 10.
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable Logic
Array Input Element 11.
27
28
29
P0.3/TRST/ADCBUSY
RST
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output.
Reset Input, Active Low.
P3.4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable Logic
Array Input 12.
30
31
32
33
34
P3.5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic
Array Input Element 13.
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.
IRQ0/P0.4/PWMTRIP/PLAO[1]
IRQ1/P0.5/ADCBUSY/PLAO[2]
P2.0/SPM9/PLAO[5]/CONVSTART Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
35
36
XCLKO
XCLKI
Output from the Crystal Oscillator Inverter.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
Rev. F | Page 26 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No. Mnemonic
Description
37
38
39
40
P3.6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input
Element 14.
General-Purpose Input and Output Port 3.7/PWM Synchronization Input and Output/
Programmable Logic Array Input Element 15.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
P3.7/PWMSYNC/PLAI[15]
P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6]
41
42
43
44
45
IOGND
IOVDD
P4.0/PLAO[8]
P4.1/PLAO[9]
P1.5/SPM5/PLAI[5]/IRQ3
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
46
47
48
49
50
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic
Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
51
52
53
54
55
P4.2/PLAO[10]
P4.3/PLAO[11]
P4.4/PLAO[12]
P4.5/PLAO[13]
VREF
General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
56
57
58
59
60
61
62
63
64
0
DACREF
DACGND
AGND
AVDD
DACVDD
ADC0
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
Ground for the DAC. Typically connected to AGND.
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
3.3 V Power Supply for the DACs. Must be connected to AVDD.
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
ADC1
ADC2/CMP0
ADC3/CMP1
EP
Exposed Pad. The pin configuration for the ADuC7024/ADuC7025 LFCSP_VQ has an exposed pad
that must be soldered for mechanical purposes and left unconnected.
Rev. F | Page 27 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ADuC7026/ADuC7027
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
1
2
3
4
5
6
7
8
9
60 P1.2/SPM2/PLAI[2]
59 P1.3/SPM3/PLAI[3]
58 P1.4/SPM4/PLAI[4]/IRQ2
57 P1.5/SPM5/PLAI[5]/IRQ3
56 P4.1/AD9/PLAO[9]
55 P4.0/AD8/PLAO[8]
PIN 1
INDICATOR
54 IOV
53 IOGND
DD
GND
REF
ADuC7026/
ADuC7027
ADCNEG
52 P1.6/SPM6/PLAI[6]
51 P1.7/SPM7/PLAO[0]
DAC0/ADC12 10
DAC1/ADC13 11
DAC2/ADC14 12
DAC3/ADC15 13
TMS 14
50 P2.2/RS/PWM0 /PLAO[7]
L
TOP VIEW
49 P2.1/WS/PWM0 /PLAO[6]
(Not to Scale)
H
48 P2.7/PWM1 /MS3
L
47 P3.7/AD7/PWM
46 P3.6/AD6/PWM
45 XCLKI
/PLAI[15]
SYNC
/PLAI[14]
TDI 15
TRIP
P0.1/PWM2 /BLE 16
H
P2.3/AE 17
P4.6/AD14/PLAO[14] 18
P4.7/AD15/PLAO[15] 19
44 XCLKO
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
42 P2.0/SPM9/PLAO[5]/CONV
START
/PLAO[2]/MS2
BM/P0.0/CMP
/PLAI[7]/MS0 20
41 IRQ1/P0.5/ADC
OUT
BUSY
Figure 25. 80-Lead LQFP Pin Configuration (ADuC7026/ADuC7027)
Table 13. Pin Function Descriptions (ADuC7026/ADuC7027)
Pin No. Mnemonic
Description
1
2
3
4
5
6
7
8
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
GNDREF
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
Single-Ended or Differential Analog Input 10.
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
9
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
10
11
12
13
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7027.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7027.
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC outputs are not
present on the ADuC7027.
DAC3 Voltage Output/Single-Ended or Differential Analog Input 15. DAC outputs are not
present on the ADuC7027.
14
15
16
TMS
TDI
P0.1/PWM2H/BLE
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In. Debug and download access.
General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory
Byte Low Enable.
17
P2.3/AE
General-Purpose Input and Output Port 2.3/External Memory Access Enable.
Rev. F | Page 28 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No. Mnemonic
Description
18
19
20
P4.6/AD14/PLAO[14]
General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic
Array Output Element 14.
General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic
Array Output Element 15.
Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM
is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7/External Memory Select 0.
P4.7/AD15/PLAO[15]
BM/P0.0/CMPOUT/PLAI[7]/MS0
21
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
22
23
24
TCK
TDO
P0.2/PWM2L/BHE
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory
Byte High Enable.
25
26
27
IOGND
IOVDD
LVDD
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
28
29
DGND
Ground for Core Logic.
P3.0/AD0/PWM0H/PLAI[8]
General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High-Side
Output/Programmable Logic Array Input Element 8.
30
31
32
33
P3.1/AD1/PWM0L/PLAI[9]
P3.2/AD2/PWM1H/PLAI[10]
P3.3/AD3/PWM1L/PLAI[11]
P2.4/PWM0H/MS0
General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low-Side
Output/Programmable Logic Array Input Element 9.
General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High-Side
Output/Programmable Logic Array Input Element 10.
General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low-Side
Output/Programmable Logic Array Input Element 11.
General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory
Select 0.
34
35
P0.3/TRST/A16/ADCBUSY
P2.5/PWM0L/MS1
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output.
General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory
Select 1.
36
P2.6/PWM1H/MS2
General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory
Select 2.
37
38
RST
Reset Input, Active Low.
P3.4/AD4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High-Side
Output/Programmable Logic Array Input 12.
39
40
P3.5/AD5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low-Side
Output/Programmable Logic Array Input Element 13.
IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/
External Memory Select 1.
41
IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2 Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External
Memory Select 2.
42
43
CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
P2.0/SPM9/PLAO[5]/
44
45
XCLKO
XCLKI
Output from the Crystal Oscillator Inverter.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
Rev. F | Page 29 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Pin No. Mnemonic
Description
46
47
48
49
50
51
52
P3.6/AD6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cutoff/
Programmable Logic Array Input Element 14.
General-Purpose Input and Output Port 3.7/External Memory Interface/PWM Synchronization/
Programmable Logic Array Input Element 15.
General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory
Select 3.
General-Purpose Input and Output Port 2.1/External Memory Write Strobe/PWM Phase 0 High-
Side Output/Programmable Logic Array Output Element 6.
General-Purpose Input and Output Port 2.2/External Memory Read Strobe/PWM Phase 0 Low-
Side Output/Programmable Logic Array Output Element 7.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic
Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic
Array Input Element 6.
P3.7/AD7/PWMSYNC/PLAI[15]
P2.7/PWM1L/MS3
P2.1/WS/PWM0H/PLAO[6]
P2.2/RS/PWM0L/PLAO[7]
P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6]
53
54
55
IOGND
IOVDD
P4.0/AD8/PLAO[8]
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic
Array Output Element 8.
56
57
58
59
60
61
62
63
64
65
66
P4.1/AD9/PLAO[9]
General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic
Array Output Element 9.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic
Array Input Element 5/External Interrupt Request 3, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic
Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic
Array Output Element 10.
P1.5/SPM5/PLAI[5]/IRQ3
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
P4.2/AD10/PLAO[10]
P4.3/AD11/PLAO[11]
P4.4/AD12/PLAO[12]
P4.5/AD13/PLAO[13]
General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic
Array Output Element 11.
General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic
Array Output Element 12.
General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic
Array Output Element 13.
67
68
REFGND
VREF
Ground for the Reference. Typically connected to AGND.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the
internal reference.
69
70
71, 72
73, 74
75
DACREF
DACGND
AGND
AVDD
DACVDD
ADC11
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
Ground for the DAC. Typically connected to AGND.
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
3.3 V Power Supply for the DACs. Must be connected to AVDD.
Single-Ended or Differential Analog Input 11.
76
77
ADC0
Single-Ended or Differential Analog Input 0.
78
ADC1
Single-Ended or Differential Analog Input 1.
79
80
ADC2/CMP0
ADC3/CMP1
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
Rev. F | Page 30 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
ADUC7028
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
BOTTOM VIEW
(Not to Scale)
Figure 26. 64-Ball CSP_BGA Pin Configuration (ADuC7028)
Table 14. Pin Function Descriptions (ADuC7028)
Ball No.
Mnemonic
ADC3/CMP1
DACVDD
Description
A1
A2
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
3.3 V Power Supply for the DACs. Must be connected to AVDD.
3.3 V Analog Power.
A3
AVDD
A4
AGND
Analog Ground. Ground reference point for the analog circuitry.
Ground for the DAC. Typically connected to AGND.
General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
A5
DACGND
A6
P4.2/PLAO[10]
P1.1/SPM1/PLAI[1]
A7
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
A8
P1.2/SPM2/PLAI[2]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
B1
B2
B3
B4
B5
ADC4
Single-Ended or Differential Analog Input 4.
ADC2/CMP0
ADC1
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 1.
DACREF
VREF
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
B6
B7
B8
P1.0/T1/SPM0/PLAI[0]
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
C1
C2
C3
C4
C5
C6
C7
C8
D1
ADC6
Single-Ended or Differential Analog Input 6.
ADC5
Single-Ended or Differential Analog Input 5.
ADC0
Single-Ended or Differential Analog Input 0.
P4.5/PLAO[13]
P4.3/PLAO[11]
P4.0/PLAO[8]
P4.1/PLAO[9]
IOGND
General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
Ground for GPIO (see Table 78). Typically connected to DGND.
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be
connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
D2
GNDREF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
D3
D4
D5
ADC7
Single-Ended or Differential Analog Input 7.
P4.4/PLAO[12]
P3.6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array
Input Element 14.
D6
P1.7/SPM7/PLAO[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
Rev. F | Page 31 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Ball No.
Mnemonic
Description
D7
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
D8
E1
E2
E3
E4
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
DAC3 Voltage Output/ADC Input 15.
DAC3/ADC15
DAC2/ADC14
DAC1/ADC13
P3.0/PWM0H/PLAI[8]
DAC2 Voltage Output/ADC Input 14.
DAC1 Voltage Output/ADC Input 13.
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
E5
E6
E7
P3.2/PWM1H/PLAI[10]
P1.5/SPM5/PLAI[5]/IRQ3
P3.7/PWMSYNC/PLAI[15]
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
General-Purpose Input and Output Port 3.7/PWM Synchronization/Programmable Logic
Array Input Element 15.
E8
F1
F2
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
JTAG Test Port Input, Test Data In. Debug and download access.
P4.6/PLAO[14]
TDI
F3
F4
DAC0/ADC12
DAC0 Voltage Output/ADC Input 12.
P3.1/PWM0L/PLAI[9]
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
F5
P3.3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
F6
F7
RST
Reset Input, Active Low.
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External
Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array
Output Element 4.
F8
XCLKO
Output from the Crystal Oscillator Inverter.
G1
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot mode. The ADuC7028 enters UART download mode if BM is low
at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
G2
G3
G4
G5
P4.7/PLAO[15]
TMS
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
JTAG Test Port Input, Test Mode Select. Debug and download access.
TDO
JTAG Test Port Output, Test Data Out. Debug and download access.
P0.3/TRST/ADCBUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal
Output.
G6
G7
G8
H1
P3.4/PWM2H/PLAI[12]
P3.5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable
Logic Array Output Element 5/Start Conversion Input Signal for ADC.
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
P2.0/SPM9/PLAO[5]/CONVSTART
P0.6/T1/MRST/PLAO[3]
H2
H3
H4
H5
TCK
JTAG Test Port Input, Test Clock. Debug and download access.
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
IOGND
IOVDD
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
H6
H7
DGND
Ground for Core Logic.
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
H8
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.
Rev. F | Page 32 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
ADUC7029
7
6
5
4
3
2
1
A
B
C
D
E
F
G
BOTTOM VIEW
(Not to Scale)
Figure 27. 49-Ball CSP_BGA Pin Configuration (ADuC7029)
Table 15. Pin Function Descriptions (ADuC7029)
Ball No.
Mnemonic
ADC3/CMP1
ADC1
Description
A1
A2
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 0.
3.3 V Analog Power.
A3
ADC0
A4
AVDD
A5
VREF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
A6
A7
P1.0/T1/SPM0/PLAI[0]
P1.1/SPM1/PLAI[1]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
B1
B2
B3
B4
B5
B6
ADC6
Single-Ended or Differential Analog Input 6.
ADC5
Single-Ended or Differential Analog Input 5.
ADC4
Single-Ended or Differential Analog Input 4.
AGND
Analog Ground. Ground reference point for the analog circuitry.
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
DACREF
P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
B7
C1
P1.3/SPM3/PLAI[3]
GNDREF
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
C2
C3
C4
C5
AGND
Analog Ground. Ground reference point for the analog circuitry.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Ground for GPIO (see Table 78). Typically connected to DGND.
ADC2/CMP0
IOGND
P1.2/SPM2/PLAI[2]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
C6
C7
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
P1.5/SPM5/PLAI[5]/IRQ3
D1
D2
D3
D4
DAC0/ADC12
DAC0 Voltage Output/ADC Input 12.
DAC3 Voltage Output/ADC Input 15.
DAC1 Voltage Output/ADC Input 13.
DAC3/ADC15
DAC1/ADC13
P3.3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
D5
D6
D7
P3.4/PWM2H/PLAI[12]
P3.6/PWMTRIP/PLAI[14]
P1.7/SPM7/PLAO[0]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array
Input Element 14.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
Rev. F | Page 33 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Ball No.
E1
Mnemonic
Description
TMS
JTAG Test Port Input, Test Mode Select. Debug and download access.
E2
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot mode. The ADuC7029 enters UART download mode if BM is low
at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
E3
E4
E5
DAC2/ADC14
IOVDD
DAC2 Voltage Output/ADC Input 14.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
P3.2/PWM1H/PLAI[10]
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
E6
E7
P3.5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External
Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array
Output Element 4.
F1
F2
TDI
JTAG Test Port Input, Test Data In. Debug and download access.
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
F3
F4
IOGND
Ground for GPIO (see Table 78). Typically connected to DGND.
P3.1/PWM0L/PLAI[9]
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
F5
P3.0/PWM0H/PLAI[8]
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
F6
F7
RST
Reset Input, Active Low.
P2.0/SPM9/PLAO[5]/CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable
Logic Array Output Element 5/Start Conversion Input Signal for ADC.
G1
G2
G3
TCK
TDO
LVDD
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
G4
G5
DGND
Ground for Core Logic.
P0.3/TRST/ADCBUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal
Output.
G6
G7
IRQ0/P0.4/PWMTRIP/PLAO[1]
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.
Rev. F | Page 34 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
fS = 774kSPS
0.8
fS = 774kSPS
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
ADC CODES
ADC CODES
Figure 28. Typical INL Error, fS = 774 kSPS
Figure 31. Typical DNL Error, fS = 774 kSPS
1.0
0.8
1.0
0.8
fS = 1MSPS
fS = 1MSPS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
ADC CODES
ADC CODES
Figure 29. Typical INL Error, fS = 1 MSPS
Figure 32. Typical DNL Error, fS = 1 MSPS
1.0
0
–0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–0.2
–0.3
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
WCN
WCP
WCP
WCN
1.0
1.5
2.0
2.5
3.0
1.0
1.5
2.0
2.5
3.0
EXTERNAL REFERENCE (V)
EXTERNAL REFERENCE (V)
Figure 30. Typical Worst-Case (Positive (WCP) and Negative (WCN))
INL Error vs. VREF, fS = 774 kSPS
Figure 33. Typical Worst-Case (Positive (WCP )and Negative (WCN))
DNL Error vs. VREF, fS = 774 kSPS
Rev. F | Page 35 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
75
70
65
60
55
50
45
40
–76
–78
–80
–82
–84
–86
SNR
THD
–88
3.0
1161
1162
BIN
1163
1.0
1.5
2.0
2.5
EXTERNAL REFERENCE (V)
Figure 34. Code Histogram Plot, fs = 774 kSPS, VIN = 0.7 V
Figure 37. Typical Dynamic Performance vs. VREF
0
1500
1450
1400
1350
1300
1250
1200
1150
1100
1050
1000
fS = 774kSPS,
SNR = 69.3dB,
THD = –80.8dB,
PHSN = –83.4dB
–20
–40
–60
–80
–100
–120
–140
–160
0
100
200
–50
0
50
100
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 35. Dynamic Performance, fS = 774 kSPS
Figure 38. On-Chip Temperature Sensor Voltage Output vs. Temperature
20
0
39.8
39.7
39.6
39.5
39.4
39.3
39.2
39.1
39.0
38.9
fS = 1MSPS,
SNR = 70.4dB,
THD = –77.2dB,
PHSN = –78.9dB
–20
–40
–60
–80
–100
–120
–140
–160
0
50
100
150
200
–40
0
25
85
125
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 36. Dynamic Performance, fS = 1 MSPS
Figure 39. Current Consumption vs. Temperature @ CD = 0
Rev. F | Page 36 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
12.05
12.00
11.95
11.90
11.85
11.80
11.75
11.70
11.65
11.60
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
11.55
–40
0
25
85
125
–40
0
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 40. Current Consumption vs. Temperature @ CD = 3
Figure 42. Current Consumption vs. Temperature in Sleep Mode
7.85
37.4
37.2
37.0
36.8
36.6
36.4
36.2
7.80
7.75
7.70
7.65
7.60
7.55
7.50
7.45
7.40
–40
0
25
85
125
62.25
125.00
250.00
500.00
1000.00
TEMPERATURE (°C)
SAMPLING FREQUENCY (kSPS)
Figure 41. Current Consumption vs. Temperature @ CD = 7
Figure 43. Current Consumption vs. Sampling Frequency
Rev. F | Page 37 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
TERMINOLOGY
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise.
ADC SPECIFICATIONS
Integral Nonlinearity (INL)
The maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
½ LSB below the first code transition, and full scale, a point
½ LSB above the last code transition.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Offset Error
The deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, that is, +½ LSB.
Relative Accuracy
Otherwise known as endpoint linearity, relative accuracy is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale error.
Gain Error
The deviation of the last code transition from the ideal AIN
voltage (full scale − 1.5 LSB) after the offset error has been
adjusted out.
Voltage Output Settling Time
The amount of time it takes the output to settle to within a
1 LSB level for a full-scale input change.
Signal to (Noise + Distortion) Ratio (SINAD)
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
Rev. F | Page 38 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
OVERVIEW OF THE ARM7TDMI CORE
The ARM7® core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be eight bits, 16 bits, or 32 bits. The
length of the instruction word is 32 bits.
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are
•
Normal interrupt or IRQ, which is provided to service
general-purpose interrupt handling of internal and
external events.
The ARM7TDMI is an ARM7 core with four additional features.
•
•
•
•
T support for the thumb (16-bit) instruction set.
D support for debug.
M support for long multiplications.
I includes the EmbeddedICE module to support embedded
system debugging.
•
Fast interrupt or FIQ, which is provided to service data
transfers or communication channels with low latency.
FIQ has priority over IRQ.
•
•
•
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI), which can be used
to make a call to an operating system.
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set that is compressed into 16 bits,
called the thumb instruction set. Faster execution from 16-bit
memory and greater code density can usually be achieved by
using the thumb instruction set instead of the ARM instruction
set, which makes the ARM7TDMI core particularly suitable for
embedded applications.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and six status registers. Each operating mode has
dedicated banked registers.
However, the thumb mode has two limitations.
•
•
Thumb code typically requires more instructions for the
same job. As a result, ARM code is usually best for
maximizing the performance of time-critical code.
The thumb instruction set does not include some of the
instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15), and the
current program status register (CPSR) are usable. The
remaining registers are used for system-level programming and
exception handling only.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All excep-
tion modes have replacement banked registers for the stack
pointer (R13) and the link register (R14), as represented in
Figure 44. The fast interrupt mode has more registers (R8 to R12)
for fast interrupt processing. This means that interrupt processing
can begin without the need to save or restore these registers
and, thus, save critical time in the interrupt handling process.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM
and ARM thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instruc-
tions that perform 32-bit by 32-bit multiplication with a 64-bit
result, and 32-bit by 32-bit multiplication-accumulation (MAC)
with a 64-bit result. These results are achieved in fewer cycles
than required on a standard ARM7 core.
R0
USABLE IN USER MODE
R1
SYSTEM MODES ONLY
R2
R3
R4
EmbeddedICE (I)
R5
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and watch-
point registers that allow code to be halted for debugging purposes.
These registers are controlled through the JTAG test port.
R6
R7
R8_FIQ
R9_FIQ
R8
R9
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R10
R11
R12
R13
R14
R15 (PC)
R13_UND
R13_IRQ
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers can be inspected as well as the Flash/EE,
SRAM, and memory mapped registers.
R13_ABT
R14_ABT
R14_UND
R14_IRQ
R13_SVC
R14_SVC
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
CPSR
SPSR_FIQ
FIQ
MODE
SVC
MODE
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
USER MODE
Figure 44. Register Organization
Rev. F | Page 39 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
materials from ARM:
At the end of this time, the ARM7TDMI executes the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 µs in a
system using a continuous 41.78 MHz processor clock.
•
•
DDI0029G, ARM7TDMI Technical Reference Manual
DDI-0100, ARM Architecture Reference Manual
The maximum interrupt request (IRQ) latency calculation is
similar but must allow for the fact that FIQ has higher priority
and may delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles if
the LDM command is not used. Some compilers have an option
to compile without using this command. Another option is to run
the part in thumb mode where the time is reduced to 22 cycles.
INTERRUPT LATENCY
The worst-case latency for a fast interrupt request (FIQ)
consists of the following:
•
The longest time the request can take to pass through the
synchronizer
The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer plus the time to enter the
exception mode.
•
The time for the longest instruction to complete (the
longest instruction is an LDM) that loads all the registers
including the PC
The time for the data abort entry
The time for FIQ entry
•
•
Note that the ARM7TDMI always runs in ARM (32-bit) mode
when in privileged modes, for example, when executing
interrupt service routines.
Rev. F | Page 40 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
MEMORY ORGANIZATION
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two
separate blocks of memory: 8 kB of SRAM and 64 kB of on-chip
Flash/EE memory. The 62 kB of on-chip Flash/EE memory is
available to the user, and the remaining 2 kB are reserved for
the factory-configured boot page. These two blocks are mapped
as shown in Figure 45.
FLASH/EE MEMORY
The total 64 kB of Flash/EE memory is organized as 32 k × 16 bits;
31 k × 16 bits is user space and 1 k × 16 bits is reserved for the
on-chip kernel. The page size of this Flash/EE memory is 512 bytes.
Sixty-two kilobytes of Flash/EE memory are available to the
user as code and nonvolatile data memory. There is no
distinction between data and program because ARM code
shares the same space. The real width of the Flash/EE memory
is 16 bits, which means that in ARM mode (32-bit instruction),
two accesses to the Flash/EE are necessary for each instruction
fetch. It is therefore recommended to use thumb mode when
executing from Flash/EE memory for optimum access speed.
The maximum access speed for the Flash/EE memory is
41.78 MHz in thumb mode and 20.89 MHz in full ARM mode.
More details about Flash/EE access time are outlined in the
Execution Time from SRAM and Flash/EE section.
0xFFFFFFFF
0xFFFF0000
MMRs
RESERVED
0x40000FFFF
EXTERNAL MEMORY REGION 3
0x40000000
RESERVED
0x30000FFFF
EXTERNAL MEMORY REGION 2
0x30000000
RESERVED
0x20000FFFF
EXTERNAL MEMORY REGION 1
0x20000000
RESERVED
0x10000FFFF
EXTERNAL MEMORY REGION 0
0x10000000
RESERVED
0x0008FFFF
SRAM
FLASH/EE
0x00080000
Eight kilobytes of SRAM are available to the user, organized as
2 k × 32 bits, that is, two words. ARM code can run directly
from SRAM at 41.78 MHz, given that the SRAM array is
configured as a 32-bit wide memory array. More details about
SRAM access time are outlined in the Execution Time from
SRAM and Flash/EE section.
RESERVED
0x00011FFF
SRAM
0x00010000
0x0000FFFF REMAPPABLE MEMORY SPACE
0x00000000
(FLASH/EE OR SRAM)
Figure 45. Physical Memory Map
Note that by default, after a reset, the Flash/EE memory is
mirrored at Address 0x00000000. It is possible to remap the
SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP
MMR. This remap function is described in more detail in the
Flash/EE Memory section.
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
MEMORY ACCESS
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers, except the core registers, reside
in the MMR area. All shaded locations shown in Figure 47 are
unoccupied or reserved locations and should not be accessed by
user software. Table 16 shows the full MMR memory map.
The ARM7 core sees memory as a linear array of a 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 45.
The ADuC7019/20/21/22/24/25/26/27/28/29 memory organiza-
tions are configured in little endian format, which means that
the least significant byte is located in the lowest byte address,
and the most significant byte is in the highest byte address.
The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA buses: the advanced high performance bus (AHB)
used for system modules and the advanced peripheral bus
(APB) used for lower performance peripheral. Access to the
AHB is one cycle, and access to the APB is two cycles. All
peripherals on the ADuC7019/20/21/22/24/25/26/27/28/29 are
on the APB except the Flash/EE memory, the GPIOs (see
Table 78), and the PWM.
BIT 31
BIT 0
BYTE 3 BYTE 2 BYTE 1 BYTE 0
.
.
.
.
.
.
.
.
.
.
.
.
0xFFFFFFFF
B
7
3
A
6
2
9
5
1
8
4
0
0x00000004
0x00000000
32 BITS
Figure 46. Little Endian Format
Rev. F | Page 41 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
0xFFFFFFFF
0xFFFFFC3C
Table 16. Complete MMR List
Access
Byte Type
Default
Value
PWM
0xFFFFFC00
Address Name
Page
0xFFFFF820
IRQ Address Base = 0xFFFF0000
FLASH CONTROL
INTERFACE
0x0000
0x0004
0x0008
0x000C
0x0010
0x0100
0x0104
0x0108
0x010C
IRQSTA
IRQSIG1
IRQEN
IRQCLR
SWICFG
FIQSTA
FIQSIG1
FIQEN
4
4
4
4
4
4
4
4
4
R
R
R/W
W
W
R
R
R/W
W
0x00000000
0x00XXX000 83
0x00000000
0x00000000
0x00000000
0x00000000
0x00XXX000 84
0x00000000
0x00000000
83
0xFFFFF800
0xFFFFF46C
GPIO
83
83
84
84
0xFFFFF400
0xFFFF0B54
PLA
0xFFFF0B00
0xFFFF0A14
SPI
0xFFFF0A00
84
84
FIQCLR
0xFFFF0948
I2C1
1 Depends on the level on the external interrupt pins (P0.4, P0.5, P1.4, and P1.5).
0xFFFF0900
0xFFFF0848
I2C0
System Control Address Base = 0xFFFF0200
0xFFFF0800
0x0220
0x0230
0x0234
REMAP
RSTSTA
RSTCLR
1
1
1
R/W
R/W
W
0xXX1
0x01
0x00
55
55
55
0xFFFF0730
UART
0xFFFF0700
0xFFFF0620
1 Depends on the model.
DAC
0xFFFF0600
Timer Address Base = 0xFFFF0300
0xFFFF0538
ADC
0x0300
0x0304
0x0308
0x030C
0x0320
0x0324
0x0328
0x032C
0x0330
0x0340
0x0344
0x0348
0x034C
0x0360
0x0364
0x0368
0x036C
T0LD
2
2
2
1
4
4
2
1
4
4
4
2
1
2
2
2
1
R/W
R
R/W
W
R/W
R
R/W
W
R/W
R/W
R
R/W
W
R/W
R
R/W
W
0x0000
0xFFFF
0x0000
0xFF
0x00000000
0xFFFFFFFF
0x0000
85
85
85
85
86
86
86
87
87
87
87
87
88
88
88
88
89
0xFFFF0500
T0VAL
T0CON
T0CLRI
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
T2LD
T2VAL
T2CON
T2CLRI
T3LD
T3VAL
T3CON
T3CLRI
0xFFFF0490
BAND GAP
REFERENCE
0xFFFF048C
0xFFFF0448
POWER SUPPLY
MONITOR
0xFFFF0440
0xFFFF0420
PLL AND
OSCILLATOR CONTROL
0xFF
0xFFFF0404
0x00000000
0x00000000
0xFFFFFFFF
0x0000
0xFF
0x0000
0xFFFF
0x0000
0x00
0xFFFF0370
WATCHDOG
TIMER
0xFFFF0360
0xFFFF0350
WAKE-UP
TIMER
0xFFFF0340
0xFFFF0334
GENERAL-PURPOSE
TIMER
0xFFFF0320
0xFFFF0310
TIMER 0
0xFFFF0300
0xFFFF0238
REMAP AND
SYSTEM CONTROL
PLL Base Address = 0xFFFF0400
0xFFFF0220
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
POWKEY1
POWCON
POWKEY2
PLLKEY1
PLLCON
2
2
2
2
1
2
W
R/W
W
W
R/W
W
0x0000
0x0003
0x0000
0x0000
0x21
60
60
60
60
60
60
0xFFFF0110
INTERRUPT
CONTROLLER
0xFFFF0000
Figure 47. Memory Mapped Registers
PLLKEY2
0x0000
PSM Address Base = 0xFFFF0440
0x0440
0x0444
PSMCON
CMPCON
2
2
R/W
R/W
0x0008
0x0000
57
58
Rev. F | Page 42 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Access
Byte Type
Default
Value
Access
Byte Type
Default
Value
Address Name
Page
Address Name
Page
Reference Address Base = 0xFFFF0480
I2C0 Base Address = 0xFFFF0800
0x048C
REFCON
1
R/W
0x00
50
0x0800
0x0804
0x0808
0x080C
0x0810
0x0814
0x0818
0x081C
0x0824
0x0828
0x082C
0x0830
0x0838
0x083C
0x0840
0x0844
0x0848
0x084C
I2C0MSTA
I2C0SSTA
I2C0SRX
I2C0STX
I2C0MRX
I2C0MTX
I2C0CNT
I2C0ADR
I2C0BYTE
I2C0ALT
I2C0CFG
I2C0DIV
I2C0ID0
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
R/W
R
R
W
R
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x1F1F
0x00
0x00
0x00
0x00
0x01
0x0000
76
76
77
77
77
77
77
77
77
78
78
79
79
79
79
79
79
79
ADC Address Base = 0xFFFF0500
0x0500
0x0504
0x0508
0x050C
0x0510
0x0514
0x0530
0x0534
ADCCON
ADCCP
2
1
1
1
4
1
2
2
R/W
R/W
R/W
R
0x0600
0x00
0x01
0x00
0x00000000
0x00
46
47
47
48
48
48
48
48
W
ADCCN
ADCSTA
ADCDAT
ADCRST
ADCGN
ADCOF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
0x0200
0x0200
DAC Address Base = 0xFFFF0600
I2C0ID1
I2C0ID2
I2C0ID3
I2C0CCNT
I2C0FSTA
0x0600
0x0604
0x0608
0x060C
0x0610
0x0614
0x0618
0x061C
DAC0CON
DAC0DAT
DAC1CON
DAC1DAT
DAC2CON
DAC2DAT
DAC3CON
DAC3DAT
1
4
1
4
1
4
1
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00000000
0x00
0x00000000
0x00
0x00000000
0x00
56
56
56
56
56
56
56
56
I2C1 Base Address = 0xFFFF0900
0x0900
0x0904
0x0908
0x090C
0x0910
0x0914
0x0918
0x091C
0x0924
0x0928
0x092C
0x0930
0x0938
0x093C
0x0940
0x0944
0x0948
0x094C
I2C1MSTA
I2C1SSTA
I2C1SRX
I2C1STX
I2C1MRX
I2C1MTX
I2C1CNT
I2C1ADR
I2C1BYTE
I2C1ALT
I2C1CFG
I2C1DIV
I2C1ID0
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
R/W
R
R
W
R
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x1F1F
0x00
0x00
0x00
0x00
0x01
0x0000
76
76
77
77
77
77
77
77
77
78
78
79
79
79
79
79
79
79
0x00000000
UART Base Address = 0xFFFF0700
0x0700
COMTX
COMRX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x60
0x00
0x00
0x04
0x01
0xAA
0x0000
71
71
71
71
72
72
72
72
72
73
73
73
73
74
73
W
COMDIV0
COMIEN0
COMDIV1
COMIID0
COMCON0
COMCON1
COMSTA0
COMSTA1
COMSCR
COMIEN1
COMIID1
COMADR
COMDIV2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0704
0x0708
0x070C
0x0710
0x0714
0x0718
0x071C
0x0720
0x0724
0x0728
0x072C
R
I2C1ID1
I2C1ID2
I2C1ID3
I2C1CCNT
I2C1FSTA
R/W
R/W
R
R/W
R/W
SPI Base Address = 0xFFFF0A00
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
1
1
1
1
2
R
R
W
R/W
R/W
0x00
0x00
0x00
0x1B
0x0000
75
75
75
75
75
Rev. F | Page 43 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Access
Byte Type
Default
Value
Access
Byte Type
Default
Value
Address Name
Page
Address Name
Page
PLA Base Address = 0xFFFF0B00
GPIO Base Address = 0xFFFFF400
0x0B00
0x0B04
0x0B08
0x0B0C
0x0B10
0x0B14
0x0B18
0x0B1C
0x0B20
0x0B24
0x0B28
0x0B2C
0x0B30
0x0B34
0x0B38
0x0B3C
0x0B40
0x0B44
0x0B48
0x0B4C
0x0B50
0x0B54
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
PLACLK
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
4
4
4
4
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
81
81
82
82
82
82
0xF400
0xF404
0xF408
0xF40C
0xF410
0xF420
0xF424
0xF428
0xF42C
0xF430
0xF434
0xF438
0xF43C
0xF440
0xF444
0xF448
0xF450
0xF454
0xF458
0xF460
0xF464
0xF468
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
GP0DAT
GP0SET
GP0CLR
GP0PAR
GP1DAT
GP1SET
GP1CLR
GP1PAR
GP2DAT
GP2SET
GP2CLR
GP3DAT
GP3SET
GP3CLR
GP4DAT
GP4SET
GP4CLR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
R/W
R/W
R/W
R/W
R/W
R/W
W
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x000000XX1 70
0x000000XX1 70
0x000000XX1 70
68
68
68
68
68
W
R/W
R/W
W
0x20000000
68
0x000000XX1 69
0x000000XX1 70
0x000000XX1 70
W
R/W
R/W
W
W
R/W
W
W
R/W
W
0x00000000
68
0x000000XX1 69
0x000000XX1 70
0x000000XX1 70
0x000000XX1 69
0x000000XX1 70
0x000000XX1 70
0x000000XX1 69
0x000000XX1 70
0x000000XX1 70
PLAIRQ
PLAADC
PLADIN
PLADOUT
PLALCK
0x00000000
0x00000000
0x00000000
0x00000000
0x00
W
W
1 X = 0, 1, 2, or 3.
External Memory Base Address = 0xFFFFF000
Flash/EE Base Address = 0xFFFFF800
0xF000
0xF010
0xF014
0xF018
0xF01C
0xF020
0xF024
0xF028
0xF02C
XMCFG
1
1
1
1
1
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
90
90
90
90
90
90
90
90
90
0xF800
0xF804
0xF808
0xF80C
0xF810
0xF818
0xF81C
0xF820
FEESTA
1
2
1
2
2
3
4
4
R
0x20
0x0000
0x07
0xXXXX1
52
52
53
53
53
53
53
53
XM0CON
XM1CON
XM2CON
XM3CON
XM0PAR
XM1PAR
XM2PAR
XM3PAR
FEEMOD
FEECON
FEEDAT
FEEADR
FEESIGN
FEEPRO
FEEHIDE
R/W
R/W
R/W
R/W
R
0x00
0x0000
0x70FF
0x70FF
0x70FF
0x70FF
0xFFFFFF
0x00000000
0xFFFFFFFF
R/W
R/W
1 X = 0, 1, 2, or 3.
PWM Base Address = 0xFFFFFC00
0xFC00
0xFC04
0xFC08
0xFC0C
0xFC10
0xFC14
0xFC18
0xFC1C
0xFC20
0xFC24
PWMCON
PWMSTA
PWMDAT0
PWMDAT1
PWMCFG
PWMCH0
PWMCH1
PWMCH2
PWMEN
2
2
2
2
2
2
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
66
66
67
67
67
67
67
67
67
67
PWMDAT2
Rev. F | Page 44 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
ADC CIRCUIT OVERVIEW
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 49.
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to
1 MSPS when the clock source is 41.78 MHz. This block
provides the user with a multichannel multiplexer, a differential
track-and-hold, an on-chip reference, and an ADC.
1111 1111 1111
1111 1111 1110
1111 1111 1101
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of three modes.
1111 1111 1100
FS
1LSB =
4096
Fully differential mode, for small and balanced signals
Single-ended mode, for any single-ended signals
Pseudo differential mode, for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
0V 1LSB
+FS – 1LSB
The converter accepts an analog input range of 0 V to VREF when
operating in single-ended or pseudo differential mode. In fully
differential mode, the input signal must be balanced around a
common-mode voltage (VCM) in the 0 V to AVDD range with a
maximum amplitude of 2 VREF (see Figure 48).
VOLTAGE INPUT
Figure 49. ADC Transfer Function in Pseudo Differential or Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN– input voltage pins (that
is, VIN+ − VIN–). The maximum amplitude of the differential
signal is, therefore, –VREF to +VREF p-p (that is, 2 × VREF). This is
regardless of the common mode (CM). The common mode is
the average of the two signals, for example, (VIN+ + VIN–)/2, and
is, therefore, the voltage that the two inputs are centered on.
This results in the span of each input being CM VREF/2. This
voltage has to be set up externally, and its range varies with VREF
(see the Driving the Analog Inputs section).
AV
DD
V
2V
CM
REF
V
CM
2V
REF
V
2V
CM
REF
0
Figure 48. Examples of Balanced Signals in Fully Differential Mode
A high precision, low drift, factory calibrated, 2.5 V reference is
provided on-chip. An external reference can also be connected as
described in the Band Gap Reference section.
The output coding is twos complement in fully differential mode
with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when
VREF = 2.5 V. The output result is 11 bits, but this is shifted by 1
to the right. This allows the result in ADCDAT to be declared as a
signed integer when writing C code. The designed code
transitions occur midway between successive integer LSB values
(that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS − 3/2 LSB). e ideal
input/output transfer characteristic is shown in Figure 50.
Single or continuous conversion modes can be initiated in the
CONVSTART
software. An external
pin, an output generated from
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC channel
input. This facilitates an internal temperature sensor channel
that measures die temperature to an accuracy of 3°C.
SIGN
BIT
0
0
0
1111 1111 1110
1111 1111 1100
1111 1111 1010
2 × V
4096
REF
1LSB =
0
0
1
0000 0000 0010
0000 0000 0000
1111 1111 1110
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range
is 0 V to VREF. The output coding is straight binary in pseudo
differential and single-ended modes with
1
1
1
0000 0000 0100
0000 0000 0010
0000 0000 0000
1 LSB = FS/4096, or
–V
+ 1LSB
0LSB
+V
– 1LSB
REF
REF
2.5 V/4096 = 0.61 mV, or
610 μV when VREF = 2.5 V
VOLTAGE INPUT (V + – V –)
IN
IN
Figure 50. ADC Transfer Function in Differential Mode
Rev. F | Page 45 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ACQ
BIT TRIAL
WRITE
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
ADC CLOCK
CONV
START
The top four bits are the sign bits. The 12-bit result is placed
from Bit 16 to Bit 27, as shown in Figure 51. Again, it should be
noted that, in fully differential mode, the result is represented in
twos complement format. In pseudo differential and single-
ended modes, the result is represented in straight binary format.
ADC
BUSY
DATA
ADCDAT
31
27
16 15
0
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
SIGN BITS
12-BIT ADC RESULT
Figure 51. ADC Result Format
Figure 52. ADC Timing
The same format is used in DACxDAT, simplifying the software.
ADuC7019
Current Consumption
The ADuC7019 is identical to the ADuC7020 except for one
buffered ADC channel, ADC3, and it has only three DACs. The
output buffer of the fourth DAC is internally connected to the
ADC3 channel as shown in Figure 53.
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA
multiplied by the sampling frequency (in kilohertz (kHz)).
Figure 43 shows the current consumption vs. the sampling
frequency of the ADC.
ADuC7019
1MSPS
12-BIT ADC
12-BIT
DAC
MUX
Timing
ADC3
DAC3
Figure 52 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight clocks
and the clock divider is 2. The number of extra clocks (such as
bit trial or write) is set to 19, which gives a sampling rate of
774 kSPS. For conversion on the temperature sensor, the ADC
acquisition time is automatically set to 16 clocks, and the ADC
clock divider is set to 32. When using multiple channels,
including the temperature sensor, the timing settings revert to
the user-defined settings after reading the temperature sensor
channel.
ADC15
Figure 53. ADC3 Buffered Input
Note that the DAC3 output pin must be connected to a 10 nF
capacitor to AGND. This channel should be used to measure dc
voltages only. ADC calibration may be necessary on this channel.
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
Table 17. ADCCON Register
Name
Address
Default Value
Access
ADCCON
0xFFFF0500
0x0600
R/W
ADCCON is an ADC control register that allows the programmer
to enable the ADC peripheral, select the mode of operation of
the ADC (in single-ended mode, pseudo differential mode, or
fully differential mode), and select the conversion type. This
MMR is described in Table 18.
Rev. F | Page 46 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 18. ADCCON MMR Bit Designations
Table 19. ADCCP Register
Bit
Value Description
Name
Address
Default Value
Access
15:13
12:10
Reserved.
ADC clock speed.
ADCCP
0xFFFF0504
0x00
R/W
ADCCP is an ADC positive channel selection register. This
MMR is described in Table 20.
000
fADC/1. This divider is provided to obtain
1 MSPS ADC with an external clock <41.78 MHz.
001
010
011
100
101
fADC/2 (default value).
fADC/4.
fADC/8.
fADC/16.
fADC/32.
ADC acquisition time.
Two clocks.
Four clocks.
Eight clocks (default value).
16 clocks.
Enable start conversion.
Table 20. ADCCP1 MMR Bit Designation
Bit
7:5
4:0
Value
Description
Reserved.
Positive channel selection bits.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
ADC0.
ADC1.
ADC2.
ADC3.
ADC4.
ADC5.
ADC6.
ADC7.
ADC8.
ADC9.
ADC10.
ADC11.
DAC0/ADC12.
DAC1/ADC13.
DAC2/ADC14.
DAC3/ADC15.
9:8
7
00
01
10
11
Set by the user to start any type of conversion
command. Cleared by the user to disable a
start conversion (clearing this bit does not
stop the ADC when continuously converting).
6
5
Reserved.
ADC power control.
Set by the user to place the ADC in normal
mode (the ADC must be powered up for at least
5 μs before it converts correctly). Cleared by the
user to place the ADC in power-down mode.
Conversion mode.
Single-ended mode.
Differential mode.
Pseudo differential mode.
Reserved.
Temperature sensor.
AGND (self-diagnostic feature).
Internal reference (self-diagnostic feature).
AVDD/2.
4:3
2:0
00
01
10
11
Others Reserved.
1 ADC and DAC channel availability depends on the part model. See Ordering
Guide for details.
Conversion type.
000
001
010
011
Enable CONVSTART pin as a conversion input.
Enable Timer1 as a conversion input.
Enable Timer0 as a conversion input.
Single software conversion. Sets to 000 after
conversion (note that Bit 7 of ADCCON MMR
should be cleared after starting a single
software conversion to avoid further
Table 21. ADCCN Register
Name
Address
Default Value
Access
ADCCN
0xFFFF0508
0x01
R/W
ADCCN is an ADC negative channel selection register. This
MMR is described in Table 22.
conversions triggered by the CONVSTART pin).
100
101
Continuous software conversion.
PLA conversion.
Other Reserved.
Rev. F | Page 47 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 27. ADCOF Register
Table 22. ADCCN MMR Bit Designation
Name
Address
Default Value
0x0200
Access
Bit
7:5
4:0
Value
Description
ADCOF
0xFFFF0534
R/W
Reserved.
Negative channel selection bits.
ADCOF is a 10-bit offset calibration register.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
ADC0.
ADC1.
ADC2.
ADC3.
ADC4.
ADC5.
ADC6.
ADC7.
ADC8.
ADC9.
ADC10.
ADC11.
DAC0/ADC12.
DAC1/ADC13.
DAC2/ADC14.
DAC3/ADC15.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three modes: differential, pseudo
differential, and single-ended.
Differential Mode
The ADuC7019/20/21/22/24/25/26/27/28/29 each contain a
successive approximation ADC based on two capacitive DACs.
Figure 54 and Figure 55 show simplified schematics of the ADC
in acquisition and conversion phase, respectively. The ADC
comprises control logic, a SAR, and two capacitive DACs. In
Figure 54 (the acquisition phase), SW3 is closed and SW1 and
SW2 are in Position A. The comparator is held in a balanced
condition, and the sampling capacitor arrays acquire the
differential signal on the input.
Internal reference (self-diagnostic feature).
Others Reserved.
CAPACITIVE
DAC
COMPARATOR
Table 23. ADCSTA Register
C
C
B
A
S
S
CHANNEL+
CHANNEL–
AIN0
Name
Address
Default Value
Access
SW1
SW2
CONTROL
LOGIC
MUX
SW3
ADCSTA
0xFFFF050C
0x00
R
A
B
AIN11
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADCBUSY
pin. This pin is high during a conversion. When the conversion
is finished, ADCBUSY goes back low. This information can be
available on P0.5 (see the General-Purpose Input/Output
section) if enabled in the ADCCON register.
V
REF
CAPACITIVE
DAC
Figure 54. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 55, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. The output
impedances of the sources driving the VIN+ and VIN– input
voltage pins must be matched; otherwise, the two inputs have
different settling times, resulting in errors.
Table 24. ADCDAT Register
Name
Address
Default Value
Access
ADCDAT
0xFFFF0510
0x00000000
R
ADCDAT is an ADC data result register. It holds the 12-bit
ADC result as shown in Figure 51.
CAPACITIVE
DAC
Table 25. ADCRST Register
Name
Address
Default Value
Access
COMPARATOR
C
C
B
A
S
S
CHANNEL+
CHANNEL–
AIN0
ADCRST
0xFFFF0514
0x00
R/W
SW1
SW2
CONTROL
LOGIC
MUX
SW3
ADCRST resets the digital interface of the ADC. Writing any value
to this register resets all the ADC registers to their default values.
A
B
AIN11
V
REF
Table 26. ADCGN Register
CAPACITIVE
DAC
Name
Address
Default Value
Access
Figure 55. ADC Conversion Phase
ADCGN
0xFFFF0530
0x0200
R/W
ADCGN is a 10-bit gain calibration register.
Rev. F | Page 48 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
AV
DD
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the VIN− pin
of the ADuC7019/20/21/22/24/25/26/27/28/29. SW2 switches
between A (Channel−) and B (VREF). The VIN− pin must be
connected to ground or a low voltage. The input signal on VIN+
can then vary from VIN− to VREF + VIN−. Note that VIN− must be
chosen so that VREF + VIN− does not exceed AVDD.
D
C2
R1
C1
D
AV
DD
D
D
C2
R1
CAPACITIVE
DAC
C1
COMPARATOR
C
C
B
A
S
S
CHANNEL+
AIN0
SW1
SW2
CONTROL
LOGIC
MUX
SW3
Figure 58. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
Track Phase: Switches Closed
A
B
AIN11
V
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This can necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application. Figure 59 and Figure 60 give an
example of an ADC front end.
REF
CAPACITIVE
DAC
V
IN–
CHANNEL–
Figure 56. ADC in Pseudo Differential Mode
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The VIN− pin can be floating. The input signal range on
VIN+ is 0 V to VREF.
CAPACITIVE
DAC
COMPARATOR
C
C
B
A
S
S
CHANNEL+
AIN0
ADuC7019/
ADuC702x
SW1
CONTROL
LOGIC
MUX
SW3
10Ω
ADC0
CHANNEL–
AIN11
0.01µF
CAPACITIVE
DAC
Figure 59. Buffering Single-Ended/Pseudo Differential Input
Figure 57. ADC in Single-Ended Mode
ADuC7019/
ADuC702x
Analog Input Structure
ADC0
V
REF
Figure 58 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Care must be taken to ensure that the analog input
signals never exceed the supply rails by more than 300 mV;
exceeding 300 mV causes these diodes to become forward-
biased and start conducting into the substrate. These diodes can
conduct up to 10 mA without causing irreversible damage to
the part.
ADC1
Figure 60. Buffering Differential Inputs
When no amplifier is used to drive the analog input, the source
impedance should be limited to values lower than 1 kΩ. The
maximum source impedance depends on the amount of total
harmonic distortion (THD) that can be tolerated. The THD
increases as the source impedance increases and the performance
degrades.
The C1 capacitors in Figure 58 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors and
typically have a capacitance of 16 pF.
DRIVING THE ANALOG INPUTS
Internal or external references can be used for the ADC. In
the differential mode of operation, there are restrictions on the
common-mode input signal (VCM), which is dependent upon
the reference value and supply voltage used to ensure that the
signal remains within the supply rails. Table 28 gives some
calculated VCM minimum and VCM maximum values.
Rev. F | Page 49 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ADCCP = 0x10; // Select Temperature
Sensor as an // input to the ADC
Table 28. VCM Ranges
AVDD VREF
VCM Min VCM Max Signal Peak-to-Peak
REFCON = 0x01; // connect internal 2.5V
reference // to Vref pin
3.3 V 2.5 V
1.25 V
2.05 V
2.276 V
2.55 V
1.75 V
1.976 V
2.25 V
2.5 V
2.048 V 1.024 V
2.048 V
1.25 V
2.5 V
2.048 V
1.25 V
ADCCON = 0xE4; // continuous conversion
1.25 V
0.75 V
1.25 V
while(1)
{
3.0 V 2.5 V
2.048 V 1.024 V
while (!ADCSTA){};
// wait for end of conversion
1.25 V
0.75 V
CALIBRATION
b = (ADCDAT >> 16);
By default, the factory-set values written to the ADC offset
(ADCOF) and gain coefficient registers (ADCGN) yield
optimum performance in terms of end-point errors and
linearity for standalone operation of the part (see the
Specifications section). If system calibration is required, it is
possible to modify the default offset and gain coefficients to
improve end-point errors, but note that any modification to the
factory-set ADCOF and ADCGN values can degrade ADC
linearity performance.
// To calculate temperature in °C, use
the formula:
a = 0x525 - b;
// ((Temperature = 0x525 - Sensor
Voltage) / 1.3)
a /= 1.3;
b = floor(a);
printf("Temperature: %d
oC\n",b);
For system offset error correction, the ADC channel input stage
must be tied to AGND. A continuous software ADC conversion
loop must be implemented by modifying the value in ADCOF until
the ADC result (ADCDAT) reads Code 0 to Code 1. If the
ADCDAT value is greater than 1, ADCOF should be decremented
until ADCDAT reads 0 to 1. Offset error correction is done
digitally and has a resolution of 0.25 LSB and a range of
}
return 0;
}
BAND GAP REFERENCE
Each ADuC7019/20/21/22/24/25/26/27/28/29 provides an on-
chip band gap reference of 2.5 V, which can be used for the ADC
and DAC. This internal reference also appears on the VREF pin.
When using the internal reference, a 0.47 µF capacitor must be
connected from the external VREF pin to AGND to ensure stability
and fast response during ADC conversions. This reference can
also be connected to an external pin (VREF) and used as a refer-
ence for other circuits in the system. An external buffer is required
because of the low drive capability of the VREF output. A program-
mable option also allows an external reference input on the VREF
pin. Note that it is not possible to disable the internal reference.
Therefore, the external reference source must be capable of
overdriving the internal reference source.
3.125% of VREF
.
For system gain error correction, the ADC channel input stage
must be tied to VREF. A continuous software ADC conversion
loop must be implemented to modify the value in ADCGN
until the ADC result (ADCDAT) reads Code 4094 to Code 4095.
If the ADCDAT value is less than 4094, ADCGN should be
incremented until ADCDAT reads 4094 to 4095. Similar to the
offset calibration, the gain calibration resolution is 0.25 LSB
with a range of 3% of VREF
.
TEMPERATURE SENSOR
The ADuC7019/20/21/22/24/25/26/27/28/29 provide voltage
output from on-chip band gap references proportional to
absolute temperature. This voltage output can also be routed
through the front-end ADC multiplexer (effectively an additional
ADC channel input) facilitating an internal temperature sensor
channel, measuring die temperature to an accuracy of ±3°C.
Table 29. REFCON Register
Name
Address
Default Value
Access
REFCON
0xFFFF048C
0x00
R/W
The band gap reference interface consists of an 8-bit MMR
REFCON, described in Table 30.
The following is an example routine showing how to use the
internal temperature sensor:
Table 30. REFCON MMR Bit Designations
Bit
7:1
0
Description
int main(void)
{
Reserved.
Internal reference output enable. Set by user to
connect the internal 2.5 V reference to the VREF pin.
The reference can be used for an external component
but must be buffered. Cleared by user to disconnect
the reference from the VREF pin.
float a = 0;
short b;
ADCCON = 0x20;
delay(2000);
// power-on the ADC
Rev. F | Page 50 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
NONVOLATILE FLASH/EE MEMORY
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate
Flash/EE memory technology on-chip to provide the user with
nonvolatile, in-circuit reprogrammable memory space.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described in Table 1, before data retention is characterized. This
means that the Flash/EE memory is guaranteed to retain its data
for its fully specified retention lifetime every time the Flash/EE
memory is reprogrammed. In addition, note that retention
lifetime, based on an activation energy of 0.6 eV, derates with TJ
as shown in Figure 61.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7019/20/21/22/24/25/26/27/28/29, Flash/EE memory
technology allows the user to update program code space in-
circuit, without the need to replace one-time programmable
(OTP) devices at remote operating nodes.
600
Each part contains a 64 kB array of Flash/EE memory. The
lower 62 kB is available to the user and the upper 2 kB contain
permanently embedded firmware, allowing in-circuit serial
download. These 2 kB of embedded firmware also contain a
power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
450
300
150
0
Flash/EE Memory Reliability
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Figure 61. Flash/EE Memory Data Retention
PROGRAMMING
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
The 62 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the provided JTAG mode.
Serial Downloading (In-Circuit Programming)
1. Initial page erase sequence
2. Read/verify sequence (single Flash/EE)
3. Byte program sequence memory
The ADuC7019/20/21/22/24/25/26/27/28/29 facilitate code
download via the standard UART serial port or via the I2C port.
The parts enter serial download mode after a reset or power
cycle if the BM pin is pulled low through an external 1 kΩ
resistor. After a part is in serial download mode, the user can
download code to the full 62 kB of Flash/EE memory while
the device is in-circuit in its target application hardware. An
executable PC serial download is provided as part of the
development system for serial downloading via the UART.
The AN-806 Application Note describes the protocol for
serial downloading via the I2C.
4. Second read/verify sequence (endurance cycle)
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of −40° to +125°C. The results
allow the specification of a minimum endurance figure over a
supply temperature of 10,000 cycles.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
Rev. F | Page 51 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
SECURITY
FLASH/EE CONTROL INTERFACE
The 62 kB of Flash/EE memory available to the user can be read
and write protected.
Serial and JTAG programming use the Flash/EE control interface,
which includes the eight MMRs outlined in this section.
Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 42) protects
the 62 kB from being read through JTAG programming mode.
The other 31 bits of this register protect writing to the flash
memory. Each bit protects four pages, that is, 2 kB. Write
protection is activated for all types of access.
Table 31. FEESTA Register
Name
Address
Default Value
Access
FEESTA
0xFFFFF800
0x20
R
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 32.
Three Levels of Protection
Table 32. FEESTA MMR Bit Designations
•
Protection can be set and removed by writing directly into
FEEHIDE MMR. This protection does not remain after reset.
Protection can be set by writing into the FEEPRO MMR. It
takes effect only after a save protection command (0x0C)
and a reset. The FEEPRO MMR is protected by a key to
avoid direct access. The key is saved once and must be
entered again to modify FEEPRO. A mass erase sets the
key back to 0xFFFF but also erases all the user code.
Flash can be permanently protected by using the FEEPRO
MMR and a particular value of key: 0xDEADDEAD.
Entering the key again to modify the FEEPRO register
is not allowed.
Bit
15:6
5
Description
Reserved.
Reserved.
Reserved.
•
4
3
Flash interrupt status bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading the FEESTA register.
•
2
1
0
Flash/EE controller busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.
Command pass. Set by the MicroConverter when a
command completes successfully. Cleared automatic-
ally when reading the FEESTA register.
Sequence to Write the Key
1. Write the bit in FEEPRO corresponding to the page to be
protected.
2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5
must equal 0).
Table 33. FEEMOD Register
3. Write a 32-bit key in FEEADR and FEEDAT.
4. Run the write key command 0x0C in FEECON; wait for
the read to be successful by monitoring FEESTA.
5. Reset the part.
Name
Address
Default Value
Access
FEEMOD
0xFFFFF804
0x0000
R/W
FEEMOD sets the operating mode of the flash control interface.
Table 34 shows FEEMOD MMR bit designations.
To remove or modify the protection, the same sequence is used
with a modified value of FEEPRO. If the key chosen is the value
0xDEAD, the memory protection cannot be removed. Only a mass
erase unprotects the part, but it also erases all user code.
Table 34. FEEMOD MMR Bit Designations
Bit
15:9
8
Description
Reserved.
Reserved. This bit should always be set to 0.
The sequence to write the key is illustrated in the following
example (this protects writing Page 4 to Page 7 of the Flash):
7:5
Reserved. These bits should always be set to 0 except
when writing keys. See the Sequence to Write the Key
section.
FEEPRO=0xFFFFFFFD;
FEEMOD=0x48;
FEEADR=0x1234;
FEEDAT=0x5678;
FEECON= 0x0C;
//Protect pages 4 to 7
//Write key enable
//16 bit key value
//16 bit key value
// Write key command
4
Flash/EE interrupt enable. Set by user to enable the
Flash/EE interrupt. The interrupt occurs when a
command is complete. Cleared by user to disable
the Flash/EE interrupt.
3
Erase/write command protection. Set by user to
enable the erase and write commands. Cleared to
protect the Flash against the erase/write command.
The same sequence should be followed to protect the part
permanently with FEEADR = 0xDEAD and FEEDAT = 0xDEAD.
2:0
Reserved. These bits should always be set to 0.
Rev. F | Page 52 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 35. FEECON Register
Table 37. FEEDAT Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
FEECON
0xFFFFF808
0x07
R/W
FEEDAT
0xFFFFF80C
0xXXXX1
R/W
1 X = 0, 1, 2, or 3.
FEECON is an 8-bit command register. The commands are
described in Table 36.
FEEDAT is a 16-bit data register.
Table 36. Command Codes in FEECON
Table 38. FEEADR Register
Code Command
0x001 Null
0x011 Single read
Description
Name
Address
Default Value
Access
Idle state.
FEEADR
0xFFFFF810
0x0000
R/W
Load FEEDAT with the 16-bit data.
Indexed by FEEADR.
FEEADR is another 16-bit address register.
0x021 Single write
0x031 Erase/write
Write FEEDAT at the address pointed to
by FEEADR. This operation takes 50 µs.
Erase the page indexed by FEEADR and
write FEEDAT at the location pointed by
FEEADR. This operation takes approxi-
mately 24 ms.
Table 39. FEESIGN Register
Name
Address
Default Value
Access
FEESIGN
0xFFFFF818
0xFFFFFF
R
FEESIGN is a 24-bit code signature.
0x041 Single verify Compare the contents of the location
pointed by FEEADR to the data in
Table 40. FEEPRO Register
Name
Address
Default Value
Access
FEEDAT. The result of the comparison is
returned in FEESTA, Bit 1.
FEEPRO
0xFFFFF81C
0x00000000
R/W
0x051 Single erase
0x061 Mass erase
Erase the page indexed by FEEADR.
FEEPRO MMR provides protection following a subsequent
reset of the MMR. It requires a software key (see Table 42).
Erase 62 kB of user space. The 2 kB of
kernel are protected. This operation
takes 2.48 sec. To prevent accidental
execution, a command sequence is
required to execute this instruction.
See the Command Sequence for
Executing a Mass Erase section.
Reserved.
Reserved.
Reserved.
Reserved.
Table 41. FEEHIDE Register
Name
Address
Default Value
Access
FEEHIDE
0xFFFFF820
0xFFFFFFFF
R/W
FEEHIDE MMR provides immediate protection. It does not
require any software key. Note that the protection settings in
FEEHIDE are cleared by a reset (see Table 42).
0x07
0x08
0x09
Reserved
Reserved
Reserved
Table 42. FEEPRO and FEEHIDE MMR Bit Designations
0x0A Reserved
0x0B Signature
Bit
Description
Give a signature of the 64 kB of Flash/EE
in the 24-bit FEESIGN MMR. This
operation takes 32,778 clock cycles.
31
Read protection. Cleared by user to protect all code.
Set by user to allow reading the code.
0x0C Protect
This command can run only once. The
value of FEEPRO is saved and removed
only with a mass erase (0x06) of the key.
30:0
Write protection for Page 123 to Page 120, Page 119
to Page 116, and Page 0 to Page 3. Cleared by user to
protect the pages from writing. Set by user to allow
writing the pages.
0x0D Reserved
Reserved.
0x0E
0x0F
Reserved
Ping
Reserved.
No operation; interrupt generated.
Command Sequence for Executing a Mass Erase
FEEDAT=0x3CFF;
FEEADR = 0xFFC3;
FEEMOD= FEEMOD|0x8;
1 The FEECON register always reads 0x07 immediately after execution of any
of these commands.
//Erase key enable
FEECON=0x06;
//Mass erase command
Rev. F | Page 53 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
RESET AND REMAP
EXECUTION TIME FROM SRAM AND FLASH/EE
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 62.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle; the
access time of the SRAM is 2 ns, and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE): one
cycle to execute the instruction, and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction (a branch
instruction, for example) takes one cycle to fetch but also takes
two cycles to fill the pipeline with the new instructions.
0xFFFFFFFF
KERNEL
0x0008FFFF
0x00011FFF
FLASH/EE
INTERRUPT
SERVICE ROUTINES
0x00080000
0x00010000
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 22 ns, execution from Flash/EE cannot be done in
one cycle (as can be done from SRAM when the CD Bit = 0).
Also, some dead times are needed before accessing data for any
value of the CD bit.
SRAM
INTERRUPT
SERVICE ROUTINES
MIRROR SPACE
0x00000020
ARM EXCEPTION
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
VECTOR ADDRESSES 0x00000000 0x00000000
Figure 62. Remap for Exception Execution
By default, and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, which facilitates execution of exception routines from
SRAM instead of from Flash/EE. This means exceptions are
executed twice as fast, being executed in 32-bit ARM mode with
32-bit wide SRAM instead of 16-bit wide Flash/EE memory.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter, and
then four cycles are needed to fill the pipeline. A data-processing
instruction involving only the core register does not require any
extra clock cycles. However, if it involves data in Flash/EE, an
extra clock cycle is needed to decode the address of the data,
and two cycles are needed to get the 32-bit data from Flash/EE.
An extra cycle must also be added before fetching another
instruction. Data transfer instructions are more complex and
are summarized in Table 43.
Remap Operation
When a reset occurs on the ADuC7019/20/21/22/24/25/26/27/
28/29, execution automatically starts in the factory-programmed,
internal configuration code. This kernel is hidden and cannot
be accessed by user code. If the part is in normal mode (the BM
pin is high), it executes the power-on configuration routine of
the kernel and then jumps to the reset vector address,
Table 43. Execution Cycles in ARM/Thumb Mode
Fetch
Instructions Cycles
0x00000000, to execute the user’s reset exception routine.
Dead
Time
Dead
Time
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
Data Access
LD1
LDH
LDM/PUSH
STR1
STRH
2/1
2/1
2/1
2/1
2/1
2/1
1
1
N2
1
1
N1
2
1
1
1
N1
1
1
N1
2 × N2
2 × 20 ns
20 ns
The remap is done from Flash/EE by setting Bit 0 of the REMAP
register. Caution must be taken to execute this command from
Flash/EE, above Address 0x00080020, and not from the bottom
of the array because this is replaced by the SRAM.
STRM/POP
2 × N × 20 ns1
1 The SWAP instruction combines an LD and STR instruction with only one
fetch, giving a total of eight cycles + 40 ns.
This operation is reversible. The Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the REMAP MMR.
Caution must again be taken to execute the remap function
from outside the mirrored area. Any type of reset remaps the
Flash/EE memory at the bottom of the array.
2 N is the amount of data to load or store in the multiple load/store instruction
(1 < N ≤ 16).
Rev. F | Page 54 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Reset Operation
Table 46. RSTSTA Register
There are four kinds of reset: external, power-on, watchdog
expiration, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
Name
Address
Default Value
Access
RSTSTA
0xFFFF0230
0x01
R/W
Table 47. RSTSTA MMR Bit Designations
Bit
7:3
2
Description
Reserved.
Software reset. Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Table 44. REMAP Register
Name
Address
Default Value
0xXX1
Access
1
0
Watchdog timeout. Set automatically when a watchdog
timeout occurs. Cleared by setting the corresponding
bit in RSTCLR.
Power-on reset. Set automatically when a power-on
reset occurs. Cleared by setting the corresponding bit
in RSTCLR.
REMAP
1 Depends on the model.
0xFFFF0220
R/W
Table 45. REMAP MMR Bit Designations
Bit
Name
Description
4
Read-only bit. Indicates the size of the Flash/EE
memory available. If this bit is set, only 32 kB of
Flash/EE memory is available.
Read-only bit. Indicates the size of the SRAM
memory available. If this bit is set, only 4 kB of
SRAM is available.
Table 48. RSTCLR Register
Name
Address
Default Value
Access
RSTCLR
0xFFFF0234
0x00
W
3
Note that to clear the RSTSTA register, the user must write 0x07
to the RSTCLR register.
2:1
0
Reserved.
Remap Remap bit. Set by user to remap the SRAM to
Address 0x00000000. Cleared automatically
after reset to remap the Flash/EE memory to
Address 0x00000000.
Rev. F | Page 55 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
OTHER ANALOG PERIPHERALS
DAC
Table 51. DACxDAT Registers
Name
Address
Default Value
Access
R/W
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two,
three, or four 12-bit voltage output DACs on-chip, depending on
the model. Each DAC has a rail-to-rail voltage output buffer
capable of driving 5 kΩ/100 pF.
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
0xFFFF0604
0xFFFF060C
0xFFFF0614
0xFFFF061C
0x00000000
0x00000000
0x00000000
0x00000000
R/W
R/W
R/W
Each DAC has three selectable ranges: 0 V to VREF (internal
band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD.
DACREF is equivalent to an external reference for the DAC.
The signal range is 0 V to AVDD.
Table 52. DAC0DAT MMR Bit Designations
Bit
Description
31:28
27:16
15:0
Reserved.
12-bit data for DAC0.
Reserved.
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 50) and DAC0DAT
(see Table 52) are described in detail in this section.
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 63.
Table 49. DACxCON Registers
Name
Address
Default Value
0x00
Access
R/W
AV
DD
REF
REF
DAC0CON
DAC1CON
DAC2CON
DAC3CON
0xFFFF0600
0xFFFF0608
0xFFFF0610
0xFFFF0618
V
DAC
0x00
R/W
R
R
R
0x00
R/W
0x00
R/W
DAC0
Table 50. DAC0CON MMR Bit Designations
Bit Name
Value
Description
7:6
Reserved.
5
DACCLK
DACCLR
DAC update rate. Set by user to
update the DAC using Timer1.
Cleared by user to update the DAC
using HCLK (core clock).
DAC clear bit. Set by user to enable
normal DAC operation. Cleared by
user to reset data register of the DAC
to 0.
Reserved. This bit should be left at 0.
Reserved. This bit should be left at 0.
DAC range bits.
Power-down mode. The DAC output is
in three-state.
R
R
4
Figure 63. DAC Structure
As illustrated in Figure 63, the reference source for each DAC is
user-selectable in software. It can be AVDD, VREF, or DACREF. In
0-to-AVDD mode, the DAC output transfer function spans from
0 V to the voltage at the AVDD pin. In 0-to-DACREF mode, the
DAC output transfer function spans from 0 V to the voltage at the
DACREF pin. In 0-to-VREF mode, the DAC output transfer function
3
2
1:0
00
01
10
11
0 V to DACREF range.
0 V to VREF (2.5 V) range.
0 V to AVDD range.
spans from 0 V to the internal 2.5 V reference, VREF
.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AVDD and ground. Moreover, the DAC’s linearity specification
(when driving a 5 kꢀ resistive load to ground) is guaranteed
through the full transfer function, except Code 0 to Code 100,
and, in 0-to-AVDD mode only, Code 3995 to Code 4095.
Rev. F | Page 56 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Linearity degradation near ground and AVDD is caused by satu-
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 64.
The dotted line in Figure 64 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 64 represents a transfer function
in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF mode
(with VREF < AVDD or DACREF < AVDD), the lower nonlinearity is
similar. However, the upper portion of the transfer function
follows the ideal line right to the end (VREF in this case, not AVDD),
showing no signs of endpoint linearity errors.
Table 54. PSMCON MMR Bit Descriptions
Bit Name
Description
3
CMP
Comparator bit. This is a read-only bit that
directly reflects the state of the comparator.
Read 1 indicates that the IOVDD supply is above
its selected trip point or that the PSM is in
power-down mode. Read 0 indicates that the
IOVDD supply is below its selected trip point. This
bit should be set before leaving the interrupt
service routine.
2
1
TP
Trip point selection bit. 0 = 2.79 V, 1 = 3.07 V.
PSMEN Power supply monitor enable bit. Set to 1 to
enable the power supply monitor circuit. Cleared
to 0 to disable the power supply monitor circuit.
AV
DD
0
PSMI
Power supply monitor interrupt bit. This bit is set
high by the MicroConverter after CMP goes low,
indicating low I/O supply. The PSMI bit can be
used to interrupt the processor. After CMP
returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared after CMP goes high.
AV – 100mV
DD
COMPARATOR
100mV
The ADuC7019/20/21/22/24/25/26/27/28/29 integrate voltage
comparators. The positive input is multiplexed with ADC2, and
the negative input has two options: ADC3 and DAC0. The output
of the comparator can be configured to generate a system inter-
rupt, be routed directly to the programmable logic array, start
an ADC conversion, or be on an external pin, CMPOUT, as
shown in Figure 65.
0x00000000
0x0FFF0000
Figure 64. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in
Figure 64 get worse as a function of output loading. Most
of the ADuC7019/20/21/22/24/25/26/27/28/29 data sheet
specifications assume a 5 kΩ resistive load to ground at the
DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom (respectively)
of Figure 64 become larger. With larger current demands, this
can significantly limit output voltage swing.
IRQ
ADC2/CMP0
MUX
ADC3/CMP1
MUX
DAC0
POWER SUPPLY MONITOR
P0.0/CMP
OUT
The power supply monitor regulates the IOVDD supply on the
ADuC7019/20/21/22/24/25/26/27/28/29. It indicates when the
IOVDD supply pin drops below one of two supply trip points.
The monitor function is controlled via the PSMCON register.
If enabled in the IRQEN or FIQEN register, the monitor
interrupts the core using the PSMI bit in the PSMCON MMR.
This bit is immediately cleared after CMP goes high.
Figure 65. Comparator
Note that because the ADuC7022, ADuC7025, and ADu7027
parts do not support a DAC0 output, it is not possible to use
DAC0 as a comparator input on these parts.
Hysteresis
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brown-out
conditions. It also ensures that normal code execution does
not resume until a safe supply level is established.
Figure 66 shows how the input offset voltage and hysteresis
terms are defined.
CMP
OUT
V
V
H
H
Table 53. PSMCON Register
Name
Address
Default Value
Access
PSMCON
0xFFFF0440
0x0008
R/W
CMP0
V
OS
Figure 66. Comparator Hysteresis Transfer Function
Rev. F | Page 57 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Input offset voltage (VOS) is the difference between the center of
the hysteresis range and the ground level. This can either be
positive or negative. The hysteresis voltage (VH) is one-half the
width of the hysteresis range.
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
Each ADuC7019/20/21/22/24/25/26/27/28/29 integrates a
32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL
locks onto a multiple (1275) of the internal oscillator or an external
32.768 kHz crystal to provide a stable 41.78 MHz clock (UCLK) for
the system. To allow power saving, the core can operate at this
frequency, or at binary submultiples of it. The actual core oper-
ating frequency, UCLK/2CD, is refered to as HCLK. The default
core clock is the PLL clock divided by 8 (CD = 3) or 5.22 MHz.
The core clock frequency can also come from an external clock
on the ECLK pin as described in Figure 67. The core clock can
be outputted on ECLK when using an internal oscillator or
external crystal.
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 56.
Table 55. CMPCON Register
Name
Address
Default Value
Access
CMPCON
0xFFFF0444
0x0000
R/W
Table 56. CMPCON MMR Bit Descriptions
Bit
Name
Value Description
15:11
10
Reserved.
Note that when the ECLK pin is used to output the core clock,
the output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
CMPEN
Comparator enable bit. Set by user
to enable the comparator. Cleared
by user to disable the comparator.
9:8
7:6
5
CMPIN
CMPOC
CMPOL
Comparator negative input
select bits.
AVDD/2.
ADC3 input.
DAC0 output.
Reserved.
Comparator output configuration
bits.
XCLKO
XCLKI
WATCHDOG
TIMER
INT. 32kHz*
OSCILLATOR
CRYSTAL
OSCILLATOR
00
01
10
11
OCLK
WAKE-UP
TIMER
AT POWER-UP
32.768kHz
41.78MHz
00
01
10
11
Reserved.
Reserved.
PLL
P0.7/XCLK
MDCLK
Output on CMPOUT
IRQ.
.
UCLK
ANALOG
PERIPHERALS
2
I C
Comparator output logic state bit.
When low, the comparator output
is high if the positive input (CMP0)
is above the negative input (CMP1).
When high, the comparator output
is high if the positive input is below
the negative input.
CD
/2
CD
CORE
HCLK
*32.768kHz ±3%
P0.7/ECLK
Figure 67. Clocking System
4:3
CMPRES
Response time.
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
00
11
5 µs response time is typical for
large signals (2.5 V differential).
17 µs response time is typical for
small signals (0.65 mV differential).
External Crystal Selection
To switch to an external crystal, the user must do the following:
3 µs typical.
1. Enable the Timer2 interrupt and configure it for a timeout
period of >120 µs.
2. Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
3. Force the part into NAP mode by following the correct
write sequence to the POWCON register.
01/10 Reserved.
Comparator hysteresis bit. Set by
2
1
CMPHYST
CMPORI
user to have a hysteresis of about
7.5 mV. Cleared by user to have no
hysteresis.
Comparator output rising edge
interrupt. Set automatically when a
rising edge occurs on the moni-
tored voltage (CMP0). Cleared by
user by writing a 1 to this bit.
When the part is interrupted from NAP mode by the
Timer2 interrupt source, the clock source has switched to
the external clock.
0
CMPOFI
Comparator output falling edge
interrupt. Set automatically when a
falling edge occurs on the monitored
voltage (CMP0). Cleared by user.
Rev. F | Page 58 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Example source code
Example source code
t2val_old= T2VAL;
T2LD = 5;
t2val_old= T2VAL;
T2LD = 5;
TCON = 0x480;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
3)) //ensures timer value loaded
while ((T2VAL == t2val_old) || (T2VAL
> 3)) //ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
// Set Core into Nap mode
POWKEY1 = 0x01;
POWCON = 0x27;
// Set Core into Nap mode
POWKEY2 = 0xF4;
POWKEY2 = 0xF4;
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is only serviced when the lock is restored.
Power Control System
A choice of operating modes is available on the ADuC7019/20/
21/22/24/25/26/27/28/29. Table 57 describes what part is powered
on in the different modes and indicates the power-up time.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA register can determine if the
reset came from the watchdog timer.
Table 58 gives some typical values of the total current consump-
tion (analog + digital supply currents) in the different modes,
depending on the clock divider bits. The ADC is turned off. Note
that these values also include current consumption of the
regulator and other parts on the test board where these values
are measured.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1. The external clock can be up to 44 MHz, providing
the tolerance is 1%.
Table 57. Operating Modes1
Mode
Active
Pause
Nap
Sleep
Stop
Core
Peripherals
PLL
X
X
XTAL/T2/T3
IRQ0 to IRQ3
Start-Up/Power-On Time
130 ms at CD = 0
24 ns at CD = 0; 3 µs at CD = 7
24 ns at CD = 0; 3 µs at CD = 7
1.58 ms
X
X
X
X
X
X
X
X
X
X
X
X
X
1.7 ms
1 X indicates that the part is powered on.
Table 58. Typical Current Consumption at 25°C in Milliamperes
PC[2:0]
Mode
Active
Pause
Nap
CD = 0
33.1
22.7
3.8
CD = 1
21.2
13.3
3.8
CD = 2
13.8
8.5
CD = 3
10
6.1
CD = 4
8.1
4.9
CD = 5
7.2
4.3
CD = 6
6.7
4
CD = 7
6.45
3.85
3.8
000
001
010
3.8
3.8
3.8
3.8
3.8
011
100
Sleep
Stop
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Rev. F | Page 59 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
MMRs and Keys
Table 63. POWCON Register
Name
Address
Default Value
0x0003
Access
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs: PLLCON (see Table 61)
and POWCON (see Table 64). PLLCON controls the operating
mode of the clock system, whereas POWCON controls the core
clock frequency and the power-down mode.
POWCON
0xFFFF0408
R/W
Table 64. POWCON MMR Bit Designations
Bit Name Value
7
Description
Reserved.
To prevent accidental programming, a certain sequence (see
Table 65) must be followed to write to the PLLCON and
POWCON registers.
6:4 PC
000
Operating modes.
Active mode.
Pause mode.
Nap.
Sleep mode. IRQ0 to IRQ3 and Timer2
can wake up the part.
001
010
011
Table 59. PLLKEYx Registers
Name
Address
Default Value
0x0000
Access
W
PLLKEY1
PLLKEY2
0xFFFF0410
0xFFFF0418
100
Stop mode. IRQ0 to IRQ3 can wake up
the part.
0x0000
W
Others
Reserved.
Reserved.
Table 60. PLLCON Register
3
Name
Address
Default Value
Access
2:0 CD
000
001
010
011
100
101
110
111
CPU clock divider bits.
41.78 MHz.
20.89 MHz.
10.44 MHz.
5.22 MHz.
2.61 MHz.
1.31 MHz.
653 kHz.
326 kHz.
PLLCON
0xFFFF0414
0x21
R/W
Table 61. PLLCON MMR Bit Designations
Bit
7:6
5
Name
Value Description
Reserved.
32 kHz PLL input selection. Set by
user to select the internal 32 kHz
oscillator. Set by default. Cleared by
user to select the external 32 kHz crystal.
OSEL
4:2
1:0
Reserved.
Clocking modes.
Reserved.
PLL. Default configuration.
Reserved.
External clock on the P0.7 pin.
Table 65. PLLCON and POWCON Write Sequence
MDCLK
PLLCON
POWCON
00
01
10
11
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
POWKEY1 = 0x01
POWCON = user value
POWKEY2 = 0xF4
Table 62. POWKEYx Registers
Name
Address
Default Value
0x0000
Access
W
POWKEY1
POWKEY2
0xFFFF0404
0xFFFF040C
0x0000
W
Rev. F | Page 60 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
DIGITAL PERIPHERALS
an internal synchronization pulse, PWMSYNC, is produced at
the start of each PWM period. In double update mode, an
additional PWMSYNC pulse is produced at the midpoint of
each PWM period.
3-PHASE PWM
Each ADuC7019/20/21/22/24/25/26/27/28/29 provides a flexible
and programmable, 3-phase pulse-width modulation (PWM)
waveform generator. It can be programmed to generate the
required switching patterns to drive a 3-phase voltage source
inverter for ac induction motor control (ACIM). Note that only
active high patterns can be produced.
The PWM block can also provide an internal synchronization
pulse on the PWM
SYNC pin that is synchronized to the PWM
switching frequency. In single update mode, a pulse is produced
at the start of each PWM period. In double update mode, an
additional pulse is produced at the mid-point of each PWM period.
The width of the pulse is programmable through the PWMDAT2
register. The PWM block can also accept an external synchro-
nization pulse on the PWMSYNC pin. The selection of external
synchronization or internal synchronization is in the PWMCON
register. The SYNC input timing can be synchronized to the
internal peripheral clock, which is selected in the PWMCON
register. If the external synchronization pulse from the chip pin is
asynchronous to the internal peripheral clock (typical case), the
external PWMSYNC is considered asynchronous and should be
synchronized. The synchronization logic adds latency and jitter
from the external pulse to the actual PWM outputs. The size of
the pulse on the PWMSYNC pin must be greater than two core
clock periods.
The PWM generator produces three pairs of PWM signals on
the six PWM output pins (PWM0H, PWM0L, PWM1H, PWM1L,
PWM2H, and PWM2L). The six PWM output signals consist of
three high-side drive signals and three low-side drive signals.
The switching frequency and dead time of the generated PWM
patterns are programmable using the PWMDAT0 and PWMDAT1
MMRs. In addition, three duty-cycle control registers (PWMCH0,
PWMCH1, and PWMCH2) directly control the duty cycles of
the three pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMEN register. In addition,
three control bits of the PWMEN register permit crossover of
the two signals of a PWM pair. In crossover mode, the PWM
signal destined for the high-side switch is diverted to the comple-
mentary low-side output. The signal destined for the low-side
switch is diverted to the corresponding high-side output signal.
The PWM signals produced by the ADuC7019/20/21/22/24/25/
26/27/28/29 can be shut off via a dedicated asynchronous PWM
shutdown pin, PWMTRIP. When brought low, PWMTRIP instanta-
neously places all six PWM outputs in the off state (high). This
hardware shutdown mechanism is asynchronous so that the
associated PWM disable circuitry does not go through any
clocked logic. This ensures correct PWM shutdown even in
the event of a core clock loss.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the inverter power
devices. In general, there are two common isolation techniques:
optical isolation using optocouplers and transformer isolation
using pulse transformers. The PWM controller permits mixing
of the output PWM signals with a high frequency chopping signal
to permit easy interface to such pulse transformers. The features
of this gate-drive chopping mode can be controlled by the
PWMCFG register. An 8-bit value within the PWMCFG
register directly controls the chopping frequency. High
frequency chopping can be independently enabled for the high-
side and low-side outputs using separate control bits in the
PWMCFG register.
Status information about the PWM system is available to the user
in the PWMSTA register. In particular, the state of the PWMTRIP
pin is available, as well as a status bit that indicates whether oper-
ation is in the first half or the second half of the PWM period.
40-Pin Package Devices
On the 40-pin package devices, the PWM outputs are not
directly accessible, as described in the General-Purpose
Input/Output section. One channel can be brought out on a
GPIO (see Table 78) via the PLA as shown in the following
example:
The PWM generator can operate in one of two distinct modes:
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period so that the resulting PWM patterns are symmetrical
about the midpoint of the PWM period. In the double update
mode, a second updating of the PWM duty cycle values is
implemented at the midpoint of the PWM period.
PWMCON = 0x1;
// enables PWM o/p
PWMDAT0 = 0x055F;
// PWM switching freq
// Configure Port Pins
GP4CON = 0x300;
GP3CON = 0x1;
// P4.2 as PLA output
// P3.0 configured as
// output of PWM0
//(internally)
In double update mode, it is also possible to produce asymmetrical
PWM patterns that produce lower harmonic distortion in 3-phase
PWM inverters. This technique permits closed-loop controllers
to change the average voltage applied to the machine windings
at a faster rate. As a result, faster closed-loop bandwidths are
achieved. The operating mode of the PWM block is selected by
a control bit in the PWMCON register. In single update mode,
// PWM0 onto P4.2
PLAELM8 = 0x0035;
// P3.0 (PWM output)
// input of element 8
// PWM from element 8
PLAELM10 = 0x0059;
Rev. F | Page 61 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Therefore, for a 41.78 MHz fCORE, the fundamental time increment
is 24 ns. The value written to the PWMDAT0 register is effectively
the number of fCORE clock increments in one-half a PWM
period. The required PWMDAT0 value is a function of the
desired PWM switching frequency (fPWN) and is given by
DESCRIPTION OF THE PWM BLOCK
A functional block diagram of the PWM controller is shown in
Figure 68. The generation of the six output PWM signals on
Pin PWM0H to Pin PWM2L is controlled by the following four
important blocks:
PWMDAT0 = fCORE/(2 × fPWM
)
•
•
The 3-phase PWM timing unit. The core of the PWM
controller, this block generates three pairs of complemented
and dead-time-adjusted, center-based PWM signals. This
unit also generates the internal synchronization pulse,
PWMSYNC. It also controls whether the external PWMSYNC
pin is used.
The output control unit. This block can redirect the
outputs of the 3-phase timing unit for each channel to
either the high-side or low-side output. In addition, the
output control unit allows individual enabling/disabling
of each of the six PWM output signals.
The gate drive unit. This block can generate the high
frequency chopping and its subsequent mixing with the
PWM signals.
The PWM shutdown controller. This block controls the
PWM shutdown via the PWMTRIP pin and generates the
correct reset signal for the timing unit.
Therefore, the PWM switching period, tS, can be written as
tS = 2 × PWMDAT0 × tCORE
The largest value that can be written to the 16-bit PWMDAT0
MMR is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of
f
PWM(min) = 41.78 × 106/(2 × 65,535) = 318.75 Hz
Note that PWMDAT0 values of 0 and 1 are not defined and
should not be used.
PWM Switching Dead Time (PWMDAT1 MMR)
•
•
The second important parameter that must be set up in the initial
configuration of the PWM block is the switching dead time. This
is a short delay time introduced between turning off one PWM
signal (0H, for example) and turning on the complementary
signal (0L). This short time delay is introduced to permit the
power switch to be turned off (in this case, 0H) to completely
recover its blocking capability before the complementary switch is
turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
The PWM controller is driven by the ADuC7019/20/21/22/24/
25/26/27/28/29 core clock frequency and is capable of generating
two interrupts to the ARM core. One interrupt is generated on
the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.
The dead time is controlled by the 10-bit, read/write PWMDAT1
register. There is only one dead-time register that controls the dead
time inserted into all three pairs of PWM output signals. The dead
time, tD, is related to the value in the PWMDAT1 register by
3-Phase Timing Unit
PWM Switching Frequency (PWMDAT0 MMR)
The PWM switching frequency is controlled by the PWM
period register, PWMDAT0. The fundamental timing unit
of the PWM controller is
tD = PWMDAT1 × 2 × tCORE
Therefore, a PWMDAT1 value of 0x00A (= 10), introduces
a 426 ns delay between the turn-off on any PWM signal (0H,
for example) and the turn-on of its complementary signal (0L).
The amount of the dead time can, therefore, be programmed in
increments of 2tCORE (or 49 ns for a 41.78 MHz core clock).
tCORE = 1/fCORE
where fCORE is the core frequency of the MicroConverter.
CONFIGURATION
REGISTERS
DUTY CYCLE
REGISTERS
PWMCON
PWMDAT0
PWMDAT1
PWMDAT2
PWMCH0
PWMCH1
PWMCH2
PWMEN
PWMCFG
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
3-PHASE
PWM TIMING
UNIT
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
PWM
SHUTDOWN
CONTROLLER
CORE CLOCK
SYNC
PWM
PWM
SYNC
TO INTERRUPT
CONTROLLER
TRIP
Figure 68. Overview of the PWM Controller
Rev. F | Page 62 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
The PWMDAT1 register is a 10-bit register with a maximum
value of 0x3FF (= 1023), which corresponds to a maximum
programmed dead time of
The advantage of double update mode is that lower harmonic
voltages can be produced by the PWM process, and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service
routine, there is a larger computational burden on the ARM
core in double update mode.
t
D(max) = 1023 × 2 × tCORE = 1023 × 2 × 24 ×10–9 = 48.97 μs
for a core clock of 41.78 MHz.
The dead time can be programmed to be zero by writing 0 to
the PWMDAT1 register.
PWM Operating Mode (PWMCON and PWMSTA MMRs)
PWM Duty Cycles (PWMCH0, PWMCH1, and
PWMCH2 MMRs)
As discussed in the 3-Phase PWM section, the PWM controller
of the ADuC7019/20/21/22/24/25/26/27/28/29 can operate in
two distinct modes: single update mode and double update
mode. The operating mode of the PWM controller is
determined by the state of Bit 2 of the PWMCON register.
If this bit is cleared, the PWM operates in the single update
mode. Setting Bit 2 places the PWM in the double update
mode. The default operating mode is single update mode.
The duty cycles of the six PWM output signals on Pin PWM0H
to Pin PWM2L are controlled by the three 16-bit read/write duty
cycle registers, PWMCH0, PWMCH1, and PWMCH2. The
duty cycle registers are programmed in integer counts of the
fundamental time unit, tCORE. They define the desired on time of
the high-side PWM signal produced by the 3-phase timing unit
over half the PWM period. The switching signals produced by
the 3-phase timing unit are also adjusted to incorporate the
programmed dead time value in the PWMDAT1 register. The
3-phase timing unit produces active high signals so that a high
level corresponds to a command to turn on the associated
power device.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMDAT0 and PWMDAT1)
and the PWM duty cycle registers (PWMCH0, PWMCH1, and
PWMCH2) into the 3-phase timing unit. In addition, the
PWMEN register is latched into the output control unit on the
rising edge of the PWMSYNC pulse. In effect, this means that
the characteristics and resulting duty cycles of the PWM signals
can be updated only once per PWM period at the start of each
cycle. The result is symmetrical PWM patterns about the
midpoint of the switching period.
Figure 69 shows a typical pair of PWM outputs (in this case,
0H and 0L) from the timing unit in single update mode. All
illustrated time values indicate the integer value in the
associated register and can be converted to time by simply
multiplying by the fundamental time increment, tCORE. Note
that the switching patterns are perfectly symmetrical about the
midpoint of the switching period in this mode because the same
values of PWMCH0, PWMDAT0, and PWMDAT1 are used to
define the signals in both half cycles of the period.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The
rising edge of this new PWMSYNC pulse is again used to latch
new values of the PWM configuration registers, duty cycle
registers, and the PWMEN register. As a result, it is possible to
alter both the characteristics (switching frequency and dead
time) as well as the output duty cycles at the midpoint of each
PWM cycle. Consequently, it is also possible to produce PWM
switching patterns that are no longer symmetrical about the
midpoint of the period (asymmetrical PWM patterns). In
double update mode, it could be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 0 of the PWMSTA register, which is cleared during operation
in the first half of each PWM period (between the rising edge of
the original PWMSYNC pulse and the rising edge of the new
PWMSYNC pulse introduced in double update mode). Bit 0 of
the PWMSTA register is set during operation in the second half
of each PWM period. This status bit allows the user to make a
determination of the particular half cycle during implementation
of the PWMSYNC interrupt service routine, if required.
Figure 69 also demonstrates how the programmed duty cycles
are adjusted to incorporate the desired dead time into the
resulting pair of PWM signals. The dead time is incorporated
by moving the switching instants of both PWM signals (0H and
0L) away from the instant set by the PWMCH0 register.
–PWMDAT0 ÷ 2
0
+PWMDAT0 ÷ 2
0
–PWMDAT0 ÷ 2
PWMCH0
PWMCH0
0H
2 × PWMDAT1
2 × PWMDAT1
0L
PWMDAT2 + 1
PWMSYNC
PWMSTA (0)
PWMDAT0
PWMDAT0
Figure 69. Typical PWM Outputs of the 3-Phase Timing Unit
(Single Update Mode)
Rev. F | Page 63 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Both switching edges are moved by an equal amount
(PWMDAT1 × tCORE) to preserve the symmetrical output
patterns.
In general, the on times of the PWM signals in double update
mode can be defined as follows:
On the high side
Also shown are the PWMSYNC pulse and Bit 0 of the
PWMSTA register, which indicates whether operation is in the
first or second half cycle of the PWM period.
t0HH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE
t
0HL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 −
The resulting on times of the PWM signals over the full PWM
period (two half periods) produced by the timing unit can be
written as follows:
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
where Subscript 1 refers to the value of that register during the
first half cycle, and Subscript 2 refers to the value during the
second half cycle.
On the high side
t
t
0HH = PWMDAT0 + 2(PWMCH0 − PWMDAT1) × tCORE
0HL = PWMDAT0 − 2(PWMCH0 − PWMDAT1) × tCORE
The corresponding duty cycles (d) are
d0H = t0HH/tS = (PWMDAT01/2 + PWMDAT02/2 +
and the corresponding duty cycles (d)
0H = t0HH/tS = ½ + (PWMCH0 − PWMDAT1)/PWMDAT0
and on the low side
PWMCH01 + PWMCH02 − PWMDAT11 − PWMDAT12)/
(PWMDAT01 + PWMDAT02)
d
On the low side
t0LH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
t
t
0LH = PWMDAT0 − 2(PWMCH0 + PWMDAT1) × tCORE
0LL = PWMDAT0 + 2(PWMCH0 + PWMDAT1) × tCORE
t
0LL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 −
and the corresponding duty cycles (d)
OL = t0LH/tS = ½ − (PWMCH0 + PWMDAT1)/PWMDAT0
PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE
d
where Subscript 1 refers to the value of that register during the
first half cycle, and Subscript 2 refers to the value during the
second half cycle.
The minimum permissible t0H and t0L values are zero,
corresponding to a 0% duty cycle. In a similar fashion, the
maximum value is tS, corresponding to a 100% duty cycle.
The corresponding duty cycles (d) are
Figure 70 shows the output signals from the timing unit for
operation in double update mode. It illustrates a general case
where the switching frequency, dead time, and duty cycle are all
changed in the second half of the PWM period. The same value
for any or all of these quantities can be used in both halves of the
PWM cycle. However, there is no guarantee that symmetrical
PWM signals are produced by the timing unit in double update
mode. Figure 70 also shows that the dead time insertions into
the PWM signals are done in the same way as in single update
mode.
d0L = t0LH/tS = (PWMDAT01/2 + PWMDAT02/2 +
PWMCH01 + PWMCH02 + PWMDAT11 +
PWMDAT12)/(PWMDAT01 + PWMDAT02)
For the completely general case in double update mode
(see Figure 70), the switching period is given by
tS = (PWMDAT01 + PWMDAT02) × tCORE
Again, the values of t0H and t0L are constrained to lie between
zero and tS.
PWM signals similar to those illustrated in Figure 69 and
Figure 70 can be produced on the 1H, 1L, 2H, and 2L outputs by
programming the PWMCH1 and PWMCH2 registers in a manner
identical to that described for PWMCH0. The PWM controller
does not produce any PWM outputs until all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers have been written
to at least once. When these registers are written, internal
counting of the timers in the 3-phase timing unit is enabled.
–PWMDAT0 ÷ 2
2
+PWMDAT0 ÷ 2
2
–PWMDAT0 ÷ 2
1
0
+PWMDAT0 ÷ 2
1
0
PWMCH0
PWMCH0
2
1
0H
2 × PWMDAT1
2
2 × PWMDAT1
1
0L
Writing to the PWMDAT0 register starts the internal timing of
the main PWM timer. Provided that the PWMDAT0 register is
written to prior to the PWMCH0, PWMCH1, and PWMCH2
registers in the initialization, the first PWMSYNC pulse and
interrupt (if enabled) appear 1.5 × tCORE × PWMDAT0 seconds
after the initial write to the PWMDAT0 register in single update
mode. In double update mode, the first PWMSYNC pulse
appears after PWMDAT0 × tCORE seconds.
PWMSYNC
PWMDAT2 + 1
PWMDAT2 + 1
2
1
PWMSTA (0)
PWMDAT0
PWMDAT0
2
1
Figure 70. Typical PWM Outputs of the 3-Phase Timing Unit
(Double Update Mode)
Rev. F | Page 64 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
PWMCH0 = PWMCH0 =
PWMCH1 PWMCH1
Output Control Unit
The operation of the output control unit is controlled by the
9-bit read/write PWMEN register. This register controls two
distinct features of the output control unit that are directly
useful in the control of electronic counter measures (ECM) or
binary decimal counter measures (BDCM). The PWMEN
register contains three crossover bits, one for each pair of PWM
outputs. Setting Bit 8 of the PWMEN register enables the
crossover mode for the 0H/0L pair of PWM signals, setting
Bit 7 enables crossover on the 1H/1L pair of PWM signals, and
setting Bit 6 enables crossover on the 2H/2L pair of PWM
signals. If crossover mode is enabled for any pair of PWM
signals, the high-side PWM signal from the timing unit (0H, for
example) is diverted to the associated low-side output of the
output control unit so that the signal ultimately appears at the
PWM0L pin. Of course, the corresponding low-side output of
the timing unit is also diverted to the complementary high-side
output of the output control unit so that the signal appears at
the PWM0H pin. Following a reset, the three crossover bits are
cleared, and the crossover mode is disabled on all three pairs of
PWM signals. The PWMEN register also contains six bits (Bit 0
to Bit 5) that can be used to individually enable or disable each
of the six PWM outputs. If the associated bit of the PWMEN
register is set, the corresponding PWM output is disabled
regardless of the corresponding value of the duty cycle register.
This PWM output signal remains in the off state as long as the
corresponding enable/disable bit of the PWMEN register is set.
The implementation of this output enable function is imple-
mented after the crossover function.
0H
2 × PWMDAT1
2 × PWMDAT1
0L
1H
1L
2H
2L
PWMDAT0
PWMDAT0
Figure 71. Active Low PWM Signals Suitable for ECM Control,
PWMCH0 = PWMCH1, Crossover 1H/1L Pair and Disable
0L, 1H, 2H, and 2L Outputs in Single Update Mode.
In addition, the other four signals (0L, 1H, 2H, and 2L) have
been disabled by setting the appropriate enable/disable bits of
the PWMEN register. In Figure 71, the appropriate value for
the PWMEN register is 0x00A7. In normal ECM operation,
each inverter leg is disabled for certain periods of time to
change the PWMEN register based on the position of the rotor
shaft (motor commutation).
Gate Drive Unit
The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate-drive circuits for PWM
inverters. If a transformer-coupled, power device, gate-drive
amplifier is used, the active PWM signal must be chopped at a
high frequency. The 16-bit read/write PWMCFG register
programs this high frequency chopping mode. The chopped
active PWM signals can be required for the high-side drivers
only, the low-side drivers only, or both the high-side and low-
side switches. Therefore, independent control of this mode for
both high-side and low-side switches is included with two
separate control bits in the PWMCFG register.
Following a reset, all six enable bits of the PWMEN register are
cleared, and all PWM outputs are enabled by default. In a manner
identical to the duty cycle registers, the PWMEN is latched on
the rising edge of the PWMSYNC signal. As a result, changes to
this register become effective only at the start of each PWM cycle
in single update mode. In double update mode, the PWMEN
register can also be updated at the midpoint of the PWM cycle.
In the control of an ECM, only two inverter legs are switched at
any time, and often the high-side device in one leg must be
switched on at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycle values for
two PWM channels (for example, PWMCH0 = PWMCH1) and
setting Bit 7 of the PWMEN register to cross over the 1H/1L
pair of PWM signals, it is possible to turn on the high-side
switch of Phase A and the low-side switch of Phase B at the
same time. In the control of ECM, it is usual for the third
inverter leg (Phase C in this example) to be disabled for a
number of PWM cycles. This function is implemented by
disabling both the 2H and 2L PWM outputs by setting Bit 0
and Bit 1 of the PWMEN register.
Typical PWM output signals with high frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 72. Chopping of the high-side PWM outputs (0H, 1H,
and 2H) is enabled by setting Bit 8 of the PWMCFG register.
Chopping of the low-side PWM outputs (0L, 1L, and 2L) is
enabled by setting Bit 9 of the PWMCFG register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
placed in Bit 0 to Bit 7 of the PWMCFG register. The period of
this high frequency carrier is
t
CHOP = (4 × (GDCLK + 1)) × tCORE
The chopping frequency is, therefore, an integral subdivision of
the MicroConverter core frequency
f
CHOP = fCORE/(4 × (GDCLK + 1))
This situation is illustrated in Figure 71, where it can be seen
that both the 0H and 1L signals are identical because
PWMCH0 = PWMCH1 and the crossover bit for Phase B is set.
Rev. F | Page 65 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
The GDCLK value can range from 0 to 255, corresponding to a
programmable chopping frequency rate of 40.8 kHz to 10.44 MHz
for a 41.78 MHz core frequency. The gate drive features must be
programmed before operation of the PWM controller and are
typically not changed during normal operation of the PWM
controller. Following a reset, all bits of the PWMCFG register
are cleared so that high frequency chopping is disabled, by default.
PWM MMRs Interface
The PWM block is controlled via the MMRs described in
this section.
Table 66. PWMCON Register
Name
Address
Default Value
Access
PWMCON
0xFFFFFC00
0x0000
R/W
PWMCH0
PWMCH0
PWMCON is a control register that enables the PWM and
chooses the update rate.
0L
0H
Table 67. PWMCON MMR Bit Descriptions
2 × PWMDAT1
2 × PWMDAT1
Bit
7:5
4
Name
Description
Reserved.
External sync select. Set to use external
sync. Cleared to use internal sync.
External sync select. Set to select
external synchronous sync signal.
Cleared for asynchronous sync signal.
Double update mode. Set to 1 by user
to enable double update mode.
Cleared to 0 by the user to enable
single update mode.
PWM_SYNCSEL
PWM_EXTSYNC
4 × (GDCLK + 1) × tCORE
PWMDAT0
PWMDAT0
3
2
Figure 72. Typical PWM Signals with High Frequency Gate Chopping
Enabled on Both High-Side and Low-Side Switches
PWMDBL
PWM Shutdown
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
low level on the PWMTRIP pin provides an instantaneous,
asynchronous (independent of the MicroConverter core clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the off state, that is, in low state. In addition, the
PWMSYNC pulse is disabled. The PWMTRIP pin has an internal
pull-down resistor to disable the PWM if the pin becomes
disconnected. The state of the PWMTRIP pin can be read from
Bit 3 of the PWMSTA register.
1
0
PWM_SYNC_EN
PWMEN
PWM synchronization enable. Set by
user to enable synchronization. Cleared
by user to disable synchronization.
PWM enable bit. Set to 1 by user to
enable the PWM. Cleared to 0 by user
to disable the PWM. Also cleared
automatically with PWMTRIP
(PWMSTA MMR).
Table 68. PWMSTA Register
If a PWM shutdown command occurs, a PWMTRIP interrupt is
generated, and internal timing of the 3-phase timing unit of the
PWM controller is stopped. Following a PWM shutdown, the
PWM can be reenabled (in a PWMTRIP interrupt service
routine, for example) only by writing to all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers. Provided that
the external fault is cleared and the PWMTRIP is returned to a
high level, the internal timing of the 3-phase timing unit
resumes, and new duty-cycle values are latched on the next
PWMSYNC boundary.
Name
Address
Default Value
Access
PWMSTA
0xFFFFFC04
0x0000
R/W
PWMSTA reflects the status of the PWM.
Table 69. PWMSTA MMR Bit Descriptions
Bit
15:10
9
Name
Description
Reserved.
PWMSYNCINT PWM sync interrupt bit. Writing a 1 to
this bit clears this interrupt.
PWMTRIPINT PWM trip interrupt bit. Writing a 1 to
this bit clears this interrupt.
8
Note that the PWMTRIP interrupt is available in IRQ only,
and the PWMSYNC interrupt is available in FIQ only. Both
interrupts share the same bit in the interrupt controller.
Therefore, only one of the interrupts can be used at a time.
See the Interrupt System section for further details.
3
2:1
0
PWMTRIP
Raw signal from the PWMTRIP pin.
Reserved.
PWM phase bit. Set to 1 by the Micro-
Converter when the timer is counting
down (first half). Cleared to 0 by the
MicroConverter when the timer is
counting up (second half).
PWMPHASE
Rev. F | Page 66 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 70. PWMCFG Register
Table 74. PWMDAT0 Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
PWMCFG
0xFFFFFC10
0x0000
R/W
PWMDAT0
0xFFFFFC08
0x0000
R/W
PWMCFG is a gate chopping register.
PWMDAT0 is an unsigned 16-bit register for switching period.
Table 71. PWMCFG MMR Bit Descriptions
Table 75. PWMDAT1 Register
Bit
15:10
9
8
7:0
Name
Description
Name
Address
Default Value
Access
Reserved.
PWMDAT1
0xFFFFFC0C
0x0000
R/W
CHOPLO
CHOPHI
GDCLK
Low-side gate chopping enable bit.
High-side gate chopping enable bit.
PWM gate chopping period (unsigned).
PWMDAT1 is an unsigned 10-bit register for dead time.
Table 76. PWMCHx Registers
Name
Address
Default Value
0x0000
Access
R/W
Table 72. PWMEN Register
PWMCH0
PWMCH1
PWMCH2
0xFFFFFC14
0xFFFFFC18
0xFFFFFC1C
Name
Address
Default Value
Access
0x0000
R/W
PWMEN
0xFFFFFC20
0x0000
R/W
0x0000
R/W
PWMEN allows enabling of channel outputs and crossover. See
its bit definitions in Table 73.
PWMCH0, PWMCH1, and PWMCH2 are channel duty cycles
for the three phases.
Table 73. PWMEN MMR Bit Descriptions
Table 77. PWMDAT2 Register
Bit Name
Description
Name
Address
Default Value
Access
8
7
6
0H0L_XOVR Channel 0 output crossover enable bit.
Set to 1 by user to enable Channel 0 output
crossover. Cleared to 0 by user to disable
Channel 0 output crossover.
1H1L_XOVR Channel 1 output crossover enable bit.
Set to 1 by user to enable Channel 1 output
crossover. Cleared to 0 by user to disable
Channel 1 output crossover.
2H2L_XOVR Channel 2 output crossover enable bit.
Set to 1 by user to enable Channel 2 output
crossover. Cleared to 0 by user to disable
Channel 2 output crossover.
PWMDAT2
0xFFFFFC24
0x0000
R/W
PWMDAT2 is an unsigned 10-bit register for PWM sync
pulse width.
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7019/20/21/22/24/25/26/27/28/29 provide 40 general-
purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V
tolerant, meaning the GPIOs support an input voltage of 5 V.
In general, many of the GPIO pins have multiple functions (see
Table 78 for the pin function definitions). By default, the GPIO
pins are configured in GPIO mode.
5
4
3
2
1
0
0L_EN
0H_EN
1L_EN
1H_EN
2L_EN
2H_EN
0L output enable bit. Set to 1 by user to
disable the 0L output of the PWM. Cleared to 0
by user to enable the 0L output of the PWM.
0H output enable bit. Set to 1 by user to
disable the 0H output of the PWM. Cleared to
0 by user to enable the 0H output of the PWM.
1L output enable bit. Set to 1 by user to
disable the 1L output of the PWM. Cleared to 0
by user to enable the 1L output of the PWM.
1H Output Enable Bit. Set to 1 by user to
disable the 1H output of the PWM. Cleared to
0 by user to enable the 1H output of the PWM.
2L output enable bit. Set to 1 by user to
disable the 2L output of the PWM. Cleared to 0
by user to enable the 2L output of the PWM.
2H output enable bit. Set to 1 by user to
disable the 2H output of the PWM. Cleared to
0 by user to enable the 2H output of the PWM.
All GPIO pins have an internal pull-up resistor (of about
100 kΩ), and their drive capability is 1.6 mA. Note that a
maximum of 20 GPIOs can drive 1.6 mA at the same time.
Using the GPxPAR registers, it is possible to enable/disable
the pull-up resistors for the following ports: P0.0, P0.4, P0.5,
P0.6, P0.7, and the eight GPIOs of P1.
The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x).
Each port is controlled by four or five MMRs.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. Otherwise, P0.6 goes low for the reset period. For
example, if MRST is required for power-down, it can be
reconfigured in GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7019/20/21/22/24/25/26/27/28/29 part enters a
power-saving mode, the GPIO pins retain their state.
Rev. F | Page 67 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
GPxCON are the Port x control registers, which select the
function of each pin of Port x as described in Table 80.
Table 78. GPIO Pin Function Descriptions
Configuration
Port Pin
00
01
10
11
Table 80. GPxCON MMR Bit Descriptions
0
1
2
P0.0 GPIO
P0.1 GPIO
P0.2 GPIO
P0.3 GPIO
P0.4 GPIO/IRQ0 PWMTRIP
P0.5 GPIO/IRQ1 ADCBUSY
P0.6 GPIO/T1
P0.7 GPIO
P1.0 GPIO/T1
P1.1 GPIO
P1.2 GPIO
P1.3 GPIO
CMP
MS0
BLE
BHE
A16
MS1
MS2
PLAI[7]
Bit
Description
PWM2H
PWM2L
TRST
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
Reserved.
Select function of the Px.7 pin.
Reserved.
Select function of the Px.6 pin.
Reserved.
Select function of the Px.5 pin.
Reserved.
Select function of the Px.4 pin.
Reserved.
Select function of the Px.3 pin.
Reserved.
Select function of the Px.2 pin.
Reserved.
ADCBUSY
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
MRST
ECLK/XCLK1
SIN
SOUT
RTS
SIN
SCL0
SDA0
SCL1
SDA1
SCLK
MISO
MOSI
CS
CTS
P1.4 GPIO/IRQ2 RI
P1.5 GPIO/IRQ3 DCD
P1.6 GPIO
P1.7 GPIO
7:6
DSR
DTR
5:4
3:2
Select function of the Px.1 pin.
Reserved.
2
1:0
Select function of the Px.0 pin.
P2.0 GPIO
P2.1 GPIO
P2.2 GPIO
P2.3 GPIO
P2.4 GPIO
P2.5 GPIO
P2.6 GPIO
P2.7 GPIO
P3.0 GPIO
P3.1 GPIO
P3.2 GPIO
P3.3 GPIO
P3.4 GPIO
P3.5 GPIO
P3.6 GPIO
P3.7 GPIO
P4.0 GPIO
P4.1 GPIO
P4.2 GPIO
P4.3 GPIO
P4.4 GPIO
P4.5 GPIO
P4.6 GPIO
P4.7 GPIO
CONVSTART
PWM0H
PWM0L
SOUT
WS
PLAO[5]
PLAO[6]
PLAO[7]
Table 81. GPxPAR Registers
RS
Name
Address
Default Value
0x20000000
0x00000000
Access
R/W
AE
GP0PAR
GP1PAR
0xFFFFF42C
0xFFFFF43C
PWM0H
PWM0L
PWM1H
PWM1L
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
PWMTRIP
PWMSYNC
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
R/W
GPxPAR program the parameters for Port 0 and Port 1. Note that
the GPxDAT MMR must always be written after changing the
GPxPAR MMR.
3
PLAI[8]
PLAI[9]
Table 82. GPxPAR MMR Bit Descriptions
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
PLAO[10]
PLAO[11]
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
Bit
Description
31
Reserved.
30:29
28
27
Drive strength Px.7.
Pull-Up Disable Px.7.
Reserved.
26:25
24
23
Drive strength Px.6.
Pull-Up Disable Px.6.
Reserved.
4
22:21
20
19
Drive strength Px.5.
Pull-Up Disable Px.5.
Reserved.
18:17
16
15
Drive strength Px.4.
Pull-Up Disable Px.4.
Reserved.
14:13
12
11
Drive strength Px.3.
Pull-Up Disable Px.3.
Reserved.
1 When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To
configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.
2
CONVSTART signal is active in all modes of P2.0.
The
10:9
8
7
Drive strength Px.2.
Pull-Up Disable Px.2.
Reserved.
Table 79. GPxCON Registers
Name
Address
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
R/W
6:5
4
3
Drive strength Px.1.
Pull-Up Disable Px.1.
Reserved.
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
0xFFFFF400
0xFFFFF404
0xFFFFF408
0xFFFFF40C
0xFFFFF410
2:1
0
Drive strength Px.0.
Pull-Up Disable Px.0.
R/W
Rev. F | Page 68 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 83. GPIO Drive Strength Control Bits Descriptions
Table 84. GPxPAR Control Bits Access Descriptions
Control Bits Value
Description
Bit
GP0PAR
Reserved
R/W
R/W
Reserved
R/W
R/W
Reserved
R/W
GP1PAR
Reserved
R/W
R/W
Reserved
R/W
00
01
1x
3.6
Medium drive strength.
Low drive strength.
High drive strength.
31
30 to 29
28
27
26 to 25
24
23
22 to 21
20
19
18 to 17
16
15
14 to 13
12
11
3.4
3.2
3.0
2.8
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
2.6
2.4
2.2
2.0
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
10 to 9
8
7
6 to 5
4
3
Figure 73. Programmable Strength for High Level
(Typical Values)
0.5
0.4
0.3
Reserved
R (b00)
R/W
2 to 1
0
0.2
0.1
0
–0.1
–0.2
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
–0.3
–0.4
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
Figure 74. Programmable Strength for Low Level
(Typical Values)
The drive strength bits can be written to one time only after
reset. More writing to related bits has no effect on changing
drive strength. The GPIO drive strength and pull-up disable is
not always adjustable for the GPIO port. Some control bits
cannot be changed (see Table 84).
Rev. F | Page 69 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 90. GPxCLR MMR Bit Descriptions
Table 85. GPxDAT Registers
Bit
Description
Name
Address
Default Value1
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
R/W
31:24
23:16
Reserved.
GP0DAT
GP1DAT
GP2DAT
GP3DAT
GP4DAT
1 X = 0, 1, 2, or 3.
0xFFFFF420
0xFFFFF430
0xFFFFF440
0xFFFFF450
0xFFFFF460
Data Port x clear bit. Set to 1 by user to clear bit on
Port x; also clears the corresponding bit in the GPxDAT
MMR. Cleared to 0 by user; does not affect the data out.
R/W
R/W
R/W
15:0
Reserved.
R/W
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I2Cs) and the programmable logic array
(PLA) to a set of 10 GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 91.
GPxDAT are Port x configuration and data registers. They
configure the direction of the GPIO pins of Port x, set the
output value for the pins configured as output, and store the
input value of the pins configured as input.
Table 91. SPM Configuration
Table 86. GPxDAT MMR Bit Descriptions
GPIO
(00)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
P2.0
UART
(01)
UART/I2C/SPI PLA
Bit
Description
SPMMUX
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
(10)
(11)
31:24
Direction of the data. Set to 1 by user to configure
the GPIO pin as an output. Cleared to 0 by user to
configure the GPIO pin as an input.
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SCLK
MISO
MOSI
CS
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[4]
PLAO[5]
23:16
15:8
7:0
Port x data output.
Reflect the state of Port x pins at reset (read only).
Port x data input (read only).
Table 87. GPxSET Registers
Name
Address
Default Value1
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
GP0SET
GP1SET
GP2SET
GP3SET
GP4SET
1 X = 0, 1, 2, or 3.
0xFFFFF424
0xFFFFF434
0xFFFFF444
0xFFFFF454
0xFFFFF464
W
W
W
W
W
ECLK/XCLK
CONV
SIN
SOUT
Table 91 also details the mode for each of the SPMMUX pins.
This configuration must be done via the GP0CON, GP1CON,
and GP2CON MMRs. By default, these 10 pins are configured
as GPIOs.
GPxSET are data set Port x registers.
UART SERIAL INTERFACE
Table 88. GPxSET MMR Bit Descriptions
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. It is fully compatible with the 16,450 serial
port standard. The UART performs serial-to-parallel conversions
on data characters received from a peripheral device or modem,
and parallel-to-serial conversions on data characters received
from the CPU. The UART includes a fractional divider for baud
rate generation and has a network addressable mode. The UART
function is made available on the 10 pins of the ADuC7019/20/
21/22/24/25/26/27/28/29 (see Table 92).
Bit
Description
31:24
23:16
Reserved.
Data Port x set bit. Set to 1 by user to set bit on Port x;
also sets the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
15:0
Reserved.
Table 89. GPxCLR Registers
Name
Address
Default Value1
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
GP0CLR
GP1CLR
GP2CLR
GP3CLR
GP4CLR
1 X = 0, 1, 2, or 3.
0xFFFFF428
0xFFFFF438
0xFFFFF448
0xFFFFF458
0xFFFFF468
W
W
W
W
W
Table 92. UART Signal Description
Pin
Signal
Description
SPM0 (Mode 1)
SPM1 (Mode 1)
SPM2 (Mode 1)
SPM3 (Mode 1)
SPM4 (Mode 1)
SPM5 (Mode 1)
SPM6 (Mode 1)
SPM7 (Mode 1)
SPM8 (Mode 2)
SPM9 (Mode 2)
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
SIN
Serial receive data.
Serial transmit data.
Request to send.
Clear to send.
Ring indicator.
Data carrier detect.
Data set ready.
Data terminal ready.
Serial receive data.
Serial transmit data.
GPxCLR are data clear Port x registers.
SOUT
Rev. F | Page 70 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
41.78MHz
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.
BaudRate =
128
23 ×16×8×2×
2048
Baud Rate Generation
where:
Baud Rate = 19,200 bps
There are two ways of generating the UART baud rate, normal
450 UART baud rate generation and the fractional divider.
Error = 0%, compared to 6.25% with the normal baud rate
generator.
Normal 450 UART Baud Rate Generation
UART Register Definitions
The baud rate is a divided version of the core clock using the values
in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
The UART interface consists of 12 registers: COMTX, COMRX,
COMDIV0, COMIEN0, COMDIV1, COMIID0, COMCON0,
COMCON1, COMSTA0, COMSTA1, COMSCR, and
COMDIV2.
41.78MHz
Baud Rate =
2CD - 16 × 2 × DL
Table 93 gives some common baud rate values.
Table 94. COMTX Register
Table 93. Baud Rate Using the Normal Baud Rate Generator
Name
Address
Default Value
Access
Baud Rate
CD
DL
Actual Baud Rate
% Error
COMTX
0xFFFF0700
0x00
R/W
9600
0
0
0
3
3
3
0x88
0x44
0x0B
0x11
0x08
0x01
9600
19,200
118,691
9600
20,400
0
0
3
0
COMTX is an 8-bit transmit register.
19,200
115,200
9600
19,200
115,200
Table 95. COMRX Register
Name
Address
Default Value
Access
6.25
41.67
COMRX
0xFFFF0700
0x00
R
163,200
COMRX is an 8-bit receive register.
Fractional Divider
Table 96. COMDIV0 Register
The fractional divider, combined with the normal baud rate
generator, produces a wider range of more accurate baud rates.
Name
Address
Default Value
Access
COMDIV0
0xFFFF0700
0x00
R/W
FBEN
CORE
CLOCK
/2
COMDIV0 is a low byte divisor latch. COMTX, COMRX,
and COMDIV0 share the same address location. COMTX
and COMRX can be accessed when Bit 7 in the COMCON0
register is cleared. COMDIV0 can be accessed when Bit 7
of COMCON0 is set.
/16DL
UART
/(M+N/2048)
Figure 75. Baud Rate Generation Options
Calculation of the baud rate using fractional divider is as follows:
Table 97. COMIEN0 Register
41.78 MHz
Baud Rate =
Name
Address
Default Value
Access
N
2048
2
CD ×16×DL×2× M +
COMIEN0
0xFFFF0704
0x00
R/W
COMIEN0 is the interrupt enable register.
41.78MHz
N
M+
=
2048 Baud Rate × 2CD × 16 ×DL×2
Table 98. COMIEN0 MMR Bit Descriptions
Bit
7:4
3
Name
Description
For example, generation of 19,200 baud with CD bits = 3
(Table 93 gives DL = 0x08) is
N/A
EDSSI
Reserved.
Modem status interrupt enable bit. Set by
user to enable generation of an interrupt if
any of COMSTA1[3:1] is set. Cleared by user.
Rx status interrupt enable bit. Set by user to
enable generation of an interrupt if any of
COMSTA0[4:1] is set. Cleared by user.
Enable transmit buffer empty interrupt. Set
by user to enable interrupt when buffer is
empty during a transmission. Cleared by user.
Enable receive buffer full interrupt. Set by
user to enable interrupt when buffer is full
during a reception. Cleared by user.
41.78 MHz
N
M +
M +
=
2048 19200 ×23 ×16×8×2
2
1
0
ELSI
N
=1.06
2048
ETBEI
ERBFI
where:
M = 1
N = 0.06 × 2048 = 128
Rev. F | Page 71 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 99. COMDIV1 Register
Table 104. COMCON1 Register
Name
Address
Default Value
Access
Name
Address
Default Value
0x00
Access
COMDIV1
0xFFFF0704
0x00
R/W
COMCON1
0xFFFF0710
R/W
COMDIV1 is a divisor latch (high byte) register.
COMCON1 is the modem control register.
Table 100. COMIID0 Register
Table 105. COMCON1 MMR Bit Descriptions
Name
Address
Default Value
Access
Bit Name
Description
COMIID0
0xFFFF0708
0x01
R
7:5
Reserved.
4
LOOPBACK Loopback. Set by user to enable loopback
mode. In loopback mode, SOUT (see Table 78)
is forced high. The modem signals are also
directly connected to the status inputs (RTS
to CTS and DTR to DSR). Cleared by user to
be in normal mode.
COMIID0 is the interrupt identification register.
Table 101. COMIID0 MMR Bit Descriptions
Bit 2:1
Status Bits NINT Priority
Bit 0
Clearing
Operation
Definition
00
11
1
0
N/A
No interrupt N/A
3
2
PEN
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no
parity transmission or checking.
1 (Highest) Receive line
status
Read
COMSTA0
interrupt
STOP
Stop bit. Set by user to transmit 1.5 stop bits
if the word length is five bits, or 2 stop bits if
the word length is six bits, seven bits, or
eight bits. The receiver checks the first stop
bit only, regardless of the number of stop bits
selected. Cleared by user to generate 1 stop
bit in the transmitted data.
10
01
0
0
2
3
Receive
buffer full
interrupt
Transmit
buffer
Read
COMRX
Write data to
COMTX or
read
empty
interrupt
4 (Lowest) Modem
status
COMIID0
Read
COMSTA1
1
0
RTS
DTR
Request to send. Set by user to force the RTS
output to 0. Cleared by user to force the RTS
output to 1.
Data terminal ready. Set by user to force the
DTR output to 0. Cleared by user to force the
DTR output to 1.
00
0
interrupt
Table 102. COMCON0 Register
Name
Address
Default Value
Access
Table 106. COMSTA0 Register
COMCON0
0xFFFF070C
0x00
R/W
Name
Address
Default Value
Access
COMCON0 is the line control register.
COMSTA0
0xFFFF0714
0x60
R
Table 103. COMCON0 MMR Bit Descriptions
COMSTA0 is the line status register.
Bit
Name
Description
Table 107. COMSTA0 MMR Bit Descriptions
Bit Name Description
7
DLAB
Divisor latch access. Set by user to enable access
to the COMDIV0 and COMDIV1 registers. Cleared
by user to disable access to COMDIV0 and
COMDIV1 and enable access to COMRX and
COMTX.
Set break. Set by user to force SOUT to 0. Cleared
to operate in normal mode.
Stick parity. Set by user to force parity to defined
values: 1 if EPS = 1 and PEN = 1,
0 if EPS = 0 and PEN = 1.
Even parity select bit. Set for even parity. Cleared
for odd parity.
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no parity
transmission or checking.
Stop bit. Set by user to transmit 1.5 stop bits if the
word length is five bits or 2 stop bits if the word
length is six bits, seven bits, or eight bits. The
receiver checks the first stop bit only, regardless
of the number of stop bits selected. Cleared by user
to generate 1 stop bit in the transmitted data.
7
6
Reserved.
TEMT
THRE
COMTX and shift register empty status bit. Set
automatically if COMTX and shift register are
empty. Cleared automatically when writing to
COMTX.
COMTX empty. Set automatically if COMTX is
empty. Cleared automatically when writing to
COMTX.
6
5
BRK
SP
5
4
3
EPS
4
3
2
1
0
BI
Break error. Set when SIN is held low for more than
the maximum word length. Cleared automatically.
Framing error. Set when an invalid stop bit occurs.
Cleared automatically.
Parity error. Set when a parity error occurs.
Cleared automatically.
Overrun error. Set automatically if data is over-
written before being read. Cleared automatically.
PEN
FE
PE
OE
DR
2
STOP
WLS
Data ready. Set automatically when COMRX is full.
Cleared by reading COMRX.
1:0
Word length select:
00 = five bits, 01 = six bits, 10 = seven bits,
11 = eight bits.
Rev. F | Page 72 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 108. COMSTA1 Register
Network Addressable UART Register Definitions
Name
Address
Default Value
Access
Four additional registers, COMIEN0, COMIEN1, COMIID1, and
COMADR are used in network addressable UART mode only.
COMSTA1
0xFFFF0718
0x00
R
COMSTA1 is a modem status register.
In network address mode, the least significant bit of the COMIEN1
register is the transmitted network address control bit. If set to
1, the device is transmitting an address. If cleared to 0, the
device is transmitting data. For example, the following master-
based code transmits the slave’s address followed by the data:
Table 109. COMSTA1 MMR Bit Descriptions
Bit Name Description
7
6
5
4
3
DCD
RI
DSR
CTS
Data carrier detect.
Ring indicator.
Data set ready.
Clear to send.
COMIEN1 = 0xE7;
//Setting ENAM,
E9BT, E9BR, ETD, NABP
COMTX = 0xA0; // Slave address is 0xA0
DDCD Delta DCD. Set automatically if DCD changed
state since last COMSTA1 read. Cleared automati-
cally by reading COMSTA1.
while(!(0x020==(COMSTA0 & 0x020))){} //
wait for adr tx to finish.
2
1
0
TERI
Trailing edge RI. Set if RI changed from 0 to 1
since COMSTA1 was last read. Cleared
automatically by reading COMSTA1.
COMIEN1 = 0xE6;
to indicate Data is coming
// Clear NAB bit
COMTX = 0x55; // Tx data to slave: 0x55
DDSR Delta DSR. Set automatically if DSR changed state
since COMSTA1 was last read. Cleared
Table 113. COMIEN1 Register
automatically by reading COMSTA1.
Name
Address
Default Value
Access
DCTS
Delta CTS. Set automatically if CTS changed state
since COMSTA1 was last read. Cleared
automatically by reading COMSTA1.
COMIEN1
0xFFFF0720
0x04
R/W
COMIEN1 is an 8-bit network enable register.
Table 110. COMSCR Register
Table 114. COMIEN1 MMR Bit Descriptions
Name
Address
Default Value
Access
Bit Name Description
COMSCR
0xFFFF071C
0x00
R/W
7
6
5
ENAM Network address mode enable bit. Set by user to
enable network address mode. Cleared by user to
disable network address mode.
COMSCR is an 8-bit scratch register used for temporary
storage. It is also used in network addressable UART mode.
E9BT
9-bit transmit enable bit. Set by user to enable
9-bit transmit. ENAM must be set. Cleared by user
to disable 9-bit transmit.
Table 111. COMDIV2 Register
Name
Address
Default Value
Access
E9BR
9-bit receive enable bit. Set by user to enable
9-bit receive. ENAM must be set. Cleared by user
to disable 9-bit receive.
COMDIV2
0xFFFF072C
0x0000
R/W
COMDIV2 is a 16-bit fractional baud divide register.
4
3
ENI
Network interrupt enable bit.
E9BD
Word length. Set for 9-bit data. E9BT has to be
cleared. Cleared for 8-bit data.
Table 112. COMDIV2 MMR Bit Descriptions
Bit
Name
Description
2
ETD
Transmitter pin driver enable bit. Set by user to
enable SOUT pin as an output in slave mode or
multimaster mode. Cleared by user; SOUT is
three-state.
15
FBEN
Fractional baud rate generator enable bit.
Set by user to enable the fractional baud
rate generator. Cleared by user to generate
baud rate using the standard 450 UART
baud rate generator.
1
0
NABP Network address bit. Interrupt polarity bit.
NAB
Network address bit (if NABP = 1). Set by user to
transmit the slave address. Cleared by user to
transmit data.
14:13
12:11
Reserved.
FBM[1:0]
M if FBM = 0, M = 4 (see the Fractional
Divider section).
10:0
FBN[10:0] N (see the Fractional Divider section).
Table 115. COMIID1 Register
Name
Address
Default Value
Access
Network Addressable UART Mode
COMIID1
0xFFFF0724
0x01
R
This mode connects the MicroConverter to a 256-node serial
network, either as a hardware single master or via software in a
multimaster network. Bit 7 (ENAM) of the COMIEN1 register
must be set to enable UART in network addressable mode (see
Table 114). Note that there is no parity check in this mode.
COMIID1 is an 8-bit network interrupt register. Bit 7 to Bit 4
are reserved (see Table 116).
Rev. F | Page 73 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
MISO (Master In, Slave Out) Pin
Table 116. COMIID1 MMR Bit Descriptions
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
Bit 3:1
Status
Bits
Bit 0
Clearing
Operation
NINT Priority Definition
000
110
1
0
No interrupt
2
3
Matching network Read COMRX
address
MOSI (Master Out, Slave In) Pin
101
0
Address
transmitted,
buffer empty
Write data to
COMTX or
read COMIID0
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
011
010
001
0
0
0
1
2
3
Receive line status Read
interrupt
COMSTA0
Receive buffer full Read COMRX
interrupt
SCLK (Serial Clock I/O) Pin
Transmit buffer
empty interrupt
Write data to
COMTX or
read COMIID0
Read
COMSTA1
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI SCLK
period. Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
000
0
4
Modem status
interrupt
Note that to receive a network address interrupt, the slave must
ensure that Bit 0 of COMIEN0 (enable receive buffer full interrupt)
is set to 1.
In master mode, the polarity and phase of the clock are
controlled by the SPICON register, and the bit rate is defined
in the SPIDIV register as follows:
Table 117. COMADR Register
Name
Address
Default Value
Access
fUCLK
2×(1+ SPIDIV)
fSERIAL CLOCK
=
COMADR
0xFFFF0728
0xAA
R/W
COMADR is an 8-bit, read/write network address register that
holds the address checked for by the network addressable
UART. Upon receiving this address, the device interrupts the
processor and/or sets the appropriate status bit in COMIID1.
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 118.
Table 118. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
0
1
2
3
4
5
SERIAL PERIPHERAL INTERFACE
SPIDIV in Hex 0x05
0x0B
0x17
0x2F
0x5F
0xBF
The ADuC7019/20/21/22/24/25/26/27/28/29 integrate a complete
hardware serial peripheral interface (SPI) on-chip. SPI is an
industry standard, synchronous serial interface that allows eight
bits of data to be synchronously transmitted and simultaneously
received, that is, full duplex up to a maximum bit rate of 3.48 Mb,
as shown in Table 118. The SPI interface is not operational with
core clock divider (CD) bits. POWCON[2:0] = 6 or 7 in master
mode.
SPI dpeed
in MHz
3.482 1.741 0.870 0.435 0.218 0.109
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10.4 Mb at CD = 0.
The formula to determine the maximum speed is as follows:
fHCLK
4
fSERIAL CLOCK
=
The SPI port can be configured for master or slave operation.
and typically consists of four pins: MISO (P1.5), MOSI (P1.6),
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
CS
SCLK (P1.4), and
(P1.7).
On the transmit side, the SPITX register (and a TX shift register
outside it) loads data onto the transmit pin (in slave mode,
MISO; in master mode, MOSI). The transmit status bit, Bit 0,
in SPISTA indicates whether there is valid data in the SPITX
register.
Chip Select ( Input) Pin
CS
CS
In SPI slave mode, a transfer is initiated by the assertion of
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
,
Similarly, the receive data path consists of the SPIRX register
(and an RX shift register). SPISTA, Bit 3 indicates whether there
is valid data in the SPIRX register. If valid data in the SPIRX
register is overwritten or if valid data in the RX shift register is
discarded, SPISTA, Bit 5 (the overflow bit) is set.
CS
CS
deassertion of . In slave mode,
is always an input.
Rev. F | Page 74 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
SPI Registers
Table 121. SPIRX Register
Name
Address
Default Value
Access
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPIRX
0xFFFF0A04
0x00
R
SPIRX is an 8-bit, read-only receive register.
Table 119. SPISTA Register
Name
Address
Default Value
Access
Table 122. SPITX Register
SPISTA
0xFFFF0A00
0x00
R
Name
Address
Default Value
Access
SPITX
0xFFFF0A08
0x00
W
SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4
of this register generates an interrupt. Bit 6 of the SPICON
register determines which bit generates the interrupt.
SPITX is an 8-bit, write-only transmit register.
Table 123. SPIDIV Register
Name
Table 120. SPISTA MMR Bit Descriptions
Address
Default Value
Access
Bit
7:6
5
Description
SPIDIV
0xFFFF0A0C
0x1B
R/W
Reserved.
SPIDIV is an 8-bit, serial clock divider register.
SPIRX data register overflow status bit. Set if SPIRX is
overflowing. Cleared by reading the SPIRX register.
Table 124. SPICON Register
Name
4
3
SPIRX data register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading the SPIRX register.
SPIRX data register full status bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading the SPIRX register.
Address
Default Value
Access
SPICON
0xFFFF0A10
0x0000
R/W
SPICON is a 16-bit control register.
2
1
0
SPITX data register underflow status bit. Set auto-
matically if SPITX is underflowing. Cleared by writing in
the SPITX register.
SPITX data register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
SPITX data register empty status bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
Table 125. SPICON MMR Bit Descriptions
Bit
Description
Function
15:13
12
Reserved
Continuous transfer enable
N/A
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is
CS
available in the TX register. is asserted and remains asserted for the duration of each 8-bit serial transfer
until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit
serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period.
11
10
Loop back enable
Slave MISO output enable
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Set this bit to disable the output driver on the MISO pin. The MISO pin becomes open drain when this bit is
set. Clear this bit for MISO to operate as normal.
9
Clip select output enable
Set by user in master mode to disable the chip select output. cleared by user to enable the chip select
output.
CS
P1.7 should be configured as before SPICON is configured as a master when the chip select output
enabled is also selected.
8
SPIRX overflow overwrite enable
Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by user,
the new serial byte received is discarded.
7
6
SPITX underflow mode
Transfer and interrupt mode
Set by user to transmit 0. Cleared by user to transmit the previous data.
Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when TX is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when RX is full.
5
4
3
2
LSB first transfer enable bit
Reserved
Serial clock polarity mode bit
Serial clock phase mode bit
Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial
clock pulses at the end of each serial bit transfer.
1
0
Master mode enable bit
SPI enable bit
Set by user to enable master mode. Cleared by user to enable slave mode.
Set by user to enable the SPI. Cleared by user to disable the SPI.
Rev. F | Page 75 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
I2C-COMPATIBLE INTERFACES
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3 contain
the device IDs. The device compares the four I2C0IDx registers
to the address byte. To be correctly addressed, the seven MSBs of
either ID register must be identical to that of the seven MSBs of
the first received address byte. The LSB of the ID registers (the
transfer direction bit) is ignored in the process of address
recognition.
The ADuC7019/20/21/22/24/25/26/27/28/29 support two licensed
I2C interfaces. The I2C interfaces are both implemented as a hard-
ware master and a full slave interface. Because the two I2C inter-
faces are identical, this data sheet describes only I2C0 in detail.
Note that the two masters and one of the slaves have individual
interrupts (see the Interrupt System section).
Note that when configured as an I2C master device, the
ADuC7019/20/21/22/24/25/26/27/28/29 cannot generate a
repeated start condition.
I2C Registers
The I2C peripheral interface consists of 18 MMRs, which are
discussed in this section.
The two GPIO pins used for data transfer, SDAx and SCLx, are
configured in a wired-AND format that allows arbitration in a
multimaster system. These pins require external pull-up resistors.
Typical pull-up values are 10 kΩ.
The I2C bus peripheral address in the I2C bus system is pro-
grammed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
Table 126. I2CxMSTA Registers
Name
Address
Default Value
Access
R/W
I2C0MSTA
I2C1MSTA
0xFFFF0800
0xFFFF0900
0x00
0x00
R/W
I2CxMSTA are status registers for the master channel.
Table 127. I2C0MSTA MMR Bit Descriptions
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer during the initial address
transfer. If the master does not lose arbitration and the slave
acknowledges, the data transfer is initiated. This continues until
the master issues a stop condition and the bus becomes idle.
The I2C peripheral can be configured only as a master or slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes.
Access
Bit Type
Description
7
R/W
Master transmit FIFO flush. Set by user to flush
the master Tx FIFO. Cleared automatically after
the master Tx FIFO is flushed. This bit also
flushes the slave receive FIFO.
Master busy. Set automatically if the master is
busy. Cleared automatically.
Arbitration loss. Set in multimaster mode if
another master has the bus. Cleared when the
bus becomes available.
No ACK. Set automatically if there is no
acknowledge of the address by the slave
device. Cleared automatically by reading the
I2C0MSTA register.
Master receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0MRX
register.
Master transmit IRQ. Set at the end of a
transmission. Cleared automatically by writing
to the I2C0MTX register.
Master transmit FIFO underflow. Set
automatically if the master transmit FIFO is
underflowing. Cleared automatically by
writing to the I2C0MTX register.
Master TX FIFO not full. Set automatically if the
slave transmit FIFO is not full. Cleared automati-
cally by writing twice to the I2C0STX register.
6
5
R
R
4
R
Serial Clock Generation
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
3
2
1
R
R
R
The bit rate is defined in the I2C0DIV MMR as follows:
fUCLK
fSERIAL CLOCK
=
(2 + DIVH) + (2 + DIVL)
where:
UCLK = clock before the clock divider.
f
DIVH = the high period of the clock.
DIVL = the low period of the clock.
0
R
Thus, for 100 kHz operation,
DIVH = DIVL = 0xCF
Table 128. I2CxSSTA Registers
and for 400 kHz,
Name
Address
Default Value
0x01
Access
DIVH = 0x28, DIVL = 0x3C
The I2CxDIV registers correspond to DIVH:DIVL.
I2C0SSTA
I2C1SSTA
0xFFFF0804
0xFFFF0904
R
R
0x01
I2CxSSTA are status registers for the slave channel.
Rev. F | Page 76 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 130. I2CxSRX Registers
Table 129. I2C0SSTA MMR Bit Descriptions
Name
Address
Default Value
0x00
Access
Bit
Value Description
I2C0SRX
I2C1SRX
0xFFFF0808
0xFFFF0908
R
R
31:15
14
Reserved. These bits should be written as 0.
0x00
Start decode bit. Set by hardware if the device
receives a valid start plus matching address.
Cleared by an I2C stop condition or an I2C
general call reset.
I2CxSRX are receive registers for the slave channel.
Table 131. I2CxSTX Registers
13
Repeated start decode bit. Set by hardware
if the device receives a valid repeated start and
matching address. Cleared by an I2C stop condi-
tion, a read of the I2CSSTA register, or an I2C
general call reset.
Name
Address
Default Value
0x00
Access
W
I2C0STX
I2C1STX
0xFFFF080C
0xFFFF090C
0x00
W
I2CxSTX are transmit registers for the slave channel.
12:11
ID decode bits.
Table 132. I2CxMRX Registers
Name
00
01
10
11
Received Address Matched ID Register 0.
Received Address Matched ID Register 1.
Received Address Matched ID Register 2.
Received Address Matched ID Register 3.
Address
Default Value
0x00
Access
I2C0MRX
I2C1MRX
0xFFFF0810
0xFFFF0910
R
R
0x00
10
Stop after start and matching address interrupt.
Set by hardware if the slave device receives an
I2C stop condition after a previous I2C start
condition and matching address. Cleared by a
read of the I2C0SSTA register.
General call ID.
No general call.
General call reset and program address.
General call program address.
General call matching alternative ID.
General call interrupt. Set if the slave device
receives a general call of any type. Cleared by
setting Bit 8 of the I2CxCFG register. If it is a
general call reset, all registers are at their
default values. If it is a hardware general call,
the Rx FIFO holds the second byte of the
general call. This is similar to the I2C0ALT
register (unless it is a general call to reprogram
the device address). For more details, see the I2C
bus specification, Version 2.1, January 2000.
Slave busy. Set automatically if the slave is busy.
Cleared automatically.
No ACK. Set if master asking for data and no
data is available. Cleared automatically by
reading the I2C0SSTA register.
I2CxMRX are receive registers for the master channel.
Table 133. I2CxMTX Registers
Name
Address
Default Value
0x00
Access
W
I2C0MTX
I2C1MTX
0xFFFF0814
0xFFFF0914
9:8
0x00
W
00
01
10
11
I2CxMTX are transmit registers for the master channel.
Table 134. I2CxCNT Registers
Name
Address
Default Value
0x00
Access
R/W
7
I2C0CNT
I2C1CNT
0xFFFF0818
0xFFFF0918
0x00
R/W
I2CxCNT are 3-bit, master receive, data count registers. If a master
read transfer sequence is initiated, the I2CxCNT registers denote
the number of bytes (−1) to be read from the slave device. By
default, this counter is 0, which corresponds to the one byte
expected.
Table 135. I2CxADR Registers
6
5
Name
Address
Default Value
0x00
Access
R/W
I2C0ADR
I2C1ADR
0xFFFF081C
0xFFFF091C
0x00
R/W
I2CxADR are master address byte registers. The I2CxADR
value is the device address that the master wants to commun-
icate with. It automatically transmits at the start of a master
transfer sequence if there is no valid data in the I2CxMTX
register when the master enable bit is set.
4
3
2
1
0
Slave receive FIFO overflow. Set automatically if
the slave receive FIFO is overflowing. Cleared
automatically by reading the I2C0SSTA register.
Slave receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0SRX
register or flushing the FIFO.
Slave transmit IRQ. Set at the end of a trans-
mission. Cleared automatically by writing to the
I2C0STX register.
Slave transmit FIFO underflow. Set automatically if
the slave transmit FIFO is underflowing. Cleared
automatically by writing to the I2C0SSTA register.
Table 136. I2CxBYTE Registers
Name
Address
Default Value
0x00
Access
R/W
I2C0BYTE
I2C1BYTE
0xFFFF0824
0xFFFF0924
0x00
R/W
I2CxBYTE are broadcast byte registers. Data written to these
registers does not go through the TxFIFO. This data is transmitted
at the start of a transfer sequence before the address. After the
byte is transmitted and acknowledged, the I2C expects another
byte written in I2CxBYTE or an address written to the address
register.
Slave transmit FIFO not full. Set automatically if
the slave transmit FIFO is not full. Cleared auto-
matically by writing twice to the I2C0STX register.
Rev. F | Page 77 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 137. I2CxALT Registers
Table 138. I2CxCFG Registers
Name
Address
Default Value
0x00
Access
R/W
Name
Address
Default Value
Access
R/W
I2C0ALT
I2C1ALT
0xFFFF0828
0xFFFF0928
I2C0CFG
I2C1CFG
0xFFFF082C
0xFFFF092C
0x00
0x00
0x00
R/W
R/W
I2CxALT are hardware general call ID registers used in slave mode.
I2CxCFG are configuration registers.
Table 139. I2C0CFG MMR Bit Descriptions
Bit
Description
31:5 Reserved. These bits should be written by the user as 0.
14
Enable stop interrupt. Set by the user to generate an interrupt upon receiving a stop condition and after receiving a valid start
condition and matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition.
13
12
11
10
9
Reserved.
Reserved.
Enable stretch SCL (holds SCL low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line.
Reserved.
Slave Tx FIFO request interrupt enable. Set by the user to disable the slave Tx FIFO request interrupt. Cleared by the user to generate
an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to input data into the slave Tx FIFO if
it is empty. At 400 ksps and the core clock running at 41.78 MHz, the user has 45 clock cycles to take appropriate action, taking
interrupt latency into account.
8
7
6
5
4
General call status bit clear. Set by the user to clear the general call status bits. Cleared automatically by hardware after the general
call status bits are cleared.
Master serial clock enable bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial
clock in master mode.
Loopback enable bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to operate
in normal mode.
Start backoff disable bit. Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit. Cleared by
user to enable start backoff. After losing arbitration, the master waits before trying to retransmit.
Hardware general call enable. When this bit and Bit 3 are set and have received a general call (Address 0x00) and a data byte, the
device checks the contents of I2C0ALT against the receive register. If the contents match, the device has received a hardware general
call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a
“to whom it may concern” call. The ADuC7019/20/21/22/24/25/26/27/28/29 watch for these addresses. The device that requires
attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and
acts appropriately. The LSB of the I2C0ALT register should always be written to 1, as indicated in The I2C-Bus Specification, January
2000, from NXP.
3
General call enable bit. This bit is set by the user to enable the slave device to acknowledge (ACK) an I2C general call, Address 0x00
(write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of slave address by hardware)
as the data byte, the I2C interface resets as as indicated in The I2C-Bus Specification, January 2000, from NXP. This command can be
used to reset an entire I2C system. The general call interrupt status bit sets on any general call. The user must take corrective action by
setting up the I2C interface after a reset. If it receives a 0x04 (write programmable part of slave address by hardware) as the data byte,
the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address.
2
1
0
Reserved.
Master enable bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel.
Slave enable bit. Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in I2C0ID0,
I2C0ID1, I2C0ID2, and I2C0ID3. At 400 kSPs, the core clock should run at 41.78 MHz because the interrupt latency could be up to 45
clock cycles alone. After the I2C read bit, the user has 0.5 of an I2C clock cycle to load the Tx FIFO. AT 400 kSPS, this is 1.26 μs, the
interrupt latency.
Rev. F | Page 78 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 140. I2CxDIV Registers
Table 144. I2C0FSTA MMR Bit Descriptions
Name
Address
Default Value
0x1F1F
Access
R/W
Access
Type
Bit
15:10
9
Value Description
I2C0DIV
I2C1DIV
0xFFFF0830
0xFFFF0930
Reserved.
Master transmit FIFO flush. Set by the
0x1F1F
R/W
R/W
I2CxDIV are the clock divider registers.
user to flush the master Tx FIFO.
Cleared automatically when the
master Tx FIFO is flushed. This bit
also flushes the slave receive FIFO.
Slave transmit FIFO flush. Set by the
user to flush the slave Tx FIFO. Cleared
automatically after the slave Tx FIFO
is flushed.
Master Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Table 141. I2CxIDx Registers
Name
Address
Default Value
0x00
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2C0ID0
I2C0ID1
I2C0ID2
I2C0ID3
I2C1ID0
I2C1ID1
I2C1ID2
I2C1ID3
0xFFFF0838
0xFFFF083C
0xFFFF0840
0xFFFF0844
0xFFFF0938
0xFFFF093C
0xFFFF0940
0xFFFF0944
8
R/W
R
0x00
0x00
0x00
7:6
0x00
00
01
10
11
0x00
0x00
0x00
5:4
3:2
1:0
R
R
R
Master Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Slave Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Slave Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
00
01
10
11
Table 142. I2CxCCNT Registers
Name
Address
Default Value
Access
R/W
I2C0CCNT
I2C1CCNT
0xFFFF0848
0xFFFF0948
0x01
0x01
R/W
00
01
10
11
I2CxCCNT are 8-bit start/stop generation counters. They hold
off SDA low for start and stop conditions.
Table 143. I2CxFSTA Registers
Name
Address
Default Value
0x0000
Access
R/W
00
01
10
11
I2C0FSTA
I2C1FSTA
0xFFFF084C
0xFFFF094C
0x0000
R/W
I2CxFSTA are FIFO status registers.
Rev. F | Page 79 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
PROGRAMMABLE LOGIC ARRAY (PLA)
Table 146. PLAELMx Registers
Every ADuC7019/20/21/22/24/25/26/27/28/29 integrates a
fully programmable logic array (PLA) that consists of two
independent but interconnected PLA blocks. Each block
consists of eight PLA elements, giving each part a total of
16 PLA elements.
Name
Address
Default Value
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
0xFFFF0B00
0xFFFF0B04
0xFFFF0B08
0xFFFF0B0C
0xFFFF0B10
0xFFFF0B14
0xFFFF0B18
0xFFFF0B1C
0xFFFF0B20
0xFFFF0B24
0xFFFF0B28
0xFFFF0B2C
0xFFFF0B30
0xFFFF0B34
0xFFFF0B38
0xFFFF0B3C
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Each PLA element contains a two-input lookup table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 76.
0
4
A
2
LOOKUP
TABLE
B
3
1
Figure 76. PLA Element
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the lookup table, and bypass/use the flip-flop. See
Table 147 and Table 152.
In total, 30 GPIO pins are available on each ADuC7019/20/21/
22/24/25/26/27/28/29 for the PLA. These include 16 input pins
and 14 output pins, which msut be configured in the GPxCON
register as PLA pins before using the PLA. Note that the
comparator output is also included as one of the 16 input pins.
Table 147. PLAELMx MMR Bit Descriptions
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
Bit
Value Description
31:11
10:9
8:7
Reserved.
Mux 0 control (see Table 152).
Mux 1 control (see Table 152).
CONVSTART
signal of the ADC, to an MMR, or to any of the 16
PLA output pins.
6
Mux 2 control. Set by user to select the output
of Mux 0. Cleared by user to select the bit value
from PLADIN.
Mux 3 control. Set by user to select the input
pin of the particular element. Cleared by user to
select the output of Mux 1.
The two blocks can be interconnected as follows:
Output of Element 15 (Block 1) can be fed back to Input 0
of Mux 0 of Element 0 (Block 0).
5
Output of Element 7 (Block 0) can be fed back to the Input 0
of Mux 0 of Element 8 (Block 1).
4:1
Lookup table control.
Table 145. Element Input/Output
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.
NOR.
PLA Block 0
PLA Block 1
Input
P3.0
B AND NOT A.
NOT A.
A AND NOT B.
NOT B.
EXOR.
NAND.
AND.
EXNOR.
B.
NOT A OR B.
A.
A OR NOT B.
OR.
Element Input
Output
P1.7
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
Element
Output
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
0
1
2
3
4
5
6
7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P0.0
8
9
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
10
11
12
13
14
15
PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs
described in this section.
1.
0
Mux 4 control. Set by user to bypass the flip-
flop. Cleared by user to select the flip-flop
(cleared by default).
Rev. F | Page 80 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 148. PLACLK Register
Table 150. PLAIRQ Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
PLACLK
0xFFFF0B40
0x00
R/W
PLAIRQ
0xFFFF0B44
0x00000000
R/W
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. Note that the maximum frequency when using the
GPIO pins as the clock input for the PLA blocks is 44 MHz.
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source
of the IRQ.
Table 151. PLAIRQ MMR Bit Descriptions
Table 149. PLACLK MMR Bit Descriptions
Bit
Value
Description
Bit
Value
Description
15:13
12
Reserved.
7
Reserved.
PLA IRQ1 enable bit. Set by user to enable
IRQ1 output from PLA. Cleared by user to
disable IRQ1 output from PLA.
6:4
Block 1 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz) external crystal only.
Timer1 overflow.
Reserved.
000
001
010
011
100
101
Other
11:8
PLA IRQ1 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 enable bit. Set by user to enable
IRQ0 output from PLA. Cleared by user to
disable IRQ0 output from PLA.
0000
0001
1111
7:5
4
3
Reserved.
2:0
Block 0 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz) external crystal only.
Timer1 overflow.
Reserved.
000
001
010
011
100
101
Other
3:0
PLA IRQ0 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
0000
0001
1111
Table 152. Feedback Configuration
Bit
Value
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
10:9
00
01
10
11
00
01
10
11
8:7
Rev. F | Page 81 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 153. PLAADC Register
Table 156. PLADIN MMR Bit Descriptions
Name
Address
Default Value
Access
Bit
Description
PLAADC
0xFFFF0B48
0x00000000
R/W
31:16
15:0
Reserved.
Input bit to Element 15 to Element 0.
PLAADC is the PLA source for the ADC start conversion signal.
Table 157. PLADOUT Register
Table 154. PLAADC MMR Bit Descriptions
Name
Address
Default Value
Access
Bit
31:5
4
Value Description
PLADOUT
0xFFFF0B50
0x00000000
R
Reserved.
ADC start conversion enable bit. Set by user
PLADOUT is a data output MMR for PLA. This register is
always updated.
to enable ADC start conversion from PLA.
Cleared by user to disable ADC start
conversion from PLA.
Table 158. PLADOUT MMR Bit Descriptions
3:0
ADC start conversion source.
PLA Element 0.
PLA Element 1.
Bit
Description
0000
0001
1111
31:16
15:0
Reserved.
Output bit from Element 15 to Element 0.
PLA Element 15.
Table 159. PLALCK Register
Table 155. PLADIN Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
PLALCK
0xFFFF0B54
0x00
W
PLADIN
0xFFFF0B4C
0x00000000
R/W
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modifying any of the PLA MMRs, except
PLADIN. A PLA tool is provided in the development system to
easily configure the PLA.
PLADIN is a data input MMR for PLA.
Rev. F | Page 82 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-purpose
interrupt handling of internal and external events.
There are 23 interrupt sources on the ADuC7019/20/21/22/
24/25/26/27/28/29 that are controlled by the interrupt
controller. Most interrupts are generated from the on-chip
peripherals, such as ADC and UART. Four additional interrupt
sources are generated from external interrupt request pins,
IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI CPU core only
recognizes interrupts as one of two types: a normal interrupt
request IRQ or a fast interrupt request FIQ. All the interrupts
can be masked separately.
The four 32-bit registers dedicated to IRQ are IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
Table 161. IRQSTA Register
Name
Address
Default Value
Access
IRQSTA
0xFFFF0000
0x00000000
R
IRQSTA (read-only register) provides the current-enabled IRQ
source status. When set to 1, that source should generate an
active IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create the IRQ signal
to the ARM7TDMI core.
The control and configuration of the interrupt system are
managed through nine interrupt-related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ register (except for Bit 23) represent
the same interrupt source as described in Table 160.
Table 160. IRQ/FIQ MMRs Bit Description
Table 162. IRQSIG Register
Bit
Description
All interrupts OR’ed (FIQ only)
SWI
Name
Address
Default Value
0x00XXX0001
Access
0
1
IRQSIG
0xFFFF0004
R
1 X indicates an undefined value.
2
Timer0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Timer1
IRQSIG reflects the status of the different IRQ sources. If a periph-
eral generates an IRQ signal, the corresponding bit in the IRQSIG
is set; otherwise, it is cleared. The IRQSIG bits are cleared when
the interrupt in the particular peripheral is cleared. All IRQ
sources can be masked in the IRQEN MMR. IRQSIG is read only.
Wake-up timer (Timer2)
Watchdog timer (Timer3)
Flash control
ADC channel
PLL lock
I2C0 slave
I2C0 master
I2C1 master
SPI slave
Table 163. IRQEN Register
Name
Address
Default Value
Access
IRQEN
0xFFFF0008
0x00000000
R/W
IRQEN provides the value of the current enable mask. When
each bit is set to 1, the source request is enabled to create an
IRQ exception. When each bit is set to 0, the source request is
disabled or masked, which does not create an IRQ exception.
SPI master
UART
External IRQ0
Comparator
PSM
External IRQ1
PLA IRQ0
Note that to clear an already enabled interrupt source, the user
must set the appropriate bit in the IRQCLR register. Clearing an
interrupt’s IRQEN bit does not disable the interrupt.
PLA IRQ1
Table 164. IRQCLR Register
External IRQ2
External IRQ3
PWM trip (IRQ only)/PWM sync (FIQ only)
Name
Address
Default Value
Access
IRQCLR
0xFFFF000C
0x00000000
W
IRQCLR (write-only register) clears the IRQEN register in
order to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
independently manipulates the enable mask without requiring
an atomic read-modify-write.
Rev. F | Page 83 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
FIQ
Table 170. SWICFG MMR Bit Descriptions
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface providing the
second-level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit
31:3
2
Description
Reserved.
Programmed interrupt (FIQ). Setting/clearing this bit
corresponds with setting/clearing Bit 1 of FIQSTA
and FIQSIG.
1
Programmed interrupt (IRQ). Setting/clearing this bit
corresponds with setting/clearing Bit 1 of IRQSTA
and IRQSIG.
Table 165. FIQSTA Register
Name
Address
Default Value
Access
0
Reserved.
FIQSTA
0xFFFF0100
0x00000000
R
Note that any interrupt signal must be active for at least the
equivalent of the interrupt latency time, which is detected by
the interrupt controller and by the user in the IRQSTA/FIQSTA
register.
Table 166. FIQSIG Register
Name
Address
Default Value
0x00XXX0001
Access
FIQSIG
0xFFFF0104
R
1 X indicates an undefined value.
TIMERS
The ADuC7019/20/21/22/24/25/26/27/28/29 have four general-
purpose timer/counters.
Table 167. FIQEN Register
Name
Address
Default Value
Access
FIQEN
0xFFFF0108
0x00000000
R/W
•
•
•
•
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Table 168. FIQCLR Register
Name
Address
Default Value
Access
FIQCLR
0xFFFF010C
0x00000000
W
These four timers in their normal mode of operation can be
either free running or periodic.
Bit 31 to Bit 1 of FIQSTA are logically OR’d to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
In free-running mode, the counter decreases from the
maximum value until zero scale and starts again at the
minimum value. (It also increases from the minimum value
until full scale and starts again at the maximum value.)
The logic for FIQEN and IRQEN does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN does, as a side effect, clear the same bit in IRQEN.
Also, a bit set to 1 in IRQEN does, as a side effect, clear the
same bit in FIQEN. An interrupt source can be disabled in both
the IRQEN and FIQEN masks.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale and
starts again at the value stored in the load register.
The timer interval is calculated as follows:
Note that to clear an already enabled FIQ source, the user must
set the appropriate bit in the FIQCLR register. Clearing an
interrupt’s FIQEN bit does not disable the interrupt.
If the timer is set to count down then
(
TxLD
)
×Prescaler
Programmed Interrupts
Interval =
SourceClock
Because the programmed interrupts are nonmaskable, they are
controlled by another register, SWICFG, which simultaneously
writes into the IRQSTA and IRQSIG registers and/or the
FIQSTA and FIQSIG registers. The 32-bit SWICFG register is
dedicated to software interrupts(see Table 170). This MMR
allows the control of a programmed source interrupt.
If the timer is set to count up, then
Fs − TxLD × Prescaler
SourceClock
(
)
Interval =
The value of a counter can be read at any time by accessing its
value register (TxVAL). Note that when a timer is being clocked
from a clock other than core clock, an incorrect value may be
read (due to an asynchronous clock system). In this configur-
ation, TxVAL should always be read twice. If the two readings
are different, it should be read a third time to get the correct
value.
Table 169. SWICFG Register
Name
Address
Default Value
Access
SWICFG
0xFFFF0010
0x00000000
W
Timers are started by writing in the control register of the
corresponding timer (TxCON).
Rev. F | Page 84 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting
up. An IRQ can be cleared by writing any value to clear the
register of that particular timer (TxCLRI).
The Timer0 interface consists of four MMRs: T0LD, T0VAL,
T0CON, and T0CLRI.
Table 172. T0LD Register
Name
Address
Default Value
Access
T0LD
0xFFFF0300
0x0000
R/W
When using an asynchronous clock-to-clock timer, the
interrupt in the timer block may take more time to clear
than the time it takes for the code in the interrupt routine to
execute. Ensure that the interrupt signal is cleared before
leaving the interrupt service routine. This can be done by
checking the IRQSTA MMR.
T0LD is a 16-bit load register.
Table 173. T0VAL Register
Name
Address
Default Value
Access
T0VAL
0xFFFF0304
0xFFFF
R
T0VAL is a 16-bit read-only register representing the current
state of the counter.
Hour:Minute:Second:1/128 Format
To use the timer in hour:minute:second:hundredths format,
select the 32,768 kHz clock and prescaler of 256. The hun-
dredths field does not represent milliseconds but 1/128 of
a second (256/32,768). The bits representing the hour,
minute, and second are not consecutive in the register.
This arrangement applies to TxLD and TxVAL when using
the hour:minute:second:hundredths format as set in
TxCON[5:4]. See Table 171 for additional details.
Table 174. T0CON Register
Name
Address
Default Value
Access
T0CON
0xFFFF0308
0x0000
R/W
T0CON is the configuration MMR described in Table 175.
Table 175. T0CON MMR Bit Descriptions
Bit
15:8
7
Value Description
Reserved.
Timer0 enable bit. Set by user to enable Timer0.
Table 171. Hour:Minnute:Second:Hundredths Format
Cleared by user to disable Timer0 by default.
Bit
Value
Description
6
Timer0 mode. Set by user to operate in
periodic mode. Cleared by user to operate
in free-running mode. Default mode.
Reserved.
Prescale.
Core Clock/1. Default value.
Core Clock/16.
Core Clock/256.
Undefined. Equivalent to 00.
Reserved.
31:24
23:22
21:16
15:14
13.8
7
0 to 23 or 0 to 255
0
0 to 59
0
0 to 59
0
Hours
Reserved
Minutes
Reserved
Seconds
Reserved
1/128 second
5:4
3:2
00
01
10
11
6:0
0 to 127
Timer0 (RTOS Timer)
1:0
Timer0 is a general-purpose, 16-bit timer (count down) with a
programmable prescaler (see Figure 77). The prescaler source is
the core clock frequency (HCLK) and can be scaled by factors
of 1, 16, or 256.
Table 176. T0CLRI Register
Name
Address
Default Value
Access
T0CLRI
0xFFFF030C
0xFF
W
T0CLRI is an 8-bit register. Writing any value to this register
clears the interrupt.
Timer0 can be used to start ADC conversions as shown in the
block diagram in Figure 77.
16-BIT
LOAD
16-BIT
PRESCALER
/1, 16 OR 256
TIMER0 IRQ
DOWN
HCLK
COUNTER
ADC CONVERSION
TIMER0
VALUE
Figure 77. Timer0 Block Diagram
Rev. F | Page 85 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Timer1 (General-Purpose Timer)
The Timer1 interface consists of five MMRs: T1LD, T1VAL,
T1CON, T1CLRI, and T1CAP.
Timer1 is a general-purpose, 32-bit timer (count down or count
up) with a programmable prescaler. The source can be the
32 kHz external crystal, the core clock frequency, or an external
GPIO (P1.0 or P0.6). The maximum frequency of the clock
input is 44 Mhz). This source can be scaled by a factor of 1, 16,
256, or 32,768.
Table 177. T1LD Register
Name
Address
Default Value
Access
T1LD
0xFFFF0320
0x00000000
R/W
T1LD is a 32-bit load register.
The counter can be formatted as a standard 32-bit value or as
hours: minutes: seconds: hundredths.
Table 178. T1VAL Register
Name
Address
Default Value
Access
T1VAL
0xFFFF0324
0xFFFFFFFF
R
Timer1 has a capture register (T1CAP) that can be triggered by
a selected IRQ source initial assertion. This feature can be used
to determine the assertion of an event more accurately than the
precision allowed by the RTOS timer when the IRQ is serviced.
T1VAL is a 32-bit read-only register that represents the current
state of the counter.
Table 179. T1CON Register
Timer1 can be used to start ADC conversions as shown in the
block diagram in Figure 78.
Name
Address
Default Value
Access
T1CON
0xFFFF0328
0x0000
R/W
T1CON is the configuration MMR described in Table 180.
32-BIT
LOAD
32kHz OSCILLATOR
PRESCALER
/1, 16, 256
OR 32,768
32-BIT
UP/DOWN
COUNTER
HCLK
P0.6
P1.0
TIMER1 IRQ
ADC CONVERSION
TIMER1
VALUE
CAPTURE
IRQ[31:0]
Figure 78. Timer1 Block Diagram
Rev. F | Page 86 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 180. T1CON MMR Bit Descriptions
Table 182. T1CAP Register
Bit
Value
Description
Name
Address
Default Value
Access
31:18
17
Reserved.
T1CAP
0xFFFF0330
0x00000000
R/W
Event select bit. Set by user to enable time
capture of an event. Cleared by user to
disable time capture of an event.
Event select range, 0 to 31. These events are
as described in Table 160. All events are
offset by two; that is, Event 2 in Table 160
becomes Event 0 for the purposes of
Timer1.
T1CAP is a 32-bit register. It holds the value contained in
T1VAL when a particular event occurs. This event must be
selected in T1CON.
16:12
11:9
Timer2 (Wake-Up Timer)
Timer2 is a 32-bit wake-up timer (count down or count up)
with a programmable prescaler. The source can be the 32 kHz
external crystal, the core clock frequency, or the internal 32 kHz
oscillator. The clock source can be scaled by a factor of 1, 16,
256, or 32,768. The wake-up timer continues to run when the
core clock is disabled.
Clock select.
Core clock (HCLK).
000
001
010
011
External 32.768 kHz crystal.
P1.0 rising edge triggered.
P0.6 rising edge triggered.
Count up. Set by user for Timer1 to count
up. Cleared by user for Timer1 to count
down by default.
The counter can be formatted as plain 32-bit value or as
hours: minutes: seconds: hundredths.
8
32-BIT
LOAD
7
Timer1 enable bit. Set by user to enable
Timer1. Cleared by user to disable Timer1 by
default.
INTERNAL
OSCILLATOR
PRESCALER
/1, 16, 256
OR 32,768
32-BIT
UP/DOWN
COUNTER
EXTERNAL
CRYSTAL
TIMER2 IRQ
6
Timer1 mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
HCLK
TIMER2
VALUE
5:4
Format.
Figure 79. Timer2 Block Diagram
00
01
10
11
Binary.
Reserved.
The Timer2 interface consists of four MMRs: T2LD, T2VAL,
T2CON, and T2CLRI.
Hr: min: sec: hundredths (23 hours to 0 hour).
Hr: min: sec: hundredths (255 hours to 0
hour).
Table 183. T2LD Register
Name
Address
Default Value
Access
3:0
Prescale.
T2LD
0xFFFF0340
0x00000000
R/W
0000
0100
1000
1111
Source Clock/1.
Source Clock/16.
Source Clock/256.
Source Clock/32,768.
T2LD is a 32-bit register load register.
Table 184. T2VAL Register
Name
Address
Default Value
Access
T2VAL
0xFFFF0344
0xFFFFFFFF
R
Table 181. T1CLRI Register
Name
Address
Default Value
Access
T2VAL is a 32-bit read-only register that represents the current
state of the counter.
T1CLRI
0xFFFF032C
0xFF
W
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
Table 185. T2CON Register
Name
Address
Default Value
Access
T2CON
0xFFFF0348
0x0000
R/W
T2CON is the configuration MMR described in Table 186.
Rev. F | Page 87 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
16-BIT
LOAD
Table 186. T2CON MMR Bit Descriptions
Bit
Value Description
WATCHDOG
16-BIT
UP/DOWN
COUNTER
31:11
10:9
Reserved.
Clock source.
RESET
PRESCALER
/1, 16 OR 256
32.768kHz
TIMER3 IRQ
00
01
10
11
External crystal.
External crystal.
Internal oscillator.
Core clock (41 MHz/2CD).
TIMER3
VALUE
Figure 80. Timer3 Block Diagram
Watchdog Mode
8
Count up. Set by user for Timer2 to count up.
Cleared by user for Timer2 to count down by
default.
Watchdog mode is entered by setting Bit 5 in the T3CON MMR.
Timer3 decreases from the value present in the T3LD register to 0.
T3LD is used as the timeout. The maximum timeout can be
512 sec, using the prescaler/256, and full scale in T3LD. Timer3
is clocked by the internal 32 kHz crystal when operating in
watchdog mode. Note that to enter watchdog mode success-
fully, Bit 5 in the T3CON MMR must be set after writing to the
T3LD MMR.
7
6
Timer2 enable bit. Set by user to enable Timer2.
Cleared by user to disable Timer2 by default.
Timer2 mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
Format.
Binary.
5:4
00
01
10
11
Reserved.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in the T3CON register. To avoid reset or interrupt, any
value must be written to T3CLRI before the expiration period.
This reloads the counter with T3LD and begins a new timeout
period.
Hr: min: sec: Hundredths (23 hours to 0 hour).
Hr: min: sec: Hundredths (255 hours to 0 hour).
Prescale.
Source Clock/1 by default.
Source Clock/16.
Source Clock/256 expected for Format 2 and
Format 3.
Source Clock/32,768.
3:0
0000
0100
1000
When watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers cannot be modified until a reset
clears the watchdog enable bit, which causes Timer3 to exit
watchdog mode.
1111
Table 187. T2CLRI Register
Name
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CON, and T3CLRI.
Address
Default Value
Access
T2CLRI
0xFFFF034C
0xFF
W
Table 188. T3LD Register
T2CLRI is an 8-bit register. Writing any value to this register
clears the Timer2 interrupt.
Name
Address
Default Value
Access
T3LD
0xFFFF0360
0x0000
R/W
Timer3 (Watchdog Timer)
T3LD is a 16-bit register load register.
Timer3 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a processor reset.
Table 189. T3VAL Register
Name
Address
Default Value
Access
T3VAL
0xFFFF0364
0xFFFF
R
Normal Mode
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source
is 32 kHz from the PLL and can be scaled by a factor of 1, 16,
or 256 (see Figure 80).
Table 190. T3CON Register
Name
Address
Default Value
Access
T3CON
0xFFFF0368
0x0000
R/W
T3CON is the configuration MMR described in Table 191.
Rev. F | Page 88 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
The value 0x00 should not be used as an initial seed due to
the properties of the polynomial. The value 0x00 is always
guaranteed to force an immediate reset. The value of the LFSR
cannot be read; it must be tracked/generated in software.
Table 191. T3CON MMR Bit Descriptions
Bit
15:9
8
Value
Description
Reserved.
Count up. Set by user for Timer3 to count up.
Cleared by user for Timer3 to count down by
default.
The following is an example of a sequence:
1. Enter initial seed, 0xAA, in T3CLRI before starting Timer3
in watchdog mode.
2. Enter 0xAA in T3CLRI; Timer3 is reloaded.
3. Enter 0x37 in T3CLRI; Timer3 is reloaded.
4. Enter 0x6E in T3CLRI; Timer3 is reloaded.
5. Enter 0x66. 0xDC was expected; the watchdog resets the chip.
7
6
Timer3 enable bit. Set by user to enable Timer3.
Cleared by user to disable Timer3 by default.
Timer3 mode. Set by user to operate in
periodic mode. Cleared by user to operate
in free-running mode. Default mode.
5
Watchdog mode enable bit. Set by user to
enable watchdog mode. Cleared by user to
disable watchdog mode by default.
EXTERNAL MEMORY INTERFACING
4
Secure clear bit. Set by user to use the secure
clear option. Cleared by user to disable the
secure clear option by default.
Prescale.
Source Clock/1 by default.
Source Clock/16.
The ADuC7026 and ADuC7027 are the only models in their
series that feature an external memory interface. The external
memory interface requires a larger number of pins. This is why
it is only available on larger pin count packages. The XMCFG
MMR must be set to 1 to use the external port.
3:2
00
01
10
11
Although 32-bit addresses are supported internally, only the
lower 16 bits of the address are on external pins.
Source Clock/256.
Undefined. Equivalent to 00.
1
0
Watchdog IRQ option bit. Set by user to
produce an IRQ instead of a reset when
the watchdog reaches 0. Cleared by user to
disable the IRQ option.
The memory interface can address up to four 128 kB blocks of
asynchronous memory (SRAM or/and EEPROM).
The pins required for interfacing to an external memory are
shown in Table 193.
Reserved.
Table 193. External Memory Interfacing Pins
Table 192. T3CLRI Register
Pin
Function
Name
Address
Default Value
Access
AD[16:1]
A16
MS[3:0]
WS
Address/data bus
Extended addressing for 8-bit memory only
Memory select
T3CLRI
0xFFFF036C
0x00
W
T3CLRI is an 8-bit register. Writing any value to this register on
successive occassions clears the Timer3 interrupt in normal
mode or resets a new timeout period in watchdog mode.
Write strobe
RS
Read strobe
Note that the user must perform successive writes to this
register to ensure resetting the timeout period.
AE
BHE, BLE
Address latch enable
Byte write capability
Secure Clear Bit (Watchdog Mode Only)
There are four external memory regions available, as described
in Table 194. Associated with each region are the MS[3:0] pins.
These signals allow access to the particular region of external
memory. The size of each memory region can be 128 kB maxi-
mum, 64 k × 16 or 128 k × 8. To access 128 k with an 8-bit
memory, an extra address line (A16) is provided (see the example
in Figure 82). The four regions are configured independently.
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3CLRI
to avoid a watchdog reset. The value is a sequence generated
by the 8-bit linear feedback shift register (LFSR) polynomial =
X8 + X6 + X5 + X + 1, as shown in Figure 81.
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q D
0
Table 194. Memory Regions
7
6
5
4
3
2
1
Address Start
0x10000000
0x20000000
0x30000000
0x40000000
Address End
0x1000FFFF
0x2000FFFF
0x3000FFFF
0x4000FFFF
Contents
CLOCK
External Memory 0
External Memory 1
External Memory 2
External Memory 3
Figure 81. 8-Bit LFSR
The initial value or seed is written to T3CLRI before entering
watchdog mode. After entering watchdog mode, a write to
T3CLRI must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload occurs. If
it fails to match the expected state, a reset is immediately
generated, even if the count has not yet expired.
Each external memory region can be controlled through three
MMRs: XMCFG, XMxCON, and XMxPAR.
Rev. F | Page 89 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
EEPROM
64k × 16-BIT
ADuC7026/
ADuC7027
Table 198. XMxPAR Registers
A16
Name
Address
Default Value
Access
R/W
AD15:AD0
D0:D15
A0:A15
XM0PAR
XM1PAR
XM2PAR
XM3PAR
0xFFFFF020
0xFFFFF024
0xFFFFF028
0xFFFFF02C
0x70FF
0x70FF
0x70FF
0x70FF
R/W
LATCH
R/W
AE
R/W
MS0
MS1
CS
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
WS
RS
WE
OE
Table 199. XMxPAR MMR Bit Descriptions
RAM
128k × 8-BIT
Bit
Description
D0:D7
15
Enable byte write strobe. This bit is used only for two,
8-bit memory devices sharing the same memory region.
Set by the user to gate the A0 output with the WS
output. This allows byte write capability without using
BHE and BLE signals. Cleared by user to use BHE and BLE
signals.
A16
A0:A15
CS
WE
OE
Figure 82. Interfacing to External EEPROM/RAM
14:12 Number of wait states on the address latch enable STROBE.
11
10
Reserved.
Table 195. XMCFG Register
Extra address hold time. Set by user to disable extra hold
time. Cleared by user to enable one clock cycle of hold
on the address in read and write.
Name
Address
Default Value
Access
XMCFG
0xFFFFF000
0x00
R/W
9
Extra bus transition time on read. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the read strobe (RS).
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
8
Extra bus transition time on write. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the write strobe (WS).
Table 196. XMxCON Registers
7:4
3:0
Number of write wait states. Select the number of wait
states added to the length of the WS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
Number of read wait states. Select the number of wait
states added to the length of the RS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
Name
Address
Default Value
0x00
Access
R/W
XM0CON
XM1CON
XM2CON
XM3CON
0xFFFFF010
0xFFFFF014
0xFFFFF018
0xFFFFF01C
0x00
R/W
0x00
R/W
0x00
R/W
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Figure 83, Figure 84, Figure 85, and Figure 86 show the timing
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
Table 197. XMxCON MMR Bit Descriptions
Bit Description
1
Selects data bus width. Set by user to select a 16-bit data
bus. Cleared by user to select an 8-bit data bus.
0
Enables memory region. Set by user to enable the memory
region. Cleared by user to disable the memory region.
Rev. F | Page 90 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
UCLK
AD[16:0]
MSx
ADDRESS
DATA
AE
RS
Figure 83. External Memory Read Cycle
UCLK
AD[16:0]
ADDRESS
DATA
EXTRA ADDRESS
HOLD TIME
XMxPAR (BIT 10)
MSx
AE
RS
BUS TURN OUT CYCLE
(BIT 9)
BUS TURN OUT CYCLE
(BIT 9)
Figure 84. External Memory Read Cycle with Address Hold and Bus Turn Cycles
Rev. F | Page 91 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
UCLK
AD[16:0]
ADDRESS
DATA
EXTRA ADDRESS
HOLD TIME
(BIT 10)
MSx
AE
WS
WRITE HOLD ADDRESS
AND DATA CYCLES
(BIT 8)
WRITE HOLD ADDRESS
AND DATA CYCLES
(BIT 8)
Figure 85. External Memory Write Cycle with Address and Write Hold Cycles
UCLK
AD[16:0]
ADDRESS
DATA
MSx
AE
1 ADDRESS WAIT STATE
(BIT 14 TO BIT 12)
WS
1 WRITE STROBE WAIT STATE
(BIT 7 TO BIT 4)
Figure 86. External Memory Write Cycle with Wait States
Rev. F | Page 92 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
HARDWARE DESIGN CONSIDERATIONS
Finally, note that the analog and digital ground pins on the
ADuC7019/20/21/22/24/25/26/27/28/29 must be referenced to
the same system ground reference point at all times.
POWER SUPPLIES
The ADuC7019/20/21/22/24/25/26/27/28/29 operational power
supply voltage range is 2.7 V to 3.6 V. Separate analog and
digital power supply pins (AVDD and IOVDD, respectively) allow
AVDD to be kept relatively free of noisy digital signals often
present on the system IOVDD line. In this mode, the part can
also operate with split supplies; that is, it can use different
voltage levels for each supply. For example, the system can
be designed to operate with an IOVDD voltage level of 3.3 V
whereas the AVDD level can be at 3 V or vice versa. A typical
split supply configuration is shown in Figure 87.
IOVDD Supply Sensitivity
The IOVDD supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
DIGITAL
SUPPLY
ANALOG
SUPPLY
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
+
–
+
–
10µF
10µF
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
50 mV on IOVDD, a filter such as the one shown in Figure 89
is recommended.
ADuC7026
73
74
75
AV
DD
26
54
IOV
DD
DACV
DD
0.1µF
0.1µF
8
GND
REF
70
71
67
DACGND
AGND
ADuC7026
1µH
25
53
26
IOGND
IOV
DD
REFGND
10µF
54
DIGITAL
SUPPLY
+
–
Figure 87. External Dual Supply Connections
0.1µF
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 88. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AVDD supply line as well.
25
53
IOGND
Figure 89. Recommended IOVDD Supply Filter
Linear Voltage Regulator
Each ADuC7019/20/21/22/24/25/26/27/28/29 requires a single
3.3 V supply, but the core logic requires a 2.6 V supply. An on-
chip linear regulator generates the 2.6 V from IOVDD for the
core logic. The LVDD pin is the 2.6 V supply for the core logic.
An external compensation capacitor of 0.47 µF must be
connected between LVDD and DGND (as close as possible to
these pins) to act as a tank of charge as shown in Figure 90.
BEAD
DIGITAL SUPPLY
1.6Ω
10µF
10µF
+
–
ADuC7026
73
AV
DD
74
75
26
54
IOV
DD
DACV
DD
0.1µF
0.1µF
8
GND
REF
ADuC7026
70
71
67
DACGND
AGND
25
53
27
LV
DD
IOGND
REFGND
0.47mF
28
DGND
Figure 88. External Single Supply Connections
Note that in both Figure 87 and Figure 88, a large value (10 µF)
reservoir capacitor sits on IOVDD, and a separate 10 µF capacitor
sits on AVDD. In addition, local small-value (0.1 µF) capacitors are
located at each AVDD and IOVDD pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AVDD pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
Figure 90. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOVDD to help improve line regulation performance of the on-
chip voltage regulator.
Rev. F | Page 93 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
For example, do not power components on the analog side (as
seen in Figure 91b) with IOVDD because that forces return
currents from IOVDD to flow through AGND. Avoid digital
currents flowing under analog circuitry, which can occur if a
noisy digital chip is placed on the left half of the board (shown
in Figure 91c). If possible, avoid large discontinuities in the
ground plane(s) such as those formed by a long trace on the same
layer because they force return signals to travel a longer path.
In addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the
ADuC7019/20/21/22/24/25/26/27/28/29-based designs to
achieve optimum performance from the ADCs and DAC.
Although the parts have separate pins for analog and digital
ground (AGND and IOGND), the user must not tie these to
two separate ground planes unless the two ground planes are
connected very close to the part. This is illustrated in the
simplified example shown in Figure 91a. In systems where
digital and analog ground planes are connected together
somewhere else (at the system power supply, for example), the
planes cannot be reconnected near the part because a ground
loop results. In these cases, tie all the ADuC7019/20/21/
22/24/25/26/27/28/29 AGND and IOGND pins to the analog
ground plane, as illustrated in Figure 91b. In systems with only
one ground plane, ensure that the digital and analog components
are physically separated onto separate halves of the board so
that digital return currents do not flow near analog circuitry
(and vice versa).
When connecting fast logic signals (rise/fall time < 5 ns) to any of
the ADuC7019/20/21/22/24/25/26/27/28/29 digital inputs, add a
series resistor to each relevant line to keep rise and fall times
longer than 5 ns at the part’s input pins. A value of 100 Ω or
200 Ω is usually sufficient to prevent high speed signals from
coupling capacitively into the part and affecting the accuracy
of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7019/20/21/22/24/25/26/27/28/29
can be generated by the internal PLL or by an external clock
input. To use the internal PLL, connect a 32.768 kHz parallel
resonant crystal between XCLKI and XCLKO, and connect a
capacitor from each pin to ground as shown in Figure 92. The
crystal allows the PLL to lock correctly to give a frequency of
41.78 MHz. If no external crystal is present, the internal
oscillator is used to give a typical frequency of 41.78 MHz 3%.
The ADuC7019/20/21/22/24/25/26/27/28/29 can then be
placed between the digital and analog sections, as illustrated in
Figure 91c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
ADuC7026
a.
XCLKI
45
12pF
AGND
DGND
32.768kHz
TO
INTERNAL
PLL
44
12pF
XCLKO
Figure 92. External Parallel Resonant Crystal Connections
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
To use an external source clock input instead of the PLL (see
Figure 93), Bit 1 and Bit 0 of PLLCON must be modified.The
external clock uses P0.7 and XCLK.
COMPONENTS HERE
b.
AGND
DGND
ADuC7026
XCLKO
XCLKI
EXTERNAL
CLOCK
SOURCE
TO
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
FREQUENCY
DIVIDER
c.
XCLK
Figure 93. Connecting an External Clock Source
DGND
Using an external clock source, the ADuC7019/20/21/22/24/
25/26/27/28/29-specified operational clock speed range is
50 kHz to 44 MHz 1%, which ensures correct operation of
the analog peripherals and Flash/EE.
Figure 91. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, the user should pay particular attention to the flow
of current from the supplies and back to ground. Make sure the
return paths for all currents are as close as possible to the paths
the currents took to reach their destinations.
Rev. F | Page 94 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
3.3V
POWER-ON RESET OPERATION
IOV
DD
An internal power-on reset (POR) is implemented on the
ADuC7019/20/21/22/24/25/26/27/28/29. For LVDD below 2.35 V
typical, the internal POR holds the part in reset. As LVDD rises
above 2.35 V, an internal timer times out for, typically, 128 ms
before the part is released from reset. The user must ensure that
the power supply IOVDD reaches a stable 2.7 V minimum level
by this time. Likewise, on power-down, the internal POR holds
the part in reset until LVDD drops below 2.35 V.
2.6V
2.35V TYP
2.35V TYP
LV
DD
128ms TYP
POR
Figure 94 illustrates the operation of the internal POR in detail.
0.12ms TYP
TYPICAL SYSTEM CONFIGURATION
MRST
A typical ADuC7020 configuration is shown in Figure 95. It
summarizes some of the hardware considerations discussed in
the previous sections. The bottom of the CSP package has an
exposed pad that must be soldered to a metal plate on the board
for mechanical reasons. The metal plate of the board can be
connected to ground.
Figure 94. Internal Power-On Reset Operation
+
–
10Ω
0.01µF
RS232 INTERFACE*
0.47µF
AV
DD
STANDARD D-TYPE
SERIAL COMMS
40 39 38 37 36 35 34 33 32 31
DV
DD
ADM3202
CONNECTOR TO
PC HOST
1
2
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
C1+
V
16
CC
1
2
3
4
5
6
7
8
9
V+
GND 15
3
GND
REF
C1–
C2+
C2–
V–
T1
14
13
12
11
10
9
OUT
4
DAC0
R1
IN
5
R1
OUT
ADuC7020
6
XCLKI
T1
T2
IN
IN
7
XCLKO
T2
OUT
8
TMS
TDI
32.768kHz
R2
R2
OUT
IN
9
10
P0.0
1kΩ
DV
DD
11 12 13 14 15 16 17 18 19 20
* EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS
PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.
DV
DD
1kΩ
0.47µF
DV
DD
DV
DD
AV
1
2
3
DD
DV
DD
ADP3333-3.3
TRST
1.5Ω
OUT IN
4
5
6
7
8
9
TDI
270Ω
GND SD
TMS
TCK
10µF
10µF
0.1µF
10
11
12
13
14
15
16
17
18
19
20
TDO
NOT CONNECTED IN THIS EXAMPLE
Figure 95. Typical System Configuration
Rev. F | Page 95 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
DEVELOPMENT TOOLS
PC-BASED TOOLS
Software
•
Integrated development environment, incorporating
assembler, compiler, and nonintrusive JTAG-based
debugger
Serial downloader software
Example code
Four types of development systems are available for the
ADuC7019/20/21/22/24/25/26/27/28/29 family.
•
The ADuC7026 QuickStart Plus is intended for new users
who want to have a comprehensive hardware development
environment. Because the ADuC7026 contains the superset
of functions available on the ADuC7019/20/21/22/24/25/
26/27/28/29, it is suitable for users who wish to develop on
any of the parts in this family. All parts are fully code
compatible.
•
•
Miscellaneous
CD-ROM documentation
IN-CIRCUIT SERIAL DOWNLOADER
The serial downloader is a Windows application that allows the
user to serially download an assembled program to the on-chip
program Flash/EE memory via the serial port on a standard PC.
•
The ADuC7020, ADuC7024, and ADuC7026 QuickStart
systems are intended for users who already have an emulator.
These systems consist of the following PC-based (Windows®
compatible) hardware and software development tools.
The UART-based serial downloader is included in all the
development systems and is usable with the ADuC7019/20/21/
22/24/25/26/27/28/29 parts that do not contain the I suffix in
the Ordering Guide.
An I2C based serial downloader and a USB-to-I2C adaptor
board, USB-EA-CONVZ, are also available at www.analog.com.
The I2C-based serial downloader is only usable with the part
models containing the I suffix (see Ordering Guide).
Hardware
•
•
•
ADuC7019/20/21/22/24/25/26/27/28/29 evaluation board
Serial port programming cable
RDI-compliant JTAG emulator (included in the
ADuC7026 QuickStart Plus only)
Rev. F | Page 96 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
30
40
1
5.85
5.75 SQ
5.65
0.50
BSC
PIN 1
INDICATOR
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTOM VIEW)
10
11
21
20
0.50
0.40
0.30
0.20 MIN
TOP VIEW
4.50 REF
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 96. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
4.25
4.10 SQ
3.95
EXPOSED
PAD
21
20
10
11
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 97. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 x 6 mm Body, Very Very Thin Quad
(CP-40-9)
Dimensions shown in millimeters
Rev. F | Page 97 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
9.10
9.00 SQ
8.90
0.60 MAX
0.60
MAX
PIN 1
INDICATOR
49
48
64
1
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
*
EXPOSED
PAD
0.50
BSC
4.85
4.70 SQ
4.55
0.50
0.40
0.30
33
32
16
17
0.25 MIN
BOTTOM VIEW
7.50 REF
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 98. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm x 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
12.20
12.00 SQ
0.75
11.80
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
PLANE
17
32
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 99. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
Rev. F | Page 98 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
14.20
14.00 SQ
13.80
0.75
0.60
0.45
1.60
MAX
80
61
60
1
PIN
1
12.20
12.00 SQ
11.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
20
41
0.15
0.05
21
40
SEATING
PLANE
0.08
COPLANARITY
VIEW A
0.50
BSC
0.27
0.22
0.17
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BDD
Figure 100. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-1)
Dimensions shown in millimeters
6.10
6.00 SQ
5.90
A1 CORNER
INDEX AREA
8
7
6
5
4
3
2
1
A
B
C
D
E
F
1.50
SQ
BALL A1
4.55 SQ
PAD CORNER
TOP VIEW
0.65
G
H
BOTTOM VIEW
DETAIL A
DETAIL A
*
1.40 MAX
0.65 MIN
0.15 MIN
COPLANARITY
0.10
0.45
0.40
0.35
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-225
WITH THE EXCEPTION TO PACKAGE HEIGHT.
Figure 101. 64-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-64-4)
Dimensions shown in millimeters
Rev. F | Page 99 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
5.05
5.00 SQ
4.95
A1 CORNER
INDEX AREA
7
6
5
4
3
2
1
A
B
C
D
E
F
BALL A1
INDICATOR
3.90
BSC SQ
TOP VIEW
G
BOTTOM
VIEW
0.65
BSC
0.55
BSC
DETAIL A
1.20 MAX
1.00 MAX
0.85 MIN
DETAIL A
0.35
0.20
COPLANARITY
0.05 MAX
0.45
0.40
0.35
SEATING
PLANE
BALL DIAMETER
Figure 102. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-49-1)
Dimensions shown in millimeters
Rev. F | Page 100 of 104
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
ORDERING GUIDE
ADC
DAC
FLASH/
RAM
Down- Temperature
Package
Description
Package Ordering
Model1, 2
Channels3 Channels
GPIO loader
Range
Option
CP-40-1
CP-40-1
CP-40-1
CP-40-9
CP-40-9
CP-40-9
CP-40-9
CP-40-9
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
ST-64-2
ST-64-2
CP-64-1
CP-64-1
CP-64-1
CP-64-1
ST-64-2
ST-64-2
ST-80-1
ST-80-1
ST-80-1
ST-80-1
ST-80-1
ST-80-1
ST-80-1
ST-80-1
BC-64-4
BC-64-4
BC-49-1
BC-49-1
BC-49-1
BC-49-1
Quantity
ADuC7019BCPZ62I
ADuC7019BCPZ62I-RL
ADuC7019BCPZ62IRL7
ADuC7020BCPZ62
ADuC7020BCPZ62-RL7
ADuC7020BCPZ62I
ADuC7020BCPZ62I-RL
ADuC7020BCPZ62IRL7
ADuC7021BCPZ62
ADuC7021BCPZ62-RL
ADuC7021BCPZ62-RL7
ADuC7021BCPZ62I
ADuC7021BCPZ62I-RL
ADuC7021BCPZ32
ADuC7021BCPZ32-RL7
ADuC7022BCPZ62
ADuC7022BCPZ62-RL7
ADuC7022BCPZ32
ADuC7022BCPZ32-RL
ADuC7024BCPZ62
ADuC7024BCPZ62-RL7
ADuC7024BCPZ62I
ADuC7024BCPZ62I-RL
ADuC7024BSTZ62
ADuC7024BSTZ62-RL
ADuC7025BCPZ62
ADuC7025BCPZ62-RL
ADuC7025BCPZ32
ADuC7025BCPZ32-RL
ADuC7025BSTZ62
ADuC7025BSTZ62-RL
ADuC7026BSTZ62
ADuC7026BSTZ62-RL
ADuC7026BSTZ62I
ADuC7026BSTZ62I-RL
ADuC7027BSTZ62
5
5
5
3
3
3
4
4
4
4
4
2
2
2
2
2
2
2
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
32 kB/4 kB
32 kB/4 kB
62 kB/8 kB
62 kB/8 kB
32 kB/4 kB
32 kB/4 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
32 kB/4 kB
32 kB/4 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
14
14
14
14
14
14
14
14
13
13
13
13
13
13
13
13
13
13
13
30
30
30
30
30
30
30
30
30
30
30
30
40
40
40
40
40
40
40
40
30
30
22
22
22
22
I2C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_WQ
40-Lead LFCSP_WQ
40-Lead LFCSP_WQ
40-Lead LFCSP_WQ
40-Lead LFCSP_WQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LQFP
I2C
I2C
2,500
750
5
5
5
UART
UART
I2C
750
5
5
I2C
2,500
750
I2C
8
8
8
8
8
8
8
UART
UART
UART
I2C
2,500
750
I2C
2,500
750
UART
UART
UART
UART
UART
UART
UART
UART
I2C
10
10
10
10
10
10
10
10
10
10
12
12
12
12
12
12
12
12
12
12
16
16
16
16
8
750
2,500
750
2
2
2
2
2
2
I2C
2,500
1,500
2,500
2,500
1,000
1,000
1,000
1,000
1,000
2,500
4,000
4,000
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
I2C
64-Lead LQFP
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LQFP
64-Lead LQFP
4
4
4
4
80-Lead LQFP
80-Lead LQFP
80-Lead LQFP
80-Lead LQFP
I2C
UART
UART
I2C
80-Lead LQFP
80-Lead LQFP
80-Lead LQFP
80-Lead LQFP
ADuC7027BSTZ62-RL
ADuC7027BSTZ62I
ADuC7027BSTZ62I-RL
ADuC7028BBCZ62
ADuC7028BBCZ62-RL
ADuC7029BBCZ62
ADuC7029BBCZ62-RL
ADuC7029BBCZ62I
ADuC7029BBCZ62I-RL
I2C
4
4
4
4
4
4
UART
UART
UART
UART
I2C
64-Ball CSP_BGA
64-Ball CSP_BGA
49-Ball CSP_BGA
49-Ball CSP_BGA
49-Ball CSP_BGA
49-Ball CSP_BGA
8
7
7
7
7
I2C
Rev. F | Page 101 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ADC
DAC
FLASH/
RAM
Down- Temperature
GPIO loader
Range
Package
Description
Package Ordering
Model1, 2
Channels3 Channels
Option
Quantity
EVAL-ADuC7020MKZ
EVAL-ADuC7020QSZ
ADuC7020 MiniKit
ADuC7020 QuickStart
Development System
EVAL-ADuC7020QSPZ
EVAL-ADuC7024QSZ
EVAL-ADuC7026QSZ
EVAL-ADuC7026QSPZ
EVAL-ADuC7028QSZ
EVAL-ADUC7029QSZ
ADuC7020 QuickStart
Development System
ADuC7024 QuickStart
Development System
ADuC7026 QuickStar
Development System
ADuC7026 QuickStart Plus
Development System
ADuC7028 QuickStart
Development System
ADuC7029 QuickStart
Development System
1 Z = RoHS Compliant Part.
2 Models ADuC7026 and ADuC7027 include an external memory interface.
3 One of the ADC channels is internally buffered for ADuC7019 models.
Rev. F | Page 102 of 104
Data Sheet
NOTES
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 103 of 104
ADuC7019/20/21/22/24/25/26/27/28/29
NOTES
I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).
©2005-2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04955-0-5/13(F)
Rev. F | Page 104 of 104
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