EVAL-ADuC7023QSPZ2_技术文档

Precision Analog Microcontroller, 12-Bit Analog

I/O, ARM7TDMI MCU with Enhanced IRQ Handler

Data Sheet

ADuC7023

FEATURES

APPLICATIONS

Analog I/O

Optical networking

Multichannel, 12-bit, 1 MSPS ADC

Up to 12 ADC channels

Fully differential and single-ended modes

0 V to V_REFanalog input range

12-bit voltage output DACs

4 DAC outputs available

On-chip voltage reference

On-chip temperature sensor

Voltage comparator

Microcontroller

Industrial control and automation systems

Smart sensors, precision instrumentation

Base station systems

GENERAL DESCRIPTION

The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data

acquisition system, incorporating high performance multichannel

ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip.

The ADC consists of up to 12 single-ended inputs. An additional four

inputs are available but are multiplexed with the four DAC output

pins. The ADC can operate in single-ended or differential input modes.

The ADC input voltage is 0 V to V_REF. A low drift band gap reference,

temperature sensor, and voltage comparator complete the ADC

peripheral set.

ARM7TDMI core, 16-bit/32-bit RISC architecture

JTAG port supports code download and debug

Clocking options

Trimmed on-chip oscillator ( 3ꢀ%

External watch crystal

External clock source up to 44 MHz

41.78 MHz PLL with programmable divider

Memory

62 kB Flash/EE memory, 8 kB SRAM

In-circuit download, JTAG-based debug

Software-triggered in-circuit reprogrammability

Vectored interrupt controller for FIQ and IRQ

8 priority levels for each interrupt type

Interrupt on edge or level external pin inputs

On-chip peripherals

2× fully I²C-compatible channels

SPI (20 Mbps in master mode, 10 Mbps in slave mode%

With 4-byte FIFO on input and output stages

Up to 20 GPIO pins—Digital only GPIOs are 5 V tolerant

3× general-purpose timers

Watchdog timer (WDT%

Programmable logic array (PLA%

16 PLA elements

The DAC output range is programmable to one of two voltage ranges.

The DAC outputs have an enhanced feature of being able to retain

their output voltage during a watchdog or software reset sequence.

The devices operate from an on-chip oscillator and a PLL,

generating an internal high frequency clock of 41.78 MHz. This

clock is routed through a programmable clock divider from which

the MCU core clock operating frequency is generated. The

microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC

machine that offers up to 41 MIPS peak performance. Eight

kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE

memory are provided on chip. The ARM7TDMI core views all

memory and registers as a single linear array.

The ADuC7023 contains an advanced interrupt controller. The

vectored interrupt controller (VIC) allows every interrupt to be

assigned a priority level. It also supports nested interrupts to a

maximum level of eight per IRQ and FIQ. When IRQ and FIQ

interrupt sources are combined, a total of 16 nested interrupt levels

are supported.

On-chip factory firmware supports in-circuit download via the I²C

serial interface port, and nonintrusive emulation is supported via

the JTAG interface. These features are incorporated into a low cost

QuickStart™ development system supporting this MicroConverter®

family. The part contains a 16-bit PWM with five output signals.

16-bit, 5-channel PWM

Power

Specified for 3 V operation

Active mode: 11 mA at 5 MHz, 28 mA at 41.78 MHz

Packages and temperature range

32-lead 5 mm × 5 mm LFCSP

40-lead LFCSP

For communication purposes, the part contains 2 × I²C channels that

can be individually configured for master or slave mode. An SPI

interface supporting both master and slave modes is also provided.

36-Lead WLCSP

The parts operate from 2.7 V to 3.6 V and are specified over an

industrial temperature range of −40°C to +125°C. e ADuC7023 is

available in either a 32-lead or 40-lead LFCSP package. A 36-ball

wafer level CSP package (WLCSP) is also available.

Fully specified for −40°C to +125°C operation

Tools

Low cost QuickStart development system

Full third-party support

Rev. E

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADuC7023

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Flash/EE Control Interface ....................................................... 38

Execution Time from SRAM and Flash/EE............................ 41

Reset and Remap........................................................................ 41

Other Analog Peripherals.............................................................. 44

DAC.............................................................................................. 44

Power Supply Monitor............................................................... 46

Comparator................................................................................. 46

Oscillator and PLL—Power Control........................................ 48

Digital Peripherals.......................................................................... 51

General-Purpose Input/Output................................................ 51

Serial Peripheral Interface......................................................... 54

I²C..................................................................................................... 59

Configuring External Pins for I²C Functionality................... 59

Serial Clock Generation ............................................................ 59

I²C Bus Addresses....................................................................... 59

I²C Registers................................................................................ 60

Programmable Logic Array (PLA)........................................... 67

Pulse-Width Modulator................................................................. 71

Pulse-Width Modulator General Overview ........................... 71

Processor Reference Peripherals................................................... 76

Interrupt System......................................................................... 76

IRQ ............................................................................................... 76

Fast Interrupt Request (FIQ) .................................................... 77

Vectored Interrupt Controller (VIC)....................................... 78

Timers.......................................................................................... 83

Hardware Design Considerations ................................................... 88

Power Supplies ............................................................................. 88

Grounding and Board Layout Recommendations................. 89

Clock Oscillator.......................................................................... 89

Power-On Reset Operation....................................................... 90

Typical System Configuration .................................................. 91

Development Tools......................................................................... 92

PC-Based Tools........................................................................... 92

In-Circuit I²C Downloader ....................................................... 92

Outline Dimensions....................................................................... 93

Ordering Guide .......................................................................... 95

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Timing Specifications .................................................................. 8

Absolute Maximum Ratings.......................................................... 13

ESD Caution................................................................................ 13

Pin Configurations and Function Descriptions ......................... 14

Typical Performance Characteristics ........................................... 18

Terminology .................................................................................... 19

ADC Specifications .................................................................... 19

DAC Specifications..................................................................... 19

Overview of the ARM7TDMI Core............................................. 20

Thumb Mode (T)........................................................................ 20

Long Multiply (M)...................................................................... 20

EmbeddedICE (I) ....................................................................... 20

Exceptions ................................................................................... 20

ARM Registers ............................................................................ 20

Interrupt Latency........................................................................ 21

Memory Organization ................................................................... 22

Memory Access........................................................................... 22

Flash/EE Memory....................................................................... 22

SRAM........................................................................................... 22

Memory Mapped Registers....................................................... 22

ADC Circuit Overview .................................................................. 29

Transfer Function ....................................................................... 29

Typical Operation ....................................................................... 30

MMR Interface............................................................................ 30

Converter Operation.................................................................. 33

Driving the Analog Inputs ........................................................ 34

Calibration................................................................................... 34

Temperature Sensor ................................................................... 34

Band Gap Reference................................................................... 36

Nonvolatile Flash/EE Memory ..................................................... 37

Programming.............................................................................. 37

Security ........................................................................................ 38

Rev. E | Page 2 of 96

Data Sheet

ADuC7023

REVISION HISTORY

7/13—Rev. D to Rev. E

Changed SPICLK to SCLK in Serial Peripheral Interface Section

and in SCLK (Serial Clock I/O) Pin Section ...............................53

Changes to Table 79 ........................................................................68

Changes to Timers Section ............................................................82

Added Hours, Minutes, Seconds, and 1/128 Format Section and

Table 101...........................................................................................82

Changes to T0LD Register Section and T1LD Register Section.....83

Changes to T2LD Register Section.......................................................85

Updated Outline Dimensions........................................................92

Changes to Ordering Guide...........................................................93

Changes to Ordering Guide...........................................................95

7/13—Rev. C to Rev. D

Added WLCSP (Throughout) .........................................................1

Changes to Features Section ............................................................1

Added Shared Analog/Digital Inputs to AGND Rating of −0.3 V

to AV_DD+ 0.3 V, Endnote 1, and Endnote 2; Table 8..................13

Added Figure 9; Renumbered Sequentially; Added WLCSP Pin

Numbers to Table 9.........................................................................14

Changes to Pin P1.7/PWM3/SDA1/PLAI[6] and Pin

7/10—Rev. A to Rev. B

P1.6/PWM2/SCL1/PLAI[5] Descriptions; Table 9.....................16

Changes to ADC Circuit Overview Section, Transfer Function

Section, and Figure 20 Caption .....................................................29

Changes to Typical Operation Section, ADCCON Register

Section, and ADCON[13] Description in Table 24....................30

Changes to Bits[4:3] Value 10 Description; Table 24..................31

Changes to Converter Operation Section and Deleted Pseudo

Differential Mode Section..............................................................33

Changes to Figure 27 and Figure 28 Caption ..............................34

Changes to Table 30 and Following Text......................................36

Changes to JTAG Access Section ..................................................37

Changes to References to ADC and the DACs Section .............45

Changes to General-Purpose Input/Output Section..................51

Changes to SPIDIV Register Section............................................56

Changes to Bits[1:0] Value 01 Description; Table 66..................61

Changes to T0CLRI Register Section ...........................................84

Changes to Figure 53 ......................................................................90

Updated Outline Dimensions........................................................93

Changes to Ordering Guide...........................................................95

Changes to Temperature Sensor Parameter in Table 1 ................6

Change to Table 10 and changes to Table 11...............................23

Changes to Table 12 and Table 13.................................................24

Changes to Table 16 and Table 17.................................................25

Changes to Table 18 ........................................................................26

Change to Table 21 and changes to Table 22...............................27

Changes to Table 24 ........................................................................29

Changes to ADCGN Register and ADCOF Register Sections .32

Changes to Temperature Sensor Section .....................................34

Changes to Table 29 ........................................................................35

Change to REMAP Register and RSTCLR Register Sections ...41

Change to RSTKEY1 Register and RSTKEY2 Register

Sections.............................................................................................42

Changes to Oscillator and PLL—Power Control Section..........48

Changes to General-Purpose Input/Output Section..................51

Changes to Serial Peripheral Interface Section...........................53

Changes to Table 75 ........................................................................67

Changes to Table 83 and Pulse-Width Modulator General

Overview Section ............................................................................70

Changes to Table 84 ........................................................................71

Change to Table 85..........................................................................72

Change to FIQSTAN Register Section .........................................81

Change to T2CLRI Register Section.............................................85

5/12—Rev. B to Rev. C

Changed SDATA to SDA and SCLK to SCL, Table 2; SDATA to

SDA and SCLK to SCL, Table 3; and SDATA to SDA and SCLK

to SCL, Figure 2 .................................................................................8

Changes to Figure 7, Figure 8, and Table 9..................................14

Changed SCLK to SCL, Table 17...................................................25

Changed SCLK to SCL, Table 18...................................................26

Changes to Bit 6, Table 24 and 4 to 0, Description Column,

Table 25.............................................................................................30

Changed Reference in REFCON Register Section from Table 22

to Table 30 ........................................................................................35

Added Note 1 to Table 53...............................................................49

Changes to Note 1, Table 55...........................................................50

Changed SPICLK (Serial Clock I/O) Pin Section to SCLK

(Serial Clock I/O) Pin Section.......................................................53

6/10—Rev. 0 to Rev. A

Changes to Temperature Sensor Parameter in Table 1 ................6

Changes to Table 24 ........................................................................29

Changes to Temperature Sensor Section .....................................34

Changes to DACBKEY0 Register Section and to Table 43........47

Changes to Ordering Guide...........................................................93

1/10—Revision 0: Initial Version

Rev. E | Page 3 of 96

ADuC7023

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

ADC0

12-BIT

DAC

DAC0

ADuC7023

40-LEAD LFCSP

1MSPS

12-BIT ADC

MUX

12-BIT

DAC

DAC1

DAC2

DAC3

ADC12

TEMP

SENSOR

12-BIT

DAC

ADC2/CMP0

ADC3/CMP1

VECTORED

INTERRUPT

CONTROLLER

12-BIT

DAC

BAND GAP

REF

CMP

OUT

V

REF

ARM7TDMI-BASED MCU WITH

ADDITIONAL PERIPHERALS

OSC

AND PLL

XCLKI

XCLKO

2k × 32 SRAM

31k × 16 FLASH/EEPROM

PLA

GPIO

JTAG

PSM

POR

PWM

3 GENERAL-

PURPOSE TIMERS

RST

2

SPI, 2 × I C

Figure 1.

Rev. E | Page 4 of 96

Data Sheet

ADuC7023

SPECIFICATIONS

AV_DD= IOV_DD= 2.7 V to 3.6 V, V_REF= 2.5 V internal reference, f_CORE= 41.78 MHz, T_A= −40°C to +125°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

ADC Power-Up Time

DC Accuracy^{1, 2}

Eight acquisition clocks and f_ADC/2

5

μs

Resolution

Integral Nonlinearity

12

Bits

LSB

0.6

1.5

2.5 V internal reference

1.0 V external reference

2.5 V internal reference

1.0 V external reference

ADC input is a dc voltage

1.0

0.5

+0.7/−0.6

1

Differential Nonlinearity^{3, 4}

+1/−0.9

DC Code Distribution

ENDPOINT ERRORS⁵

Offset Error

Offset Error Match

Gain Error

1

2

1

2

LSB

Gain Error Match

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel-to-Channel Crosstalk

ANALOG INPUT

f_IN= 10 kHz sine wave, f_SAMPLE= 1 MSPS

69

dB

Includes distortion and noise components

−78

−75

−80

Measured on adjacent channels

Input Voltage Ranges

Differential Mode

Single-Ended Mode

Leakage Current

V_CMV_REF/2⁶

0 to V_REF

6

V

µA

pF

1

20

Input Capacitance

During ADC acquisition

ON-CHIP VOLTAGE REFERENCE

Output Voltage

0.47 µF from V_REFto AGND

2.5

V

Accuracy

4

mV

ppm/°C

dB

Ω

ms

T_A= 25°C

Reference Temperature Coefficient

Power Supply Rejection Ratio

Output Impedance

Internal V_REFPower-On Time

EXTERNAL REFERENCE INPUT

Input Voltage Range

DAC CHANNEL SPECIFICATIONS

DC Accuracy⁷

15

75

51

1

0.625

AV_DD

V

R_L= 5 kΩ, C_L= 100 pF

Resolution

Relative Accuracy

Differential Nonlinearity

Offset Error

Gain Error⁸

12

2

Bits

LSB

mV

%

1

15

1

Guaranteed monotonic

2.5 V internal reference

Gain Error Mismatch

DC Accuracy⁹

0.1

%

% of full scale on DAC0

R_L= 1 kΩ, C_L= 100 pF

Resolution

Relative Accuracy

Differential Nonlinearity

Offset Error

Gain Error¹⁰

12

2.5

1

15

1

Bits

LSB

mV

%

Guaranteed monotonic

2.5 V internal reference

Gain Error Mismatch

ANALOG OUTPUTS

Output Voltage Range 1

Output Voltage Range 2

Output Impedance

0.1

%

% of full scale on DAC0

V_REFrange: AGND to AV_DD

0 to 2.5

0 to AV_DD

2

V

Ω

Rev. E | Page 5 of 96

ADuC7023

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DAC IN OP AMP MODE

DAC Output Buffer in Op Amp Mode

Input Offset Voltage

Input Offset Voltage Drift

Input offset Current

Input Bias Current

Gain

Unity-Gain Frequency

CMRR

Settling Time

0.25

mV

µV/°C

nA

dB

MHz

dB

µs

V/µs

dB

8

0.3

0.4

80

5

80

10

1.5

75

5 kΩ load

R_L= 5 kΩ, C_L= 100 pF

Output Slew Rate

PSRR

DAC AC CHARACTERISTICS

Voltage Output Settling Time

Digital-to-Analog Glitch Energy

10

20

µs

nV-sec

1 LSB change at major carry (where maximum number of

bits simultaneously change in the DACxDAT register)

COMPARATOR

Input Offset Voltage

Input Bias Current

Input Voltage Range

Input Capacitance

Hysteresis^{4, 6}

10

mV

µA

V

pF

mV

1

7

AGND

2

AV_DD– 1.2

15

Hysteresis can be turned on or off via the CMPHYST bit

in the CMPCON register

Response Time

3

µs

100 mV overdrive and configured with CMPRES = 11

Indicates die temperature

TEMPERATURE SENSOR

Voltage Output at 25°C

Voltage TC

1.369

4.42

3

V

mV/°C

°C

Accuracy with No Calibration

Accuracy with One Point Calibration

Using Contents of TEMPREF Register

1.5

°C

θ_JAThermal Impedance

40-Lead LFCSP

32-Lead LFCSP

26

32.5

°C/W

POWER SUPPLY MONITOR (PSM)

IOV_DDTrip Point Selection

Power Supply Trip Point Accuracy

POWER-ON RESET

2.79

2

V

%

V

One trip point

Of the selected nominal trip point voltage

2.41

WATCHDOG TIMER (WDT)

Timeout Period

0

512

sec

FLASH/EE MEMORY

Endurance¹¹

Data Retention¹²

10,000

20

Cycles

Years

T_J= 85°C

DIGITAL INPUTS

Logic 1 Input Current

Logic 0 Input Current

All digital inputs excluding XCLKI and XCLKO

V_IH= V_DDor V_IH= 5 V

V_IL= 0 V; except TDI

V_IL= 0 V; TDI

0.2

−40

−80

10

1

µA

pF

−60

−120

Input Capacitance

LOGIC INPUTS⁴

All logic inputs excluding XCLKI

V_INL, Input Low Voltage

V_INH, Input High Voltage

LOGIC OUTPUTS

0.8

0.4

V

2.0

2.4

All digital outputs excluding XCLKO

I_SOURCE= 1.6 mA

V_OH, Output High Voltage

V_OL, Output Low Voltage¹³

CRYSTAL INPUTS XCLKI AND XCLKO

Logic Inputs, XCLKI Only

V_INL, Input Low Voltage

V_INH, Input High Voltage

XCLKI Input Capacitance

XCLKO Output Capacitance

V

I_SINK= 1.6 mA

1.1

1.7

20

V

pF

20

Rev. E | Page 6 of 96

Data Sheet

ADuC7023

Parameter

Min

Typ

Max

Unit

kHz

%

Test Conditions/Comments

INTERNAL OSCILLATOR

32.768

3

MCU CLOCK RATE

From 32 kHz Internal Oscillator

From 32 kHz External Crystal

Using an External Clock

326

41.78

kHz

CD = 7

CD = 0

T_A= 85°C

T_A= 125°C

Core clock = 41.78 MHz

MHz

0.05

44

41.78

START-UP TIME

At Power-On

From Pause/Nap Mode

66

24

ms

ns

CD = 0

CD = 7

3.07

1.58

1.7

µs

ms

From Sleep Mode

From Stop Mode

PROGRAMMABLE LOGIC ARRAY (PLA)

Pin Propagation Delay

12

2.5

ns

From input pin to output pin

Element Propagation Delay

POWER REQUIREMENTS^{14, 15}

Power Supply Voltage Range

AV_DDto AGND and IOV_DDto DGND

Analog Power Supply Currents

AV_DDCurrent

2.7

3.6

V

200

µA

ADC in idle mode

Digital Power Supply Current

IOV_DDCurrent in Normal Mode

Code executing from Flash/EE

CD = 7

CD = 3

CD = 0 (41.78 MHz clock)

8.5

11

28

14

10

15

35

20

mA

IOV_DDCurrent in Pause Mode

IOV_DDCurrent in Sleep Mode

230

650

µA

T_A= 125°C

Additional Power Supply Currents

ADC

1.4

0.7

400

mA

µA

At 1 MSPS

At 62.5 kSPS

Per DAC

DAC

ESD TESTS

2.5 V reference, T_A= 25°C

HBM Passed

FICDM Passed

3

kV

1.0

¹All ADC channel specifications are guaranteed during normal microcontroller core operation.

²Apply to all ADC input channels.

³Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).

⁴Not production tested but supported by design and/or characterization data on production release.

⁵Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 28. Based on external ADC

system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).

⁶The input signal can be centered on any dc common-mode voltage (V_CM) as long as this value is within the ADC voltage input range specified.

⁷DAC linearity is calculated using a reduced code range of 100 to 3995.

⁸DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V_REF

⁹DAC linearity is calculated using a reduced code range of 100 to 3995.

.

¹⁰DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V_REF

.

¹¹Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

¹²Retention lifetime equivalent at junction temperature (T_J) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.

¹³Test carried out with a maximum of eight I/Os set to a low output level.

¹⁴Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with

3.6 V supply, and sleep mode with 3.6 V supply.

¹⁵IOV_DDpower supply current decreases typically by 2 mA during a Flash/EE erase cycle.

Rev. E | Page 7 of 96

ADuC7023

Data Sheet

TIMING SPECIFICATIONS

Table 2. I²C Timing in Fast Mode (400 kHz)

Slave

Max

Master

Parameter

Description

Min

200

100

300

100

0

100

1.3

Typ

Unit

ns

μs

ns

t_L

t_H

SCL low pulse width

SCL high pulse width

Start condition hold time

Data setup time

Data hold time

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCL and SDA

Fall time for both SCL and SDA

1360

1140

t_SHD

t_DSU

t_DHD

t_RSU

t_PSU

t_BUF

t_R

740

400

800

200

300

t_F

Table 3. I²C Timing in Standard Mode (100 kHz)

Slave

Parameter

Description

Min

Max

Unit

μs

ns

μs

ns

μs

ns

t_L

t_H

SCL low pulse width

SCL high pulse width

Start condition hold time

Data setup time

Data hold time

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCL and SDA

Fall time for both SCL and SDA

4.7

4.0

250

0

4.7

4.0

4.7

t_SHD

t_DSU

t_DHD

t_RSU

t_PSU

t_BUF

t_R

3.45

1

300

t_F

t_BUF

t_SUP

t_R

MSB

t_F

SDA (I/O)

MSB

LSB

ACK

t_DSU

t_DHD

t_RSU

t_PSU

t_R

t_SHD

t_H

1

2–7

8

9

1

SCL (I)

t_L

t_SUP

P

S

S(R)

t_F

STOP

START

REPEATED

START

CONDITION CONDITION

Figure 2. I²C-Compatible Interface Timing

Rev. E | Page 8 of 96

Data Sheet

ADuC7023

Table 4. SPI Master Mode Timing (Phase Mode = 1)

Parameter

Description

Min

Typ

Max

Unit

ns

t_SL

t_SH

SCLK low pulse width¹

SCLK high pulse width¹

Data output valid after SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

(SPIDIV + 1) × t_UCLK

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

25

1 × t_UCLK

2 × t_UCLK

5

12.5

Data output rise time

SCLK rise time

SCLK fall time

t_SF

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLK

(POLARITY = 1)

t_DAV

t_DF

t_DR

MSB

BIT 6 TO BIT 1

LSB

MOSI

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 3. SPI Master Mode Timing (Phase Mode = 1)

Rev. E | Page 9 of 96

ADuC7023

Data Sheet

Table 5. SPI Master Mode Timing (Phase Mode = 0)

Parameter

Description

SCLK low pulse width¹

Min

Typ

Max

Unit

ns

t_SL

t_SH

(SPIDIV + 1) × t_UCLK

SCLK high pulse width¹

Data output valid after SCLK edge

Data output setup before SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

Data output rise time

SCLK rise time

SCLK fall time

t_DAV

t_DOSU

t_DSU

t_DHD

t_DF

t_DR

t_SR

t_SF

25

75

1 × t_UCLK

2 × t_UCLK

5

12.5

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLK

(POLARITY = 1)

t_DAV

t_DOSU

t_DF

t_DR

MSB

BIT 6 TO BIT 1

LSB

MOSI

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 4. SPI Master Mode Timing (Phase Mode = 0)

Rev. E | Page 10 of 96

Data Sheet

ADuC7023

Table 6. SPI Slave Mode Timing (Phase Mode = 1)

Parameter

Description

Min

Typ

Max

Unit

t_SS

SS to SCLK edge

200

ns

t_SL

t_SH

SCLK low pulse width¹

(SPIDIV + 1) × t_UCLK

ns

SCLK high pulse width¹

Data output valid after SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

25

1 × t_UCLK

2 × t_UCLK

5

12.5

Data output rise time

SCLK rise time

SCLK fall time

SS high after SCLK edge

t_SF

t_SFS

0

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

SS

t_SFS

t_SS

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLK

(POLARITY = 1)

t_DAV

t_DF

t_DR

MSB

BIT 6 TO BIT 1

LSB

MOSI

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 5. SPI Slave Mode Timing (Phase Mode = 1)

Rev. E | Page 11 of 96

ADuC7023

Data Sheet

Table 7. SPI Slave Mode Timing (Phase Mode = 0)

Parameter

Description

Min

Typ

Max

Unit

t_SS

SS to SCLK edge

200

ns

t_SL

t_SH

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

t_SF

t_DOCS

t_SFS

SCLK low pulse width¹

(SPIDIV + 1) × t_UCLK

ns

SCLK high pulse width¹

Data output valid after SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

Data output rise time

SCLK rise time

SCLK fall time

Data output valid after SS edge

SS high after SCLK edge

25

1 × t_UCLK

2 × t_UCLK

5

12.5

25

0

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

SS

t_SFS

t_SS

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLK

(POLARITY = 1)

t_DAV

t_DOCS

t_DF

t_DR

MSB

BIT 6 TO BIT 1

LSB

MOSI

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 6. SPI Slave Mode Timing (Phase Mode = 0)

Rev. E | Page 12 of 96

Data Sheet

ADuC7023

ABSOLUTE MAXIMUM RATINGS

AGND = GND_REF, T_A= 25°C, unless otherwise noted.

Table 8.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

AV_DDto IOV_DD

AGND to DGND

−0.3 V to +0.3 V

−0.3 V to +6 V

−0.3 V to +5.3 V

−0.3 V to IOV_DD+ 0.3 V

−0.3 V to AV_DD+ 0.3 V

IOV_DDto DGND, AV_DDto AGND

Digital Input Voltage to DGND¹

Digital Output Voltage to DGND¹

Shared Analog/Digital Inputs to AGND²

V_REFto AGND

Only one absolute maximum rating can be applied at any one time.

Analog Inputs to AGND

Analog Outputs to AGND

ESD CAUTION

Operating Temperature Range, Industrial −40°C to +125°C

Storage Temperature Range

Junction Temperature

−65°C to +150°C

150°C

θ_JAThermal Impedance

40-Lead LFCSP

26°C/W

32-Lead LFCSP

32.5°C/W

Peak Solder Reflow Temperature

SnPb Assemblies (10 sec to 30 sec)

RoHS Compliant Assemblies

(20 sec to 40 sec)

240°C

260°C

¹These limits apply to the P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, P0.7, P1.0,

P1.1, P1.6, and P1.7 pins.

²These limits apply to the P1.2, P1.3, P1.4, P1.5, P2.0, P2.2, P2.3, and P2.4 pins.

Rev. E | Page 13 of 96

ADuC7023

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AV

P0.3/PLAO[9]/TCK

P0.2/PLAO[8]/TDI

1

2

3

4

5

6

7

8

24

23

DD

P2.2/ADC7/SYNC/PLAO[6]

AV

DD

REF

DAC0

DAC1

DAC2

1

30

29

GND

REF

GND

P1.5/ADC6/PWM

/PLAO[4]

2

3

4

5

6

7

8

9

10

TRIPINPUT

DAC0

DAC1

DAC2

DAC3

22 P0.1/PLAI[9]/TDO

P0.0/nTRST/ADC

28 P0.3/PLAO[9]/TCK

27 P0.2/PLAO[8]/TDI

ADuC7023

TOP VIEW

(Not to Scale)

/PLAI[8]/BM

21

20 TMS

BUSY

ADuC7023

TOP VIEW

(Not to Scale)

26

P0.1/PLAI[9]/TDO

25 P0.0/nTRST/ADC

24 TMS

PLAI[8]/BM

DAC3

BUSY

RTCK

XCLKO

17 XCLKI

19

18

P1.4/ADC10/PLAO[3]

P2.0/ADC12/PWM4/PLAI[7]

P0.4/IRQ0/SCL0/PLAI[0]/CONV

START

23 RTCK

22 XCLKO

21 XCLKI

P0.5/SDA0/PLAI[1]/COMP

P0.4/IRQ0/SCL0/PLAI[0]/CONV

OUT

START

P0.5/SDA0/PLAI[1]/COMP

OUT

NOTES

1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND

EITHER CONNECTED TO AGND OR LEFT FLOATING.

1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND

EITHER CONNECTED TO AGND OR LEFT FLOATING.

Figure 8. 32-Lead LFCSP Pin Configuration

Figure 7. 40-Lead LFCSP Pin Configuration

BALL A1

CORNER

1

2

3

4

5

6

A

B

C

D

A1

B1

C1

D1

A2

B2

C2

D2

A3

A4

A5

A6

B3

C3

D3

B4

C4

D4

B5

C5

D5

B6

C6

D6

E

F

E1

F1

E2

F2

E3

F3

E4

F4

E5

F5

E6

F6

ADuC7023

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 9. 36-Lead WLCSP Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

40-

32-

36-

LFCSP LFCSP WLCSP Mnemonic

Description

0

N/A

Exposed Paddle

Exposed Pad. The paddle needs to be soldered and either connected to

AGND or left floating.

36

37

38

39

32

28

29

30

31

A4

B4

A5

B5

B2

ADC0

ADC1

ADC2/CMP0

ADC3/CMP1

P2.4/ADC9/PLAI[10]

Single-Ended or Differential Analog Input 0.

Single-Ended or Differential Analog Input 1.

Single-Ended or Differential Analog Input 2/Comparator Positive Input.

Single-Ended or Differential Analog Input 3/Comparator Negative Input.

General-Purpose Input and Output Port 2.4/ADC Single-Ended or Dif-

ferential Analog Input/Programmable Logic Array Input Element 10.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled.

N/A

Rev. E | Page 14 of 96

Data Sheet

ADuC7023

Pin No.

40-

LFCSP LFCSP WLCSP Mnemonic

32-

36-

Description

31

30

8

N/A

A1

B1

E6

P2.3/ADC8/PLAO[7]

General-Purpose Input and Output Port 2.3/ADC Single-Ended or

Differential Analog Input 8/Programmable Logic Array Output Element 7.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, pull-up resistor should be

disabled manually.

General-Purpose Input and Output Port 2.2/ADC Single-Ended or

Differential Analog Input 7/PWM Sync/Programmable Logic Array Output

Element 6. By default, this pin is configured as a digital input with a weak

pull-up resistor enabled. When used as ADC input, pull-up resistor should

be disabled manually.

General-Purpose Input and Output Port 2.0/ADC Single-Ended or

Differential Analog Input 12/PWM Output 4/Programmable Logic Array Input

Element 7. By default, this pin is configured as a digital input with a weak pull-

up resistor enabled. When used as an ADC input, it is not possible to

disable the internal pull-up resister. This means that this pin has a higher

leakage current value than other analog input pins.

P2.2/ADC7/SYNC/PLAO[6]

P2.0/ADC12/PWM4/PLAI[7]

2

C4

GND_REF

Ground Voltage Reference for the ADC. For optimal performance, the

analog power supply should be separated from DGND.

3

4

5

6

3

4

5

6

C5

C6

D5

D6

D2

DAC0

DAC1

DAC2

DAC3

TMS

DAC0 Voltage Output or ADC Input.

DAC1 Voltage Output or ADC Input.

DAC2 Voltage Output

DAC3 Voltage Output

24

20

Test Mode Select, JTAG Test Port Input. Debug and download access.

This pin has an internal pull-up resistor to IOV_DD. In some cases an external

pull-up resistor is also required to ensure the part does not enter an

erroneous state.

25

21

D1

P0.0/nTRST/ADC_BUSY/PLAI[8]/BM This is a multifunction pin as follows:

General-Purpose Input and Output Port 0.0. By default, this pin is

configured as GPIO.

JTAG Reset Input. Debug and download access. If this pin is held low, JTAG

access is not possible because the JTAG interface is held in reset and

P0.1/P0.2/P0.3 are configured as GPIO pins.

ADC Busy Signal.

Programmable Logic Array Input Element 8.

Boot Mode Entry Pin. The ADuC7023 enters I²C download mode if BM is

low at reset with a flash address 0x80014 = 0xFFFFFFFFF. The ADuC7023

executes code if BM is pulled high at reset or if BM is low at reset with a

flash address 0x80014 not equal to 0xFFFFFFFFF.

26

22

C1

P0.1/PLAI[9]/TDO

The default value of this pin depends on the level of P0.0/BM. If P0.0/

BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this

pin defaults to a JTAG test data output pin. This is a multifunction pin as

follows:

General-Purpose Input and Output Port 0.1.

Programmable Logic Array Input Element 9.

Test Data Out, JTAG Test Port Output. Debug and download access. When

debugging the part via JTAG, this pin must not be toggled by user code,

and the GP0CON/GP0DAT register bits affecting this pin can not be

changed.

27

23

C2

P0.2/PLAO[8]/TDI

The default value of this pin depends on the level of P0.0/BM. If P0.0/

BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin

defaults to a JTAG test data input pin. This is a multifunction pin as follows:

General-Purpose Input and Output Port 0.2.

Programmable Logic Array Output Element 8.

Test Data In, JTAG Test Port Input. Debug and download access. When

debugging the part via JTAG, this pin must not be toggled by user code,

and the GP0CON/GP0DAT register bits affecting this pin must not be

changed.

Rev. E | Page 15 of 96

ADuC7023

Data Sheet

Pin No.

40-

LFCSP LFCSP WLCSP Mnemonic

32-

36-

Description

28

24

C3

P0.3/PLAO[9]/TCK

The default value of this pin depends on the level of P0.0/BM. If P0.0/BM =

0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin

defaults to a JTAG test data clock pin. This is a multifunction pin as follows:

General-Purpose Input and Output Port 0.3.

Programmable Logic Array Output Element 9.

Test Clock, JTAG Test Port Clock Input. Debug and download access. When

debugging the part via JTAG, this pin must not be toggled by user code

and the GP0CON/GP0DAT register bits affecting this pin must not be

changed.

17

18

19

13

14

15

E3

F3

D3

DGND

IOV_DD

LV_DD

Digital Ground.

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

2.6 V Output of the On-Chip Voltage Regulator. This output must be

connected to a 0.47 µF capacitor to DGND only.

20

23

16

19

F2

E1

RST

Reset Input, Active Low.

RTCK

Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is

an output signal from the JTAG controller. If using a 20-lead JTAG header,

connect to Pin 11.

9

7

F6

P0.4/IRQ0/SCL0/PLAI[0]/CONV

General-Purpose Input and Output Port 0.4/External Interrupt Request 0/ I²C0

Clock Signal/Programmable Logic Array Input Element 0/ADC External

Convert Start. By default, this pin is configured as a digital input with a

weak pull-up resistor enabled.

10

11

8

9

E5

F5

P0.5/SDA0/PLAI[1]/COMP_OUT

P0.6/MISO/SCL1/PLAI[2]

General-Purpose Input and Output Port 0.5/I²C0 Data Signal/ Programmable

Logic Array Input Element 1/Voltage Comparator Output. By default, this

pin is configured as a digital input with a weak pull-up resistor enabled.

General-Purpose Input and Output Port 0.6/SPI MISO Signal/I²C1 Clock On

32-Lead and 36-Ball Packages/Programmable Logic Array Input Element 2.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled.

12

10

D4

P0.7/MOSI/SDA1/PLAO[0]

General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I²C1 Data

Signal On 32-Lead and 36-Ball Packages/Programmable Logic Array Output

Element 0.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled.

21

17

F1

XCLKI

Input to the Crystal Oscillator Inverter and Input to the Internal Clock

Generator Circuits. Connect to DGND if unused.

22

16

18

N/A

E2

N/A

XCLKO

P1.7/PWM3/SDA1/PLAI[6]

Output from the Crystal Oscillator Inverter. Leave unconnected if unused.

General-Purpose Input and Output Port 1.7/PWM Output 3/I²C1 Data

Signal/Programmable Logic Array Input Element 6. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

15

29

N/A

P1.6/PWM2/SCL1/PLAI[5]

General-Purpose Input and Output Port 1.6/PWM Output 2/I²C1 Clock

Signal/Programmable Logic Array Input Element 5. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

General-Purpose Input and Output Port 1.5/ADC Single-Ended or

Differential Analog Input 6/PWM_TRIPINPUT/Programmable Logic Array Output

Element 4. By default, this pin is configured as a digital input with a weak

pull-up resistor enabled. When used as ADC input, the pull-up resistor

should be disabled manually.

P1.5/ADC6/PWM_TRIPINPUT/PLAO[4]

7

N/A

P1.4/ADC10/PLAO[3]

General-Purpose Input and Output Port 1.4/ADC Single-Ended or Dif-

ferential Analog Input 10/Programmable Logic Array Output Element 3.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, the pull-up resistor should be

disabled manually.

Rev. E | Page 16 of 96

Data Sheet

ADuC7023

Pin No.

40-

LFCSP LFCSP WLCSP Mnemonic

32-

36-

Description

34

26

A3

P1.3/ADC5/IRQ3/PLAI[4]

General-Purpose Input and Output Port 1.3/ADC Single-Ended or

Differential Analog Input 5/External Interrupt Request 3/ Programmable

Logic Array Input Element 4.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, the pull-up resistor should be

disabled manually.

33

25

A2

P1.2/ADC4/IRQ2/PLAI[3]/ECLK/

General-Purpose Input and Output Port 1.2/ADC Single-Ended or

Differential Analog Input 4/External Interrupt Request 2/ Programmable

Logic Array Input Element 3/Input-Output for External Clock.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, the pull-up resistor should be

disabled manually.

14

13

35

12

11

27

F4

E4

B3

P1.1/SS/IRQ1/PWM1/PLAO[2]/T1 General-Purpose Input and Output Port 1.1/SPI Interface Slave Select

(Active Low)/External Interrupt Request 1/PWM Output 1/ Programmable

Logic Array Output Element 2/Timer 1 Input Clock. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

P1.0/SCLK/PWM0/PLAO[1]

General-Purpose Input and Output Port 1.0/SPI Interface Clock Signal/

PWM Output 0/Programmable Logic Array Output Element 1. By default,

this pin is configured as a digital input with a weak pull-up resistor

enabled.

V_REF

2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor

when using the internal reference.

40

1

32

1

A6

B6

AGND

AV_DD

Analog Ground. Ground reference point for the analog circuitry.

3.3 V Analog Power.

Rev. E | Page 17 of 96

ADuC7023

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.2

1.0

0.8

0.6

0.5

0.4

0.3

0.2

0.6

0.4

0.2

0

0.1

0

–0.2

–0.4

–0.1

–0.2

–0.3

–0.4

–0.6

–0.8

–1.0

0

500

1000 1500

ADC CODES

SAMPLING RATE = 950kSPS

2000 2500 3000 3500

4095

0

500

1000 1500

2000 2500 3000 3500

4095

ADC CODES

SAMPLING RATE = 950kSPS

WORST CASE POSITIVE = 1.09, CODE = 4032

WORST CASE NEGATIVE = –0.98, CODE = 3422

WORST CASE POSITIVE = 0.63, CODE = 2364

WORST CASE NEGATIVE = –0.46, CODE = 2363

Figure 10. Typical DNL, f_ADC= 950 kSPS, Internal Reference Used

Figure 13. Typical INL, f_ADC= 950 kSPS, External 1.0 V Reference Used

0.6

20

0.4

0.2

0

–20

–40

–60

0

–0.2

–0.4

–0.6

–80

–100

–200

–400

–0.8

–1.0

0

500

1000 1500

ADC CODES

SAMPLING RATE = 950kSPS

2000 2500 3000 3500

4095

0

20,000

40,000

60,000

80,000

104,400

FREQUENCY (Hz)

WORST CASE POSITIVE = 0.57, CODE = 4063

WORST CASE NEGATIVE = –0.90, CODE = 3356

Figure 11. Typical INL, f_ADC= 950 kSPS, Internal Reference Used

Figure 14. SINAD, THD, and PHSN of ADC , Internal 2.5 V Reference Used

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

0

500

1000 1500

ADC CODES

SAMPLING RATE = 950kSPS

2000 2500 3000 3500

4095

WORST CASE POSITIVE = 0.64, CODE = 3583

WORST CASE NEGATIVE = –0.61, CODE = 1830

Figure 12. Typical DNL, f_ADC= 950 kSPS, External 1.0 V Reference Used

Rev. E | Page 18 of 96

Data Sheet

ADuC7023

TERMINOLOGY

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the

quantization noise.

ADC SPECIFICATIONS

Integral Nonlinearity (INL)

The maximum deviation of any code from a straight line

passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a point

½ LSB below the first code transition, and full scale, a point

½ LSB above the last code transition.

The theoretical signal to (noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Total Harmonic Distortion

The ratio of the rms sum of the harmonics to the fundamental.

DAC SPECIFICATIONS

Offset Error

The deviation of the first code transition (0000 . . . 000) to

(0000 . . . 001) from the ideal, that is, +½ LSB.

Relative Accuracy

Otherwise known as endpoint linearity, relative accuracy is a

measure of the maximum deviation from a straight line passing

through the endpoints of the DAC transfer function. It is

measured after adjusting for zero error and full-scale error.

Gain Error

The deviation of the last code transition from the ideal AIN

voltage (full scale − 1.5 LSB) after the offset error has been

adjusted out.

Voltage Output Settling Time

The amount of time it takes the output to settle to within a

1 LSB level for a full-scale input change.

Signal to (Noise + Distortion) Ratio

The measured ratio of signal to (noise + distortion) at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

Rev. E | Page 19 of 96

ADuC7023

Data Sheet

OVERVIEW OF THE ARM7TDMI CORE

The ARM7® core is a 32-bit reduced instruction set computer

(RISC). It uses a single 32-bit bus for instruction and data. The

length of the data can be 8 bits, 16 bits, or 32 bits. The length of

the instruction word is 32 bits.

EXCEPTIONS

ARM supports five types of exceptions and a privileged

processing mode for each type. The five types of exceptions are:

•

Normal interrupt or IRQ. This is provided to service

general-purpose interrupt handling of internal and

external events.

The ARM7TDMI is an ARM7 core with four additional features: T

support for the thumb (16-bit) instruction set, D support for

debug, M support for long multiplications, and I includes the

EmbeddedICE module to support embedded system debugging

•

Fast interrupt or FIQ. This is provided to service data

transfers or communication channels with low latency. FIQ

has priority over IRQ.

THUMB MODE (T)

•

Memory abort.

An ARM instruction is 32 bits long. The ARM7TDMI

processor supports a second instruction set that has been

compressed into 16 bits, called the Thumb® instruction set.

Faster execution from 16-bit memory and greater code density

can usually be achieved by using the Thumb instruction set

instead of the ARM instruction set, which makes the

ARM7TDMI core particularly suitable for embedded

applications.

Attempted execution of an undefined instruction.

Software interrupt instruction (SWI). This can be used to

make a call to an operating system.

Typically, the programmer defines interrupt as IRQ, but for

higher priority interrupt, that is, faster response time, the

programmer can define interrupt as FIQ.

ARM REGISTERS

However, the Thumb mode has two limitations. Thumb code

typically requires more instructions for the same job. As a

result, ARM code is usually best for maximizing the

performance of time critical code. Also, the Thumb instruction

set does not include some of the instructions needed for

exception handling, which automatically switches the core to

ARM code for exception handling.

ARM7TDMI has a total of 37 registers: 31 general-purpose

registers and six status registers. Each operating mode has

dedicated banked registers.

When writing user-level programs, 15 general-purpose 32-bit

registers (R0 to R14), the program counter (R15), and the

current program status register (CPSR) are usable. The

remaining registers are only used for system-level programming

and exception handling.

See the ARM7TDMI user guide for details on the core

architecture, the programming model, and both the ARM

and ARM Thumb instruction sets.

When an exception occurs, some of the standard registers are

replaced with registers specific to the exception mode. All excep-

tion modes have replacement banked registers for the stack

pointer (R13) and the link register (R14) as represented in

Figure 15. The fast interrupt mode has more registers (R8 to R12)

for fast interrupt processing. This means the interrupt processing

can begin without the need to save or restore these registers,

and thus save critical time in the interrupt handling process.

LONG MULTIPLY (M)

The ARM7TDMI instruction set includes four extra instruc-

tions that perform 32-bit by 32-bit multiplication with a 64-bit

result, and 32-bit by 32-bit multiplication-accumulation (MAC)

with a 64-bit result. These results are achieved in fewer cycles

than required on a standard ARM7 core.

EmbeddedICE (I)

R0

USABLE IN USER MODE

R1

EmbeddedICE provides integrated on-chip support for the core.

The EmbeddedICE module contains the breakpoint and watch-

point registers that allow code to be halted for debugging purposes.

These registers are controlled through the JTAG test port.

SYSTEM MODES ONLY

R2

R3

R4

R5

R6

R7

When a breakpoint or watchpoint is encountered, the processor

halts and enters debug state. Once in a debug state, the

processor registers can be inspected as well as the Flash/EE,

SRAM, and memory mapped registers.

R8_FIQ

R9_FIQ

R8

R9

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

R10

R11

R12

R13

R14

R15 (PC)

R13_UND

R13_IRQ

R13_ABT

R14_ABT

R14_UND

R14_IRQ

R13_SVC

R14_SVC

SPSR_UND

SPSR_IRQ

SPSR_ABT

SPSR_SVC

CPSR

SPSR_FIQ

FIQ

MODE

SVC

MODE

ABORT

MODE

IRQ

MODE

UNDEFINED

MODE

USER MODE

Figure 15. Register Organization

Rev. E | Page 20 of 96

Data Sheet

ADuC7023

More information relative to the model of the programmer and

the ARM7TDMI core architecture can be found in ARM7TDMI

technical and ARM architecture manuals available directly from

ARM Ltd.

The maximum interrupt request (IRQ) latency calculation is

similar but must allow for the fact that FIQ has higher priority

and could delay entry into the IRQ handling routine for an

arbitrary length of time. This time can be reduced to 42 cycles if

the LDM command is not used. Some compilers have an option

to compile without using this command. Another option is to run

the part in thumb mode where the time is reduced to 22 cycles.

INTERRUPT LATENCY

The worst-case latency for a fast interrupt request (FIQ)

consists of the following: the longest time the request can take

to pass through the synchronizer, the time for the longest

instruction to complete (the longest instruction is an LDM) that

loads all the registers including the PC, and the time for the

data abort and FIQ entry.

The minimum latency for FIQ or IRQ interrupts is a total of

five cycles, which consist of the shortest time the request can

take through the synchronizer, plus the time to enter the

exception mode.

The ARM7TDMI always runs in ARM (32-bit) mode when in

privileged modes, for example, when executing interrupt

service routines.

At the end of this time, the ARM7TDMI executes the instruc-

tion at 0x1C (FIQ interrupt vector address). The maximum

total time is 50 processor cycles, which is just under 1.2 µs in a

system using a continuous 41.78 MHz processor clock.

Rev. E | Page 21 of 96

ADuC7023

Data Sheet

MEMORY ORGANIZATION

The ADuC7023 incorporates two separate blocks of memory:

8 kB of SRAM and 64 kB of on-chip Flash/EE memory; 62 kB of

on-chip Flash/EE memory is available to the user, and the

remaining 2 kB are reserved for the factory configured boot

page. These two blocks are mapped as shown in Figure 16.

FLASH/EE MEMORY

The total 64 kB of Flash/EE memory is organized as 32k × 16 bits;

31k × 16 bits is user space and 1 k × 16 bits is reserved for the

on-chip kernel. The page size of this Flash/EE memory is 512 bytes.

62 kilobytes of Flash/EE memory are available to the user as

code and nonvolatile data memory. There is no distinction

between data and program because ARM code shares the same

space. The real width of the Flash/EE memory is 16 bits, which

means that in ARM mode (32-bit instruction), two accesses to

the Flash/EE are necessary for each instruction fetch. It is,

therefore, recommended to use Thumb mode when executing

from Flash/EE memory for optimum access speed. The

maximum access speed for the Flash/EE memory is 41.78 MHz

in Thumb mode and 20.89 MHz in full ARM mode. More

details about Flash/EE access time are outlined later in the

Execution Time from SRAM and Flash/EE section.

0xFFFFFFFF

0xFFFF0000

MMRs

RESERVED

0x0008FFFF

FLASH/EE

0x00080000

SRAM

RESERVED

Eight kilobytes of SRAM are available to the user, organized as

2k × 32 bits, that is, two words. ARM code can run directly from

SRAM at 41.78 MHz, given that the SRAM array is configured

as a 32-bit wide memory array. More details about SRAM access

time are outlined later in the Execution Time from SRAM and

Flash/EE section.

0x00011FFF

SRAM

0x00010000

0x0000FFFF REMAPPABLE MEMORY SPACE

0x00000000

(FLASH/EE OR SRAM)

Figure 16. Physical Memory Map

By default, after a reset, the Flash/EE memory is mirrored at

Address 0x00000000. It is possible to remap the SRAM at

Address 0x00000000 by clearing Bit 0 of the Remap MMR.

This remap function is described in more detail in the Flash/EE

Memory section.

MEMORY MAPPED REGISTERS

The memory mapped register (MMR) space is mapped into the

upper two pages of the memory array and accessed by indirect

addressing through the ARM7 banked registers.

MEMORY ACCESS

The MMR space provides an interface between the CPU and

all on-chip peripherals. All registers, except the core registers,

reside in the MMR area. All shaded locations shown in Figure 18

are unoccupied or reserved locations and should not be

accessed by user software. Table 10 to Table 23 show the full

MMR memory map.

The ARM7 core sees memory as a linear array of the 2³²byte

location where the different blocks of memory are mapped as

outlined in Figure 16.

The ADuC7023 memory organizations are configured in little

endian format, which means that the least significant byte is

located in the lowest byte address, and the most significant byte

is in the highest byte address.

The access time for reading from or writing to an MMR depends

on the advanced microcontroller bus architecture (AMBA) bus

used to access the peripheral. The processor has two AMBA

buses: advanced high performance bus (AHB) used for system

modules and advanced peripheral bus (APB) used for lower

performance peripheral. Access to the AHB is one cycle, and

access to the APB is two cycles. All peripherals on the ADuC7023

are on the APB except the Flash/EE memory and the GPIOs.

BIT 31

BIT 0

BYTE 3 BYTE 2 BYTE 1 BYTE 0

.

0xFFFFFFFF

B

7

3

A

6

2

9

5

1

8

4

0

0x00000004

0x00000000

32 BITS

Figure 17. Little Endian Format

Rev. E | Page 22 of 96

Data Sheet

ADuC7023

0xFFFFFFFF

0xFFFFF820

FLASH CONTROL

INTERFACE

0xFFFFF800

0xFFFFF46C

GPIO

PWM

PLA

SPI

0xFFFFF400

0xFFFF0FBF

0xFFFF0F80

0xFFFF0B54

0xFFFF0B00

0xFFFF0A14

0xFFFF0A00

0xFFFF0948

2

I C1

0xFFFF0900

0xFFFF0848

2

I C0

0xFFFF0800

0xFFFF0620

0xFFFF0600

0xFFFF0538

0xFFFF0500

0xFFFF0490

0xFFFF048C

0xFFFF0448

0xFFFF0440

0xFFFF0420

0xFFFF0404

0xFFFF0370

DAC

ADC

BAND GAP

REFERENCE

POWER SUPPLY

MONITOR

PLL AND

OSCILLATOR CONTROL

WATCHDOG

TIMER

0xFFFF0360

0xFFFF0334

GENERAL-PURPOSE

TIMER

0xFFFF0320

0xFFFF0310

0xFFFF0300

0xFFFF0238

0xFFFF0220

0xFFFF0140

0xFFFF0000

TIMER0

REMAP AND

SYSTEM CONTROL

INTERRUPT

CONTROLLER

Figure 18. Memory Mapped Registers

Rev. E | Page 23 of 96

ADuC7023

Data Sheet

Table 10. IRQ Address Base = 0xFFFF0000

Address Name

Byte Access Type Default Value

Description

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

IRQSTA

IRQSIG

IRQEN

IRQCLR

SWICFG

IRQBASE

4

R

R/W

W

0x00000000

Active IRQ source.

Current state of all IRQ sources (enabled and disabled).

Enabled IRQ sources.

MMR to disable IRQ sources.

Software interrupt configuration MMR.

Base address of all vectors. Points to start of a 64-byte memory block

which can contain up to 32 pointers to separate subroutine handlers.

This register contains the subroutine address for the currently active IRQ

source.

This register contains the interrupt priority setting for Interrupt Source 1

to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7.

This register contains the interrupt priority setting for Interrupt Source 8

to Interrupt Source 15.

This register contains the interrupt priority setting for Interrupt Source 16 to

Interrupt Source 21.

0x00000000

R/W

0x00000000

0x001C

0x0020

0x0024

0x0028

0x002C

IRQVEC

IRQP0

IRQP1

IRQP2

4

R

R/W

RESERVE

D

Reserved.

0x0030

0x0034

IRQCONN

IRQCONE

4

R/W

0x00000000

Used to enable IRQ and FIQ interrupt nesting.

This register configures the external interrupt sources as rising edge,

falling edge, or level triggered.

0x0038

0x003C

IRQCLRE

IRQSTAN

4

R/W

0x00000000

Used to clear an edge level triggered interrupt source.

This register indicates the priority level of an interrupt that has just

caused an interrupt exception.

0x0100

0x0104

0x0108

0x010C

0x011C

0x013C

FIQSTA

FIQSIG

FIQEN

FIQCLR

FIQVEC

FIQSTAN

4

R

R/W

W

R

0x00000000

Active FIQ source.

Current state of all FIQ sources (enabled and disabled).

Enabled FIQ sources.

MMR to disable FIQ sources.

FIQ interrupt vector.

This register indicates the priority level of an FIQ that has just caused an

FIQ exception.

0x00000000

RW

Table 11. System Control Address Base = 0xFFFF0200

Address Name

Byte Access Type Default Value¹

Description

0x0220

0x0230

0x0234

0x0248

0x024C

Remap²

RSTSTA

RSTCLR

RSTKEY1

RSTCFG

1

R/W

W

R/W

0x00

0x01

0x00

0xXX

0x00

Remap control register.

RSTSTA status MMR.

RSTCLR MMR for clearing RSTSTA register.

0x76 should be written to this register before writing to RSTCFG.

This register allows the DAC and GPIO outputs to retain state after a

watchdog or software reset.

0x0250

RSTKEY2

1

W

0xXX

0xB1 should be written to this register after writing to RSTCFG.

¹N/A means not applicable.

²Updated by kernel.

Rev. E | Page 24 of 96

Data Sheet

ADuC7023

Table 12. Timer Address Base = 0xFFFF0300

Address Name

Byte Access Type

Default Value¹

0x0000

0xFFFF

0x0000

Description

0x0300

0x0304

0x0308

0x030C

0x0320

0x0324

0x0328

0x032C

0x0330

0x0360

0x0364

0x0368

0x036C

T0LD

2

1

4

1

4

2

1

R/W

R

R/W

W

R/W

R

R/W

W

R

R/W

R

R/W

W

Timer0 load register.

T0VAL

T0CON

T0CLRI

T1LD

T1VAL

T1CON

T1CLRI

T1CAP

T2LD

Timer0 value register.

Timer0 control MMR.

Timer0 interrupt clear register.

Timer1 load register.

Timer1 value register

Timer1 control MMR.

Timer1 interrupt clear register.

Timer1 capture register.

Timer2 load register.

0xXX

0x00000000

0xFFFFFFFF

0x00000000

0xXX

0x00000000

0x0000

0xFFFF

0x0000

0xXX

T2VAL

T2CON

T2CLRI

Timer2 value register.

Timer2 control MMR.

Timer2 interrupt clear register.

¹N/A means not applicable.

Table 13. PLL/PSM Base Address = 0xFFFF0400

Address Name

Byte Access Type Default Value¹

Description

0x0404

0x0408

0x040C

0x0410

0x0414

0x0418

0x0434

0x0438

0x043C

0x0440

0x0444

POWKEY1

2

1

2

1

2

W

R/W

W

R/W

W

R/W

W

R/W

0xXXXX

0x00

0xXXXX

0x21

0xXXXX

0x0004

0xXXXX

0x0008

0x0000

POWCON0 prewrite key.

Power control and core speed control register.

POWCON0 postwrite key.

PLLCON prewrite key.

PLL clock source selection MMR.

PLLCON postwrite key.

POWCON1 prewrite key.

Power control and core speed control register.

POWCON1 postwrite key.

Power supply monitor control register.

Comparator control register.

POWCON0

POWKEY2

PLLKEY1

PLLCON

PLLKEY2

POWKEY3

POWCON1

POWKEY4

PSMCON

CMPCON

¹N/A means not applicable.

Table 14. Reference Base Address = 0xFFFF0480

Address:

0x048c

Name:

REFCON

Byte:

1

Access type:

Default value:

Description:

Read/write

0x00

Reference control register.

Table 15. ADC Address Base = 0xFFFF0500

Address Name Byte Access Type Default Value

Description

0x0500

0x0504

0x0508

0x050C

0x0510

0x0514

ADCCON

ADCCP

ADCCN

ADCSTA

ADCDAT

ADCRST

2

1

4

1

R/W

R

R/W

0x0600

0x00

0x01

0x00

0x00000000

0x00

ADC control MMR.

ADC positive channel selection register.

ADC negative channel selection register.

ADC status MMR.

ADC data output MMR.

ADC reset MMR.

Rev. E | Page 25 of 96

ADuC7023

Data Sheet

Address Name

Byte Access Type Default Value

Description

0x0530

0x0534

0x0544

0x0548

ADCGN

ADCOF

TSCON

2

1

2

R/W

Factory configured

0x00

ADC gain calibration MMR.

ADC offset calibration MMR.

Temperature sensor chopping enable register.

Temperature sensor reference value.

TEMPREF

Factory configured

Table 16. DAC Address Base = 0xFFFF0600

Address Name Byte Access Type Default Value

Description

0x0600

0x0604

0x0608

0x060C

0x0610

0x0614

0x0618

0x061C

0x0654

0x0650

0x0658

DAC0CON

1

4

1

4

1

4

1

4

1

2

R/W

W

0x00

0x00000000

0x00

0x00000000

0x00

0x00000000

0x00

0x00000000

0x00

0x0000

DAC0 control MMR.

DAC0 data MMR.

DAC1 control MMR.

DAC1 data MMR.

DAC2 control MMR.

DAC2 data MMR.

DAC3 control MMR.

DAC3 data MMR.

DAC Configuration MMR

DAC Key0 MMR

DAC0DAT

DAC1CON

DAC1DAT

DAC2CON

DAC2DAT

DAC3CON

DAC3DAT

DACBCFG

DACBKEY0

DACBKEY1

W

DAC Key1 MMR

Table 17. I²C0 Base Address = 0XFFFF0800

Address Name Byte Access Type Default Value

Description

0x0800

0x0804

0x0808

0x080C

0x0810

I2C0MCON

I2C0MSTA

I2C0MRX

I2C0MTX

I2C0MCNT0

2

1

2

R/W

R

W

R/W

0x0000

0x00

0x0000

I²C0 master control register.

I²C0 master status register.

I²C0 master receive register.

I²C0 master transmit register.

I²C0 master read count register. Write the number of required

bytes into this register prior to reading from a slave device.

0x0814

0x0818

0x081C

I2C0MCNT1

I2C0ADR0

I2C0ADR1

1

R

0x00

I²C0 master current read count register. This register contains the

number of bytes already received during a read from slave sequence.

I²C0 address byte register. Write the required slave address in here

prior to communications.

I²C0 address byte register. Write the required slave address in here

prior to communications. Used in 10-bit mode only.

R/W

0x0824

0x0828

0x082C

0x0830

0x0834

0x0838

0x083C

0x0840

0x0844

0x0848

0x084C

I2C0DIV

I2C0SCON

I2C0SSTA

I2C0SRX

I2C0STX

I2C0ALT

I2C0ID0

I2C0ID1

I2C0ID2

I2C0ID3

I2C0FSTA

2

1

2

R/W

R

0x1F1F

0x0000

0x00

I²C0 clock control register. Used to configure the SCL frequency.

I²C0 slave control register.

I²C0 slave status register.

I²C0 slave receive register.

I²C0 slave transmit register.

W

R/W

I²C0 hardware general call recognition register.

I²C0 slave ID0 register. Slave bus ID register.

I²C0 slave ID1 register. Slave bus ID register.

I²C0 slave ID2 register. Slave bus ID register.

I²C0 slave ID3 register. Slave bus ID register.

I²C0 FIFO status register. Used in both master and slave modes.

0x0000

Table 18. I²C1 Base Address = 0XFFFF0900

Address Name Byte Access Type Default Value

Description

0x0900

0x0904

0x0908

0x090C

0x0910

I2C1MCON

I2C1MSTA

I2C1MRX

I2C1MTX

I2C1MCNT0

2

1

2

R/W

R

W

R/W

0x0000

0x00

0x0000

I²C1 master control register.

I²C1 master status register.

I²C1 master receive register.

I²C1 master transmit register.

I²C1 master read count register. Write the number of required bytes

into this register prior to reading from a slave device.

Rev. E | Page 26 of 96

Data Sheet

ADuC7023

Address Name

Byte Access Type Default Value

Description

0x0914

0x0918

0x091C

I2C1MCNT1

1

R

0x00

I²C1 master current read count register. This register contains the

number of bytes already received during a read from slave sequence.

I2C1ADR0

I2C1ADR1

R/W

I²C1 address byte register. Write the required slave address in here

prior to communications.

I²C1 address byte register. Write the required slave address in here

prior to communications. Used in 10-bit mode only.

0x0924

0x0928

0x092C

0x0930

0x0934

0x0938

0x093C

0x0940

0x0944

0x0948

0x094C

I2C1DIV

I2C1SCON

I2C1SSTA

I2C1SRX

I2C1STX

I2C1ALT

I2C1ID0

I2C1ID1

I2C1ID2

I2C1ID3

I2C1FSTA

2

1

2

R/W

R

0x1F1F

0x0000

0x00

I²C1 clock control register. Used to configure the SCL frequency.

I²C1 slave control register.

I²C1 slave status register.

I²C1 slave receive register.

I²C1 slave transmit register.

W

R/W

I²C1 hardware general call recognition register.

I²C1 slave ID0 register. Slave bus ID register.

I²C1 slave ID1 register. Slave bus ID register.

I²C1 slave ID2 register. Slave bus ID register.

I²C1 slave ID3 register. Slave bus ID register.

I²C1 FIFO status register. Used in both master and slave modes.

0x0000

Table 19. SPI Base Address = 0xFFFF0A00

Address Name Byte Access Type Default Value

Description

0x0A00

0x0A04

0x0A08

0x0A0C

0x0A10

SPISTA

SPIRX

SPITX

SPIDIV

SPICON

2

1

2

R

W

R/W

0x0000

0x00

0xXX

0x00

0x0000

SPI status MMR.

SPI receive MMR.

SPI transmit MMR.

SPI baud rate select MMR.

SPI control MMR.

Table 20. PLA Base Address = 0XFFFF0B00

Address Name Byte Access Type Default Value

PLAELM0

Description

0x0B00

0x0B04

0x0B08

0x0B0C

0x0B10

0x0B14

0x0B18

0x0B1C

0x0B20

0x0B24

0x0B28

0x0B2C

0x0B30

0x0B34

0x0B38

0x0B3C

0x0B40

0x0B44

0x0B48

0x0B4C

0x0B50

0x0B54

2

1

4

1

R/W

R

0x0000

0x00

PLA Element 0 control register.

PLA Element 1 control register.

PLA Element 2 control register.

PLA Element 3 control register.

PLA Element 4 control register.

PLA Element 5 control register.

PLA Element 6 control register.

PLA Element 7 control register.

PLA Element 8 control register.

PLA Element 9 control register.

PLA Element 10 control register.

PLA Element 11 control register.

PLA Element 12 control register.

PLA Element 13 control register.

PLA Element 14 control register.

PLA Element 15 control register.

PLA clock select register.

PLAELM1

PLAELM2

PLAELM3

PLAELM4

PLAELM5

PLAELM6

PLAELM7

PLAELM8

PLAELM9

PLAELM10

PLAELM11

PLAELM12

PLAELM13

PLAELM14

PLAELM15

PLACLK

PLAIRQ

PLAADC

PLADIN

PLADOUT

PLALCK

0x00000000

0x00

PLA interrupt control register.

PLA ADC trigger control register.

PLA data in register.

PLA data out register.

PLA lock register.

W

Rev. E | Page 27 of 96

ADuC7023

Data Sheet

Table 21. PWM Base Address = 0xFFFF0F80

Address Name

Byte Access Type Default Value

Description

0x0F80

PWMCON1

2

R/W

0x0012

PWM Control Register 1. See the Pulse-Width Modulator section

for full details.

0x0F84

0x0F88

0x0F8C

0x0F90

0x0F94

0x0F98

0x0F9C

0x0FA0

0x0FA4

0x0FA8

0x0FB8

PWM0COM0

PWM0COM1

PWM0COM2

PWM0LEN

PWM1COM0

PWM1COM1

PWM1COM2

PWM1LEN

2

R/W

W

0x0000

Compare Register 0 for PWM Output 0 and PWM Output 1.

Compare Register 1 for PWM Output 0 and PWM Output 1.

Compare Register 2 for PWM Output 0 and PWM Output 1.

Frequency control for PWM Output 0 and PWM Output 1.

Compare Register 0 for PWM Output 2 and PWM Output 3.

Compare Register 1 for PWM Output 2 and PWM Output 3.

Compare Register 2 for PWM Output 2 and PWM Output 3.

Frequency control for PWM Output 2 and PWM Output 3.

Compare Register 0 for PWM Output 4 and PWM Output 5.

Compare Register 1 for PWM Output 4 and PWM Output 5.

PWM2COM0

PWM2COM1

PWMCLRI

PWM interrupt clear register. Writing any value to this register

clears a PWM interrupt source.

Table 22. GPIO Base Address = 0xFFFFF400

Address Name Byte Access Type Default Value

Description

0xF400

0xF404

0xF408

0xF420

0xF424

0xF428

0xF42C

0xF430

0xF434

0xF438

0xF43C

0xF440

0xF444

0xF448

0xF44C

GP0CON

4

R/W

W

0x00001111

0x00000000

0x000000XX

0x22220000

0x000000XX

0x22000022

0x000000XX

0x00000000

GPIO Port0 control MMR.

GPIO Port1 control MMR.

GPIO Port2 control MMR.

GPIO Port0 data control MMR.

GPIO Port0 data set MMR.

GPIO Port0 data clear MMR.

GPIO Port0 pull-up disable MMR.

GPIO Port1 data control MMR.

GPIO Port1 data set MMR.

GPIO Port1 data clear MMR.

GPIO Port1 pull-up disable MMR.

GPIO Port2 data control MMR.

GPIO Port2 data set MMR.

GPIO Port2 data clear MMR.

GPIO Port2 pull-up disable MMR.

GP1CON

GP2CON

GP0DAT

GP0SET

GP0CLR

GP0PAR

GP1DAT

GP1SET

GP1CLR

GP1PAR

GP2DAT

GP2SET

GP2CLR

GP2PAR

W

R/W

W

R/W

W

R/W

Table 23. Flash/EE Base Address = 0xFFFFF800

Address Name Byte Access Type Default Value

Description

0xF800

0xF804

0xF808

0xF80C

0xF810

0xF818

0xF81C

0xF820

FEESTA

1

2

1

2

3

4

R

0x20

0x0000

0x07

0xXXXX

0x0000

0xFFFFFF

0x00000000

0xFFFFFFFF

Flash/EE status MMR.

Flash/EE control MMR.

Flash/EE data MMR.

Flash/EE address MMR.

Flash/EE LFSR MMR.

Flash/EE protection MMR.

FEEMOD

FEECON

FEEDAT

FEEADR

FEESIGN

FEEPRO

FEEHIDE

R/W

R

R/W

Rev. E | Page 28 of 96

Data Sheet

ADuC7023

ADC CIRCUIT OVERVIEW

The analog-to-digital converter (ADC) incorporates a fast,

multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V

supplies and is capable of providing a throughput of up to

1 MSPS when the clock source is 41.78 MHz. This block

provides the user with a multichannel multiplexer, a differential

track-and-hold, an on-chip reference, and an ADC.

1111 1111 1111

1111 1111 1110

1111 1111 1101

1111 1111 1100

FS

4096

1LSB =

The ADC consists of a 12-bit successive approximation

0000 0000 0011

0000 0000 0010

0000 0000 0001

0000 0000 0000

converter based around two capacitor DACs. Depending on the

input signal configuration, the ADC can operate in one of two

different modes: fully differential mode (for small and balanced

signals) or single-ended mode (for any single-ended signals).

0V 1LSB

+FS – 1LSB

VOLTAGE INPUT

The converter accepts an analog input range of 0 V to V_REFwhen

operating in single-ended mode. In fully differential mode, the

input signal must be balanced around a common-mode voltage

(V_CM) in the 0 V to AV_DDrange with a maximum amplitude of

2 V_REF(see Figure 19).

Figure 20. ADC Transfer Function in Single-Ended Mode

Fully Differential Mode

The amplitude of the differential signal is the difference between

the signals applied to the V_IN+and V_IN–pins (that is, V_IN+

_IN−). The maximum amplitude of the differential signal is,

therefore, −V_REFto +V_REFp-p (that is, 2 × V_REF). This is regardless of

the common mode (CM). The common mode is the average of

the two signals, for example, (V_IN++ V_IN–)/2, and is, therefore,

the voltage on which the two inputs are centered. This results in

the span of each input being CM V_REF/2. This voltage has to be

set up externally, and its range varies with V_REF(see the Driving

the Analog Inputs section).

−

V

AV

DD

V

2V

CM

REF

V

CM

2V

REF

V

2V

CM

REF

0

Figure 19. Examples of Balanced Signals in Fully Differential Mode

The output coding is twos complement in fully differential mode

with 1 LSB = 2 V_REF/4096 or 2 × 2.5 V/4096 = 1.22 mV when

A high precision, low drift, factory calibrated, 2.5 V reference is

provided on chip. An external reference can also be connected as

described later in the Band Gap Reference section.

V_REF= 2.5 V. The output result is 11 bits, but this is shifted by

one to the right. This allows the result in the ADCDAT MMR to

be declared as a signed integer when writing C code. The

designed code transitions occur midway between successive

integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS −

3/2 LSB). The ideal input/output transfer characteristic is shown

in Figure 21.

Single or continuous conversion modes can be initiated in the

CONV_START

software. An external

pin, an output generated from

the on-chip PLA, or a Timer0 or Timer1 overflow can also be

used to generate a repetitive trigger for ADC conversions.

A voltage output from an on-chip band gap reference propor-

tional to absolute temperature can also be routed through the

front-end ADC multiplexer. This temperature channel can be

selected as an ADC input. This facilitates an internal temperature

sensor channel that measures die temperature.

SIGN

BIT

0

1111 1111 1110

1111 1111 1100

1111 1111 1010

2 × V

4096

REF

1LSB =

TRANSFER FUNCTION

Single-Ended Mode

0

1

0000 0000 0010

0000 0000 0000

1111 1111 1110

In single-ended mode, the input range is 0 V to V_REF. The

output coding is straight binary in single-ended mode with

1

0000 0000 0100

0000 0000 0010

0000 0000 0000

1 LSB = FS/4096, or

2.5 V/4096 = 0.61 mV, or

610 μV when V_REF= 2.5 V

–V

+ 1LSB

0LSB

+V

– 1LSB

REF

VOLTAGE INPUT (V + – V –)

IN

Figure 21. ADC Transfer Function in Differential Mode

The ideal code transitions occur midway between successive

integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,

FS − 3/2 LSB). The ideal input/output transfer characteristic

is shown in Figure 20.

Rev. E | Page 29 of 96

ADuC7023

Data Sheet

ACQ

BIT TRIAL

WRITE

TYPICAL OPERATION

When configured via the ADC control and channel selection

registers, the ADC converts the analog input and provides a

12-bit result in the ADC data register.

ADC CLOCK

The top four bits are the sign bits. The 12-bit result is placed

from Bit 16 to Bit 27 as shown in Figure 22. Note that in fully

differential mode, the result is represented in twos complement

format. In single-ended mode, the result is represented in

straight binary format.

CONV

START

ADC

BUSY

DATA

ADCDAT

31

27

16 15

0

ADCSTA = 0

ADCSTA = 1

ADC INTERRUPT

SIGN BITS

12-BIT ADC RESULT

Figure 22. ADC Result Format

Figure 23. ADC Timing

The same format is used in DACxDAT, simplifying the software.

MMR INTERFACE

Current Consumption

The ADC is controlled and configured via the eight MMRs

described in this section.

The ADC in standby mode, that is, powered up but not

converting, typically consumes 640 μA. The internal reference

adds 140 μA. During conversion, the extra current is 0.3 μA

multiplied by the sampling frequency (in kHz).

ADCCON Register

Name:

ADCCON

0xFFFF0500

0x0600

Timing

Address:

Default value:

Access:

Figure 23 gives details of the ADC timing. Users control the

ADC clock speed and the number of acquisition clocks in the

ADCCON MMR. By default, the acquisition time is eight

clocks, and the clock divider is two. The number of extra clocks

(such as bit trial or write) is set to 19, which gives a sampling

rate of 774 kSPS. For conversion on the temperature sensor, set

ADCCON = 0x37A3. When using multiple channels including

the temperature sensor, the timing settings revert to the user-

defined settings after reading the temperature sensor channel.

Read/write

Function:

ADCCON is an ADC control register

that allows the programmer to enable the

ADC peripheral, select the mode of

operation of the ADC (either in single-

ended mode or fully differential mode),

and select the conversion type. This MMR

is described in Table 24.

Table 24. ADCCON MMR Bit Designations

Bit

Value

Description

15 to 14

13

Reserved.

Temperature sensor conversion enable. Set to 1 for temperature sensor conversions and single

software conversions. Set to 0 for normal ADC conversions.

12 to 10

ADC clock speed.

000

001

010

011

100

101

f_ADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz.

f_ADC/2 (default value).

f_ADC/4.

f_ADC/8.

f_ADC/16.

f_ADC/32.

9 to 8

ADC acquisition time.

2 clocks.

4 clocks.

8 clocks (default value).

16 clocks.

00

01

10

11

Rev. E | Page 30 of 96

Data Sheet

ADuC7023

Bit

Value

Description

7

Enable start conversion.

This bit is set by the user to start any type of conversion command.

This bit is cleared by the user to disable a start conversion (clearing this bit does not stop the ADC

when continuously converting).

6

5

Reserved

ADC power control.

This bit is set by the user to place the ADC in normal mode (the ADC must be powered up for at least

5 μs before it converts correctly).

This bit is cleared by the user to place the ADC in power-down mode.

4 to 3

2 to 0

Conversion mode.

Single-ended mode.

Differential mode.

Reserved.

00

01

10

11

Reserved.

Conversion type.

000

001

010

011

Enable CONV_STARTpin as a conversion input.

Enable Timer1 as a conversion input.

Enable Timer0 as a conversion input.

Single software conversion. This bit is set to 000 after conversion (note that Bit 13 of the ADCCON

MMR should be set before starting a single software conversion to avoid further conversions

triggered by the CONV_STARTpin).

100

101

Continuous software conversion.

PLA conversion.

Other

Reserved.

ADCCP Register

Table 25. ADCCP MMR Bit Designation

Name:

ADCCP

0xFFFF0504

0x00

Bit

Value

Description

7 to 5

4 to 0

Reserved.

Address:

Positive channel selection bits.

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

Others

ADC0.

ADC1.

ADC2.

Default value:

Access:

Read/write

ADC3.

Function:

ADCCP is an ADC positive channel

selection register. This MMR is described in

Table 25.

ADC4¹.

ADC5¹.

ADC6¹.

ADC7¹.

ADC8¹.

ADC9¹.

ADC10¹.

Reserved.

ADC12¹.

Reserved

DAC0

DAC1

Temperature sensor.

AGND (self-diagnostic feature).

Internal reference (self-diagnostic feature).

AV_DD/2.

Reserved.

¹When a selected ADC channel is shared with one GPIO, by default, this pin is

configured with a weak pull-up resistor enabled. The pull-up resistor should

be disabled manually in the appropriate GPxPAR register. Note the internal

pull-up resistor on P2.0/AIN12 for 40-lead package cannot be disabled.

Rev. E | Page 31 of 96

ADuC7023

Data Sheet

ADCCN Register

ADCSTA Register

Name:

ADCCN

0xFFFF0508

0x01

Name:

ADCSTA

0xFFFF050C

0x00

Address:

Default value:

Access:

Default Value:

Access:

Read/write

Read

Function:

ADCCN is an ADC negative channel

selection register. This MMR is described in

Table 26.

Function:

ADCSTA is an ADC status register that

indicates when an ADC conversion result is

ready. The ADCSTA register contains only

one bit, ADCReady (Bit 0), representing

the status of the ADC. This bit is set at the

end of an ADC conversion, generating an

ADC interrupt. It is cleared automatically

by reading the ADCDAT MMR. When the

ADC is performing a conversion, the status

of the ADC can be read externally via the

ADC_BUSYpin. This pin is high during a

conversion. When the conversion is

Table 26. ADCCN MMR Bit Designation

Bit

Value

Description

7 to 5

4 to 0

Reserved.

Negative channel selection bits.

ADC0.

ADC1.

ADC2.

ADC3.

ADC4.

ADC5.

ADC6.

ADC7.

ADC8.

ADC9.

ADC10.

Reserved

ADC12.

Reserved

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

finished, ADC_BUSYgoes back low. This

information can be available on P0.0 (see

the General-Purpose Input/Output section)

if enabled in the ADCCON register.

ADCDAT Register

Name:

ADCDAT

0xFFFF0510

0x00000000

Read

Address:

Default value:

Access:

DAC1.

Temperature sensor.

AGND (self-diagnostic feature).

Internal reference (self-diagnostic feature).

Reserved

Function:

ADCDAT is an ADC data result register.

Hold the 12-bit ADC result as shown in

Figure 22.

Others Reserved.

ADCRST Register

Name:

ADCRST

0xFFFF0514

0x00

Address:

Default Value:

Access:

Read/write

Function:

ADCRST resets the digital interface of the

ADC. Writing any value to this register

resets all the ADC registers to their

default value.

Rev. E | Page 32 of 96

Data Sheet

ADuC7023

ADCGN Register

CAPACITIVE

DAC

Name:

ADCGN

COMPARATOR

C

B

A

S

CHANNEL+

CHANNEL–

ADC0

Address:

0xFFFF0530

Factory configured

Read/write

SW1

SW2

CONTROL

LOGIC

MUX

SW3

Default value:

Access:

A

B

ADC11

V

REF

CAPACITIVE

DAC

Function:

ADCGN is a 10-bit gain calibration

register.

Figure 25. ADC Conversion Phase

When the ADC starts a conversion, as shown in Figure 25,

SW3 opens, and then SW1 and SW2 move to Position B. This

causes the comparator to become unbalanced. Both inputs are

disconnected once the conversion begins. The control logic

and the charge redistribution DACs are used to add and

subtract fixed amounts of charge from the sampling capacitor

arrays to bring the comparator back into a balanced condition.

When the comparator is rebalanced, the conversion is complete.

The control logic generates the ADC output code. The output

impedances of the sources driving the V_IN+and V_IN–pins must

be matched; otherwise, the two inputs have different settling

times, resulting in errors.

ADCOF Register

Name:

ADCOF

Address:

0xFFFF0534

Factory configured

Read/write

Default value:

Access:

Function:

ADCOF is a 10-bit offset calibration

register.

CONVERTER OPERATION

Single-Ended Mode

The ADC incorporates a successive approximation (SAR)

architecture involving a charge-sampled input stage. This

architecture can operate in two different modes: differential

and single-ended.

In single-ended mode, SW2 is always connected internally to

ground. The V_IN−pin can be floating. The input signal range on

V

_IN+is 0 V to V_REF.

Differential Mode

CAPACITIVE

DAC

The ADuC7023 contains a successive approximation ADC

based on two capacitive DACs. Figure 24 and Figure 25 show

simplified schematics of the ADC in acquisition and conversion

phase, respectively. The ADC is comprised of control logic, a

SAR, and two capacitive DACs. In Figure 24 (the acquisition

phase), SW3 is closed and SW1 and SW2 are in Position A. The

comparator is held in a balanced condition, and the sampling

capacitor arrays acquire the differential signal on the input.

COMPARATOR

C

B

A

S

CHANNEL+

ADC0

SW1

CONTROL

LOGIC

MUX

SW3

S

CHANNEL–

ADC11

CAPACITIVE

DAC

Figure 26. ADC in Single-Ended Mode

CAPACITIVE

DAC

Analog Input Structure

COMPARATOR

Figure 27 shows the equivalent circuit of the analog input structure

of the ADC. The four diodes provide ESD protection for the analog

inputs. Care must be taken to ensure that the analog input signals

never exceed the supply rails by more than 300 mV; this causes

these diodes to become forward-biased and start conducting

into the substrate. These diodes can conduct up to 10 mA

without causing irreversible damage to the part.

C

B

A

S

CHANNEL+

CHANNEL–

ADC0

SW1

SW2

CONTROL

LOGIC

MUX

SW3

S

A

B

ADC11

V

REF

CAPACITIVE

DAC

Figure 24. ADC Acquisition Phase

Rev. E | Page 33 of 96

ADuC7023

Data Sheet

The C1 capacitors in Figure 27 are typically 4 pF and can be

primarily attributed to pin capacitance. The resistors are

lumped components made up of the on resistance of the

switches. The value of these resistors is typically about 100 Ω.

The C2 capacitors are the ADC sampling capacitors and

typically have a capacitance of 16 pF.

signal remains within the supply rails. Table 27 gives some

calculated V_CMminimum and V_CMmaximum values.

Table 27. V_CMRanges

AV_DDV_REF

V_CMMin V_CMMax Signal Peak-to-Peak

3.3 V 2.5 V

1.25 V

2.05 V

2.276 V

2.55 V

1.75 V

1.976 V

2.25 V

2.5 V

2.048 V 1.024 V

1.25 V

2.048 V

1.25 V

2.5 V

2.048 V

1.25 V

AV

DD

0.75 V

1.25 V

D

3.0 V 2.5 V

C2

R1

2.048 V 1.024 V

1.25 V

C1

D

0.75 V

CALIBRATION

AV

DD

By default, the factory-set values written to the ADC offset

(ADCOF) and gain coefficient registers (ADCGN) yield

optimum performance in terms of endpoint errors and linearity

for standalone operation of the part (see the Specifications

section). If system calibration is required, it is possible to

modify the default offset and gain coefficients to improve

endpoint errors, but note that any modification to the factory-

set ADCOF and ADCGN values can degrade ADC linearity

performance.

D

C2

R1

C1

Figure 27. Equivalent Analog Input Circuit Conversion Phase: Switches Open,

Track Phase: Switches Closed

For ac applications, removing high frequency components from

the analog input signal is recommended by using an RC low-

pass filter on the relevant analog input pins. In applications

where harmonic distortion and signal-to-noise ratio are critical,

the analog input should be driven from a low impedance

source. Large source impedances significantly affect the ac

performance of the ADC. This can necessitate the use of an

input buffer amplifier. The choice of the op amp is a function of

the particular application. Figure 28 and Figure 29 give an

example of an ADC front end.

For system offset error correction, the ADC channel input stage

must be tied to AGND. A continuous software ADC conversion

loop must be implemented by modifying the value in ADCOF until

the ADC result (ADCDAT) reads Code 0 to Code 1. If the

ADCDAT value is greater than 1, ADCOF should be decremented

until ADCDAT reads Code 0 to Code 1. Offset error correction

is done digitally and has a resolution of 0.25 LSB and a range of

3.125% of V_REF

.

For system gain error correction, the ADC channel input

stage must be tied to V_REF. A continuous software ADC

conversion loop must be implemented to modify the value

in ADCGN until the ADCDAT reads Code 4094 to Code 4095.

If the ADCDAT value is less than 4094, ADCGN should be

incremented until ADCDAT reads Code 4094 to Code 4095.

Similar to the offset calibration, the gain calibration resolution

ADuC7023

10Ω

ADC0

0.01µF

Figure 28. Buffering Single-Ended Differential Input

is 0.25 LSB with a range of 3% of V_REF

.

ADuC7023

ADC0

TEMPERATURE SENSOR

V

REF

The ADuC7023 provides a voltage output from an on-chip

band gap reference that is proportional to absolute temperature.

This voltage output can also be routed through the front-end

ADC multiplexer (effectively an additional ADC channel

input), facilitating an internal temperature sensor channel,

measuring die temperature.

ADC1

Figure 29. Buffering Differential Inputs

When no amplifier is used to drive the analog input, limit the

source impedance to values lower than 1 kΩ. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases and the performance degrades.

An ADC temperature sensor conversion differs from a standard

ADC voltage. The ADC performance specifications do not

apply to the temperature sensor.

DRIVING THE ANALOG INPUTS

Chopping of the internal amplifier should be enabled using the

TSCON register. To enable this mode, the user must set Bit 0 of

TSCON. The user must also take two consecutive ADC readings

and average them in this mode.

Internal or external references can be used for the ADC. When

operating in differential mode, there are restrictions on the

common-mode input signal (V_CM), which is dependent upon

the reference value and supply voltage used to ensure that the

Rev. E | Page 34 of 96

Data Sheet

ADuC7023

The ADCCON register must be configured to 0x37A3.

To calculate die temperature use the following formula:

T − T_REF= (V_ADC− V_TREF) × K

Table 28. TSCON MMR Bit Designations

Bit

7 to 1

0

Description

Reserved.

Temperature sensor chop enable bit.

where:

This bit is set to 1 to enable chopping of the internal

amplifier to the ADC.

T is the temperature result.

T_REFis 25°C.

This bit is cleared to disable chopping.

This bit is cleared by default.

V

_ADCis the average ADC result from two consecutive

conversions.

_TREFis 1369 mV, which corresponds to T_REF= 25°C as

V

TEMPREF Register

described in Table 1.

Name:

TEMPREF

K is the gain of the ADC in temperature sensor mode as

determined by characterization data, K = 0.2262°C/mV. This

corresponds to 1/V TC specification as shown in Table 1.

Address:

Default value:

Access:

0xFFFF0548

Factory configured

Read/write

Using the default values from Table 1 and without any calibra-

tion, this equation becomes

T – 25°C = (V_ADC− 1369) × 0.2262

Table 29. TEMPREF MMR Bit Designations

Bit Description

15 to 9 Reserved.

where:

_ADCis in millivolts.

V

For increased accuracy, perform a single point calibration at a

controlled temperature value.

8

Temperature reference voltage sign.

7 to 0

Temperature sensor offset calibration voltage.

To calculate the V_TREFfrom the TEMPREF register,

perform the following calculation:

For the calculation shown without calibration, (T_REF, V_TREF) =

(25°C, 1369 mV). The idea of a single point calibration is to use

other known (T_REF, V_TREF) values to replace the common (25°C,

1369 mV) for every part.

If TEMPREF sign negative, subtract TEMPREF from 2292

C_TREF= 2292 − TEMPREF[7:0]

where TEMREF[8] = 1.

For some users, it is not possible to get such a known pair. For

these cases, an ADuC7023 comes with a single point calibration

value loaded in the TEMPREF register. For more details on this

register, see the TEMPREF Register section.

or

If TEMREF sign positive, add TEMPREF to 2292

C_TREF= TEMPREF[7:0] + 2292

where:

During production testing of the ADuC7023, the TEMPREF

register is loaded with an offset adjustment factor. Each part

will have a different value in the TEMPREF register. Using this

single point calibration, use the same formula as shown:

TEMPREF[8] = 0.

Then,

T − T_REF= (V_ADC− V_TREF) × K

V_TREF= (C_TREF× V_REF)/4096 × 1000

where:

C_TREFis calculated as above.

V_REFis 2.5 V, internal reference voltage.

T

_REFis 27°C when using the TEMPREF register method, but is

not guaranteed.

_TREFcan be calculated using the TEMPREF register.

T

Insert V_TREFinto

TSCON Register

T – T_REF= (V_ADC– V_TREF) × K

Name:

TSCON

where:

Address:

0xFFFF0544

0x00

T_REFis 27°C, when using TEMREF register.

V_ADCis the average ADC result from two

consecutive conversions.

Default value:

Access:

V_TREFis calculated as above.

Read/write

Note that ADC code value 2292 is a default value

when using the TEMREF register. It is not an exact

value and must only be used with the TEMPREF

register.

Rev. E | Page 35 of 96

ADuC7023

Data Sheet

BAND GAP REFERENCE

Table 30. REFCON MMR Bit Designations

Bit

7 to 1

0

Description

The ADuC7023 provides an on-chip band gap reference of

2.5 V, which can be used for the ADC and DAC. This internal

reference also appears on the V_REFpin. When using the internal

reference, a 0.47 μF capacitor must be connected from the external

Reserved.

Internal reference output enable.

This bit is set by the user to connect the internal 2.5 V

reference to the V_REFpin. The reference can be used

for an external component but needs to be buffered.

This bit is cleared by the user to disconnect the

reference from the V_REFpin.

V_REFpin to AGND to ensure stability and fast response during

ADC conversions. This reference can also be connected to an

external pin (V_REF) and used as a reference for other circuits in

the system.

To connect an external reference source to the ADuC7023,

configure REFCON = 0x01. ADC and the DACs can be

configured to use the same or different reference resource. See

Table 42.

An external buffer is required because of the low drive capability

of the V_REFoutput. A programmable option also allows an

external reference input on the V_REFpin.

REFCON Register

Name:

REFCON

0xFFFF048C

0x00

Address:

Default value:

Access:

Read/write

Function:

The band gap reference interface consists

of an 8-bit MMR REFCON described in

Table 30.

Rev. E | Page 36 of 96

Data Sheet

ADuC7023

NONVOLATILE FLASH/EE MEMORY

The ADuC7023 incorporates Flash/EE memory technology on

chip to provide the user with nonvolatile, in-circuit reprogram-

mable memory space.

Flash/EE memory is guaranteed to retain its data for its fully

specified retention lifetime every time the Flash/EE memory is

reprogrammed. In addition, note that retention lifetime, based

on activation energy of 0.6 eV, derates with T_Jas shown in

Figure 30.

Like EEPROM, flash memory can be programmed in-system at

a byte level, although it must first be erased. The erase is performed

in page blocks. As a result, flash memory is often and more

correctly referred to as Flash/EE memory.

600

The Flash/EE memory represents a step closer to the ideal memory

device that includes nonvolatility, in-circuit programmability,

high density, and low cost. Incorporated in the ADuC7023,

Flash/EE memory technology allows the user to update program

code space in-circuit, without needing to replace one-time

programmable (OTP) devices at remote operating nodes.

450

300

150

0

Each part contains a 64 kB array of Flash/EE memory. The lower

62 kB are available to the user, and the upper 2 kB contain

permanently embedded firmware, allowing in-circuit serial

download. These 2 kB of embedded firmware also contain a

power-on configuration routine that downloads factory-

calibrated coefficients to the various calibrated peripherals

(such as ADC, temperature sensor, and band gap references).

This 2 kB embedded firmware is hidden from user code.

30

40

55

70

85

100

125

135

150

JUNCTION TEMPERATURE (°C)

Figure 30. Flash/EE Memory Data Retention

PROGRAMMING

The 62 kB of Flash/EE memory can be programmed in circuit,

using the serial download mode or the provided JTAG mode.

Flash/EE Memory Reliability

The Flash/EE memory arrays on the parts are fully qualified for

two key Flash/EE memory characteristics: Flash/EE memory

cycling endurance and Flash/EE memory data retention.

Downloading (In-Circuit Programming) via I²C

The ADuC7023 facilitates code download via the the I²C port.

The parts enter download mode after a reset or power cycle if

the BM pin is pulled low through an external 1 kΩ resistor and

Flash Addess 0x80014 = 0xFFFFFFFF. Once in download mode,

the user can download code to the full 62 kB of Flash/EE

memory while the device is in-circuit in its target application

hardware. An executable PC I²C download is provided as part

of the development system for serial downloading via the I²C. A

USB to I²C download dongle can be purchased from Analog

Devices, Inc. This board connects to the USB port of a PC and

to the I²C port of the ADuC7023. The part number is USB-

I2C/LIN-CONV-Z.

Endurance quantifies the ability of the Flash/EE memory to be

cycled through many program, read, and erase cycles. A single

endurance cycle is composed of four independent, sequential

events, defined as:

1. Initial page erase sequence.

2. Read/verify sequence (single Flash/EE).

3. Byte program sequence memory.

4. Second read/verify sequence (endurance cycle).

In reliability qualification, every half word (16-bit wide)

location of the three pages (top, middle, and bottom) in the

Flash/EE memory is cycled 10,000 times from 0x0000 to

0xFFFF. As indicated in Table 1, the Flash/EE memory

endurance qualification is carried out in accordance with

JEDEC Retention Lifetime Specification A117 over the

industrial temperature range of −40° to +125°C. The results

allow the specification of a minimum endurance figure over a

supply temperature of 10,000 cycles.

The AN-806 Application Note describes the protocol for serial

downloading via the I²C in more detail.

JTAG Access

The JTAG protocol uses the on-chip JTAG interface to facilitate

code download and debug.

To access the part via the JTAG interface, the P0.0/BM pin must

be set high to enable P0.1/P0.2/P0.3 as JTAG pins.

Retention quantifies the ability of the Flash/EE memory to

retain its programmed data over time. Again, the parts are

qualified in accordance with the formal JEDEC Retention

Lifetime Specification (A117) at a specific junction temperature

(T_J= 85°C). As part of this qualification procedure, the

Flash/EE memory is cycled to its specified endurance limit

before data retention is characterized. This means that the

When debugging, user code should not write to the P0.1/P0.2

and P0.3 pins. If user code toggles any of these pins, JTAG

debug pods are not able to connect to the ADuC7023. In case

this happens, the user should have a function in code that can

be called externally to mass erase the part. Alternatively, the

user should ensure that Flash Address 0x80014 is erased to

allow erasing of the part through the I²C interface.

Rev. E | Page 37 of 96

ADuC7023

Data Sheet

To remove or modify the protection, the same sequence is used

with a modified value of FEEPRO. If the key chosen is the value

0xDEAD, the memory protection cannot be removed. Only a mass

erase unprotects the part, but it also erases all user code.

SECURITY

The 62 kB of Flash/EE memory available to the user can be read

and write protected.

Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 34) protects

the 62 kB from being read through JTAG programming mode.

The other 31 bits of this register protect writing to the flash

memory. Each bit protects four pages, that is, 2 kB. Write

protection is activated for all types of access.

The sequence to write the key is illustrated in the following

example (this protects writing Page 4 to Page 7 of the Flash):

FEEPRO=0xFFFFFFFD; //Protect Page 4 to

Page 7

FEEMOD=0x48; //Write key enable

Three Levels of Protection

FEEADR=0x1234;

FEEDAT=0x5678;

FEECON= 0x0C;

//16 bit key value

//Write key command

Protection can be set and removed by writing directly into

FEEHIDE MMR. This protection does not remain after reset.

Protection can be set by writing into FEEPRO MMR. It only

takes effect after a save protection command (0x0C) and a reset.

The FEEPRO MMR is protected by a key to avoid direct access.

The key is saved once and must be entered again to modify

FEEPRO. A mass erase sets the key back to 0xFFFF but also

erases all the user code.

The same sequence should be followed to

protect the part permanently with FEEADR =

0xDEAD and FEEDAT = 0xDEAD.

FLASH/EE CONTROL INTERFACE

Serial and JTAG programming use the Flash/EE control interface,

which includes the eight MMRs outlined in this section.

Flash can be permanently protected by using the FEEPRO

MMR and a particular value of key: 0xDEADDEAD. Entering

the key again to modify the FEEPRO register is not allowed.

FEESTA Register

Name:

FEESTA

Sequence to Write the Key

Address:

0xFFFFF800

1. Write the bit in FEEPRO corresponding to the page to be

protected.

Default value: 0x20

2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5

must equal 0).

Access:

Read

3. Write a 32-bit key in FEEADR, FEEDAT.

Function:

FEESTA is a read-only register that reflects the

status of the flash control interface as

described in Table 31.

4. Run the write key command 0x0C in FEECON; wait for

the read to be successful by monitoring FEESTA.

5. Reset the part.

Table 31. FEESTA MMR Bit Designations

Bit

Description

7 to 6

Reserved.

5

4

3

Reserved.

Flash interrupt status bit.

This bit is set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit

in the FEEMOD register is set.

This bit is cleared when reading FEESTA register.

Flash/EE controller busy.

This bit is set automatically when the controller is busy.

This bit is cleared automatically when the controller is not busy.

Command fail.

This bit is set automatically when a command is not completed.

This bit is cleared automatically when reading FEESTA register.

Command pass.

2

1

0

This bit is set by the MicroConverter when a command is completed.

This bit is cleared automatically when reading the FEESTA register.

Rev. E | Page 38 of 96

Data Sheet

ADuC7023

FEEMOD Register

Name:

FEEMOD

0xFFFFF804

0x0000

Address:

Default value:

Access:

Read/write

Function:

FEEMOD sets the operating mode of the flash control interface. Table 32 shows FEEMOD MMR bit designations.

Table 32. FEEMOD MMR Bit Designations

Bit

Description

15 to 9

8

Reserved.

Reserved. Always set this bit to 0.

7 to 5

4

Reserved. Always set this bit to 0 except when writing keys. See the Sequence to Write the Key section.

Flash/EE interrupt enable.

This bit is set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.

This bit is cleared by the user to disable the Flash/EE interrupt.

Erase/write command protection.

3

This bit is set by the user to enable the erase and write commands.

This bit is cleared to protect the Flash/EE against erase/write command.

Reserved. Always set this bit to 0.

2 to 0

FEECON Register

Name:

FEECON

Address:

0xFFFFF808

Default value:

Access:

0x07

Read/write

Function:

FEECON is an 8-bit command register. The commands are described in Table 33.

Table 33. Command Codes in FEECON

Code Command

0x00¹Null

Description

Idle state.

0x01¹Single read

0x02¹Single write

0x03¹Erase/write

Load FEEDAT with the 16-bit data. Indexed by FEEADR.

Write FEEDAT at the address pointed by FEEADR. This operation takes 50 µs.

Erase the page indexed by FEEADR, and write FEEDAT at the location pointed by FEEADR. This operation takes

approximately 24 ms.

Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The result of the comparison is

returned in FEESTA Bit 1.

0x04¹Single verify

0x05¹Single erase

0x06¹Mass erase

Erase the page indexed by FEEADR.

Erase 62 kB of user space. The 2 kB of kernel are protected. This operation takes 2.48 sec. To prevent accidental

execution, a command sequence is required to execute this instruction. See the Command Sequence for

Executing a Mass Erase section.

0x07

0x08

0x09

Reserved

Reserved.

0x0A Reserved

0x0B Signature

0x0C Protect

Reserved.

Give a signature of the 64 kB of Flash/EE in the 24-bit FEESIGN MMR. This operation takes 32,778 clock cycles.

This command can run one time only. The value of FEEPRO is saved and removed only with a mass erase (0x06) or

the key (FEEADR/FEEDAT).

Rev. E | Page 39 of 96

ADuC7023

Data Sheet

Code Command

Description

0x0D Reserved

Reserved.

0x0E

0x0F

Reserved

Ping

Reserved.

No operation; interrupt generated.

¹The FEECON register always reads 0x07 immediately after execution of any of these commands.

FEEPRO Register

FEEDAT Register

Name:

FEEPRO

Name:

FEEDAT

Address:

0xFFFFF81C

Address:

0xFFFFF80C

Default value: 0x00000000

Default value: 0xXXXX

Access:

Read/write

Access:

Read/write

Function:

FEEPRO MMR provides protection following a

subsequent reset of the MMR. It requires a

software key (see Table 34).

Function:

FEEDAT is a 16-bit data register.

FEEADR Register

Name:

FEEADR

FEEHIDE Register

Address:

0xFFFFF810

Name:

FEEHIDE

Default value: 0x0000

Address:

0xFFFFF820

Access:

Read/write

FEEADR is another 16-bit address register.

Default value: 0xFFFFFFFF

Function:

Access:

Read/write

Function:

FEEHIDE MMR provides immediate

protection. It does not require any software

key. The protection settings in FEEHIDE are

cleared by a reset (see Table 34).

FEESIGN Register

Name:

FEESIGN

Address:

0xFFFFF818

Default value: 0xFFFFFF

Table 34. FEEPRO and FEEHIDE MMR Bit Designations

Bit

Description

Access:

Read

31

Read protection.

This bit is cleared by the user to protect the code

This bit is set by the user to allow reading the code.

Function:

FEESIGN is a 24-bit code signature.

30 to 0 Write protection for Page 123 to Page 120, Page 119 to

Page 116, and Page 0 to Page 3.

This bit is cleared by the user to protect the pages in

writing.

This bit is set by the user to allow writing the pages.

Command Sequence for Executing a Mass Erase

FEEDAT = 0x3CFF;

FEEADR = 0xFFC3;

FEEMOD = FEEMOD|0x8;

FEECON = 0x06;

command

//Erase key enable

//Mass erase

Rev. E | Page 40 of 96

Data Sheet

ADuC7023

EXECUTION TIME FROM SRAM AND FLASH/EE

RESET AND REMAP

Execution from SRAM

The ARM exception vectors are all situated at the bottom of the

memory array, from Address 0x00000000 to Address 0x00000020

as shown in Figure 31.

Fetching instructions from SRAM takes one clock cycle because

the access time of the SRAM is 2 ns, and a clock cycle is 22 ns

minimum. However, if the instruction involves reading or

writing data to memory, one extra cycle must be added if the

data is in SRAM (or three cycles if the data is in Flash/EE); one

cycle to execute the instruction and two cycles to obtain the

32-bit data from Flash/EE. A control flow instruction (a branch

instruction, for example) takes one cycle to fetch but also takes

two cycles to fill the pipeline with the new instructions.

0xFFFFFFFF

KERNEL

0x0008FFFF

0x00011FFF

FLASH/EE

INTERRUPT

SERVICE ROUTINES

0x00080000

0x00010000

Execution from Flash/EE

Because the Flash/EE width is 16 bits and the access time for

16-bit words is 22 ns, execution from Flash/EE cannot be

completed in one cycle (as can be done from SRAM when the

CD bit = 0). Also, some dead times are needed before accessing

data for any value of CD bits.

SRAM

INTERRUPT

SERVICE ROUTINES

MIRROR SPACE

0x00000020

ARM EXCEPTION

In ARM mode, where instructions are 32 bits, two cycles are

needed to fetch any instruction when CD = 0. In thumb mode,

where instructions are 16 bits, one cycle is needed to fetch any

instruction.

VECTOR ADDRESSES 0x00000000 0x00000000

Figure 31. Remap for Exception Execution

By default, and after any reset, the Flash/EE is mirrored at the

bottom of the memory array. The remap function allows the

programmer to mirror the SRAM at the bottom of the memory

array, which facilitates execution of exception routines from

SRAM instead of from Flash/EE. This means exceptions are

executed twice as fast, being executed in 32-bit ARM mode with

32-bit wide SRAM instead of 16-bit wide Flash/EE memory.

Timing is identical in both modes when executing instructions

that involve using the Flash/EE for data memory. If the instruction

to be executed is a control flow instruction, an extra cycle is

needed to decode the new address of the program counter, and

then four cycles are needed to fill the pipeline. A data processing

instruction involving only the core register does not require any

extra clock cycles. However, if it involves data in Flash/EE, an

extra clock cycle is needed to decode the address of the data,

and two cycles are needed to get the 32-bit data from Flash/EE.

An extra cycle must also be added before fetching another

instruction. Data transfer instructions are more complex and

are summarized in Table 35.

Remap Operation

When a reset occurs on the ADuC7023, execution automatically

starts in factory programmed, internal configuration code. This

kernel is hidden and cannot be accessed by user code. If the part is

in normal mode (BM pin is high), it executes the power-on

configuration routine of the kernel and then jumps to the reset

vector address, 0x00000000, to execute the reset exception

routine of the user.

Table 35. Execution Cycles in ARM/Thumb Mode

Fetch

Instructions Cycles

Dead

Time

Dead

Time

Because the Flash/EE is mirrored at the bottom of the memory

array at reset, the reset interrupt routine must always be written

in Flash/EE.

Data Access

LD¹

LDH

LDM/PUSH

STR¹

STRH

2/1

1

N²

1

N¹

2

1

N¹

1

N¹

2 × N²

2 × 20 ns

20 ns

The remap is done from Flash/EE by setting Bit 0 of the Remap

register. Caution must be taken to execute this command from

Flash/EE above Address 0x00080020, and not from the bottom

of the array because this is replaced by the SRAM.

STRM/POP

2 × N × 20 ns¹

¹The SWAP instruction combines an LD and STR instruction with only one

fetch, giving a total of eight cycles + 40 ns.

This operation is reversible. The Flash/EE can be remapped at

Address 0x00000000 by clearing Bit 0 of the Remap MMR.

Caution must again be taken to execute the remap function

from outside the mirrored area. Any type of reset remaps the

Flash/EE memory at the bottom of the array.

²N is the number of data to load or store in the multiple load/store instruction

(1 < N ≤ 16).

Rev. E | Page 41 of 96

ADuC7023

Data Sheet

REMAP Register

Table 37. RSTSTA MMR Bit Designations

Bit

7 to 3

2

Description

Name:

REMAP

0xFFFF0220

0x00

Reserved.

Address:

Software reset.

This bit is set by the user to force a software reset.

This bit is cleared by setting the corresponding bit

in RSTCLR.

Default value:

Access:

Read/write

1

0

Watchdog timeout.

This bit is set automatically when a watchdog

timeout occurs.

This bit is cleared by setting the corresponding bit

in RSTCLR.

Table 36. REMAP MMR Bit Designations

Bit

7 to 5

4

Name

Description

Reserved.

Read-only bit. Indicates the size of the

Flash/EE memory available. If this bit is set,

only 32 kB of Flash/EE memory is available.

Power-on reset.

This bit is set automatically when a power-on reset

occurs.

3

Read-only bit. Indicates the size of the

SRAM memory available. If this bit is set,

only 4 kB of SRAM is available.

This bit is cleared by setting the corresponding bit

in RSTCLR.

2 to 1

JTAFO

Read only bits. See the P0.0/BM

description for further details.

If = [00], then P0.1/P0.2/P0.3 are

configured as JTAG pins.

If = [1x], then P0.1/P0.2/P0.3 are

configured as GPIO pins.

These bits are configured by the kernel

after any reset sequence and depend on

the state of P0.0 during the last reset

sequence.

RSTCLR Register

Name:

RSTCLR

Address:

0xFFFF0234

Default value: 0x00

Access:

Write

Function:

Note that to clear the RSTSTA register, users

must write the Value 0x07 to the RSTCLR

register.

0

Remap

Remap bit.

This bit is set by the user to remap the

SRAM to Address 0x00000000.

This bit is cleared automatically after reset

to remap the Flash/EE memory to Address

0x00000000.

RSTCFG Register

Name:

RSTCFG

Reset Operation

Address:

0xFFFF024C

There are four kinds of reset: external, power-on, watchdog

expiration, and software force. The RSTSTA register indicates

the source of the last reset, and RSTCLR allows clearing of the

RSTSTA register. These registers can be used during a reset

exception service routine to identify the source of the reset. If

RSTSTA is null, the reset is external.

Default value: 0x00

Access:

Read/write

Table 38. RSTCFG MMR Bit Designations

Bit

Description

The RSTCFG register allows different peripherals to retain their

state after a watchdog or software reset.

7 to 3 Reserved. Always set to 0.

2

This bit is set to 1 to configure the DAC outputs to retain

their state after a watchdog or software reset.

This bit is cleared for the DAC pins and registers to

return to their default state.

RSTSTA Register

Name:

RSTSTA

1

0

Reserved. Always set to 0.

Address:

0xFFFF0230

This bit is set to 1 to configure the GPIO pins to retain

their state after a watchdog or software reset.

This bit is cleared for the GPIO pins and registers to

return to their default state.

Default value: 0x01

Access: Read/write

Rev. E | Page 42 of 96

Data Sheet

ADuC7023

RSTKEY1 Register

Table 39. RSTCFG Write Sequence

Name

Code

Name:

RSTKEY1

RSTCFG

RSTKEY2

0x76

Address:

Default value:

Access

0xFFFF0248

0xXX

User value

0xB1

Write

RSTKEY2Register

Name:

RSTKEY2

0xFFFF0250

0xXX

Address:

Default value:

Access:

Write

Rev. E | Page 43 of 96

ADuC7023

Data Sheet

OTHER ANALOG PERIPHERALS

DACxDAT Registers

DAC

Name

Address

Default Value

Access

R/W

The ADuC7023 incorporates four, 12-bit voltage output DACs

on chip. Each DAC has a rail-to-rail voltage output buffer

capable of driving 5 kΩ/100 pF.

DAC0DAT

DAC1DAT

DAC2DAT

DAC3DAT

0xFFFF0604

0xFFFF060C

0xFFFF0614

0xFFFF061C

0x00000000

Each DAC has two selectable ranges: 0 V to V_REF(internal band

gap 2.5 V reference) and 0 V to AV_DD.

Table 41. DAC0DAT MMR Bit Designations

The signal range is 0 V to AV_DD.

Bit

Description

By setting RSTCFG Bit 2, the DAC output pins can retain their

state during a watchdog or software reset.

31 to 28

27 to 16

15 to 0

Reserved.

12-bit data for DAC0.

Reserved.

MMRs Interface

Each DAC is independently configurable through a control

register and a data register. These two registers are identical for

the four DACs. Only DAC0CON (see Table 40) and DAC0DAT

(see Table 41) are described in detail in this section.

Using the DACs

The on-chip DAC architecture consists of a resistor string DAC

followed by an output buffer amplifier. The functional equivalent

is shown in Figure 32.

DACxCON Registers

Name

Address

Default Value

0x00

Access

R/W

AV

DD

REF

DAC0CON

DAC1CON

DAC2CON

DAC3CON

0xFFFF0600

0xFFFF0608

0xFFFF0610

0xFFFF0618

V

DAC

R

DAC0

Table 40. DAC0CON MMR Bit Designations

Bit

Value Name

Description

7

Reserved.

6

DACBY

This bit is set to bypass the DAC

output buffer.

This bit is cleared to enable the

DAC output buffer.

R

5

4

DACCLK DAC update rate.

This bit is set by the user to update

the DAC using Timer1.

This bit is cleared by the user to

update the DAC using HCLK (core

clock).

Figure 32. DAC Structure

As illustrated in Figure 32, the reference source for each DAC

is user-selectable in software. It can be either AV_DDor V_REF. In

0-to-AV_DDmode, the DAC output transfer function spans from

0 V to the voltage at the AV_DDpin. In 0-to-V_REFmode, the DAC

output transfer function spans from 0 V to the internal 2.5 V

DACCLR DAC clear bit.

This bit is set by the user to enable

normal DAC operation.

This bit is cleared by the user to

reset data register of the DAC to 0.

reference, V_REF

.

The DAC output buffer amplifier features a true, rail-to-rail

output stage implementation. This means that when unloaded,

each output is capable of swinging to within less than 5 mV of

both AV_DDand ground. Moreover, the DAC linearity specification

(when driving a 5 kꢀ resistive load to ground) is guaranteed

through the full transfer function except Code 0 to Code 100,

and, in 0-to-AV_DDmode only, Code 3995 to Code 4095.

3

Reserved. This bit remains at 0.

DAC range bits.

Power-down mode. The DAC

output is in tristate.

Reserved.

0 V to V_REF(2.5 V) range.

0 V to AV_DDrange.

2

1 to 0

00

01

10

11

Linearity degradation near ground and V_DDis caused by saturation

of the output amplifier, and a general representation of its effects

(neglecting offset and gain error) is illustrated in Figure 33. The

dotted line in Figure 33 indicates the ideal transfer function, and

the solid line represents what the transfer function may look like

with endpoint nonlinearities due to saturation of the output

amplifier. Figure 33 represents a transfer function in 0-to-AV_DD

Rev. E | Page 44 of 96

Data Sheet

ADuC7023

mode only. In 0-to-V_REFmode (with V_REF< AV_DD), the lower

nonlinearity is similar. However, the upper portion of the transfer

function follows the ideal line right to the end (V_REFin this case,

not AV_DD), showing no signs of endpoint linearity errors.

Configuring DAC Buffers in Op Amp Mode

In op amp mode, the DAC output buffers are used as an op amp

with the DAC itself disabled.

If DACBCFG Bit 0 is set, ADC0 is the positive input to the op

amp, ADC1 is the negative input, and DAC0 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC0CON.

AV

DD

AV – 100mV

DD

If DACBCFG Bit 1 is set, ADC2 is the positive input to the op

amp, ADC3 is the negative input, and DAC1 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC1CON.

If DACBCFG Bit 2 is set, ADC4 is the positive input to the op

amp, ADC5 is the negative input, and DAC2 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC2CON.

100mV

0x00000000

0x0FFF0000

Figure 33. Endpoint Nonlinearities Due to Amplifier Saturation

The endpoint nonlinearities conceptually illustrated in Figure 33

get worse as a function of output loading. Most of the ADuC7023

data sheet specifications assume a 5 kΩ resistive load to ground

at the DAC output. As the output is forced to source or sink more

current, the nonlinear regions at the top or bottom of Figure 33

become larger, respectively. With larger current demands, this

can significantly limit output voltage swing.

If DACBCFG Bit 3 is set, ADC8 is the positive input to the op

amp, ADC9 is the negative input, and DAC3 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC3CON.

DACBCFG Register

Name:

DACBCFG

0xFFFF0654

0x00

References to ADC and the DACs

Address:

Default value:

Access:

ADC and DACs can be configured to use internal V_REFor an

external reference as a reference source. Internal V_REFmust

work with an external 0.47 µF capacitor. Note that if an external

reference is used, the DACs will no longer meet offset and gain

specifications. If an external reference is required for the ADC,

then the DACs should be configured to use the 0 to AV_DDrange.

Read/write

Table 43. DACBCFG MMR Bit Designations

Bit

7 to 4

3

Description

Reserved. Always set to 0.

Table 42. Reference Source Selection for ADC and DAC

This bit is set to 1 to configure DAC3 output

buffer in op amp mode.

REFCON Bit 0

DACxCON[1:0]

Description

0

00

ADC works with external

This bit is cleared for the DAC buffer to operate

as normal.

reference. DACs power down.

0

01

10

11

Reserved.

2

1

0

This bit is set to 1 to configure DAC2 output

buffer in op amp mode.

This bit is cleared for the DAC buffer to operate

as normal.

ADC works with external

reference. DACs work with

internal AV_DD.

This bit is set to 1 to configure DAC1 output

buffer in op amp mode.

This bit is cleared for the DAC buffer to operate

as normal.

1

00

01

ADC works with internal

V_REF. DACs power down.

ADC and DACs work with an

external reference. The

external reference must be

capable of overdriving the

internal reference.

This bit is set to 1 to configure DAC0 output

buffer in op amp mode.

This bit is cleared for the DAC buffer to operate

as normal.

1

10

11

ADC and DACs work with

internal V_REF

ADC works with internal V_REF.

DACs work with internal AV_DD.

Rev. E | Page 45 of 96

ADuC7023

Data Sheet

Table 45. PSMCON MMR Bit Descriptions

Bit Name Description

DACBKEY0 Register

Name:

DACBKEY0

0xFFFF0650

0x0000

3

CMP

Comparator bit. This is a read-only bit that

directly reflects the state of the comparator.

Read 1 indicates the IOV_DDsupply is above its

selected trip point, or the PSM is in power-down

mode. Read 0 indicates the IOV_DDsupply is

below its selected trip point. This bit should be

set before leaving the interrupt service routine.

Address:

Default value:

Access:

Write

DACBKEY1 Register

2

1

TP

Trip point selection bits.

0 = 2.79 V.

1 = reserved.

Name:

DACBKEY1

0xFFFF0658

0x0000

Address:

PSMEN Power supply monitor enable bit.

This bit is set to 1 to enable the power supply

monitor circuit.

This bit is cleared to 0 to disable the power

supply monitor circuit.

Default value:

Access:

Write

0

PSMI

Power supply monitor interrupt bit. This bit is set

high by the MicroConverter once CMP goes low,

indicating low I/O supply. The PSMI bit can be

used to interrupt the processor. Once CMP

returns high, the PSMI bit can be cleared by

writing a 1 to this location. A 0 write has no

effect. There is no timeout delay; PSMI can be

immediately cleared once CMP goes high.

Table 44. DACBCFG Write Sequence

Name

Code

DACBKEY0

DACBCFG

DACBKEY1

0x9A

User value

0x0C

POWER SUPPLY MONITOR

The power supply monitor regulates the IOV_DDsupply on the

ADuC7023. It indicates when the IOV_DDsupply pin drops

below a supply trip point. The monitor function is controlled

via the PSMCON register. If enabled in the IRQEN or FIQEN

register, the monitor interrupts the core using the PSMI bit in

the PSMCON MMR. This bit is immediately cleared when

CMP goes high.

COMPARATOR

The ADuC7023 integrates voltage comparators. The positive

input is multiplexed with ADC2, and the negative input has two

options: ADC3 or DAC0. The output of the comparator can be

configured to generate a system interrupt, be routed directly to

the programmable logic array, start an ADC conversion, or be

on an external pin, COMP_OUT, as shown in Figure 34.

This monitor function allows the user to save working registers

to avoid possible data loss due to low supply or brownout

conditions. It also ensures that normal code execution does not

resume until a safe supply level has been established.

IRQ

ADC2/CMP0

MUX

ADC3/CMP1

MUX

PSMCON Register

DAC0

Name:

PSMCON

0xFFFF0440

0x0008

P0.5/COMP

OUT

Address:

Default value:

Access:

Figure 34. Comparator

Hysteresis

Figure 35 shows how the input offset voltage and hysteresis

terms are defined. Input offset voltage (V_OS) is the difference

between the center of the hysteresis range and the ground level.

This can either be positive or negative. The hysteresis voltage

(V_H) is ½ the width of the hysteresis range.

Read/write

COMP

OUT

V

H

CMP0

V

OS

Figure 35. Comparator Hysteresis Transfer Function

Rev. E | Page 46 of 96

Data Sheet

ADuC7023

Comparator Interface

The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 46.

CMPCON Register

Name:

CMPCON

0xFFFF0444

0x0000

Address:

Default value:

Access:

Read/write

Table 46. CMPCON MMR Bit Descriptions

Bit

Value Name

Description

15 to 11

10

Reserved.

CMPEN

Comparator enable bit.

This bit is set by the user to enable the comparator.

This bit is cleared by the user to disable the comparator.

9 to 8

7 to 6

CMPIN

Comparator negative input select bits.

AV_DD/2.

ADC3 input.

DAC0 output.

00

01

10

11

Reserved.

CMPOC

00

Comparator output configuration bits.

Reserved.

01

10

Output on COMP_OUT

.

11

IRQ.

5

CMPOL

Comparator output logic state bit. When low, the comparator output is high if the positive input (CMP0)

is above the negative input (CMP1). When high, the comparator output is high if the positive input is

below the negative input.

4 to 3

CMPRES

00

Response time.

5 µs response time typical for large signals (2.5 V differential).

17 µs response time typical for small signals (0.65 mV differential).

11

3 µs typical.

Reserved.

01/10

CMPHYST

2

1

0

Comparator hysteresis bit.

This bit is set by the user to have a hysteresis of about 7.5 mV.

This bit is cleared by the user to have no hysteresis.

Comparator output rising edge interrupt.

This bit is set automatically when a rising edge occurs on the monitored voltage (CMP0).

This bit is cleared by the user by writing a 1 to this bit.

Comparator output rallying edge interrupt.

CMPORI

CMPOFI

This bit is set automatically when a falling edge occurs on the monitored voltage (CMP0).

This bit is cleared by user.

Rev. E | Page 47 of 96

ADuC7023

Data Sheet

The selection of the clock source is in the PLLCON register. By

default, the part uses the internal oscillator feeding the PLL.

OSCILLATOR AND PLL—POWER CONTROL

Clocking System

In noisy environments, noise can couple to the external crystal

pins, and PLL may quickly lose lock. A PLL interrupt is

provided in the interrupt controller. The core clock is immediately

halted, and this interrupt is only serviced when the lock is restored.

Each ADuC7023 integrates a 32.768 kHz 3% oscillator, a clock

divider, and a PLL. The PLL locks onto a multiple (1275) of the

internal oscillator or an external 32.768 kHz crystal to provide a

stable 41.78 MHz clock (UCLK) for the system. To allow power

saving, the core can operate at this frequency, or at binary

In case of crystal loss, use the watchdog timer. During

initialization, a test on the RSTSTA can determine if the reset

came from the watchdog timer.

submultiples of it. The actual core operating frequency, UCLK/2^CD

is referred to as HCLK. The default core clock is the PLL clock

divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency

can also come from an external clock on the ECLK pin as

described in Figure 36.

,

Power Control System

A choice of operating modes is available on the ADuC7023.

Table 47 describes what part is powered on in the different

modes and indicates the power-up time.

INTERNAL

32kHz*

OSCILLATOR

XCLKO

XCLKI

CRYSTAL

OSCILLATOR

WATCHDOG

TIMER

Table 48 gives some typical values of the total current consumption

(analog + digital supply currents) in the different modes,

depending on the clock divider bits. The ADC is turned off.

Note that these values also include current consumption of the

regulator and other parts on the test board where these values

are measured.

TIMERS

AT POWER UP

32.768kHz

OCLK

41.78MHz

PLL

P1.2/XCLK

MDCLK

UCLK

ANALOG

PERIPHERALS

2

I C

CD

/2

CD

CORE

HCLK

*32.768kHz ±3%

P1.2/ECLK

Figure 36. Clocking System

Table 47. Operating Modes

Mode

Active

Pause

Nap

Sleep

Stop

Core

Peripherals

PLL

X

XTAL/T2/T3

IRQ0 to IRQ3

Start-Up/Power-On Time

66 ms at CD = 0

230 ns at CD = 0; 3 µs at CD = 7

283 ns at CD = 0; 3 µs at CD = 7

1.23 ms

Yes

X

1.45 ms

X = don’t care.

Table 48. Typical Current Consumption at 25°C in mA

PC[2:0]

Mode

Active

Pause

Nap

CD = 0

CD = 1

CD = 2

CD = 3

CD = 4

CD = 5

7.5

4.6

CD = 6

7.2

4.6

CD = 7

7

4.6

000

001

010

28

14

5

17

9

4.5

12

7.6

4.5

11

5.7

4.5

9.3

4.8

4.5

011

100

Sleep

Stop

0.23

Rev. E | Page 48 of 96

Data Sheet

ADuC7023

MMRs and Keys

POWKEY1 Register

The operating mode, clocking mode, and programmable clock

divider are controlled via three MMRs, PLLCON (see Table 49)

and POWCONx. PLLCON controls the operating mode of the

clock system, POWCON0 controls the core clock frequency and

the power-down mode, POWCON1 controls the clock

frequency to I²C and SPI.

Name:

POWKEY1

Address:

Default value:

Access:

0xFFFF0404

0xXXXX

Write

To prevent accidental programming, a certain sequence has to

be followed to write to the PLLCON and POWCONx registers.

Function:

POWKEY1 prevents accidental

programming to POWCON0.

PLLKEY1 Register

Name:

PLLKEY1

POWKEY2 Register

Name

POWKEY2

0xFFFF040C

0xXXXX

Write

Address:

0xFFFF0410

Address

Default value: 0xXXXX

Access: Write

Default value

Access

PLLKEY2 Register

Function:

POWKEY2 prevents accidental

programming to POWCON0.

Name:

PLLKEY2

Address:

0xFFFF0418

POWCON0 Register

Default value: 0xXXXX

Access: Write

Name:

POWCON0

Address:

Default value:

Access:

0xFFFF0408

0x00

PLLCON Register

Name:

PLLCON

Read/write

Address:

0xFFFF0414

Table 51. POWCON0 MMR Bit Designations

Default value: 0x21

Bit

Value

Name

Description

7

Reserved.

Access:

Read/write

6 to 4

PC

Operating modes.

Active mode.

Pause mode.

Nap.

Sleep mode. IRQ0 to IRQ3 can wake

up the part.

Table 49. PLLCON MMR Bit Designations

000

001

010

011

Bit

7 to 6

5

Value Name

Description

Reserved.

OSEL

32 kHz PLL input selection. This bit

is set by the user to select the internal

32 kHz oscillator. This bit is set by

default. This bit is cleared by the user

to select the external 32 kHz crystal.

100

Stop mode. IRQ0 to IRQ3 can wake

up the part.

Others

Reserved.

4 to 2

1 to 0

Reserved.

3

Reserved.

MDCLK Clocking modes.

2 to 0

CD

CPU clock divider bits.

41.78 MHz.

20.89 MHz.

10.44 MHz.

5.22 MHz.

2.61 MHz.

1.31 MHz.

653 kHz.

326 kHz.

00

01

10

11

Reserved.

PLL default configuration.

Reserved.

External clock on Pin 33 (40-lead

LFCSP)/Pin 25 (32-lead LFCSP).

000

001

010

011

100

101

110

111

Table 50. PLLCON Write Sequence

Name

Code

PLLKEY1

PLLCON

PLLKEY2

0xAA

User value

0x55

Rev. E | Page 49 of 96

ADuC7023

Data Sheet

Table 52. POWCON0 Write Sequence

Table 53. POWCON1 MMR Bit Designations

Name

Code

Bit

Value

Name

Description

POWKEY1

POWCON0

POWKEY2

0x01

User value

0xF4

15 to 9

8

Reserved.

SPIPO

Clearing this bit powers

down the SPI.

7 to 6

SPICLKDIV

SPI block driving clock

divider bits.

POWKEY3 Register

00

01

10

11

41.78 MHz.

20.89 MHz.

10.44 MHz.

5.22 MHz.

Name:

POWKEY3

Address:

Default value:

Access:

0xFFFF0434

0xXXXX

Write

5

I2C1PO

Clearing this bit powers

down the I²C1.

4 to 3

I2C1CLKDIV I²C0 block driving clock

divider bits.

Function:

POWKEY3 prevents accidental

programming to POWCON1.

00

01

10

11

41.78 MHz.

10.44 MHz.

5.22 MHz.

1.31 MHz.

POWKEY4 Register

Name

POWKEY4

2

I2C0PO

Clearing this bit powers

down the I²C0.

Address

Default Value

Access

0xFFFF043C

0xXXXX

Write

1 to 0

I2C0CLKDIV I²C1 block driving clock

divider bits.

00

01

10

11

41.78 MHz.

10.44 MHz.

5.22 MHz.

1.31 MHz.

Function:

POWKEY4 prevents accidental

programming to POWCON1.

¹Divided clock for SPI/I2C0/I2C1 must be greater than or equal to the CPU

clock as selected by POWCON0[2:0]

POWCON1 Register

Table 54. POWCON1 Write Sequence

Name:

POWCON1

Name

Code

POWKEY3

POWCON1

POWKEY4

0x76

User value

0XB1

Address:

Default value:

Access:

0xFFFF0438

0x0004

Read/write

Rev. E | Page 50 of 96

Data Sheet

ADuC7023

DIGITAL PERIPHERALS

GENERAL-PURPOSE INPUT/OUTPUT

GPxCON Registers

Name

Address

Default Value

0x00001111

0x00000000

Access

R/W

The ADuC7023 provides up to 20 general-purpose, bidirectional

I/O (GPIO) pins. All I/O pins apart from the pins shared with the

ADC are 5 V tolerant, meaning the GPIOs support an input voltage

of 5 V. The shared ADC pins only support an input up to AVDD.

In general, many of the GPIO pins have multiple functions (see

Table 55 for the pin function definitions). By default, the GPIO

pins are configured in GPIO mode.

GP0CON

GP1CON

GP2CON

0xFFFFF400

0xFFFFF404

0xFFFFF408

R/W

GPxCON are the Port x control registers, which select the

function of each pin of Port x as described in Table 56.

Table 56. GPxCON MMR Bit Descriptions

Bit

All GPIO pins have an internal pull-up resistor (of about 100 kΩ)

and their drive capability is 1.6 mA. Note that a maximum of

20 GPIOs can drive 1.6 mA at the same time. Using the GPxPAR

registers, it is possible to enable/disable the pull-up resistors.

Description

31 to 30

29 to 28

27 to 26

25 to 24

23 to 22

21 to 20

19 to 18

17 to 16

15 to 14

13 to 12

11 to 10

9 to 8

Reserved.

Select function of Px.7 pin.

Reserved.

Select function of Px.6 pin.

Reserved.

Select function of Px.5 pin.

Reserved.

Select function of Px.4 pin.

Reserved.

Select function of Px.3 pin.

Reserved.

Select function of Px.2 pin.

Reserved.

The 20 GPIOs are grouped in three ports, Port 0 to Port 2 (Port x).

Each port is controlled by four or five MMRs.

The input level of any GPIO can be read at any time in the

GPxDAT MMR, even when the pin is configured in a mode

other than GPIO. The PLA input is always active.

When the ADuC7023 part enters a power-saving mode, the

GPIO pins retain their state. Also note, that by setting RSTCFG

bit 0, the GPIO pins can retain their state during a watchdog or

software reset.

7 to 6

5 to 4

3 to 2

1 to 0

Select function of Px.1 pin.

Reserved.

Select function of Px.0 pin.

Table 55. GPIO Pin Function Descriptions

Configuration

Port

00

01

10

11

0

P0.0

P0.1¹

P0.2¹

P0.3¹

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2³

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

GPIO/BM

GPIO

nTRST

TDO

ADC_BUSY

PLAI[8]

PLAI[9]

PLAO[8]

PLAO[9]

PLAI[0]

PLAI[1]

PLAI[2]

PLAO[0]

PLAO[1]

PLAO[2]

PLAI[3]

PLAI[4]

PLAO[3]

GP0PAR Register

Name

GP0PAR

GPIO

TDI

GPIO

TCK

Address

0xFFFFF42C

0x22220000

Read/write

GPIO/IRQ0

GPIO

SCL0

SDA0

MISO

MOSI

SCLK

SS

CONV_START

COMP_OUT

SCL1²

Default value

Access

GPIO

SDA1²

1

GPIO

PWM0

PWM1

ECLK

Function

GP0PAR programs the parameters for Port 0,

Port 1, and Port 2. Note that the GP0DAT

MMR must always be written after changing

the GP0PAR MMR.

GPIO/IRQ1

GPIO/IRQ2

GPIO/IRQ3

GPIO

ADC4

ADC5

ADC10

ADC6

SCL1⁴

SDA1⁴

ADC12

GPIO

PWM_TRIPINPUTPLAO[4]

GP1PAR Register

GPIO

PWM2

PWM3

PWM4

PLAI[5]

PLAI[6]

PLAI[7]

GPIO

Name

GP1PAR

2

GPIO

Address

Default value

Access

0xFFFFF43C

0x22000022

Read/write

P2.2

P2.3

P2.4

GPIO

ADC7

ADC8

ADC9

PWMsync

PLAO[6]

PLAO[7]

PLAI[10]

¹These pins should not be used by user code when debugging the part via

JTAG. See Table 36 for further details on how to configure these pins for

GPIO mode. The default value of these pins depends on the level of the

P0.0/BM pin during the last reset sequence.

Function

GP1PAR programs the parameters for Port 0,

Port 1, and Port 2. Note that the GP1DAT

MMR must always be written after changing

the GP1PAR MMR.

²I²C1 function is only available on the 32-lead and 36-ball packages.

³When configured in Mode 2, P1.2 is ECLK by default, or core clock output. To

configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.

⁴I²C1 function is only available on the 40-lead package.

Rev. E | Page 51 of 96

ADuC7023

Data Sheet

3.6

GP2PAR Register

3.4

3.2

3.0

2.8

Name

GP2PAR

Address

0xFFFFF44C

Default value 0x00000000

Access

Read/write

2.6

2.4

2.2

2.0

Function

GP2PAR programs the parameters for Port 0,

Port 1, and Port 2. Note that the GP2DAT

MMR must always be written after changing

the GP2PAR MMR.

HIGH DRIVE STRENGTH

MEDIUM DRIVE STRENGTH

LOW DRIVE STRENGTH

–24

–18

–12

–6

0

6

12

18

24

LOAD CURRENT (mA)

Table 57. GPxPAR MMR Bit Descriptions

Figure 37. Programmable Strength for High Level

Bit

Description

0.5

31

Reserved.

30 to 29

28

27

Drive strength Px.7

Pull-up disable Px.7.

Reserved.

0.4

0.3

0.2

0.1

0

26 to 26

24

23

22 to 21

20

19

Drive strength Px.6

Pull-up disable Px.6.

Reserved.

Drive strength Px.5

Pull-up disable Px.5.

Reserved.

–0.1

–0.2

HIGH DRIVE STRENGTH

MEDIUM DRIVE STRENGTH

LOW DRIVE STRENGTH

18 to 17

16

15

Drive strength Px.4

Pull-up disable Px.4.

Reserved.

–0.3

–0.4

–24

–18

–12

–6

0

6

12

18

24

LOAD CURRENT (mA)

14 to 13

12

11

10 to 9

8

7

6 to 5

4

3

Drive strength Px.3

Pull-up disable Px.3.

Reserved.

Drive strength Px.2

Pull-up disable Px.2.

Reserved.

Drive strength Px.1

Pull-up disable Px.1.

Reserved.

Figure 38. Programmable Strength for Low Level

The drive strength bits can be written one time only after reset.

More writing to related bits has no effect on changing drive

strength. The GPIO drive strength and pull-up disable is not

always adjustable for the GPIO port. Some control bits cannot be

changed (see Table 59).

Table 59. GPxPAR Control Bits Access Descriptions¹

2 to 1

0

Drive strength Px.0

Pull-up disable Px.0.

Bit

GP0PAR

GP1PAR

GP2PAR

31

Reserved

30 to 29

28

27

26 to 26

24

23

22 to 21

20

19

18 to 17

16

R/W

Reserved

R/W

Reserved

R/W

Reserved

R (b00)

R/W

Reserved

R/W

Reserved

R (b00)

R/W

Reserved

R (b00)

R/W

Reserved

R (b00)

Table 58. GPIO Drive Strength Control Bits Descriptions

Control Bits Value

Description

00

01

1x

Medium drive strength.

Low drive strength.

High drive strength.

R/W

15

14 to 13

12

Reserved

R (b00)

R/W

Reserved

R (b00)

R/W

Reserved

R (b00)

R/W

11

Reserved

Rev. E | Page 52 of 96

Data Sheet

ADuC7023

GP2SET Register

Bit

GP0PAR

GP1PAR

R (b00)

R/W

GP2PAR

R (b00)

R/W

10 to 9

8

R (b00)

R/W

Name:

GP2SET

Address:

0xFFFFF444

0x000000XX

Write

7

Reserved

R (b00)

R/W

Reserved

R (b00)

R/W

Reserved

R (b00)

R/W

Reserved

R (b00)

R/W

Reserved

R (b00)

6 to 5

4

3

2 to 1

0

Default value:

Access:

Function:

GP2SET is a data set Port x

register.

R (b0)

¹When P2.0 is configured as AIN12, the internal pull-up resistor cannot be

disabled.

Table 61. GPxSET MMR Bit Descriptions

Bit

GP0DAT Register

Name

Description

Address

Default Value

0x000000XX

Access

R/W

31 to 24

23 to 16

Reserved.

GP0DAT

GP1DAT

GP2DAT

0xFFFFF420

0xFFFFF430

0xFFFFF440

Data port x.

This bit is set to 1 by the user to set bit on Port x; this

bit also sets the corresponding bit in the GPxDAT

MMR.

This bit is cleared to 0 by the user; this bit does not

affect the data out.

R/W

GPxDAT are Port x configuration and data registers. They

configure the direction of the GPIO pins of Port x, set the

output value for the pins configured as output, and store the

input value of the pins configured as input.

15 to 0

Reserved.

Table 60. GPxDAT MMR Bit Descriptions

GP0CLR Registers

Bit

Description

Name:

GP0CLR

31 to 24

Direction of the data.

Address:

Default value:

Access:

0xFFFFF428

This bit is set to 1 by the user to configure the GPIO

pin as an output.

This bit is cleared to 0 by the user to configure the

GPIO pin as an input.

0x000000XX

Write

23 to 16

15 to 8

7 to 0

Port x data output.

Reflect the state of port x pins at reset (read only).

Port x data input (read only).

Function:

GP0CLR is a data clear Port x register.

GP1CLR Registers

GP0SET Register

Name:

GP1CLR

Name:

GP0SET

Address:

0xFFFFF438

Address:

0xFFFFF424

Default value:

Access:

0x000000XX

Default value:

Access:

0x000000XX

Write

Function:

GP1CLR is a data clear Port x register.

Function:

GP0SET is a data set Port x register.

GP2CLR Registers

GP1SET Register

Name:

GP2CLR

Name:

GP1SET

Address:

0xFFFFF448

Address:

0xFFFFF434

0x000000XX

Write

Default value:

Access:

0x000000XX

Default value:

Access:

Write

Function:

GP2CLR is a data clear Port x register.

Function:

GP1SET is a data set Port x

register.

Rev. E | Page 53 of 96

ADuC7023

Data Sheet

Table 62. GPxCLR MMR Bit Descriptions

The maximum speed of the SPI clock is independent on the

clock divider bits.

Bit

Description

31 to 24 Reserved.

In slave mode, the SPICON register must be configured with

the phase and polarity of the expected input clock. The slave

accepts data from an external master up to 10 Mbps.

23 to 16 Data port x clear bit.

This bit is set to 1 by the user to clear the bit on Port x;

this bit also clears the corresponding bit in the GPxDAT

MMR.

This bit is cleared to 0 by the user; this bit does not affect

the data out.

In both master and slave modes, data is transmitted on one edge

of the SCLK signal and sampled on the other. Therefore, it is

important that the polarity and phase are configured the same

for the master and slave devices.

15 to 0

Reserved.

SPI Chip Select ( Input) Pin

SS

SERIAL PERIPHERAL INTERFACE

SS

In SPI slave mode, a transfer is initiated by the assertion of

,

The ADuC7023 integrates a complete hardware serial peripheral

interface (SPI) on chip. SPI is an industry standard, synchronous

serial interface that allows eight bits of data to be synchronously

transmitted and simultaneously received, that is, full duplex up

to a maximum bit rate of 20 Mbps.

which is an active low input signal. The SPI port then transmits

and receives 8-bit data until the transfer is concluded by

SS

deassertion of . In slave mode, is always an input.

SS

In SPI master mode, the is an active low output signal. It

The SPI port can be configured for master or slave operation and

asserts itself automatically at the beginning of a transfer and

deasserts itself upon completion.

SS

typically consists of four pins: MISO, MOSI, SCLK, and SPI

.

Configuring External Pins for SPI Functionality

MISO (Master In, Slave Out) Pin

P1.1 is the slave chip select pin. In slave mode, this pin is an

input and must be driven low by the master. In master mode,

this pin is an output and goes low at the beginning of a transfer

and high at the end of a transfer.

The MISO pin is configured as an input line in master mode

and an output line in slave mode. The MISO line on the master

(data in) should be connected to the MISO line in the slave

device (data out). The data is transferred as byte wide (8-bit)

serial data, MSB first.

P1.0 is the SCLK pin.

MOSI (Master Out, Slave In) Pin

P0.6 is the master in, slave out (MISO) pin.

P0.7 is the master out, slave in (MOSI) pin.

The MOSI pin is configured as an output line in master mode

and an input line in slave mode. The MOSI line on the master

(data out) should be connected to the MOSI line in the slave

device (data in). The data is transferred as byte wide (8-bit)

serial data, MSB first.

To configure these pins for SPI mode, see the General-Purpose

Input/Output section.

SPI Registers

The following MMR registers control the SPI interface: SPISTA,

SPIRX, SPITX, SPIDIV, and SPICON.

SCLK (Serial Clock I/O) Pin

The master serial clock (SCLK) synchronizes the data being

transmitted and received through the MOSI SCLK period.

Therefore, a byte is transmitted/received after eight SCLK

periods. The SCLK pin is configured as an output in master

mode and as an input in slave mode.

SPI Status Register

Name:

SPISTA

Address:

0xFFFF0A00

In master mode, polarity and phase of the clock are controlled

by the SPICON register, and the bit rate is defined in the

SPIDIV register as follows:

Default value: 0x0000

Access:

Read

f_UCLK

2×(1+ SPIDIV)

Function:

This 32-bit MMR contains the status of the SPI

interface in both master and slave modes.

f_{SERIAL CLOCK}

=

where:

_UCLKis the clock selected by POWCON1 Bit 7 to Bit 6.

f

Rev. E | Page 54 of 96

Data Sheet

ADuC7023

Table 63. SPISTA MMR Bit Designations

Bit

Name

Description

15 to 12

11

Reserved bits.

SPIREX

SPI Rx FIFO excess bytes present.

This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON

This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE.

10 to 8

SPIRXFSTA[2:0] SPI Rx FIFO status bits.

[000] = Rx FIFO is empty.

[001] = 1 valid byte in the FIFO.

[010] = 2 valid byte in the FIFO.

[011] = 3 valid byte in the FIFO.

[100] = 4 valid byte in the FIFO.

7

SPIFOF

SPI Rx FIFO overflow status bit.

This bit is set when the Rx FIFO is full when new data is loaded to the FIFO. This bit generates an interrupt

except when SPIRFLH is set in SPICON.

This bit is cleared when the SPISTA register is read.

SPI Rx IRQ status bit.

This bit is set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the

required number of bytes have been received.

This bit is cleared when the SPISTA register is read.

SPI Tx IRQ status bit.

This bit is set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required

number of bytes have been transmitted.

6

SPIRXIRQ

SPITXIRQ

SPITXUF

5

This bit is cleared when the SPISTA register is read.

SPI Tx FIFO underflow.

4

This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt

except when SPITFLH is set in SPICON.

This bit is cleared when the SPISTA register is read.

3 to 1

SPITXFSTA[2:0] SPI Tx FIFO status bits.

[000] = Tx FIFO is empty.

[001] = 1 valid byte in the FIFO.

[010] = 2 valid byte in the FIFO.

[011] = 3 valid byte in the FIFO.

[100] = 4 valid byte in the FIFO.

0

SPIISTA

SPI interrupt status bit.

This bit is set to 1 when an SPI based interrupt occurs.

This bit is cleared after reading SPISTA.

SPITX Register

SPIRX Register

Name:

SPITX

Name:

SPIRX

Address:

0xFFFF0A08

Address:

0xFFFF0A04

Default value: 0xXX

Default value: 0x00

Access:

Write

Access:

Read

Function:

This 8-bit MMR is the SPI transmit register.

Function:

This 8-bit MMR is the SPI receive register.

Rev. E | Page 55 of 96

ADuC7023

Data Sheet

SPIDIV Register

SPI Control Register

Name:

SPIDIV

Name:

SPICON

Address:

0xFFFF0A0C

Address:

0xFFFF0A10

Default value: 0x00

Default value: 0x0000

Access:

Read/write

Access:

Read/write

Function:

This 6-bit MMR is the SPI baud rate selection

register. (Note that the maximum value of this

MMR is 0x3F.)

Function:

This 16-bit MMR configures the SPI peripheral

in both master and slave modes.

Rev. E | Page 56 of 96

Data Sheet

ADuC7023

Table 64. SPICON MMR Bit Designations

Bit

Name

Description

15 to SPIMDE

14

SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.

[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been

received into the FIFO.

[01] = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been

received into the FIFO.

[10] = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have

been received into the FIFO.

[11] = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full or four bytes

present.

13

12

11

SPITFLH

SPIRFLH

SPI Tx FIFO flush enable bit.

This bit is set to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.

If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit.

Any writes to the Tx FIFO are ignored while this bit is set.

This bit is cleared to disable Tx FIFO flushing.

SPI Rx FIFO flush enable bit.

This bit is set to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.

If this bit is set, all incoming data is ignored and no interrupts are generated.

If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.

This bit is cleared to disable Rx FIFO flushing.

SPICONT Continuous transfer enable.

This bit is set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in

the Tx register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty.

This bit is cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.

If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle.

10

9

SPILP

Loop back enable bit.

This bit is set by the user to connect MISO to MOSI and test software.

This bit is cleared by the user to be in normal mode.

SPIOEN

SPIROW

SPIZEN

Slave MISO output enable bit.

This bit is set for MISO to operate as normal.

This bit is cleared to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is clear.

SPIRX overflow overwrite enable.

This bit is set by the user; the valid data in the Rx register is overwritten by the new serial byte received.

This bit is cleared by the user; the new serial byte received is discarded.

SPI transmit zeros when Tx FIFO is empty.

8

7

This bit is set to transmit 0x00 when there is no valid data in the Tx FIFO.

This bit is cleared to transmit the last transmitted value when there is no valid data in the Tx FIFO.

6

SPITMDE SPI transfer and interrupt mode.

This bit is set by the user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.

This bit is cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.

LSB first transfer enable bit.

5

SPILF

This bit is set by the user; the LSB is transmitted first.

This bit is cleared by the user; the MSB is transmitted first.

4

SPIWOM SPI wired or mode enable bit.

This bit is set to 1 enable open-drain data output. External pull-ups are required on data out pins.

This bit is cleared for normal output levels.

3

SPICPO

SPICPH

Serial clock polarity mode bit.

This bit is set by the user; the serial clock idles high.

This bit is cleared by the user; the serial clock idles low.

Serial clock phase mode bit.

2

This bit is set by the user; the serial clock pulses at the beginning of each serial bit transfer.

This bit is cleared by the user; the serial clock pulses at the end of each serial bit transfer.

Rev. E | Page 57 of 96

ADuC7023

Data Sheet

Bit

Name

Description

1

SPIMEN

Master mode enable bit.

This bit is set by the user to enable master mode.

This bit is cleared by the user to enable slave mode.

SPI enable bit.

0

SPIEN

This bit is set by the user to enable the SPI.

This bit is cleared by the user to disable the SPI.

Rev. E | Page 58 of 96

Data Sheet

ADuC7023

I²C

The ADuC7023 incorporates two I²C peripherals that may be

configured as a fully I²C-compatible I²C bus master device or as

a fully I²C bus-compatible slave device.

SERIAL CLOCK GENERATION

The I²C master in the system generates the serial clock for a

transfer. The master channel can be configured to operate in

fast mode (400 kHz) or standard mode (100 kHz).

The two pins used for data transfer, SDA and SCL, are configured

in a wire-AND format that allows arbitration in a multimaster

system. These pins require external pull-up resistors. Typical

pull-up values are between 4.7 kΩ and 10 kΩ.

The I²C bus peripheral address in the I²C bus system is pro-

grammed by the user. This ID can be modified any time a

transfer is not in progress. The user can configure the interface

to respond to four slave addresses.

The transfer sequence of an I²C system consists of a master

device initiating a transfer by generating a start condition while

the bus is idle. The master transmits the slave device address

and the direction of the data transfer (read or/write) during the

initial address transfer. If the master does not lose arbitration

and the slave acknowledges the data, transfer is initiated. This

continues until the master issues a stop condition and the bus

becomes idle.

The bit rate is defined in the I2CDIV MMR as follows:

f_UCLK

f_{SERIAL CLOCK}

=

(2 + DIVH) +(2 + DIVL)

where:

_UCLKis the clock before the clock divider and the clock selected

f

by POWCON1 Bit 4 to Bit 0.

DIVH is the high period of the clock.

DIVL is the low period of the clock.

Thus, for 100 kHz operation,

DIVH = DIVL = 0xCF

and for 400 kHz,

DIVH = 0x28, DIVL = 0x3C

The I2CDIV register corresponds to DIVH:DIVL.

The I²C peripheral can only be configured as a master or slave

at any given time. The same I²C channel cannot simultaneously

support master and slave modes.

I²C BUS ADDRESSES

Slave Mode

In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and

I2CxID3 contain the device IDs. The device compares the four

I2CxIDx registers to the address byte received from the bus

master. To be correctly addressed, the 7MSBs of either ID

register must be identical to that of the 7MSBs of the first

received address byte. The LSB of the ID registers (the transfer

direction bit) is ignored in the process of address recognition.

The I²C interface on the ADuC7023 includes support for

repeated start conditions. In master mode, the ADuC7023 can

be programmed to generate a repeated start. In slave mode, the

ADuC7023 recognizes repeated start conditions. In master and

slave mode, the part recognizes both 7-bit and 10-bit bus addresses.

In I²C master mode, the ADuC7023 supports continuous reads

from a single slave up to 512 bytes in a single transfer sequence.

Clock stretching is supported in both master and slave modes.

In slave mode, the ADuC7023 can be programmed to return a

NACK. This allows the validation of checksum bytes at the end

of I2C transfers. Bus arbitration in master mode is supported.

Internal and external loopback modes are supported for I²C

hardware testing. In loopback mode. The transmit and receive

circuits in both master and slave mode contain 2-byte FIFOs.

Status bits are available to the user to control these FIFOs.

The ADuC7023 also supports 10-bit addressing mode. When

Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit

address is supported in slave mode and is stored in registers

I2CxID0 and I2CxID1. The 10-bit address is derived as follows:

I2CxID0[0] is the read/write bit and is not part of the I²C

address.

I2CxID0[7:1] = Address Bits[6:0].

I2CxID1[2:0] = Address Bits[9:7].

I2CxID1[7:3] must be set to 11110b.

Master Mode

CONFIGURING EXTERNAL PINS FOR I²C

FUNCTIONALITY

The I²C pins of the ADuC7023 device are P0.4 and P0.5 for I²C0

In master mode, the I2CxADR0 register is programmed with

the I²C address of the device.

and P0.6 and P0.7 for I²C1.

P0.4 and P0.6 are the I²C clock signals and P0.5 and P0.7 are the

I²C data signals. For instance, to configure I²C0 pins (SCL0,

SDA0), Bit 16 and Bit 20 of the GP0CON register must be set to

1 to enable I²C mode. On the other hand, to configure I²C1 pins

(SCL1, SDA1), Bit 25 and Bit 29 of the GP0CON register must

be set to 1 to enable I²C mode, as shown in the GPIO section.

I²C1 function is available at P0.6 and P0.7 on 32-lead and 36-

ball packages and available at P1.6 and P1.7 on 40-lead package.

In 7-bit address mode, I2CxADR0[7:1] are set to the device

address. I2CxADR0[0] is the read/write bit.

In 10-bit address mode, the 10-bit address is created as follows:

I2CxADR0[7:3] must be set to 11110b.

I2CxADR0[2:1] = Address Bits[9:8].

I2CxADR1[7:0] = Address Bits[7:0].

I2CxADR0[0] is the read/write bit.

Rev. E | Page 59 of 96

ADuC7023

Data Sheet

I²C REGISTERS

The I²C peripheral interfaces consists of a number of MMRs. These are described in the following section.

I²C Master Registers

I²C Master Control Registers, I2CxMCON

Name:

I2C0MCON, I2C1MCON

Address:

Default value:

Access:

0xFFFF0800, 0xFFFF0900

0x0000, 0x0000

Read/write

Function:

These 16-bit MMRs configure the I²C peripheral in master mode.

Table 65. I2CxMCON MMR Bit Designations

Bit

Name

Description

15 to 9

8

Reserved. These bits are reserved and should not be written to.

I²C transmission complete interrupt enable bit.

This bit is set to enable an interrupt on detecting a stop condition on the I²C bus.

This bit clears this interrupt source.

I2CMCENI

7

6

5

4

3

I2CNACKENI I²C no acknowledge received interrupt enable bit.

This bit is set to enable interrupts when the I²C master receives a no acknowledge.

This bit clears this interrupt source.

I2CALENI

I2CMTENI

I2CMRENI

I2CMSEN

I²C arbitration lost interrupt enable bit.

This bit is set to enable interrupts when the I²C master has lost in trying to gain control of the I²C bus.

This bit clears this interrupt source.

I²C transmit interrupt enable bit.

This bit is set to enable interrupts when the I²C master has transmitted a byte.

This bit clears this interrupt source.

I²C receive interrupt enable bit.

This bit is set to enable interrupts when the I²C master receives data.

This bit is cleared by the user to disable interrupts when the I²C master is receiving data.

I²C master SCL stretch enable bit.

This bit is set to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low

until I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.

This bit is cleared to disable clock stretching.

I²C internal loopback enable bit.

This bit is set to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to

their respective input signals.

This bit is cleared by the user to disable loopback mode.

I²C master backoff disable bit.

This bit is set to allow the device to compete for control of the bus even if another device is currently driving a

start condition.

2

1

0

I2CILEN

I2CBD

This bit is cleared to back off until the I²C bus becomes free.

I²C master enable bit.

I2CMEN

This bit is set by the user to enable I²C master mode.

This bit is cleared to disable I²C master mode.

Rev. E | Page 60 of 96

Data Sheet

ADuC7023

I²C Master Status Registers, I2CxMSTA

Name:

I2C0MSTA , I2C1MSTA

Address:

Default value:

Access:

0xFFFF0804, 0xFFFF0904

0x0000, 0x0000

Read

Function:

These 16-bit MMRs are the I²C status registers in master mode.

Table 66. I2CxMSTA MMR Bit Designations

Bit

Name

Description

15 to 11

10

Reserved. These bits are reserved.

I²C bus busy status bit.

I2CBBUSY

This bit is set to 1 when a start condition is detected on the I²C bus.

This bit is cleared when a stop condition is detected on the bus.

Master Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit is cleared in all other conditions.

I²C transmission complete status bit.

9

8

I2CMRxFO

I2CMTC

This bit is set to 1 when a transmission is complete between the master and the slave with which it was

communicating. If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit clears this interrupt source.

I²C master no acknowledge data bit.

7

I2CMNA

This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write

transfer. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

6

5

I2CMBUSY

I2CAL

I²C master busy status bit.

This bit is set to 1 when the master is busy processing a transaction.

This bit is cleared if the master is ready or if another master device has control of the bus.

I²C arbitration lost status bit.

This bit is set to 1 when the I²C master has lost in trying to gain control of the I²C bus. If the I2CALENI bit in

I2C1MCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I²C master no acknowledge address bit.

4

I2CMNA

This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If

the I2CNACKENI bit in I2C1MCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I²C master receive request bit.

This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2C1MCON is set, an interrupt is

generated.

This bit is cleared in all other conditions.

I²C master transmit request bit.

This bit becomes high if the Tx FIFO is empty or only contains one byte and the master has transmitted an

address and write. If the I2CMTENI bit in I2C1MCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I²C master Tx FIFO status bits.

00 = I²C master Tx FIFO empty.

01 = Reserved.

3

I2CMRXQ

I2CMTXQ

I2CMTFSTA

2

1 to 0

10 = 1 byte in master Tx FIFO.

11 = I²C master Tx FIFO full.

Rev. E | Page 61 of 96

ADuC7023

Data Sheet

I²C Master Receive Registers, I2CxMRX

I²C Master Current Read Count Registers, I2CxMCNT1

Name:

I2C0MRX, I2C1MRX

Name:

I2C0MCNT1, I2C1MCNT1

Address:

0xFFFF0808, 0xFFFF0908

Address:

0xFFFF0814, 0xFFFF0914

Default value: 0x00

Default value: 0x00, 0x00

Access:

Read only

Access:

Read

Function:

These 8-bit MMRs are the I²C master receive

registers.

Function:

These 8-bit MMRs hold the number of bytes

received thus far during a read sequence with a

slave device.

I²C Master Transmit Registers, I2CxMTX

I²C Address 0 Registers, I2CxADR0

Name:

I2C0MTX, I2C1MTX

Name:

I2C0ADR0, I2C1ADR0

Address:

0xFFFF080C 0xFFFF090C

Address:

0xFFFF0818, 0xFFFF0918

Default value: 0x00, 0x00

Default value: 0x00

Access:

Write only

Access:

Read/write

Function:

These 8-bit MMRs are the I²C master transmit

registers

Function:

These 8-bit MMRs hold the 7-bit slave address

and the read/write bit when the master begins

communicating with a slave.

I²C Master Read Count Registers, I2CxMCNT0

Name:

I2C0MCNT0, I2C1MCNT0

Table 68. I2CxADR0 MMR in 7-Bit Address Mode: Address =

0xFFFF0818, 0xFFFF0918. Default Value = 0x00

Address:

0xFFFF0810, 0xFFFF0910

Bit

Name

Description

Default value: 0x0000, 0x0000

7 to 1

I2CADR These bits contain the 7-bit address of the

required slave device.

Access:

Read/write

0

R/W

Bit 0 is the read/write bit.

When this bit = 1, a read sequence is

requested.

When this bit = 0, a write sequence is

requested.

Function:

These 16-bit MMRs hold the required number

of bytes when the master begins a read

sequence from a slave device.

Table 67. I2CxMCNT0 MMR Bit Descriptions: Address =

0xFFFF0810, 0xFFFF0910. Default Value = 0x0000

Table 69. I2CxADR0 MMR in 10-Bit Address Mode

Bit

Name

Description

Bit

Name

Description

7 to 3

These bits must be set to [11110b] in 10-bit

address mode.

15 to 9

8

Reserved.

I2CRECNT This bit is set if greater than 256 bytes are

required from the slave.

2 to 1

0

I2CMADR These bits contain ADDR[9:8] in 10-bit

address mode.

This bit is cleared when reading 256 bytes

or less.

R/W

Read/write bit.

When this bit = 1, a read sequence is

requested.

When this bit = 0, a write sequence is

requested.

7 to 0

I2CRCNT

These eight bits hold the number of bytes

required during a slave read sequence,

minus 1. If only a single byte is required,

these bits should be set to 0.

Rev. E | Page 62 of 96

Data Sheet

ADuC7023

I²C Address 1 Registers, I2CxADR1

Table 71. I2CxDIV MMR

Bit Name Description

15 to 8 DIVH

Name:

I2C0ADR1, I2C1ADR1

These bits control the duration of the high

period of SCL.

Address:

0xFFFF081C , 0xFFFF091C

7 to 0

DIVL

These bits control the duration of the low

period of SCL.

Default value: 0x00

Access:

Read/write

I²C Slave Registers

I²C Slave Control Registers, I2CxSCON

Function:

These 8-bit MMRs are used in 10-bit

addressing mode only. These registers contain

the least significant byte of the address.

Name:

I2C0SCON, I2C1SCON

Address:

0xFFFF0828, 0xFFFF0928

Table 70. I2CxADR1 MMR in 10-Bit Address Mode

Default value: 0x0000

Bit

Name

Description

Access:

Read/write

7 to 0 I2CLADR

These bits contain ADDR[7:0] in 10-bit

address mode.

Function:

These 16-bit MMRs configure the I²C

peripheral in slave mode.

I²C Master Clock Control Register, I2CxDIV

Name:

I2C0DIV, I2C1DIV

Address:

0xFFFF0824, 0xFFFF0924

Default value: 0x1F1F

Access:

Read/write

Function:

These MMRs control the frequency of the I²C

clock generated by the master on to the SCL

pin. For further details, see the I2C initial section.

Table 72. I2CxSCON MMR Bit Designations

Bit

Name

Description

15 to 11

10

Reserved bits.

I2CSTXENI

Slave transmit interrupt enable bit.

This bit is set to enable an interrupt after a slave transmits a byte.

This bit clears this interrupt source.

9

8

7

6

I2CSRXENI

I2CSSENI

Slave receive interrupt enable bit.

This bit is set to enable an interrupt after the slave receives data.

This bit clears this interrupt source.

I²C stop condition detected interrupt enable bit

This bit is set to enable an interrupt on detecting a stop condition on the I²C bus.

This bit clears this interrupt source.

I2CNACKEN

I2CSSEN

I²C no acknowledge enable bit.

This bit is set to no acknowledge the next byte in the transmission sequence.

This bit is cleared to let the hardware control the acknowledge/no acknowledge sequence.

I²C slave SCL stretch enable bit.

This bit is set to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low

until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.

This bit is cleared to disable clock stretching.

I²C early transmit interrupt enable bit.

5

I2CSETEN

This bit is set to enable a transmit request interrupt just after the positive edge of SCL during the read bit

transmission.

This bit is cleared to enable a transmit request interrupt just after the negative edge of SCL during the read bit

transmission.

Rev. E | Page 63 of 96

ADuC7023

Data Sheet

Bit

Name

Description

I²C general call status and ID clear bit.

4

I2CGCCLR

Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register.

This bit is cleared at all other times.

3

I2CHGCEN

I²C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having

received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT against

the receive register. If the contents match, the device has received a hardware general call. This is used if a

device needs urgent attention from a master device without knowing which master it needs to turn to. This is a

broadcast message to all master devices on the bus. The ADuC7023 watches for these addresses. The device

that requires attention embeds its own address into the message. All masters listen, and the one that can

handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be

written to 1, as per the I²C January 2000 bus specification.

This bit and I2CGCEN are set to enable hardware general call recognition in slave mode.

This bit is cleared to disable recognition of hardware general call commands.

2

I2CGCEN

I²C general call enable. This bit is set to enable the slave device to acknowledge an I²C general call, Address

0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of

the slave address by hardware) as the data byte, the I²C interface resets as per the I²C January 2000 bus

specification. This command can be used to reset an entire I²C system. If it receives a 0x04 (write programmable part

of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call.

The user must take corrective action by reprogramming the device address.

This bit is set to allow the slave acknowledge I²C general call commands.

This bit is cleared to disable recognition of general call commands.

I²C 10-bit address mode.

This bit is set to 1 to enable 10-bit address mode.

This bit is cleared to 0 to enable normal address mode.

I²C slave enable bit.

1

0

ADR10EN

I2CSEN

This bit is set by user to enable I²C slave mode.

This bit is cleared by the user to disable I²C slave mode.

I²C Slave Status Registers, I2CxSSTA

Name:

I2C0SSTA, I2C1SSTA

Address:

Default value:

Access:

0xFFFF082C, 0xFFFF092C

0x0000, 0x0000

Read/write

Function:

These 16-bit MMRs are the I²C status registers in slave mode.

Rev. E | Page 64 of 96

Data Sheet

ADuC7023

Table 73. I2CxSSTA MMR Bit Designations

Bit

15

14

Name

Description

Reserved bit.

I2CSTA

This bit is set to 1 if: A start condition followed by a matching address is detected. It is also set if a start

byte (0x01) is received. If general calls are enabled and a general call code of (0x00) is received.

This bit is cleared on receiving a stop condition.

This bit is set to 1 if a repeated start condition is detected.

This bit is cleared on receiving a stop condition.

13

I2CREPS

12 to 11

I2CID[1:0]

I²C address matching register. These bits indicate which I2CxIDx register matches the received address.

[00] = received address matches I2CxID0.

[01] = received address matches I2CxID1.

[10] = received address matches I2CxID2.

[11] = received address matches I2CxID3.

10

I2CSS

I²C stop condition after start detected bit.

This bit is set to 1 when a stop condition is detected after a previous start and matching address.

When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated.

This bit is cleared by reading this register.

9 to 8

I2CGCID[1:0] I²C general call ID bits.

[00] = no general call received.

[01] = general call reset and program address.

[10] = general program address.

[11] = general call matching alternative ID.

These bits are not cleared by a general call reset command.

These bits are cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.

I²C general call status bit.

7

I2CGC

This bit is set to 1 if the slave receives a general call command of any type. If the command received is a

reset command, then all registers return to their default state. If the command received is a hardware

general call, the Rx FIFO holds the second byte of the command, and this can be compared with the

I2CxALT register.

This bit is cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.

I²C slave busy status bit.

This bit is set to 1 when the slave receives a start condition.

This bit is cleared by hardware if the received address does not match any of the I2CxIDx registers, the

slave device receives a stop condition or if a repeated start address does not match any of the I2CxIDx

registers.

I²C slave no acknowledge data bit.

6

5

I2CSBUSY

I2CSNA

This bit is set to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted

under the following conditions: if no acknowledge is returned because there is no data in the Tx FIFO or if

the I2CNACKEN bit is set in the I2CxSCON register.

This bit is cleared in all other conditions.

Slave Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit is cleared in all other conditions.

I²C slave receive request bit.

4

3

I2CSRxFO

I2CSRXQ

This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur if the

I2CSRXENI bit in I2CxSCON is set.

The Rx FIFO must be read or flushed to clear this bit.

I²C slave transmit request bit.

2

I2CSTXQ

This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in

I2CxSCON is = 0, , this bit goes high just after the negative edge of SCL during the read bit transmission. If

the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the read

bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCON is set.

This bit is cleared in all other conditions.

Rev. E | Page 65 of 96

ADuC7023

Data Sheet

Bit

Name

Description

I²C slave FIFO underflow status bit.

1

I2CSTFE

This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at

the rising edge of SCL during the read bit.

This bit is cleared in all other conditions.

I²C slave early transmit FIFO status bit.

0

I2CETSTA

If the I2CSETEN bit in I2CxSCON is = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in

I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission.

This bit asserts once only for a transfer.

This bit is cleared after being read.

I²C Slave Receive Registers, I2CxSRX

I²C Slave Device ID Registers, I2CxIDx

Name:

I2C0SRX, I2C1SRX

Name:

I2C0IDx, I2C1IDx

Address:

0xFFFF0830, 0xFFFF0930

Addresses:

0xFFFF093C = I2C1ID0

0xFFFF083C = I2C0ID0

Default value: 0x00

0xFFFF0940 = I2C1ID1

0xFFFF0840 = I2C0ID1

Access:

Read

Function:

These 8-bit MMRs are the I²C slave receive

register.

0xFFFF0944 = I2C1ID2

0xFFFF0844 = I2C0ID2

0xFFFF0948 = I2C1ID3

0xFFFF0848 = I2C0ID3

I²C Slave Transmit Registers, I2CxSTX

Name:

I2C0STX, I2C1STX

Default value: 0x00

Address:

0xFFFF0834, 0xFFFF0934

Access:

Read/write

Default value: 0x00

Function:

These 8-bit MMRs are programmed with I²C

bus IDs of the slave. See the I²C Bus Addresses

section for further details.

Access:

Write

Function:

These 8-bit MMRs are the I²C slave transmit

registers.

I²C Common Registers

I²C FIFO Status Registers, I2CxFSTA

I²C Hardware General Call Recognition Registers,

I2CxALT

Name:

I2C0FSTA, I2C1FSTA

Name:

I2C0ALT, I2C1ALT

Address:

0xFFFF084C, 0xFFFF094C

Address:

0xFFFF0838, 0xFFFF0938

Default value: 0x0000

Default value: 0x00

Access:

Read/write

Access:

Read/write

Function:

These 16-bit MMRs contain the status of the

Rx/Tx FIFOs in both master and slave modes.

Function:

These 8-bit MMRs are used with hardware

general calls when the I2CxSCON Bit 3 is set to 1.

These registers are used in cases where a master is

unable to generate an address for a slave, and

instead, the slave must generate the address for

the master.

Rev. E | Page 66 of 96

Data Sheet

ADuC7023

Table 74. I2CxFSTA MMR Bit Designations

The PLA is configured via a set of user MMRs. The output(s) of

the PLA can be routed to the internal interrupt system, to the

Bit

Name

Description

CONV_START

eight PLA output pins.

signal of the ADC, to an MMR, or to any of the

15 to 10

9

Reserved bits.

I2CFMTX

I2CFSTX

This bit is set to 1 to flush the master

Tx FIFO.

Table 75. Element Input/Output

8

This bit is set to 1 to flush the slave Tx

FIFO.

I²C master receive FIFO status bits.

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = 1 byte in FIFO.

[11] = FIFO full.

I²C master transmit FIFO status bits.

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = 1 byte in FIFO.

[11] = FIFO full.

I²C slave receive FIFO status bits.

[00] = FIFO empty

[01] = byte written to FIFO

[10] = 1 byte in FIFO

[11] = FIFO full

I²C slave transmit FIFO status bits.

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = 1 byte in FIFO.

PLA Block 0

PLA Block 1

Input

P0.0

P0.1

P2.4

NC

Element

Input

P0.4

P0.5

P0.6

P1.2

P1.3

P1.6

P1.7

P2.0

Output

P0.7

P1.0

P1.1

P1.4

Element

Output

P0.2

P0.3

P2.5¹

NC

7 to 6

I2CMRXSTA

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

P1.5

P2.1¹

NC

5 to 4

3 to 2

1 to 0

I2CMTXSTA

I2CSRXSTA

I2CSTXSTA

P2.2

NC

P2.3

NC

¹Internal pins only. Read via GPxDAT register.

PLA MMRs Interface

The PLA peripheral interface consists of the 22 MMRs

described in the following sections.

PLAELMx Registers

PLAELMx are Element 0 to Element 15 control registers. They

configure the input and output mux of each element, select the

function in the look-up table, and bypass/use the flip-flop (see

Table 77).

[11] = FIFO full.

Table 76. PLAELMx Registers

Name

Address

Default Value

0x0000

Access

R/W

PROGRAMMABLE LOGIC ARRAY (PLA)

PLAELM0

PLAELM1

PLAELM2

PLAELM3

PLAELM4

PLAELM5

PLAELM6

PLAELM7

PLAELM8

PLAELM9

PLAELM10

PLAELM11

PLAELM12

PLAELM13

PLAELM14

PLAELM15

0xFFFF0B00

0xFFFF0B04

0xFFFF0B08

0xFFFF0B0C

0xFFFF0B10

0xFFFF0B14

0xFFFF0B18

0xFFFF0B1C

0xFFFF0B20

0xFFFF0B24

0xFFFF0B28

0xFFFF0B2C

0xFFFF0B30

0xFFFF0B34

0xFFFF0B38

0xFFFF0B3C

Every ADuC7023 integrates a fully programmable logic array

(PLA) consisting of sixteen PLA elements.

Each PLA element contains a two-input look-up table that can

be configured to generate any logic output function based on

two inputs and a flip-flop. This is represented in Figure 39.

0

4

A

2

LOOK-UP

TABLE

B

3

1

Figure 39. PLA Element

In total, 20 GPIO pins are available on the ADuC7023 for the

PLA. These include 11 input pins and nine output pins, which

need to be configured in the GPxCON register as PLA pins before

using the PLA.

Rev. E | Page 67 of 96

ADuC7023

Data Sheet

Table 77. PLAELMx MMR Bit Descriptions

PLACLK Register

Bit

Value

Description

Name:

PLACLK

0xFFFF0B40

0x00

31 to 11

10 to 9

8 to 7

6

Reserved.

Address:

Mux 0 control (see Table 81).

Mux 1 control (see Table 81).

Mux 2 control.

This bit is set by the user to select the

output of Mux 0.

Default value:

Access:

Read/write

Function:

PLACLK is the clock selection for the flip-

flops. The maximum frequency when using

the GPIO pins as the clock input for the PLA

blocks is 41.78 MHz.

This bit is cleared by the user to select the

bit value from the PLADIN register.

5

Mux 3 control.

This bit is set by the user to select the

input pin of the particular element.

This bit is cleared by the user to select the

output of Mux 1.

4 to 1

Look-up table control.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0.

NOR.

B and not A.

Not A.

A and not B.

Not B.

EXOR.

NAND.

AND.

EXNOR.

B.

Not A or B.

A.

Table 78. PLACLK MMR Bit Descriptions

Bit

Value

Description

31 to 7

6 to 4

Reserved.

Clock source selection.

GPIO clock on P0.5.

GPIO clock on P1.1.

GPIO clock on P1.6.

HCLK.

External 32.768 kHz crystal.

Timer1 overflow.

UCLK.

000

001

010

011

100

101

110

111

Internal 32,768 oscillator.

Reserved.

A or not B.

OR.

1.

3

2 to 0

Clock source selection.

GPIO clock on P0.5.

GPIO clock on P1.1.

GPIO clock on P1.6.

HCLK.

External 32.768 kHz crystal.

Timer1 overflow.

UCLK.

000

001

010

011

100

101

110

111

0

Mux 4 control.

This bit is set by the user to bypass the flip-

flop.

This bit is cleared by the user to select the

flip-flop (cleared by default).

Internal 32,768 oscillator.

Rev. E | Page 68 of 96

Data Sheet

ADuC7023

PLAIRQ Register

Table 79. PLAIRQ MMR Bit Descriptions

Name:

PLAIRQ

Bit

Value Description

31 to 13

12

Reserved.

Address:

0xFFFF0B44

0x00000000

Read/write

PLA IRQ1 enable bit.

PLA Element 0.

Default value:

Access:

11 to 8

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PLA Element 1.

PLA Element 2.

PLA Element 3.

PLA Element 4.

PLA Element 5.

PLA Element 6.

PLA Element 7.

PLA Element 8.

PLA Element 9.

PLA Element 10.

PLA Element 11.

PLA Element 12.

PLA Element 13.

PLA Element 14.

PLA Element 15.

Reserved.

Function:

PLAIRQ enables IRQ0 and/or IRQ1 and

selects the source of the IRQ.

7 to 5

4

PLA IRQ0 enable bit.

This bit is set by the user to enable IRQ0

output from PLA.

This bit is cleared by the user to disable

IRQ0 output from PLA.

3 to 0

PLA IRQ0 source.

PLA Element 0.

PLA Element 1.

PLA Element 2.

PLA Element 3.

PLA Element 4.

PLA Element 5.

PLA Element 6.

PLA Element 7.

Reserved.

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

Rev. E | Page 69 of 96

ADuC7023

Data Sheet

Table 80. Feedback Configuration

Bit

Value

PLAELM0

Element 15

Element 2

Element 4

Element 6

Element 1

Element 3

Element 5

Element 7

PLAELM1 to PLAELM7

Element 0

Element 2

Element 4

Element 6

PLAELM8

Element 7

Element 10

Element 12

Element 14

Element 9

Element 11

Element 13

Element 15

PLAELM9 to PLAELM15

Element 8

Element 10

Element 12

Element 14

10 to 9

00

01

10

11

8 to 7

00

01

10

11

Element 1

Element 3

Element 5

Element 7

Element 9

Element 11

Element 13

Element 15

PLADIN Register

PLAADC Register

Name:

PLADIN

Name:

PLAADC

Address:

0xFFFF0B4C

0x00000000

Read/write

Address:

Default value:

Access:

0xFFFF0B48

Default value:

Access:

0x00000000

Read/write

Function:

PLADIN is a data input MMR for PLA.

Function:

PLAADC is the PLA source for the ADC start

conversion signal.

Table 82. PLADIN MMR Bit Descriptions

Bit

Description

Table 81. PLAADC MMR Bit Descriptions

31 to 16

15 to 0

Reserved.

Bit

Value

Description

Input bit to Element 15 to Element 0.

31 to 5

4

Reserved.

ADC start conversion enable bit.

PLADOUT Register

This bit is set by the user to enable ADC

start conversion from PLA.

Name:

PLADOUT

This bit is cleared by the user to disable ADC

start conversion from PLA.

Address:

Default value:

Access:

0xFFFF0B50

0x00000000

Read

3 to 0

ADC start conversion source.

PLA Element 0.

PLA Element 1.

PLA Element 2.

PLA Element 3.

PLA Element 4.

PLA Element 5.

PLA Element 6.

PLA Element 7.

PLA Element 8.

PLA Element 9.

PLA Element 10.

PLA Element 11.

PLA Element 12.

PLA Element 13.

PLA Element 14.

PLA Element 15.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Function:

PLADOUT is a data output MMR for PLA.

This register is always updated.

Table 83. PLADOUT MMR Bit Descriptions

Bit

Description

31 to 16

15 to 0

Reserved.

Output bit from Element 15 to Element 0.

PLALCK Register

Name:

PLALCK

Address:

Default value:

Access:

0xFFFF0B54

0x00

Write

Function:

PLALCK is a PLA lock option. Bit 0 is written

only once. When set, it does not allow

modifying any of the PLA MMRs, except

PLADIN. A PLA tool is provided in the

development system to easily configure PLA.

Rev. E | Page 70 of 96

Data Sheet

ADuC7023

PULSE-WIDTH MODULATOR

PULSE-WIDTH MODULATOR GENERAL OVERVIEW

In all modes, the PWMxCOMx MMRs control the point at

which the PWM outputs change state. An example of the first

pair of PWM outputs (PWM0 and PWM1) is shown in Figure 40.

The ADuC7023 integrates a 5-channel pulse-width modulator

(PWM) interface. The PWM outputs can be configured to drive

an H-bridge or can be used as standard PWM outputs. On

power-up, the PWM outputs default to H-bridge mode. This

ensures that the motor is turned off by default. In standard

PWM mode, the outputs are arranged as three pairs of PWM

pins. Users have control over the period of each pair of outputs

and over the duty cycle of each individual output.

HIGH SIDE

(PWM0)

LOW SIDE

(PWM1)

Table 84. PWM MMRs

PWM0COM2

MMR Name

PWMCON1

PWM0COM0

Description

PWM Control Register 1.

Compare Register 0 for PWM Output 0 and

PWM Output 1.

PWM0COM1

PWM0COM0

PWM0COM1

PWM0COM2

PWM0LEN

Compare Register 1 for PWM Output 0 and

PWM Output 1.

Compare Register 2 for PWM Output 0 and

PWM Output 1.

Frequency control for PWM Output 0 and PWM

Output 1.

Compare Register 0 for PWM Output 2 and

PWM Output 3.

Compare Register 1 for PWM Output 2 and

PWM Output 3.

Compare Register 2 for PWM Output 2 and

PWM Output 3.

Frequency control for PWM Output 2 and PWM

Output 3.

Compare Register 0 for PWM Output 4

Compare Register 1 for PWM Output 4

PWM interrupt clear.

PWM0LEN

Figure 40. PWM Timing

The PWM clock is selectable via PWMCON1 with one of the

following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or

256. The length of a PWM period is defined by PWMxLEN.

PWM1COM0

PWM1COM1

PWM1COM2

PWM1LEN

The PWM waveforms are set by the count value of the 16-bit

timer and the compare registers contents, as shown with the

PWM0 and PWM1 waveforms in Figure 40.

The low-side waveform, PWM1, goes high when the timer

count reaches PWM0LEN, and it goes low when the timer

count reaches the value held in PWM0COM2 or when the

high-side waveform (PWM0) goes low.

PWM2COM0

PWM2COM1

PWMCLRI

The high-side waveform, PWM0, goes high when the timer

count reaches the value held in PWM0COM0, and it goes low

when the timer count reaches the value held in PWM0COM1.

PWMCON1 Control Register

Name:

PWMCON1

0xFFFF0F80

0x0012

Address:

Default value:

Access:

Read and write

Function:

This is a 16-bit MMR that configures the

PWM outputs.

Rev. E | Page 71 of 96

ADuC7023

Data Sheet

Table 85. PWMCON1 MMR Bit Designations

Bit

Name

Description

14

SYNC

Enables PWM synchronization.

Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low

transition on the P2.2/SYNC pin.

Cleared by the user to ignore transitions on the P2.2/SYNC pin.

Set to 0 by the user.

13

12

Reserved

PWM3INV

Set to 1 by the user to invert PWM3.

Cleared by the user to use PWM3 in normal mode.

Set to 1 by the user to invert PWM1.

Cleared by the user to use PWM1 in normal mode.

11

10

PWM1INV

PWMTRIP

Set to 1 by the user to enable PWM trip interrupt. When the PWM trip input (Pin P1.5/PWM_TRIPINPUT) is low, the

PWMEN bit is cleared and an interrupt is generated.

Cleared by the user to disable the PWMTRIP interrupt.

If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect.

Set to 1 by the user to enable PWM outputs.

9

ENA

Cleared by the user to disable PWM outputs.

If HOFF = 1 and HMODE = 1, see Table 86.

8 to 6

PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider.

[000] = UCLK/2.

[001] = UCLK/4.

[010] = UCLK/8.

[011] = UCLK/16.

[100] = UCLK/32.

[101] = UCLK/64.

[110] = UCLK/128.

[111] = UCLK/256.

5

4

POINV

HOFF

Set to 1 by the user to invert all PWM outputs.

Cleared by the user to use PWM outputs as normal.

High side off.

Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.

Cleared by the user to use the PWM outputs as normal.

Load compare registers.

3

LCOMP

Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of

the PWM timer from 0x00 to 0x01.

Cleared by the user to use the values previously stored in the internal compare registers.

Direction control.

Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.

Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.

Enables H-bridge mode.¹

Set to 1 by the user to enable H-bridge mode.

Cleared by the user to operate the PWMs in standard mode.

Set to 1 by the user to enable all PWM outputs.

2

1

0

DIR

HMODE

PWMEN

Cleared by the user to disable all PWM outputs.

¹In H-bridge mode, HMODE = 1. See Table 86 to determine the PWM outputs.

Rev. E | Page 72 of 96

Data Sheet

ADuC7023

On power-up, PWMCON1 defaults to 0x0012 (HOFF = 1 and

HMODE = 1). All GPIO pins associated with the PWM are

configured in PWM mode by default (see Table 86). Clear the

PWM trip interrupt by writing any value to the PWMCLRI

MMR. Note that when using the PWM trip interrupt, clear the

PWM interrupt before exiting the ISR. This prevents generation

of multiple interrupts.

Table 86. PWM Output Selection

PWMCON1 MMR¹

PWM Outputs²

ENA

HOFF

POINV

DIR

X

0

1

PWM0

PWM1

PWM2

PWM3

0

X

1

0

1

0

X

0

1

0

HS1

1

0

LS1

1

HS1

0

1

0

LS1

0

1

0

1

HS1

LS1

X is don’t care.

²HS = high side, LS = low side.

Table 87. Compare Registers

Name

Address

Default Value

Access

R/W

PWM0COM0

PWM0COM1

PWM0COM2

PWM1COM0

PWM1COM1

PWM1COM2

PWM2COM0

PWM2COM1

0xFFFF0F84

0xFFFF0F88

0xFFFF0F8C

0xFFFF0F94

0xFFFF0F98

0xFFFF0F9C

0xFFFF0FA4

0xFFFF0FA8

0x0000

Rev. E | Page 73 of 96

ADuC7023

Data Sheet

PWM1COM0 Compare Register

PWM0COM0 Compare Register

Name:

PWM1COM0

Name:

PWM0COM0

Address:

0xFFFF0F94

Address:

0xFFFF0F84

Default value: 0x0000

Access:

Read and write

Access:

Read and write

Function:

PWM2 output pin goes high when the PWM

timer reaches the count value stored in this

register.

Function:

PWM0 output pin goes high when the PWM

timer reaches the count value stored in this

register.

PWM1COM1 Compare Register

PWM0COM1 Compare Register

Name:

PWM1COM1

Name:

PWM0COM1

Address:

0xFFFF0F98

Address:

0xFFFF0F88

Default value: 0x0000

Access:

Read and write

Access:

Read and write

Function:

PWM2 output pin goes low when the PWM

timer reaches the count value stored in this

register.

Function:

PWM0 output pin goes low when the PWM

timer reaches the count value stored in this

register.

PWM1COM2 Compare Register

PWM0COM2 Compare Register

Name:

PWM1COM2

Name:

PWM0COM2

Address:

0xFFFF0F9C

Address:

0xFFFF0F8C

Default value: 0x0000

Access:

Read and write

Access:

Read and write

Function:

PWM3 output pin goes low when the PWM

timer reaches the count value stored in this

register.

Function:

PWM1 output pin goes low when the PWM

timer reaches the count value stored in this

register.

PWM1LEN Register

PWM0LEN Register

Name:

PWM1LEN

Name:

PWM0LEN

Address:

0xFFFF0FA0

Address:

0xFFFF0F90

Default value: 0x0000

Access:

Read and write

Access:

Read and write

Function:

PWM3 output pin goes high when the PWM

timer reaches the value stored in this register.

Function:

PWM1 output pin goes high when the PWM

timer reaches the value stored in this register.

Rev. E | Page 74 of 96

Data Sheet

ADuC7023

PWM2COM0 Compare Register

PWMCLRI Register

Name:

PWM2COM0

Name:

PWMCLRI

Address:

0xFFFF0FA4

Address:

Default value:

Access:

0xFFFF0FB8

0x0000

Default value: 0x0000

Access:

Read/write

Write

Function:

PWM4 output pin goes high when the PWM

timer reaches the count value stored in this

register.

Function:

Write any value to this register to clear a PWM

interrupt source. This register must be written

to before exiting a PWM interrupt service

routine; otherwise, multiple interrupts occur.

PWM2COM1 Compare Register

Name:

PWM2COM1

Address:

0xFFFF0FA8

Default value: 0x0000

Access:

Read/write

Function:

PWM4 output pin goes low when the PWM

timer reaches the count value stored in this

register.

Rev. E | Page 75 of 96

ADuC7023

Data Sheet

PROCESSOR REFERENCE PERIPHERALS

INTERRUPT SYSTEM

IRQ

There are 22 interrupt sources on the ADuC7023 that are

controlled by the interrupt controller. Most interrupts are

generated from the on-chip peripherals, such as ADC. Four

additional interrupt sources are generated from external interrupt

request pins, IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI

CPU core only recognizes interrupts as one of two types, a

normal interrupt request IRQ or a fast interrupt request FIQ.

All the interrupts can be masked separately.

The interrupt request (IRQ) is the exception signal to enter the

IRQ mode of the processor. It is used to service general-purpose

interrupt handling of internal and external events.

The four 32-bit registers dedicated to IRQ are: IRQSTA, IRQSIG,

IRQEN, and IRQCLR.

IRQSTA Register

Name:

IRQSTA

The control and configuration of the interrupt system is managed

through nine interrupt related registers, four dedicated to IRQ,

and four dedicated to FIQ. An additional MMR is used to select

the programmed interrupt source. The bits in each IRQ and

FIQ registers represent the same interrupt source as described

in Table 88.

Address:

Default value:

Access:

0xFFFF0000

0x00000000

Read

Function:

IRQSTA (read-only register) provides the

current-enabled IRQ source status. When

set to 1, that source generates an active IRQ

request to the ARM7TDMI core. There is no

priority encoder or interrupt vector

generation. This function is implemented in

software in a common interrupt handler

routine. All 32 bits are logically OR’ed to

create the IRQ signal to the ARM7TDMI

core.

The ADuC7023 contains a vectored interrupt controller (VIC)

that supports nested interrupts up to eight levels. The VIC also

allows the programmer to assign priority levels to all interrupt

sources. Interrupt nesting is enabled by setting the ENIRQN bit

in the IRQCONN register. A number of extra MMRs are used

when the full-vectored interrupt controller is enabled.

IRQSTA/FIQSTA should be saved immediately upon entering

the interrupt service routine (ISR) to ensure that all valid

interrupt sources are serviced.

Table 88. IRQ/FIQ MMRs Bit Description

IRQSIG Register

Bit

Description

All interrupts OR’ed (FIQ only).

SWI.

0

1

Name:

IRQSIG

Address:

0xFFFF0004

0x00XXX000

Read

2

Timer0.

3

4

5

6

Timer1.

Default value:

Access:

Watchdog timer (Timer 2).

Flash control.

ADC channel.

PLL lock.

Function:

IRQSIG reflects the status of the different IRQ

sources. If a peripheral generates an IRQ

signal, the corresponding bit in the IRQSIG is

set; otherwise, it is cleared. The IRQSIG bits

are cleared when the interrupt in the

particular peripheral is cleared. All IRQ

sources can be masked in the IRQEN MMR.

IRQSIG is read-only.

7

8

9

I²C0 master.

I²C0 slave.

I²C1 master.

I²C1 slave.

10

11

12

13

14

15

16

17

18

19

20

21

SPI.

External IRQ0.

Comparator.

PSM.

External IRQ1.

PLA IRQ0.

External IRQ2.

External IRQ3.

PLA IRQ1.

PWM.

Rev. E | Page 76 of 96

Data Sheet

ADuC7023

IRQEN Register

FIQSIG

Name:

IRQEN

FIQSIG reflects the status of the different FIQ sources. If a

peripheral generates an FIQ signal the corresponding bit in

the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are

cleared when the interrupt in the particular peripheral is cleared.

All FIQ sources can be masked in the FIQEN MMR. FIQSIG is

read only.

Address:

0xFFFF0008

0x00000000

Read/write

Default value:

Access:

FIQSIG Register

Function:

IRQEN provides the value of the current

enable mask. When each bit is set to 1, the

source request is enabled to create an IRQ

exception. When each bit is set to 0, the

source request is disabled or masked, which

does not create an IRQ exception.

Name:

FIQSIG

Address:

0xFFFF0104

Default value: 0x00000000

Access:

Read only

To clear an already enabled interrupt source,

users must set the appropriate bit in the

IRQCLR register. Clearing an interrupt

IRQEN bit does not disable this interrupt.

FIQEN

FIQEN provides the value of the current enable mask. When a bit is

set to 1, the corresponding source request is enabled to create an

FIQ exception. When a bit is set to 0, the corresponding source

request is disabled or masked which does not create an FIQ

exception. The FIQEN register cannot be used to disable an

interrupt.

IRQCLR Register

Name:

IRQCLR

Address:

0xFFFF000C

0x00000000

Write

FIQEN Register

Default value:

Access:

Name:

FIQEN

Address:

0xFFFF0108

Function:

IRQCLR (write-only register) clears the

IRQEN register to mask an interrupt source.

Each bit set to 1 clears the corresponding bit

in the IRQEN register without affecting the

remaining bits. The pair of registers, IRQEN

and IRQCLR, independently manipulate the

enable mask without requiring an atomic

read-modify-write.

Default value: 0x00000000

Access:

Read/write

FIQCLR

FIQCLR is a write-only register that allows the FIQEN register

to clear in order to mask an interrupt source. Each bit that is set

to 1 clears the corresponding bit in the FIQEN register without

affecting the remaining bits. The pair of registers, FIQEN and

FIQCLR, allows independent manipulation of the enable mask

without requiring an atomic read-modify-write.

FAST INTERRUPT REQUEST (FIQ)

The fast interrupt request (FIQ) is the exception signal to enter

the FIQ mode of the processor. It is provided to service data

transfer or communication channel tasks with low latency. The

FIQ interface is identical to the IRQ interface and provides the

second level interrupt (highest priority). Four 32-bit registers

are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.

This register should only be used to disable an interrupt source

when in the interrupt sources interrupt service routine or if the

peripheral is temporarily disabled by its own control register.

This register should not be used to disable an IRQ source if that

IRQ source has an interrupt pending or could have an interrupt

pending.

Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ

signal to the core and to Bit 0 of both the FIQ and IRQ registers

(FIQ source).

FIQCLR Register

Name:

FIQCLR

The logic for FIQEN and FIQCLR does not allow an interrupt

source to be enabled in both IRQ and FIQ masks. A bit set to 1

in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise,

a bit set to 1 in IRQEN clears, as a side effect, the same bit in

FIQEN. An interrupt source can be disabled in both IRQEN

and FIQEN masks.

Address:

Default value:

Access:

0xFFFF010C

0x00000000

Write only

Rev. E | Page 77 of 96

ADuC7023

Data Sheet

FIQSTA

VECTORED INTERRUPT CONTROLLER (VIC)

FIQSTA is a read-only register that provides the current enabled

FIQ source status (effectively a logic AND of the FIQSIG and

FIQEN bits). When set to 1, that source generates an active FIQ

request to the ARM7TDMI core. There is no priority encoder

or interrupt vector generation. This function is implemented in

software in a common interrupt handler routine.

The ADuC7023 incorporates an enhanced interrupt control

system or vectored interrupt controller. The vectored interrupt

controller for IRQ interrupt sources is enabled by setting Bit 0

of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables

the vectored interrupt controller for the FIQ interrupt sources.

The vectored interrupt controller provides the following

enhancements to the standard IRQ/FIQ interrupts:

FIQSTA Register

•

Vectored interrupts allow a user to define separate interrupt

service routine addresses for every interrupt source. This is

achieved by using the IRQBASE and IRQVEC registers.

IRQ/FIQ interrupts can be nested up to eight levels depending

on the priority settings. An FIQ still has a higher priority

than an IRQ. Therefore, if the VIC is enabled for both the

FIQ and IRQ and prioritization is maximized, then it is

possible to have 16 separate interrupt levels.

Name:

FIQSTA

Address:

0xFFFF0100

•

Default value: 0x00000000

Access: Read only

Programmed Interrupts

Because the programmed interrupts are not maskable, they are

controlled by another register (SWICFG) that writes into both

IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG

registers at the same time.

•

Programmable interrupt priorities, using the IRQP0 to IRQP2

registers, can be assigned an interrupt priority level value

between 0 and 7.

VIC MMRs

The 32-bit register dedicated to software interrupt is SWICFG

described in Table 89. This MMR allows the control of a

programmed source interrupt.

IRQBASE Register

The vector base register, IRQBASE, is used to point to the start

address of memory used to store 32 pointer addresses. These

pointer addresses are the addresses of the individual interrupt

service routines.

Table 89. SWICFG MMR Bit Designations

Bit

Description

31 to 3 Reserved.

Name:

IRQBASE

2

1

0

Programmed interrupt FIQ. Setting/clearing this bit

corresponds to setting/clearing Bit 1 of FIQSTA and

FIQSIG.

Address:

0xFFFF0014

Programmed interrupt IRQ. Setting/clearing this bit

corresponds to setting/clearing Bit 1 of IRQSTA and

IRQSIG.

Default value: 0x00000000

Access: Read and write

Reserved.

Any interrupt signal must be active for at least the minimum

interrupt latency time, to be detected by the interrupt controller

and to be detected by the user in the IRQSTA and FIQSTA

registers.

Table 90. IRQBASE MMR Bit Designations

Bit

Type

Initial Value

Reserved

0

Description

31:16

15:0

Read only

R/W

Always read as 0.

Vector base address.

PROGRAMMABLE PRIORITY

PER INTERRUPT (IRQP0/IRQP1/IRQP2)

POINTER TO

FUNCTION

(IRQVEC)

IRQ_SOURCE

FIQ_SOURCE

INTERNAL

ARBITER

LOGIC

INTERRUPT VECTOR

BIT 31 TO BIT 22 TO BIT 7 BIT 6 TO BIT 1 TO

BIT 23

(IRQBASE)

BIT 2

BIT 0

UNUSED

HIGHEST LBSs

PRIORITY

ACTIVE IRQ

Figure 41. Interrupt Structure

Rev. E | Page 78 of 96

Data Sheet

ADuC7023

IRQVEC Register

Table 91. IRQVEC MMR Bit Designations

Initial

Value

The IRQ interrupt vector register, IRQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active IRQ. This register should only be read when

an IRQ occurs and IRQ interrupt nesting has been enabled by

setting Bit 0 of the IRQCONN register.

Bit

Type

Description

31 to 23 Read only

0

Always read as 0.

22 to 7

6 to 2

R/W

IRQBASE register value.

Read only

Highest priority source. This is

a value between 0 and 21

representing the possible

interrupt sources. For example,

if the highest currently active

IRQ is Timer 2, then these bits

are [00100].

IRQVEC Register

Name:

IRQVEC

Address:

0xFFFF001C

1 to 0

Reserved

0

Reserved bits.

Default value: 0x00000000

Access: Read only

Priority Registers

The IRQ interrupt vector register, IRQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active IRQ. This register should only be read when

an IRQ occurs and IRQ interrupt nesting has been enabled by

setting Bit 0 of the IRQCONN register.

Rev. E | Page 79 of 96

ADuC7023

Data Sheet

Bit

Name

Description

IRQP0 Register

18 to 16

SPIPI

A priority level of 0 to 7 can be set for

SPI.

Name:

IRQP0

15

Reserved Reserved bit.

I2C1SPI A priority level of 0 to 7 can be set for

I²C1 slave.

Reserved Reserved bit.

I2C1MPI A priority level of 0 to 7 can be set for

I²C1 master.

Reserved Reserved bits.

I2C0SPI A priority level of 0 to 7 can be set for

I²C0 slave.

Reserved Reserved bits.

I2C0MPI A priority level of 0 to 7 can be set for

I²C0 master.

Address:

0xFFFF0020

14 to 12

Default value: 0x00000000

Access: Read and write

11

10 to 8

Table 92. IRQP0 MMR Bit Designations

Bit

7

Name

Description

6 to 4

31

Reserved

Reserved bit

30 to 28 PLLPI

A priority level of 0 to 7 can be set for

PLL lock interrupt.

3

2 to 0

27

Reserved

Reserved bit

26 to 24 ADCPI

A priority level of 0 to 7 can be set for

the ADC interrupt source.

IRQP2 Register

23

Reserved

Reserved bit

Name:

IRQP2

22 to 20 FlashPI

A priority level of 0 to 7 can be set for

the Flash controller interrupt source.

Address:

0xFFFF0028

19

Reserved

Reserved bit.

Default value: 0x00000000

Access: Read and write

18 to 16 T2PI

A priority level of 0 to 7 can be set for

Timer2.

15

Reserved

Reserved bit.

14 to 12 T1PI

A priority level of 0 to 7 can be set for

Timer1.

Table 94. IRQP2 MMR Bit Designations

Bit

Name

Description

11

Reserved

Reserved bit.

31 to 23 Reserved

22 to 20 PWMPI

Reserved bit.

10 to 8

T0PI

A priority level of 0 to 7 can be set for

Timer0.

A priority level of 0 to 7 can be set for

PWM.

7

Reserved

SWINTP

Reserved bit

19

Reserved

Reserved bit.

6 to 4

A priority level of 0 to 7 can be set for

the software interrupt source.

18 to 16 PLA1PI

A priority level of 0 to 7 can be set for

PLA IRQ1.

3 to 0

Reserved

Interrupt 0 cannot be prioritized.

15

Reserved

Reserved bit.

14 to 12 IRQ3PI

A priority level of 0 to 7 can be set for

IRQ3.

IRQP1 Register

Name:

IRQP1

11

Reserved

Reserved bit.

10 to 8

IRQ2PI

A priority level of 0 to 7 can be set for

IRQ2.

Address:

0xFFFF0024

7

Reserved

PLA0PI

Reserved bit.

Default value: 0x00000000

Access: Read and write

6 to 4

A priority level of 0 to 7 can be set for

PLA IRQ0.

3

Reserved

IRQ1PI

Reserved bit.

Table 93. IRQP1 MMR Bit Designations

2 to 0

A priority level of 0 to 7 can be set for

IRQ1.

Bit

Name

Reserved Reserved bit.

PSMPI A priority level of 0 to 7 can be set for

Description

31

30 to 28

the power supply monitor interrupt

source.

27

Reserved Reserved bit.

COMPI A priority level of 0 to 7 can be set for

comparator.

Reserved Reserved bit.

IRQ0PI A priority level of 0 to 7 can be set for

IRQ0.

Reserved Reserved bit.

26 to 24

23

22 to 20

19

Rev. E | Page 80 of 96

Data Sheet

ADuC7023

IRQCONN Register

Table 96. IRQSTAN MMR Bit Designations

Bit Name Description

The IRQCONN register is the IRQ and FIQ control register.

It contains two active bits. The first to enable nesting and

prioritization of IRQ interrupts and the other to enable

nesting and prioritization of FIQ interrupts.

31 to 8 Reserved

These bits are reserved and should not be

written to.

7 to 0

This bit is set to 1 to enable nesting of FIQ

interrupts.

If these bits are cleared, then FIQs and IRQs may still be used,

but it is not possible to nest IRQs or FIQs. Neither is it possible

to set an interrupt source priority level. In this default state, an

FIQ does have a higher priority than an IRQ.

When this bit is cleared, it means no

nesting or prioritization of FIQs is

allowed.

FIQVEC Register

The FIQ interrupt vector register, FIQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active FIQ. This register should only be read when

an FIQ occurs and FIQ interrupt nesting has been enabled by

setting Bit 1 of the IRQCONN register.

Name:

IRQCONN

0xFFFF0030

Address:

Default value: 0x00000000

Access: Read and write

Name:

FIQVEC

Table 95. IRQCONN MMR Bit Designations

Address:

0xFFFF011C

Bit

Name

Description

Default value: 0x00000000

Access: Read only

31 to 2 Reserved

These bits are reserved and should not be

written to.

1

0

ENFIQN

ENIRQN

This bit is set to 1 to enable nesting of FIQ

interrupts.

This bit is cleared to mean no nesting or

prioritization of FIQs is allowed.

Table 97. FIQVEC MMR Bit Designations

Initial

Value

Bit

Type

Description

This bit is set to 1 to enable nesting of IRQ

interrupts.

When this bit is cleared, it means no

nesting or prioritization of IRQs is

allowed.

31 to 23

22 to 7

6 to 2

Read only

R/W

0

Always read as 0.

IRQBASE register value.

Highest priority source. This

is a value between 0 and 27

that represents the possible

interrupt sources. For

example, if the highest

currently active FIQ is

Timer 2, then these bits are

[00100].

IRQSTAN Register

If IRQCONN Bit 0 is asserted and IRQVEC is read then one of

these bits is asserted. The bit that asserts depends on the priority of

the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts. If the IRQ is

of Priority 1, then Bit 1 asserts, and so forth. When a bit is set in

this register, all interrupts of that priority and lower are blocked.

1 to 0

Reserved

0

Reserved bits.

To clear a bit in this register, all bits of a higher priority must be

cleared first. It is only possible to clear one bit at a time. For

example, if this register is set to 0x09, then writing 0xFF changes

the register to 0x08, and writing 0xFF a second time changes

the register to 0x00.

Name:

IRQSTAN

Address:

0xFFFF003C

Default value: 0x00000000

Access: Read and write

Rev. E | Page 81 of 96

ADuC7023

Data Sheet

FIQSTAN Register

Table 99. IRQCONE MMR Bit Designations

Bit

Value Name

Description

If IRQCONN Bit 1 is asserted and FIQVEC is read, then one of

these bits assert. The bit that asserts depends on the priority of

the FIQ. If the FIQ is of Priority 0, then Bit 0 asserts. If the FIQ

is of Priority 1, then Bit 1 asserts, and so forth.

31 to 12

Reserved

These bits are reserved and

should not be written to.

11 to 10 11

PLA1SRC[1:0] PLA IRQ1 triggers on falling

edge.

When a bit is set in this register, all interrupts of that priority

and lower are blocked.

10

01

00

PLA IRQ1 triggers on rising

edge.

PLA IRQ1 triggers on low

level.

PLA IRQ1 triggers on high

level.

To clear a bit in this register, all bits of a higher priority must be

cleared first. It is only possible to clear one bit at a time. For

example, if this register is set to 0x09, then writing 0xFF changes

the register to 0x08 and writing 0xFF a second time changes the

register to 0x00.

9 to 8

7 to 6

5 to 4

3 to 2

1 to 0

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

00

IRQ3SRC[1:0] External IRQ3 triggers on

falling edge.

External IRQ3 triggers on

rising edge.

External IRQ3 triggers on

low level.

External IRQ3 triggers on

high level.

Name:

FIQSTAN

Address:

0xFFFF013C

Default value: 0x00000000

Access: Read/write

IRQ2SRC[1:0] External IRQ2 triggers on

falling edge.

Table 98. FIQSTAN MMR Bit Designations

External IRQ2 triggers on

rising edge.

External IRQ2 triggers on

low level.

External IRQ2 triggers on

high level.

Bit

Name

Description

31 to 8

Reserved These bits are reserved and should not be

written to.

7 to 0

This bit is set to 1 to enables nesting of

FIQ interrupts.

When this bit is cleared, it means no

nesting or prioritization of FIQs is

allowed.

PLA0SRC[1:0] PLA IRQ0 triggers on falling

edge.

PLA IRQ0 triggers on rising

edge.

PLA IRQ0 triggers on low

level.

PLA IRQ0 triggers on high

level.

External Interrupts and PLA interrupts

The ADuC7023 provides up to four external interrupt sources

and two PLA interrupt sources. These external interrupts can be

individually configured as level or rising/falling edge triggered.

IRQ1SRC[1:0] External IRQ1 triggers on

falling edge.

To enable the external interrupt source or the PLA interrupt

source, the appropriate bit must be set in the FIQEN or IRQEN

register. To select the required edge or level to trigger on, the

IRQCONE register must be appropriately configured.

External IRQ1 triggers on

rising edge.

External IRQ1 triggers on

low level.

External IRQ1 triggers on

high level.

To properly clear an edge-based external IRQ interrupt or an edge-

based PLA interrupt, set the appropriate bit in the IRQCLRE

register.

IRQ0SRC[1:0] External IRQ0 triggers on

falling edge.

IRQCONE Register

External IRQ0 triggers on

rising edge.

External IRQ0 triggers on

low level.

External IRQ0 triggers on

high level.

Name:

IRQCONE

Address:

0xFFFF0034

Default value: 0x00000000

Access: Read and write

Rev. E | Page 82 of 96

Data Sheet

ADuC7023

The value of a counter can be read at any time by accessing its

value register (TxVAL). When a timer is being clocked from a

clock other than core clock, an incorrect value may be read (due

to asynchronous clock system). In this configuration, TxVAL

should always be read twice. If the two readings are different, it

should be read a third time to get the correct value.

IRQCLRE Register

Name:

IRQCLRE

Address:

0xFFFF0038

Default value: 0x00000000

Access: Read and write

Timers are started by writing in the control register of the

corresponding timer (TxCON).

Table 100. IRQCLRE MMR Bit Designations

In normal mode, an IRQ is generated each time the value of the

counter reaches zero when counting down. It is also generated

each time the counter value reaches full scale when counting up.

An IRQ can be cleared by writing any value to clear the register

of that particular timer (TxCLRI).

Bit

Name

Description

31 to

21

Reserved These bits are reserved and should not be

written to.

20

19

18

17

16

PLA1CLRI A 1 must be written to this bit in the PLA IRQ1

interrupt service routine to clear an edge

triggered PLA IRQ1 interrupt.

When using an asynchronous clock-to-clock timer, the interrupt in

the timer block can take more time to clear than the time it takes

for the code in the interrupt routine to execute. Ensure that the

interrupt signal is cleared before leaving the interrupt service

routine. This can be done by checking the IRQSTA MMR.

IRQ3CLRI

A 1 must be written to this bit in the external

IRQ3 interrupt service routine to clear an edge

triggered IRQ3 interrupt.

IRQ2CLRI

A 1 must be written to this bit in the external

IRQ2 interrupt service routine to clear an edge

triggered IRQ2 interrupt.

Hours, Minutes, Seconds, and 1/128 Format

PLA0CLRI A 1 must be written to this bit in the PLA IRQ0

interrupt service routine to clear an edge

triggered PLA IRQ0 interrupt.

To use the timer in hours, minutes, seconds,and hundreds

format, select the 32768 kHz clock and a prescaler of 256. The

hundreds field does not represent milliseconds but 1/128 of a

seconds (256/32,768). The bits representing the hour, minute,

and second are not consecutive in the register. This arrangement

applies to T1LD and T1VAL when using the Hr:Min:Sec:hundreds

format as set in T1CON[5:4]. See Table 101 for more details.

IRQ1CLRI

A 1 must be written to this bit in the external

IRQ1 interrupt service routine to clear an edge

triggered IRQ1 interrupt.

15 to

14

Reserved These bits are reserved and should not be

written to.

13

IRQ0CLRI

A 1 must be written to this bit in the external

IRQ0 interrupt service routine to clear an edge

triggered IRQ0 interrupt.

Table 101. Hours, Minutes, Seconds, and Hundreds Format

Bit

Value

Description

12 to

0

Reserved These bits are reserved and should not be

written to.

31:24

23:22

21:16

15:14

13:8

7

0 to 23 or 0 to 255

0

0 to 59

0

0 to 59

0

Hours

Reserved

Minutes

Reserved

Seconds

Reserved

1/128 of second

TIMERS

The ADuC7023 has three general-purpose timer/counters: Timer0,

Timer1, and Timer2 or Watchdog Timer.

These three timers in their normal mode of operation can be

either free-running or periodic.

6:0

0 to 127

In free-running mode, the counter decreases from the maximum

value until zero scale and starts again at the minimum value. (It

also increases from the minimum value until full scale and starts

again at the maximum value.)

Timer0 (RTOS Timer)

Timer0 is a general-purpose, 16-bit timer (count-down) with a

programmable prescaler (see Figure 42). The prescaler source is

the core clock frequency (HCLK) and can be scaled by factors

of 1, 16, or 256.

In periodic mode, the counter decrements/increments from the

value in the load register (TxLD MMR) until zero/full scale and

starts again at the value stored in the load register.

Timer0 can be used to start ADC conversions as shown in the

block diagram in Figure 42.

The timer interval is calculated as follows.

If the timer is set to count down,

16-BIT

LOAD

32.768kHz

OSCILLATOR

(

TxLD

)

× Prescaler

16-BIT

DOWN

COUNTER

PRESCALER

/1, 16, OR 256

Interval =

TIMER0 IRQ

UCLK

HCLK

SourceClock

ADC CONVERSION

If the timer is set to count up,

FullScale -TxLD

TIMER0

VALUE

(

)

× Prescaler

Interval =

Figure 42. Timer0 Block Diagram

SourceClock

Rev. E | Page 83 of 96

ADuC7023

Data Sheet

The Timer0 interface consists of four MMRs: T0LD, T0VAL,

T0CON, and T0CLRI.

T0CLRI Register

Name:

T0CLRI

0xFFFF030C

0xXX

T0LD Register

Address:

Name:

T0LD

Default value:

Access:

Address:

Default value:

Access:

0xFFFF0300

0x0000

Write

T0CLRI is an 8-bit register. Writing any value to this register

clears the interrupt.

Read/write

T0LD is a 16-bit load register that holds the 16-bit value that is

loaded into the counter.

The following is the recommended procedure for servicing the

Timer 0 interrupt:

void IRQ_Handler(void) __irq

T0VAL Register

{

Name:

T0VAL

if(IRQSTA & BIT2) // Timer0 IRQ?

{

Address:

Default Value:

Access:

0xFFFF0304

0xFFFF

Read

T0CLRI = 0;

//clear Timer0 interrupt

T0CON = 0x00; //disable Timer0 interrupt

T0CON = 0xC8; //enable Timer0 interrupt

T0VAL is a 16-bit read-only register representing the current

state of the counter.

}

T0CON Register

Timer1 (General-Purpose Timer)

Name:

T0CON

0xFFFF0308

0x0000

Timer1 is a general-purpose, 32-bit timer (count down or count

up) with a programmable prescaler. The source can be the 32 kHz

external crystal, the undivided system, the core clock, or P1.1

(maximum frequency 44 MHz). This source can be scaled by a

factor of 1, 16, 256, or 32,768.

Address:

Default value:

Access:

R/W

The counter can be formatted as a standard 32-bit value or as

hours, minutes, seconds, hundredths.

T0CON is the configuration MMR described in Table 102.

Timer1 has a capture register (T1CAP) that can be triggered by

a selected IRQ source initial assertion. This feature can be used

to determine the assertion of an event more accurately than the

precision allowed by the RTOS timer when the IRQ is serviced.

Table 102. T0CON MMR Bit Descriptions

Bit

Value Description

15 to 8

7

Reserved.

Timer0 enable bit.

Timer1 can be used to start ADC conversions as shown in the

block diagram in Figure 43.

This bit is set by the user to enable Timer0. This

bit is cleared by the user to disable Timer0 by

default.

32-BIT

LOAD

6

Timer0 mode.

This bit is set by the user to operate in

periodic mode.

This bit is cleared by the user to operate in

free-running mode. Default mode.

32kHz OSCILLATOR

PRESCALER

/1, 16, 256,

OR 32,768

32-BIT

UP/DOWN

COUNTER

HCLK

UCLK

P1.1

TIMER1 IRQ

ADC CONVERSION

TIMER1

VALUE

5 to 4

Clock select bits.

HCLK.

UCLK.

Internal 32768 Hz oscillator.

Reserved.

CAPTURE

IRQ[19:0]

00

01

10

11

00

01

10

11

Figure 43. Timer1 Block Diagram

The Timer1 interface consists of five MMRs: T1LD, T1VAL,

T1CON, T1CLRI, and T1CAP.

3 to 2

1 to 0

Source clock/1. Default value.

Source clock/16.

Source clock/256.

Undefined. Equivalent to 00.

Reserved.

Rev. E | Page 84 of 96

Data Sheet

ADuC7023

T1LD Register

Bit

Value

Description

6

Timer1 mode. This bit is set by the user to

operate in periodic mode. This bit is

cleared by the user to operate in free-

running mode. Default mode.

Name:

T1LD

Address:

0xFFFF0320

0x00000000

Read/write

Default value:

Access:

5 to 4

Format.

Binary.

Reserved.

Hours, minutes, seconds, hundredths

(23 hours to 0 hour).

Hours, minutes, seconds, hundredths

(255 hours to 0 hour).

00

01

10

T1LD is a 32-bit load register that holds the 32-bit value that is

loaded into the counter.

11

T1VAL Register

3 to 0

Prescale.

Name:

T1VAL

0000

0100

1000

1111

Source clock/1.

Source clock/16.

Source clock/256.

Source clock/32,768.

Address:

Default value:

Access:

0xFFFF0324

0xFFFFFFFF

Read

T1CLRI Register

T1VAL is a 32-bit read-only register that represents the current

state of the counter.

Name:

T1CLRI

Address:

0xFFFF032C

0xXX

T1CON Register

Name:

T1CON

Default value:

Access:

Address:

Default value:

Access:

0xFFFF0328

0x00000000

Read/write

Write

T1CLRI is an 8-bit register. Writing any value to this register

clears the Timer1 interrupt.

T1CAP Register

T1CON is the configuration MMR described in Table 103.

Name:

T1CAP

Table 103. T1CON MMR Bit Descriptions

Address:

Default value:

Access:

0xFFFF0330

0x00000000

Read

Bit

Value

Description

31 to 18

17

Reserved.

Event select bit. This bit is set by the user

to enable time capture of an event. This

bit is cleared by the user to disable time

capture of an event.

T1CAP is a 32-bit register. It holds the value contained in T1VAL

when a particular event occurrs. This event must be selected in

T1CON.

16 to 12

11 to 9

Event select range, 0 to 31. These events

are as described in Table 88. All events are

offset by two, that is, Event 2 in Table 88

becomes Event 0 for the purposes of

Timer1.

Clock select.

000

001

010

011

Core clock (HCLK).

Internal 32.768 kHz crystal

UCLK

P1.1 raising edge triggered.

8

7

Count up. This bit is set by the user for

Timer1 to count up. This bit is cleared by

the user for Timer1 to count down by

default.

Timer1 enable bit. This bit is set by the

user to enable Timer1. This bit is cleared

by the user to disable Timer1 by default.

Rev. E | Page 85 of 96

ADuC7023

Data Sheet

Timer2 (Watchdog Time)

T2VAL Register

Name: T2VAL

Address: 0xFFFF0364

Timer2 has two modes of operation: normal mode and watchdog

mode. The watchdog timer is used to recover from an illegal

software state. When enabled, it requires periodic servicing to

prevent it from forcing a processor reset.

Default

value:

0xFFFF

Normal Mode

Timer2 in normal mode is identical to Timer0, except for the

clock source and the count-up functionality. The clock source is

32 kHz from the PLL and can be scaled by a factor of 1, 16, or

256 (see Figure 44).

Access:

Read

T2VAL is a 16-bit read-only register that represents the current

state of the counter.

16-BIT

LOAD

T2CON Register

Name:

T2CON

16-BIT

UP/DOWN

COUNTER

WATCHDOG RESET

TIMER2 IRQ

PRESCALER

1, 4, 16, OR 256

32.768kHz

Address: 0xFFFF0368

Default

value:

0x0000

TIMER2

VALUE

Figure 44. Timer2 Block Diagram

Access:

Read/write

Watchdog Mode

T2CON is the configuration MMR described in Table 104.

Watchdog mode is entered by setting Bit 5 in the T2CON MMR.

Timer2 decreases from the value present in the T2LD register

until 0. T2LD is used as the timeout. The maximum timeout can

be 512 sec using the prescaler/256, and full-scale in T2LD. Timer3

is clocked by the internal 32 kHz crystal when operating in the

watchdog mode. To enter watchdog mode successfully, Bit 5 in

the T2CON MMR must be set after writing to the T2LD MMR.

Table 104. T2CON MMR Bit Descriptions

Bit

Value

Description

15 to 9

8

Reserved.

Count up.

This bit is set by the user for Timer2 to count up.

This bit is cleared by the user for Timer2 to

count down by default.

If the timer reaches 0, a reset or an interrupt occurs, depending

on Bit 1 in the T2CON register. To avoid reset or interrupt, any

value must be written to T2CLRI before the expiration period. This

reloads the counter with T2LD and begins a new timeout period.

7

6

Timer2 enable bit.

This bit is set by the user to enable Timer2. This

bit is cleared by user to disable Timer2 by

default.

Timer2 mode.

When watchdog mode is entered, T2LD and T2CON are write-

protected. These two registers cannot be modified until a reset

clears the watchdog enable bit, which causes Timer2 to exit

watchdog mode.

This bit is set by user to operate in periodic

mode.

This bit is cleared by the user to operate in free-

running mode. Default mode.

5

Watchdog mode enable bit.

This bit is set by the user to enable watchdog

mode.

This bit is cleared by the user to disable

watchdog mode by default.

The Timer2 interface consists of four MMRs: T2LD, T2VAL,

T2CON, and T2CLRI.

T2LD Register

Name:

T2LD

4

Secure clear bit.

This bit is set by the user to use the secure clear

option.

Address: 0xFFFF0360

This bit is cleared by the user to disable the

secure clear option by default.

Default

value:

0x0000

3 to 2

Prescale.

00

01

10

11

Source clock/1 by default.

Source clock/16.

Source clock/256.

Access:

Read/write

T2LD is a 16-bit register load register that holds the 16-bit value

that is loaded into the counter.

Undefined. Equivalent to 00.

1

0

Watchdog IRQ Option Bit.

This bit is set by the user to produce an IRQ

instead of a reset when the watchdog reaches 0.

This bit is cleared by the user to disable the IRQ

option.

Reserved.

Rev. E | Page 86 of 96

Data Sheet

ADuC7023

T2CLRI Register

Secure Clear Bit (Watchdog Mode Only)

Name:

T2CLRI

0xFFFF036C

0xXX

The secure clear bit is provided for a higher level of protection.

When set, a specific sequential value must be written to T2CLRI

to avoid a watchdog reset. The value is a sequence generated by

the 8-bit linear feedback shift register (LFSR) polynomial = X8

+ X6 + X5 + X + 1 shown in Figure 45.

Address:

Default value:

Access:

Write

The initial value or seed is written to T2CLRI before entering

watchdog mode. After entering watchdog mode, a write to T2CLRI

must match this expected value. If it matches, the LFSR is advanced

to the next state when the counter reload happens. If it fails to

match the expected state, a reset is immediately generated, even

if the count has not yet expired.

T2CLRI is an 8-bit register. Writing any value to this register on

successive occassions clears the Timer2 interrupt in normal

mode or resets a new timeout period in watchdog mode.

The user must perform successive writes to this register to ensure

resetting the timeout period.

The value 0x00 should not be used as an initial seed due to the

properties of the polynomial. The value 0x00 is always guaranteed

to force an immediate reset. The value of the LFSR cannot be

read; it must be tracked/generated in software.

An example of a sequence follows:

1. Enter initial seed, 0xAA, in T2CLRI before starting Timer2

in watchdog mode.

2. Enter 0xAA in T2CLRI; Timer2 is reloaded.

3. Enter 0x37 in T2CLRI; Timer2 is reloaded.

4. Enter 0x6E in T2CLRI; Timer2 is reloaded.

5. Enter 0x66. 0xDC was expected; the watchdog resets the chip.

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

7

6

5

4

3

2

1

0

CLOCK

Figure 45. 8-Bit LFSR

Rev. E | Page 87 of 96

ADuC7023

Data Sheet

HARDWARE DESIGN CONSIDERATIONS

IOV_DDSupply Sensitivity

POWER SUPPLIES

The IOV_DDsupply is sensitive to high frequency noise because it

is the supply source for the internal oscillator and PLL circuits.

When the internal PLL loses lock, the clock source is removed

by a gating circuit from the CPU, and the ARM7TDMI core

stops executing code until the PLL regains lock. This feature is

to ensure that no flash interface timings or ARM7TDMI

timings are violated.

The ADuC7023 operational power supply voltage range is 2.7 V

to 3.6 V. Separate analog and digital power supply pins (AV_DD

and IOV_DD, respectively) allow AV_DDto be kept relatively free of

noisy digital signals often present on the system IOV_DDline. In

this mode, the part can also operate with split supplies, that is, it

can use different voltage levels for each supply. For example, the

system can be designed to operate with an IOV_DDvoltage level

of 3.3 V while the AV_DDlevel can be at 3 V, or vice versa. A

typical split supply configuration is shown in Figure 46.

Typically, frequency noise greater than 50 kHz and 50 mV p-p

on top of the supply causes the core to stop working.

DIGITAL SUPPLY

ANALOG SUPPLY

If decoupling values recommended in the Power Supplies section

do not sufficiently dampen all noise soures below 50 mV on IOV_DD

a filter such as the one shown in Figure 48 is recommended.

10µF

,

ADuC7023

AV

DD

IOV

DD

1µH

0.1µF

DIGITAL

10µF

SUPPLY

ADuC7023

GND

REF

IOGND

AGND

IOV

DD

0.1µF

Figure 46. External Dual Supply Connections

As an alternative to providing two separate power supplies, the

user can reduce noise on AV_DDby placing a small series resistor

and/or ferrite bead between AV_DDand IOV_DD, and then decoupling

AV_DDseparately to ground. An example of this configuration is

shown in Figure 47. With this configuration, other analog circuitry

(such as op amps, voltage reference, and others) can be powered

from the AV_DDsupply line as well.

IOGND

Figure 48. Recommended IOV_DDSupply Filter

Linear Voltage Regulator

Each ADuC7023 requires a single 3.3 V supply, but the core

logic requires a 2.6 V supply. An on-chip linear regulator generates

the 2.6 V from IOV_DDfor the core logic. The LV_DDpin is the 2.6 V

supply for the core logic. An external compensation capacitor of

0.47 µF must be connected between LV_DDand DGND (as close

as possible to these pins) to act as a tank of charge, as shown in

Figure 49.

BEAD

DIGITAL SUPPLY

1.6V

10µF

ADuC7023

AV

DD

IOV

DD

0.1µF

GND

REF

ADuC7023

AGND

IOGND

REFGND

LV

DD

0.47µF

DGND

Figure 47. External Single Supply Connections

In both Figure 46 and Figure 47, a large value (10 µF) reservoir

capacitor sits on IOV_DD, and a separate 10 µF capacitor sits on

AV_DD. In addition, local small-value (0.1 µF) capacitors are located

at each AV_DDand IOV_DDpin of the chip. As per standard design

practice, include all of these capacitors and ensure the smaller

capacitors are close to each AV_DDpin with trace lengths as

short as possible. Connect the ground terminal of each of

these capacitors directly to the underlying ground plane.

Figure 49. Voltage Regulator Connections

The LV_DDpin should not be used for any other chip. It is also

recommended to use excellent power supply decoupling on

IOV_DDto help improve line regulation performance of the

on-chip voltage regulator.

Finally, the analog and digital ground pins on the ADuC7023

must be referenced to the same system ground reference point

at all times.

Rev. E | Page 88 of 96

Data Sheet

ADuC7023

For example, do not power components on the analog side (as

seen in Figure 50b) with IOV_DDbecause that would force return

currents from IOV_DDto flow through AGND. Avoid digital

currents flowing under analog circuitry, which can occur if a

noisy digital chip is placed on the left half of the board (shown

in Figure 50c). If possible, avoid large discontinuities in the

ground plane(s) such as those formed by a long trace on the same

layer, because they force return signals to travel a longer path.

In addition, make all connections to the ground plane directly,

with little or no trace separating the pin from its via to ground.

GROUNDING AND BOARD LAYOUT

RECOMMENDATIONS

As with all high resolution data converters, special attention

must be paid to grounding and PC board layout of the

ADuC7023-based designs to achieve optimum performance

from the ADCs and DACs.

Although the parts have separate pins for analog and digital ground

(AGND and DGND), the user must not tie these to two separate

ground planes unless the two ground planes are connected very

close to the part. This is illustrated in the simplified example

shown in Figure 50a. In systems where digital and analog ground

planes are connected together somewhere else (at the system

power supply, for example), the planes cannot be reconnected

near the part because a ground loop would result. In these cases, tie

all the ADuC7023 AGND and DGND pins to the analog ground

plane, as illustrated in Figure 50b. In systems with only one ground

plane, ensure that the digital and analog components are physically

separated onto separate halves of the board so that digital return

currents do not flow near analog circuitry (and vice versa).

When connecting fast logic signals (rise/fall time < 5 ns) to any of

the ADuC7023 digital inputs, add a series resistor to each

relevant line to keep rise and fall times longer than 5 ns at the

input pins of the part. A value of 100 Ω or 200 Ω is usually

sufficient enough to prevent high speed signals from coupling

capacitively into the part and affecting the accuracy of ADC

conversions.

CLOCK OSCILLATOR

The clock source for the ADuC7023 can be generated by the

internal PLL or by an external clock input. To use the internal

PLL, connect a 32.768 kHz parallel resonant crystal between

XCLKI and XCLKO, and connect a capacitor from each pin to

ground, as shown in Figure 51. The crystal allows the PLL to lock

correctly to give a frequency of 41.78 MHz. If no external crystal

is present, the internal oscillator is used to give a typical

frequency of 41.78 MHz 3%.

The ADuC7023 can then be placed between the digital and

analog sections, as illustrated in Figure 50c.

PLACE ANALOG

COMPONENTS HERE

PLACE DIGITAL

COMPONENTS HERE

a.

AGND

DGND

ADuC7023

XCLKI

12pF

32.768kHz

TO

INTERNAL

PLL

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS HERE

12pF

XCLKO

b.

Figure 51. External Parallel Resonant Crystal Connections

AGND

DGND

To use an external source clock input instead of the PLL (see

Figure 52), Bit 1 and Bit 0 of PLLCON must be modified. The

external clock uses P1.1 and XCLK.

ADuC7023

PLACE ANALOG

COMPONENTS HERE

PLACE DIGITAL

COMPONENTS HERE

XCLKO

c.

XCLKI

DGND

EXTERNAL

CLOCK

SOURCE

TO

FREQUENCY

DIVIDER

XCLK

Figure 50. System Grounding Schemes

Figure 52. Connecting an External Clock Source

In all of these scenarios, and in more complicated real-life

applications, users should pay particular attention to the flow of

current from the supplies and back to ground. Make sure the return

paths for all currents are as close as possible to the paths the

currents took to reach their destinations.

Using an external clock source, the ADuC7023 specified

operational clock speed range is 50 kHz to 44 MHz 1%, which

ensures correct operation of the analog peripherals and Flash/EE.

Rev. E | Page 89 of 96

ADuC7023

Data Sheet

3.3V

2.6V

POWER-ON RESET OPERATION

IOV

LV

DD

An internal power-on reset (POR) is implemented on the

ADuC7023. For LV_DDbelow 2.40 V typical, the internal POR

holds the part in reset. As LV_DDrises above 2.40 V, an internal

timer times out for typically 64 ms before the part is released

from reset. The user must ensure that the power supply IOV_DD

has reached a stable 2.7 V minimum level by this time. Likewise, on

power-down, the internal POR holds the part in reset until

LV_DDhas dropped below 2.40 V.

2.40V TYP

DD

64ms TYP

POR

Figure 53 illustrates the operation of the internal POR in detail.

Figure 53. Internal Power-On Reset Operation

Rev. E | Page 90 of 96

Data Sheet

ADuC7023

TYPICAL SYSTEM CONFIGURATION

A typical ADuC7023 configuration is shown in Figure 54. It summarizes some of the hardware considerations. The bottom of the LFCSP

package has an exposed pad that needs to be soldered to a metal plate on the board for mechanical reasons. The metal plate of the board

can be connected to ground.

ADuC7023

AV_DD

P0.3/PLAO[9]/TCK

GND_REF

DAC0

DAC1

DAC2

DAC3

P0.2/PLAO[8]/TDI

P0.1/PLAI[9]/TDO

P0.0/nTRST/ADC

/ PLAI[8]/ BM

TMS

BUSY

RTCK

P0.4/IRQ0/SCL0/PLAI[0]/CONV

P0.5/SDA0/PLAI[1]/COMP_OUT

XCLKO

XCLKI

2

PULL-UPs FOR I C PINS

Figure 54. Typical System Configuration

Rev. E | Page 91 of 96

ADuC7023

Data Sheet

DEVELOPMENT TOOLS

Software

PC-BASED TOOLS

The software system has an integrated development environment,

incorporating an assembler, compiler, and nonintrusive JTAG-

based debugger. The software sytem uses a serial downloader

software and example code.

Four types of development systems are available for the ADuC7023

family. The ADuC7023 QuickStart Plus is intended for new users

who want to have a comprehensive hardware development

environment.

Miscellaneous

These systems consist of the following PC-based (Windows®

compatible) hardware and software development tools.

The miscellaneous systems use CD-ROM documentation.

IN-CIRCUIT I²C DOWNLOADER

Hardware

An I²C-based serial downloader is available at www.analog.com.

This software requires an USB-to-I²C adaptor board available

from Analog Devices. The part number for this USB-to-I²C

adapter is USB-I2C/LIN-CONV-Z.

The hardware system uses the ADuC7023 evaluation board, a

serial port programming cable, and a RDI-compliant JTAG

emulator (included in the ADuC7023 QuickStart Plus only).

Rev. E | Page 92 of 96

Data Sheet

ADuC7023

OUTLINE DIMENSIONS

6.10

6.00 SQ

5.90

0.30

0.23

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

31

30

40

1

0.50

BSC

4.45

4.30 SQ

4.25

EXPOSED

PAD

21

20

10

11

0.45

0.40

0.35

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.

Figure 55. 40-Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-10)

Dimensions shown in millimeters

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

25

24

32

1

0.50

BSC

3.65

3.50 SQ

3.45

EXPOSED

PAD

8

9

17

16

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

3.50 REF

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 56. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-11)

Dimensions shown in millimeters

Rev. E | Page 93 of 96

ADuC7023

Data Sheet

3.445

3.405 SQ

3.365

6

5

4

3

2

1

A

BALL A1

IDENTIFIER

B

C

D

E

F

2.50

BSC SQ

0.50

BALL PITCH

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.380

0.360

0.340

0.650

0.600

0.550

SIDE VIEW

COPLANARITY

0.05

0.360

0.320

0.280

SEATING

PLANE

0.270

0.240

0.210

Figure 57. 36-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-36-3)

Dimensions shown in millimeters

Rev. E | Page 94 of 96

Data Sheet

ADuC7023

ORDERING GUIDE

ADC

DAC

Channels

FLASH/

RAM

Temperature

Downloader Range

Package Ordering

Model¹

Channels

GPIO

20

Package Description Option

Quantity

ADuC7023BCP6Z62I

12

4

62 kB/8 kB

I²C

−40°C to +125°C

40-Lead LFCSP_WQ

32-Lead LFCSP_WQ

36-Ball WLCSP

CP-40-10 490

ADuC7023BCP6Z62IRL 12

ADuC7023BCP6Z62IR7 12

20

CP-40-10 2,500

CP-40-10 750

CP-32-11 490

CP-32-11 5,000

CP-32-11 1,500

CB-36-03 1,500

20

ADuC7023BCPZ62I

8

12

ADuC7023BCPZ62I-RL

ADuC7023BCPZ62I-R7

ADuC7023BCBZ62I-R7

EVAL-ADuC7023QSPZ

8

12

8

12

10

16

ADuC7023

QuickStart Plus

Development System

Using 32-Pin

ADuC7023

EVAL-ADuC7023QSPZ1

EVAL-ADuC7023QSPZ2

ADuC7023

QuickStart Plus

Development System

Using 40-Pin

ADuC7023

QuickStart Plus

Development System

Using 36-Ball

ADuC7023

¹Z = RoHS Compliant Part.

Rev. E | Page 95 of 96

ADuC7023

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D08675-0-7/13(E)

Rev. E | Page 96 of 96


型号：	EVAL-ADuC7023QSPZ2
厂家：	ADI
描述：	Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler 精密模拟微控制器， 12位模拟I / O ， ARM7TDMI微控制器与增强型IRQ处理程序微控制器
文件：	总96页 (文件大小：1473K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-ADuC7023QSPZ2 [ADI]

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