EVAL-CONTROL-BRD2 [ADI]
4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer; 4通道， 1.5 MSPS ，具有序10位和12位并行ADC
| 型号： | EVAL-CONTROL-BRD2 |
| 厂家： | 
ADI |
| 描述： | 4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer |
| 文件： | 总32页 (文件大小：768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Channel, 1.5 MSPS, 10-Bit and 12-Bit
Parallel ADCs with a Sequencer
AD7933/AD7934
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
AGND
Throughput rate: 1.5 MSPS
DD
Specified for VDD of 2.7 V to 5.25 V
Low power
AD7933/AD7934
V
REFIN/
V
REFOUT
2.5V
6 mW maximum at 1.5 MSPS with 3 V supplies
13.5 mW maximum at 1.5 MSPS with 5 V supplies
4 analog input channels with a sequencer
Software configurable analog inputs
4-channel single-ended inputs
VREF
V
V
0
IN
IN
CLKIN
CONVST
BUSY
12-/10-BIT
SAR ADC
AND
I/P
MUX
T/H
CONTROL
3
2-channel fully differential inputs
2-channel pseudo differential inputs
Accurate on-chip 2.5 V reference
0.2ꢀ maximum @ 25°C, 25 ppm/°C maximum (AD7934)
70 dB SINAD at 50 kHz input frequency
No pipeline delays
SEQUENCER
V
PARALLEL INTERFACE/CONTROL REGISTER
DRIVE
High speed parallel interface—word/byte modes
Full shutdown mode: 2 μA maximum
28-lead TSSOP package
DB0 DB11
CS RD WR W/B
DGND
Figure 1.
GENERAL DESCRIPTION
The AD7933/AD7934 are 10-bit and 12-bit, high speed, low
power, successive approximation (SAR) analog-to-digital
converters (ADCs). The parts operate from a single 2.7 V to
5.25 V power supply and feature throughput rates up to 1.5 MSPS.
The parts contain a low noise, wide bandwidth, differential track-
and-hold amplifier that handles input frequencies up to 50 MHz.
These parts use advanced design techniques to achieve very low
power dissipation at high throughput rates. They also feature
flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
PRODUCT HIGHLIGHTS
The AD7933/AD7934 feature four analog input channels with a
channel sequencer that allows a preprogrammed selection of
channels to be sequentially converted. These parts can accept
either single-ended, fully differential, or pseudo differential
analog inputs.
1. High throughput with low power consumption.
2. Four analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Single-ended, pseudo differential or fully differential
analog inputs that are software selectable.
5. Single-supply operation with VDRIVE function.
The VDRIVE function allows the parallel interface to connect
directly to 3 V or 5 V processor systems independent of VDD
6. No pipeline delay.
The conversion process and data acquisition are controlled
using standard control inputs that allow for easy interfacing to
microprocessors and DSPs. The input signal is sampled on the
.
CONVST
falling edge of
this point.
, and the conversion is also initiated at
CONVST
7. Accurate control of the sampling instant via a
input and once-off conversion control.
The AD7933/AD7934 has an accurate on-chip 2.5 V reference
that is used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
Table 1. Related Devices
Device
No. of Bits
12/10
12
No. of Channels
Speed
AD7938/AD7939
AD7938-6
8
8
4
1.5 MSPS
625 kSPS
625 kSPS
AD7934-6
12
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
AD7933/AD7934
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 17
ADC Transfer Function............................................................. 17
Typical Connection Diagram ................................................... 18
Analog Input Structure.............................................................. 18
Analog Inputs ............................................................................. 19
Analog Input Selection .............................................................. 21
Reference ..................................................................................... 22
Parallel Interface......................................................................... 23
Power Modes of Operation....................................................... 26
Power vs. Throughput Rate....................................................... 27
Microprocessor Interfacing....................................................... 27
Application Hints ........................................................................... 29
Grounding and Layout .............................................................. 29
Evaluating the AD7933/AD7934 Performance...................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7933 Specifications................................................................. 3
AD7934 Specifications................................................................. 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 13
Control Register.............................................................................. 15
Sequencer Operation ................................................................. 16
Circuit Information........................................................................ 17
REVISION HISTORY
2/07—Rev. A to Rev B
Changes to Timing Specifications.................................................. 7
Changes to Figure 13...................................................................... 12
12/05—Rev. 0 to Rev. A
Replaced Figures.................................................................Universal
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Added Table 1.................................................................................... 1
Changes to Specifications Section.................................................. 3
Changes to Table 5............................................................................ 9
Changes to Terminology Section.................................................. 13
Changes to Control Register Section ........................................... 15
Changes to Circuit Information Section ..................................... 17
Changes to Application Hints Section......................................... 29
1/05—Revision 0: Initial Version
Rev. B | Page 2 of 32
AD7933/AD7934
SPECIFICATIONS
AD7933 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX1, unless otherwise noted.
Table 2.
Parameter
Value1
Unit
Test Conditions/Comments
fIN = 50 kHz sine wave
Differential mode
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
61
dB min
dB min
dB max
dB max
60
−70
−72
Single-ended mode
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
fa = 30 kHz, fb = 50 kHz
−86
−90
−75
5
72
50
dB typ
dB typ
dB typ
ns typ
fIN= 50 kHz, fNOISE = 300 kHz
Aperture Jitter2
Full Power Bandwidth2
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
10
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Single-Ended and Pseudo Differential
Input
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
0.5
0.5
LSB max
LSB max
Guaranteed no missed codes to 10 bits
Straight binary output coding
2
LSB max
LSB max
LSB max
LSB max
0.5
1.5
0.5
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Twos complement output coding
1.5
0.5
2
0.5
1.5
0.5
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Single-Ended Input Range
0 toVREF
0 to 2 ×VREF
V
V
RANGE bit = 0
RANGE bit = 1
Pseudo Differential Input Range
VIN+
0 to VREF
V
V
V typ
V typ
RANGE bit = 0
RANGE bit = 1
VDD = 3 V
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
VIN−
VDD = 5 V
Fully Differential Input Range3
VIN+ and VIN−
VIN+ and VIN−
DC Leakage Current4
VCM VREF/2
VCM VREF
1
45
10
V
V
VCM = VREF/2, RANGE bit = 0
VCM = VREF, RANGE bit = 1
μA max
pF typ
pF typ
Input Capacitance
When in track
When in hold
Rev. B | Page 3 of 32
AD7933/AD7934
Parameter
Value1
Unit
Test Conditions/Comments
1ꢀ ꢁpeꢂcfceꢃ peꢄfoꢄmanꢂe
0.2ꢀ max ꢅ 25ꢆC
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
DC Leakage Cuꢄꢄent4
VREFOUT Output Voltage
VREFOUT Tempeꢄatuꢄe Coeffcꢂcent
2.5
1
2.5
25
5
10
130
10
15
25
V
μA max
V
ppm/ꢆC max
ppm/ꢆC typ
μV typ
μV typ
Ω typ
VREF Nocꢁe
0.1 Hz to 10 Hz banꢃwcꢃth
0.1 Hz to 1 MHz banꢃwcꢃth
VREF Output Impeꢃanꢂe
VREF Input Capaꢂctanꢂe
pF typ
pF typ
When cn tꢄaꢂk
When cn holꢃ
LOGIC INPUTS
Input Hcgh Voltage, VINH
Input Low Voltage, VINL
Input Cuꢄꢄent, IIN
2.4
0.8
5
V mcn
V max
μA max
pF max
Typcꢂally 10 nA, VIN = 0 V oꢄ VDRIVE
4
Input Capaꢂctanꢂe, CIN
10
LOGIC OUTPUTS
Output Hcgh Voltage, VOH
Output Low Voltage, VOL
Floatcng-State Leakage Cuꢄꢄent
Floatcng-State Output Capaꢂctanꢂe4
Output Coꢃcng
2.4
0.4
3
10
V mcn
ISOURCE = 200 μA
ISINK = 200 μA
V max
μA max
pF max
Stꢄacght (natuꢄal) bcnaꢄy
Twoꢁ ꢂomplement
CODING bct = 0
CODING bct = 1
CONVERSION RATE
Conveꢄꢁcon Tcme
Tꢄaꢂk-anꢃ-Holꢃ Aꢂqucꢁctcon Tcme
t2 + 13 tCLK
125
80
nꢁ
nꢁ max
nꢁ typ
MSPS max
Full-ꢁꢂale ꢁtep cnput
Scne wave cnput
Thꢄoughput Rate
1.5
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V mcn/max
V mcn/max
VDRIVE
6
IDD
Dcgctal cnputꢁ = 0 V oꢄ VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on oꢄ off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 100 kSPS, VDD = 5 V
Statcꢂ
Noꢄmal Moꢃe (Statcꢂ)
Noꢄmal Moꢃe (Opeꢄatconal)
0.8
2.7
2.0
0.3
160
2
mA typ
mA max
mA max
mA typ
μA typ
Autoꢁtanꢃby Moꢃe
Full/Autoꢁhutꢃown Moꢃe (Statcꢂ)
Poweꢄ Dcꢁꢁcpatcon
μA max
SCLK on oꢄ off
Noꢄmal Moꢃe (Opeꢄatconal)
13.5
6
800
480
10
mW max
mW max
μW typ
μW typ
μW max
μW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Autoꢁtanꢃby Moꢃe (Statcꢂ)
Full/Autoꢁhutꢃown Moꢃe
6
1 Tempeꢄatuꢄe ꢄange cꢁ −40ꢆC to +85ꢆC.
2 See Teꢄmcnology ꢁeꢂtcon.
3 VCM cꢁ the ꢂommon-moꢃe voltage. Foꢄ full ꢂommon-moꢃe ꢄange, ꢁee Fcguꢄe 25 anꢃ Fcguꢄe 26. VIN+ anꢃ VIN− muꢁt alwayꢁ ꢄemacn wcthcn GND/VDD
4 Sample teꢁteꢃ ꢃuꢄcng cnctcal ꢄeleaꢁe to enꢁuꢄe ꢂomplcanꢂe.
.
5 Thcꢁ ꢃevcꢂe cꢁ opeꢄatconal wcth an exteꢄnal ꢄefeꢄenꢂe cn the ꢄange of 0.1 V to VDD. See the Refeꢄenꢂe ꢁeꢂtcon foꢄ moꢄe cnfoꢄmatcon.
6 Meaꢁuꢄeꢃ wcth a mcꢃꢁꢂale ꢃꢂ analog cnput.
Rev. B | Page 4 of 32
AD7933/AD7934
AD7934 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Value1
Unit
Test Conditions/Comments
fIN = 50 kHz ꢁcne wave
Dcffeꢄentcal moꢃe
Scngle-enꢃeꢃ moꢃe
Dcffeꢄentcal moꢃe
DYNAMIC PERFORMANCE
Scgnal-to-Nocꢁe + Dcꢁtoꢄtcon (SINAD)2
70
ꢃB mcn
ꢃB mcn
ꢃB mcn
ꢃB mcn
ꢃB max
ꢃB max
ꢃB max
68
71
Scgnal-to-Nocꢁe Ratco (SNR)2
69
Scngle-enꢃeꢃ moꢃe
Total Haꢄmoncꢂ Dcꢁtoꢄtcon (THD)2
−73
−70
−73
−85 ꢃB typ, ꢃcffeꢄentcal moꢃe
−80 ꢃB typ, ꢁcngle-enꢃeꢃ moꢃe
−82 ꢃB typ
Peak Haꢄmoncꢂ oꢄ Spuꢄcouꢁ Nocꢁe (SFDR)2
Inteꢄmoꢃulatcon Dcꢁtoꢄtcon (IMD)2
Seꢂonꢃ-Oꢄꢃeꢄ Teꢄmꢁ
Thcꢄꢃ-Oꢄꢃeꢄ Teꢄmꢁ
Channel-to-Channel Iꢁolatcon
Apeꢄtuꢄe Delay2
fa = 30 kHz, fb = 50 kHz
−86
−90
−85
5
ꢃB typ
ꢃB typ
ꢃB typ
nꢁ typ
fIN = 50 kHz, fNOISE = 300 kHz
Apeꢄtuꢄe Jctteꢄ2
72
pꢁ typ
Full Poweꢄ Banꢃwcꢃth2
50
MHz typ
MHz typ
ꢅ 3 ꢃB
10
ꢅ 0.1 ꢃB
DC ACCURACY
Reꢁolutcon
Integꢄal Nonlcneaꢄcty2
12
1
Bctꢁ
LSB max
LSB max
Dcffeꢄentcal moꢃe
1.5
Scngle-enꢃeꢃ moꢃe
Dcffeꢄentcal Nonlcneaꢄcty 2
Dcffeꢄentcal Moꢃe
Scngle-Enꢃeꢃ Moꢃe
Scngle-Enꢃeꢃ anꢃ Pꢁeuꢃo Dcffeꢄentcal Input
Offꢁet Eꢄꢄoꢄ2
Offꢁet Eꢄꢄoꢄ Matꢂh2
Gacn Eꢄꢄoꢄ2
0.95
−0.95/+1.5
LSB max
LSB max
Guaꢄanteeꢃ no mcꢁꢁeꢃ ꢂoꢃeꢁ to 12 bctꢁ
Guaꢄanteeꢃ no mcꢁꢁeꢃ ꢂoꢃeꢁ to 12 bctꢁ
Stꢄacght bcnaꢄy output ꢂoꢃcng
6
1
3
1
LSB max
LSB max
LSB max
LSB max
Gacn Eꢄꢄoꢄ Matꢂh2
Twoꢁ ꢂomplement output ꢂoꢃcng
Fully Dcffeꢄentcal Input
Poꢁctcve Gacn Eꢄꢄoꢄ2
Poꢁctcve Gacn Eꢄꢄoꢄ Matꢂh2
Zeꢄo-Coꢃe Eꢄꢄoꢄ2
Zeꢄo-Coꢃe Eꢄꢄoꢄ Matꢂh2
Negatcve Gacn Eꢄꢄoꢄ2
Negatcve Gacn Eꢄꢄoꢄ Matꢂh2
ANALOG INPUT
3
1
6
1
3
1
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Scngle-Enꢃeꢃ Input Range
0 to VREF
0 to 2 × VREF
V
V
RANGE bct = 0
RANGE bct = 1
Pꢁeuꢃo Dcffeꢄentcal Input Range
VIN+
0 to VREF
V
V
V typ
V typ
RANGE bct = 0
RANGE bct = 1
VDD = 3 V
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
VIN−
VDD = 5 V
Fully Dcffeꢄentcal Input Range3
VIN+ anꢃ VIN−
VCM VREF/2
VCM VREF
V
V
VCM = VREF/2, RANGE bct = 0
VCM = VREF, RANGE bct = 1
VIN+ anꢃ VIN−
DC Leakage Cuꢄꢄent4
Input Capaꢂctanꢂe
1
45
10
μA max
pF typ
pF typ
When cn tꢄaꢂk
When cn holꢃ
Rev. B | Page 5 of 32
AD7933/AD7934
Parameter
Value1
Unit
Test Conditions/Comments
1ꢀ ꢁpeꢂcfceꢃ peꢄfoꢄmanꢂe
0.2ꢀ max ꢅ 25ꢆC
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
DC Leakage Cuꢄꢄent
VREFOUT Output Voltage
VREFOUT Tempeꢄatuꢄe Coeffcꢂcent
2.5
1
2.5
25
5
10
130
10
15
25
V
μA max
V
ppm/ꢆC max
ppm/ꢆC typ
μV typ
μV typ
Ω typ
VREF Nocꢁe
0.1 Hz to 10 Hz banꢃwcꢃth
0.1 Hz to 1 MHz banꢃwcꢃth
VREF Output Impeꢃanꢂe
VREF Input Capaꢂctanꢂe
pF typ
pF typ
When cn tꢄaꢂk-anꢃ-holꢃ
When cn tꢄaꢂk-anꢃ-holꢃ
LOGIC INPUTS
Input Hcgh Voltage, VINH
Input Low Voltage, VINL
Input Cuꢄꢄent, IIN
2.4
0.8
5
V mcn
V max
μA max
pF max
Typcꢂally 10 nA, VIN = 0 V oꢄ VDRIVE
4
10
Input Capaꢂctanꢂe, CIN
LOGIC OUTPUTS
Output Hcgh Voltage, VOH
Output Low Voltage, VOL
Floatcng-State Leakage Cuꢄꢄent
Floatcng-State Output Capaꢂctanꢂe4
Output Coꢃcng
2.4
0.4
3
10
V mcn
ISOURCE = 200 μA
ISINK = 200 μA
V max
μA max
pF max
Stꢄacght (natuꢄal) bcnaꢄy
Twoꢁ ꢂomplement
CODING bct = 0
CODING bct = 1
CONVERSION RATE
Conveꢄꢁcon Tcme
Tꢄaꢂk-anꢃ-Holꢃ Aꢂqucꢁctcon Tcme
t2 + 13 tCLK
125
80
nꢁ
nꢁ max
nꢁ typ
MSPS max
Full-ꢁꢂale ꢁtep cnput
Scne wave cnput
Thꢄoughput Rate
1.5
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V mcn/max
V mcn/max
VDRIVE
6
IDD
Dcgctal cnputꢁ = 0 V oꢄ VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on oꢄ off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
fSAMPLE = 100 kSPS, VDD = 5 V
Statcꢂ
Noꢄmal Moꢃe (Statcꢂ)
Noꢄmal Moꢃe (Opeꢄatconal)
0.8
2.7
2.0
0.3
160
2
mA typ
mA max
mA max
mA typ
μA typ
Autoꢁtanꢃby Moꢃe
Full/Autoꢁhutꢃown Moꢃe (Statcꢂ)
Poweꢄ Dcꢁꢁcpatcon
μA max
SCLK on oꢄ off
Noꢄmal Moꢃe (Opeꢄatconal)
13.5
6
800
480
10
mW max
mW max
μW typ
μW typ
μW max
μW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Autoꢁtanꢃby Moꢃe (Statcꢂ)
Full/Autoꢁhutꢃown Moꢃe
6
1 Tempeꢄatuꢄe ꢄange cꢁ −40ꢆC to +85ꢆC.
2 See the Teꢄmcnology ꢁeꢂtcon.
3 VCM cꢁ the ꢂommon-moꢃe voltage. Foꢄ full ꢂommon-moꢃe ꢄange, ꢁee Fcguꢄe 25 anꢃ Fcguꢄe 26. VIN+ anꢃ VIN− muꢁt alwayꢁ ꢄemacn wcthcn GND/VDD
4 Sample teꢁteꢃ ꢃuꢄcng cnctcal ꢄeleaꢁe to enꢁuꢄe ꢂomplcanꢂe.
.
5 Thcꢁ ꢃevcꢂe cꢁ opeꢄatconal wcth an exteꢄnal ꢄefeꢄenꢂe cn the ꢄange of 0.1 V to VDD. See the Refeꢄenꢂe ꢁeꢂtcon foꢄ moꢄe cnfoꢄmatcon.
6 Meaꢁuꢄeꢃ wcth a mcꢃꢁꢂale ꢃꢂ analog cnput.
Rev. B | Page 6 of 32
AD7933/AD7934
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter1 AD7933 AD7934 Unit
Description
2
fCLKIN
700
25.5
30
700
25.5
30
kHz mcn
MHz max
nꢁ mcn
CLKIN fꢄequenꢂy
tQUIET
Mcncmum tcme between enꢃ of ꢄeaꢃ anꢃ ꢁtaꢄt of next ꢂonveꢄꢁcon, that cꢁ, the tcme fꢄom
when the ꢃata buꢁ goeꢁ cnto thꢄee-ꢁtate untcl the next fallcng eꢃge of CONVST
t1
10
15
50
0
10
15
50
0
nꢁ mcn
nꢁ mcn
nꢁ max
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ max
nꢁ mcn
nꢁ max
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ mcn
nꢁ max
nꢁ mcn
nꢁ mcn
CONVST pulꢁe wcꢃth
t2
CONVST fallcng eꢃge to CLKIN fallcng eꢃge ꢁetup tcme
CLKIN fallcng eꢃge to BUSY ꢄcꢁcng eꢃge
CS to WR ꢁetup tcme
t3
t4
t5
0
0
CS to WR holꢃ tcme
t6
10
10
10
10
0
10
10
10
10
0
WR pulꢁe wcꢃth
t7
Data ꢁetup tcme befoꢄe WR
Data holꢃ afteꢄ WR
t8
t9
New ꢃata valcꢃ befoꢄe fallcng eꢃge of BUSY
CS to RD ꢁetup tcme
t10
t11
t12
0
0
CS to RD holꢃ tcme
30
30
3
30
30
3
RD pulꢁe wcꢃth
3
t13
Data aꢂꢂeꢁꢁ tcme afteꢄ RD
Buꢁ ꢄelcnqucꢁh tcme afteꢄ RD
Buꢁ ꢄelcnqucꢁh tcme afteꢄ RD
HBEN to RD ꢁetup tcme
4
t14
50
0
50
0
t15
t16
t17
t18
t19
t20
t21
t22
0
0
HBEN to RD holꢃ tcme
10
0
10
0
Mcncmum tcme between ꢄeaꢃꢁ/wꢄcteꢁ
HBEN to WR ꢁetup tcme
10
40
15.7
7.8
10
40
15.7
7.8
HBEN to WR holꢃ tcme
CLKIN fallcng eꢃge to BUSY fallcng eꢃge
CLKIN low pulꢁe wcꢃth
CLKIN hcgh pulꢁe wcꢃth
1 Sample teꢁteꢃ ꢃuꢄcng cnctcal ꢄeleaꢁe to enꢁuꢄe ꢂomplcanꢂe. All cnput ꢁcgnalꢁ aꢄe ꢁpeꢂcfceꢃ wcth tRISE = tFALL = 5 nꢁ (10ꢀ to 90ꢀ of VDD) anꢃ tcmeꢃ fꢄom a voltage level of
1.6 V. All tcmcng ꢁpeꢂcfcꢂatconꢁ aꢄe wcth a 25 pF loaꢃ ꢂapaꢂctanꢂe (ꢁee Fcguꢄe 34, Fcguꢄe 35, Fcguꢄe 36, anꢃ Fcguꢄe 37).
2 Mcncmum CLKIN foꢄ ꢁpeꢂcfceꢃ peꢄfoꢄmanꢂe; wcth ꢁloweꢄ SCLK fꢄequenꢂceꢁ, peꢄfoꢄmanꢂe ꢁpeꢂcfcꢂatconꢁ apply typcꢂally.
3 The tcme ꢄequcꢄeꢃ foꢄ the output to ꢂꢄoꢁꢁ 0.4 V oꢄ 2.4 V.
4 t14 cꢁ ꢃeꢄcveꢃ fꢄom the meaꢁuꢄeꢃ tcme taken by the ꢃata outputꢁ to ꢂhange 0.5 V. The meaꢁuꢄeꢃ numbeꢄ cꢁ then extꢄapolateꢃ baꢂk to ꢄemove the effeꢂtꢁ of ꢂhaꢄgcng oꢄ
ꢃcꢁꢂhaꢄgcng the 25 pF ꢂapaꢂctoꢄ. Thcꢁ meanꢁ that the tcme, t14, quoteꢃ cn the tcmcng ꢂhaꢄaꢂteꢄcꢁtcꢂꢁ cꢁ the tꢄue buꢁ ꢄelcnqucꢁh tcme of the paꢄt anꢃ cꢁ cnꢃepenꢃent of the
buꢁ loaꢃcng.
Rev. B | Page 7 of 32
AD7933/AD7934
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
VDD to AGND/DGND
−0.3 V to +7 V
VDRIVE to AGND/DGND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
10 mA
Analog Input Voltage to AGND
Dcgctal Input Voltage to DGND
VDRIVE to VDD
Dcgctal Output Voltage to AGND
VREFIN to AGND
ESD CAUTION
AGND to DGND
Input Cuꢄꢄent to Any Pcn Exꢂept Supplceꢁ1
Opeꢄatcng Tempeꢄatuꢄe Range
Commeꢄꢂcal (B Veꢄꢁcon)
Stoꢄage Tempeꢄatuꢄe Range
Junꢂtcon Tempeꢄatuꢄe
−40ꢆC to +85ꢆC
−65ꢆC to +150ꢆC
150ꢆC
θJA Theꢄmal Impeꢃanꢂe (TSSOP)
θJC Theꢄmal Impeꢃanꢂe (TSSOP)
Leaꢃ Tempeꢄatuꢄe, Solꢃeꢄcng
Reflow Tempeꢄatuꢄe (10 ꢁeꢂ to 30 ꢁeꢂ)
ESD
97.9ꢆC/W
14ꢆC/W
255ꢆC
1.5 kV
1 Tꢄanꢁcent ꢂuꢄꢄentꢁ of up to 100 mA ꢃo not ꢂauꢁe SCR latꢂh-up.
Rev. B | Page 8 of 32
AD7933/AD7934
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
3
DD
IN
W/B
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
V
V
V
V
2
1
0
IN
IN
IN
3
4
AD7933/
AD7934
5
/V
REFIN REFOUT
6
AGND
CS
TOP VIEW
(Not to Scale)
7
8
RD
9
WR
10
11
12
13
14
CONVST
CLKIN
BUSY
DB11
DB10
V
DRIVE
DGND
DB8/HBEN
DB9
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD
Poweꢄ Supply Input. The VDD ꢄange foꢄ the AD7933/AD7934 cꢁ fꢄom 2.7 V to 5.25 V. Deꢂouple the ꢁupply to AGND
wcth a 0.1 μF ꢂapaꢂctoꢄ anꢃ a 10 μF tantalum ꢂapaꢂctoꢄ.
2
W/B
Woꢄꢃ/Byte Input. When thcꢁ cnput cꢁ logcꢂ hcgh, woꢄꢃ tꢄanꢁfeꢄ moꢃe cꢁ enableꢃ, anꢃ ꢃata cꢁ tꢄanꢁfeꢄꢄeꢃ to anꢃ fꢄom
the AD7933/AD7934 cn 10-bct woꢄꢃꢁ on Pcn DB2 to Pcn DB11, oꢄ cn 12-bct woꢄꢃꢁ on Pcn DB0 to Pcn DB11. When W/B
cꢁ logcꢂ low, byte tꢄanꢁfeꢄ moꢃe cꢁ enableꢃ. Data anꢃ the ꢂhannel ID aꢄe tꢄanꢁfeꢄꢄeꢃ on Pcn DB0 to Pcn DB7, anꢃ Pcn
DB8/HBEN aꢁꢁumeꢁ ctꢁ HBEN funꢂtconalcty. When opeꢄatcng cn byte tꢄanꢁfeꢄ moꢃe, tce off unuꢁeꢃ ꢃata lcneꢁ to
DGND.
3 to 10 DB0 to DB7 Data Bct 0 to Data Bct 7. Thꢄee-ꢁtate paꢄallel ꢃcgctal I/O pcnꢁ that pꢄovcꢃe the ꢂonveꢄꢁcon ꢄeꢁult anꢃ allow
pꢄogꢄammcng of the ꢂontꢄol ꢄegcꢁteꢄ. Theꢁe pcnꢁ aꢄe ꢂontꢄolleꢃ by CS, RD, anꢃ WR. The logcꢂ hcgh/low voltage
levelꢁ foꢄ theꢁe pcnꢁ aꢄe ꢃeteꢄmcneꢃ by the VDRIVE cnput. When ꢄeaꢃcng fꢄom the AD7933, the two LSBꢁ (DB0 anꢃ
DB1) aꢄe alwayꢁ 0, anꢃ the LSB of the ꢂonveꢄꢁcon ꢄeꢁult cꢁ avaclable on DB2.
11
12
13
VDRIVE
Logcꢂ Poweꢄ Supply Input. The voltage ꢁupplceꢃ at thcꢁ pcn ꢃeteꢄmcneꢁ at what voltage the paꢄallel cnteꢄfaꢂe of the
AD7933/AD7934 opeꢄateꢁ. Deꢂouple thcꢁ pcn to DGND. The voltage at thcꢁ pcn may be ꢃcffeꢄent to that at VDD but
ꢁhoulꢃ neveꢄ exꢂeeꢃ VDD by moꢄe than 0.3 V.
Dcgctal Gꢄounꢃ. Thcꢁ cꢁ the gꢄounꢃ ꢄefeꢄenꢂe pocnt foꢄ all ꢃcgctal ꢂcꢄꢂuctꢄy on the AD7933/AD7934. Conneꢂt thcꢁ pcn
to the DGND plane of a ꢁyꢁtem. The DGND anꢃ AGND voltageꢁ ꢁhoulꢃ cꢃeally be at the ꢁame potentcal anꢃ muꢁt
not be moꢄe than 0.3 V apaꢄt, even on a tꢄanꢁcent baꢁcꢁ.
Data Bct 8/Hcgh Byte Enable. When W/B cꢁ hcgh, thcꢁ pcn aꢂtꢁ aꢁ Data Bct 8, a thꢄee-ꢁtate I/O pcn that cꢁ ꢂontꢄolleꢃ
by CS, RD, anꢃ WR. When W/B cꢁ low, thcꢁ pcn aꢂtꢁ aꢁ the hcgh byte enable pcn. When HBEN cꢁ low, the low byte of
ꢃata wꢄctten to oꢄ ꢄeaꢃ fꢄom the AD7933/AD7934 cꢁ on DB0 to DB7. When HBEN cꢁ hcgh, the top fouꢄ bctꢁ of the
ꢃata becng wꢄctten to, oꢄ ꢄeaꢃ fꢄom, the AD7933/AD7934 aꢄe on DB0 to DB3. When ꢄeaꢃcng fꢄom the ꢃevcꢂe, DB4
anꢃ DB5 ꢂontacn the ID of the ꢂhannel to whcꢂh the ꢂonveꢄꢁcon ꢄeꢁult ꢂoꢄꢄeꢁponꢃꢁ (ꢁee the ꢂhannel aꢃꢃꢄeꢁꢁ bctꢁ cn
Table 10). DB6 anꢃ DB7 aꢄe alwayꢁ 0. When wꢄctcng to the ꢃevcꢂe, DB4 to DB7 of the hcgh byte muꢁt be all 0ꢁ.
Note that when ꢄeaꢃcng fꢄom the AD7933, the two LSBꢁ cn the low byte aꢄe 0ꢁ, anꢃ the ꢄemacncng ꢁcx bctꢁ aꢄe
ꢂonveꢄꢁcon ꢃata.
DGND
DB8/HBEN
14 to
16
DB9 to
DB11
Data Bct 9 to Data Bct 11. Thꢄee-ꢁtate paꢄallel ꢃcgctal I/O pcnꢁ that pꢄovcꢃe the ꢂonveꢄꢁcon ꢄeꢁult anꢃ alꢁo allow the
ꢂontꢄol ꢄegcꢁteꢄ to be pꢄogꢄammeꢃ cn woꢄꢃ moꢃe. Theꢁe pcnꢁ aꢄe ꢂontꢄolleꢃ by CS, RD, anꢃ WR. The logcꢂ hcgh/low
voltage levelꢁ foꢄ theꢁe pcnꢁ aꢄe ꢃeteꢄmcneꢃ by the VDRIVE cnput.
17
BUSY
Buꢁy Output. Thcꢁ cꢁ the logcꢂ output cnꢃcꢂatcng the ꢁtatuꢁ of the ꢂonveꢄꢁcon. The BUSY output goeꢁ hcgh followcng
the fallcng eꢃge of CONVST anꢃ ꢁtayꢁ hcgh foꢄ the ꢃuꢄatcon of the ꢂonveꢄꢁcon. Onꢂe the ꢂonveꢄꢁcon cꢁ ꢂomplete anꢃ
the ꢄeꢁult cꢁ avaclable cn the output ꢄegcꢁteꢄ, the BUSY output goeꢁ low. The tꢄaꢂk-anꢃ-holꢃ ꢄetuꢄnꢁ to tꢄaꢂk moꢃe
juꢁt pꢄcoꢄ to the fallcng eꢃge of BUSY, on the 13th ꢄcꢁcng eꢃge of CLKIN (ꢁee Fcguꢄe 34).
18
19
CLKIN
Maꢁteꢄ Cloꢂk Input. The ꢂloꢂk ꢁouꢄꢂe foꢄ the ꢂonveꢄꢁcon pꢄoꢂeꢁꢁ cꢁ applceꢃ to thcꢁ pcn. Conveꢄꢁcon tcme foꢄ the
AD7933/AD7934 takeꢁ 13 ꢂloꢂk ꢂyꢂleꢁ + t2. The fꢄequenꢂy of the maꢁteꢄ ꢂloꢂk cnput theꢄefoꢄe ꢃeteꢄmcneꢁ the
ꢂonveꢄꢁcon tcme anꢃ aꢂhcevable thꢄoughput ꢄate. The CLKIN ꢁcgnal ꢂan be a ꢂontcnuouꢁ oꢄ buꢄꢁt ꢂloꢂk.
Conveꢄꢁcon Staꢄt Input. A fallcng eꢃge on CONVST cnctcateꢁ a ꢂonveꢄꢁcon. The tꢄaꢂk-anꢃ-holꢃ goeꢁ fꢄom tꢄaꢂk to
holꢃ moꢃe on the fallcng eꢃge of CONVST, anꢃ the ꢂonveꢄꢁcon pꢄoꢂeꢁꢁ cꢁ cnctcateꢃ at thcꢁ pocnt. Followcng poweꢄ-
ꢃown, when opeꢄatcng cn the autoꢁhutꢃown oꢄ autoꢁtanꢃby moꢃe, a ꢄcꢁcng eꢃge on CONVST cꢁ uꢁeꢃ to poweꢄ up
the ꢃevcꢂe.
CONVST
Rev. B | Page 9 of 32
AD7933/AD7934
Pin No. Mnemonic Description
20
21
WR
RD
Wꢄcte Input. Aꢂtcve low logcꢂ cnput uꢁeꢃ cn ꢂonjunꢂtcon wcth CS to wꢄcte ꢃata to the ꢂontꢄol ꢄegcꢁteꢄ.
Reaꢃ Input. Aꢂtcve low logcꢂ cnput uꢁeꢃ cn ꢂonjunꢂtcon wcth CS to aꢂꢂeꢁꢁ the ꢂonveꢄꢁcon ꢄeꢁult. The ꢂonveꢄꢁcon
ꢄeꢁult cꢁ plaꢂeꢃ on the ꢃata buꢁ followcng the fallcng eꢃge of RD ꢄeaꢃ whcle CS cꢁ low.
22
23
CS
Chcp Seleꢂt. Aꢂtcve low logcꢂ cnput uꢁeꢃ cn ꢂonjunꢂtcon wcth RD anꢃ WR to ꢄeaꢃ ꢂonveꢄꢁcon ꢃata oꢄ wꢄcte ꢃata to
the ꢂontꢄol ꢄegcꢁteꢄ.
Analog Gꢄounꢃ. Thcꢁ cꢁ the gꢄounꢃ ꢄefeꢄenꢂe pocnt foꢄ all analog ꢂcꢄꢂuctꢄy on the AD7933/AD7934. All analog cnput
ꢁcgnalꢁ anꢃ any exteꢄnal ꢄefeꢄenꢂe ꢁcgnal ꢁhoulꢃ be ꢄefeꢄꢄeꢃ to thcꢁ AGND voltage. The AGND anꢃ DGND voltageꢁ
ꢁhoulꢃ cꢃeally be at the ꢁame potentcal anꢃ muꢁt not be moꢄe than 0.3 V apaꢄt, even on a tꢄanꢁcent baꢁcꢁ.
AGND
24
VREFIN/VREFOUT Refeꢄenꢂe Input/Output. Thcꢁ pcn cꢁ ꢂonneꢂteꢃ to the cnteꢄnal ꢄefeꢄenꢂe anꢃ cꢁ the ꢄefeꢄenꢂe ꢁouꢄꢂe foꢄ the ADC.
The nomcnal cnteꢄnal ꢄefeꢄenꢂe voltage cꢁ 2.5 V, anꢃ thcꢁ appeaꢄꢁ at thcꢁ pcn. It cꢁ ꢄeꢂommenꢃeꢃ to ꢃeꢂouple the
VREFIN/VREFOUT pcn to AGND wcth a 470 nF ꢂapaꢂctoꢄ. Thcꢁ pcn ꢂan be oveꢄꢃꢄcven by an exteꢄnal ꢄefeꢄenꢂe. The cnput
voltage ꢄange foꢄ the exteꢄnal ꢄefeꢄenꢂe cꢁ 0.1 V to VDD; howeveꢄ, enꢁuꢄe that the analog cnput ꢄange ꢃoeꢁ not
exꢂeeꢃ VDD + 0.3 V. See the Refeꢄenꢂe ꢁeꢂtcon.
25 to
28
VIN0 to VIN3
Analog Input 0 to Analog Input 3. Fouꢄ analog cnput ꢂhannelꢁ that aꢄe multcplexeꢃ cnto the on-ꢂhcp tꢄaꢂk-anꢃ-
holꢃ. The analog cnputꢁ ꢂan be pꢄogꢄammeꢃ aꢁ fouꢄ ꢁcngle-enꢃeꢃ cnputꢁ, two fully ꢃcffeꢄentcal pacꢄꢁ, oꢄ two pꢁeuꢃo
ꢃcffeꢄentcal pacꢄꢁ by appꢄopꢄcately ꢁettcng the MODE bctꢁ cn the ꢂontꢄol ꢄegcꢁteꢄ (ꢁee Table 10). Seleꢂt the analog
cnput ꢂhannel to be ꢂonveꢄteꢃ ectheꢄ by wꢄctcng to Aꢃꢃꢄeꢁꢁ Bct ADD1 anꢃ Aꢃꢃꢄeꢁꢁ Bct ADD0 cn the ꢂontꢄol ꢄegcꢁteꢄ
pꢄcoꢄ to the ꢂonveꢄꢁcon, oꢄ by uꢁcng the on-ꢂhcp ꢁequenꢂeꢄ. The cnput ꢄange foꢄ all cnput ꢂhannelꢁ ꢂan ectheꢄ be 0 V
to VREF oꢄ 0 V to 2 × VREF, anꢃ the ꢂoꢃcng ꢂan be bcnaꢄy oꢄ twoꢁ ꢂomplement, ꢃepenꢃcng on the ꢁtateꢁ of the RANGE
anꢃ CODING bctꢁ cn the ꢂontꢄol ꢄegcꢁteꢄ. To avocꢃ nocꢁe pcꢂkup, ꢂonneꢂt any unuꢁeꢃ cnput ꢂhannelꢁ to AGND.
Rev. B | Page 10 of 32
AD7933/AD7934
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
–60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100mV p-p SINE WAVE ON V AND/OR V
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
4096 POINT FFT
DD
DRIVE
V
F
= 5V
DD
= 1.5MSPS
–70
–80
SAMPLE
F
= 49.62kHz
IN
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
INT REF
–90
EXT REF
–100
–110
–120
–100
–110
10
210
410
610
810
1010
SUPPLY RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
Figure 6. AD7934 FFT @ VDD = 5 V
1.0
0.8
0.6
–70
INTERNAL/EXTERNAL REFERENCE
V
= 5V
DD
V
= 5V
DIFFERENTIAL MODE
DD
–75
0.4
0.2
–80
–85
0
–0.2
–0.4
–90
–95
–0.6
–0.8
–1.0
0
500
1000
1500 2000 2500 3000
CODE
3500
4000
0
100
200
300
400
500
600
700
800
NOISE FREQUENCY (kHz)
Figure 7. AD7934 Typical DNL @ VDD = 5 V
Figure 4. Channel-to-Channel Isolation
1.0
0.8
0.6
80
70
60
50
40
30
20
V
= 5V
V
= 5V
DD
DD
DIFFERENTIAL MODE
V
= 3V
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
F
= 1.5MSPS
SAMPLE
RANGE = 0 TO V
DIFFERENTIAL MODE
REF
0
500
1000
1500 2000 2500 3000
CODE
3500
4000
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
Figure 8. AD7934 Typical INL @ VDD = 5 V
Figure 5. AD7934 SINAD vs. Analog Input Frequency for Various Supply Voltages
Rev. B | Page 11 of 32
AD7933/AD7934
10000
9000
8000
7000
6000
5000
4000
3000
4
9997
CODES
INTERNAL
REF
DIFFERENTIAL MODE
SINGLE-ENDED MODE
3
2
1
POSITIVE DNL
NEGATIVE DNL
0
2000
1000
0
3 CODES
2049 2050
–1
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
2046
2047
2048
V
(V)
CODE
REF
Figure 9. AD7934 DNL vs. VREF for VDD = 3 V
Figure 12. AD7934 Histogram of Codes for
10,000 Samples @ VDD = 5 V with Internal Reference
12
11
10
120
110
100
90
DIFFERENTIAL MODE
V
= 5V
DD
DIFFERENTIAL MODE
V
= 5V
DD
SINGLE-ENDED MODE
9
8
V
= 3V
DD
SINGLE-ENDED MODE
80
V
= 3V
DD
DIFFERENTIAL MODE
70
7
6
60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
200
400
600
800
1000
1200
V
(V)
RIPPLE FREQUENCY (kHz)
REF
Figure 10. AD7934 ENOB vs. VREF
Figure 13. CMRR vs. Common-Mode Ripple with VDD = 5 V and 3 V
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
= 5V
DD
V
= 3V
DD
–4.0
–4.5
–5.0
SINGLE-ENDED MODE
2.5 3.0 3.5
0
0.5
1.0
1.5
V
2.0
(V)
REF
Figure 11. AD7934 Offset vs. VREF
Rev. B | Page 12 of 32
AD7933/AD7934
TERMINOLOGY
Integral Nonlinearity (INL)
Negative Gain Error
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, 1 LSB below the first code
transition, and full scale, 1 LSB above the last code transition.
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100…000) to (100…001) from the ideal (that is,
−VREFIN + 1 LSB) after the zero-code error has been adjusted out.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Negative Gain Error Match
The difference in negative gain error between any two channels.
Offset Error
Channel-to-Channel Isolation
The deviation of the first code transition (00…000) to (00…001)
from the ideal (that is, AGND + 1 LSB).
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale sine wave signal to the three nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at
2 × VREF, while the signal amplitude is at 1 × VREF. See Figure 4.
Offset Error Match
The difference in offset error between any two channels.
Gain Error
The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, VREF – 1 LSB) after the offset
error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the input varies from 1 kHz to 1 MHz.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal VIN voltage
(that is, VREF).
PSRR (dB) = 10 log(Pf/PfS)
where:
Zero-Code Error Match
The difference in zero-code error between any two channels.
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Positive Gain Error
Common-Mode Rejection Ratio (CMRR)
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to +VREF
biased about the VREFIN point. It is the deviation of the last
code transition (011…110) to (011…111) from the ideal (that is,
+VREF – 1 LSB) after the zero-code error has been adjusted out.
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
Positive Gain Error Match
The difference in positive gain error between any two channels.
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Rev. B | Page 13 of 32
AD7933/AD7934
Track-and-Hold Acquisition Time
Peak Harmonic or Spurious Noise
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±± LSB, after the end of conversion.
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-noise and distortion at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fSAMPLE/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities create distortion products
at sum and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The theoretical signal-to-noise and distortion ratio for an ideal
N-bit converter with a sine wave input is given by
SINAD = (6.02 N + 1.76) dB
The AD7933/AD7934 is tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually
distanced in frequency from the original sine waves, while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The intermodulation distortion is
calculated per the THD specification, as the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals, expressed in dB.
Thus, for a 12-bit converter, SINAD is 74 dB, and for a 10-bit
converter, SINAD is 62 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamen-
tal. For the AD7933/AD7934, it is defined as
2
2
2
2
2
⎛
⎜
⎞
⎟
V2 +V3 +V4 +V5 +V6
THD dB = −20 log
( )
⎜
⎝
⎟
⎠
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Rev. B | Page 14 of 32
AD7933/AD7934
CONTROL REGISTER
register are all 0s. When writing to the control register between
The control register on the AD7933/AD7934 is a 12-bit, write-
CONVST
conversions, ensure that
performing the write.
returns high before
CS
only register. Data is written to this register using the
and
WR
pins. The functions of the control register bits are described
in Table 8. At power-up, the default bit settings in the control
Table 7. Control Register Bits
MSB
LSB
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
MODE0
DB2
SEQ1
DB1
DB0
PM1
PM0
CODING
REF
ZERO
ADD1
ADD0
MODE1
SEQ0
RANGE
Table 8. Control Register Bit Function Description
Bit No. Mnemonic Description
11, 10
PM1, PM0
CODING
REF
Power Management Bits. Use these two bits to select the power mode of operation. The user can choose between
normal mode or various power-down modes of operation as shown in Table 9.
This bit selects the output coding of the conversion result. If the CODING bit is set to 0, the output coding is
straight (natural) binary. If the CODING bit is set to 1, the output coding is twos complement.
This bit selects whether the internal or external reference is used to perform the conversion. If the REF bit is
Logic 0, an external reference should be applied to the VREF pin, and if it is Logic 1, the internal reference is
selected. See the Reference section.
9
8
7
ZERO
This bit is not used; therefore, it should always be set to Logic 0.
6, 5
ADD1,
ADD0
Use these two address bits to select which analog input channel is to be converted in the next conversion, if the
sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being
used (see Table 11 for more information). The selected input channel is decoded as shown in Table 10.
4, 3
2
MODE1,
MODE0
SEQ1
The two mode pins select the type of analog input on the four VIN pins. The AD7933/AD7934 have either four
single-ended inputs, two fully differential inputs, or two pseudo differential inputs (see Table 10).
The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the sequencer function
(see Table 11).
1
SEQ0
The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the sequencer function
(see Table 11).
0
RANGE
This bit selects the analog input range of the AD7933/AD7934. If RANGE is set to 0, the analog input range
extends from 0 V to VREF. If RANGE is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range
is selected, VDD must be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that
the analog input remains within the supply rails. See the Analog Inputs section for more information.
Table 9. Power Mode Selection Using the Power Management Bits in the Control Register
PM1 PM0 Mode
Description
0
0
0
1
Normal Mode
When operating in normal mode, all circuitry is fully powered up at all times.
Autoshutdown When operating in autoshutdown mode, the AD7933/AD7934 enters full shutdown mode at the end of
each conversion. In this mode, all circuitry is powered down.
1
0
Autostandby
When the AD7933/AD7934 enters this mode, the reference remains fully powered, the reference buffer is
partially powered down, and all other circuitry is fully powered down. This mode is similar to
autoshutdown mode, but it allows the part to power up in 7 μs (or 600 ns if an external reference is used).
See the Power Modes of Operation section for more information.
1
1
Full Shutdown When the AD7933/AD7934 enters this mode, all circuitry is powered down. The information in the control
register is retained.
Rev. B | Page 15 of 32
AD7933/AD7934
aborted after applying 12.5 CLKIN periods to the ADC, ensure
CONVST
applied to the part before writing to the control register to
program the sequencer. If these conditions are not met, the
sequencer will not be in the correct state to handle being
reprogrammed for another sequence of conversions and the
performance of the converter is not guaranteed.
SEQUENCER OPERATION
that a rising edge of
or a falling edge of CLKIN is
The configuration of the SEQ0 and SEQ1 bits in the control
register allows use of the sequencer function. Table 11 outlines
the two sequencer modes of operation.
Writing to the Control Register to Program the Sequencer
The AD7933 and AD7934 need 13 full CLKIN periods to
perform a conversion. If the ADC does not receive the full 13
CLKIN periods, the conversion aborts. If a conversion is
Table 10. Analog Input Type Selection
MODE0 = 0, MODE1 = 0
MODE0 = 0, MODE1 = 1
MODE0 = 1, MODE1 = 0
MODE0 = 1, MODE1 = 1
Not Used
Four Single-Ended
Input Channels
Two Fully Differential
Input Channels
Two Pseudo Differential
Input Channels
Channel Address
ADD1
ADD0
VIN+
VIN0
VIN1
VIN2
VIN3
VIN−
VIN+
VIN0
VIN1
VIN2
VIN3
VIN−
VIN1
VIN0
VIN3
VIN2
VIN+
VIN0
VIN1
VIN2
VIN3
VIN−
VIN1
VIN0
VIN3
VIN2
0
0
1
1
0
1
0
1
AGND
AGND
AGND
AGND
Table 11. Sequence Selection Modes
SEQ0 SEQ1 Sequence Type
0
0
Seleꢂt thcꢁ ꢂonfcguꢄatcon when the ꢁequenꢂe funꢂtcon cꢁ not uꢁeꢃ. The analog cnput ꢂhannel ꢁeleꢂteꢃ on eaꢂh cnꢃcvcꢃual
ꢂonveꢄꢁcon cꢁ ꢃeteꢄmcneꢃ by the ꢂontentꢁ of ADD1 anꢃ ADD0, the ꢂhannel aꢃꢃꢄeꢁꢁ bctꢁ, cn eaꢂh pꢄcoꢄ wꢄcte opeꢄatcon. Thcꢁ
moꢃe of opeꢄatcon ꢄefleꢂtꢁ the noꢄmal opeꢄatcon of a multcꢂhannel ADC, wcthout uꢁcng the ꢁequenꢂeꢄ funꢂtcon, wheꢄe
eaꢂh wꢄcte to the AD7933/AD7934 ꢁeleꢂtꢁ the next ꢂhannel foꢄ ꢂonveꢄꢁcon.
0
1
1
1
0
1
Not uꢁeꢃ.
Not uꢁeꢃ.
Uꢁe thcꢁ ꢂonfcguꢄatcon cn ꢂonjunꢂtcon wcth ADD1 anꢃ ADD0, the ꢂhannel aꢃꢃꢄeꢁꢁ bctꢁ, to pꢄogꢄam ꢂontcnuouꢁ ꢂonveꢄꢁconꢁ
on a ꢂonꢁeꢂutcve ꢁequenꢂe of ꢂhannelꢁ. The ꢁequenꢂe of ꢂhannelꢁ extenꢃꢁ fꢄom Channel 0 thꢄough to a ꢁeleꢂteꢃ fcnal
ꢂhannel aꢁ ꢃeteꢄmcneꢃ by the ꢂhannel aꢃꢃꢄeꢁꢁ bctꢁ cn the ꢂontꢄol ꢄegcꢁteꢄ. When cn ꢃcffeꢄentcal oꢄ pꢁeuꢃo ꢃcffeꢄentcal moꢃe,
cnveꢄꢁe ꢂhannelꢁ (foꢄ example, VIN1, VIN0) aꢄe not ꢂonveꢄteꢃ.
Rev. B | Page 16 of 32
AD7933/AD7934
CIRCUIT INFORMATION
The AD7933/AD7934 are fast, 4-channel, 10-bit and 12-bit,
single-supply, successive approximation analog-to-digital
converters. The parts operate from a 2.7 V to 5.25 V power
supply and feature throughput rates up to 1.5 MSPS.
When the ADC starts a conversion (see Figure 15), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the VIN+ and the VIN− pins must match;
otherwise, the two inputs have different settling times, resulting
in errors.
The AD7933/AD7934 provide the user with an on-chip
track-and-hold, an internal accurate reference, an analog-to-
digital converter, and a parallel interface housed in a 28-lead
TSSOP package.
The AD7933/AD7934 have four analog input channels that
can be configured to be four single-ended inputs, two fully
differential pairs, or two pseudo differential pairs. There is
an on-chip channel sequencer that allows the user to select a
consecutive sequence of channels through which the ADC can
CAPACITIVE
DAC
COMPARATOR
CONVST
cycle with each falling edge of
.
C
B
A
S
V
V
IN+
SW1
CONTROL
LOGIC
The analog input range for the AD7933/AD7934 is 0 V to VREF
or 0 V to 2 × VREF, depending on the status of the RANGE bit in
the control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
SW3
SW2
A
B
IN–
C
S
V
REF
CAPACITIVE
DAC
Figure 15. ADC Conversion Phase
The AD7933/AD7934 provide flexible power management
options to allow users to achieve the best power performance
for a given throughput rate. These options are selected by
programming PM1 and PM0, the power management bits, in
the control register.
ADC TRANSFER FUNCTION
The output coding for the AD7933/AD7934 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code transitions
occur at successive LSB values (1 LSB, 2 LSBs, and so on), and
the LSB size is VREF/1024 for the AD7933 and VREF/4096 for the
AD7934. The ideal transfer characteristics of the AD7933/AD7934
for both straight binary and twos complement output coding are
shown in Figure 16 and Figure 17, respectively.
CONVERTER OPERATION
The AD7933/AD7934 are successive approximation ADCs
based around two capacitive digital-to-analog converters (DACs).
Figure 14 and Figure 15 show simplified schematics of the ADC
in acquisition and conversion phase, respectively. The ADC
comprises control logic, a SAR, and two capacitive DACs. Both
figures show the operation of the ADC in differential/pseudo
differential modes. Single-ended mode operation is similar but
111...111
111...110
VIN− is internally tied to AGND. In acquisition phase, SW3 is
closed, SW1 and SW2 are in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
111...000
011...111
1 LSB = V
1 LSB = V
/4096 (AD7934)
/1024 (AD7933)
REF
REF
CAPACITIVE
DAC
000...010
000...001
000...000
COMPARATOR
C
B
A
S
V
V
IN+
SW1
SW2
1 LSB
+V
– 1 LSB
REF
CONTROL
LOGIC
0V
SW3
ANALOG INPUT
A
B
IN–
C
NOTES
1. V
S
V
REF
IS EITHER V
REF
OR 2 × V .
REF
REF
CAPACITIVE
DAC
Figure 16. AD7933/AD7934 Ideal Transfer Characteristic
with Straight Binary Output Coding
Figure 14. ADC Acquisition Phase
Rev. B | Page 17 of 32
AD7933/AD7934
1 LSB = 2 × V
1 LSB = 2 × V
/4096 (AD7934)
/1024 (AD7933)
REF
REF
ANALOG INPUT STRUCTURE
011...111
011...110
Figure 19 shows the equivalent circuit of the analog input
structure of the AD7933/AD7934 in differential/pseudo
differential modes. In single-ended mode, VIN− is internally
tied to AGND. The four diodes provide ESD protection for the
analog inputs. Ensure that the analog input signals never exceed
the supply rails by more than 300 mV; doing so causes these
diodes to become forward-biased and start conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
000...001
000...000
111...111
100...010
100...001
100...000
–V
+ 1 LSB
V
+V – 1 LSB
REF
REF
REF
The C1 capacitors in Figure 19 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 45 pF.
Figure 17. AD7933/AD7934 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 18 shows a typical connection diagram for the
AD7933/AD7934. The AGND and DGND pins are connected
together at the device for good noise suppression. If the internal
reference is used, the VREFIN/VREFOUT pin is decoupled to AGND
with a 0.47 μF capacitor to avoid noise pickup. Alternatively,
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
drive the analog input from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp is a function of the particular
application.
VREFIN/VREFOUT can be connected to an external reference source.
In this case, decouple the reference pin with a 0.1 μF capacitor.
In both cases, the analog input range can either be 0 V to VREF
(RANGE bit = 0) or 0 V to 2 × VREF (RANGE bit = 1). The
analog input configuration can be either four single-ended
inputs, two differential pairs, or two pseudo differential pairs
(see Table 10). The VDD pin is connected to either a 3 V or 5 V
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface. As shown in Figure 18, it is
connected to the same 3 V supply of the microprocessor to
allow a 3 V logic interface (see the Digital Inputs section).
V
DD
D
R1
C2
V
IN+
D
C1
3V/5V
SUPPLY
V
DD
+
+
10µF
0.1µF
D
D
R1
C2
V
IN–
V
V
DD
AD7933/AD7934
C1
W/B
0
CLKIN
CS
IN
0 TO V
0 TO 2 × V
/
REF
REF
Figure 19. Equivalent Analog Input Circuit,
Conversion Phase: Switches Open, Track Phase: Switches Closed
RD
V
3
IN
WR
BUSY
CONVST
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 20 and Figure 21 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V in single-ended mode and fully
differential mode, respectively.
DB0
AGND
DGND
DB11/DB9
V
/V
REFIN REFOUT
V
DRIVE
+
+
0.1µF
10µF
3V
SUPPLY
2.5V
V
REF
+
0.1µF EXTERNAL V
REF
0.47µF INTERNAL V
REF
Figure 18. Typical Connection Diagram
Rev. B | Page 18 of 32
AD7933/AD7934
–40
F
= 50kHz
ANALOG INPUTS
IN
–45
–50
–55
–60
–65
–70
–75
–80
The AD7933/AD7934 have software selectable analog input
configurations. Users can choose from among the following
configurations: four single-ended inputs, two fully differential
pairs, or two pseudo differential pairs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 10).
V
= 3V
DD
Single-Ended Mode
V
= 5V
DD
The AD7933/AD7934 can have four single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An amplifier suitable for this function is
the AD8021. The analog input range of the AD7933/AD7934
–85
–90
10
100
1k
R
(Ω)
SOURCE
Figure 20. THD vs. Source Impedance in Single-Ended Mode
–60
can be programmed to be either 0 V to VREF, or 0 V to 2 × VREF
.
F
= 50kHz
IN
–65
–70
–75
–80
–85
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
Figure 23 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude ±1.25 V being preconditioned before it is
applied to the AD7933/AD7934. In cases where the analog
input amplitude is ±2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7933/AD7934 is a signal ranging from 0 V to 5 V. In this
case, the 2 × VREF mode can be used.
V
= 3V
DD
–90
–95
V
= 5V
DD
–100
10
100
1k
R
(Ω)
SOURCE
Figure 21. THD vs. Source Impedance in Fully Differential Mode
+2.5V
R
+1.25V
0V
R
Figure 22 shows a graph of the THD vs. the analog input fre-
quency for various supplies, while sampling at 1.5 MHz with an
SCLK of 25.5 MHz. In this case, the source impedance is 10 Ω.
0V
–1.25V
V
IN
V
0
IN
IN
3R
AD7933/
AD7934*
R
–50
V
3
V
REFOUT
V
= 3V
DD
SINGLE-ENDED MODE
–60
–70
0.47µF
V
= 5V
DD
SINGLE-ENDED MODE
–80
–90
*ADDITIONAL PINS OMITTED FOR CLARITY.
V
= 5V/3V
Figure 23. Single-Ended Mode Connection Diagram
DD
DIFFERENTIAL MODE
Differential Mode
–100
The AD7933/AD7934 can have two differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
–110
–120
F
= 1.5MSPS
SAMPLE
RANGE = 0 TO V
REF
0
100
200
300
400
500
600
700
INPUT FREQUENCY (kHz)
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 24 defines the fully differential analog
input of the AD7933/AD7934.
Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages
Rev. B | Page 19 of 32
AD7933/AD7934
4.5
4.0
T
= 25°C
A
V
REF
p-p
V
V
IN+
AD7933/
AD7934*
3.5
3.0
V
REF
p-p
IN–
COMMON-MODE
VOLTAGE
2.5
2.0
1.5
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 24. Differential Input Definition
1.0
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in each
differential pair (that is, VIN+ − VIN−). VIN+ and VIN− should be
simultaneously driven by two signals, each of amplitude
0.5
0
0.1
0.6
1.1
1.6
2.1
2.6
V
(V)
REF
V
REF (or 2 × VREF depending on the range chosen) that are
Figure 26. Input Common-Mode Range vs. VREF
(2 × VREF Range, VDD = 5 V)
180° out of phase. The amplitude of the differential signal is,
therefore, −VREF to +VREF peak-to-peak (that is, 2 × VREF). This is
regardless of the common mode (CM). The common mode is
the average of the two signals (that is (VIN+ + VIN−)/2) and is,
therefore, the voltage on which the two inputs are centered.
This results in the span of each input being CM ± VREF/2. This
voltage has to be set up externally and its range varies with the
reference value, VREF. As the value of VREF increases, the
common-mode range decreases. When driving the inputs with
an amplifier, the actual common-mode range is determined by
the output voltage swing of the amplifier.
Driving Differential Inputs
Differential operation requires that VIN+ and VIN− be simultane-
ously driven with two equal signals that are 180° out of phase.
The common mode must be set up externally and has a range
that is determined by VREF, the power supply, and the particular
amplifier used to drive the analog inputs. Differential modes of
operation with either an ac or dc input provide the best THD
performance over a wide frequency range. Since not all applica-
tions have a signal preconditioned for differential operation,
there is often a need to perform single-ended-to-differential
conversion.
Figure 25 and Figure 26 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 V
to VREF range or 2 × VREF range, respectively. The common
mode must be in this range to guarantee the functionality of the
AD7933/AD7934.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7933/AD7934.
The circuit configurations shown in Figure 27 and Figure 28
show how a dual op amp converts a single-ended signal into a
differential signal for both a bipolar and unipolar input signal,
respectively.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 1024 for the
AD7933, and 0 to 4096 for the AD7934. If the 2 × VREF range is
used, the input signal amplitude extends from −2 VREF to
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that can be used in this configuration to
provide differential drive to the AD7933/AD7934.
+2 VREF
.
3.5
T
= 25°C
A
3.0
2.5
2.0
1.5
1.0
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 27 and Figure 28 are optimized for
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 27 is configured to
convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
0.5
0
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
V
REF
Figure 25. Input Common-Mode Range vs. VREF
(0 V to VREF Range, VDD = 5 V)
The circuit in Figure 28 converts a unipolar, single-ended signal
into a differential signal.
Rev. B | Page 20 of 32
AD7933/AD7934
220Ω
V
p-p
REF
2 × V
REF
p-p
V
IN+
V+
440Ω
3.75V
GND
27Ω
AD7933/
AD7934*
2.5V
1.25V
V
V–
IN–
V
IN+
V
220Ω
220Ω
220Ω
REF
AD7933/
AD7934
DC INPUT
VOLTAGE
+
0.47µF
V
V+
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
*ADDITIONAL PINS OMITTED FOR CLARITY.
A
V–
Figure 29. Pseudo Differential Mode Connection Diagram
0.47µF
+
10kΩ
20kΩ
ANALOG INPUT SELECTION
As shown in Table 10, users can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are two different ways of selecting the analog
input to be converted depending on the state of the SEQ0 and
SEQ1 bits in the control register.
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Unipolar Differential Signal
220Ω
V
p-p
REF
V
V+
REF
440Ω
3.75V
27Ω
Traditional Multichannel Operation (SEQ0 = SEQ1 = 0)
2.5V
GND
1.25V
Any one of four analog input channels or two pairs of channels
can be selected for conversion in any order by setting the SEQ0
and SEQ1 bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD1 and
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is that of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 30 shows a flowchart of this
mode of operation. The channel configurations are shown in
Table 10.
V–
V
V
IN+
220Ω
220Ω
AD7933/
AD7934
V+
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
A
V–
0.47µF
10kΩ
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar
Signal into a Differential Signal
POWER ON
Another method of driving the AD7933/AD7934 is to use the
AD8138 differential amplifier. The AD8138 can be used as a
single-ended-to-differential amplifier, or differential-to-differential
amplifier. The device is as easy to use as an op amp and greatly
simplifies differential signal amplification and driving.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED
CHANNEL TO CONVERT ON (ADD1 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
Pseudo Differential Mode
The AD7933/AD7934 can have two pseudo differential pairs by
setting the MODE0 and MODE1 bits in the control register to 1
and 0, respectively. VIN+ is connected to the signal source and
must have an amplitude of VREF (or 2 × VREF depending on the
range chosen) to make use of the full dynamic range of the part.
A dc input is applied to the VIN− pin. The voltage applied to this
input provides an offset from ground or a pseudo ground for
the VIN+ input. The benefit of pseudo differential inputs is that
they separate the analog input signal ground from the ADC
ground, allowing the cancellation of dc common-mode
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED ON BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0.
Figure 30. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Consecutive Sequence
(SEQ0 = 1, SEQ1 = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD1 and ADD0 bits in the control register. This
is done by setting the SEQ0 and SEQ1 bits in the control
register both to 1. Once the control register is written to, the
next conversion is on Channel 0, then Channel 1, and so on
until the channel selected by the Address Bit ADD1 and Address
Bit ADD0 is reached. The ADC then returns to Channel 0 and
voltages. Typically, this range can extend to −0.3 V to +0.7 V
when VDD = 3 V, or −0.3 V to +1.8 V when VDD = 5 V. Figure 29
shows a connection diagram for pseudo differential mode.
Rev. B | Page 21 of 32
AD7933/AD7934
WR
The performance of the part with different reference values is
shown in Figure 9 to Figure 11. The value of the reference sets
the analog input span and the common-mode voltage range.
Errors in the reference source result in gain errors in the
AD7933/AD7934 transfer function and add to the specified
full-scale errors on the part.
starts the sequence again. The
input must be kept high to
ensure that the control register is not accidentally overwritten
and the sequence interrupted. This pattern continues until the
AD7933/AD7934 is written to. Figure 31 shows the flowchart of
the consecutive sequence mode.
POWER ON
Table 12 lists suitable voltage references available from Analog
Devices that can be used. Figure 33 shows a typical connection
diagram for an external reference.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD1 AND ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ0 = 1 SEQ1 = 1.
Table 12. Examples of Suitable Voltage References
Output
Initial Accuracy
Operating
Current (μA)
CONTINUOUSLY CONVERT ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD1 AND ADD0
WITH EACH CONVST PULSE.
Reference Voltage (V) (ꢀ maximum)
AD780
ADR421
ADR420
2.5/3
2.5
2.048
0.04
0.04
0.05
1000
500
500
Figure 31. Consecutive Sequence Mode Flow Chart
REFERENCE
The AD7933/AD7934 can operate with either the on-chip
reference or an external reference. The internal reference is
selected by setting the REF bit in the internal control register to 1.
A block diagram of the internal reference circuitry is shown in
Figure 32. The internal reference circuitry includes an on-chip
2.5 V band gap reference and a reference buffer. When using the
internal reference, decouple the VREFIN/VREFOUT pin to AGND with a
0.47 μF capacitor. This internal reference not only provides the
reference for the analog-to-digital conversion, but it can also be
used externally in the system. It is recommended that the
reference output is buffered using an external precision op amp
before applying it anywhere in the system.
AD7933/
AD7934*
AD780
O/P SELECT
V
NC
1
2
3
4
8
7
6
5
NC
NC
REF
V
+V
DD
IN
2.5V
TEMP
V
OUT
0.1µF
10nF
0.1µF
0.1µF
GND
TRIM
NC
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. Typical VREF Connection Diagram
Digital Inputs
The digital inputs applied to the AD7933/AD7934 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the VDD + 0.3 V limit that is on the analog inputs.
BUFFER
REFERENCE
V
/
REFIN
V
REFOUT
Another advantage of the digital inputs not being restricted by
the VDD + 0.3 V limit is the fact that power supply sequencing
AD7933/
AD7934
ADC
issues are avoided. If any of these inputs are applied before VDD
,
Figure 32. Internal Reference Circuit Block Diagram
there is no risk of latch-up as there would be on the analog inputs
Alternatively, an external reference can be applied to the
VREFIN/VREFOUT pin of the AD7933/AD7934. An external
reference input is selected by setting the REF bit in the internal
control register to 0. The external reference input range is 0.1 V
to VDD. It is important to ensure that, when choosing the
reference value, the maximum analog input range (VIN MAX) is
never greater than VDD + 0.3 V to comply with the maximum
ratings of the device. For example, if operating in differential
mode and the reference is sourced from VDD, the 0 V to 2 × VREF
range cannot be used. This is because the analog input signal
range now extends to 2 × VDD, which exceeds the maximum
rating conditions. In the pseudo differential modes, the user
must ensure that VREF + VIN− ≤ VDD when using the 0 V to VREF
if a signal greater than 0.3 V was applied prior to VDD
.
VDRIVE Input
The AD7933/AD7934 have a VDRIVE feature. VDRIVE controls the
voltage at which the parallel interface operates. VDRIVE allows the
ADC to easily interface to 3 V and 5 V processors.
For example, if the AD7933/AD7934 are operated with a VDD
of 5 V, and the VDRIVE pin is powered from a 3 V supply, the
AD7933/AD7934 have better dynamic performance with a
VDD of 5 V while still being able to interface to 3 V processors.
Ensure that VDRIVE does not exceed VDD by more than 0.3 V (see
the Absolute Maximum Ratings section).
range, or when using the 2 × VREF range that 2 × VREF + VIN− ≤ VDD
.
In all cases, the specified reference is 2.5 V.
Rev. B | Page 22 of 32
AD7933/AD7934
At the end of the conversion, BUSY goes low and can be used to
PARALLEL INTERFACE
CS
RD
activate an interrupt service routine. The
and
lines are
The AD7933/AD7934 have a flexible, high speed, parallel
interface. This interface is 10 bits (AD7933) or 12 bits (AD7934)
then activated in parallel to read the 10 bits or 12 bits of
conversion data. When power supplies are first applied to the
B
wide and is capable of operating in either word (W/ tied high)
CONVST
CONVST
device, a rising edge on
and-hold into track. The acquisition time of 125 ns minimum
CONVST
is necessary to put the track-
B
or byte (W/ tied low) mode. The
signal is used to
initiate conversions and, when operating in autoshutdown or
autostandby mode, it is used to initiate power-up.
must be allowed before
is brought low to initiate a
conversion. The ADC then goes into hold on the falling edge of
th
CONVST
A falling edge on the
conversions, and it also puts the ADC track-and-hold into
CONVST
signal is used to initiate
CONVST
and back into track on the 13 rising edge of CLKIN
after this (see Figure 34). When operating the device in
autoshutdown or autostandby mode, where the ADC powers
down at the end of each conversion, a rising edge on the
track. Once the
signal goes low, the BUSY signal goes
high for the duration of the conversion. In between conversions,
CONVST
must be brought high for a minimum time of t1. This
CONVST
signal is used to power up the device.
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
B
t1
A
CONVST
tCONVERT
1
2
3
4
5
12
13
14
t2
CLKIN
BUSY
t20
t3
t9
INTERNAL
TRACK/HOLD
tACQUISITION
CS
RD
t10
t11
t12
t13
t14
THREE-STATE
tQUIET
DB0 TO DB11
DATA
THREE-STATE
WITH CS AND RD TIED LOW
OLD DATA
DB0 TO DB11
DATA
B
Figure 34. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/ = 1)
Rev. B | Page 23 of 32
AD7933/AD7934
Reading Data from the AD7933/AD7934
CS
RD
The
triggered active low. In either word mode or byte mode,
RD
and
signals are gated internally and the level is
CS
and
can be tied together as the timing specifications for t10 and
11 are 0 ns minimum. This means the bus is constantly driven
B
With the W/ pin tied logic high, the AD7933/AD7934
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word on
Pin DB0 to Pin DB11 (12-bit word) and Pin DB2 to DB11
(10-bit word). The DB8/HBEN pin assumes its DB8 function.
t
by the AD7933/AD7934.
CS
The data is placed onto the data bus a time t13 after both
go low. The
the device. After a time, t14, the data lines become three-stated.
and
B
With the W/ pin tied to logic low, the AD7933/AD7934
RD
RD
rising edge can be used to latch data out of
interface operates in byte mode. In this case, the DB8/HBEN
pin assumes its HBEN function.
CS RD
can be tied permanently low, and the
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Alternatively,
and
Conversion data from the AD7933/AD7934 must be accessed in
two read operations with eight bits of data provided on DB0 to
DB7 for each of the read operations. The HBEN pin determines
whether the read operation accesses the high byte or the low
byte of the 12- or 10-bit word. For a low byte read, DB0 to DB7
provide the eight LSBs of the 12-bit word. For 10-bit operation,
the two LSBs of the low byte are 0s and are followed by six bits
of conversion data. For a high byte read, DB0 to DB3 provide the
four MSBs of the 12-/10-bit word. DB4 and DB5 of the high byte
provide the Channel ID. DB6 and DB7 are always 0.
RD
Note that if
causes a degradation in linearity performance of approximately
CS
is pulsed during the conversion time, this
0.25 LSB. Reading during conversion, by way of tying
and
RD
low, does not cause any degradation.
Figure 34 shows the read cycle timing diagram for a 12- or
10-bit transfer. When operating in word mode, the HBEN input
does not exist and only the first read operation is required to
access data from the device. When operating in byte mode, the
two read cycles shown in Figure 35 are required to access the
full data-word from the device.
HBEN/DB8
t15
t16
t15
t16
CS
t10
t11
t17
t12
RD
t13
t14
DB0 TO DB7
LOW BYTE
HIGH BYTE
B
Figure 35. AD7933/AD7934 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. B | Page 24 of 32
AD7933/AD7934
Writing Data to the AD7933/AD7934
Figure 36 shows the write cycle timing diagram of the
AD7933/AD7934 in word mode. When operating in word
mode, the HBEN input does not exist and only one write
operation is required to write the word of data to the device.
Provide data on DB0 to DB11. When operating in byte mode,
the two write cycles shown in Figure 37 are required to write the
full data-word to the AD7933/AD7934. In Figure 37, the first
write transfers the lower eight bits of the data-word from DB0
to DB7, and the second write transfers the upper four bits of the
data-word.
B
With W/ tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7933/AD7934. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7933/AD7934 should be
provided on the DB0 to DB11 inputs, with DB0 being the LSB
B
of the data-word. With W/ tied logic low, the AD7933/AD7934
requires two write operations to transfer a full 12-bit word.
DB8/HBEN assumes its HBEN function. Data written to the
AD7933/AD7934 should be provided on the DB0 to DB7
inputs. HBEN determines whether the byte written is high byte
or low byte data. The low byte of the data-word has DB0 being
the LSB of the full data-word. For the high byte write, HBEN
should be high and the data on the DB0 input should be Data
Bit 8 of the 12-bit word.
When writing to the AD7933/AD7934, the top four bits in the
high byte must be 0s.
WR
The data is latched into the device on the rising edge of
.
WR
The data needs to be set up a time, t7, before the
rising
WR
CS
edge and held for a time, t8, after the
WR
rising edge. The
CS
WR
can be tied
and
signals are gated internally.
and
together as the timing specifications for t4 and t5 are 0 ns
CS
RD
have not already been tied
minimum (assuming
together).
and
CS
t4
t5
WR
t6
t8
t7
DATA
DB0 TO DB11
B
Figure 36. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1)
HBEN/DB8
t18
t19
t18
t19
CS
t4
t5
t17
t6
t7
WR
t8
DB0 TO DB7
LOW BYTE
HIGH BYTE
B
Figure 37. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. B | Page 25 of 32
AD7933/AD7934
Autostandby (PM1 = 1; PM0 = 0)
POWER MODES OF OPERATION
In this mode of operation, the AD7933/AD7934 automatically
enter standby mode at the end of each conversion, shown as
Point A in Figure 34. When this mode is entered, all circuitry
on the AD7933/AD7934 is powered down except for the
reference and reference buffer. The track-and-hold goes into
hold at this point and remains in hold as long as the device is in
standby. The part remains in standby until the next rising edge
The AD7933/AD7934 have four different power modes of
operation. These modes are designed to provide flexible power
management options. Different options can be chosen to optimize
the power dissipation/throughput rate ratio for differing applica-
tions. The mode of operation is selected by PM1 and PM0, the
power management bits, in the control register (see Table 9 for
details). When power is first applied to the AD7933/AD7934, an
on-chip, power-on reset circuit ensures the default power-up
condition is normal mode.
CONVST
of
powers up the device. The power-up time required
depends on whether the internal or external reference is used.
With an external reference, the power-up time required is a
minimum of 600 ns, while using the internal reference, the
power-up time required is a minimum of 7 μs. The user should
ensure this power-up time has elapsed before initiating another
Note that, after power-on, track-and-hold is in hold mode, and
CONVST
the first rising edge of
track mode.
places the track-and-hold into
CONVST
conversion as shown in Figure 38. This rising edge of
also places the track-and-hold back into track mode.
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate performance
wherein the user does not have to worry about any power-up
times because the AD7933/AD7934 remain fully powered up at
all times. At power-on reset, this mode is the default setting in
the control register.
Full Shutdown Mode (PM1 = 1; PM0 = 1)
When this mode is entered, all circuitry on the AD7933/AD7934
is powered down upon completion of the write operation, that
WR
is, on the rising edge of
. The track-and-hold enters hold
mode at this point. The part retains the information in the
control register while in shutdown. The AD7933/AD7934
remain in full shutdown mode, with the track-and-hold in hold
mode, until the power management bits (PM1 and PM0) in the
control register are changed. If a write to the control register
occurs while the part is in full shutdown mode, and the power
management bits are changed to PM0 = PM1 = 0 (normal
Autoshutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7933/AD7934 automatically
enter full shutdown at the end of each conversion, shown at
Point A in Figure 34 and Figure 38. In shutdown mode, all
internal circuitry on the device is powered down. The part
retains information in the control register during shutdown.
The track-and-hold also goes into hold at this point and remains in
hold as long as the device is in shutdown. The AD7933/AD7934
WR
mode), the part begins to power up on the
rising edge, and
the track-and-hold returns to track. To ensure the part is fully
powered up before a conversion is initiated, the power-up time
CONVST
remains in shutdown mode until the next rising edge of
(see Point B in Figure 34 and Figure 38). In order to keep the
CONVST
CONVST
of 10 ms minimum should be allowed before the
falling edge; otherwise, invalid data is read.
device in shutdown for as long as possible,
should
idle low between conversions, as shown in Figure 38. On this
rising edge, the part begins to power up and the track-and-hold
returns to track mode. The power-up time required is 10 ms
minimum regardless of whether the user is operating with the
internal or external reference. The user should ensure that the
power-up time has elapsed before initiating a conversion.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
tPOWER-UP
B
A
CONVST
1
14
1
14
CLKIN
BUSY
Figure 38. Autoshutdown/Autostandby Mode
Rev. B | Page 26 of 32
AD7933/AD7934
POWER vs. THROUGHPUT RATE
10
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7933/AD7934 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 39
shows a plot of power vs. throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example, if
the device runs at a throughput rate of 10 kSPS, the overall cycle
time is 100 μs. If the maximum CLKIN frequency of 25.5 MHz
is used, the conversion time accounts for only 0.525 μs of the
overall cycle time while the AD7933/AD7934 remains in
standby mode for the remainder of the cycle.
T
= 25°C
A
9
8
7
6
5
4
3
V
= 5V
DD
V
= 3V
DD
2
1
0
0
200
400
600
800
1000
1200
1400
1600
THROUGHPUT (kSPS)
Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference
Figure 40 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and 3 V.
In both plots, the figures apply when using the internal
reference. If an external reference is used, the power-up time
reduces to 600 ns; therefore, the AD7933/AD7934 remains in
standby for a greater time in every cycle. Additionally, the
current consumption, when converting, should be lower than
the specified maximum of 2.7 mA with VDD = 5 V, or 2.0 mA
with VDD = 3 V, respectively.
MICROPROCESSOR INTERFACING
AD7933/AD7934 to ADSP-21xx Interface
Figure 41 shows the AD7933/AD7934 interfaced to the
ADSP-21xx series of DSPs as a memory-mapped device.
A single wait state may be necessary to interface the AD7933/
AD7934 to the ADSP-21xx, depending on the clock speed of
the DSP. The wait state can be programmed via the data memory
wait state control register of the ADSP-21xx (see the ADSP-21xx
family User’s Manual for details). The following instruction
reads from the AD7933/AD7934:
1.8
T
= 25°C
A
1.6
1.4
1.2
1.0
0.8
0.6
0.4
V
= 5V
DD
MR = DM (ADC)
where ADC is the address of the AD7933/AD7934.
DSP/USER SYSTEM
V
= 3V
DD
CONVST
A0 TO A15
ADDRESS BUS
AD7933/
AD7934*
ADSP-21xx*
DMS
ADDRESS
DECODER
CS
0.2
0
IRQ2
WR
BUSY
WR
0
20
40
60
80
100
120
140
THROUGHPUT (kSPS)
RD
RD
Figure 39. Power vs. Throughput in
Autostandby Mode Using Internal Reference
DB0 TO DB11
D0 TO D23
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 41. Interfacing to the ADSP-21xx
Rev. B | Page 27 of 32
AD7933/AD7934
DSP/USER SYSTEM
CONVST
AD7933/AD7934 to ADSP-21065L Interface
Figure 42 shows a typical interface between the AD7933/AD7934
and the ADSP-21065L SHARC® processor. This interface is an
A0 TO A15
TMS32020/
ADDRESS BUS
AD7933/
AD7934*
TMS320C25/
TMS320C50*
MS
example of one of three DMA handshake modes. The
control line is actually three memory select lines. Internal
MS
X
ADDRESS
EN
IS
CS
DECODER
ADDR25 to 24 are decoded into
3 to 0, these lines are then
READY
DMAR
asserted as chip selects. The
1 (DMA Request 1) is used
TMS320C25
ONLY
MSC
in this setup as the interrupt to signal the end of the conversion.
The rest of the interface is standard handshaking operation.
STRB
WR
RD
R/W
DSP/USER SYSTEM
INT
X
CONVST
BUSY
ADDR TO ADDR
ADDRESS BUS
0
23
DMD0 TO DMD15
DB11 TO DB0
DATA BUS
ADDRESS
LATCH
AD7933/
AD7934*
*ADDITIONAL PINS OMITTED FOR CLARITY.
MS
X
Figure 43. Interfacing to TMS32020/TMS320C25/TMS320C5x
ADDRESS BUS
ADSP-21065L*
ADDRESS
DECODER
AD7933/AD7934 to 80C186 Interface
CS
DMAR
Figure 44 shows the AD7933/AD7934 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent, high speed DMA channels where data transfers
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7933/AD7934 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation, which also resets the interrupt latch. Sufficient
priority must be assigned to the DMA channel to ensure that
the DMA request is serviced before the completion of the next
conversion.
BUSY
RD
1
RD
WR
WR
DB0 TO DB11
D0 TO D31
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 42. Interfacing to the ADSP-21065L
AD7933/AD7934 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7933/AD7934 and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 43. Select the memory-mapped address for the
AD7933/AD7934 to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7933/AD7934 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the
MICROPROCESSOR/
USER SYSTEM
CONVST
AD0 TO AD15
A16 TO A19
ADDRESS/DATA BUS
ADDRESS
LATCH
AD7933/
AD7934*
ALE
ADDRESS BUS
and the
lines when interfacing to the TMS320C25, no
RD
WR
80C186*
DRQ1
ADDRESS
DECODER
wait states are necessary. However, if slower logic is used, data
accesses may be slowed sufficiently when reading from, and
writing to, the part to require the insertion of one wait state.
Extra wait states are necessary when using the TMS320C5x at
their fastest clock speeds (see the TMS320C5x User’s Guide
for details).
CS
Q
R
S
BUSY
RD
RD
WR
WR
DATA BUS
DB0 TO DB11
Data is read from the ADC using the following instruction:
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Interfacing to the 80C186
IN D, ADC
where:
D is the data memory address.
ADC is the AD7933/AD7934 address.
Rev. B | Page 28 of 32
AD7933/AD7934
APPLICATION HINTS
GROUNDING AND LAYOUT
Good decoupling is also important. Decouple all analog
supplies with 10 μF tantalum capacitors in parallel with 0.1 μF
capacitors to GND. To achieve the best performance from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 ꢀF capacitors should have a low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These types of
capacitors provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Design the printed circuit board that houses the AD7933/AD7934
so that the analog and digital sections are separated and con-
fined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Generally, a minimum
etch technique is best for ground planes because it offers
optimum shielding. Join digital and analog ground planes in
only one place, establishing a star ground point connection as
close as possible to the ground pins on the AD7933/AD7934.
Avoid running digital lines under the device because this
couples noise onto the die. However, the analog ground plane
should be allowed to run under the AD7933/AD7934 to avoid
noise coupling. To provide low impedance paths and reduce the
effects of glitches on the power supply line, use as large a trace
as possible on the power supply lines to the AD7933/AD7934.
EVALUATING THE AD7933/AD7934
PERFORMANCE
The recommended layout for the AD7933/AD7934 is outlined
in the evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7933/AD7934
evaluation board, as well as many other Analog Devices evalua-
tion boards ending in the CB designator, to demonstrate and
evaluate the ac and dc performance of the AD7933/AD7934.
Shield fast switching signals, such as clocks, with digital ground
to avoid radiating noise to other sections of the board, and
never run clock signals near the analog inputs. Avoid crossover
of digital and analog signals. To reduce the effects of feedthrough
through the board, run traces on opposite sides of the board at
right angles to each other. A microstrip technique is by far the
best, but it is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes, while signals are placed on the solder side.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7933/AD7934. The
software and documentation are on the CD that ships with the
evaluation board.
Rev. B | Page 29 of 32
AD7933/AD7934
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 45. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7933BRU
AD7933BRU-REEL
AD7933BRU-REEL7
AD7933BRUZ2
AD7933BRUZ-REEL72
AD7934BRU
AD7934BRU-REEL
AD7934BRU-REEL7
AD7934BRUZ2
AD7934BRUZ-REEL72
EVAL-AD7933CB3
EVAL-AD7934CB3
EVAL-CONTROL-BRD24
Temperature Range
Linearity Error (LSB)1
Package Description
Package Option
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
−40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
−40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
–40ꢆC to +85ꢆC
1
1
1
1
1
1
1
1
1
1
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
28-Leaꢃ TSSOP
Evaluatcon Boaꢄꢃ
Evaluatcon Boaꢄꢃ
Contꢄolleꢄ Boaꢄꢃ
RU-28
RU-28
1 Lcneaꢄcty eꢄꢄoꢄ heꢄe ꢄefeꢄꢁ to cntegꢄal lcneaꢄcty eꢄꢄoꢄ.
2 Z = Pb-fꢄee paꢄt.
3 Thcꢁ ꢂan be uꢁeꢃ aꢁ a ꢁtanꢃalone evaluatcon boaꢄꢃ oꢄ cn ꢂonjunꢂtcon wcth the Evaluatcon Boaꢄꢃ Contꢄolleꢄ foꢄ evaluatcon/ꢃemonꢁtꢄatcon puꢄpoꢁeꢁ.
4 The evaluatcon boaꢄꢃ ꢂontꢄolleꢄ cꢁ a ꢂomplete unct that allowꢁ a PC to ꢂontꢄol anꢃ ꢂommuncꢂate wcth all Analog Devcꢂeꢁ evaluatcon boaꢄꢃꢁ enꢃcng cn the letteꢄꢁ CB.
The followcng neeꢃꢁ to be oꢄꢃeꢄeꢃ to obtacn a ꢂomplete evaluatcon kct: the ADC evaluatcon boaꢄꢃ (foꢄ example, EVAL-AD7934CB), the EVAL-CONTROL-BRD2, anꢃ a
12 V aꢂ tꢄanꢁfoꢄmeꢄ. See the ꢄelevant evaluatcon boaꢄꢃ ꢃata ꢁheet foꢄ moꢄe ꢃetaclꢁ.
Rev. B | Page 30 of 32
AD7933/AD7934
NOTES
Rev. B | Page 31 of 32
AD7933/AD7934
NOTES
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03713-0-2/07(B)
Rev. B | Page 32 of 32
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