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EVAL-CONTROLBRD2 [ADI]

4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer; 4通道， 1.5 MSPS ，具有序12位和10位并行ADC
EVAL-CONTROLBRD2
型号： EVAL-CONTROLBRD2
厂家： ADI    ADI
描述：

4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
4通道， 1.5 MSPS ，具有序12位和10位并行ADC
文件： 总32页 (文件大小：1158K)
中文：  中文翻译
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4-Channel, 1.5 MSPS, 12-Bit and 10-Bit  
Parallel ADCs with a Sequencer  
Preliminary Technical Data  
AD7933/AD7934  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
V
AGND  
DD  
Fast throughput rate: 1.5 MSPS  
Specified for VDD of 2.7 V to 5.25 V  
Low power  
AD7933/AD7934  
V
REFIN/  
V
REFOUT  
2.5V  
8 mW max at 1.5 MSPS with 3 V supplies  
16 mW max at 1.5 MSPS with 5 V supplies  
4 analog input channels with a sequencer  
Software configurable analog inputs  
4-channel single-ended inputs  
2-channel fully differential inputs  
2-channel pseudo-differential inputs  
Accurate on-chip 2.5 V reference  
Wide input bandwidth  
VREF  
V
V
0
IN  
IN  
CLKIN  
12-/10-BIT  
SAR ADC  
AND  
I/P  
CONVST  
T/H  
MUX  
CONTROL  
BUSY  
3
SEQUENCER  
V
PARALLEL INTERFACE/CONTROL REGISTER  
DRIVE  
70 dB SNR at 50 kHz input frequency  
No pipeline delays  
High speed parallel interface—word/byte modes  
Full shutdown mode: 1 µA max  
28 lead TSSOP package  
DB0 DB11  
CS RD WR W/B  
DGND  
Figure 1.  
GENERAL DESCRIPTION  
These parts use advanced design techniques to achieve very low  
power dissipation at high throughput rates. They also feature  
flexible power management options. An on-chip control register  
allows the user to set up different operating conditions,  
including analog input range and configuration, output coding,  
power management, and channel sequencing.  
The AD7933/AD7934 are 12-bit and 10-bit, high speed, low  
power, successive approximation (SAR) ADCs. The parts  
operate from a single 2.7 V to 5.25 V power supply and feature  
throughput rates to 1.5 MSPS. The parts contain a low noise,  
wide bandwidth, differential track-and-hold amplifier that can  
handle input frequencies up to 20 MHz.  
The AD7933/AD7934 feature 4 analog input channels with a  
channel sequencer to allow a consecutive sequence of channels  
to be converted on. These parts can accept either single-ended,  
fully differential, or pseudo-differential analog inputs.  
PRODUCT HIGHLIGHTS  
1. High throughput with low power consumption.  
2. Four analog inputs with a channel sequencer.  
3. Accurate on-chip 2.5 V reference.  
4. Software configurable analog inputs. Single-ended, pseudo-  
differential, or fully differential analog inputs that are  
software selectable.  
5. Single-supply operation with VDRIVE function. The VDRIVE  
function allows the parallel interface to connect directly to  
The conversion process and data acquisition are controlled  
using standard control inputs, which allows for easy interfacing  
to microprocessors and DSPs. The input signal is sampled on  
the falling edge of  
and the conversion is also initiated  
CONVST  
at this point.  
3 V, or 5 V processor systems independent of VDD  
6. No pipeline delay.  
.
The AD7933/AD7934 has an accurate on-chip 2.5 V reference  
that can be used as the reference source for the analog-to-digital  
conversion. Alternatively, this pin can be overdriven to provide  
an external reference.  
7. Accurate control of the sampling instant via a  
CONVST  
input and once off conversion control.  
Rev. PrG  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
AD7933/AD7934  
Preliminary Technical Data  
TABLE OF CONTENTS  
AD7933—Specifications.................................................................. 3  
Analog Input Structure.............................................................. 19  
Analog Inputs.............................................................................. 20  
Analog Input Selection .............................................................. 22  
Reference Section ....................................................................... 22  
Parallel Interface......................................................................... 24  
Power Modes of Operation....................................................... 27  
Power vs. Throughput Rate....................................................... 28  
Microprocessor Interfacing....................................................... 28  
Application Hints ........................................................................... 30  
Grounding and Layout .............................................................. 30  
Evaluating the AD7933/AD7934 Performance...................... 30  
Outline Dimensions....................................................................... 31  
Ordering Guide .......................................................................... 31  
AD7934—Specifications.................................................................. 5  
Timing Specifications....................................................................... 7  
Absolute Maximum Ratings............................................................ 8  
ESD Caution.................................................................................. 8  
Pin Configuration and Function Descriptions............................. 9  
Terminology .................................................................................... 11  
Typical Performance Characteristics ........................................... 13  
Control Register.......................................................................... 16  
Sequencer Operation ................................................................. 17  
Circuit Information........................................................................ 18  
Converter Operation.................................................................. 18  
ADC Transfer Function............................................................. 18  
Typical Connection Diagram ................................................... 19  
REVISION HISTORY  
8/04—Revision PrG: Preliminary Version  
Rev. PrG | Page 2 of 32  
Preliminary Technical Data  
AD7933—SPECIFICATIONS  
AD7933/AD7934  
VDD = VDRIVE =2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to  
TMAX, unless otherwise noted.  
Table 1.  
Parameter  
B Version1  
Unit  
Test Conditions/Comments  
DYNAMIC PERFORMANCE  
Signal-to-Noise + Distortion (SINAD)2  
Signal-to-Noise Ratio (SNR)2  
Total Harmonic Distortion (THD)2  
Peak Harmonic or Spurious Noise (SFDR)2  
Intermodulation Distortion (IMD)2  
Second-Order Terms  
Third-Order Terms  
Channel-to-Channel Isolation  
Aperture Delay2  
FIN = 50 kHz sine wave  
60  
60  
−73  
−73  
dB min  
dB min  
dB max  
dB max  
fa = 40.1 kHz, fb = 51.5 kHz  
−75  
−75  
−75  
5
50  
20  
dB typ  
dB typ  
dB typ  
ns typ  
ps typ  
MHz typ  
MHz typ  
Aperture Jitter2  
Full Power Bandwidth2, 3  
@ 3 dB  
@ 0.1 dB  
2.5  
DC ACCURACY  
Resolution  
10  
Bits  
Integral Nonlinearity2  
Differential Nonlinearity2  
Total Unadjusted Error  
Single-Ended and Pseudo Differential Input  
Offset Error2  
0.5  
0.5  
TBD  
LSB max  
LSB max  
LSB max  
Guaranteed no missed codes to 10 bits  
Straight binary output coding  
4.5  
0.5  
2
LSB max  
LSB max  
LSB max  
LSB max  
Offset Error Match2  
Gain Error2  
Gain Error Match2  
0.6  
Fully Differential Input  
Positive Gain Error2  
Positive Gain Error Match2  
Zero-Code Error2  
Zero-Code Error Match2  
Negative Gain Error2  
Negative Gain Error Match2  
ANALOG INPUT  
Twos complement output coding offset  
2
0.6  
3
1
2
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
0.6  
Single-Ended Input Range  
Pseudo-Differential Input Range: VIN+  
VIN−  
0 to VREF or 0 to 2 × VREF  
0 to VREF or 2 × VREF  
−0.1 to +0.4  
VCM VREF/2  
V
V
V
V
Depending on RANGE bit setting  
Depending on RANGE bit setting  
Fully Differential Input Range: VIN+ and VIN−  
VCM = common-mode voltage4 = VREF/2  
VIN+ and VIN−  
VCM VREF  
V
VCM = VREF, VIN+ or VIN− must remain within GND/VDD  
DC Leakage Current5  
Input Capacitance  
1
45  
10  
µA max  
pF typ  
pF typ  
When in track  
When in hold  
REFERENCE INPUT/OUTPUT  
VREF Input Voltage6  
2.5  
1
V
1ꢀ specified performance  
0.1ꢀ @ 25ꢁC  
DC Leakage Current5  
VREF Input Impedance  
VREFOUT Output Voltage  
VREFOUTTemperature Coefficient  
VREF Noise  
µA max  
kΩ  
V
ppm/ꢁC typ  
µV typ  
µV typ  
10  
2.5  
15  
10  
130  
0.1 Hz to 10 Hz bandwidth  
0.1 Hz to 1 MHz bandwidth  
Rev. PrG | Page 3 of 32  
 
 
 
AD7933/AD7934  
Preliminary Technical Data  
Parameter  
B Version1  
Unit  
Test Conditions/Comments  
VREF Output Impedance  
VREF Input Capacitance  
10  
15  
25  
Ω typ  
pF typ  
pF typ  
When in track  
When in hold  
LOGIC INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current, IIN  
2.4  
0.8  
1
V min  
V max  
µA max  
pF max  
Typically 10 nA, VIN = 0 V or VDRIVE  
5
Input Capacitance, CIN  
10  
LOGIC OUTPUTS  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Floating-State Leakage Current  
Floating-State Output Capacitance5  
Output Coding  
2.4  
0.4  
10  
V min  
ISOURCE = 200 µA;  
ISINK = 200 µA  
V max  
µA max  
pF max  
10  
Straight (Natural) Binary  
Twos Complement  
CODING bit = 0  
CODING bit = 1  
CONVERSION RATE  
Conversion Time  
Track-and-Hold Acquisition Time  
Throughput Rate  
POWER REQUIREMENTS  
VDD  
t2 + 13 tclk + t20  
135  
1.5  
ns  
ns max  
MSPS max  
Full scale step input  
2.7/5.25  
2.7 /5.25  
V min/max  
V min/max  
VDRIVE  
7
IDD  
Digital I/Ps = 0 V or VDRIVE  
VDD = 2.7 V to 5.25 V, SCLK on or off  
VDD = 4.75 V to 5.25 V  
VDD = 2.7 V to 3.6 V  
FSAMPLE = 250 kSPS  
(Static)  
FSAMPLE = 250 kSPS  
(Static)  
SCLK on or off  
Normal Mode(Static)  
Normal Mode (Operational)  
0.5  
3.2  
2.6  
1.55  
90  
1
mA typ  
mA max  
mA max  
mA typ  
µA max  
mA typ  
µA max  
µA max  
Auto StandBy Mode  
Auto Shutdown Mode  
1
1
Full Shutdown Mode  
Power Dissipation  
Normal Mode (Operational)  
16  
8
450  
270  
5
3
5
3
mW max  
mW max  
µW max  
µW max  
µW max  
µW max  
µW max  
µW max  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
VDD = 3 V  
Auto Standby Mode (Static)  
Auto Shutdown Mode (Static)  
Full Shutdown Mode  
1 Temperature range is as follows: B Versions: −40ꢁC to +85ꢁC.  
2 See Terminology section.  
3 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave >3.5 MHz) within the acquisition time may cause an incorrect conversion result to be  
returned by the converter.  
4 For full common-mode range see  
5 Sample tested during initial release to ensure compliance.  
6 This device is operational with an external reference in the range 0.1 V to 3.5 V differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes.  
7 Measured with a midscale dc input.  
Rev. PrG | Page 4 of 32  
Preliminary Technical Data  
AD7934—SPECIFICATIONS  
AD7933/AD7934  
VDD = VDRIVE = 2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to  
TMAX, unless otherwise noted.  
Table 2.  
Parameter  
B Version1  
Unit  
Test Conditions/Comments  
DYNAMIC PERFORMANCE  
Signal-to-Noise + Distortion (SINAD)2  
Signal-to-Noise Ratio (SNR)2  
Total Harmonic Distortion (THD)2  
Peak Harmonic or Spurious Noise (SFDR)2  
Intermodulation Distortion (IMD)2  
Second-Order Terms  
Third-Order Terms  
Channel-to-Channel Isolation  
Aperture Delay2  
FIN = 50 kHz sine wave  
70  
70  
−75  
−75  
dB min  
dB min  
dB max  
dB max  
−80 dB typ  
−82 dB typ  
fa = 40.1 kHz, fb = 51.5 kHz  
−85  
−85  
−85  
5
50  
20  
dB typ  
dB typ  
dB typ  
ns typ  
ps typ  
MHz typ  
MHz typ  
Aperture Jitter2  
Full Power Bandwidth2, 3  
@ 3 dB  
@ 0.1 dB  
2.5  
DC ACCURACY  
Resolution  
12  
Bits  
Integral Nonlinearity2  
Differential Nonlinearity2  
Total Unadjusted Error  
Single-Ended and Pseudo-Differential Input  
Offset Error2  
1
LSB max  
LSB max  
LSB max  
0.95  
TBD  
Guaranteed no missed codes to 12 bits  
Straight binary output coding  
4.5  
0.5  
2
LSB max  
LSB max  
LSB max  
LSB max  
Offset Error Match2  
Gain Error2  
Gain Error Match2  
0.6  
Fully Differential Input  
Positive Gain Error2  
Positive Gain Error Match2  
Zero-Code Error2  
Zero-Code Error Match2  
Negative Gain Error2  
Negative Gain Error Match2  
ANALOG INPUT  
Twos complement output coding  
2
0.6  
3
1
2
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
0.6  
Single-Ended Input Range  
Pseudo-Differential Input Range: VIN+  
VIN−  
0 to VREF or 0 to 2 × VREF  
0 to VREF or 2 × VREF  
−0.1 to +0.4  
VCM VREF/2  
V
V
V
V
Depending on RANGE bit setting  
Depending on RANGE bit setting  
Fully Differential Input Range: VIN+ and VIN−  
VCM = common-mode voltage4 = VREF/2  
VIN+ and VIN−  
VCM VREF  
V
VCM = VREF, VIN+ or VIN− must remain within GND/VDD  
DC Leakage Current5  
Input Capacitance  
1
45  
10  
µA max  
pF typ  
pF typ  
When in track  
When in hold  
REFERENCE INPUT/OUTPUT  
VREF Input Voltage6  
2.5  
1
V
1ꢀ specified performance  
0.1ꢀ @ 25ꢁC  
DC Leakage Current  
VREF Input Impedance  
VREFOUT Output Voltage  
VREFOUT Temperature Coefficient  
VREF Noise  
µA max  
kΩ typ  
V
ppm/ꢁC typ  
µV typ  
µV typ  
10  
2.5  
15  
10  
130  
0.1 Hz to 10 Hz bandwidth  
0.1 Hz to 1 MHz bandwidth  
Rev. PrG | Page 5 of 32  
 
 
 
AD7933/AD7934  
Preliminary Technical Data  
Parameter  
B Version1  
Unit  
Test Conditions/Comments  
VREF Output Impedance  
VREF Input Capacitance  
10  
15  
25  
Ω typ  
pF typ  
pF typ  
When in track-and-hold  
When in track-and-hold  
LOGIC INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current, IIN  
2.4  
0.8  
1
V min  
V max  
µA max  
pF max  
Typically 10 nA, VIN = 0 V or VDRIVE  
5
Input Capacitance, CIN  
10  
LOGIC OUTPUTS  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Floating-State Leakage Current  
Floating-State Output Capacitance5  
Output Coding  
2.4  
0.4  
10  
V min  
ISOURCE = 200 µA;  
ISINK = 200 µA  
V max  
µA max  
pF max  
10  
CODING bit = 0  
CODING bit = 1  
Straight (Natural) Binary  
Twos Complement  
CONVERSION RATE  
Conversion Time  
Track-and-Hold Acquisition Time  
Throughput Rate  
POWER REQUIREMENTS  
VDD  
t2 + 13 tclk + t20  
135  
1.5  
ns  
ns max  
MSPS max  
Full scale step input  
2.7/5.25  
2.7 /5.25  
V min/max  
V min/max  
VDRIVE  
7
IDD  
Digital I/Ps = 0 V or VDRIVE  
VDD = 2.7 V to 5.25 V, SCLK on or off  
VDD = 4.75 V to 5.25 V  
VDD = 2.7 V to 3.6 V  
FSAMPLE = 250 kSPS  
(Static)  
FSAMPLE = 250 kSPS  
(Static)  
SCLK on or off  
Normal Mode(Static)  
Normal Mode (Operational)  
0.5  
3.2  
2.6  
1.55  
90  
1
mA typ  
mA max  
mA max  
mA typ  
µA max  
mA typ  
µA max  
µA max  
Auto StandBy Mode  
Auto Shutdown Mode  
1
1
Full Shutdown Mode  
Power Dissipation  
Normal Mode (Operational)  
16  
8
450  
270  
5
3
5
3
mW max  
mW max  
µW max  
µW max  
µW max  
µW max  
µW max  
µW max  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
VDD = 3 V  
Auto Standby Mode (Static)  
Auto Shutdown Mode (Static)  
Full Shutdown Mode  
1 Temperature ranges is as follows: B Versions: −40ꢁC to +85ꢁC.  
2 See Terminology section.  
3 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the  
converter.  
4 For full common mode range see  
5 Sample tested during initial release to ensure compliance.  
6 This device is operational with an external reference in the range 0.1 V to 3.5 V in differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes.  
See the Reference Section for more information.  
7 Measured with a midscale dc input.  
Rev. PrG | Page 6 of 32  
Preliminary Technical Data  
TIMING SPECIFICATIONS1  
AD7933/AD7934  
VDD = VDRIVE =2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to  
TMAX, unless otherwise noted.  
Table 3.  
Limit at TMIN, TMAX  
Parameter AD7933 AD7934 Unit  
Description  
kHz  
min  
MHz  
max  
2
fCLKIN  
10  
24  
10  
10  
24  
10  
Minimum time between end of read and start of next conversion, i.e., time from when the  
data bus goes into three-state until the next falling edge of CONVST.  
tQUIET  
ns min  
CONVST Pulse Width.  
t1  
10  
20  
TBD  
0
10  
20  
TBD  
0
ns min  
ns min  
CONVST Falling Edge to CLKIN Falling Edge Setup Time.  
t2  
t3  
ns min CLKIN Falling Edge to BUSY Rising Edge.  
CS to WR Setup Time.  
CS to WR Hold Time.  
WR Pulse Width.  
t4  
ns min  
ns min  
ns min  
ns min  
ns min  
t5  
0
0
t6  
25  
10  
5
25  
10  
5
Data Setup Time before WR.  
Data Hold after WR.  
t7  
t8  
t9  
0.5 tCLKIN 0.5 tCLKIN ns min New Data Valid before Falling Edge of BUSY.  
CS to RD Setup Time.  
t10  
t11  
t12  
0
0
ns min  
ns min  
ns min  
ns max  
ns min  
ns max  
ns min  
ns min  
CS to RD Hold Time.  
0
0
RD Pulse Width.  
55  
50  
5
55  
50  
5
3
Data Access Time after RD.  
Bus Relinquish Time after RD.  
Bus Relinquish Time after RD.  
HBEN to RD Setup Time.  
HBEN to RD Hold Time.  
t13  
4
t14  
40  
15  
5
40  
15  
5
t15  
t16  
t17  
t18  
t19  
t20  
10  
0
10  
0
ns min Minimum Time between Reads/Writes.  
HBEN to WR Setup Time.  
HBEN to WR Hold Time.  
ns min  
ns min  
5
5
TBD  
TBD  
ns min CLKIN Falling Edge to BUSY Rising Edge.  
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of 1.6 V.  
All timing specifications given above are with a 25 pF load capacitance. See Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode  
(W/ = 1), Figure 38, Figure 39, and Figure 40.  
2 Mark/space ratio for CLKIN is 40/60 to 60/40.  
3 The time required for the output to cross TBD.  
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or  
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the  
bus loading.  
Rev. PrG | Page 7 of 32  
 
 
 
 
AD7933/AD7934  
Preliminary Technical Data  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Table 4.  
Parameter  
Rating  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those listed in the operational sections  
of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
VDD to AGND/DGND  
−0.3 V to +7 V  
VDRIVE to AGND/DGND  
Analog Input Voltage to AGND  
Digital Input Voltage to DGND  
VDRIVE to VDD  
Digital Output Voltage to AGND  
VREFIN to AGND  
−0.3 V to VDD +0.3 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to +7 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to VDRIVE + 0.3 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to +0.3 V  
10 mA  
AGND to DGND  
Input Current to Any Pin Except Supplies1  
Operating Temperature Range  
Commercial (B Version)  
Storage Temperature Range  
Junction Temperature  
θJA Thermal Impedance  
θJC Thermal Impedance  
Lead Temperature, Soldering  
Reflow Temperature (10 sec to 30 sec)  
ESD  
−40ꢁC to +85ꢁC  
−65ꢁC to +150ꢁC  
150ꢁC  
97.9ꢁC/W (TSSOP)  
14ꢁC/W (TSSOP)  
255ꢁC  
2 kV  
1 Transient currents of up to 100 mA will not cause SCR latch-up.  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate  
on the human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Rev. PrG | Page 8 of 32  
 
 
 
Preliminary Technical Data  
AD7933/AD7934  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
V
3
DD  
IN  
W/B  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
V
V
V
V
2
1
0
IN  
IN  
IN  
3
4
AD7933/  
AD7934  
5
V
REFIN/ REFOUT  
6
TOP VIEW  
(Not to Scale)  
AGND  
CS  
RD  
7
8
9
WR  
10  
11  
12  
13  
14  
CONVST  
CLKIN  
BUSY  
DB11  
DB10  
V
DRIVE  
DGND  
DB8/HBEN  
DB9  
Figure 2. Pin Configuration  
Table 5. Pin Function Description  
Pin No.  
Mnemonic  
Description  
1
VDD  
Power Supply Input. The VDD range for the AD7933/AD7934 is from 2.7 V to 5.25 V. The supply should be  
decoupled to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.  
2
W/B  
Word/Byte Input. When this input is logic high, word transfer mode is enabled and data is transferred to and  
from the AD7933/AD7934 in 12-/10-bit words on Pins DB0/DB2 to DB11. When this pin is logic low, byte  
transfer mode is enabled. Data and the channel ID is transferred on Pins DB0 to DB7 and Pin DB8/HBEN  
assumes its HBEN functionality.  
3 to 10  
DB0 to DB7  
Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the  
control register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage  
levels for these pins are determined by the VDRIVE input. When reading from the AD7933, the two LSBs (DB0 and  
DB1) are always 0 and the LSB of the conversion result is available on DB2.  
11  
12  
13  
VDRIVE  
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of  
the AD7933/AD7934 will operate. This pin should be decoupled to DGND. The voltage at this pin may be  
different to that at VDD but should never exceed VDD by more than 0.3 V.  
Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. The DGND  
and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a  
transient basis.  
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled  
by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte  
of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of  
the data being written to or read from the AD7933/AD7934 are on DB0 to DB3 When reading from the device,  
DB4 of the high byte is always 0 and DB5 and DB6 will contain the ID of the channel for which the conversion  
result corresponds (see Channel Address Bits in Table 9). When writing to the device, DB4 to DB7 of the high  
byte must be all 0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s and the  
remaining 6 bits, conversion data.  
DGND  
DB8/HBEN  
14 to 16  
17  
DB9 to DB11  
BUSY  
Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the  
control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic  
high/low voltage levels for these pins are determined by the VDRIVE input.  
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the  
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and  
the result is available in the output register, the BUSY output will go low. The track-and-hold returns to track  
mode just prior to the falling edge of BUSY, and the acquisition time for the part begins when BUSY goes low.  
18  
19  
CLKIN  
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the  
AD7933/AD7934 takes 13.5 clock cycles. The frequency of the master clock input therefore determines the  
conversion time and achievable throughput rate.  
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from  
track to hold mode on the falling edge of CONVST and the conversion process is initiated at this point.  
Following power-down, when operating in the auto shutdown or auto standby mode, a rising edge on  
CONVST is used to power up the device.  
CONVST  
Rev. PrG | Page 9 of 32  
 
AD7933/AD7934  
Preliminary Technical Data  
Pin No.  
20  
Mnemonic  
Description  
WR  
RD  
Write Input. Active low logic input used in conjunction with CS to write data to the control register.  
21  
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion  
result is placed on the data bus following the falling edge of RD read while CS is low.  
22  
23  
CS  
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data to  
the control register.  
Analog Ground. This is the ground reference point for all analog circuitry on the AD7933/AD7934. All analog  
input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND  
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient  
basis.  
AGND  
24  
VREFIN/VREFOUT  
Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.  
The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an  
external reference. The input voltage range for the external reference is 0.1 V to 3.5 V for differential mode and  
is 0.1 V to VDD in single-ended and pseudo-differential mode, depending on VDD.  
25 to 28  
VIN0 to VIN3  
Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-and-  
hold. The analog inputs can be programmed to be four single ended inputs, two fully differential pairs or two  
pseudo-differential pairs by setting the MODE bits in the control register appropriately (see Table 9). The  
analog input channel to be converted can either be selected by writing to the address bits (ADD1 and ADD0) in  
the control register prior to the conversion, or the on-chip sequencer can be used. The input range for all input  
channels can either be 0 V to VREF or 0 V to 2 × VREF and the coding can be binary or twos complement,  
depending on the states of the RANGE and CODING bits in the control register. Any unsed input channels  
should be connected to AGND to avoid noise pickup.  
Rev. PrG | Page 10 of 32  
AD7933/AD7934  
TERMINOLOGY  
Preliminary Technical Data  
Integral Nonlinearity  
Negative Gain Error Match  
This is the maximum deviation from a straight line passing  
through the endpoints of the ADC transfer function. The  
endpoints of the transfer function are zero scale, a point 1 LSB  
below the first code transition, and full scale, a point 1 LSB  
above the last code transition.  
This is the difference in negative gain error between any two  
channels.  
Channel-to-Channel Isolation  
It is a measure of the level of crosstalk between channels. It is  
measured by applying a full-scale sine wave signal to the three  
nonselected input channels and applying a 50 kHz signal to the  
selected channel. The channel-to-channel isolation is defined as  
the ratio of the power of the 50 kHz signal on the selected  
channel to the power of the noise signal that appears in the FFT  
of this channel.  
Differential Nonlinearity  
This is the difference between the measured and the ideal 1 LSB  
change between any two adjacent codes in the ADC.  
Offset Error  
This is the deviation of the first code transition (00 . . .000) to  
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB  
Power Supply Rejection Ratio (PSRR)  
It is defined as the ratio of the power in the ADC output at full-  
scale frequency, f, to the power of a 100 mV p-p sine wave  
applied to the ADC VDD supply of frequency fS. The frequency  
of the input varies from 1 kHz to 1 MHz.  
Offset Error Match  
This is the difference in offset error between any two channels.  
Gain Error  
This is the deviation of the last code transition (111 . . .110) to  
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset  
error has been adjusted out.  
PSRR (dB) = 10log(Pf/PfS)  
Pf is the power at frequency f in the ADC output; PfS is the  
power at frequency fS in the ADC output.  
Gain Error Match  
This is the difference in gain error between any two channels.  
Track-and-Hold Acquisition Time  
The track-and-hold amplifier returns into track mode and the  
end of conversion. The track-and-hold acquisition time is the  
time required for the output of the track-and-hold amplifier to  
reach its final value, within 1/2 LSB, after the end of  
conversion.  
Zero-Code Error  
This applies when using the twos complement output coding  
option, in particular to the 2 × VREF input range with −VREF to  
+VREF biased about the VREFIN point. It is the deviation of the  
midscale transition (all 0s to all 1s) from the ideal VIN voltage,  
i.e., VREF  
.
Signal-to-(Noise + Distortion) Ratio (SINAD)  
This is the measured ratio of signal-to-(noise + distortion) at  
the output of the ADC. The signal is the rms amplitude of the  
fundamental. Noise is the sum of all nonfundamental signals up  
to half the sampling frequency (fS/2), excluding dc. The ratio is  
dependent on the number of quantization levels in the  
digitization process; the more levels, the smaller the  
quantization noise. The theoretical signal-to-(noise +  
distortion) ratio for an ideal N-bit converter with a sine wave  
input is given by  
Zero-Code Error Match  
This is the difference in zero-code error between any two  
channels.  
Positive Gain Error  
This applies when using the twos complement output coding  
option, in particular to the 2 × VREF input range with −VREF to  
+VREF biased about the VREFIN point. It is the deviation of the last  
code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,  
+VREF – 1 LSB) after the zero-code error has been adjusted out.  
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB  
Positive Gain Error Match  
This is the difference in positive gain error between any two  
channels.  
Thus, for a 12-bit converter, this is 74 dB, and for a 10-bit  
converter, this is 62 dB.  
Negative Gain Error  
This applies when using the twos complement output coding  
option, in particular to the 2 × VREF input range with −VREF to  
+VREF biased about the VREF point. It is the deviation of the first  
code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e.,  
−VREFIN + 1 LSB) after the zero-code error has been adjusted  
out.  
Rev. PrG | Page 11 of 32  
 
AD7933/AD7934  
Preliminary Technical Data  
Intermodulation Distortion  
Total Harmonic Distortion (THD)  
With inputs consisting of sine waves at two frequencies, fa and  
fb, any active device with nonlinearities will create distortion  
products at sum and difference frequencies of mfa nfb where  
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those  
for which neither m nor n are equal to zero. For example, the  
second-order terms include (fa + fb) and (fa − fb), while the  
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa  
− 2fb).  
THD is the ratio of the rms sum of harmonics to the  
fundamental. For the AD7933/AD7934, it is defined as  
2
V22 +V32 +V42 +V52 +V6  
THD dB = −20log  
( )  
V1  
where V1 is the rms amplitude of the fundamental and V2, V3,  
V4, V5, and V6 are the rms amplitudes of the second through the  
sixth harmonics.  
The AD7933/AD7934 is tested using the CCIF standard where  
two input frequencies near the top end of the input bandwidth  
are used. In this case, the second-order terms are usually  
distanced in frequency from the original sine waves, while the  
third-order terms are usually at a frequency close to the input  
frequencies. As a result, the second- and third-order terms are  
specified separately. The calculation of the intermodulation  
distortion is as per the THD specification where it is the ratio of  
the rms sum of the individual distortion products to the rms  
amplitude of the sum of the fundamentals expressed in dBs.  
Peak Harmonic or Spurious Noise  
Peak harmonic or spurious noise is defined as the ratio of the  
rms value of the next largest component in the ADC output  
spectrum (up to fS/2 and excluding dc) to the rms value of the  
fundamental. Normally, the value of this specification is  
determined by the largest harmonic in the spectrum, but for  
ADCs where the harmonics are buried in the noise floor, it will  
be a noise peak  
Rev. PrG | Page 12 of 32  
Preliminary Technical Data  
AD7933/AD7934  
TYPICAL PERFORMANCE CHARACTERISTICS  
TA = 25°C, unless otherwise noted.  
Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling  
Figure 6. AD7934 FFT @ VDD = 5 V  
Figure 4. Channel-to-Channel Isolation  
Figure 7. AD7934 Typical DNL @ VDD = 5 V  
Figure 5. AD7934 SINAD vs. Analog Input Frequency for Various Supply Voltages  
Figure 8. AD7934 Typical INL @ VDD = 5 V  
Rev. PrG | Page 13 of 32  
 
AD7933/AD7934  
Preliminary Technical Data  
Figure 9. AD7934 Change in INL vs. VREF for VDD = 5 V  
Figure 12. AD7934 Offset vs. VREF  
Figure 10.AD7934 Change in DNL vs. VREF for VDD = 5 V  
Figure 13. AD7934 Histogram of Codes @ VDD = 5 V with the Internal Reference  
Figure 11. AD7934 Change in ENOB vs. VREF for VDD = 5 V  
Figure 14. AD7934 Histogram of Codes @ VDD = 5 V with an External Reference  
Rev. PrG | Page 14 of 32  
Preliminary Technical Data  
AD7933/AD7934  
Figure 15. AD7933 FFT @ VDD = 5 V  
Figure 17. AD7933 Typical INL @ VDD = 5 V  
Figure 16. AD7933 Typical DNL @ VDD = 5 V  
Rev. PrG | Page 15 of 32  
AD7933/AD7934  
Preliminary Technical Data  
CONTROL REGISTER  
The control register on the AD7933/AD7934 is a 12-bit, write-only register. Data is written to this register using the  
and  
pins. The  
WR  
CS  
control register is shown below and the functions of the bits are described in Table 7. At power-up, the default bit settings in the control  
register are all 0s.  
Table 6. Control Register Bits  
MSB  
D11  
PM1  
LSB  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
PM0  
CODING REF  
ZERO  
ADD1  
ADD0  
MODE1  
MODE0  
SEQ1  
SEQ0  
RANGE  
Table 7. Control Register Bit Function Description  
Bit No.  
Mnemonic Description  
Power Management Bits. These two bits are used to select the power mode of operation. The user can choose  
between either normal mode or various power-down modes of operation as shown in Table 8.  
This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight  
(natural) binary. If this bit is set to 1, the output coding is twos complement.  
11, 10  
PM1, PM0  
CODING  
9
This bit selects whether the internal or an external reference is used to perform the conversion. If this bit is Logic 0,  
an external reference should be applied to the VREF pin, and if it is Logic 1, the internal reference is selected (see  
the Reference Section).  
8
REF  
7
ZERO  
This bit is not used so it should always be set to Logic 0.  
These two address bits are used to either select which analog input channel is to be converted in the next  
conversion, if the sequencer is not being used, or to select the final channel in a consecutive sequence when the  
sequencer is being used as described in Table 10. The selected input channel is decoded as shown in Table 9.  
ADD1,  
ADD0  
6, 5  
MODE1,  
MODE0  
The two mode pins select the type of analog input on the four VIN pins. The AD7933/AD7934 have either four  
single-ended inputs, two fully differential inputs, or two pseudo-differential inputs (see Table 9).  
The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the sequencer function (see  
Table 10).  
The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the sequencer function (see  
Table 10).  
4, 3  
2
SEQ1  
SEQ0  
1
This bit selects the analog input range of the AD7933/AD7934. If it is set to 0, the analog input range extends from  
0 V to VREF. If it is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range is selected, AVDD  
must be 4.75 V to 5.25 V.  
0
RANGE  
Table 8. Power Mode Selection using the Power Management Bits in the Control Register  
PM1 PM0 Mode  
Description  
0
0
1
1
0
1
0
1
Normal  
Mode  
Auto  
Shutdown  
Auto  
Standby  
Full  
Shutdown  
When operating in normal mode, all circuitry is fully powered up at all times.  
When operating in auto shutdown mode, the AD7933/AD7934 will enter full shutdown mode at the end of  
each conversion. In this mode, all circuitry is powered down.  
When the AD7933/AD7934 enter this mode, all circuitry is partially powered down. This mode is similar to  
the auto shutdown mode but it allows the part to power up in 1 µs.  
When the AD7933/AD7934 enters this mode, all circuitry is powered down. The information in the control  
register is retained.  
Rev. PrG | Page 16 of 32  
 
 
 
Preliminary Technical Data  
AD7933/AD7934  
Table 9. Analog Input Type Selection  
Channel Address  
MODE0 = 0, MODE1 = 0  
MODE0 = 0, MODE1 = 1  
MODE0 = 1, MODE1 = 0  
MODE0 = 1, MODE1 = 1  
Not Used  
Four Single-Ended I/P  
Channels  
Two Fully Differential  
I/P Channels  
Two Pseudo-Differential  
I/P Channels  
ADD1  
ADD0  
VIN+  
VIN−  
VIN+  
VIN−  
VIN+  
VIN−  
0
0
1
1
0
1
0
1
VIN0  
VIN1  
VIN2  
VIN3  
AGND  
AGND  
AGND  
AGND  
VIN0  
VIN1  
VIN2  
VIN3  
VIN1  
VIN0  
VIN3  
VIN2  
VIN0  
VIN1  
VIN2  
VIN3  
VIN1  
VIN0  
VIN3  
VIN2  
SEQUENCER OPERATION  
The configuration of the SEQ0 and SEQ1 bits in the control register allow the user to use the sequencer function. Table 10 outlines the  
two sequencer modes of operation.  
Table 10. Sequence Selection Modes  
SEQ0 SEQ1 Sequence Type  
This configuration is selected when the sequence function is not used. The analog input channel selected on each  
individual conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each prior write  
operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function  
being used, where each write to the AD7933/AD7934 selects the next channel for conversion.  
0
0
0
1
1
1
0
1
Not Used.  
Not Used.  
This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to program continuous  
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by  
the channel address bits in the control register. When in differential or pseudo-differential mode, inverse channels (e.g.,  
VIN1, VIN0) are not converted in this mode.  
Rev. PrG | Page 17 of 32  
 
 
 
AD7933/AD7934  
Preliminary Technical Data  
CIRCUIT INFORMATION  
The AD7933/AD7934 are fast, 4-channel, 12-bit and10-bit,  
single-supply, successive approximation analog-to-digital  
converters. The parts operate from either a 2.7 V to 3.6 V or  
4.75 V to 5.25 V power supply and feature throughput rates up  
to 1.5 MSPS.  
When the ADC starts a conversion (Figure 19), SW3 will open  
and SW1 and SW2 will move to Position B, causing the  
comparator to become unbalanced. Both inputs are  
disconnected once the conversion begins. The control logic and  
charge redistribution DACs are used to add and subtract fixed  
amounts of charge from the sampling capacitor arrays to bring  
the comparator back into a balanced condition. When the  
comparator is rebalanced, the conversion is complete. The  
control logic generates the ADC’s output code. The output  
impedances of the sources driving the VIN+ and the VIN− pins  
must be matched; otherwise, the two inputs will have different  
settling times, resulting in errors.  
The AD7933/AD7934 provide the user with an on-chip track-  
and-hold, an internal accurate reference, an analog-to-digital  
converter, and a parallel interface housed in a 28-lead TSSOP  
package.  
The AD7933/AD7934 have four analog input channels that can  
be configured to be four single-ended inputs, two fully  
differential pairs, or two pseudo-differential pairs. There is an  
on-chip channel sequencer that allows the user to select a  
consecutive sequence of channels through which the ADC can  
CAPACITIVE  
DAC  
COMPARATOR  
C
B
A
S
V
V
IN+  
cycle with each falling edge of  
.
CONVST  
SW1  
CONTROL  
LOGIC  
SW3  
SW2  
A
B
The analog input range for the AD7933/AD7934 is 0 to VREF or  
0 to 2 × VREF, depending on the status of the RANGE bit in the  
control register. The output coding of the ADC can be either  
binary or twos complement, depending on the status of the  
CODING bit in the control register.  
IN–  
C
S
V
REF  
CAPACITIVE  
DAC  
Figure 19. ADC Conversion Phase  
The AD7933/AD7934 provide flexible power management  
options to allow users to achieve the best power performance  
for a given throughput rate. These options are selected by  
programming the power management bits, PM1 and PM0, in  
the control register.  
ADC TRANSFER FUNCTION  
The output coding for the AD7933/AD7934 is either straight  
binary or twos complement, depending on the status of the  
CODING bit in the control register. The designed code  
transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs,  
and so on) and the LSB size is VREF/1024 for the AD7933 and  
VREF/4096 for the AD7934. The ideal transfer characteristics of  
the AD7933/AD7934 for both straight binary and twos  
complement output coding are shown in Figure 20 and Figure 21,  
respectively.  
CONVERTER OPERATION  
The AD7933/AD7934 are a successive approximation ADC  
based on two capacitive DACs. Figure 18 and Figure 19 show  
simplified schematics of the ADC in acquisition and conversion  
phase, respectively. The ADC comprises of control logic, a SAR,  
and two capacitive DACs. Both figures show the operation of  
the ADC in differential/pseudo-differential mode. Single-ended  
mode operation is similar but VIN− is internally tied to AGND.  
In the acquisition phase, SW3 is closed, SW1 and SW2 are in  
Position A, the comparator is held in a balanced condition, and  
the sampling capacitor arrays acquire the differential signal on  
the input.  
111...111  
111...110  
111...000  
011...111  
1 LSB = V  
1 LSB = V  
/4096 (AD7934)  
/1024 (AD7933)  
REF  
REF  
CAPACITIVE  
DAC  
COMPARATOR  
000...010  
000...001  
000...000  
C
B
A
S
V
V
IN+  
SW1  
1 LSB  
+V –1 LSB  
REF  
CONTROL  
LOGIC  
SW3  
0V  
SW2  
ANALOG INPUT  
A
B
IN–  
C
S
NOTE: V  
REF  
IS EITHER V OR 2 × V  
REF REF  
V
REF  
CAPACITIVE  
DAC  
Figure 20. AD7933/AD7934 Ideal Transfer Characteristic  
with Straight Binary Output Coding  
Figure 18. ADC Acquisition Phase  
Rev. PrG | Page 18 of 32  
 
 
 
 
Preliminary Technical Data  
AD7933/AD7934  
ANALOG INPUT STRUCTURE  
1 LSB = 2  
1 LSB = 2  
×
×
V
V
/4096 (AD7934)  
/1024 (AD7933)  
REF  
REF  
Figure 23 shows the equivalent circuit of the analog input  
structure of the AD7933/AD7934 in differential/pseudo-  
differential mode. In single-ended mode, VIN− is internally tied  
to AGND. The four diodes provide ESD protection for the  
analog inputs. Care must be taken to ensure that the analog  
input signals never exceed the supply rails by more than  
300 mV. This causes these diodes to become forward-biased and  
start conducting into the substrate. These diodes can conduct  
up to 10 mA without causing irreversible damage to the part.  
011...111  
011...110  
000...001  
000...000  
111...111  
100...010  
100...001  
100...000  
–V  
+ 1 LSB  
V
+V – 1 LSB  
REFV  
The C1 capacitors, in Figure 23, are typically 4 pF and can  
primarily be attributed to pin capacitance. The resistors are  
lumped components made up of the on resistance of the  
switches. The value of these resistors is typically about 100 Ω.  
The C2 capacitors, in Figure 23, are the ADC’s sampling  
capacitors and have a typical capacitance of 16 pF.  
REF  
REF  
Figure 21. AD7933/AD7934 Ideal Transfer Characteristic  
with Twos Complement Output Coding  
TYPICAL CONNECTION DIAGRAM  
Figure 22 shows a typical connection diagram for the  
AD7933/AD7934. The AGND and DGND pins are connected  
together at the device for good noise suppression. The  
For ac applications, removing high frequency components from  
the analog input signal is recommended by using an RC low-  
pass filter on the relevant analog input pins. In applications  
where harmonic distortion and signal-to-noise ratio are critical,  
the analog input should be driven from a low impedance source.  
Large source impedances significantly affect the ac performance  
of the ADC. This may necessitate the use of an input buffer  
amplifier. The choice of the op amp is a function of the  
particular application.  
V
REFIN/VREFOUT pin is decoupled to AGND with a 0.47 µF  
capacitor to avoid noise pickup, if the internal reference is used.  
Alternatively, VREFIN/VREFOUT can be connected to a external  
reference source, and in this case, the reference pin should be  
decoupled with a 0.1 µF capacitor. In both cases, the analog  
input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to  
2 × VREF (RANGE bit = 1). The analog input configuration is  
either four single-ended inputs, two differential pairs or two  
pseudo-differential pairs (see Table 9). The VDD pin connects to  
either a 3 V or 5 V supply. The voltage applied to the VDRIVE  
input controls the voltage of the digital interface, and here, it is  
connected to the same 3 V supply of the microprocessor to  
allow a 3 V logic interface (see the Digital Inputs section).  
V
DD  
D
R1  
C2  
V
+
IN  
D
C1  
3V/5V  
V
DD  
SUPPLY  
0.1µF  
10µF  
D
D
R1  
C2  
V
–
IN  
V
V
DD  
AD7933/AD7934  
C1  
W/B  
CLKIN  
CS  
RD  
WR  
0
IN  
0 TO V  
/
REF  
Figure 23. Equivalent Analog Input Circuit, Conversion Phase—Switches,  
Open Track Phase—Switches Closed  
0 TO 2 × V  
REF  
V
3
µC/µP  
IN  
BUSY  
CONVST  
When no amplifier is used to drive the analog input, the source  
impedance should be limited to low values. The maximum  
source impedance will depend on the amount of THD that can  
be tolerated. The THD increases as the source impedance  
increases and performance degrades. Figure 24 shows a graph of  
the THD versus the analog input signal frequency for different  
source impedances for both VDD = 5 V and 3 V.  
DB0  
AGND  
DGND  
DB11/DB9  
V
/V  
REFIN REFOUT  
V
DRIVE  
0.1µF  
10µF  
3V  
2.5V  
SUPPLY  
V
REF  
0.1µF EXTERNAL V  
REF  
0.47µF INTERNAL V  
REF  
Figure 22. Typical Connection Diagram  
Rev. PrG | Page 19 of 32  
 
 
 
AD7933/AD7934  
Preliminary Technical Data  
+2.5V  
R
+1.25V  
0V  
–1.25V  
0V  
R
V
IN  
V
V
IN0  
3R  
AD7933/  
AD7934*  
IN3  
V
REFOUT  
0.47µF  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 26. Single-Ended Mode Connection Diagram  
Figure 24. THD vs. Analog Input Frequency for Various Source Impedances  
Differential Mode  
The AD7933/AD7934 can have two differential analog input  
pairs by setting Bits MODE0 and MODE1 in the control  
register to 0 and 1, respectively.  
Figure 25 shows a graph of the THD versus the analog input  
frequency for various supplies, while sampling at 1.5 MHz with  
an SCLK of 20 MHz. In this case, the source impedance is 10 Ω.  
Differential signals have some benefits over single-ended  
signals, including noise immunity based on the device’s  
common-mode rejection and improvements in distortion  
performance. Figure 27 defines the fully differential analog  
input of the AD7933/AD7934.  
V
REF  
V
V
IN+AD7933/  
AD7934*  
p-p  
V
REF  
IN–  
p-p  
COMMON-MODE  
VOLTAGE  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 25. THD vs. Analog Input Frequency for Various Supply Voltages  
Figure 27. Differential Input Definition  
ANALOG INPUTS  
The amplitude of the differential signal is the difference  
between the signals applied to the VIN+ and VIN− pins in each  
differential pair (i.e., VIN+ − VIN−). VIN+ and VIN− should be  
simultaneously driven by two signals, each of amplitude VREF  
that are 180° out of phase. The amplitude of the differential  
signal is therefore −VREF to +VREF peak-to-peak (i.e., 2 × VREF).  
This is regardless of the common mode (CM). The common  
mode is the average of the two signals, i.e. (VIN+ + VIN−)/2, and is  
therefore the voltage that the two inputs are centered on. This  
results in the span of each input being CM VREF/2. This  
The AD7933/AD7934 have software selectable analog input  
configurations. Users can choose either four single-ended  
inputs, two fully differential pairs, or two pseudo-differential  
pairs. The analog input configuration is chosen with Bits  
MODE0/MODE1 in the internal control register (see Table 9).  
Single-Ended Mode  
The AD7933/AD7934 can have four single-ended analog input  
channels by setting the MODE0 and MODE1 bits in the control  
register both to 0. In applications where the signal source has a  
high impedance, it is recommended to buffer the analog input  
before applying it to the ADC. The analog input range is either 0  
voltage has to be set up externally and its range varies with VREF  
.
As the value of VREF increases, the common-mode range  
decreases. When driving the inputs with an amplifier, the actual  
common-mode range is determined by the amplifier’s output  
voltage swing.  
to VREF or 0 to 2 × VREF  
.
If the analog input signal to be sampled is bipolar, the internal  
reference of the ADC can be used to externally bias up this  
signal to make it of the correct format for the ADC.  
Figure 28 and Figure 29 show how the common-mode range  
typically varies with VREF for both a 5 V and a 3 V power supply.  
The common mode must be in this range to guarantee the  
functionality of the AD7933/AD7934.  
Figure 26 shows a typical connection diagram when operating  
the ADC in single-ended mode.  
Rev. PrG | Page 20 of 32  
 
 
 
 
Preliminary Technical Data  
AD7933/AD7934  
When a conversion takes place, the common mode is rejected  
resulting in a virtually noise free signal of amplitude −VREF to  
+VREF corresponding to the digital codes of 0 to 1024 for the  
AD7933 and 0 to 4096 for the AD7934.  
Using an Op Amp Pair  
An op amp pair can be used to directly couple a differential  
signal to one of the analog input pairs of the AD7933/AD7934.  
The circuit configurations shown in Figure 30 and Figure 31  
show how a dual op amp can be used to convert a single-ended  
signal into a differential signal for both a bipolar and unipolar  
input signal, respectively.  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
The voltage applied to Point A sets up the common-mode  
voltage. In both diagrams, it is connected in some way to the  
reference, but any value in the common-mode range can be  
input here to set up the common mode. A suitable dual op amp  
that could be used in this configuration to provide differential  
drive to the AD7933/AD7934 is the AD8022.  
0.5  
0
Take care when choosing the op amp; the selection depends on  
the required power supply and system performance objectives.  
The driver circuits in Figure 30 and Figure 31 are optimized for  
dc coupling applications requiring best distortion performance.  
0
0.5  
1.0  
1.5  
REF  
2.0  
2.5  
3.0  
V
(V)  
Figure 28. Input Common-Mode Range vs.  
VREF (0 to VREF Range, VDD = 5 V)  
The circuit configuration shown in Figure 30 converts a  
unipolar, single-ended signal into a differential signal.  
4.5  
4.0  
The circuit configuration in Figure 31 is configured to convert  
and level shift a single-ended, ground-referenced (bipolar)  
signal to a differential signal centered at the VREF level of the  
ADC.  
3.5  
3.0  
2.5  
2.0  
1.5  
220Ω  
2
×
V
p-p  
REF  
V+  
390Ω  
3.75V  
2.5V  
1.25V  
V
27Ω  
REF  
GND  
V–  
V
V
IN+  
1.0  
220Ω  
220Ω  
V+  
AD7933/  
AD7934  
0.5  
0
IN–  
V
REF  
3.75V  
2.5V  
1.25V  
0.1  
0.6  
1.1  
1.6  
2.1  
2.6  
27Ω  
A
V
(V)  
V–  
REF  
0.47µF  
10kΩ  
Figure 29. Input Common-Mode Range vs.  
VREF (2 × VREF Range, VDD = 5 V)  
20kΩ  
Driving Differential Inputs  
Figure 30. Dual Op Amp Circuit to Convert a  
Single-Ended Unipolar Signal into a Differential Signal  
Differential operation requires that VIN+ and VIN− be  
simultaneously driven with two equal signals that are 180° out  
of phase. The common mode must be set up externally and  
have a range that is determined by VREF, the power supply, and  
the particular amplifier used to drive the analog inputs.  
Differential modes of operation with either an ac or dc input  
provide the best THD performance over a wide frequency  
range. Since not all applications have a signal preconditioned for  
differential operation, there is often a need to perform single-  
ended-to-differential conversion.  
220Ω  
2
×
V
p-p  
REF  
V+  
390Ω  
220Ω  
3.75V  
2.5V  
1.25V  
GND  
27Ω  
V–  
V
V
IN+  
220Ω  
220Ω  
V+  
AD7933/  
AD7934  
IN–  
V
REF  
3.75V  
2.5V  
1.25V  
27Ω  
A
V–  
0.47µF  
10kΩ  
20kΩ  
Figure 31. Dual Op Amp Circuit to Convert a  
Single-Ended Bipolar Signal into a Differential Signal  
Rev. PrG | Page 21 of 32  
 
 
AD7933/AD7934  
Preliminary Technical Data  
Pseudo-Differential Mode  
POWER ON  
The AD7933/AD7934 can have two pseudo-differential pairs by  
setting Bits MODE0 and MODE1 in the control register to 1, 0,  
respectively. VIN+ is connected to the signal source that must  
have an amplitude of VREF to make use of the full dynamic range  
of the part. ADC input is applied to the VIN− pin. The voltage  
applied to this input provides an offset from ground or a pseudo  
ground for the VIN+ input. The benefit of pseudo-differential  
inputs is that they separate the analog input signal ground from  
the ADC’s ground allowing dc common-mode voltages to be  
cancelled. Figure 32 shows a connection diagram for the  
pseudo-differential mode.  
WRITE TO THE CONTROL REGISTER TO  
SET UP OPERATING MODE, ANALOG INPUT  
AND OUTPUT CONFIGURATION  
SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED  
CHANNEL TO CONVERT ON (ADD1 TO ADD0).  
ISSUE CONVST PULSE TO INITIATE A CONVERSION  
ON THE SELECTED CHANNEL.  
INITIATE A READ CYCLE TO READ THE DATA  
FROM THE SELECTED CHANNEL.  
INITIATE A WRITE CYCLE TO SELECT THE NEXT  
CHANNEL TO BE CONVERTED ON BY  
CHANGING THE VALUES OF BITS ADD2 TO ADD0  
IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0.  
Figure 33. Normal Multichannel Operation Flow Chart  
V
p-p  
REF  
Using the Sequencer: Consecutive Sequence (SEQ0 = 1,  
SEQ1 = 1)  
V
IN+  
AD7933/  
AD7934*  
A sequence of consecutive channels can be converted beginning  
with Channel 0 and ending with a final channel selected by  
writing to Bits ADD1 and ADD0 in the control register. This is  
done by setting the SEQ0 and SEQ1 bits in the control register  
both to 1. Once the control register is written to set this mode  
up, the next conversion is on Channel 0, then Channel 1, and so  
on until the channel selected by the address bits, ADD1 and  
ADD0, is reached. The ADC then returns to Channel 0 and  
V
IN–  
V
REF  
DC INPUT  
VOLTAGE  
RANGE  
0.47µF  
±100mV  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 32. Pseudo-Differential Mode Connection Diagram  
starts the sequence again. The  
input must be kept high to  
WR  
ANALOG INPUT SELECTION  
ensure that the control register is not accidentally overwritten  
and the sequence interrupted. This pattern continues until such  
time as the AD7933/AD7934 is written to. Figure 34 shows the  
flow chart of the consecutive sequence mode.  
As shown in Table 9, users can set up their analog input  
configuration by setting the values in Bits MODE0 and MODE1  
in the control register. Assuming the configuration is chosen,  
there are two different ways of selecting the analog input to be  
converted depending on the state of the SEQ0 and SEQ1 bits in  
the control register.  
POWER ON  
WRITE TO THE CONTROL REGISTER TO  
SET UP OPERATING MODE, ANALOG INPUT  
AND OUTPUT CONFIGURATION SELECT  
FINAL CHANNEL (ADD1 AND ADD0) IN  
CONSECUTIVE SEQUENCE.  
Normal Multichannel Operation (SEQ0 = SEQ1 = 0)  
Any one of four analog input channels or two pairs of channels  
may be selected for conversion in any order by setting the SEQ0  
and SEQ1 bits in the control register both to 0. The channel to  
be converted is selected by writing to Bits ADD1 and ADD0 in  
the control register to program the multiplexer prior to the  
conversion. This mode of operation is of a normal multichannel  
ADC where each data write selects the next channel for  
conversion. Figure 33 shows a flow chart of this mode of  
operation. The channel configurations are shown in Table 9.  
SET SEQ0 = 1 SEQ1 = 1.  
CONTINUOUSLY CONVERT ON A CONSECUTIVE  
SEQUENCE OF CHANNELS FROM CHANNEL 0  
UP TO AND INCLUDING THE PREVIOUSLY  
SELECTED FINAL CHANNEL ON ADD1 AND ADD0  
WITH EACH CONVST PULSE.  
Figure 34. Consecutive Sequence Mode Flow Chart  
REFERENCE SECTION  
The AD7933/AD7934 can operate with either the on-chip  
reference or an external reference. The internal reference is  
selected by setting the REF bit in the internal control register to 1.  
A block diagram of the internal reference circuitry is shown in  
Figure 35. The internal reference circuitry includes an on-chip  
2.5 V band gap reference and a reference buffer. When using the  
internal reference, the VREFIN/VREFOUT pin should be decoupled to  
AGND with a 0.47 µF capacitor. This internal reference not only  
provides the reference for the analog-to-digital conversion, but it  
also is used externally in the system. It is recommended that the  
reference output is buffered using an external precision op amp  
before applying it anywhere in the system.  
Rev. PrG | Page 22 of 32  
 
 
 
 
Preliminary Technical Data  
AD7933/AD7934  
BUFFER  
Example 2  
REFERENCE  
V
/
REFIN  
V
REFOUT  
V
V
IN MAX = VDD + 0.3  
IN MAX = VREF + VREF/2  
AD7933/  
AD7934  
ADC  
If VDD = 3.6 V, then VIN MAX = 3.9 V.  
Therefore, 3 × VREF/2 = 3.6 V.  
Figure 35. Internal Reference Circuit Block Diagram  
Alternatively, an external reference can be applied to the  
VREFIN/VREFOUT pin of the AD7933/AD7934. An external  
reference input is selected by setting the REF bit in the internal  
control register to 0. When using an external reference, the  
V
REF MAX = 2.6 V  
Therefore, when operating with at VDD = 3 V, the value of VREF  
can range from 100 mV to a maximum value of 2.4 V. When  
VDD = 2.7 V, VREF MAX = 2 V.  
V
REFIN/VREFOUT pin should be decoupled to AGND with a 0.1 µF  
capacitor. When operating in differential mode, the external  
reference input range is 0.1 V to 3.5V, and in single-ended and  
pseudo-differential mode, the external reference input range is  
0.1 V to VDD. In all cases, the specified reference is 2.5 V.  
These examples show that the maximum reference applied to  
the AD7933/AD7934 is directly dependant on the value applied  
to VDD.  
It is important to ensure that, when choosing the reference  
value, the maximum analog input range (VIN MAX) is never  
greater than VDD + 0.3 V to comply with the maximum ratings  
of the device. In pseudo differential mode, the user must ensure  
that VREFIN − VIN− ≤ VDD.  
The performance of the part at different reference values is  
shown in Figures TBD to TBD. The value of the reference sets  
the analog input span and the common-mode voltage range.  
Errors in the reference source result in gain errors in the  
AD7933/AD7934 transfer function and add to the specified  
full-scale errors on the part. Table 11 lists suitable voltage  
references available from ADI that could be used, and Figure 36  
shows a typical connection diagram for an external reference.  
The following two examples calculate the maximum VREF input  
that can be used when operating the AD7933/AD7934 in  
differential mode with a VDD of 5 V and 3 V, respectively.  
Table 11. Examples of Suitable Voltage References  
Example 1  
Output  
Initial Accuracy Operating  
Reference Voltage  
(% max)  
Current (µA)  
V
V
IN MAX = VDD + 0.3  
AD780  
ADR421  
ADR420  
2.5/3  
2.5  
0.04  
0.04  
0.05  
1000  
500  
500  
IN MAX = VREF + VREF/2  
2.048  
If VDD = 5 V, then VIN MAX = 5.3 V.  
Therefore, 3 × VREF/2 = 5.3 V.  
AD7933/  
AD7934*  
AD780  
V
NC  
1
2
3
4
O/PSELECT  
8
7
6
5
NC  
NC  
V
REF MAX = 3.5 V  
REF  
V
+V  
IN  
DD  
2.5V  
Therefore, when operating at VDD = 5 V, the value of VREF can  
range from 100 mV to a maximum value of 3.5 V. When VDD  
4.75 V, VREF MAX = 3.17 V.  
TEMP  
GND  
V
OUT  
TRIM  
0.1µF  
10nF  
0.1µF  
0.1µF  
=
NC  
NC = NO CONNECT  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 36. Typical VREF Connection Program  
Rev. PrG | Page 23 of 32  
 
 
AD7933/AD7934  
Preliminary Technical Data  
Digital Inputs  
PARALLEL INTERFACE  
The digital inputs applied to the AD7933/AD7934 are not  
limited by the maximum ratings that limit the analog inputs.  
Instead, the digital inputs applied can go to 7 V and are not  
restricted by the AVDD + 0.3 V limit that is on the analog inputs.  
The AD7933/AD7934 have a flexible, high speed, parallel  
interface. This interface is 12-bits (AD7934) or 10-bits  
(AD7933) wide and is capable of operating in either word (W/  
B
tied high) or byte (W/ tied low) mode. The  
signal is  
CONVST  
B
used to initiate conversions, and when operating in auto  
shutdown or auto standby mode, it is used to power up the  
ADC.  
Another advantage of the digital inputs not being restricted by  
the AVDD + 0.3 V limit is the fact that power supply sequencing  
issues are avoided. If any of these inputs are applied before AVDD,  
then there is no risk of latch-up as there would be on the analog  
inputs if a signal greater than 0.3 V was applied prior to AVDD.  
A falling edge on the  
signal is used to initiate  
CONVST  
conversions, and it also puts the ADC track-and-hold into track.  
Once the signal goes low, the BUSY signal goes high  
VDRIVE Input  
CONVST  
for the duration of the conversion. In between conversions,  
The AD7933/AD7934 has a VDRIVE feature. VDRIVE controls the  
voltage at which the parallel interface operates. VDRIVE allows the  
ADC to easily interface to 1.8 V, 3 V, and 5 V processors. VDRIVE  
of 1.8 V can only be used if VDD = 2.7 V to 3.6 V.  
must be brought high for a minimum time of t1. This  
CONVST  
must happen after the 14th rising edge of CLKIN; otherwise, the  
conversion will be aborted and the track-and-hold will go back  
into track. At the end of the conversion, BUSY goes low and can  
For example, if the AD7933/AD7934 operated with an AVDD of  
5 V and the VDRIVE pin could be powered from a 3 V supply, the  
AD7933/AD7934 has better dynamic performance with an  
AVDD of 5 V while still being able to interface to 3 V processors.  
Care should be taken to ensure VDRIVE does not exceed AVDD by  
more than 0.3 V (see Table 4).  
be used to activate an interrupt service routine. The  
and  
CS  
RD  
lines are then activated in parallel to read the 12 bits or 10 bits  
of conversion data. When power supplies are first applied to the  
device, a rising edge on  
puts the track-and-hold into  
CONVST  
track. The acquisition time of 135 ns minimum must be allowed  
before is brought low to initiate a conversion. The  
CONVST  
ADC will then go into hold on the falling edge of  
back into track on the 13th rising edge of CLKIN after this (see  
Figure 37). When operating the device in auto shutdown or auto  
standby mode, where the ADC powers down at the end of each  
and  
CONVST  
conversion, a rising edge on the  
signal is used to  
CONVST  
power up the device.  
B
t1  
A
CONVST  
tCONVERT  
1
2
3
4
5
12  
13  
14  
t2  
CLKIN  
BUSY  
t20  
t3  
t9  
INTERNAL  
tAQUISITION  
TRACK/HOLD  
CS  
RD  
t10  
t11  
t14  
t12  
t13  
THREE-STATE  
DB0 TO DB11  
DATA  
THREE-STATE  
tQUIET  
WITH CS AND RD TIED LOW  
OLD DATA  
DB0 TO DB11  
DATA  
B
Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode (W/ = 1)  
Rev. PrG | Page 24 of 32  
 
 
AD7933/AD7934  
Preliminary Technical Data  
Reading Data from the AD7933/AD7934  
transfer. When operated in word mode, the HBEN input does  
not exist and only the first read operation is required to access  
data from the device. When operated in byte mode, the two read  
cycles shown in Figure 38 are required to access the full data-  
word from the device.  
With the W/ pin tied logic high, the AD7933/AD7934  
B
interface operates in word mode. In this case, a single read  
operation from the device accesses the conversion data-word on  
Pins DB0/DB2 to DB11. The DB8/HBEN pin assumes its DB8  
function. With the W/ pin tied to logic low, the  
B
The  
and  
signals are gated internally and level triggered  
RD  
CS  
AD7933/AD7934 interface operates in byte mode. In this case,  
the DB8/HBEN pin assumes its HBEN function. Conversion  
data from the AD7933/ AD7934 must be accessed in two read  
operations with 8 bits of data provided on DB0 to DB7 for each  
of the read operations. The HBEN pin determines whether the  
read operation accesses the high byte or the low byte of the12-  
or 10-bit word. For a low byte read, DB0 to DB7 provide the  
eight LSBs of the 12-bit word. For 10-bit operation, the two  
LSBs of the low byte are 0s and are followed by 6 bits of  
conversion data. For a high byte read, DB0 to DB3 provide the  
4 MSBs of the 12-/10-bit word. DB4 of the high byte is always 0  
and DB5 and DB6 of the high byte provide the Channel ID.  
Figure 37 shows the read cycle timing diagram for a 12-/10-bit  
active low. In either word mode or byte mode,  
be tied together as the timing specification t10 and t11 is 0 ns  
minimum. The data is placed onto the data bus a time t13 after  
and  
may  
RD  
CS  
both  
and  
go low. The  
rising edge can be used to latch  
CS  
RD  
RD  
data out of the device. After a time, t14, the data lines will  
become three-stated.  
Alternatively,  
and  
can be tied permanently low and the  
RD  
CS  
conversion data will be valid and placed onto the data bus a  
time, t9, before the falling edge of BUSY.  
HBEN/DB8  
t15  
t16  
t15  
t16  
CS  
t10  
t11  
t17  
t12  
RD  
t13  
t14  
DB0 TO DB7  
LOW BYTE  
HIGH BYTE  
B
Figure 38. AD7933/AD7934 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ = 0)  
Rev. PrG | Page 25 of 32  
 
AD7933/AD7934  
Preliminary Technical Data  
Writing Data to the AD7933/AD7934  
to write the word of data to the device. Data should be provided  
on DB0 to DB11. When operated in byte mode, the two write  
cycles shown in Figure 40 are required to write the full data-  
word to the AD7933/AD7934. In Figure 40, the first write  
transfers the lower 8 bits of the data-word from DB0 to DB7  
and the second write transfers the upper 4 bits of the data-word.  
With W/ tied logic high, a single write operation transfers the  
B
full data-word on DB0 to DB11 to the control register on the  
AD7933/AD7934. The DB8/HBEN pin assumes its DB8  
function. Data written to the AD7933/AD7934 should be  
provided on the DB0 to DB11 inputs with DB0 being the LSB of  
the data-word. With W/ tied logic low, the AD7933/AD7934  
B
When writing to the AD7933/AD7934, the top 4 bits in the high  
byte must be 0s.  
requires two write operations to transfer a full 12-bit word.  
DB8/HBEN assumes its HBEN function. Data written to the  
AD7933/AD7934 should be provided on the DB0 to DB7  
inputs. HBEN determines whether the byte written is high byte  
or low byte data. The low byte of the data-word has DB0 being  
the LSB of the full data-word. For the high byte write, HBEN  
should be high and the data on the DB0 input should be data bit  
8 of the 12 bit word.  
The data is latched into the device on the rising edge of  
.
WR  
The data needs to be setup a time, t7, before the  
rising edge  
WR  
and held for a time, t8, after the  
rising edge. The  
and  
WR  
WR  
and  
CS  
may be tied together as  
WR  
signals are gated internally.  
CS  
the timing specification for t4 and t5 is 0 ns minimum (assuming  
and  
have not already been tied together).  
CS  
RD  
Figure 39 shows the write cycle timing diagram of the  
AD7933/AD7934. When operated in word mode, the HBEN  
input does not exist and only the one write operation is required  
CS  
t4  
t5  
WR  
t6  
t8  
t7  
DATA  
DB0 TO DB11  
B
Figure 39. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1)  
HBEN/DB8  
t18  
t19  
t18  
t19  
CS  
t4  
t5  
t17  
t6  
WR  
t7  
LOW BYTE  
t8  
DB0 TO DB7  
HIGH BYTE  
B
Figure 40. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0)  
Rev. PrG | Page 26 of 32  
 
 
Preliminary Technical Data  
AD7933/AD7934  
internal reference, the power-up time is typically TBD, and with  
an external reference, the power-up time is typically TBD. The  
user should ensure that the power-up time has elapsed before  
initiating a conversion.  
POWER MODES OF OPERATION  
The AD7933/AD7934 have four different power modes of  
operation. These modes are designed to provide flexible power  
management options. Different options can be chosen to  
optimize the power dissipation/throughput rate ratio for  
differing applications. The mode of operation is selected by the  
power management bits, PM1 and PM0, in the control register,  
as detailed in Table 8. When power is first applied to the  
AD7933/AD7934 an on-chip, power-on reset circuit ensures the  
default power-up condition is normal mode.  
Auto Standby (PM1 = 1; PM0 = 0)  
In this mode of operation, the AD7933/AD7934 automatically  
enter standby mode at the end of each conversion. When this  
mode is entered, all circuitry on the AD7933/AD7934 is  
powered down except for the reference and reference buffer.  
Also, track-and-hold goes into hold at this point and remains in  
hold as long as the device is in standby The part remains in  
Note that, after power-on, track-and-hold is in hold mode and  
standby until the next rising edge of  
powers up the  
CONVST  
the first rising edge of  
places the track-and-hold into  
CONVST  
device, which takes at least TBD. The user should ensure this  
power-up time has elapsed before initiating another conversion,  
as shown in Figure 41. This rising edge of CONVST also places  
track-and-hold back into track mode.  
track mode.  
Normal Mode (PM1 = PM0 = 0)  
This mode is intended for the fastest throughput rate  
performance because the user does not have to worry about any  
power-up times because the AD7933/AD7934 remain fully  
powered up at all times. At power-on reset, this mode is the  
default setting in the control register.  
Full Shutdown Mode (PM1 = 1; PM0 = 1)  
When this mode is entered, all circuitry on the  
AD7933/AD7934 is powered down upon completion of the  
write operation, i.e., on rising edge of  
. The part retains the  
WR  
Auto Shutdown (PM1 = 0; PM0 = 1)  
information in the control register while the part is in  
shutdown. The AD7933/AD7934 remain in full shutdown  
mode, and track-and-hold in hold mode, until the power  
management bits (PM1 and PM0) in the control register are  
changed. If a write to the control register occurs while the part  
is in full shutdown mode, and the power management bits are  
changed to PM0 = PM1 = 0, i.e., normal mode, the part begins  
In this mode of operation, the AD7933/AD7934 automatically  
enter full shutdown at the end of each conversion, which is  
shown at Point A in Figure 37. In shutdown mode, all internal  
circuitry on the device is powered. The part retains information  
in the control register during shutdown. It remains in shutdown  
mode until the next rising edge of  
(see Point B in  
CONVST  
Figure 37). In order to keep the device in shutdown for as long  
as possible, should idle low between conversions as  
to power up on the  
rising edge and the track and hold  
WR  
returns to track.. To ensure the part is fully powered up before a  
conversion is initiated, the power-up time, TBD, should be  
CONVST  
shown in Figure 41. On this rising edge, the part begins to  
power-up and track-and-hold returns to track mode. The  
power-up time required depends on whether the user is  
operating with the internal or external reference. With the  
allowed before the  
falling edge; otherwise, invalid  
CONVST  
data is read.  
tPOWER-UP  
B
A
CONVST  
1
14  
1
14  
CLKIN  
BUSY  
Figure 41. Auto-Shutdown/Auto-Standby Mode  
Rev. PrG | Page 27 of 32  
 
 
AD7933/AD7934  
Preliminary Technical Data  
OPTIONAL  
POWER VS. THROUGHPUT RATE  
A big advantage of powering the ADC down after a conversion  
is that the power consumption of the part is significantly  
reduced at lower throughput rates. When using the different  
power modes, the AD7933/AD7934 is only powered up for the  
duration of the conversion. Therefore, the average power  
consumption per cycle is significantly reduced. Figure 42 and  
Figure 43 show plots of the power versus the throughput when  
operating in auto shutdown and auto standby modes.  
CONVST  
A0 TO A15  
ADDRESS BUS  
AD7933/  
ADSP-21xx*  
DMS  
AD7934*  
ADDRESS  
CS  
DECODER  
IRQ2  
WR  
BUSY  
WR  
RD  
RD  
DB0 TO DB11  
D0 TO D23  
DATA BUS  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 44. Interfacing to the ADSP-21xx  
AD7933/AD7934 to ADSP-21065L Interface  
Figure 45 shows a typical interface between the  
AD7933/AD7934 and the ADSP-21065L SHARC processor.  
This interface is an example of one of three DMA handshake  
modes. The  
control line is actually three memory select  
MSx  
lines. Internal ADDR25–24 are decoded into  
, these lines are  
MS3-0  
then asserted as chip selects. The  
(DMA request 1) is  
DMAR1  
used in this setup as the interrupt to signal the end of the  
conversion. The rest of the interface is standard handshaking  
operation.  
Figure 42. Power vs. Throughput in Auto Shutdown Mode  
OPTIONAL  
CONVST  
ADDR TO ADDR  
23  
ADDRESS BUS  
0
ADDRESS  
LATCH  
AD7933/  
AD7934*  
MS  
X
ADDRESS BUS  
ADDRESS  
DECODER  
ADSP-21065L*  
DMAR  
CS  
BUSY  
RD  
1
RD  
WR  
WR  
DB0 TO DB11  
Figure 43. Power vs. Throughput in Auto Standby Mode  
D0 TO D31  
DATA BUS  
MICROPROCESSOR INTERFACING  
AD7933/AD7934 to ADSP-21xx Interface  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 45. Interfacing to the ADSP-21065L  
Figure 44 shows the AD7933/AD7934 interfaced to the ADSP-  
21xx series of DSPs as a memory mapped device. A single wait  
state may be necessary to interface the AD7933/AD7934 to the  
ADSP-21xx, depending on the clock speed of the DSP. The wait  
state can be programmed via the data memory wait state  
control register of the ADSP-21xx (see the ADSP-21xx family  
User’s Manual for details). The following instruction reads from  
the AD7933/AD7934:  
MR = DM (ADC)  
where ADC is the address of the AD7933/AD7934.  
Rev. PrG | Page 28 of 32  
 
 
 
 
 
Preliminary Technical Data  
AD7933/AD7934  
AD7933/AD7934 to TMS32020, TMS320C25, and  
TMS320C5x Interface  
AD7933/AD7934 to 80C186 Interface  
Figure 47 shows the AD7933/AD7934 interfaced to the 80C186  
microprocessor. The 80C186 DMA controller provides two  
independent high speed DMA channels where data transfer can  
occur between memory and I/O spaces. Each data transfer  
consumes two bus cycles, one cycle to fetch data and the other  
to store data. After the AD7933/AD7934 has finished a  
conversion, the BUSY line generates a DMA request to  
Channel 1 (DRQ1). As a result of the interrupt, the processor  
performs a DMA READ operation which also resets the  
interrupt latch. Sufficient priority must be assigned to the DMA  
channel to ensure that the DMA request will be serviced before  
the completion of the next conversion.  
Parallel interfaces between the AD7933/AD7934 and the  
TMS32020, TMS320C25 and TMS320C5x family of DSPs are  
shown in Figure 46. The memory mapped address chosen for  
the AD7933/AD7934 should be chosen to fall in the I/O  
memory space of the DSPs. The parallel interface on the  
AD7933/AD7934 is fast enough to interface to the TMS32020  
with no extra wait states. If high speed glue logic, such as 74AS  
devices, are used to drive the  
and the  
lines when  
RD  
WR  
interfacing to the TMS320C25, then again, no wait states are  
necessary. However, if slower logic is used, data accesses may be  
slowed sufficiently when reading from and writing to the part to  
require the insertion of one wait state. Extra wait states will be  
necessary when using the TMS320C5x at their fastest clock  
speeds (see the TMS320C5x User’s Guide for details).  
OPTIONAL  
CONVST  
AD0 TO AD15  
A16 TO A19  
ADDRESS/DATA BUS  
Data is read from the ADC using the following instruction:  
IN D, ADC  
ADDRESS  
LATCH  
AD7933/  
AD7934*  
ALE  
ADDRESS BUS  
ADDRESS  
DECODER  
80C186*  
DRQ1  
CS  
where D is the data memory address, and ADC is the  
AD7933/AD7934 address.  
Q
R
S
OPTIONAL  
BUSY  
RD  
RD  
CONVST  
A0 TO A15  
WR  
WR  
DB0 TO DB11  
ADDRESS BUS  
ADDRESS  
TMS32020/  
DATA BUS  
AD7933/  
AD7934*  
TMS320C25/  
TMS320C50*  
*ADDITIONAL PINS OMITTED FOR CLARITY  
IS  
EN  
CS  
DECODER  
Figure 47. Interfacing to the 80C186  
READY  
TMS320C25  
ONLY  
MSC  
STRB  
WR  
RD  
R/W  
INT  
X
BUSY  
DMD0 TO DMD15  
DB11 TO DB0  
DATA BUS  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 46. Interfacing to the TMS32020/C25/C5x  
Rev. PrG | Page 29 of 32  
 
 
AD7933/AD7934  
Preliminary Technical Data  
APPLICATION HINTS  
GROUNDING AND LAYOUT  
to ground planes, while signals are placed on the solder side.  
The printed circuit board that houses the AD7933/AD7934  
should be designed so that the analog and digital sections are  
separated and confined to certain areas of the board. This  
facilitates the use of ground planes that can be easily separated.  
A minimum etch technique is generally best for ground planes  
as it gives the best shielding. Digital and analog ground planes  
should be joined in only one place, and the connection should  
be a star ground point established as close to the ground pins on  
the AD7933/AD7934 as possible. Avoid running digital lines  
under the device as this couples noise onto the die. The analog  
ground plane should be allowed to run under the  
Good decoupling is also important. All analog supplies should  
be decoupled with 10 µF tantalum capacitors in parallel with  
0.1 µF capacitors to GND. To achieve the best from these  
decoupling components, they must be placed as close as  
possible to the device.  
EVALUATING THE AD7933/AD7934  
PERFORMANCE  
The recommended layout for the AD7933/AD7934 is outlined  
in the evaluation board documentation. The evaluation board  
package includes a fully assembled and tested evaluation board,  
documentation, and software for controlling the board from the  
PC via the evaluation board controller. The evaluation board  
controller can be used in conjunction with the  
AD7933/AD7934 evaluation board, as well as many other ADI  
evaluation boards ending in the CB designator, to  
demonstrate/evaluate the ac and dc performance of the  
AD7933/AD7934.  
AD7933/AD7934 to avoid noise coupling. The power supply  
lines to the AD7933/AD7934 should use as large a trace as  
possible to provide low impedance paths and reduce the effects  
of glitches on the power supply line.  
Fast switching signals, such as clocks, should be shielded with  
digital ground to avoid radiating noise to other sections of the  
board, and clock signals should never run near the analog  
inputs. Avoid crossover of digital and analog signals. Traces on  
opposite sides of the board should run at right angles to each  
other. This reduces the effects of feedthrough through the  
board. A microstrip technique is by far the best but is not always  
possible with a double-sided board.  
The software allows the user to perform ac (fast Fourier  
transform) and dc (histogram of codes) tests on the  
AD7933/AD7934. The software and documentation are on the  
CD that ships with the evaluation board.  
In this technique, the component side of the board is dedicated  
Rev. PrG | Page 30 of 32  
 
Preliminary Technical Data  
OUTLINE DIMENSIONS  
AD7933/AD7934  
9.80  
9.70  
9.60  
28  
15  
4.50  
4.40  
4.30  
6.40 BSC  
1
14  
PIN 1  
0.65  
BSC  
1.20 MAX  
0.15  
0.05  
8°  
0°  
0.75  
0.60  
0.45  
0.30  
0.19  
0.20  
0.09  
SEATING  
PLANE  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-153AE  
Figure 48. 28-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-28)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model  
Temperature Range Linearity Error (LSB)1 Package Option Package Descriptions  
AD7934BRU  
AD7933BRU  
EVAL-AD7934CB2  
EVAL-AD7933CB3  
EVAL-CONTROL BRD24  
−40ꢁC to +85ꢁC  
−40ꢁC to +85ꢁC  
1
1
RU-28  
RU-28  
Thin Shrink Small Outline Package (TSSOP)  
Thin Shrink Small Outline Package (TSSOP)  
Evaluation Board  
Evaluation Board  
Controller Board  
1 Linearity error here refers to integral linearity error.  
2 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.  
3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.  
4 Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB  
designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (EVAL-AD7934CB), the EVAL-CONTROL BRD2, and a 12 V  
ac transformer. See the EVAL-AD7933/34CB evaluation board technical note for more details.  
Rev. PrG | Page 31 of 32  
 
 
 
 
 
AD7933/AD7934  
NOTES  
Preliminary Technical Data  
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
PR03713-0-8/04(PrG)  
Rev. PrG | Page 32 of 32  

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