FDVE0630-1R0M [ADI]
20 V, 6 A Synchronous Step-Down; 20 V ， 6的同步降压型
| 型号： | FDVE0630-1R0M |
| 厂家： | 
ADI |
| 描述： | 20 V, 6 A Synchronous Step-Down |
| 文件： | 总28页 (文件大小：827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20 V, 6 A Synchronous Step-Down
Regulator with Low-Side Driver
Data Sheet
ADP2381
FEATURES
TYPICAL APPLICATIONS CIRCUIT
V
Input voltage: 4.5 V to 20 V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
PVIN
PVIN
BST
L
Integrated 44 mΩ high-side MOSFET
0.6 V 1% reference voltage over temperature
Continuous output current: 6 A
Programmable switching frequency: 250 kHz to 1.4 MHz
Synchronizes to external clock: 250 kHz to 1.4 MHz
180° out-of-phase synchronization
Programmable UVLO
C
V
BST
OUT
C
IN
SW
SW
C
OUT
UVLO ADP2381
PGOOD
FET
LD
C
RT
VREG
PGND
GND
VREG
R
OSC
11
10
9
SYNC
EN/SS
COMP
R
R
TOP
C
SS
FB
Power-good output
BOT
External compensation
C
C_EA
R
C_EA
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
C
CP_EA
Figure 1.
APPLICATIONS
100
95
90
85
80
75
70
65
60
55
50
Communication infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load application
V
V
V
= 3.3V
= 5V
= 1.2V
OUT
OUT
OUT
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
Figure 2. ADP2381 Efficiency vs. Output Current, VIN = 12 V, fSW = 250 kHz
GENERAL DESCRIPTION
The ADP2381 is a current mode control, synchronous, step-
down, dc-to-dc regulator. It integrates a 44 mΩ power MOSFET
and a low-side driver to provide a high efficiency solution. The
ADP2381 runs from an input voltage of 4.5 V to 20 V and can
deliver 6 A of output current. The output voltage can be
adjusted to 0.6 V to 90% of the input voltage. The switching
frequency of the ADP2381 can be programmed from
250 kHz to 1.4 MHz or fixed at 290 kHz or 550 kHz. The
synchronization function allows the switching frequency to be
synchronized to an external clock to minimize system noise.
External compensation and an adjustable soft start provide
design flexibility. The power-good output provides simple and
reliable power sequencing. Additional features include
programmable undervoltage lockout (UVLO), overvoltage
protection (OVP), overcurrent protection (OCP), and thermal
shutdown (TSD).
The ADP2381 operates over the −40°C to +125°C junction
temperature range and is available in a 16-lead TSSOP_EP
package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
ADP2381
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Input Capacitor Selection.......................................................... 15
Output Voltage Setting .............................................................. 15
Voltage Conversion Limitations............................................... 15
Inductor Selection ...................................................................... 15
Output Capacitor Selection....................................................... 17
Low-Side Power Device Selection............................................ 17
Programming Input Voltage UVLO ........................................ 18
Compensation Design ............................................................... 18
ADIsimPower Design Tool ....................................................... 19
Design Example .............................................................................. 20
Output Voltage Setting .............................................................. 20
Frequency Setting....................................................................... 20
Inductor Selection ...................................................................... 20
Output Capacitor Selection....................................................... 20
Low-Side MOSFET Selection ................................................... 21
Compensation Components..................................................... 21
Soft Start Time Program ........................................................... 21
Input Capacitor Selection.......................................................... 21
Schematic for Design Example................................................. 21
External Components Recommendation.................................... 23
Circuit Board Layout Recommendations ................................... 25
Typical Application Circuits ......................................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Information................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Description .............................. 6
Typical Performance Characteristics ............................................. 7
Functional Block Diagram ............................................................ 12
Theory of Operation ...................................................................... 13
Control Scheme .......................................................................... 13
Internal Regulator (VREG)....................................................... 13
Bootstrap Circuitry .................................................................... 13
Low-Side Driver.......................................................................... 13
Oscillator ..................................................................................... 13
Synchronization.......................................................................... 13
Enable and Soft Start.................................................................. 13
Power Good................................................................................. 14
Peak Current Limit and Short-Circuit Protection ................. 14
Overvoltage Protection (OVP) ................................................. 14
Undervoltage Lockout (UVLO)................................................ 14
Thermal Shutdown..................................................................... 14
REVISION HISTORY
3/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADP2381
SPECIFICATIONS
VIN = 12 V, TJ = −40°C to +125°C for min/max specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
VPVIN
IQ
ISHDN
4.5
2
80
20
V
No switching
EN/SS = GND
PVIN rising
2.8
130
4.3
3.9
3.5
170
4.5
mA
µA
V
PVIN falling
3.7
V
FB
FB Regulation Voltage
VFB
IFB
0°C < TJ < 85°C
−40°C < TJ < +125°C
0.594
0.591
0.6
0.6
0.01
0.606
0.609
0.1
V
V
µA
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
gm
ISOURCE
ISINK
360
40
40
500
60
60
620
80
80
µS
µA
µA
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
SW
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
7.6
65
8
350
100
8.4
V
mV
mA
135
High-Side On Resistance1
High-Side Peak Current Limit
Negative Current-Limit Threshold Voltage2
SW Minimum On Time
SW Minimum Off Time
LOW-SIDE DRIVER (LD)
Rising Time2
VBST − VSW = 5 V
44
9.6
20
120
200
70
11.5
mΩ
A
mV
ns
7.7
tMIN_ON
tMIN_OFF
170
300
ns
tR
tF
CDL = 2.2 nF; see Figure 17
CDL = 2.2 nF; see Figure 20
20
10
4
ns
ns
Ω
Falling Time2
Sourcing Resistor
6
Sinking Resistor
2
3.5
Ω
BST
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
VBOOT
fSW
4.5
5
5.7
V
RT pin connected to GND
RT pin open
ROSC = 100 kΩ
210
400
425
250
290
550
500
360
690
570
1400
kHz
kHz
kHz
kHz
Switching Frequency Range
SYNC
fSW
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
EN/SS
Enable Threshold
Internal Soft Start
SS Pin Pull-Up Current
250
100
100
1.3
1400
kHz
ns
ns
V
0.4
0.5
4
V
V
1500
3.3
Clock cycles
µA
ISS_UP
2.6
Rev. 0 | Page 3 of 28
ADP2381
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER GOOD (PGOOD)
PGOOD Range
FB rising threshold
FB falling threshold
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
95
90
1024
16
0.01
125
%
%
PGOOD Deglitch Time
Clock cycles
Clock cycles
µA
PGOOD Leakage Current
PGOOD Output Low Voltage
UVLO
0.1
200
IPGOOD = 1 mA
mV
Rising Threshold
Falling Threshold
1.2
1.1
1.28
V
V
1.02
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
25
°C
°C
1 Pin-to-pin measurement.
2 Guaranteed by design.
Rev. 0 | Page 4 of 28
Data Sheet
ADP2381
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
Table 2.
Parameter
Rating
PVIN, PGOOD
SW
BST
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
THERMAL INFORMATION
Table 3. Thermal Resistance
UVLO, FB, EN/SS, COMP, SYNC, RT
VREG, LD
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Package Type
Unit
θJA
16-lead TSSOP_EP
39.48
°C/W
θJA is specified for the worst-case conditions, that is, a device
soldered in circuit board (4-layer, JEDEC standard board) for
surface-mount packages.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 28
ADP2381
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PVIN
PVIN
BST
SW
UVLO
PGOOD
RT
SW
ADP2381
TOP VIEW
(Not to Scale)
LD
VREG
PGND
GND
FB
SYNC
EN/SS
COMP
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED
TO AN EXTERNAL GROUND PLANE UNDERNEATH
THE IC FOR THERMAL DISSIPATION.
Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2
PVIN
Power Input. Connect to the input power source and connect a bypass capacitor between this pin and
PGND.
3
4
5
UVLO
PGOOD
RT
Undervoltage Lockout Pin. An external resistor divider can be used to set the turn-on threshold.
Power-Good Output (Open Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency
between 250 kHz and 1.4 MHz. If the RT pin is connected to GND, the switching frequency is set to 290
kHz. If the RT pin is open, the switching frequency is set to 550 kHz.
6
7
SYNC
EN/SS
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency
between 250 kHz and 1.4 MHz (see the Oscillator section and the Synchronization section for details).
Enable Pin (EN). When this pin voltage falls below 0.5 V, the regulator is disabled.
Soft Start (SS). This pin can also be used to set the soft start time.
Connect a capacitor from SS to GND to program the slow soft start time. If this pin is open, the regulator
is enabled and uses the internal soft start.
8
9
COMP
FB
Error Amplifier Output. Connect an RC network from COMP to FB.
Feedback Voltage Sense Input. Connect to a resistor divider from VOUT.
10
11
12
13
14, 15
16
17
GND
PGND
VREG
LD
SW
BST
Analog Ground. Connect to the ground plane.
Power Ground. Connect to the source of the synchronous N-channel MOSFET.
Internal 8 V Regulator Output. Place a 1 µF ceramic capacitor between this pin and GND.
Low-Side Gate Driver Output. Connect this pin to the gate of the synchronous N-MOSFET.
Switch Node Output. Connect this pin to the output inductor.
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF ceramic capacitor between SW and BST.
The exposed pad should be soldered to an external ground plane underneath the IC for thermal
dissipation.
EPAD
Rev. 0 | Page 6 of 28
Data Sheet
ADP2381
TYPICAL PERFORMANCE CHARACTERISTICS
Operating conditions: TA = 25oC, VIN = 12 V, V OUT = 3.3 V, L = 2.2 µH, COUT = 2 × 100 µF, fSW = 500 kHz, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
INDUCTOR: FDVE1040-2R2M
MOSFET: FDS6298
INDUCTOR: FDVE1040-4R7M
MOSFET: FDS6298
0
1
2
3
4
5
6
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 500 kHz
Figure 7. Efficiency at VIN = 12 V, fSW = 250 kHz
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
INDUCTOR: FDVE1040-3R3M
MOSFET: FDS6298
INDUCTOR: 744 333 0100
MOSFET: FDS6298
0
1
2
3
4
5
6
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 18 V, fSW = 500 kHz
Figure 8. Efficiency at VIN = 5 V, fSW = 500 kHz
160
3.20
3.00
2.80
2.60
2.40
2.20
2.00
1.80
150
140
130
120
110
100
90
T
T
T
= –40°C
= +25°C
= +125°C
T
T
T
= –40°C
= +25°C
= +125°C
J
J
J
J
J
J
4
6
8
10
12
(V)
14
16
18
20
4
6
8
10
12
(V)
14
16
18
20
V
V
IN
IN
Figure 6. Shutdown Current vs. VIN
Figure 9. Quiescent Current vs. VIN
Rev. 0 | Page 7 of 28
ADP2381
Data Sheet
4.5
4.4
1.30
1.25
RISING
FALLING
0
4.3
4.2
4.1
4.0
3.9
3.8
RISING
1.20
1.15
1.10
FALLING
1.05
1.00
3.7
3.6
–40
–20
20
40
60
80
100
120
120
120
–40
–20
0
20
40
60
80
100
120
120
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. PVIN UVLO Threshold vs. Temperature
Figure 13. UVLO Pin Threshold vs. Temperature
3.30
606
604
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
602
600
598
596
594
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. SS Pin Pull-Up Current vs. Temperature
Figure 14. FB Voltage vs. Temperature
530
520
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
510
500
490
480
470
R
= 100kΩ
OSC
7.6
–40
–40
–20
0
20
40
60
80
100
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Frequency vs. Temperature
Figure 15. VREG Voltage vs. Temperature
Rev. 0 | Page 8 of 28
Data Sheet
ADP2381
70
11.0
10.5
60
10.0
9.5
9.0
8.5
8.0
50
40
30
20
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
SW
SW
1
1
LD
LD
2
2
CH1 5.00V CH2 5.00V
M20.0ns
46.60%
A
CH2
3.70V
CH1 5.00V CH2 5.00V
M20.0ns
43.80%
A
CH2
3.70V
T
T
Figure 17. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF
Figure 20. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF
V
(AC)
OUT
1
EN/SS
3
I
L
V
OUT
1
2
SW
PGOOD
4
2
I
OUT
4
B
B
CH1 10mV
CH2 10V
CH4 2A Ω
M2.00µs
50.00%
A
CH2
6.00V
CH1 2.00V
CH3 5.00V
CH2 5.00V
CH4 5.00A Ω
M2.00ms
50.00%
A
CH2
5.80V
W
W
T
T
Figure 18. Working Mode Waveform
Figure 21. Soft Start with Full Load
Rev. 0 | Page 9 of 28
ADP2381
Data Sheet
SYNC
EN/SS
3
3
V
OUT
1
SW
PGOOD
2
4
2
I
L
B
B
CH1 2.00V
CH3 5.00V
CH2 5.00V
M2.00ms
A
CH2
2.00V
2.52 A
1.96V
CH3 5.00V
CH2 10.0V M1.00µs
50.00%
A
CH2
7.00V
W
W
CH4 5.00A Ω
T
49.60%
T
Figure 22. Precharged Output
Figure 25. External Synchronization
V
(AC)
OUT
V
(AC)
OUT
1
1
V
IN
SW
I
OUT
3
2
4
B
B
B
B
CH2 10.0V
CH1 100mV
M200µs
70.20%
A
CH4
CH1 20.0mV
CH3 5.00V
M1.00ms
W
T 20.20%
A
CH3
13.5V
W
W
W
CH4 2.00A Ω
T
Figure 23. Load Transient Response, 1 A to 5 A
Figure 26. Line Transient Response, VIN from 10 V to 16 V, IOUT = 6 A
V
V
OUT
OUT
1
2
4
1
SW
SW
2
I
I
L
L
4
B
B
CH1 2.00V
CH2 10.0V
CH4 5.00A Ω
M10.00ms
30.40%
A CH1
CH1 2.00V
CH2 10.0V
CH4 5.00A Ω
M10.00ms
60.40%
A
CH1
1.96V
W
W
T
T
Figure 24. Output Short Entry
Figure 27. Output Short Recovery
Rev. 0 | Page 10 of 28
Data Sheet
ADP2381
7
6
5
4
3
7
6
5
4
3
2
1
V
V
V
V
V
V
= 1V
OUT
OUT
OUT
OUT
OUT
OUT
2
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
1
OUT
V
OUT
0
25
0
25
40
55
70
85
100
40
55
70
85
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 28. Load Current vs. Ambient Temperature, VIN = 12 V,
SW = 500 kHz
Figure 29. Load Current vs. Ambient Temperature, VIN = 12 V,
SW = 250 kHz
f
f
Rev. 0 | Page 11 of 28
ADP2381
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
VREG
ADP2381
CLK
RT
BIAS AND DRIVER
REGULATOR
PVIN
OSCILLATOR
SYNC
SLOPE RAMP
UVLO
PVIN
320kΩ
BOOST
REGULATOR
UVLO
+
125kΩ
1.2V
–
+
A
CS
–
+
OCP
–
HICCUP
MODE
I
MAX
SLOPE RAMP
Σ
COMP
BST
SW
0.6V
+
I
SS
+
CMP
–
NFET
EN/SS
FB
+
DRIVER
AMP
–
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
OVP
0.7V
–
VREG
PROTECTION
+
–
CLK
DRIVER
LD
0.54V
PGND
+
PGOOD
GND
NEGATIVE
CURRENT LIMIT
CMP
DEGLITCH
–
+
Figure 30. Functional Block Diagram
Rev. 0 | Page 12 of 28
Data Sheet
ADP2381
THEORY OF OPERATION
The ADP2381 is a synchronous, step-down, dc-to-dc regulator.
It uses current-mode architecture with an integrated high-side
power switch and a low-side driver. It targets high performance
applications that require high efficiency and design flexibility.
A 100 kΩ resistor sets the frequency to 500 kHz, and a 215 kΩ
resistor sets the frequency to 250 kHz. Figure 31 shows the typical
relationship between fSW and ROSC
.
1400
The ADP2381 can operate with an input voltage from 4.5 V to
20 V and regulate the output voltage down to 0.6 V. Additional
features for design flexibility include programmable switching
frequency, soft start, external compensation, and power-good pin.
1200
1000
800
600
400
200
0
CONTROL SCHEME
The ADP2381 uses fixed frequency, peak current-mode PWM
control architecture. At the start of each oscillator cycle, the
high-side N-MOSFET is turned on, putting a positive voltage
across the inductor. Current in the inductor increases until
the current sense signal crosses the peak inductor current thresh-
old that turns off the high-side N-MOSFET and turns on the
low-side N-MOSFET. This puts a negative voltage across the
inductor, causing the inductor current to decrease. The low-
side N-MOSFET stays on for the rest of the cycle.
20
60
100
140
180
(kΩ)
220
260
300
R
OSC
Figure 31. Switching Frequency vs. ROSC
SYNCHRONIZATION
INTERNAL REGULATOR (VREG)
To synchronize the ADP2381, connect an external clock to the
SYNC pin. The frequency of the external clock can be in the
range of 250 kHz to 1.4 MHz. During synchronization, the
switching rising edge runs 180° out of phase with the external
clock rising edge.
The internal regulator provides a stable supply for the internal
circuits and provides bias voltage for the low-side gate driver.
Placing a 1 µF ceramic capacitor between VREG and GND is
recommended. The internal regulator also includes a current-
limit circuit to protect the circuit if the maximum external
load is added.
When the ADP2381 is being synchronized, connect a resistor
from the RT pin to GND to program the internal oscillator to
run at 90% to 110% of the external synchronization clock.
BOOTSTRAP CIRCUITRY
The ADP2381 has integrated the boot regulator to provide the
gate drive voltage for the high-side N-MOSFET. It generates a
5 V bootstrap voltage between BST and SW by differential
sensing.
ENABLE AND SOFT START
When the voltage of the EN/SS pin exceeds 0.5 V, the ADP2381
starts operation.
The ADP2381 has an internal digital soft start. The internal soft
start time can be calculated by using the following equation:
It is recommended to place a 0.1 µF, X7R or X5R ceramic
capacitor between the BST pin and the SW pin.
1500
SW[kHz]
LOW-SIDE DRIVER
tSS_ INT
=
(ms)
f
The LD pin provides the gate driver for the low-side N-channel
MOSFET. Internal circuitry monitors the external MOSFET to
ensure break-before-make switching to prevent cross
conduction.
A slow soft start time can be programmed by the EN/SS pin.
Place a capacitor between the EN/SS pin and GND. An internal
current charges this capacitor to establish the soft start ramp.
The soft start time can be calculated by using the following
equation:
OSCILLATOR
The ADP2381 switching frequency is controlled by the RT pin.
If the RT pin is connected to GND, the switching frequency is
set to 290 kHz. If the RT pin is open, the switching frequency is
set to 550 kHz. A resistor connected from RT to GND can
program the switching frequency according to the following
equation:
0.6V×CSS
tSS_ EXT
=
ISS_UP
where:
SS is the soft start capacitance.
SS_UP is the soft start pull-up current (3.3 µA).
C
I
57,600
OSC[kΩ]+15
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the EN/SS voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
f
SW[kHz]=
R
Rev. 0 | Page 13 of 28
ADP2381
Data Sheet
If the output voltage is charged prior to turn-on, the ADP2381
prevents the low-side MOSFET from turning on, which
discharges the output voltage until the soft start voltage exceeds
the voltage on the FB pin.
restart. If the current limit fault is cleared, the regulator resumes
normal operation. Otherwise, it reenters hiccup mode.
The ADP2381 also provides a sink current limit to prevent the
low-side MOSFET from sinking a lot of current from the load.
When the voltage across the low-side MOSFET exceeds the
sink current-limit threshold, which is typically 20 mV, the low-
side MOSFET turns off immediately for the rest of this cycle.
Both high-side and low-side MOSFETs turn off until the next
clock cycle.
When the regulator is disabled or a current fault happens, the
soft start capacitor is discharged, and the internal digital soft
start is reset to 0 V.
POWER GOOD
The power-good (PGOOD) pin is an active high, open-drain
output that requires a pull-up resistor. A logic high indicates
that the voltage at the FB pin (and, therefore, the output
voltage) is above 95% of the reference voltage and there is a
1024 cycle waiting period before PGOOD is pulled high. A logic
low indicates that the voltage at the FB pin is below 90% of the
reference voltage and there is a 16-cycle waiting period before
PGOOD is pulled low.
In some cases, the input voltage (PVIN) ramp rate is too slow or
the output capacitor is too large to support the setting regulation
voltage during the soft start, causing the regulator to enter
hiccup mode. To avoid such cases, use a resistor divider at the
UVLO pin to program the UVLO input voltage, or use a longer
soft start time.
OVERVOLTAGE PROTECTION (OVP)
The ADP2381 provides an overvoltage protection feature to
protect the system against an output shorting to a higher voltage
supply or a strong load transient occurring. If the feedback
voltage increases to 0.7 V, the internal high-side MOSFET and
low-side driver are turned off until the voltage at FB decreases to
0.63 V. At that time, the ADP2381 resumes normal operation.
PEAK CURRENT LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2381 has a peak current-limit protection circuit to
prevent current runaway. During soft start, the ADP2381 uses
frequency foldback to prevent output current runaway. The
switching frequency is reduced according to the voltage on the
FB pin, which allows more time for the inductor to discharge.
The correlation between the switching frequency and FB pin
voltage is shown in Table 5.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO pin enable threshold is 1.2 V with 100 mV
hysteresis.
The ADP2381 has an internal voltage divider consisting of two
resistors from PVIN to GND, 320 kΩ for the high-side resistor
and 125 kΩ for the low-side resistor. An external resistor divider
from PVIN to GND can be used to override the internal resistor
divider.
Table 5. Switching Frequency and FB Pin Voltage
FB Pin Voltage
Switching Frequency
VFB ≥ 0.4 V
fSW
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
fSW/2
fSW/4
THERMAL SHUTDOWN
For heavy load protection, the ADP2381 uses hiccup mode for
overcurrent protection. When the inductor peak current reaches
the current-limit value, the high-side MOSFET turns off and
the low-side driver turns on until the next cycle, while the
overcurrent counter increments. If the overcurrent counter
reaches 10, or the FB pin voltage falls to ≤0.4 V after the soft
start, the regulator enters hiccup mode. The high-side MOSFET
and low-side MOSFET are both turned off. The regulator
remains in this mode for 4096 clock cycles and then attempts to
In the event that the ADP2381 junction temperatures rise above
150°C, the thermal shutdown circuit turns off the regulator.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient
temperature. A 25°C hysteresis is included so that when thermal
shutdown occurs, the ADP2381 does not return to operation
until the on-chip temperature drops below 125°C. Upon
recovery, soft start is initiated prior to normal operation.
Rev. 0 | Page 14 of 28
Data Sheet
ADP2381
APPLICATIONS INFORMATION
The maximum output voltage for a given input voltage and
INPUT CAPACITOR SELECTION
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is
typically 200 ns, and the maximum duty cycle of the ADP2381
is typically 90%.
The input decoupling capacitor is used to attenuate high
frequency noise on the input. This capacitor should be a
ceramic capacitor in the range of 10 µF to 47 µF. It should be
placed close to the PVIN pin. The loop composed by this input
capacitor, high-side NFET, and low-side NFET must be kept as
small as possible.
The maximum output voltage limited by the minimum off time
at a given input voltage and frequency can be calculated using
the following equation:
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the input
capacitor should be larger than the following equation:
V
OUT_MAX = VIN × (1 – tMIN_OFF × fSW) – (RDSON_HS – RDSON_LS) ×
OUT_MAX × (1 – tMIN_OFF × fSW) – (RDSON_LS + RL) × IOUT_MAX
where:
OUT_MAX is the maximum output voltage.
MIN_OFF is the minimum off time.
I
(2)
IC
= IOUT × D ×(1 − D)
_RMS
IN
V
t
I
OUTPUT VOLTAGE SETTING
OUT_MAX is the maximum output current.
The output voltage of ADP2381 can be set by an external
resistive divider using the following equation:
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated by using the
following equation:
RTOP
RBOT
VOUT = 0.6 × 1 +
VOUT_MAX = DMAX × VIN
(3)
To limit output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT is less than 30 kΩ.
where DMAX is the maximum duty.
As Equation 1 to Equation 3 show, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
Table 6 gives the recommended resistor divider values for
various output voltage options.
INDUCTOR SELECTION
Table 6. Resistor Divider for Different Output Voltages
The inductor value is determined by the operating frequency,
VOUT (V)
RTOP
,
1% (kΩ)
RBOT, 1% (kΩ)
input voltage, output voltage, and inductor ripple current. Using
a small inductor leads to a faster transient response, but it
degrades efficiency due to larger inductor ripple current,
whereas using a large inductor value leads to smaller ripple
current and better efficiency, but it results in a slower transient
response.
1.0
10
15
1.2
10
10
1.5
15
10
1.8
20
10
2.5
3.3
5.0
47.5
10
22
15
2.21
3
As a guideline, the inductor ripple current, ΔIL, is typically set
to 1/3 of the maximum load current. The inductor can be
calculated using the following equation:
VOLTAGE CONVERSION LIMITATIONS
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2381 is typically 120 ns. The
minimum output voltage at a given input voltage and frequency
can be calculated using the following equation:
(
VIN − VOUT
)
× D
L =
∆IL × fSW
where:
V
V
IN is the input voltage.
OUT is the output voltage.
ΔIL is the inductor current ripple.
SW is the switching frequency.
D is the duty cycle.
V
OUT_MIN = VIN × tMIN_ON × fSW – (RDSON_HS – RDSON_LS) × IOUT_MIN
× tMIN_ON × fSW – (RDSON_LS + RL) × IOUT_MIN (1)
where:
OUT_MIN is the minimum output voltage.
MIN_ON is the minimum on time.
SW is the switching frequency.
f
V
t
f
VOUT
D =
VIN
R
DSON_HS is the high-side MOSFET on resistance.
The ADP2381 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when
the duty cycle is larger than 50%. The internal slope
compensation limits the minimum inductor value.
R
DSON_LS is the low-side MOSFET on resistance.
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
Rev. 0 | Page 15 of 28
ADP2381
Data Sheet
For a duty cycle that is larger than 50%, the minimum inductor
value is determined by the following equation:
quick saturation characteristic, the saturation current rating of
the inductor should be higher than the current-limit threshold of
the switch to prevent the inductor from becoming saturated.
VOUT ×(1 − D)
2 × fSW
The rms current of the inductor can be calculated by
The inductor peak current is calculated using the following
equation:
∆IL2
12
IRMS
= +
IO2UT
∆IL
2
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
IPEAK = IOUT
+
The saturation current of the inductor must be larger than the
peak inductor current. For the ferrite core inductors with a
Table 7. Recommended Inductors
Vendor
Part No.
Value (µH)
0.47
0.75
1.0
1.5
2.2
ISAT (A)
15.6
10.9
9.5
13.7
11.4
9.8
IRMS (A)
14.1
10.7
9.5
14.6
11.6
9.0
DCR (mΩ)
3.7
6.2
8.5
4.6
Toko
FDVE0630-R47M
FDVE0630-R75M
FDVE0630-1R0M
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
IHLP3232DZ-R47M-11
IHLP3232DZ-R68M-11
IHLP3232DZ-1R0M-11
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
744 325 120
6.8
3.3
4.7
10.1
13.8
2.38
3.22
4.63
5.8
8.2
8.0
Vishay
0.47
0.68
1.0
1.5
2.2
14
14.5
12
27.5
25.6
18.6
17
25
22.2
18.2
15
12
10
9
3.3
4.7
14.4
16.5
1.8
9.5
Wurth Elektronik
1.2
25
20
744 325 180
1.8
18
16
3.5
744 325 240
2.4
17
14
4.75
5.9
744 325 330
3.3
15
12
744 325 420
4.2
14
11
7.1
Rev. 0 | Page 16 of 28
Data Sheet
ADP2381
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
performance.
,
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output ripple
voltage and the loop dynamics of the regulator.
The selected output capacitor voltage rating should be greater
than the output voltage. The rms current rating of the output
capacitor should be larger than the following equation:
During a load step transient on the output, for example, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp up the inductor
current, which causes the output to undershoot. The output
capacitance required to satisfy the voltage droop requirement
can be calculated using the following equation:
∆IL
12
IC
=
_RMS
OUT
LOW-SIDE POWER DEVICE SELECTION
KUV × ∆ISTEP2 × L
The ADP2381 has an integrated low-side MOSFET driver that
drives the low-side NFET. The selection of the low-side NFET
affects the dc-to-dc regulator performance.
COUT _UV
=
2 ×
(
VIN −VOUT × ∆VOUT _UV
)
where:
UV is a factor typically of 2.
ΔISTEP is the load step.
The selected MOSFET must meet the following requirements:
K
•
•
•
Drain-source voltage (VDS) must be higher than
1.2 × VIN.
Drain current (ID) must be greater than 1.2 × ILIMIT_MAX
which is the selected maximum current-limit threshold.
The ADP2381 low-side gate drive voltage is 8 V. Make sure
that the selected MOSFET can fully turn on at 8 V. Total
gate charge (Qg at 8 V) must be less than 50 nC. Lower Qg
characteristics constitute higher efficiency.
ΔVOUT_UV is the allowable undershoot on the output voltage.
,
Another case occurs when a load is suddenly removed from the
output. The energy stored in the inductor rushes into the
capacitor, which causes the output to overshoot. The output
capacitance required to meet the overshoot requirement can be
calculated using the following equation:
KOV × ∆ISTEP2 × L
COUT _OV
=
•
The low-side MOSFET carries the inductor current when
the high-side MOSFET is turned off. For low duty cycle
application, the low-side MOSFET carries the output
current during most of the period. To achieve higher
efficiency, it is important to select a low on-resistance
MOSFET. The power conduction loss of the low-side
MOSFET can be calculated by using the following
equation:
VOUT + ∆VOUT _OV
2 −VOUT
2
where:
OV is a factor typically of 2.
K
ΔVOUT_OV is the allowable undershoot on the output voltage.
The output ripple is determined by the ESR and the capaci-
tance. Use the following equation to select a capacitor that can
meet the output ripple requirements:
P
FET_LOW = IOUT2 × RDSON × (1 – D)
∆
IL
8 × fSW × ∆VOUT _RIPPLE
∆VOUT _RIPPLE
COUT _RIPPLE
=
where RDSON is the on resistance of the low-side MOSFET.
Make sure that the MOSFET can handle the thermal
dissipation due to the power loss.
•
RESR
=
∆IL
Some recommended MOSFETs are listed in Table 8.
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
ESR is the equivalent series resistance of the output capacitor.
R
Table 8. Recommended MOSFETs
Vendor
Fairchild
Fairchild
Fairchild
Vishay
AOS
Part No.
FDS6298
FDS8880
FDM7578
SiA430DJ
AON7402
AO4884L
VDS (V)
30
30
25
20
ID (A)
13
10.7
14
10.8
39
10
RDSON (mΩ)
Qg (nC)
10
12
8
5.3
12
12
8
18.5
15
16
30
40
7.1
13.6
AOS
Rev. 0 | Page 17 of 28
ADP2381
Data Sheet
1
PROGRAMMING INPUT VOLTAGE UVLO
fZ =
fP =
2×π × RESR ×COUT
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling
threshold of PVIN and UVLO are listed in Table 9. These
default values can be replaced by using an external voltage
divider to achieve a more accurate externally adjustable UVLO,
as shown in Figure 32. Lower values of the external resistors are
recommended to obtain a high accuracy UVLO threshold
because the values of the internal 320 kΩ and 125 kΩ resistors
may vary by as much as 20%.
1
2×π ×(R + RESR )×COUT
where:
VI = 8.7 A/V.
R is the load resistance.
OUT is the output capacitance.
ESR is the equivalent series resistance of the output capacitor.
A
C
R
The external voltage loop is compensated by a transconduct-
ance amplifier with a simple external RC network placed either
between COMP and GND or between COMP and FB, as shown
in Figure 33 and Figure 34, respectively.
Table 9. Default Rising/Falling Voltage Threshold
Pin
Rising Threshold (V)
Falling Threshold (V)
PVIN
UVLO
4.28
1.2
3.92
1.1
Compensation Network Between COMP and GND
Figure 33 shows the simplified peak current mode control small
signal circuit with a compensation network placed between
COMP and GND.
ADP2381
VIN
PVIN
320kΩ
125kΩ
R1
V
V
R
OUT
OUT
UVLO
R2
R
R
ADP2381
TOP
COMP
V
COMP
FB
+
–
A
VI
C
R
OUT
–
gm
+
BOT
R
C
Figure 32. External Programmable UVLO
C
CP
ESR
C
C
GND
A 1 kΩ resistor for R2 is an appropriate choice. Use the
following equation to obtain the value of R1 for a chosen input
voltage rising threshold:
Figure 33. Small Signal Circuit with Compensation Network Between COMP
and GND
(
V
IN _RISING −1.2 V × R2
)
R1 =
1.2 V
The RC and CC compensation components contribute a zero,
and the optional CCP and RC contribute an optional pole.
where VIN_RISING is the rising threshold of VIN.
The closed-loop transfer function is as follows:
The falling threshold of VIN can be determined by the
following equation:
1+ RC ×CC ×s
RC ×CC ×CCP
RBOT
RBOT + RTOP
−gm
C +CCP
TV (s)=
×
×
×GVD (s)
C
1.1 V × R1
VIN _FALLING
=
+ 1.1 V
s× 1+
×s
R2
C
C +CCP
where VIN_FALLING is the falling threshold of VIN.
Use the following design guidelines to select the RC, CC, and CCP
compensation components:
COMPENSATION DESIGN
The ADP2381 uses a peak current-mode control architecture
for excellent load and line transient response. For peak current-
mode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
•
Determine the cross frequency, fC. Generally, fc is between
SW/12 and fSW/6.
RC can be calculated by
f
•
2×π ×VOUT ×COUT × fC
RC =
VREF × gm ×AVI
The control to output transfer function is given by the following
equation:
where:
REF = 0.6 V.
V
gm = 500 µS.
s
1+
1+
•
Place the compensation zero at the domain pole, fP. CC can
be determined by:
2×π × fZ
s
2×π × fP
V
OUT (s)
GVD (s)=
= AVI ×R×
VCOMP (s)
(R + RESR )×COUT
CC =
RC
Rev. 0 | Page 18 of 28
Data Sheet
ADP2381
where:
•
CCP is optional, and it can be used to cancel the zero caused
by the ESR of the output capacitors.
r0 is the equivalent output impedance of the trans-conductance
amplifier, 40 MΩ.
R
ESR ×COUT
CCP
=
RTOP RBOT
RTOP + RBOT
RC
R
TOP //RBOT =
Compensation Network Between COMP and FB
Solve the preceding equations to obtain:
The compensation RC network can also be placed between
COMP and FB, as shown in Figure 34.
r0RCCCCCP
(B + RCCC )(r0 + A)
CC _ EA = B × gm
−
C
CP_EA
B + RCCC
CC _ EA
C
RC _ EA
CCP _ EA
where:
=
R
C_EA
C_EA
V
V
R
OUT
OUT
r0RCCCCCP
(B + RCCC )(r0 + A)
=
R
R
ADP2381
TOP
COMP
FB
+
–
A
VI
C
–
gm
OUT
V
COMP
+
A = (RTOP //RBOT )(1 + gm × r0 )
BOT
R
ESR
r0 (CCP + CC )
B =
GND
1 + gm (A + r0 )
ADIsimPower DESIGN TOOL
Figure 34. Small Signal Circuit with Compensation Network Between COMP
and FB
The ADP2381 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and parts count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about the ADIsimPower design tools, visit
When connecting the compensation network as shown in
Figure 34, it should have the same pole and zero as in Figure 33
to maintain the same compensation performance.
Assuming that the compensation networks of Figure 33 and
Figure 34 have the same pole and zero,
C
CP _ EA +CC _ EA
RCCC =RC _ EACC _ EA
−
gm
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
r0RCCCCCP = r0RC _ EACC _ EACCP _ EA
+
RC _ EACC _ EA CP _ EA(RTOP //RBOT )(1 + gm ×r0 )
C
r0(CCP +CC )+ RCCC =
r0 (CCP _ EA +CC _ EA )+ RC _ EACC _ EA
+
(CCP _ EA + CC _ EA )(RTOP //RBOT )(1 + gm × r0 )
Rev. 0 | Page 19 of 28
ADP2381
Data Sheet
DESIGN EXAMPLE
This section provides the procedures of selecting the external
components based on the example specifications listed in Table 10.
The schematic of this design example is shown in Figure 36.
This results in IPEAK = 7.09 A.
The rms current flowing through the inductor can be calculated
by the following equation:
Table 10. Step-Down DC-to-DC Regulator Requirements
2
IL
12
2
IRMS
IOUT
Parameter
Specification
VIN = 12.0 V ± 10%
VOUT = 3.3 V
Input Voltage
This results in IRMS = 6.03 A.
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
According to the calculated rms and peak inductor current
values, select an inductor with a minimum rms current rating of
6.03 A and a minimum saturation current rating of 7.09 A.
IOUT = 6 A
∆VOUT_RIPPLE = 33 mV
±±%ꢀ 1 A to ± Aꢀ 2 A/μs
fSW = ±00 kHz
Switching Frequency
To protect the inductor from reaching its saturation limit, the
inductor should be rated for at least 9.6 A saturation current for
reliable operation.
OUTPUT VOLTAGE SETTING
Choose a 10 kΩ resistor as the top feedback resistor (RTOP) and
calculate the bottom feedback resistor (RBOT) by using the
following equation:
Based on these requirements, select a 2.2 μH inductor, such as
the FDVE1040-2R2M from Toko, which has 6.8 mΩ DCR and
11.4 A saturation current.
0.6
VOUT 0.6
RBOT RTOP
OUTPUT CAPACITOR SELECTION
The output capacitor is required to meet both the output voltage
ripple requirement and the load transient response.
To set the output voltage to 3.3 V, the resistors values are
RTOP = 10 kΩ, RBOT = 2.21 kΩ.
To meet the output voltage ripple requirement, use the
following equation to calculate the ESR and capacitance of the
output capacitor:
FREQUENCY SETTING
Connect a 100 kΩ resistor from RT pin to GND to set the
switching frequency at 500 kHz.
IL
COUT _ RIPPLE
8 fSW VOUT _ RIPPLE
INDUCTOR SELECTION
The peak-to-peak inductor ripple current, ΔIL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
VOUT _RIPPLE
IL
RESR
This results in COUT_RIPPLE = 16.5 μF and RESR = 15.1 mΩ.
(VIN VOUT ) D
L
To meet the 5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
IL fSW
where:
VIN = 12 V.
VOUT = 3.3 V.
D = VOUT/VIN = 0.275.
ΔIL = 1.8A.
KOV ISTEP2 L
COUT _OV
COUT _UV
2
2
(VOUT VOUT _OV ) VOUT
KUV ISTEP2 L
fSW = 500 kHz.
2 (VIN VOUT ) VOUT _UV
This results in L = 2.659 μH. Choose the standard inductor
value of 2.2 μH.
where:
OV = KUV = 2, the coefficients for estimation purposes.
ΔISTEP = 4 A, the load transient step.
ΔVOUT_OV = 5%VOUT, the overshoot voltage.
ΔVOUT_UV = 5%VOUT, the undershoot voltage.
K
The peak-to-peak inductor ripple current can be calculated by
the following equation:
VIN VOUT D
IL
This results in COUT_OV = 63.1 μF and COUT_UV = 24.5 μF.
L fSW
According to the preceding calculation, the output capacitance
must be larger than 63 μF, and the ESR of the output capacitor
must be smaller than 15 mΩ. It is recommended that one 100
μF, X5R, 6.3 V ceramic capacitor and one 47 μF, X5R, 6.3 V
ceramic capacitor be used, such as the GRM32ER60J107ME20
and GRM32ER60J476ME20 from Murata with an ESR = 2 mΩ.
This results in ΔIL = 2.18 A.
The peak inductor current can be calculated using the following
equation:
IL
2
IPEAK IOUT
Rev. 0 | Page 20 of 28
Data Sheet
ADP2381
This results in
LOW-SIDE MOSFET SELECTION
R
C
C
C_EA = 73.3 kΩ.
C_EA = 727.6 pF.
CP_EA = 2.56 pF.
A low RDSON N-channel MOSFET is selected as a high efficiency
solution. The breakdown voltage of the MOSFET must be
higher than 1.2 × VIN, and the drain current must be larger than
1.2 × ILIMIT
.
Choose the standard values for RC_EA = 73.2 kΩ, CC_EA = 820 pF,
and CCP_EA = 2.2 pF.
It is recommended that a 30 V, N-channel MOSFET, such as the
FDS6298 from Fairchild, be used. The RDSON of the FDS6298 at
a 4.5 V driver voltage is 9.4 mΩ, and the total gate charge at 5 V
is 10 nC.
Figure 35 shows the bode plot at 6 A. The cross frequency is
kHz, and the phase margin is 61°.
60
180
144
108
72
COMPENSATION COMPONENTS
48
36
For a better load transient and stability performance, set the
cross frequency, fC, at fSW/10. In this case, fC = 1/500 kHz =
50 kHz.
24
12
36
r0RCCCCCP
(B + RCCC )(r0 + A)
0
0
CC _ EA = B × gm
−
–12
–24
–36
–48
–36
–72
–108
–144
B + RCCC
RC _ EA
CCP _ EA
where:
RC =
=
CC _ EA
r0RCCCCCP
(B + RCCC )(r0 + A)
=
–60
1k
–180
10k
100k
1M
FREEQUENCY (Hz)
Figure 35. Bode Plot at 6 A
2 ×π ×VOUT ×COUT × fC
VREF × gm × AVI
=
SOFT START TIME PROGRAM
2 ×π × 3.3V × 94μF × 50kHz
0.6V × 500 μS × 8.7 A/V
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
= 37.3kΩ
=1.39 nF
(R + RESR ) × COUT
CC =
=
RC
tSS_ EXT × ISS_UP 4 ms × 3.3μA
CSS
=
=
= 22nF
(3.3V /6A + 0.002 Ω) × 94μF
0.6
0.6V
37.3kΩ
Choose a standard component value, CSS = 22 nF.
RESR × COUT 0.002 Ω× 94 μF
CCP
=
=
= 5.04 pF
INPUT CAPACITOR SELECTION
RC
37.3kΩ
A minimum 10 μF ceramic capacitor is required to be placed
near the PVIN pin. In this application, one 10 μF, X5R, 25 V
ceramic capacitor is recommended.
10 kΩ×2.21 kΩ
10 kΩ + 2.21 kΩ
RTOP RBOT
RTOP + RBOT
A =
(
1+ gm ×r0
)
=
×
(
1+500μS×40 MΩ
r0 (CCP + CC ) 40MΩ ×(5.04pF+1.39nF)
1 + gm(A + r0 ) 1+500μS×(3.62×107 +40 MΩ)
)
= 3.62×107
SCHEMATIC OF DESIGN EXAMPLE
See Figure 36 for a schematic of the design example.
B =
=
=
1.46 ×10−6
Rev. 0 | Page 21 of 28
ADP2381
Data Sheet
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
C
0.1µF
PVIN
PVIN
BST
BST
2.2µH
V
= 3.3V
OUT
C
IN
SW
SW
10µF
25V
C
C
OUT2
OUT1
100µF
6.3V
47µF
6.3V
UVLO ADP2381
PGOOD
M1
FDS6298
R
LD
OSC
100kΩ
C
VREG
1µF
RT
VREG
PGND
GND
SYNC
EN/SS
COMP
R
TOP
10kΩ
1%
C
22nF
SS
FB
R
BOT
2.21kΩ
1%
C
820pF
C_EA
R
C_EA
73.2kΩ
C
CP_EA
2.2pF
Figure 36. Schematic of Design Example
Rev. 0 | Page 22 of 28
Data Sheet
ADP2381
EXTERNAL COMPONENTS RECOMMENDATION
Table 11. Recommended External Components for Typical Applications with Compensation Network Between COMP and GND, 6
A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
VOUT (V)
L (µH)
2.2
2.2
3.3
3.3
4.7
4.7
6.8
1.5
2.2
2.2
2.2
3.3
2.2
1
COUT (µF)1
680 + 470
680 + 2 × 100
680 + 2 × 100
680
RTOP (kΩ)
RBOT (kΩ)
RC (kΩ)
CC (pF)
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
680
CCP (pF)
150
130
100
91
250
1
10
15
68
1.2
1.5
1.8
2.5
3.3
5
10
10
56
15
10
71.5
71.5
69.8
36
20
10
470
47.5
10
15
62
3 × 100
2 × 100
680 + 2 × 100
680 + 2 × 100
680
2.21
3
10
22
36
6.8
150
130
100
91
1
10
15
47
5
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
10
10
56
5
15
10
59
5
470
20
10
47
5
3 × 100
3 × 100
470
47.5
10
15
28
10
5
2.21
10
36
10
500
12
12
12
12
12
12
5
10
62
68
1.5
1.5
2.2
2.2
3.3
1
470
15
10
82
56
3 × 100
3 × 100
2 × 100
100
20
10
39
10
47.5
10
15
56
6.8
4.7
3.3
82
2.21
3
47
22
36
1
680
10
15
75
5
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
1
470
10
10
62
68
5
1
3 × 100
2 × 100
2 × 100
100 + 47
2 × 100
100
15
10
33
10
5
1
20
10
25.5
36
8.2
6.8
4.7
4.7
3.3
2.2
1.8
8.2
6.8
6.8
4.7
3.3
2.2
5
1.5
1
47.5
10
15
5
2.21
10
36
1000
12
12
12
12
5
1
20
51
1
47.5
10
15
36
680
1.5
1.5
0.47
0.47
0.68
0.68
0.68
0.68
100
2.21
3
47
680
100
22
73.2
43
680
1
3 × 100
2 × 100
2 × 100
100 + 47
100
10
15
680
5
1.2
1.5
1.8
2.5
3.3
10
10
34.8
43
680
5
15
10
680
5
20
10
39
680
5
47.5
10
15
36
680
5
100
2.21
47
680
1 680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 23 of 28
ADP2381
Data Sheet
Table 12. Recommended External Components for Typical Applications with Compensation Network between COMP and FB, 6 A
Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
VOUT (V)
L (µH)
2.2
2.2
3.3
3.3
4.7
4.7
6.8
1.5
2.2
2.2
2.2
3.3
2.2
1
COUT (µF)1
680 + 470
680 + 2 × 100
680 + 2 × 100
680
RTOP (kΩ)
RBOT (kΩ)
RC_EA (kΩ)
270
200
287
316
470
71.5
86.6
191
200
240
220
187
71.5
220
330
169
360
93.1
86.6
330
220
130
100
220
71.5
232
240
93.1
169
178
120
178
169
240
93.1
CC_EA (pF)
750
820
680
680
470
1500
1200
750
820
680
680
390
1500
390
390
330
220
680
620
390
390
330
330
220
680
160
100
390
330
180
220
180
160
100
390
CCP_EA (pF)
39
39
22
22
10
4.7
2.2
39
39
22
22
2.2
4.7
22
15
2.2
1
250
1
10
15
1.2
1.5
1.8
2.5
3.3
5
10
10
15
10
20
10
470
47.5
10
15
3 × 100
2 × 100
680 + 2 × 100
680 + 2 × 100
680
2.21
3
22
1
10
15
5
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
10
10
5
15
10
5
470
20
10
5
3 × 100
3 × 100
470
47.5
10
15
5
2.21
10
500
12
12
12
12
12
12
5
10
1.5
1.5
2.2
2.2
3.3
1
470
15
10
3 × 100
3 × 100
2 × 100
100
20
10
47.5
10
15
2.21
3
2.2
1.5
22
22
2.2
2.2
1
22
1
680
10
15
5
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
1
470
10
10
5
1
3 × 100
2 × 100
2 × 100
100 + 47
2 × 100
100
15
10
5
1
20
10
5
1.5
1
47.5
10
15
5
2.21
10
2.2
1
1000
12
12
12
12
5
1
20
1
47.5
10
15
1
1.5
1.5
0.47
0.47
0.68
0.68
0.68
0.68
100
2.21
3
1
100
22
1
1
3 × 100
2 × 100
2 × 100
100 + 47
100
10
15
2.2
2.2
1
5
1.2
1.5
1.8
2.5
3.3
10
10
5
15
10
5
20
10
1
5
47.5
10
15
1
5
100
2.21
1
1 680 μF: 4V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 24 of 28
Data Sheet
ADP2381
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential for obtaining the best
performance from the ADP2381. Poor printed circuit board
(PCB) layout degrades the output regulation as well as the
electromagnetic interface (EMI) and electromagnetic
compatibility (EMC) performance. Figure 38 shows a PCB
layout example. For optimum layout, use the following
guidelines:
plane. In addition, ensure that the high current path from
the power ground plane through the external MOSFET,
inductor, and output capacitor back to the power ground
plane is as short as possible by tying the MOSFET source
node to the PGND plane as close as possible to the input
and output capacitors.
Make the low-side driver path from the LD pin of the
ADP2381 to the external MOSFET gate node and back to
the PGND pin of the ADP2381 as short as possible, and
use a wide trace for better noise immunity.
•
•
Use separate analog ground and power ground planes.
Connect the ground reference of sensitive analog circuitry,
such as output voltage divider components, to analog
ground. In addition, connect the ground reference of
power components, such as input and output capacitors
and a low-side MOSFET, to power ground. Connect both
ground planes to the exposed pad of the ADP2381.
Place the input capacitor, inductor, low-side MOSFET,
output capacitor as close to the IC as possible and use short
traces.
•
•
Connect the exposed pad of the ADP2381 to a large copper
plane to maximize its power dissipation capability for
better thermal dissipation.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Try to
minimize the length of the trace that connects the top of
the feedback resistor divider to the output while keeping
the trace away from the high current traces and the
switching node to avoid noise pickup. To further reduce
noise pickup, place an analog ground plane on either side
of the FB trace and ensure that the trace is as short as
possible to reduce parasitic capacitance pickup.
•
•
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the
input capacitor through the inductor, the output capacitor,
and the power ground plane back to the input capacitor as
short as possible. To accomplish this, ensure that the input
and output capacitors share a common power ground
V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PVIN
PVIN
BST
L
C
V
BST
OUT
C
IN
SW
SW
C
OUT
UVLO ADP2381
PGOOD
FET
LD
C
RT
VREG
PGND
GND
VREG
R
OSC
SYNC
EN/SS
COMP
R
R
TOP
C
SS
FB
BOT
C
C_EA
R
C_EA
C
CP_EA
Figure 37. High Current Path in the PCB Circuit
Rev. 0 | Page 25 of 28
ADP2381
Data Sheet
POWER GROUND PLANE
VIA
PVIN
Input
Bulk Cap
Bottom Layer
Trace
Output
Capacitor
Copper Plane
Input
Bypass
Cap
LOW-SIDE
MOSFET
CBST
PVIN
BST
SW
INDUCTOR
PVIN
VOUT
SW
UVLO
PGOOD
RT
SW
Pull Up
LD
CVREG
VREG
PGND
GND
FB
SYNC
EN/SS
COMP
CC_EA
RC_EA
CSS
RTOP
ROSC
RBOT
CCP_EA
ANALOG GROUND PLANE
Figure 38. Recommended PCB Layout
Rev. 0 | Page 26 of 28
Data Sheet
ADP2381
TYPICAL APPLICATION CIRCUITS
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
1µH
C
0.1µF
PVIN
BST
BST
V
= 1.2V
OUT
C
10µF
25V
IN
PVIN
SW
SW
C
OUT
470µF
6.3V
UVLO ADP2381
PGOOD
M1
FDS6298
R
LD
OSC
100kΩ
C
VREG
1µF
RT
VREG
PGND
GND
SYNC
EN/SS
COMP
R
TOP
10kΩ
1%
C
SS
FB
22nF
R
10kΩ
1%
BOT
R
62kΩ
C
C
68pF
CP
C
1.5nF
C
Figure 39. Compensation Network Between COMP and GND, VIN = 12 V, VOUT = 1.2 V, IOUT = 6 A, fSW = 500 kHz
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
C
0.1µF
PVIN
PVIN
BST
BST
1.5µH
V
= 1.8V
R1
OUT
C
IN
SW
SW
7.32kΩ
10µF
25V
C
C
C
OUT3
OUT1
OUT2
1%
100µF
6.3V
100µF
6.3V
100µF
6.3V
UVLO ADP2381
PGOOD
M1
FDS6298
R2
LD
1kΩ
R
OSC
1%
100kΩ
C
VREG
1µF
RT
VREG
PGND
GND
SYNC
EN/SS
COMP
R
TOP
20kΩ
1%
C
22nF
SS
FB
R
BOT
10kΩ
1%
C
330pF
C_EA
R
C_EA
169kΩ
C
CP_EA
2.2pF
Figure 40. Programming Input Voltage UVLO Rising Threshold at 10 V, VIN = 12 V, VOUT = 1.8 V, IOUT = 6 A, fSW = 500 kHz
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
3.3µH
PVIN
PVIN
BST
C
0.1µF
BST
C
V
= 5V
OUT
IN
OUT
10µF
25V
SW
SW
C
UVLO ADP2381
PGOOD
100µF
6.3V
M1
FDS6298
R
LD
OSC
82kΩ
RT
VREG
PGND
GND
C
VREG
1µF
SYNC
EN/SS
COMP
R
TOP
22kΩ
1%
FB
R
SOT
3kΩ
1%
C
620pF
C_EA
R
C_EA
86.6kΩ
C
CP_EA
1.5pF
Figure 41. Using Internal Soft Start, Programming Switching Frequency at 600 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 6 A, fSW = 600 kHz
Rev. 0 | Page 27 of 28
ADP2381
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
3.40
2.68
16
1
9
8
9
8
16
4.50
4.40
4.30
2.46
1.75
EXPOSED
PAD
6.40 BSC
1
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
TOP VIEW
BOTTOM VIEW
SECTION OF THIS DATA SHEET.
0.95
0.90
0.85
0.20
0.09
1.10 MAX
0.25
8°
0°
0.70
0.60
0.50
SEATING
PLANE
0.15 MAX
0.05 MIN
0.30
0.19
0.65 BSC
COPLANARITY
0.076
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 42. 16-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
(RE-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead TSSOP_EP
16-Lead TSSOP_EP
Evaluation Board
Package Option
RE-16-4
RE-16-4
Packing
ADP2381AREZ-R7
ADP2381AREZ
ADP2381-EVALZ
Reel
Tube
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10209-0-3/12(0)
Rev. 0 | Page 28 of 28
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