HMC1126ACEZ-R7 [ADI]
GaAs, pHEMT, Low Noise Amplifier, 400 MHz to 52 GHz;
| 型号： | HMC1126ACEZ-R7 |
| 厂家： | 
ADI |
| 描述： | GaAs, pHEMT, Low Noise Amplifier, 400 MHz to 52 GHz |
| 文件： | 总21页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GaAs, pHEMT, Low Noise Amplifier,
400 MHz to 52 GHz
Data Sheet
HMC1126ACEZ
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Gain: 12 dB typical at 10 GHz to 26 GHz
Input return loss: 14 dB typical at 10 GHz to 26 GHz
Output return loss: 16 dB typical at 10 GHz to 40 GHz
OP1dB: 17.5 dB typical at 10 GHz to 26 GHz
GND
GND
GND
RFIN
GND
GND
1
2
3
4
5
6
18 GND
17 GND
16
15
14
RFOUT
GND
PSAT: 21 dBm typical at 10 GHz to 26 GHz
OIP3: 28.5 dBm typical at 10 GHz to 26 GHz
Noise figure: 3.5 dB typical at 10 GHz to 26 GHz
5 V supply voltage at 85 mA
GND
13 GND
50 Ω matched input and output
No external passive components required
5.00 mm × 5.00 mm, 24-terminal LGA_CAV package
Figure 1.
APPLICATIONS
Test instrumentation
Military and space
GENERAL DESCRIPTION
The HMC1126ACEZ is a gallium arsenide (GaAs),
external passive components for operation (ac coupling capacitors
and power supply decoupling capacitors) are integrated, which
facilitates a small and compact printed circuit board (PCB)
footprint.
pseudomorphic high electron mobility transfer (pHEMT), low
noise amplifier that operates from 400 MHz to 52 GHz. The
HMC1126ACEZ provides 12 dB of typical gain, 28.5 dBm typical
output third-order intercept (OIP3), 17.5 dBm typical output
power at 1 dB gain compression (OP1dB), and a 3.5 dB typical
noise figure at 10 GHz to 26 GHz. The HMC1126ACEZ
requires 85 mA from a 5 V supply. All of the typically required
The HMC1126ACEZ is housed in a 5.00 mm × 5.00 mm,
24-terminal chip array small outline no lead cavity (LGA_CAV)
package.
Rev. 0
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Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC1126ACEZ
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Pin Configuration and Function Descriptions .............................6
Interface Schematics .....................................................................6
Typical Performance Characteristics .............................................7
Theory of Operation ...................................................................... 15
Applications Information ............................................................. 16
Power-Up and Power-Down Sequencing............................... 16
Biasing the HMC1126ACEZ with the HMC920LP5E.......... 17
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications ................................................................... 3
400 MHz to 10 GHz Frequency Range ..................................... 3
10 GHz to 26 GHz Frequency Range ........................................ 3
26 GHz to 40 GHz Frequency Range ........................................ 4
40 GHz to 52 GHz Frequency Range ........................................ 4
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance...................................................................... 5
Electrostatic Discharge (ESD) Ratings...................................... 5
ESD Caution.................................................................................. 5
Constant Drain Current Biasing vs. Constant Gate Voltage
Biasing.......................................................................................... 19
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
11/2021—Revision 0: Initial Version
Rev. 0 | Page 2 of 21
Data Sheet
HMC1126ACEZ
ELECTRICAL SPECIFICATIONS
400 MHz TO 10 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, VGG2 = 1 V, and supply current (IDQ) = 85 mA, unless otherwise stated. Adjust VGG1 between −2 V and 0 V to
achieve IDQ = 85 mA typical.
Table 1.
Parameter
Min Typ
0.4
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
10
GHz
dB
GAIN
10.5 12.5
0.003
Gain Variation over Temperature
dB/°C
RETURN LOSS
Input
Output
11.5
13
dB
dB
OUTPUT
OP1dB
Saturated Output Power (PSAT
15
17.5
20
29
dBm
dBm
dBm
dBm
dB
)
OIP3
Output power (POUT) per tone = 0 dBm with 1 MHz tone spacing
POUT per tone = 0 dBm with 1 MHz tone spacing
Second-Order Intercept (OIP2)
31
NOISE FIGURE
4.0
SUPPLY
IDQ
VDD
85
5
mA
V
Adjust VGG1 to achieve IDQ = 85 mA typical
3.3
10 GHz TO 26 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, VGG2 = 1 V, and IDQ = 85 mA, unless otherwise stated. Adjust VGG1 between −2 V and 0 V to achieve IDQ = 85 mA typical.
Table 2.
Parameter
Min
10
Typ
Max
Unit
GHz
dB
Test Conditions/Comments
FREQUENCY RANGE
26
GAIN
10
12
Gain Variation over Temperature
0.006
dB/°C
RETURN LOSS
Input
Output
OUTPUT
OP1dB
PSAT
14
16
dB
dB
17.5
21
28.5
28
dBm
dBm
dBm
dBm
dB
OIP3
OIP2
POUT per tone = 0 dBm with 1 MHz tone spacing
POUT per tone = 0 dBm with 1 MHz tone spacing
NOISE FIGURE
SUPPLY
IDQ
3.5
85
5
mA
V
Adjust VGG1 to achieve IDQ = 85 mA typical
VDD
3.3
Rev. 0 | Page 3 of 21
HMC1126ACEZ
Data Sheet
26 GHz TO 40 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, VGG2 = 1 V, and IDQ = 85 mA, unless otherwise stated. Adjust VGG1 between −2 V and 0 V to achieve IDQ = 85 mA typical.
Table 3.
Parameter
Min
26
Typ
Max
Unit
GHz
dB
Test Conditions/Comments
FREQUENCY RANGE
40
GAIN
10.5
12.5
Gain Variation over Temperature
0.007
dB/°C
RETURN LOSS
Input
Output
OUTPUT
OP1dB
PSAT
13.5
16
dB
dB
16
20
27
4.5
dBm
dBm
dBm
dB
OIP3
POUT per tone = 0 dBm with 1 MHz tone spacing
Adjust VGG1 to achieve IDQ = 85 mA typical
NOISE FIGURE
SUPPLY
IDQ
85
5
mA
V
VDD
3.3
40 GHz TO 52 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, VGG2 = 1 V, and IDQ = 85 mA, unless otherwise stated. Adjust VGG1 between −2 V and 0 V to achieve IDQ = 85 mA typical.
Table 4.
Parameter
Min
Typ
Max
Unit
GHz
dB
Test Conditions/Comments
FREQUENCY RANGE
40
52
GAIN
12
Gain Variation over Temperature
0.01
dB/°C
RETURN LOSS
Input
Output
OUTPUT
OP1dB
PSAT
7.5
15
dB
dB
12.5
17.5
23.5
6
dBm
dBm
dBm
dB
OIP3
POUT per tone = 0 dBm with 1 MHz tone spacing
Adjust VGG1 to achieve IDQ = 85 mA typical
NOISE FIGURE
SUPPLY
IDQ
85
5
mA
V
VDD
3.3
Rev. 0 | Page 4 of 21
Data Sheet
HMC1126ACEZ
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Thermal performance is directly linked to system design and
operating environment. Careful attention to the PCB thermal
design is required.
Parameter
Rating
VDD
6 V
Gate Bias Voltage
VGG1
VGG2
For VDD = 3.3 V
For VDD = 4 V
For VDD = 5 V
RFIN Power
−3 V to 0 V
θJC is the channel to case thermal resistance, channel to bottom
of die using die attach epoxy.
0.5 V to 2.5 V
0.5 V to 3 V
1.0 V to 4 V
22 dBm
Table 6. Thermal Resistance
Package Type
θJC
Unit
CE-24-21
54.3
°C/W
Continuous Power Dissipation (PDISS), TA = 85°C
(Derate 18.4 mW/°C Above 85°C)
Temperature
Channel
Peak Reflow (Moisture Sensitivity Level
(MSL) 3)1
Storage Range
Operating Range
Junction to Maintain 1,000,000 Hours
Mean Time to Failure (MTTF)
Nominal Junction (TA = 85°C, VDD = 5 V,
IDQ = 85 mA)
1.66 W
1 θJC was determined by simulation under the following conditions: the heat
transfer is due solely to thermal conduction from the channel, through the
ground paddle, to the PCB, and the ground pad is held constant at the
operating temperature of 85°C.
175°C
260°C
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
−40°C to +150°C
−40°C to +85°C
175
Human body model (HBM) per ANSI/ESDA/JEDDEC JS-001.
Table 7. HMC1126ACEZ, 24-Terminal LGA_CAV
108
ESD Model
Withstand Threshold (V)
Class
HBM
250
1A
1 See the Ordering Guide for more information.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 5 of 21
HMC1126ACEZ
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
18 GND
GND
GND
GND
17
16
GND
RFOUT
HMC1126ACEZ
TOP VIEW
15 GND
14
RFIN 4
(Not to Scale)
5
6
GND
GND
GND
13 GND
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD
TO A GROUND PLANE WITH LOW THERMAL
AND ELECTRICAL IMPEDENCE.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 3, 5, 6, 7, 9, 11 to 15, GND
17, 18, 19, 21 to 24
Ground. All the ground pins must be connected to a low impedance ground plane. See Figure 7 for
the interface schematic.
4
8
RFIN
VGG1
RF Input. RFIN is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic.
Gate Control 1 for the Amplifier. Adjust VGG1 to achieve IDQ = 85 mA. See Figure 6 for the interface
schematic.
10
VGG2
Gate Control 2 for the Amplifier. For nominal operation, apply 1 V to VGG2. See Figure 5 for the
interface schematic.
16
20
RFOUT
VDD
RF Output. RFOUT is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic.
Drain Supply Voltage with Integrated RF Choke. Connect the dc bias to VDD to provide IDQ. See Figure 4
for the interface schematic.
EPAD
Exposed Pad. Connect the exposed pad to a ground plane with low thermal and electrical
impedance.
INTERFACE SCHEMATICS
1
V
GG
RFIN
Figure 3. RFIN Interface Schematic
Figure 6. VGG1 Interface Schematic
V
DD
RFOUT
GND
Figure 4. VDD and RFOUT Interface Schematic
Figure 7. GND Interface Schematic
2
V
GG
Figure 5. VGG2 Interface Schematic
Rev. 0 | Page 6 of 21
Data Sheet
HMC1126ACEZ
TYPICAL PERFORMANCE CHARACTERISTICS
IDQ is the drain current without the RF signal applied, and IDD is the drain current with the RF signal applied.
15
15
10
10
S22
S21
S11
5
5
0
S22
S21
S11
0
–5
–5
–10
–15
–20
–25
–10
–15
–20
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
5
10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Low Frequency Gain and Return Loss vs. Frequency, VDD = 5 V,
IDQ = 85 mA, VGG2 = 1 V (S22 Is the Output Return Loss, S21 Is the Gain, and
S11 Is the Input Return Loss)
Figure 11. Gain and Return Loss vs. Frequency,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
16
14
12
10
8
0
–5
+85°C
+25°C
–40°C
–10
–15
–20
–25
6
+85°C
+25°C
–40°C
4
2
0
2
7
12
17
22
27
32
37
42
47
52
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9.Gain vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 12. Output Return Loss vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
0
–5
16
14
12
10
8
+85°C
+25°C
–40°C
–10
–15
–20
6
5.0V
4.0V
3.3V
4
2
0
2
7
12
17
22
27
32
37
42
47
52
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Input Return Loss vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 13. Gain vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
Rev. 0 | Page 7 of 21
HMC1126ACEZ
Data Sheet
0
0
–5
1.4V
1.0V
5.0V
4.0V
3.3V
–5
–10
–15
–20
–10
–15
–20
2
7
12
17
22
27
32
37
42
47
52
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Input Return Loss vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
Figure 17. Input Return Loss vs. Frequency at Various VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
0
0
5.0V
4.0V
3.3V
1.4V
1.0V
–5
–10
–15
–20
–25
–5
–10
–15
–20
–25
2
7
12
17
22
27
32
37
42
47
52
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Output Return Loss vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
Figure 18. Output Return Loss vs. Frequency at Various VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
16
14
12
10
8
16
14
12
10
8
6
6
1.4V
1.0V
85mA
75mA
65mA
4
2
0
4
2
0
2
7
12
17
22
27
32
37
42
47
52
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Gain vs. Frequency at Various VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
Figure 19. Gain vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
Rev. 0 | Page 8 of 21
Data Sheet
HMC1126ACEZ
0
22
20
18
16
14
12
10
8
85mA
75mA
65mA
–5
–10
–15
–20
5.0V
4.0V
3.3V
6
4
2
0
2
7
12
17
22
27
32
37
42
47
52
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. Input Return Loss vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
Figure 23. OP1dB vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
0
22
20
18
16
14
12
10
8
85mA
75mA
65mA
–5
–10
–15
–20
–25
1.4V
1.0V
6
4
2
0
2
7
12
17
22
27
32
37
42
47
52
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. Output Return Loss vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
Figure 24. OP1dB vs. Frequency at Various VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
6
4
2
0
6
4
2
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. Low Frequency OP1dB vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 25. OP1dB vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Rev. 0 | Page 9 of 21
HMC1126ACEZ
Data Sheet
22
20
18
16
14
12
10
8
24
22
20
18
16
14
12
10
8
1.4V
1.0V
85mA
75mA
65mA
6
4
2
0
6
4
2
0
2
7
12
17
22
27
32
37
42
47
52
2
2
2
7
12
17
22
27
32
37
42
47
52
52
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. OP1dB vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
Figure 29. PSAT vs. Frequency at Various VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
24
22
20
18
16
14
12
10
8
24
22
20
18
16
14
12
10
8
5.0V
4.0V
3.3V
85mA
75mA
65mA
6
6
4
4
2
2
0
0
2
7
12
17
22
27
32
37
42
47
52
7
12
17
22
27
32
37
42
47
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 27. PSAT vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
Figure 30. PSAT vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
24
22
20
18
16
14
12
10
8
24
22
20
18
16
14
12
10
8
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
6
6
4
4
2
2
0
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
7
12
17
22
27
32
37
42
47
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 28. Low Frequency PSAT vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 31. PSAT vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Rev. 0 | Page 10 of 21
Data Sheet
HMC1126ACEZ
0.65
0.60
0.55
0.50
0.45
0.40
25
130
120
110
100
90
50GHz
46GHz
40GHz
36GHz
30GHz
26GHz
20GHz
16GHz
10GHz
6GHz
P
GAIN
PAE
OUT
20
15
10
5
I
DD
2GHz
0
–10
80
–5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
–5
0
5
10
INPUT POWER AT 85°C (dBm)
INPUT POWER (dBm)
Figure 35. PDISS vs. Input Power at 85°C for Various Frequencies,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 32. POUT, Gain, Power Added Efficiency (PAE), and IDD vs. Input Power at
2 GHz, VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
200
150
100
50
25
20
15
10
5
130
120
110
100
90
P
GAIN
PAE
OUT
I
DD
0
–50
0
80
–10
–5
0
5
10
15
INPUT POWER (dBm)
GATE VOLTAGE (V)
Figure 33. POUT, Gain, PAE, and IDD vs. Input Power at 26 GHz,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 36. Drain Current vs. Gate Voltage,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
25
20
15
10
5
130
32
30
28
26
24
22
20
18
P
GAIN
PAE
OUT
120
110
100
90
I
DD
5.0V
4.0V
3.3V
16
14
12
10
0
–10
80
10
–5
0
5
2
7
12
17
22
27
32
37
42
47
52
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 34. POUT, Gain, PAE, and IDD vs. Input Power at 50 GHz,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 37. OIP3 vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
Rev. 0 | Page 11 of 21
HMC1126ACEZ
Data Sheet
32
30
28
26
24
22
20
18
32
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
16
14
12
10
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 41. OIP3 vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 38. Low Frequency OIP3 vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
80
70
60
50
40
30
20
10
32
30
28
26
24
22
20
18
16
52GHz
50GHz
46GHz
42GHz
38GHz
34GHz
30GHz
26GHz
22GHz
18GHz
14GHz
10GHz
6GHz
2GHz
1.4V
14
1.0V
12
10
–5
0
5
10
2
7
12
17
22
27
32
37
42
47
52
P
PER TONE (dBm)
OUT
FREQUENCY (GHz)
Figure 42. Third-Order Intermodulation (IM3) vs. POUT per Tone at Various
Frequencies, VDD = 3.3 V, IDQ = 85 mA, VGG2 = 1 V
Figure 39. OIP3 vs. Frequency at Various VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
80
52GHz
50GHz
46GHz
42GHz
38GHz
34GHz
30GHz
26GHz
22GHz
18GHz
14GHz
10GHz
6GHz
32
30
28
26
24
22
20
18
16
14
12
10
70
60
50
40
30
20
10
2GHz
85mA
75mA
65mA
–5
0
5
10
2
7
12
17
22
27
32
37
42
47
52
P
PER TONE (dBm)
OUT
FREQUENCY (GHz)
Figure 43. IM3 vs. POUT per Tone at Various Frequencies,
VDD = 4 V, IDQ = 85 mA, VGG2 = 1 V
Figure 40. OIP3 vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
Rev. 0 | Page 12 of 21
Data Sheet
HMC1126ACEZ
80
70
60
50
40
30
20
34
32
30
28
26
24
22
20
18
16
14
12
10
52GHz
50GHz
46GHz
42GHz
38GHz
34GHz
30GHz
26GHz
22GHz
18GHz
14GHz
10GHz
6GHz
2GHz
1.4V
1.0V
10
–5
0
5
10
2
4
6
8
10
12
14
16
18
20
22
24
24
24
P
PER TONE (dBm)
FREQUENCY (GHz)
OUT
Figure 47. OIP2 vs. Frequency at Various VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
Figure 44. IM3 vs. POUT per Tone at Various Frequencies,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
34
32
30
28
26
24
22
20
18
16
14
12
10
34
32
30
28
26
24
22
20
18
16
14
12
10
85mA
75mA
65mA
5.0V
4.0V
3.3V
2
4
6
8
10
12
14
16
18
20
22
2
4
6
8
10
12
14
16
18
20
22
24
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 48. OIP2 vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
Figure 45. OIP2 vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
34
32
30
28
26
24
22
20
18
16
14
12
10
36
34
32
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
2
4
6
8
10
12
14
16
18
20
22
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 49. OIP2 vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 46. Low Frequency OIP2 vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Rev. 0 | Page 13 of 21
HMC1126ACEZ
Data Sheet
12
11
12
11
10
9
5.0V
4.0V
3.3V
85mA
75mA
65mA
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
2
6
10 14 18 22 26 30 34 38 42 46 50
FREQUENCY (GHz)
2
6
10 14 18 22 26 30 34 38 42 46 50
FREQUENCY (GHz)
Figure 50. Noise Figure vs. Frequency at Various VDD Voltages,
IDQ = 85 mA, VGG2 = 1 V
Figure 53. Noise Figure vs. Frequency at Various IDQ Currents,
VDD = 5 V, VGG2 = 1 V
15
12
14
13
12
11
10
9
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
11
10
9
8
7
8
6
7
5
6
5
4
4
3
3
2
2
1
1
0
0.25
0
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2
6
10 14 18 22 26 30 34 38 42 46 50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 51. Low Frequency Noise Figure vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Figure 54. Noise Figure vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
12
0
11
1.4V
1.0V
–10
–20
–30
–40
–50
–60
–70
+85°C
+25°C
–40°C
10
9
8
7
6
5
4
3
2
1
0
2
6
10 14 18 22 26 30 34 38 42 46 50
FREQUENCY (GHz)
2
7
12
17
22
27
32
37
42
47
52
FREQUENCY (GHz)
Figure 52. Noise Figure vs. Frequency at VGG2 Voltages,
VDD = 5 V, IDQ = 85 mA
Figure 55. Reverse Isolation vs. Frequency at Various Temperatures,
VDD = 5 V, IDQ = 85 mA, VGG2 = 1 V
Rev. 0 | Page 14 of 21
Data Sheet
HMC1126ACEZ
THEORY OF OPERATION
V
2
V
DD
GG
The HMC1126ACEZ is a GaAs, pHEMT, low noise amplifier.
The low noise amplifier uses a fundamental cell of two field
effect transistors (FETs), as shown in Figure 56. This
fundamental cell is duplicated a number of times, thereby
increasing the operational bandwidth.
0.1µF
0.1µF
100pF
100pF
RFOUT
The negative VGG1 sets the supply current, and the voltage on
V
GG2 ensures that there are approximately equal dc voltages
GND
RFIN
across the top and bottom FETs. The RFIN and RFOUT pins
are ac-coupled and matched to 50 Ω. VDD is applied through an
integrated choke. The 0.1 μF and 100 pF decoupling capacitors
are integrated. As a result, no external passive components are
required for operation.
V
1
GG
100pF
0.1µF
GND
GND
Figure 56. Simplified Block Diagram
Rev. 0 | Page 15 of 21
HMC1126ACEZ
Data Sheet
APPLICATIONS INFORMATION
Figure 57 shows the basic connections for operating the
HMC1126ACEZ. Because the RFIN and RFOUT pins are
internally ac-coupled, no external ac coupling is required.
Because VDD, VGG1, and VGG2 are internally decoupled, no
external components are required on these pins. Figure 57 shows
the configuration used to characterize and qualify the device.
Power-Up
The following power-up sequencing is recommended:
1. Connect GND to ground.
2. Set VGG1 to −2 V.
3. Set VDD to 5 V.
4. Set VGG2 to 1 V.
5. Increase VGG1 to achieve an IDQ = 85 mA.
6. Apply the RF signal.
See the HMC1126-EVALZ user guide for information on using
the evaluation board.
POWER-UP AND POWER-DOWN SEQUENCING
Power-Down
To avoid damaging the device, careful attention must be paid to
the power-up and power-down sequencing of the RF input, the
gate bias voltages, and the drain bias voltage.
The following power-down sequencing is recommended:
1. Turn off the RF signal.
2. Decrease VGG1 to −2 V to achieve an IDQ = 0 mA.
3. Decrease VGG2 to 0 V.
4. Decrease VDD to 0 V.
5. Increase VGG1 to 0 V.
V
DD
(5V)
1
2
3
18
17
16
15
14
13
GND RFOUT
RFIN
GND
4
5
6
GND
GND
V
1
V
2
GG
GG
(–2V TO 0V)
(1V)
Figure 57. Basic Connections
Rev. 0 | Page 16 of 21
Data Sheet
HMC1126ACEZ
The target drain current must first be determined and set. This
current must be set based on the maximum drain current
required during operation, including when the device is
generating the maximum expected output power. In this case, a
target drain current of 120 mA was chosen. Set the target value
by attaching a 2.05 kΩ ground referenced resistor to the ISENSE
pin (Pin 25) on the HMC920LP5E.
BIASING THE HMC1126ACEZ WITH THE
HMC920LP5E
The HMC920LP5E (see Figure 58) is designed to provide active
bias control for enhancement mode and depletion mode
amplifiers, such as the HMC1126ACEZ. The HMC920LP5E
measures and regulates drain current to compensate for
temperature changes and part to part variations.
To ensure adequate headroom, the supply voltage for the
HMC920LP5E must be set higher than the target drain voltage to
the HMC1126ACEZ (5 V). Accordingly, VDD1 and VDD2 on the
HMC920LP5E are set to 5.3 V.
VDD1
VDD1
TRGOUT
VDRAIN
VDRAIN
VGATE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DRAIN
LDO
The voltage on the LDOCC pin (Pin 29) on the HMC920LP5E
drives the VDRAIN pins which in turn drive the V
DD pin of the
DIGITAL
LDO
HMC1126ACEZ. Because the LDOCC output is connected to the
VDRAIN output through an internal metal-oxide semiconductor
field effect transistor (MOSFET) switch with an on resistance of
0.5 Ω, the LDOCC voltage (VLDOCC) must be set slightly higher
than the target drain voltage to the HMC1126ACEZ. To
determine the required LDOCC voltage, use the following
equation:
VDIG
GATE
CONTROL
VDIGFB
PORCAP
BGCAP
EN
CONTROL
BLOCK
VGATEFB
VNEGIN
VNEGFB
AGND
BANDGAP
NEGATIVE VOLTAGE
REGULATOR
V
LDOCC = VDRAIN + IDRAIN × 0.5
CURALM
HMC920LP5E
Therefore, VLDOCC = 5 V+ (0.12 × 0.5) = 5.06 V.
PACKAGE
BASE
To set VLDOCC to 5.06 V, use the following equation with R5 set
to 10 kΩ:
R10 = (R5/2) × (VLDOCC − 2)
Figure 58. Functional Diagram of the HMC920LP5E
Therefore, R10 = (10000/2) × (5.06 – 2) = 15.3 kΩ.
Additionally, the HMC920LP5E properly sequences gate and drain
voltages to ensure safe on and off operation and offers circuit
self protection in the event of a short circuit. The active bias
controller contains an internal charge pump that generates the
negative voltage needed to drive the VGG1 pin on the
HMC1126ACEZ. Alternatively, an external negative voltage can be
provided.
Setting VGG1 and VGG
2
The VGG2 fixed bias voltage is set to 1 V using a resistor divider that
is derived from VDD1 and VDD2 on the HMC920LP5E. Because
the current into the VGG2 pin is low (<1 mA), large resistor
values in the kΩ range can be used to set the VGG2 voltage and save
on overall current usage.
The recommended minimum voltage for VGG1 into the
HMC1126ACEZ is −2 V, which is also the default value for the
VNEGIN pin on the HMC920LP5E. As a result, there is no need to
adjust the VNEGIN and VGATE voltages.
For more information regarding the use of the HMC920LP5E,
refer to the HMC920LP5E data sheet and the AN-1363
Application Note.
Application Circuit Setup
Refer to the HMC920LP5E data sheet for the detailed schematic.
Figure 59 shows the application circuit for bias control of the
HMC1126ACEZ using the HMC920LP5E. The current through
the HMC920LP5E is measured, and the VGATE output voltage
serves until the setpoint drain current is achieved. The various
external components around the HMC920LP5E are set as follows
in this section.
Rev. 0 | Page 17 of 21
HMC1126ACEZ
Data Sheet
V
LDOCC
5.06V
R5
10kΩ
R10
15.3kΩ
+
C9
10µF
R16
1.69kΩ
C24
100pF
R15
3.32kΩ
R14
1kΩ
R4
2.05Ω
V
DD
V
DD
5.3V
VDD1
TRGOUT
VDRAIN
VDRAIN
VGATE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
1
2
3
4
5
6
18
17
16
15
14
13
VDRAIN = 5V
IDRAIN = 120mA
C6
4.7µF
C19
22µF
VDD1
C22
0.1µF
RFOUT
VDIG
HMC1126ACEZ
RFIN
VDIGFB
PORCAP
BGCAP
EN
C21
10µF
HMC920LP5E
VGATEFB
VNEGIN
VNEGFB
AGND
V
1
V
2
GG
GG
CURALM
R2
4kΩ
R1
1kΩ
C6
4.7µF
Figure 59. Application Circuit Using the HMC920LP5E with the HMC1126ACEZ (Additional Circuitry Omitted for Clarity)
VGATE initially drops to −2 V, and VDRAIN rises to 5 V. Then,
VGATE and VGG1 increase until IDRAIN equals 120 mA. The
closed control loop then regulates IDRAIN to 120 mA. When the
EN pin goes low, VGATE and VGG1 drop back to −2 V and
VDRAIN drops to 0 V.
HMC920LP5E Bias Sequence
When the HMC920LP5E bias control circuit is set up, the
HMC1126ACEZ bias can be toggled on and off by applying 3.5 V
(high) or 0 V (low) to the EN pin of the HMC920LP5E. If EN is
left floating, the pin floats high. When EN is set to 3.5 V,
Rev. 0 | Page 18 of 21
Data Sheet
HMC1126ACEZ
The current and temperature limit of IDD under the constant
current operation is usually set by the thermal limitations
detailed in the Absolute Maximum Ratings section (see the
continuous power dissipation specification in Table 5).
Increasing IDD does not indefinitely increase OP1dB. Therefore,
consider the trade-off between the power dissipation and OP1dB
performance when using a constant drain current bias.
CONSTANT DRAIN CURRENT BIASING vs.
CONSTANT GATE VOLTAGE BIASING
Voltage Biasing
The HMC920LP5E uses closed loop feedback to continuously
adjust VGATE to maintain a constant drain current bias over the
dc supply variation, temperature, and part to part variations.
Constant drain current bias is an ideal method for reducing
time in calibration procedures and maintaining consistent
performance over time.
The performance of the constant drain current circuit is
summarized in Figure 60 to Figure 67. These figures include
comparisons with a constant gate voltage bias. Note that Figure 60
indicates a current consumption of 140 mA, which includes the
complete current consumption of the circuit, that is, 120 mA drain
current for the HMC1126ACEZ and an additional 20 mA of
quiescent current in the HMC920LP5E. Using 140 mA as the
current consumption also results in lower PAE compared to a
constant gate voltage bias.
In comparison to a constant gate voltage bias, where the current
increases dynamically when the RF power is applied, a constant
drain current bias results in constant power consumption.
The OP1dB performance for the constant drain current bias
can be varied by varying the bias setpoint. By increasing the bias
current, OP1dB increases, as shown in Figure 66. The trade-off
with a constant drain current is that this higher drain current is
present for all RF input and output power levels.
180
14
CONSTANT DRAIN CURRENT BIAS
CONSTANT GATE VOLTAGE BIAS
170
CONSTANT DRAIN CURRENT BIAS
CONSTANT GATE VOLTAGE BIAS
12
160
150
140
130
120
110
100
90
10
8
6
4
2
80
–10
0
–10
–5
0
5
10
15
–5
0
5
10
15
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 60. IDD vs. Input Power, VDD = 5 V, Frequency = 26 GHz, Constant Drain
Current Bias (IDD = 140 mA) and Constant Gate Voltage Bias
Figure 62. PAE vs. Input Power, VDD = 5 V, Frequency = 26 GHz,
Constant Drain Current Bias (IDD = 140 mA) and Constant Gate Voltage Bias
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
CONSTANT DRAIN CURRENT BIAS
CONSTANT GATE VOLTAGE BIAS
6
6
4
2
0
CONSTANT DRAIN CURRENT BIAS
CONSTANT GATE VOLTAGE BIAS
4
2
0
–10
–5
0
5
10
15
2
6
10
14
18
22
26
30
34
38
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 61. Output Power vs. Input Power, VDD = 5 V, Frequency = 26 GHz,
Constant Drain Current Bias (IDD = 140 mA) and Constant Gate Voltage Bias
Figure 63. OP1dB vs. Frequency, VDD =5 V, Constant Drain Current Bias (IDD
140 mA) and Constant Gate Voltage Bias
=
Rev. 0 | Page 19 of 21
HMC1126ACEZ
Data Sheet
22
20
18
16
14
12
10
22
20
18
16
14
12
10
8
+85°C
+25°C
–40°C
8
6
4
2
0
160mA
140mA
130mA
120mA
6
4
2
0
2
6
10
14
18
22
26
30
34
38
2
6
10
14
18
22
26
30
34
38
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 64. OP1dB vs. Frequency for Various Temperatures, Data Measured
with Constant Drain Current
Figure 66. OP1dB vs. Frequency for Various Drain Currents,
Data Measured with Constant Drain Current Bias
24
22
20
18
16
14
12
24
22
20
18
16
14
12
10
8
10
+85°C
+25°C
8
160mA
140mA
130mA
120mA
–40°C
6
6
4
2
0
4
2
0
2
6
10
14
18
22
26
30
34
38
2
6
10
14
18
22
26
30
34
38
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 65. PSAT vs. Frequency for Various Temperatures,
Data Measured with Constant Drain Current
Figure 67. PSAT vs. Frequency for Various Drain Currents,
Data Measured with Constant Drain Current Bias
Rev. 0 | Page 20 of 21
Data Sheet
HMC1126ACEZ
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.35
0.30
0.25
0.10
BSC
PIN 1
CORNER
PIN 1 CORNER
OR
INDICAT
19
24
18
1
3.25
REF
2.90 BSC
SQ
13
6
7
12
0.65
BSC
0.50
0.45
0.40
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.18
0.15
0.12
Ø
1.70
1.60
1.50
1.35 REF
(Vent Hole)
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.29
0.25
0.21
SEATING
PLANE
SECTION OF THIS DATA SHEET.
Figure 68. 24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
5.00 mm × 5.00 mm Body and 1.60 mm Package Height
(CE-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
MSL
Model1, 2
Temperature Range Rating3
Package Description
Package Option
HMC1126ACEZ
HMC1126ACEZ-R7 −40°C to +85°C
HMC1126-EVALZ
−40°C to +85°C
MSL3
MSL3
24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] CE-24-2
24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] CE-24-2
Evaluation Board
1 Z = RoHS Compliant Part.
2 When ordering the evaluation board only, reference the model number, HMC1126-EVALZ.
3 See the Absolute Maximum Ratings section for additional information.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D25048-11/21(0)
Rev. 0 | Page 21 of 21
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