HMC7044LP10BE_技术文档

High Performance, 3.2 GHz, 14-Output

Jitter Attenuator with JESD204B

Data Sheet

HMC7044

FEATURES

APPLICATIONS

Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at

2457.6 MHz

Noise floor: −156 dBc/Hz at 2457.6 MHz

JESD204B clock generation

Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)

Data converter clocking

Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output

Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)

from PLL2

Microwave baseband cards

Phase array reference distribution

GENERAL DESCRIPTION

Maximum CLKOUTx/

CLKOUTx

and SCLKOUTx/

SCLKOUTx

The HMC7044 is a high performance, dual-loop, integer-N

jitter attenuator capable of performing reference selection and

generation of ultralow phase noise frequencies for high speed data

converters with either parallel or serial (JESD204B type) interfaces.

The HMC7044 features two integer mode PLLs and overlapping

on-chip VCOs that are SPI-selectable with wide tuning ranges

around 2.5 GHz and 3 GHz, respectively. The device is designed

to meet the requirements of GSM and LTE base station designs,

and offers a wide range of clock management and distribution

features to simplify baseband and radio card clock tree designs.

The HMC7044 provides 14 low noise and configurable outputs

to offer flexibility in interfacing with many different compo-

nents including data converters, field-programmable gate arrays

(FPGAs), and mixer local oscillators (LOs).

frequency up to 3200 MHz

JESD204B-compatible system reference (SYSREF) pulses

25 ps analog, and ½ VCO cycle digital delay independently

programmable on each of 14 clock output channels

SPI-programmable phase noise vs. power consumption

SYSREF valid interrupt to simplify JESD204B synchronization

Narrow-band, dual core VCOs

Up to 2 buffered voltage controlled oscillator (VCXO) outputs

Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes

Frequency holdover mode to maintain output frequency

Loss of signal (LOS) detection and hitless reference switching

4× GPIOs alarms/status indicators to determine the health of

the system

External VCO input to support up to 6000 MHz

On-board regulators for excellent PSRR

68-lead, 10 mm × 10 mm LFCSP package

The DCLK and SYSREF clock outputs of the HMC7044 can be

configured to support signaling standards, such as CML, LVDS,

LVPECL, and LVCMOS, and different bias settings to offset

varying board insertion losses.

FUNCTIONAL BLOCK DIAGRAM

OSCIN

CPOUT1 OSCIN

CPOUT2 OSCOUT1 OSCOUT1

CLKOUT0

SCLKOUT1

CLKOUT2

SCLKOUT3

CLKIN0/RFSYNCIN

CLKIN1/FIN

÷

CLKIN1/FIN

PLL1

PLL2

CLKIN2/OSCOUT0

CLKIN3

CLKOUT12

SCLKOUT13

÷

SYSREF

CONTROL

SYNC

14-CLOCK

DISTRIBUTION

SPI

CONTROL

INTERFACE

SDATA

SLEN SCLK

Figure 1.

Rev. B

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HMC7044* PRODUCT PAGE QUICK LINKS

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DESIGN RESOURCES

• HMC7044 Material Declaration

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• HMC7044 Evaluation Kit

• Symbols and Footprints

DOCUMENTATION

Data Sheet

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Attenuator with JESD204B Data Sheet

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• UG-826: Evaluating the HMC7044 Dual Loop Clock Jitter

Cleaner

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TOOLS AND SIMULATIONS

• HMC7044 IBIS Model

DOCUMENT FEEDBACK

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REFERENCE MATERIALS

Press

• Analog Devices Clock Jitter Attenuator Optimizes

JESD204B Serial Interface Functionality in Base Station

Designs

Technical Articles

• Synchronizing Sample Clocks of a Data Converter Array

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HMC7044

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 23

Detailed Block Diagram ............................................................ 24

Dual PLL Overview.................................................................... 25

Component Blocks—Input PLL (PLL1).................................. 25

Component Blocks—Output PLL (PLL2) .............................. 30

Clock Output Network .............................................................. 31

Reference Buffer Details............................................................ 38

Typical Programming Sequence............................................... 38

Power Supply Considerations................................................... 39

SeriaL Control Port ........................................................................ 42

Serial Port Interface (SPI) Control........................................... 42

Applications Information .............................................................. 43

PLL1 Noise Calculations ........................................................... 43

PLL2 Noise Calculations ........................................................... 43

Phase Noise Floor and Jitter...................................................... 43

Control Registers............................................................................ 44

Control Register Map ................................................................ 44

Control Register Map Bit Descriptions ................................... 52

Evaluation PCB Schematic............................................................ 69

Evaluation PCB........................................................................... 69

Outline Dimensions....................................................................... 71

Ordering Guide .......................................................................... 71

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Table of Contents .............................................................................. 2

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Conditions..................................................................................... 3

Supply Current.............................................................................. 3

Digital Input/Output (I/O) Electrical Specifications............... 4

PLL1 Characteristics .................................................................... 5

PLL2 Characteristics .................................................................... 7

VCO Characteristics .................................................................... 8

Clock Output Distribution Characteristics............................... 9

Spur Characteristics ................................................................... 10

Noise and Jitter Characteristics ................................................ 10

Clock Output Driver Characteristics....................................... 11

Absolute Maximum Ratings.......................................................... 13

ESD Caution................................................................................ 13

Pin Configuration and Function Descriptions........................... 14

Typical Performance Characteristics ........................................... 17

Typical Application Circuits.......................................................... 21

Terminology .................................................................................... 22

REVISION HISTORY

11/2016—Rev. A to Rev. B

5/2016—Rev. 0 to Rev. A

Changes to Table 1 and Endnote 4, Table 2................................... 3

Changes to Reliable Signal Swing Parameter, Table 4.................. 5

Change to PLL2 VCXO Input Parameter, Table 5........................ 7

Changes to Table 7 ............................................................................ 9

Added Figure 13; Renumbered Sequentially .............................. 18

Added Figure 20.............................................................................. 19

Added Figure 21, Figure 22, and Figure 23................................. 20

Changes to Figure 34...................................................................... 21

Changes to Table 15 and Table 17 ................................................ 34

Changes to Figure 47...................................................................... 37

Changes to Table 23........................................................................ 41

Changes to Table 25........................................................................ 46

Changes to Table 49........................................................................ 57

Change to Table 75 ......................................................................... 68

Changes to Table 3.............................................................................4

Changes to Current Range (I_CP2) Parameter, Table 5....................8

Changes to Table 9.......................................................................... 11

Changes to Table 10 ....................................................................... 13

Changes to LDOBYP5 Pin Description ...................................... 15

Changes to Figure 13...................................................................... 19

Changes to Figure 30...................................................................... 25

Changes to Evaluation PCB Section ............................................ 69

Added Figure 46; Renumbered Sequentially .............................. 69

Added Figure 50 ............................................................................. 71

Updated Outline Dimensions....................................................... 71

9/2015—Revision 0: Initial Version

Rev. B | Page 2 of 72

Data Sheet

HMC7044

SPECIFICATIONS

Unless otherwise noted, f_VCXO= 122.88 MHz single-ended; CLKIN0/

, CLKIN1/ , CLKIN2/ , and CLKIN3/

CLKIN0 CLKIN1 CLKIN2 CLKIN3

differential at 122.88 MHz; f_VCO= 2949.12 MHz; doubler is on; typical value is given for V_CC= 3.3 V; and T_A= 25°C. Minimum and maximum

values are given over the full V_CCand T_A(−40°C to +85°C) variation, as listed in Table 1. Note that multifunction pins, such as

CLKIN0/RFSYNCIN, are referred to either by the entire pin name or by a single function of the pin, for example, CLKIN0, when only

that function is relevant.

CONDITIONS

Table 1.

Parameter

Min

Typ Max

Unit Test Conditions/Comments

SUPPLY VOLTAGE, V_CC

VCC1_VCO

VCC2_OUT

3.135 3.3

3.465

V

3.3 V 5%, supply voltage for VCO and VCO distribution

3.3 V 5%, supply voltage for Output Channel 2 and Output

Channel 3

VCC3_SYSREF

VCC4_OUT

3.135 3.3

3.465

V

3.3 V 5%, supply voltage for common SYSREF divider

3.3 V 5%, supply voltage for Output Channel 4, Output

Channel 5, Output Channel 6, Output Channel 7

VCC5_PLL1

VCC6_OSCOUT

VCC7_PLL2

VCC8_OUT

3.135 3.3

3.465

V

3.3 V 5%, supply voltage for the LDO used in PLL1

3.3 V 5%, supply voltage for oscillator output path

3.3 V 5%, supply voltage for the LDO used in PLL2

3.3 V 5%, supply voltage for Output Channel 8, Output

Channel 9, Output Channel 10, and Output Channel 11

VCC9_OUT

3.135 3.3

3.465

V

3.3 V 5%, supply voltage for Output Channel 0, Output

Channel 1, Output Channel 12, and Output Channel 13

TEMPERATURE

Ambient Temperature Range, T_A

−40

+25 +85

°C

SUPPLY CURRENT

For detailed test conditions, see Table 22 and Table 23.

Table 2.

Parameter^{1, 2}

CURRENT CONSUMPTION³

VCC1_VCO

Min Typ

Max Unit Test Conditions/Comments

157

65

12

225

250

37

mA

VCC2_OUT⁴

Typical value is given at T_A= 25°C with two LVDS clocks at divide by 8

VCC3_SYSREF

VCC4_OUT⁴

78

500

Typical value is given at 25°C with two LVPECL high performance clocks,

fundamental frequency of internal VCO (f_O), 2 SYSREF clocks (off)

VCC5_PLL1

VCC6_OSCOUT

VCC7_PLL2

VCC8_OUT⁴

39

0

46

124

125

80

mA

500

Typical value is given at 25°C with two LVPECL high performance clocks at

divide by 2, 2 SYSREF clocks (off)

Typical value is given at 25°C with two LVDS clocks at divide by 8, 2 SYSREF

clocks (off)

VCC9_OUT⁴

65

500

mA

Total Current

586

¹Maximum values are guaranteed by design and characterization.

²Currents include LVPECL termination currents.

³Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary

synchronization events.

⁴Typical specification applies to a normal usage profile (Profile 1 in Table 23), where PLL1 and PLL2 are locked, but very low duty cycle currents (sync events) and some

optional features are disabled. This specification assumes output configurations as described in the test conditions/comments column.

Rev. B | Page 3 of 72

HMC7044

Data Sheet

DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS

Table 3.

Parameter

Min Typ

Max Unit Test Conditions/Comments

DIGITAL INPUT SIGNALS (RESET, SYNC, SLEN, SCLK)

Safe Input Voltage Range¹

Input Load

−0.1

0.3

+3.6

V

pF

Input Voltage

Input Logic High (V_IH)

Input Logic Low (V_IL)

SPI Bus Frequency

1.2

0

V_CC

0.5

10

V

MHz

DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS

INPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)

Safe Input Voltage Range¹

Input Capacitance

Input Resistance

−0.1

0.4

+3.6

V

pF

Ω

50G

Input Voltage

Input Logic High (V_IH)

Input Logic Low (V_IL)

Input Hysteresis

1.22

0

V_CC

0.24

V

0.2

Occurs around 0.85 V

Does not include t_DGPO

GPIO1 TO GPIO4 ALARM MUXING/DELAY

Delay from Internal Alarm/Signal to General-Purpose

Output (GPO) Driver

2

ns

DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS

OUTPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)

CMOS MODE

Logic 1 Level

Logic 0 Level

1.6

1.9

0

2.2

0.1

V

Output Drive Resistance (R_DRIVE

Output Driver Delay (t_DGPO

)

50

1.5 + 42 ×

C_LOAD

Ω

ns

)

Approximately 1.5 ns + 0.69 × R_DRIVE× C_LOAD

(C_LOADin nF)

Maximum Supported DC Current¹

OPEN-DRAIN MODE¹

0.6

mA

External 1 kΩ pull-up resistor

Logic 1 Level

3.6

V

3.6 V maximum permitted; specifications

set by external supply

Against a 1 kΩ external pull-up resistor to

3.3 V

Logic 0 Level

0.13

60

0.28

Pull-Down Impedance

Ω

Maximum Supported Sink Current

5

mA

¹Guaranteed by design and characterization.

Rev. B | Page 4 of 72

Data Sheet

HMC7044

PLL1 CHARACTERISTICS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PLL1 REFERENCE INPUTS

(CLKIN0/CLKIN0, CLKIN1/CLKIN1,

CLKIN2/CLKIN2, CLKIN3/CLKIN3)

Reliable Signal Swing

Differential

0.375

0.4

1.4

2.4

V p-p

V

Differential, keep signal at reference input pin

<2.8 V, measured at 800 MHz

<250 MHz; keep signal at reference input pin

<2.8 V

If user supplied, on-chip V_CMis approximately

2.1 V

Single-Ended¹

Common-Mode Range

Input Impedance

Return Loss

100 to 2000

−12

Ω

dB

User selectable; differential

When terminated with 100 Ω differentially

PLL1 REFERENCE DIVIDER

8-Bit Lowest Common Multiple

(LCM) Dividers

16-Bit R Divider (R1)

1

255

65,535

PLL1 FEEDBACK DIVIDER

16-Bit N Divider (N1)

1

65,535

800

PLL1 FREQUENCY LIMITATIONS

PLL1 REF Input Frequency (f_REF

)

0.00015

MHz

Minimum specification set by Phase Detector 1

(PD1) low limit

Digital LOS/LCM Frequency (f_LCM

)

0.00015

123

50

MHz

Typically run at about 38.4 MHz

Minimum specification = VCXO minimum

frequency ÷ 65,535; 9.76 MHz typical

PD1 Frequency (f_PD1

PLL1 CHARGE PUMP

)

Charge Pump Current Range (I_CP1

)

120 to 1920

15

μA

%

I_CP1from 0 to 15, VCXO control voltage (V_TUNE) =

1.4 V

V_TUNE= 1.4 V

I_CP1Variation over Process Voltage

Temperature (PVT)

Source/Sink Current Mismatch

Charge Pump Current Step Size

Charge Pump Compliance Range¹

2

120

0.4 to 2.5

0.1 to 2.7

%

μA

V

Source/sink mismatch at 1.4 V

I_CPvariation less than 10%

Maintain lock in test environment

V

PLL1 NOISE PROFILE¹

Floor Figure of Merit (FOM)

Flicker FOM

Flicker Noise

Noise Floor

−222

−252

dBc/Hz

Normalized to 1 Hz

At f_OUT, f_OFFSET

Determined by formula²

Determined by formula³

Determined by formula⁴

At f_OUT, f_PD1

Total Phase Noise (Unfiltered)

PLL1 BANDWIDTH AND

ACQUISITION TIMES¹

Supported Loop Bandwidths

f_LCM/2²⁵

f_PD1/10

Hz

Typically PLL1 low BW is set by the application

and ranges between 5 Hz and 2 kHz

(PLL1_BW)⁵

PLL1 Slew Time⁶

N1/

f_{DELTA_VCXO}

sec

ns

N1 = 10 (typical) and f_{DELTA_VCXO}= 10 kHz (typical)

results in 1 ms of slew time

When VCXO has stopped slewing to steady

state (within 5°)

PLL1 Linear Acquisition Time

5/PLL1_BW

2.9

PLL1 Phase Error at PD1

Invalidates Lock

PLL1 Lock Detect Timer Period

4 to 2²⁶

t_LCM

User-selectable low phase error counts to

declare lock

7

(t_LKD

)

Rev. B | Page 5 of 72

HMC7044

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PLL1 BEHAVIOR ON REFERENCE

FAILURE¹

LOS Assertion Delay⁷

Erroneously Active I_CP1Time on

Reference Failure⁸

2 + t_DGPO

0

3 + t_DGPO

8

t_LCM

ns

From missing signal edge to alarm on GPO

Temporary Frequency Glitch Due

to Reference Failure

Integrated Frequency Error Due to

Reference Failure

Signal Valid Time to Clear LOS⁹

0.03

ppm

t_LOSVAL

I_CP1= 1 mA, C12 = 4.6 nF, Crystek CVPD-952

VCXO

I_CP1= 1 mA, C13 = 1 μF, Crystek CVPD-952 VCXO

0.016

2

3

PLL1 V_TUNELEAKAGE SOURCES

Charge Pump Tristate Leakage

Current

0.2

nA

Board Level XTAL Tune Input Port

Board Level Loop Filter

Components

0.5

2

nA

Crystek CVPD-952 VCXO

C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ, C15 =

unpopulated

HOLDOVER CHARACTERISTICS

V_TUNEDrift Over 1 sec in Tristate

Mode

Holdover

Analog-to-Digital Converter

(ADC)/Digital-to-Analog

Converter (DAC) Resolution

2

mV

C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ,

CVPD-950 VCXO

19

7-bit, monotonic, no missing code

ADC/DAC Code 0 Voltage

ADC/DAC Code 127 Voltage

DAC Temperature Stability

ADC/DAC Integral Nonlinearity

(INL)

Holdoff Timer Period^{1, 10}

0.28

2.71

0.07

−0.11

V

mV/°C

LSBs

At maximum code

Worst case across codes

1

2²⁶

t_LCM

HOLDOVER EXIT—INITIAL PHASE

OFFSETS¹

Exit Criteria = Wait for Low Phase

Error

The phase offset to make up after a transition

from holdover to acquisition when using this

feature

Exit Action = None

Exit Criteria = Any¹¹

4

ns

Exit Action = Reset Dividers

1

2

t_VCXO

Assumes N2 > 3 and dividers are reset upon

exit; note that VCXO lags at start; value applies

as the starting phase error if DAC assisted

release is used

Exit Action = None

N1

t_VCXO

Dividers are not reset upon exit

HOLDOVER EXIT CHARACTERISTICS^{1, 12}

DAC Assisted Release Period per

1/2

1/16

9

t_LKD

Based on lock detect timer setpoint

Step (t_DACASSIST

)

DAC Assisted Release Time

t_DACASSIST

Time from decision to leave holdover until in

fully natural acquisition; assumes no

interruption by LOS or user

Delay of Exit Criteria¹³= Wait for

Low Phase Error¹⁴

N1/f_{ERR_VCXO}sec

Rev. B | Page 6 of 72

Data Sheet

HMC7044

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HOLDOVER EXIT—FREQUENCY

TRANSIENTS vs. MODE

Peak Frequency Transient

DAC Assisted Release

2

ppm

Only available if using DAC-based holdover

¹Guaranteed by design and characterization.

²See the PLL1 Noise Calculations section for more information on how to calculate the flicker noise for PLL1.

³See the PLL1 Noise Calculations section for more information on how to calculate the noise floor for PLL1.

⁴See the PLL1 Noise Calculations section for more information on how to calculate the total phase noise (unfiltered) for PLL1.

⁵Set by external components. Set the lock detect thresholds (PLL1 Lock Detect Timer[4:0] in Register 0x0028) appropriately in the SPI.

⁶Depends on initial phase offset (worst case is proportional to N1) and VCXO excess tuning range available over the target (f_{DELTA_VCXO}). For PFD rates typical of PLL1,

cycle slipping is normally insignificant.

⁷t_LCMis the least common multiple (LCM) of PLL1 clock input frequencies. The specification is given in multiples of t_LCM

.

⁸If LOS triggers before the PFD edge is normally detected (more likely with high R1 values), the charge pump is more likely to disable before the next invalid

comparison occurs. Otherwise, the fast tristate circuit disables the charge pump after about 4 ns (8 ns worst case) of phase error.

⁹t_LOSVALis a register value that is programmable from 1, 2, 4, …, 64 t_LCM

.

¹⁰If the holdoff timer is used, the finite state machine (FSM) stays in holdover after LOS of the active reference before switching clocks, giving the original clock a chance

to return.

11

t

is the VCXO clock period.

VCXO

¹²See the PLL1 Holdover Exit section.

¹³The time required for the phases to intersect is inversely proportional to the holdover frequency error. Note that the frequency error during holdover is expected to

be much smaller than is available from the tuning range of the VCXO.

14

f

is the error frequency of the VCXO.

ERR_VCXO

PLL2 CHARACTERISTICS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PLL2 VCXO INPUT

Recommended Swing

Differential

Single-Ended (<250 MHz)¹

Common-Mode Range

VCXO Input Slew Rate

0.2

1.6

300

1.4

2.4

V p-p

V

Differential, keep signal at OSCIN and OSCIN pins < 2.8 V

Keep signal at OSCIN and OSCIN pins < 2.8 V

2.1

If user supplied, on-chip V_CMis approximately 2.1 V

Slew rates as low as 100 mV/ns are functional, but can

degrade the phase noise plateau by about 3 dB

mV/ns

Input Capacitance

Differential Input Resistance

Return Loss

1.5

100 to 1000

−12

pF

Ω

dB

Per side; 3 pF differential

User selectable

When terminated with 100 Ω differential

PLL2 EXTERNAL VCO INPUT

Recommended Input

Power, AC-Coupled

Differential

−6

6

dBm

dB

Single-Ended¹

Return Loss

External VCO Frequency¹

−12

2.1

When terminated with 100 Ω differential

Fundamental mode; if < 1 GHz, set the low frequency

external VCO path bit (Register 0x0064, Bit 0)

400

3200

MHz

400

1.6

6000

2.2

MHz

V

Using external VCO ÷ 2

Common-Mode Range¹

PLL2 DIVIDERS

12-Bit Reference Divider

Range (R2)

16-Bit Feedback Divider

Range (N2)

1

8

4095

65,535

PLL2 FREQUENCY LIMITATIONS

VCXO Frequency (f_VCXO

VCXO Duty Cycle

Using Doubler¹

)

10

40

500

60

MHz

%

122.88 MHz or 155 MHz are typical

Distortion can lead to a spur at f_PD/2 offset, note that

minimum pulse width > 3 ns

Rev. B | Page 7 of 72

HMC7044

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Reference Doubler Input

Frequency

10

175

MHz

R2 Input Frequency

PD2 Frequency (f_PD2

10

0.00015

500

250

MHz

)

Recommended at high end of the range for best phase

noise; typically 122.88 MHz × 2

PLL2 CHARGE PUMP

Current Range (I_CP2

I_CP2Variation over PVT

Source/Sink Current

Mismatch

)

160 to 2560

25

2

μA

%

I_CP2setting from 0 to 15 with 160 μA step size, V_TUNE= 1.4 V

V_TUNE= 1.4 V

Source/sink mismatch at 1.4 V

Current Step Size

Compliance Range

PLL2 NOISE PROFILE

Floor FOM

160

0.3 to 2.45

μA

V

I_CPvariation less than 10%

−232

−266

3

dBc/Hz Normalized to 1 Hz

dB

Flicker FOM

FOM Variation vs. PVT

FOM Degradation

PLL2 Flicker Noise

PLL2 Noise Floor

PLL2 Total Phase Noise

(Unfiltered)

3

dB

At minimum VCXO slew rate

Determined by formula²

Determined by formula³

Determined by formula⁴

dBc/Hz At f_OUT, f_OFFSET

dBc/Hz At f_OUT, f_PD2

dBc/Hz

PLL2 BANDWIDTH AND

ACQUISITION TIMES

Supported Loop

Bandwidths (PLL2_BW)

VCO Automatic Gain

Control (AGC) Settling

Time¹

VCO Calibration Time⁵

10 to 700

kHz

ms

Set by external components

10

20

Time from power-up of VCO before initiating calibration;

this applies to the 100 nF/1 μF configuration of external

decoupling capacitors on the VCO supply network

N2 from 8 to 31

N2 from 32 to 256

N2 from 256 to 4095

N2 > 4095

Maintains lock from any temperature to any temperature

2694

779

214

139

t_PD2

°C

Temperature Range

Postcalibration¹

−40

+85

PLL2 Linear Acquisition

Time

PLL2 Lock Detect Timer

Period⁵

5/PLL2_BW

512

sec

t_PD2

After VCXO has stopped slewing to steady state

Low phase error counts to declare lock

¹Guaranteed by design and characterization.

²See the PLL2 Noise Calculations section for more information on how to calculate the flicker noise for PLL2.

³See the PLL2 Noise Calculations section for more information on how to calculate the noise floor for PLL2.

⁴See the PLL2 Noise Calculations section for more information on how to calculate the total phase noise (unfiltered) for PLL2.

⁵t_PD2is the period of Phase Detector 2.

VCO CHARACTERISTICS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE CONTROLLED OSCILLATOR (VCO)

Frequency Tuning Range, On-Board VCOs¹2150

2880

3550

3200

MHz

MHz/V

Low VCO typical coverage

High VCO typical coverage

Guaranteed frequency coverage²

Low frequency VCO at 2457.6 MHz

High frequency VCO at 2949.12 MHz

2650

2400

Tuning Sensitivity

38 to 44

35 to 40

Rev. B | Page 8 of 72

Data Sheet

HMC7044

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OPEN-LOOP VCO PHASE NOISE

f_OUT= 2457.6 MHz

f_OFFSET= 100 kHz

−109

dBc/Hz

High performance mode, does not include

floor contribution due to output network

f_OFFSET= 800 kHz

f_OFFSET= 1 MHz

f_OFFSET= 10 MHz

Normalized Phase Noise Variation vs.

Frequency

−134

−136

−156

2

dBc/Hz

dB

Sweep across both VCOs, all bands;

normalize to 2457.6 MHz

Phase Noise Variation vs. Temperature

Phase Noise Degradation in Low

Performance Mode

2

dB

¹Guaranteed by design and characterization.

²Although the device covers this range without any gaps, for frequencies between ~2700 Hz and 2900 Hz, using a different VCO core to synthesize the frequency can

be required as process parameters shift. Features are built into the HMC7044 to determine which core is selected for a given frequency that can fall in this range, but it

can require software to configure these circuits appropriately.

CLOCK OUTPUT DISTRIBUTION CHARACTERISTICS

Table 7.

Parameter

Min Typ

Max Unit

Test Conditions/Comments

CLOCK OUTPUT SKEW

CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx

Skew within One Clock Output Pair

Any CLKOUTx/CLKOUTx to Any

SCLKOUTx/SCLKOUTx

15

30

|ps|

Same pair, same type termination and

configuration

Any pair, same type termination and configuration

CLOCK OUTPUT DIVIDER

12-Bit Divider Range

1

4094

1, 3, 5, and all even numbers up to 4094

SYSREF CLOCK OUTPUT DIVIDER

12-Bit Divider Range

1, 3, 5 and all even numbers up to 4094; pulse

generator behavior is only supported for divide

ratios ≥ 32

CLOCK OUTPUT ANALOG FINE DELAY

Analog Fine Delay

Adjustment Range¹

Resolution

Maximum Analog Fine Delay Frequency¹

135

25

670

17

ps

MHz

24 delay steps, f_CLKOUT= 983.04 MHz

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

3200

CLOCK OUTPUT COARSE DELAY (FLIP FLOP

BASED)

Coarse Delay Adjustment Range

0

½ VCO

period

ps

17 delay steps in ½ VCO period

f_VCO= 2949.12 MHz

Coarse Delay Resolution

Maximum Frequency Coarse Delay¹

CLOCK OUTPUT COARSE DELAY (SLIP BASED)

Coarse Delay

169.54

3200

MHz

Adjustment Range

Resolution

Maximum Frequency Coarse Delay

1 to ∞

339.08

1600

VCO period

ps

MHz

f_VCO= 2949.12 MHz

¹Guaranteed by design and characterization.

Rev. B | Page 9 of 72

HMC7044

Data Sheet

SPUR CHARACTERISTICS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE SPUR PERFORMANCE

At 122.88 MHz and Its Harmonics

−70

dBc

NOISE AND JITTER CHARACTERISTICS

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOSED-LOOP PHASE NOISE—WIDE LOOP FILTER

SSB Phase Noise

For best integrated noise

At 2457.6 MHz¹

−98.0

dBc/Hz

fs

Offset = 100 Hz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 300 kHz

Offset = 1 MHz

−111.1

−119.8

−125.2

−126.9

−131.3

−150.0

−154.0

−156.3

44.0

Offset = 5 MHz

Offset = 10 MHz

Offset = 100 MHz

Integrated jitter = 12 kHz to 20 MHz

At 614.4 MHz¹

−110.4

−122.8

−131.3

−136.6

−138.3

−142.7

−157.6

−158.8

−159.2

50.0

dBc/Hz

fs

Offset = 100 Hz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 300 kHz

Offset = 1 MHz

Offset = 5 MHz

Offset = 10 MHz

Offset = 100 MHz

Integrated jitter = 12 kHz to 20 MHz

For best 800 kHz offset

CLOSED-LOOP PHASE NOISE—NARROW LOOP FILTER

SSB Phase Noise

At 2949.12 MHz²

−100.9

−103.8

−106.9

−109.9

−132.3

−134.5

−152

dBc/Hz

fs

Offset = 100 Hz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 800 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 100 MHz

Integrated jitter = 12 kHz to 20 MHz

−155.3

108

At 983.04 MHz²

−110.4

−113.3

−116.4

−119.4

−141.7

−143.7

−157.1

dBc/Hz

Offset = 100 Hz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 800 kHz

Offset = 1 MHz

Offset = 10 MHz

Rev. B | Page 10 of 72

Data Sheet

HMC7044

Parameter

Min

Typ

Max

Unit

dBc/Hz

fs

Test Conditions/Comments

−157.1

102

Offset = 100 MHz

Integrated jitter 12 kHz to 20 MHz

OUTPUT NETWORK FLOOR FOM

CML with 100 Ω Internal Termination (CML100)

Fundamental Mode

Divide by 1 to Divide by N

LVPECL

−250

−248

−247

dBc/Hz

High performance

Low power (4 dB less power)

Fundamental Mode

Divide by 1 to Divide by N

LVDS

−250

−247

dBc/Hz

Divide by 1 to Divide by N

PHASE NOISE DEGREDATION DUE TO HARMONICS³

Fundamental Only

−244

−243

dBc/Hz

High performance

Low power (4 dB less power)

0.00

0.25

0.40

0.50

0.53

0.64

dB

Third Harmonic

Third and Fifth Harmonics

Third, Fifth, and Seventh Harmonics

Third, Fifth, Seventh, and Ninth Harmonics

Third Through 61^stHarmonics

PHASE NOISE FLOOR AND JITTER

Phase Noise Floor at f_OUT

Determined by formula⁴dBc/Hz

Determined by formula⁵sec/√Hz

Determined by formula⁶sec

Jitter Density of Floor at f_OUT

RMS Additive Jitter Due to Floor

From f_OUTand output channel FOM

¹PLL2 locked at 122.88 MHz × 2 × 10, wide (600 kHz) loop filter for best 12 kHz to 20 MHz jitter, CML100 high performance output buffer.

²PLL2 locked at 122.88 MHz × 2 × 12, narrow loop for best 800 Hz offset, CML100 high performance output buffer.

³When the harmonics of the signal are captured in the measurement bandwidth of the receiving instrument/circuit, the noise power of those harmonics can fold and

influence the overall noise. Their presence causes a decibel for decibel influence. For example, if the third harmonic is at −10 dBc, there is an additional noise

contributor of 10 dB lower than the fundamental at all offsets that folds in-band and causes a 0.2 dB hit overall. The influence of the harmonics factoring into the

degradation is primarily a function of the frequency of the buffer bandwidth relative to the third, fifth, and seventh harmonics. As the output frequency reduces, more

harmonics fall into the observation bandwidth, and the degradation worsens, but only slightly. This effect produces a penalty of 0.65 dB maximum if harmonics up to

the 61^stharmonic is included.

⁴See the Phase Noise Floor and Jitter section for more information on how to calculate the phase noise floor.

⁵See the Phase Noise Floor and Jitter section for more information on how to calculate the jitter density of floor.

⁶See the Phase Noise Floor and Jitter section for more information on how to calculate the rms additive jitter due to floor.

CLOCK OUTPUT DRIVER CHARACTERISTICS

Table 10.

Parameter

Min Typ

Max Unit

Test Conditions/Comments

CML MODE (LOW POWER)

−3 dB Bandwidth

Output Rise Time

R_L= 100 Ω, 9.6 mA

1950

175

145

185

145

MHz

ps

Differential output voltage = 980 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

R_L= 100 Ω, 14.5 mA

Differential output voltage = 1410 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

Output Fall Time

Output Duty Cycle¹

Differential Output Voltage Magnitude

47.5 50

1390

52.5

%

mV p-p diff

V

1360

V_CC− 1.05

Common-Mode Output Voltage

CML MODE (HIGH POWER)

3 dB Bandwidth

1400

250

165

255

170

MHz

ps

Output Rise Time

Output Fall Time

Rev. B | Page 11 of 72

HMC7044

Data Sheet

Parameter

Output Duty Cycle¹

Differential Output Voltage Magnitude

Min Typ

47.5 50

2000

Max Unit

Test Conditions/Comments

52.5

%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

R_L= 150 Ω, 4.8 mA

Differential output voltage = 1240 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

1.75 mA

Differential output voltage = 400 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

3.5 mA

Differential output voltage = 650 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

mV p-p diff

V

1800

V_CC− 1.6

Common-Mode Output Voltage

LVPECL MODE

3 dB Bandwidth

2400

135

130

135

130

MHz

ps

%

mV p-p diff

V

Output Rise Time

Output Fall Time

Output Duty Cycle¹

Differential Output Voltage Magnitude

47.5 50

1760

1850

V_CC− 1.3

Common-Mode Output Voltage

LVDS MODE (LOW POWER)

Maximum Operating Frequency

Output Rise Time

600

135

100

135

95

MHz

ps

%

Output Fall Time

Output Duty Cycle¹

47.5 50

Differential Output Voltage Magnitude

Common-Mode Output Voltage

LVDS MODE (HIGH POWER)

Maximum Operating Frequency

Output Rise Time

390

1.1

mV p-p diff

V

1700

145

105

145

100

MHz

ps

Output Fall Time

ps

Output Duty Cycle¹

Differential Output Voltage Magnitude

47.5 50

52.5

%

750

730

1.1

mV p-p diff

V

Common-Mode Output Voltage

CMOS MODE

Maximum Operating Frequency

Output Rise Time

Output Fall Time

Output Duty Cycle¹

600

425

420

MHz

ps

Single-ended output voltage = 940 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

47.5 50

52.5

%

f_CLKOUT= 1075 MHz (2150 MHz/2)

Output Voltage

High

V_CC− 0.07

V_CC− 0.5

0.07

V

Load current = 1 mA

Load current = 10 mA

Load current = 1 mA

Load current = 10 mA

Output

0.5

¹Guaranteed by design and characterization.

Rev. B | Page 12 of 72

Data Sheet

HMC7044

ABSOLUTE MAXIMUM RATINGS

Table 11.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Parameter

Rating

VCC1_VCO, VCC2_OUT, VCC3_SYSREF,

VCC4_OUT, VCC5_PLL1, VCC6_OSCOUT,

VCC7_PLL2, VCC8_OUT, VCC9_OUT

Maximum Junction Temperature (T_J)

Maximum Peak Reflow Temperature

−0.3 V to +3.6 V

125°C

260°C

7°C/W

Thermal Resistance (Channel to Ground

Paddle)

ESD CAUTION

Storage Temperature Range

Operating Temperature Range

ESD Sensitivity Level

−65°C to +150°C

−40°C to +85°C

Human Body Model

Charged Device Model¹

Class 1C

Class 3

¹Per JESD22-C101-F (CDM) standard.

Rev. B | Page 13 of 72

HMC7044

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLKOUT0

SCLKOUT1

RESET

1

2

3

4

5

6

7

8

9

51 VCC7_PLL2

50 CPOUT2

49 LDOBYP7

48 OSCIN

47 OSCIN

SYNC

46 LDOBYP6

45 OSCOUT1

BGABYP1

LDOBYP2

LDOBYP3

44 OSCOUT1

HMC7044

TOP VIEW

(Not to Scale)

43 CLKIN2/OSCOUT0

42 CLKIN2/OSCOUT0

41 VCC6_OSCOUT

40 CLKIN0/RFSYNCIN

39 CLKIN0/RFSYNCIN

38 VCC5_PLL1

37 CLKIN1/FIN

36 CLKIN1/FIN

35 RSV

VCC1_VCO 10

LDOBYP4 11

LDOBYP5 12

SCLKOUT3 13

SCLKOUT3 14

CLKOUT2 15

CLKOUT2 16

VCC2_OUT 17

NOTES

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.

Figure 2. Pin Configuration

Table 12. Pin Function Descriptions

Pin No. Mnemonic

Type¹Description

1

2

3

4

5

6

7

CLKOUT0

SCLKOUT1

RESET

O

I

True Clock Output Channel 0. Default DCLK profile.

Complementary Clock Output Channel 0. Default DCLK profile.

True Clock Output Channel 1. Default SYSREF profile.

Complementary Clock Output Channel 1. Default SYSREF profile.

Device Reset Input. Active high. For normal operation, set RESET to 0.

Synchronization Input. This pin is used for multichip synchronization. If not used, set SYNC to 0.

SYNC

BGABYP1

I

Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all

internally regulated supplies.

8

9

LDOBYP2

LDOBYP3

LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is

the LDO bypass for the PLL1, PLL2, and SYSREF sections.

LDO Bypass 3. Connect a 4.7 µF capacitor to ground. This pin is the 2.8 V supply to PLL1, Phase

Frequency Detector 1 (PFD1), Charge Pump 1 (CP1), RF synchronization (RFSYNC), and Pin 36

buffers.

10

11

VCC1_VCO

LDOBYP4

P

3.3 V Supply for VCO and VCO Distribution.

LDO Bypass 4. Connect a 1 µF capacitor to ground. This pin is the first stage regulator for the VCO

supply.

12

13

14

15

16

17

LDOBYP5

SCLKOUT3

CLKOUT2

VCC2_OUT

LDO Bypass 5. Connect a 100 nF capacitor to LDOBYP4. This pin is the VCO core supply voltage.

True Clock Output Channel 3. Default SYSREF profile.

Complementary Clock Output Channel 3. Default SYSREF profile.

True Clock Output Channel 2. Default DCLK profile.

O

P

Complementary Clock Output Channel 2. Default DCLK profile.

Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,

Skew, and Crosstalk section.

18

SLEN

I

SPI Latch Enable.

Rev. B | Page 14 of 72

Data Sheet

HMC7044

Pin No. Mnemonic

Type¹Description

19

20

21

22

23

24

25

26

SCLK

SDATA

I

SPI Clock.

SPI Data.

I/O

P

VCC3_SYSREF

SCLKOUT5

CLKOUT4

VCC4_OUT

Power Supply for Common SYSREF Divider.

True Clock Output Channel 5. Default SYSREF profile.

Complementary Clock Output Channel 5. Default SYSREF profile.

True Clock Output Channel 4. Default DCLK profile.

Complementary Clock Output Channel 4. Default DCLK profile.

O

P

Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the

Clock Grouping, Skew, and Crosstalk section.

27

28

29

30

31

32

33

34

35

36

37

CLKOUT6

SCLKOUT7

GPIO1

CPOUT1

CLKIN3

O

I/O

O

I

True Clock Output Channel 6. Default DCLK profile.

Complementary Clock Output Channel 6. Default DCLK profile.

True Clock Output Channel 7. Default SYSREF profile.

Complementary Clock Output Channel 7. Default SYSREF profile.

Programmable General-Purpose Input/Output 1.

PLL1 Charge Pump Output.

True Reference Clock Input 3 of PLL1.

Complementary Reference Clock Input 3 of PLL1.

Reserved Pin. This pin must be tied to ground.

I

RSV

CLKIN1/FIN

R

I

True Reference Clock Input 1 of PLL1/External VCO Input for External VCO Mode.

Complementary Reference Clock Input 1 of PLL1/Complementary External VCO Input for External

VCO Mode.

38

39

40

VCC5_PLL1

CLKIN0/RFSYNCIN

P

I

Power Supply for LDO, Used for PLL1.

True Reference Clock Input 0 of PLL1/RF Synchronization Input with Deterministic Delay.

Complementary Reference Clock Input 0 of PLL1/Complementary RF Synchronization Input with

Deterministic Delay.

41

42

43

VCC6_OSCOUT

CLKIN2/OSCOUT0 I/O

P

Power Supply for Oscillator Output Path.

True Reference Clock Input 2 (Bidirectional Pin) of PLL1/Buffered Output 0 of Oscillator Input.

Complementary Reference Clock Input 2 (Bidirectional Pin) of PLL1/Complementary Buffered

Output 0 of Oscillator Input.

44

45

46

OSCOUT1

LDOBYP6

O

True Buffered Output 1 of Oscillator Input.

Complementary Buffered Output 1 of Oscillator Input.

LDO Bypass, Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for R2, N2, Phase

Frequency Detector 2 (PFD2), Charge Pump 2 (CP2), and the PLL2 loop filter.

47

48

49

OSCIN

I

True Feedback Input to PLL1. This pin is a reference input to PLL2.

Complementary Feedback Input to PLL1. This pin is a reference input to PLL2.

LDOBYP7

LDO Bypass. Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for the VCXO buffer

and frequency doubler oscillator output divider.

50

51

52

53

54

55

56

57

CPOUT2

VCC7_PLL2

GPIO2

SCLKOUT9

CLKOUT8

VCC8_OUT

I/O

P

I/O

O

PLL2 Charge Pump Output.

Power Supply for LDO for PLL2.

Programmable General-Purpose Input/Output 2.

True Clock Output Channel 9. Default SYSREF profile.

Complementary Clock Output Channel 9. Default SYSREF profile.

True Clock Output Channel 8. Default DCLK profile.

Complementary Clock Output Channel 8. Default DCLK profile.

O

P

Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See

the Clock Grouping, Skew, and Crosstalk section.

58

59

60

61

62

63

64

CLKOUT10

SCLKOUT11

GPIO3

O

True Clock Output Channel 10. Default DCLK profile.

Complementary Clock Output Channel 10. Default DCLK profile.

True Clock Output Channel 11. Default SYSREF profile.

Complementary Clock Output Channel 11. Default SYSREF profile.

Programmable General-Purpose Input/Output 3. Sleep input by default.

Programmable General-Purpose Input/Output 4. Pulse generator request by default.

True Clock Output Channel 13. Default SYSREF profile.

O

I/O

O

GPIO4

SCLKOUT13

Rev. B | Page 15 of 72

HMC7044

Data Sheet

Pin No. Mnemonic

Type¹Description

65

66

67

68

SCLKOUT13

CLKOUT12

VCC9_OUT

O

P

Complementary Clock Output Channel 13. Default SYSREF profile.

True Clock Output Channel 12. Default DCLK profile.

Complementary Clock Output Channel 12. Default DCLK profile.

Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13.

See the Clock Grouping, Skew, and Crosstalk section.

EP

Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.

¹O is output, I is input, P is power, and I/O is input/output.

Rev. B | Page 16 of 72

Data Sheet

HMC7044

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, PFD PLL1 = 7.68 MHz, PFD PLL2 = 122.88 MHz × 2; I_CP1= 1.92 mA, I_CP2= 2.56 mA (wide loop), I_CP2= 1.12 mA

(narrow loop), PLL1 loop BW ~ 70 Hz, PLL2 wide loop BW ≈ 650 kHz, PLL2 narrow loop BW ≈ 215 kHz, PLL2 narrow loop filter =

1.1 nF | 160 Ω × 33 nF; PLL2 wide loop filter = 150 pF | 430 Ω × 4.7 nF; PLL1 loop filter = 4.7 nF | 10 µF × 1.2 kΩ.

–60

–40

–50

1: 1kHz, –107.8dBc/Hz

2: 10kHz, –119.5dBc/Hz

3: 100kHz, –124.7dBc/Hz

4: 1MHz, –131.5Bc/Hz

5: 10MHz, –153.1dBc/Hz

6: 20MHz, –154.4dBc/Hz

7: 20MHz, –154.4dBc/Hz

x: START 12kHz

–70

–60

TOTAL PLL1 NOISE (SIMULATED)

PFD/CP NOISE (SIMULATED)

WENZEL REF (SIMULATED)

VCXO (SIMULATED)

–80

–70

–80

–90

STOP 20MHz

CENTER 10MHz

SPAN 20MHz

TOTAL PLL1 NOISE (MEASURED)

–90

–100

–110

–120

–130

–140

–150

–160

–100

–110

–120

–130

–140

–150

–160

–170

–180

1

2

PLL1

3

CASCADED PLL1 + PLL2

4

NOISE:

ANALYSIS RANGE X: BAND MARKER

ANALYSIS RANGE Y: BAND MARKER

INTG NOISE: –66dBc/20MHz

RMS NOISE: 696µrad

6

7

5

0.004°

RMS JITTER: 45fs

RESIDUAL FM: 1.6kHz

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 3. Cascaded Phase Noise at 2457.6 MHz, PLL2 Wide Loop Bandwidth

Figure 6. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.

Simulated, Clean Reference Source, ~70 Hz Loop Bandwidth 80° Phase Margin

–60

–70

TOTAL PLL1 OUTPUT (SIMULATED)

1: 1kHz, –105.3dBc/Hz

2: 10kHz, –108.5dBc/Hz

PFD/CP NOISE (SIMULATED)

–70

–80

NOISY SOURCE (SIMULATED)

3: 100kHz, –111.4dBc/Hz

4: 800kHz, –134.2dBc/Hz

5: 1MHz, –136.5dBc/Hz

VCXO (SIMULATED)

NOISY SOURCE, OPEN LOOP (MEASURED)

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

6: 10MHz, –153.3dBc/Hz

7: 20MHz, –154.6dBc/Hz

x: START 12kHz

STOP 20MHz

TOTAL PLL1 NOISE (MEASURED)

–90

1

2

CENTER 10MHz

SPAN 20MHz

–100

–110

–120

–130

–140

–150

–160

3

WIDE LOOP

NARROW LOOP

4

5

NOISE:

ANALYSIS RANGE X: BAND MARKER

ANALYSIS RANGE Y: BAND MARKER

INTG NOISE: –56.9dBc/20MHz

RMS NOISE: 2.0µrad

6

7

.116°

RMS JITTER: 131fs

RESIDUAL FM: 1.5kHz

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 4. Phase Noise at 2457.6 MHz, Narrow vs. PLL2 Wide Loop

Bandwidth

Figure 7. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.

Simulated, Noisy Reference Source, ~70 Hz Loop Bandwidth, 80° Phase Margin

–120

–125

–130

–135

–70

1: 1kHz, –110.4dBc/Hz

2: 10kHz, –120.0dBc/Hz

–80

–90

3: 100kHz, –124.9dBc/Hz

4: 1MHz, –131.2dBc/Hz

5: 10MHz, –153.2dBc/Hz

6: 20MHz, –154.5dBc/Hz

7: 20MHz, –154.5dBc/Hz

x: START 12kHz

–100

–110

–120

–130

–140

–150

–160

–170

STOP 20MHz

CENTER 10MHz

1

SPAN 20MHz

–140

2

20×LOG (800kHz WIDE LOOP)

20×LOG (800kHz NARROW LOOP)

800kHz WIDE LOOP

800kHz NARROW LOOP

–145

3

4

CRYSTEK VCXO

WENZEL VCXO

–150

–155

–160

–165

–170

NOISE:

ANALYSIS RANGE X: BAND MARKER

ANALYSIS RANGE Y: BAND MARKER

INTG NOISE: –66.1dBc/20.0MHz

RMS NOISE: 702µrad

6

7

5

.040°

RMS JITTER: 45fs

RESIDUAL FM: 1.6kHz

100

600

1100

1600

2100

2600

3100

3600

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

FREQUENCY (MHz)

Figure 5. PLL2 Phase Noise vs. Frequency, VCXO Quality at 2457.6 MHz,

Wide Loop Bandwidth

Figure 8. Phase Noise vs. Frequency at Common Output Frequencies

Rev. B | Page 17 of 72

HMC7044

Data Sheet

160

140

120

100

80

3.0

2.5

2.0

1.5

1.0

0.5

0

JITTER WIDE LOOP

JITTER NARROW LOOP

LOW VCO –40°C

LOW VCO +25°C

LOW VCO +85°C

HIGH VCO –40°C

HIGH VCO +25°C

HIGH VCO +85°C

60

40

20

0

100

600

1100

1600

2100

2600

3100

3600

FREQUENCY (MHz)

Figure 9. 12 kHz to 20 MHz Jitter vs. Frequency, Wide Loop and Narrow

Loop at Common Output Frequencies

Figure 12. VCO V_TUNEvs. Frequency

–90

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

8: 100Hz, –99.8dBc/Hz

1: 1kHz, –111.1dBc/Hz

–95

LVPECL

2: 10kHz, –119.8dBc/Hz

CML100 HIGH

3: 100kHz, –125.2dBc/Hz

–100

7: 300kHz, –126.9dBc/Hz

CML100 LOW

8

4: 1MHz, –131.3Bc/Hz

–105

LVDS HIGH

5: 10MHz, –153.1dBc/Hz

CMOS (NOT IN

DIFFERENTIAL MODE)

6: 32.8MHz, –156.3dBc/Hz

–110

x: START 12kHz

STOP 20MHz

CENTER 10MHz

SPAN 20MHz

1

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

2

3

7

4

NOISE:

ANALYSIS RANGE X: BAND MARKER

ANALYSIS RANGE Y: BAND MARKER

INTG NOISE: –66.4dBc/20MHz

RMS NOISE: 678µrad

6

.039°

RMS JITTER: 44fs

RESIDUAL FM: 1.5kHz

5

100

1k

10k

100k

1M

10M

100M

1G

3G

FREQUENCY (Hz)

CLKOUTx

Figure 10. Phase Noise, CLKOUTx/

Figure 13. Differential Output Voltage vs. Frequency at Different Modes

= 2457.6 MHz, Optimized for Best

Integrated Jitter (12 kHz to 20 MHz)

2.25

2.10

100

90

80

70

60

50

40

30

20

10

0

LVPECL

1.95

1.80

1.65

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0

CML100 HIGH

CML100 LOW

LVDS HIGH

2865.72MHz

3511.86MHz

2115.38MHz

2627.755 MHz

CAP = 0 LOW VCO

CAP = 0 HIGH VCO

CAP = 31 LOW VCO

CAP = 31 HIGH VCO

0

0.5

1.0

1.5

VCO V

2.0

2.5

3.0

1.0

1.5

2.0

2.5

3.0

3.5

FREQUENCY (GHz)

(V)

TUNE

Figure 14. Differential Output Voltage vs. Frequency at Different Modes

Figure 11. VCO Gain (K_VCO) vs. VCO V_TUNE

Rev. B | Page 18 of 72

Data Sheet

HMC7044

2.5

2.0

1.5

1.0

0.5

30

25

20

15

10

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

0

100M

1G

3G

FREQUENCY (Hz)

DELAY STEP

Figure 15. LVPECL Differential Output Voltage vs. Frequency at Different

Temperatures

Figure 18. Analog Delay Step Size vs. Delay Step over Temperature, LVPECL

at 1474.56 MHz

0.4

0.3

800

700

600

0.2

500

–40°C

+25°C

+85°C

0.1

400

300

200

100

0

–0.1

–0.2

–0.3

–0.4

FUND: FUNDAMENTAL MODE AT 2949MHz

DIS: ANALOG DELAY IS DISABLED AT 1474MHz

–100

–200

0

0.4

0.8

1.2

TIME (ns)

1.6

2.0

DELAY SETTING

Figure 19. Analog Delay vs. Delay Setting over Temperature, LVPECL

at 1474.56 MHz

CLKOUT0

Figure 16. Differential CLKOUT0/

at 2457 MHz, LVPECL

30

25

20

15

10

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–40°C

+25°C

+85°C

5

0

1

2

3

4

5

6

7

8

9

10

TIME (ns)

DELAY STEP

Figure 20. Analog Delay Step Size vs Delay Step over Temperature, LVPECL

at 3072 MHz with Digital Delay = 0

CLKOUT0

Figure 17. Differential CLKOUT0/

Voltage at 614.4 MHz, LVPECL

Rev. B | Page 19 of 72

HMC7044

Data Sheet

700

600

500

400

300

200

100

0

0.6

0.4

2.5

2.0

1.5

1.0

0.5

0

CLKOUT0

CLKOUT2

VALID PHASE ALARM

0.2

0

–40°C

+25°C

+85°C

–0.2

–0.4

–0.6

–0.5

0

200

400

600

TIME (ns)

800

1000

DELAY SETTING

Figure 24. Output Channel Synchronization Before and After Rephase

Figure 21. Analog Delay vs. Delay Setting over Temperature, LVPECL at

3072 MHz with Digital Delay = 0

30

0.6

0.4

2.5

2.0

1.5

1.0

0.5

0

–40°C

+25°C

+85°C

CLKOUT0

25

20

15

CLKOUT2

VALID PHASE ALARM

0.2

0

–0.2

–0.4

–0.6

10

–0.5

330

335

340

345

350

TIME (ns)

DELAY STEP

Figure 22. Analog Delay Step Size vs Delay Step over Temperature, LVPECL

at 3072 MHz with Digital Delay = 1

Figure 25. Output Channel Synchronization Before Rephase

800

700

600

500

0.6

0.4

2.5

2.0

1.5

1.0

0.5

0

0.2

400

0

–40°C

+25°C

+85°C

300

200

100

0

–0.2

–0.4

–0.6

CLKOUT0

CLKOUT2

VALID PHASE ALARM

–0.5

715

695

700

705

710

TIME (ns)

DELAY SETTING

Figure 26. Output Channel Synchronization After Rephase

Figure 23. Analog Delay vs. Delay Setting over Temperature, LVPECL at

3072 MHz with Digital Delay = 1

Rev. B | Page 20 of 72

Data Sheet

HMC7044

TYPICAL APPLICATION CIRCUITS

HMC7044

0.1µF

HMC7044

HIGH

100Ω IMPEDANCE

HIGH

IMPEDANCE

INPUT

LVDS

OUTPUT

LVDS

OUTPUT

DOWNSTREAM

DEVICE

DOWNSTREAM

DEVICE

100Ω

INPUT

0.1µF

Figure 27. AC-Coupled LVDS Output Driver

Figure 31. DC-Coupled LVDS Output Driver

VCC

HMC7044

100Ω

LVPECL-

COMPATIBLE

OUTPUT

DOWNSTREAM

DEVICE

(LVPECL)

0.1µF

HMC7044

HIGH

IMPEDANCE

INPUT

DOWNSTREAM

DEVICE

100Ω

50Ω

CML

OUTPUT

0.1µF

50Ω

GND

Figure 32. DC-Coupled LVPECL Output Driver

Figure 28. AC-Coupled CML (Configured High-Z) Output Driver

0.1µF

HMC7044

DOWNSTREAM

DEVICE

(CML)

100Ω

HIGH

IMPEDANCE

INPUT

DOWNSTREAM

DEVICE

VCCx_OUT

100Ω

CML

OUTPUT

CML

OUTPUT

0.1µF

Figure 33. DC-Coupled CML (Internal) Output Driver

Figure 29. AC-Coupled CML (Internal) Output Driver

0.1µF

HMC7044

3.3V

DRIVER

47Ω

SELF BIASED

REF, VCXO

INPUTS

0.1µF

CLKIN0

OSCIN

and OSCIN/

CLKIN1

Input, Differential Mode

CLKIN2

CLKIN3

Figure 34. CLKIN0, CLKIN1, CLKIN2, CLKIN3, and OSCIN Input,

Single-Ended Mode

Figure 30. CLKIN0/ , CLKIN1/

, CLKIN2/

, CLKIN3/

,

Rev. B | Page 21 of 72

HMC7044

Data Sheet

TERMINOLOGY

Phase Jitter

a sine wave, the time of successive zero crossings varies. In a square

wave, the time jitter is a displacement of the edges from their

ideal (regular) times of occurrence. In both cases, the variations in

timing from the ideal are the time jitter. Because these variations

are random in nature, the time jitter is specified in seconds root

mean square (rms) or 1 sigma of the Gaussian distribution.

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for

each cycle. Actual signals, however, display a certain amount

of variation from ideal phase progression over time. This

phenomenon is phase jitter. Although many causes can

contribute to phase jitter, one major cause is random noise,

which is characterized statistically as being Gaussian (normal)

in distribution.

Time jitter that occurs on a sampling clock for a DAC or an

ADC decreases the signal-to-noise ratio (SNR) and dynamic

range of the converter. A sampling clock with the lowest possible

jitter provides the highest performance from a given converter.

This phase jitter leads to the energy of the sine wave in the

frequency domain spreading out, producing a continuous

power spectrum. This power spectrum is usually reported as

a series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in decibels) of the power contained within a 1 Hz

bandwidth with respect to the power at the carrier frequency.

For each measurement, the offset from the carrier frequency is

also given.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is

attributable to the device or subsystem being measured.

The phase noise of any external oscillators or clock sources is

subtracted, which makes it possible to predict the degree to

which the device impacts the total system phase noise when

used in conjunction with the various oscillators and clock

sources, each of which contributes its own phase noise to the

total. In many cases, the phase noise of one element dominates

the system phase noise. When there are multiple contributors to

phase noise, the total is the square root of the sum of squares of

the individual contributors.

Phase Noise

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 10 kHz to

10 MHz). This is the integrated phase noise over that frequency

offset interval and can be readily related to the time jitter due to

the phase noise within that offset frequency interval.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is attributable to

the device or subsystem being measured. The time jitter of any

external oscillators or clock sources is subtracted, which makes

it possible to predict the degree to which the device impacts the

total system time jitter when used in conjunction with the various

oscillators and clock sources, each of which contributes its own

time jitter to the total. In many cases, the time jitter of the external

oscillators and clock sources dominates the system time jitter.

Phase noise has a detrimental effect on the performance of ADCs,

DACs, and RF mixers. It lowers the achievable dynamic range of

the converters and mixers, although they are affected in somewhat

different ways.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When observing

Rev. B | Page 22 of 72

Data Sheet

HMC7044

THEORY OF OPERATION

programmed to have a different phase offset. The phase

The HMC7044 is a high performance, dual-loop, integer N

jitter attenuator capable of performing frequency translation,

reference selection, and generation of ultralow phase noise

references for high speed data converters with either parallel or

serial (JESD204B type) interfaces. The device is designed to

meet the requirements of demanding base station designs, and

offers a wide range of clock management and distribution

features to simplify baseband and radio card clock tree designs.

adjustment capability allows the designer to offset board flight

time delay variations, data converter sample window matching,

and meet JESD204B synchronization challenges. The output

signal path design of the HMC7044 is implemented to ensure

both linear phase adjustment steps and minimal noise

perturbation when phase adjustment circuits are turned on.

One of the key challenges in JESD204B system design is

ensuring the synchronization of data converter frame alignment

across the system, from the FPGA or DFE to ADCs and DACs

through a large clock tree that can comprise multiple clock

generation and distribution ICs. The HMC7044 is specifically

designed to offer features to address this challenge. Using the

SYSREF valid interrupt feature, the wait time latency can be

reduced in the FPGAs. The HMC7044 raises this flag through

its GPO port when all counters are set and outputs are at the

desired phases. Additionally, an external reference-based

synchronization feature (SYNC via PLL2 or RF SYNC only in

fanout mode) synchronizes multiple devices, that is, it ensures

that all clock outputs start with same rising edge. This operation

is achieved by rephasing the SYSREF control unit deterministi-

cally, and then restarting the output dividers with this new

desired phase.

The HMC7044 uses a dual-loop architecture, where two integer

mode PLLs are connected in series to form a jitter attenuating

clock multiplier unit. The high performance dual-loop topology

of the HMC7044 enables the wireless/RF system designer to

attenuate the incoming jitter of a primary system reference

clock (for example, Common Public Radio Interface™ (CPRI)

source) and generate low phase noise, high frequency clocks to

drive data converter sample clock inputs. The HMC7044 provides

14 low noise and configurable outputs to offer flexibility in

interfacing with many different components in an RF trans-

ceiver system, such as data converters, local oscillators,

transmit/receive modules, FPGAs, and digital front-end (DFE)

ASICs.

The first PLL in the HMC7044 is designed for low bandwidth

configuration using appropriately selected external loop filter

components, and internal charge pump bias settings to achieve

less than a few hundred Hz bandwidth, typically. The exact

bandwidth roll-off points depend on the frequency spectrum of

noise that must be attenuated in the system. The first PLL locks

an external VCXO and provides the clock holdover functions

and the reference frequency to the high performance second

PLL loop. The combination of the loops provides an excellent

clock generation unit with the capability to attenuate incoming

reference clock jitter. The second PLL loop features two

overlapping on-chip VCOs that are SPI selectable with center

frequencies at 2.5 GHz and 3 GHz, respectively. Both VCOs are

designed to have wide tuning ranges for broad output frequency

coverage. The desired output frequency is set by the chosen

VCXO frequency, VCO core (higher or lower frequency core),

and the programmed second PLL feedback divider and output

channel divider values.

Offering excellent crosstalk, frequency isolation, and spurious

performance, the device generates independent frequencies in

both single-ended and differential formats. The four input

reference options allows up to three backup frequency sources,

with hitless switching and holdover capabilities, supporting

system redundancy and uninterrupted operation on reference

data and clock failures. The device also features dedicated

oscillator fanout mode for best clock isolation, which generates

multiple copies of the VCXO clock to be distributed across the

board with excellent frequency isolation.

Both the DCLK and SYSREF clock outputs can be configured to

support different signaling standards, including CML, LVDS,

LVPECL, and LVCMOS, and different bias conditions to offset

varying board insertion losses. The outputs can also be

programmed for ac or dc coupling and 50 Ω or 100 Ω internal

and external termination options.

The HMC7044 generates up to seven DCLK and SYSREF clock

pairs per the JESD204B interface requirements. The system

designer can generate a lower number of DCLK and SYSREF

pairs, and configure the remaining output signal paths as

desired, either as DCLKs or additional SYSREFs or other

reference clocks with independent phase and frequency

adjustment. Frequency adjustment can be accomplished by

selecting the appropriate output divider values. One of the

unique features of the HMC7044 is the independent flexible

phase management of each of the 14 channels. Using a

combination of divider slip-based, digital/coarse and

analog/fine delay adjustments, each channel can be

The HMC7044 is programmed via a 3-wire serial port interface

(SPI) and powers up with a default configuration that generates

valid output frequencies within the VCO tuning ranges regardless

of whether a reference clock exists.

The HMC7044 is offered in a 68-lead, 10 mm ×10 mm, LFCSP

package with the exposed pad to ground.

Note that, throughout this data sheet, multifunction pins, such

as CLKIN0/RFSYNCIN, are referred to either by the entire pin

name or by a single function of the pin, for example, CLKIN0,

when only that function is relevant.

Rev. B | Page 23 of 72

Data Sheet

HMC7044

DETAILED BLOCK DIAGRAM

RFSYNCIN/

RFSYNCIN

CLKIN0/RFSYNCIN

IN0 PRESCALER

(1 TO 255)

FIN/

FIN

LOS

DETECT

HOLDOVER

CLKIN1/FIN

IN1 PRESCALER

(1 TO 255)

CLKIN3

IN3 PRESCALER

(1 TO 255)

R1 DIVIDER

(1 TO 65535)

REF

MUX

PHASE DETECTOR

CHARGE PUMP

PLL1

VCO1 ~ 2500MHz

VCO2 ~ 3000MHz

CPOUT1

CLKIN2/OSCOUT0

IN2 PRESCALER

(1 TO 255)

N1 DIVIDER

(1 TO 65535)

SPI

CPOUT2

VCXO PRESCALER

(1 TO 255)

PARTIALLY

INTEGRATED INTERNAL

LOOP

FILTER

VCO

×2

2×

MUX

R2 DIVIDER

(1 TO 4095)

PHASE DETECTOR

CHARGE PUMP

PLL2

OSCOUT1

OSC DIVIDER

÷1, ÷2, ÷4, ÷8

N2 DIVIDER

(8 TO 4095)

OSCIN

OSCINBUF

CLK DISTRIBUTION PATH

VCO

MUX

EXT VCO

DIVIDER

÷1, ÷2

FIN/FIN

COARSE

DIGITAL

DELAY

CYCLE

DIVIDER

(1 TO 4094)

SLIP/

SYNC

FSM

SYNC

CLKOUT0

ANALOG

MUX

DELAY

SYSREF TIMER

FUNDAMENTAL MODE

RFSYNCIN/

RFSYNCIN

GPI

SPI

SYNC/PULSOR

CONTROL

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

SCLKOUT1

ANALOG

DELAY

FUNDAMENTAL MODE

TO LEAF DIVIDERS

CYCLE

OSCINBUF

COARSE

DIGITAL

DELAY

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIVIDER

(1 TO 4094)

SLIP/

SYNC

CLKOUT2

ANALOG

DELAY

ANALOG

DELAY

CLKOUT8

MUX

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

SCLKOUT3

SCLKOUT9

DELAY

ANALOG

DELAY

ANALOG

DELAY

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

DELAY

CLKOUT4

ANALOG

DELAY

ANALOG

DELAY

CLKOUT10

MUX

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

SCLKOUT5

SCLKOUT11

DELAY

ANALOG

DELAY

ANALOG

DELAY

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

DELAY

CLKOUT6

ANALOG

DELAY

ANALOG

DELAY

CLKOUT12

MUX

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

SCLKOUT13

SCLKOUT7

DELAY

ANALOG

DELAY

ANALOG

DELAY

FUNDAMENTAL MODE

DEVICE

CONTROL

LDOs

SPI

ALARM GENERATION

BGA LDO LDO LDO LDO LDO LDO SDATA SCLK SLEN

BYP1 BYP2 BYP3 BYP4 BYP5 BYP6 BYP7

GPIO1 GPIO2 GPIO3 GPIO4

SYNC RESET

Figure 35. Top Level Diagram

Rev. B | Page 24 of 72

Data Sheet

HMC7044

In addition, PLL1 monitors its active reference for failure and

smoothly takes appropriate action, switching to a redundant

reference or going into holdover as appropriate. Figure 36 shows

the architecture of PLL1 with a typical frequency configuration.

DUAL PLL OVERVIEW

The HMC7044 uses a cascade of two PLLs, referred to as a dual

loop topology. The term dual loop sometimes refers to other

architectures as well; therefore, always refer to the block diagram

shown in Figure 35 to remove any ambiguity. In this architecture,

the first PLL (PLL1) normally operates as a jitter attenuator. PLL1

locks a clean local VCXO to a relatively noisy reference using a

very narrow loop bandwidth. The loop bandwidth preserves the

average frequency of the reference signal (which is normally

correct), while rejecting the majority of its noise. The second

PLL takes this low noise VCXO and multiplies it up to the VCO

frequency (in the 2 GHz to 3 GHz range) with very little additive

noise. The architecture provides the benefits of an output frequency

locked to an input reference signal, while being insensitive to its

noise profile.

Jitter Attenuation

For the purpose of jitter attenuation, PLL1 consists of all the

usual components in a PLL: a phase/frequency detector (PFD1),

charge pump (CP1), reference divider (R1), and feedback

divider (N1). The loop filter is external to provide maximum

flexibility, and the loop bandwidth (BW) is normally configured

very narrow (20 Hz to 500 Hz) to filter any jitter and spurious

tones coming in from relatively poor references.

The noise profile of PLL1 is typically dependent on the loop

bandwidth, input reference noise, and the VCXO characteristic.

The inherent noise sources of PLL1 (the PFD, dividers, and

charge pump) are not normally observable in an application,

and are significantly more relaxed compared with PLL2.

In ICs such as the HMC7044, the VCO is then connected to an

array of output channels, each with an optional RF divider and

phase control. The key feature that distinguishes an IC with

JESD204B support is the ability to ensure that all of the outputs

with their associated dividers have a user defined phase relationship

each and every time, regardless of process, voltage, or temperature.

This ability is necessary to support the JESD204B SERDES

standard for data converters, but it is also an immensely useful

feature in other applications as well, in all forms of arrayed systems

and in many test and measurement scenarios.

Note that the loop filter components on the board are typically

configured to produce a certain loop bandwidth, given a fixed

PFD rate, charge pump current, and VCXO characteristic.

Adjusting any of these parameters from their nominal positions

affects the loop dynamics, which can be to the advantage of the

user (for example, to scale loop BW with charge pump current),

but it must not be performed without an analysis of the stability

of the loop. Analog Devices, Inc., provides a variety of software

tools to design the loop filter and model the effects of any

change in parameters. Contact Analog Devices for the latest

recommendation.

COMPONENT BLOCKS—INPUT PLL (PLL1)

PLL1 General Description (Jitter Attenuator)

A variety of local clocks, particularly in synchronous networks,

derive their timing from a remote node in the network. These

reference signals can arrive via a GPS or clock data recovery

(CDR) receiver, or from a variety of other sources. Often, these

derived references are relatively poor quality, in terms of spurious

content, noise, and reliability.

The lock time of PLL1 typically takes the longest duration in the

clock network, and, aside from any nonlinear slewing, takes

approximately 5/PLL1_BW (for example, 5 ms for a 1 kHz loop

BW). Fortunately, there are no requirements that PLL1 must be

locked before proceeding with PLL2, output calibration, and

phasing, which normally allows system configuration to

continue in parallel while PLL1 is settling.

The function of PLL1 is to lock a clean VCXO to the average

frequency of one of these references and feed it to PLL2 to

generate a high quality clock for local use.

Rev. B | Page 25 of 72

HMC7044

Data Sheet

FORCE

V

TUNE

LOCKDET

PLL1

FSM

DAC

CYCLESLIP

ADC/DAC

CONTROL

FORCE V

TUNE

LOS

MAINTAIN_HOLDOVER

RESET

61.44MHz

COMPARATOR

122.88MHz

38.4MHz

61.44MHz

9.76MHz

÷R1

TO FSMI LOCKDET

UP

RST

SET

PHASE

ERROR

>~4ns?

TRISTATE

CP1

PFD1

0

D Q

LOCKDET

MAINTAIN

HOLDOVER

RST

÷N1

LCM

DIVIDERS

LOOP

FILTER

DOWN

CYCLE SLIP

DETECTED

(TO PLL1 FSM)

VCXO

122.88MHz

TO PLL2

Figure 36. PLL1 Architecture with a Typical Frequency Configuration

Lock Detect

PLL1 can operate in manual or automode (via the automode

reference switching bit). In manual mode, the user selects the

active reference using Manual Mode Reference Switching[1:0]

in Register 0x0029 and determines whether to go into holdover

(via the force holdover bit). In automode, the PLL1 FSM uses

the loss of signal (LOS) information, phase error data, lock

detect, and configuration data from the SPI to determine how

to handle reference interruptions. In either mode, all status

indicators are available, but PLL1 only takes evasive action in

automode. Figure 37 shows a simplified state diagram of the

PLL1 FSM.

The lock detect circuit in both PLL1 and PLL2 function the

same way. They count the number of consecutive clock cycles in

which the phase error at the PFD is below a threshold. Any phase

error above this threshold resets the counter, and the count is

restarted. When the count reaches its programmed limit, the

lock detect signal is issued and the clock of the counter is gated

off to reduce power/coupling until a large phase error restarts

the process.

Although the PLL2 loop BW is relatively well defined, the PLL1

loop BW can vary widely in any given application. The SPI word,

PLL1 Lock Detect Timer[4:0] in Register 0x0028, configures the

PLL1 lock detect timer and looks for 2^{PLL1 Lock Detect Timer[4:0]}

consecutive LCM clock cycles with a phase-error <~4 ns to

issue the lock detect. Because the loop BW of PLL1 can vary

drastically depending on the application, the user must set up

the threshold such that 2^{PLL1 Lock Detect Timer[4:0]}LCM periods is on

the order of 2× to 4× the loop time constant. For example, for

During reset, PLL1 is held in the initialization (INIT) state. When

reset is deasserted, during the preload state, the enabled reference

paths, the reference priority table, and LOS indicators are examined

to select the best reference, and, on the next cycle, it attempts to

lock. After the requisite number of counts has elapsed with low

phase error, lock detect is asserted and PLL1 transitions to the

locked state. When PLL1 is locked, a loss of lock, LOS on the active

reference, or a reference switch event initiated by a priority clash

transitions the FSM to enter holdover, where it tristates the CP and

potentially forces V_TUNEwith the holdover DAC. When a stable

clock is available and other optional conditions are met, the FSM

exits holdover. Exiting holdover is handled in one of a few different

ways, designed to minimize phase/frequency hits during the

transition. Figure 37 shows a simplification of the PLL1 FSM. In

the actual implementation, the holdover state is broken into a

number of subsections corresponding to holdover entry, stable

holdover conditions, and holdover exit. The state of the PLL1

FSM is always available for a read via the SPI (PLL1 FSM State[2:0]

bits in Register 0x0082).

f_LCM= 61.44 MHz, and a loop BW of 200 Hz, set PLL1 Lock Detect

Timer[4:0] = 19 or 20. If the value is set much higher, the lock

detect circuit takes an unnecessary length of time to indicate

lock after the phases stabilize. If the value is set much lower (for

example, much less than a loop time constant), it can improperly

indicate lock during acquisition, which can cause the PLL1

finite state machine (FSM) to improperly fall in and out of

holdover mode.

Holdover/Reference Switching Overview

When switching between redundant references, or when all

references are gone and the PLL1 is left open loop, there are

often requirements to prevent frequency deviations that can

cause downstream circuits and traffic links to overrun FIFOs

and/or lose lock themselves.

Rev. B | Page 26 of 72

Data Sheet

HMC7044

RESET

INIT

PLL1 LOS Detection

The HMC7044 checks the validity of a reference by comparing

its approximate frequency vs. the VCXO. The HMC7044 supports

references at different frequencies. The first step is to divide the

available references and the VCXO to the lowest common multiple

frequency (f_LCM). These divider settings are available via the SPI

PRELOAD

LOCKING

control bits (CLKINx/

Input Prescaler[7:0] and OSCIN/

CLKINx

OSCIN

Input Prescaler[7:0]). In the example shown in Figure 36,

_LCM= 61.44 MHz. The VCXO derived clock at f_LCMis the main

f

LOCKDET

clock to the PLL1 FSM controlling the FSM, lock detect timer,

and ADC/DAC filtering and holdover circuits. Although not

required, using the VCXO clock allows the LOS detection and

PLL1 FSM to operate at a higher rate than the PFD, allowing it to

recognize a reference failure early and enter holdover, sometimes

before a failing reference that has started to drift in either phase

or frequency (or both) can influence the PFD or CP.

LOCKED

REVERTIVE

AND HIGHER PRIORITY

CLOCK IS AVAILABLE

NOT LOCKDET

LOS ACTIVE REF

HOLDOVER

The dividers in the LOS block, and to some extent, R1, pose a

few challenges. The input frequencies are up to 800 MHz, with a

wide divider range. Furthermore, they are designed to tolerate

glitchy clocks without catastrophic results, because a reset phase

is not always available after an issue is detected.

AT LEAST ONE REFERENCE OK AND BEST

AVAILABLE REFERENCE IS SELECTED

[AND PHASES CROSSED ZERO (OPTIONAL)]

[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)]

OR

JUST ENTERED HOLDOVER (<HOLDOFF TIMER[7:0])

AND PREVIOUS CLOCK RECOVERS

[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)]

When all the references are divided to the same frequency, they

are compared relative to the VCXO derived path, and thus each

other. This comparison is performed by a circuit that looks for

three edges of a clock within one period of the other. If it appears

that a reference signal is too slow, its LOS flag is asserted and, in

automode, PLL1 uses this information to disqualify and/or

abandon a reference. Conversely, if it appears that the VCXO is

too slow according to any of the active references, a warning is

generated (available as one of the configurable options for the

GPO, or readable on the SPI) but no automated action occurs.

Figure 37. PLL1 FSM Simplified State Diagram—

Autorevertive Reference Switching = 1

PLL1 Reference Inputs

PLL1 accepts up to four candidate references on CLKIN3/

CLKIN3

CLKIN0

to CLKIN0/

. If all references appear valid, according to

the LOS, PLL1 uses a reference priority table to select the best

candidate. Using the PLL1 reference priority control bits, program

CLKIN0

CLKIN2

the highest priority clock (CLKIN0/ , CLKIN1/

,

CLKIN2 CLKIN3

), and then second

CLKIN2/

, or CLKIN3/

The HMC7044 monitors reference signals for three edges of a clock

within one period of the other, instead of the more intuitive two

edges, to avoid false LOS flags as clocks that are slightly out of

frequency cross each other in phase in the presence of interference,

noise, and circuit offsets. The result is that the LOS triggers when

the failing reference clock frequency is approximately an octave

from the intended frequency.

priority clock, and so on. It is not necessary to include unused

reference inputs in the reference priority table. Instead, specify

the same useful clock in multiple positions. In automode, reference

switching occurs in the preload state (see Figure 37) as PLL1

exits reset, or while PLL1 is in the holdover state.

The reference clock input pins (Pin 36, Pin 37, Pin 39, Pin 40,

Pin 42, and Pin 43) have dual functions; therefore, SPI configura-

tion is important for proper functionality. See the PLL1

Programming Considerations section for more information

about the relevant control bits, and the Reference Buffer Details

section for interface recommendations.

After a reference signal returns and its frequency is within an

octave of the VCXO, two to three cycles of the LOS validation

timer must expire before the LOS flag is deasserted and the

reference is considered for potential use. The LOS validation

timer is programmable between 0 LCM cycles (no hysteresis),

and 64 LCM cycles via LOS Validation Timer[2:0] in

Register 0x0015, Bits[2:0].

When a reference fails, the sourcing circuit recognizes a fault

and disables either the clock or the buffer driving the signal to

the HMC7044. For this reason, hysteresis in the input buffers

prevents internal toggling for signal swings <~75 mV p-p

differential, which allows further elements in the PLL1 architecture

to cleanly recognize the interruption and prevent unwanted

transients in the frequency.

Rev. B | Page 27 of 72

HMC7044

Data Sheet

PLL1 Holdover Entry Shortcut

The recommended methods are as follows:

When a reference fails, the LOS circuit takes a number of LCM

clock cycles to recognize the problem and to request the PLL1

FSM enter holdover and tristate the CP. By that time, if one of

the missing edges is needed to trigger the R divider output, the

PFD and CP have already saturated, pulling current out of the

loop filter for these cycles, and disturbing the holdover frequency.

The probability of this happening decreases as the PFD rate

decreases relative to f_LCM, but it is not eliminated. The HMC7044

includes a unique feature to prevent this type of frequency

runaway.

•

Wait for zero phase error (no divider reset): wait for LOS =

0 and low phase error at PFD (Holdover Exit Criteria[1:0] = 1,

Holdover Exit Action[1:0] = 1)

Resetting the dividers: wait for LOS = 0 and reset the

R1/N2 dividers (Holdover Exit Criteria[1:0] = 0, Holdover

Exit Action[1:0] = 0)

DAC assisted release: wait for LOS = 0, reset R1/N2, and

configure for DAC assisted release (Holdover Exit

Criteria[1:0] = 0, Holdover Exit Action[1:0] = 3)

Wait for Zero Phase Error

A sensor watches the up/down pulses from the PFD (see

Figure 35). When locked, the pulse width is small, based on any

small signal error, PFD/CP offset, and the reset delay of the PFD. If

the device is in the locked state and has a phase error that is larger

than expected (~4 ns), it is a sign that the reference has failed, and

the device immediately tristates the pump, reducing the amount

of time charge can be extracted from the loop from about five

LCM cycles (162 ns at 30.72 MHz) to <4 ns. This error indication

also invalidates the lock detect. When the FSM acknowledges

the issue, it holds the CP in tristate. When using the optional

DAC-based holdover, the FSM instructs the ADC/DAC that is

tracking the V_TUNEvoltage to switch from sense mode to force

mode, holding it steady to within 1 LSB (about 20 mV or 0.4 ppm)

until the HMC7044 senses a stable reference and transitions out

of holdover.

While the CP is still in tristate, the FSM monitors the PDF for a

cycle slip indication as the candidate reference and VCXO signal

cross each other. The crossing of the reference and VCXO phases

eventually occurs but can take a long time, as determined by the

inherent frequency error due to an imperfect holdover. Just after a

cycle slip event, the phase error at the PFD is at its minimum

value, and there is minimal glitch as the PLL reacquires. Figure 38

shows an example where the reference is removed and PLL1

goes into tristate-based holdover. After approximately 7 sec, the

reference is restored and, about a second later, the phases cross

and the PLL reacquires, all with less than 0.15 ppm of deviation

from the original frequency value.

1.0

0.8

0.6

0.4

PLL1 Holdover Steady State

When in the holdover state, the user has the following two

options:

TRISTATE HOLDOVER MODE ≈ 8 SECONDS

0.2

0

•

Tristate the CP

Tristate the CP and engage the holdover DAC

–0.2

ENABLE REFERENCE AND LOCK

–0.4

When in tristate mode, the HMC7044 has a very high

impedance charge pump output (~10 GΩ). This output is

normally an insignificant contributor to PLL1 V_TUNEleakage,

which is determined primarily by the on-board loop filter

components and the VCXO tuning port. This mode allows the

tuning voltage to maintain itself for significant periods while in

holdover.

–0.6

–0.8

–1.0

0

1

2

3

4

5

6

7

8

9

10

TIME (Seconds)

Figure 38. Frequency Deviation from Nominal vs. Time of Tristate Holdover

Entry and Exit When the Phases Cross Zero

To accommodate indefinite periods in holdover, or to ensure

This first method of uncontrolled release suffers from an

indeterminate amount of time for the phases to cross and exit

holdover. However, if it takes 1 sec for the phases to cross, the

frequencies are off by only 1 Hz. If it takes 10 sec to cross, the

error is 0.1 Hz. If the error is so low that it takes a long time to

exit holdover, the device is effectively frequency locked. In some

applications, being open-loop for this long of a duration can be

acceptable, considering the very small frequency errors. Although

this method of holdover exit is very smooth, it can take a very

long time to occur.

V

_TUNEis driven and not susceptible to drift, the second option

(set via the holdover uses DAC bit in Register 0x0029, Bit 2)

forces the V_TUNEvoltage to its time averaged value, obtained by

low-pass filtering the ADC value while the PLL is reporting

lock. The holdover sensing ADC and the driving DAC are seven

bits each, and have an LSB of approximately 19 mV.

PLL1 Holdover Exit

The transition out of holdover can happen in three ways and is

controlled by the Holdover Exit Criteria[1:0] bits and the Holdover

Exit Action[1:0] bits in Register 0x0016 (see the Control Register

Map Bit Descriptions section for details), which describes the

steps that the FSM takes as the HMC7044 exits holdover and

acquires lock.

Rev. B | Page 28 of 72

Data Sheet

HMC7044

20

16

12

8

Resetting the Dividers

If using tristate-based holdover, the second holdover exit

method is recommended. When a reference appears available

(LOS = 0), the FSM resets the R and N dividers and allows them

to restart immediately. This approach limits the maximum phase

error coming out of holdover to two VCXO cycles (about 8 ns

for typical VCXO frequencies). There is no need to wait an

undetermined amount of time (as in the first method of

uncontrolled release) to initiate the switch.

DAC RELEASE

4

0

–4

–8

–12

–16

–20

DAC Assisted Release

If using DAC-based holdover, the DAC and CP can set V_TUNE

concurrently as the devices exits holdover. With the DAC output

impedance at a relatively low setting (for example, 5 Ω), the device

resets the dividers as in the second method, and then the CP

attempts to influence V_TUNE. The CP fails, with the DAC sinking

the current it is trying to inject into the V_TUNEnode. Gradually,

the device increases the output impedance of the DAC, and the

CP gains more influence to manipulate V_TUNE, pulling the phases

into alignment. Using this DAC assisted CP release method

limits the holdover exit transients to within ~1 ppm.

–10

0

10

20

30

40

50

60

70

80

90

TIME (ms)

Figure 40. DAC Assisted Release

20

16

12

8

DO NOTHING

4

0

Figure 39 to Figure 41 compare the holdover release methods:

resetting the dividers vs. DAC assisted release, and uncontrolled

release (which starts with a phase error of up to one PFD

period) as the device exits holdover and reacquires to a

reference signal.

–4

–8

–12

–16

–20

20

–10

0

10

20

30

40

50

60

70

80

90

16

TIME (ms)

12

Figure 41. Wait for Zero Phase Error (No Divider Reset)

RESET DIVS

8

PLL1 Programming Considerations

4

0

Configuring Reference Inputs for PLL1 vs. Other Uses

To use the four reference clocks for PLL1, the input buffer must

be enabled and selected as a relevant path for PLL1.

–4

–8

Table 13. Input Buffer and Reference Path Settings

–12

–16

–20

Bit Name

Description

Buffer Enable

Enable the input buffer (where x = 0,

1, 2, 3, or V for VCXO) via

–10

0

10

20

30

40

50

60

70

80

90

Register 0x000A to Register 0x000E

TIME (ms)

PLL1 Reference Path

Enable[3:0]

Select one of four available reference

paths for PLL1

Figure 39. Resetting the Dividers

CLKIN0 RFSYNCIN

,

Because the CLKIN0/RFSYNCIN,

/

CLKIN1 FIN

pins can be configured for

CLKIN1/FIN, and

output network purposes, and the CLKIN2/OSCOUT0 and

CLKIN2 OSCOUT0

/

pins can function as oscillator outputs, the

SPI bits in Table 14 must be configured accordingly.

Rev. B | Page 29 of 72

HMC7044

Data Sheet

Table 14. Reference Clock Input Bit Settings

PLL2 has the following features:

Bit Name

CLKIN0/CLKIN0 In RF SYNC 0 = CLKIN0/CLKIN0 does not

Input Mode function as an RF sync input

CLKIN1/CLKIN1 in External 0 = CLKIN1/CLKIN1 does not

Description

•

Lock detect

Frequency doubler

Partially integrated loop filter

VCO selection, external VCO use

VCO calibration

VCO Input Mode

/FIN

function as external VCO (FIN/

)

OSCOUT0/OSCOUT0

Driver Enable

1 = OSCOUT0/OSCOUT0 buffer

does not drive CLKIN2/CLKIN2 pins

Multichip synchronization via PLL2

Lock Detect

Choosing f_PD1

The lock detect function of PLL2 behaves the same way as in

PLL1. It counts the number of consecutive PFD clock cycles

that occur with a low phase error. When it reaches a count of

512, it declares lock. The threshold of 512 is adjustable, but

because the PLL2 loop BW does not vary as much as PLL1, it is

expected that the user never needs to change this threshold.

Although PLL1 supports a wide range of PFD frequencies,

there are trade-offs with setting the frequency too high or too

low. A few megahertz is high enough to allow the comparison

frequency to stay at an offset outside of the PLL2 loop BW and

thus suppress any coupling that manages to bypass the PLL1

loop filter.

Frequency Doubler

Choosing f_LCM

The user can engage a frequency doubler after the VCXO buffer

and before the reference divider (see Figure 35). The frequency

doubler assumes an approximate 50% input duty cycle, where

any duty cycle distortion can result in a spur, at f_PD2/2, sup-

pressed by the PLL2 loop filter. Use of the frequency doubler is

highly recommended to achieve the best spectral performance,

provided the PFD is kept under its 250 MHz frequency limit.

At a minimum, f_LCMmust be a common submultiple of all

available references. Typical frequencies include 122.88 MHz,

61.44 MHz, 38.4 MHz, 30.72 MHz, 3.84 MHz, and 1.92 MHz.

This f_LCMclock is the main clock for the PLL1 digital logic. This

clock rate also scales the PLL1 lock detect timer speeds/thresholds,

holdover ADC averaging times, and LOS assertion and revalidation

delays. Higher frequencies slightly improve the response times to

reference interruptions, whereas lower frequencies can slightly

reduce current consumption of the device by up to ~10 mA.

Values in the 30 MHz to 70 MHz range are recommended.

Partially Integrated Loop Filter

Although the large components for the PLL2 loop filter are off

chip, there is a small on-chip resister/capacitor (RC) section

formed with R = 80 Ω and C = 4.7 pF in series. This RC section

forms a higher order pole at ~420 MHz. For practical condi-

tions, this filter segment does not affect the stability of the loop.

Program the PLL1 lock detect timer threshold based on the

PLL1 loop BW and f_LCMof the user.

OFF-CHIP

There are reserved registers, as described in the Control Register

Map Bit Descriptions section, that must be reprogrammed from

their default values. For example, Register 0x00A5 must be set

from 0x00 to 0x06.

80Ω

VCO

CP

4.7pF

COMPONENT BLOCKS—OUTPUT PLL (PLL2)

Figure 42. On-Chip RC Circuit

PLL2 Overview

Figure 43 shows the VCO input network. Depending on the

frequency band of interest (2.5 GHz or 3.0 GHz), the user must

specify which VCO to enable via the VCO Selection[1:0] SPI

PLL2 is a very low noise integer PLL designed to multiply the

frequency from the VCXO to the VCO. It typically operates

with a loop BW of 10 kHz to 700 kHz. Use bandwidths on the

lower end of the range to preserve the inherent VCO phase

noise at 800 kHz offset (useful in GSM-based systems), where

bandwidths on the upper end can provide the best integrated

phase noise/jitter values.

CLKIN1 FIN

word. To use the

/

pin as an external VCO signal,

CLKIN1

program this word to 0, and set the CLKIN1/

VCO input mode bit.

in external

Internally, PLL2 has a number of features that allow it to

efficiently achieve a Banerjee floor FOM of −232 dBc and a

flicker FOM of −266 dBc. The combination of the on-board

VCO, an internal VCXO doubler, a low N2 minimum divide

ratio, and the ability to clock the PFD at up to 250 MHz results

in an integrated jitter (at 12 kHz to 20 MHz) of 44.0 fs typical.

Rev. B | Page 30 of 72

Data Sheet

HMC7044

VCO Selection, External VCO Use

Apply the SYNC input rising edge only once. After sensing the

rising edge on the VCXO domain, the SYNC input is ignored

for the next 16 × 6 t_PD2periods as the FSM processes the event.

After this period expires, the FSM becomes sensitive again to

the SYNC pin. If the SYNC is applied periodically, the first edge

initializes the synchronization process, and then the subsequent

edges may or may not be recognized depending on their

~2.5GHz

VCO

VCO ENABLE[1:0] = 10

TO PLL2

N2 DIVIDER

AUTOCAL

~3.0GHz

VCO

VCO ENABLE[1:0] = 01

width/repetition rate with respect to 16 × 6 t_PD2

Note that the SYNC rising edge must be provided cleanly with

OSCIN

.

TO

OUTPUT

NETWORK

respect to the HMC7044 VCXO input pin (OSCIN/

CLKINx

).

pins of

CLKIN1/CLKIN1

IN EXTERNAL VCO

INPUT MODE = 1

The user normally has access to the CLKINx/

PLL1, and not to the VCXO signal directly. When PLL1 is locked,

however, the VCXO rising edge is roughly aligned to the PLL1

active reference, and, therefore, the user has indirect knowledge

of the phase of the VCXO. The VCXO is also available as an

output of the HMC7044, if the user wants to retime the SYNC

signal more directly.

÷2

DIVIDE BY 2 ON

EXTERNAL VCO ENABLE

Figure 43. VCO Input Network

The phase offset of the PLL1 active reference with respect to the

VCXO is a function of the internal delay of each path. This base

delay offset is a function of deterministic conditions (LCM, R1,

N1 divider setpoints, termination setups, and slew rates), but is also

subject to PVT variations that compress or exaggerate this offset.

VCO Calibration

The on-board VCOs contain an AGC loop that regulates the

core voltage of the oscillator to achieve the desired swing and

thus the trade-off between phase-noise and power consump-

tion. This AGC loop uses large external bypass capacitors to

eliminate the noise impact of the AGC loop, and therefore takes

time to settle after power-up, sleep, or after changing the VCO

Selection[1:0] setting. With the 100 nF/1 μF configuration,

settling time takes approximately 10 ms (typical).

For most practical purposes, the multichip synchronization

feature is limited to PLL1 reference rates <200 MHz.

CLOCK OUTPUT NETWORK

In the HMC7044, PLL1 is responsible for frequency cleanup,

redundancy, and hitless switching. PLL2 and the VCOs handle

integrated jitter and performance at an 800 kHz offset. Although

the PLL1/PLL2 and VCXO components are important, much of

the uniqueness of a JESD204B clock generation chip relates to

its array of output channels.

Each of the VCOs in the HMC7044 has 32 frequency bands.

Normally, three or more subbands can synthesize any particular

frequency, and an on-board autotune algorithm selects the solution

that provides tuning margin for temperature fluctuations. Temp-

erature compensation is applied inside to ensure the device can

be calibrated at any frequency and maintain lock as the frequency is

carried to any other frequency in the operating range.

In a device such as the HMC7044, some of the output network

requirements include the following:

•

Very good phase noise floor of the DCLK channels that can

be connected to critical data converter sample clock inputs

A large number of DCLK and SYSREF channels

Deterministic phase alignment between all output channels

relative to one another

Fine phase control of synchronization channels with

respect to the DCLK channel

Frequency coverage to satisfy typical clock rates in

expectant systems

Skew between SYSREF and DCLK channels that is much

less than a DCLK period

Spur and crosstalk performance that does not impact

system budgets

The autotune is triggered by toggling the restart dividers/FSMs

bit in Register 0x0001, Bit 1, after R2 and N2 are programmed,

the VCXO is applied, and the VCO peak detector loop has settled.

•

When the VCXO is applied to the system and the R2 and N2

divide ratios are programmed, the autotune algorithm has the

information needed to find the appropriate band of the VCO.

•

Multichip Synchronization via PLL2

To synchronize multiple HMC7044 devices together, it is recom-

mended to use the SYNC input pin. If the SYNC pin transitions

from 0 to 1 with sufficient setup/hold margin with respect to the

VCXO, this synchronization event is deterministically carried

through PLL2, up the timing chain through the N2 divider, and

then to the master SYSREF timer (see the Clock Output Network

section for more information). This mechanism of deterministic

phase adjustment allows synchronization of the SYSREF timer

and output phases of multiple HMC7044 devices.

Rev. B | Page 31 of 72

HMC7044

Data Sheet

The HMC7044 output network also supports the following

recommended features, which are sometimes critical in user

applications:

Each of the 14 output channels are logically identical. The only

distinction between the SYSREF and DCLK channels is in the

SPI configuration and in how they are used. Each channel

contains independent dividers, phase adjustment, and analog

delay circuits. This combination provides the ultimate flexibility,

cleanly accommodating nonJESD204B devices in the system.

•

Deterministic synchronization of the output channels with

respect to an external signal, which allows multichip

synchronization and clean expansion to larger systems

Pulse generator behavior to temporarily generate a

synchronization pulse stream at user request

Flexibility to define unused JESD204B SYSREF and DCLK

channels for other purposes

In addition to the 14 output channel dividers, there is an internal

SYSREF timer that continually operates, and the synchronization

of the output channel dividers occurs deterministically with respect

to this timer, which can be rephased externally by the user.

•

Glitchless phase control of signals relative to each other

50% duty cycle clocks with odd division ratios

Multimode output buffers with a variety of swings and

termination options

Skew between all channels that is much less than a DCLK

period

Adjustable performance vs. power consumption for less

sensitive clock channels

Flexibility to use an external VCO for very high

The pulse generator functionality of the JESD204B standard

involves temporarily generating SYSREF output pulses, with

appropriate phasing, to downstream devices. The centralized

SYSREF timer and its associated SYNC/pulse generator control

manage the process of enabling the intended SYSREF channels,

phasing them, and then disabling them for signal integrity and

power saving advantages.

•

performance application requirements

SYSREF INPUT NETWORK

SYNC FROM PLL2 N DIVIDER

(DUE TO SYNC PIN EVENT)

RF SYNC

D

Q

RESET

SYSREF

TIMER

VCO PATH

SYNC/

PULSE GENERATOR

CONTROL

PULSE GENERATOR REQUEST (FROM SPI, GPI, OR SYNC PIN)

SYNC REQUEST (FROM SPI OR GPI)

SYNC_FSM_STATE

OUTPUT CHANNEL × 14

LEAF

CONTROLLER

CLOCK

GATING

DIGITAL DELAY

AND RETIME

DIVIDER

Figure 44. Clock Output Network Simplified Diagram

Rev. B | Page 32 of 72

Data Sheet

HMC7044

Basic Output Divider Channel

System wide broadcast signals can be triggered from the SPI or

general-purpose input (GPI) port to issue a SYNC command

(to align dividers to the system internal SYSREF timer), issue a

pulse generator stream, (temporarily exporting SYSREF signals to

receivers), or to cause the dividers to slip a number of VCO

cycles to adjust their phases.

Each of the 14 output channels are logically identical, and support

divide ratios from 1 to 4094. The supported odd divide ratios

(1, 3, 5) have 50.0% duty cycle. The only distinction between a

SYSREF channel and a DCLK channel is in the SPI configura-

tion and the typical usage of a given channel.

Individual dividers can be made sensitive to these events by

adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]

configuration, as described in Table 16.

For basic functionality and phase control, each output path

consists of the following:

•

Divider—generates the logic signal of the appropriate

frequency and phase

Digital phase adjust—adjusts the phase of each channel in

increments of ½ VCO cycles

Retimer—a low noise flip flop to retime the channel,

removing any accumulated jitter

When output buffers are configured in CMOS mode and phase

alignment is required among the outputs, additional multislip

delays must be issued for Channel 0, Channel 3, Channel 5,

Channel 6, Channel 9, Channel 10, and Channel 13. The value

of the delay must be as large as half of the selected divider ratio.

Note that this requirement of having additional multislip delays

is not needed when channels are used in LVPECL, CML or

LVDS mode.

•

Analog fine delay—provides a number of ~25 ps delay steps

Selection mux—selects the fundamental, divider, or analog

delay, or an alternate path

If a channel is configured to behave as a pulse generator, to

temporarily power up and power down according to GPI, SPI,

or SYNC pin pulse generator commands, it has additional

controls to define its behavior outside of the pulse generator

chain (see Table 17).

•

Multimode output buffer—low noise LVDS, CML, CMOS,

or LVPECL

The digital phase adjuster and retimer launch on either clock

phase of the VCO, depending on the digital phase adjust setpoint

(Coarse Digital Delay[4:0]).

Each divider has an additional phase offset register that adjusts

its start phase, or to influence the behavior of slip events sent

via the SPI (see Table 18).

To support divider synchronization, arbitrary phase slips, and

pulse generator modes, the following blocks are included:

•

A clock gating stage pauses the clock for synchronization

or slip operations

An output channel leaf (×14) controller manages slip,

synchronization, and pulse generators with information

from the SYSREF FSM

Table 19 outlines the typical configuration combinations for a

DCLK channel relative to a SYSREF synchronization channel.

Note that other combinations are possible. Synchronization of

downstream devices can be managed manually, or by using the

pulse generator functionality of the HMC7044. See the Typical

Programming Sequence section for more information about the

differences between the two methods.

•

Each channel has an array of control signals. Some of the controls

are described in Table 15.

Rev. B | Page 33 of 72

HMC7044

Data Sheet

Table 15. Basic Divider Controls

Bit Name

Description

Channel Enable

Channel enable. If 0, the channel is disabled. If 1, the channel can be enabled depending on the settings of

Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode.

12-Bit Channel Divider[11:0] Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider

(Output Mux Selection[1:0] = 2 or 3).

High Performance Mode

High performance mode. Adjusts divider and buffer bias to slightly improve swing/phase noise at the

expense of power. The performance advantage is about 1 dB, and the current penalty depends on whether

the divider is enabled.

Coarse Digital Delay[4:0]

Fine Analog Delay[4:0]

Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the VCO. This circuit is practically

noiseless; however, note that a low amount of additional current is consumed.

Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] =

1 to expose this channel. Causes phase noise degradation of up to 12 dB; therefore, do not use on noise sensitive

DCLK channels.

Output Mux Selection[1:0]

Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input VCO

clock. Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output

Mux Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and

degrades phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic

skew vs. a path that is divider based. Such skew can be compensated for with delay (digital and analog) on

the divider-based path.

Table 16. Channel Features

Bit Name

Description

Slip Enable

Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated

following a recognized SYNC or pulse generator startup).

SYNC Enable

SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via

the SYSREF FSM) to reset its phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without

risking the state of the divider.

Start-Up Mode[1:0] 00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC

enable = 1.

11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF

controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the

pulse generator chain. This is only supported for divide ratios > 31.

Table 17. Pulse Generator Mode Behavior Options

Bit Name

Description

Dynamic Driver Enable Dynamic output buffer enable (pulse generator mode only).

0 = the output buffer is simply enabled/disabled with the main channel enable.

1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power

down outside pulse generator events.

Force Mute[1:0]

Force mute for dynamic mode. If 10, and the channel enable is true (channel enable = 1), the signal just before the

output buffer is asynchronously forced to Logic 0 when not generating pulses. Otherwise, if 00, outputs are forced

to float naturally to V_CM. To see the effect of this, the output buffer must be enabled, which is dependent on the

dynamic driver enable and Start-Up Mode[1:0] controls. Logic 0 is supported for CML, LVPECL and CMOS driver modes.

Rev. B | Page 34 of 72

Data Sheet

HMC7044

Table 18. Multislip Configuration

Bit Name

Description

Multislip Enable

Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used for multislip

operations. Note that a multislip operation is automatically started following a SYNC or pulse generator initiation if

multislip enable = 1.

Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator events) repeat the

number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the multislip amount × VCO cycles. A

value of 0 is not supported if multislip enable = 1. Note that phase slips are free from a noise and current perspective,

that is, no additional power is needed and with no noise degradation, but they take some time to occur. Each slip

operation takes a number of nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. An

alarm is available for the user to indicate when all phase operations are complete.

12-Bit Multislip Digital

Delay[11:0]

Table 19. Typical Configuration Combinations

Pulse Generator

SYSREF

Bit Name

DCLK

Manual SYSREF

Big

NonJESD204B

Any

Normal

12-Bit Channel Divider[11:0]

Start-Up Mode Bit

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

Slip Enable

Multislip Enable

High Performance Mode

Sync Enable

Small

Normal

Off

Optional

On

Big

Pulse generator

Normal

Optional

Off

On

Don’t care

Optional

Off

On

Off

Optional

Don’t care

Dynamic Driver Enable

Force Mute[1:0]

Don’t care

On

Synchronization FSM/Pulse Generator Timing

Figure 46 shows the start-up behavior of an example divider

that is configured as a pulse generator, with a period matching

the internal SYSREF period.

The block diagram showing the interface of the SYNC/pulse

generator control to the divider channels and the internal

SYSREF timer is shown in Figure 44.

The startup of the pulse stream occurs a fixed number of VCO

cycles after the FSM transitions to the start phase. Disabling the

pulse generator stream where the logic path is forced to zero

comes from a combinational path, directly from the FSM.

The SYSREF timer counts in periods defined by SYSREF

Timer[11:0], a 12-bit setting from the SPI. It sequences the enable,

reset, and startup, and disables the downstream dividers in the

event of SYNC or pulse generator requests. Program the SYSREF

timer count to a submultiple of the lowest output frequency in

the clock network, and not faster than 4 MHz. To synchronize

divider channels, it is recommended, though not required, that

the SYSREF Timer[11:0] bits be set to a related frequency that is

either a factor or multiple of other frequencies on the IC.

Because the divider has the option for nearly arbitrary phase

adjustment, it provides the opportunity for the stop condition

to arrive when the pulse stream is a Logic 1, and creates a runt

pulse.

For phase offsets of zero to 50% − 8 VCO cycles, and VCO

frequencies <3 GHz, this condition is met naturally within the

design. For fanout only mode >3 GHz, it is recommended to

use digital delay or slip offsets to increase the natural phase

offset and avoid the stress condition.

The pulse generator is defined with respect to the periods of

this SYSREF timer, not with respect to the output period. This

leads to timing constraint that must be considered to prevent

any runt pulses from affecting the pulse generator stream.

The situation is avoided by never applying phase offset more

than 50% − 8 VCO cycles to an output channel configured as a

pulse generator.

Rev. B | Page 35 of 72

HMC7044

Data Sheet

RF_SYNC OR PLL2 SYNC

RESET

NOTIFY CHANNEL FSM

WHAT TYPE OF EVENT

IS COMING

PULSE

GENERATOR

SETUP

SYNC

SETUP

POWER DIVIDERS/SYNC BLOCKS,

PAUSE BLOCKS, RESET LATCHES

CLEAR

REMOVE LATCH RESET,

PREPARE TO START CLOCKS

WAIT

SYNC

REQUEST

START CLOCKS,

STARTUP

WITH CLEAN TIMING,

SMALL PIPELINE DELAY

PULSE

GENERATOR

TIMEOUT?

WAIT UNTIL THE NUMBER OF

PULSE GENERATOR CYCLES

EXPIRES

DONE

REMOVE POWER

PULSE

GENERATOR

REQUEST

Figure 45. Synchronization FSM Flowchart

FSM STATE

STARTUP

PULSE GENERATOR = 2

DONE

DIVIDER CHANNEL

IF MUTE SIGNAL ARRIVES QUICKLY

RELATIVE TO SIGNAL TRAIN,

NO RUNT PULSE

FIXED NUMBER OF VCO CYCLES

FROM STATE CHANGE TO STARTUP, AND

ANY INTENTIONAL DIGITAL/ANALOG OFFSET

FSM STATE

STARTUP

PULSE GENERATOR = 2

DONE

DIVIDER CHANNEL

IF CONTROL IS TOO LATE

RELATIVE TO SIGNAL TRAIN,

THERE IS A RUNT PULSE

Figure 46. Start-Up Behavior of an Example Divider Configured as a Pulse Generator

Clock Grouping, Skew, and Crosstalk

As the output channels are more tightly coupled (by sharing a

clock group, or by sharing a supply pin), the skew is minimized.

However, the isolation between those channels suffers. Table 20

shows the clock grouping, and Table 21 show the typical skew

and isolation that can be expected and how it scales with distance

between output channels.

Although the output channels are logically independent, for

physical reasons, they are first grouped into pairs called clock

groups. Each clock group shares a reference, an input buffer,

and a sync retime flip flop originating from the VCO

distribution network.

Isolation improves as either the aggressor or affected frequencies

decreases. Nevertheless, for particularly important clock channels

where spurious tones must be minimized, carefully consider

their frequency and channel configurations to isolate continu-

ously running frequencies onto different supply domains.

Channels configured as pulse generators are normally not an

issue, because they are disabled during normal operation.

The second level of grouping is according to the supply pin.

Clock Group 1 (Channel 2 and Channel 3) are on an independ-

ent supply, and the other supply pins are each responsible for

two clock groups.

Rev. B | Page 36 of 72

Data Sheet

HMC7044

NORTHWEST

NORTH

Table 20. Supply Pin Clock Grouping by Location

Supply Pin

Location

Clock Group

Channel

VCC2_OUT

Southwest

1

2

3

CLKOUT0,

CLKOUT0

VCC7_PLL2

CPOUT2

VCC4_OUT

VCC8_OUT

VCC9_OUT

South

2

3

4

5

6

0

4

SCLKOUT1,

SCLKOUT1

5

LDOBYP7

RESET AND SYNC

BGABYP1

6

7

OSCIN, OSCIN

LDOBYP6

LDOBYP2

OSCOUT1,

OSCOUT1

North

8

LDOBYB3

9

CLKIN2/OSCOUT0,

CLKIN2/OSCOUT0

VCC1_VCO

LDOBYP4

10

11

12

13

0

VCC6_OSCOUT

CLKIN0/RFSYNCIN,

CLKIN0/RFSYNCIN

LDOBYP5

Northwest

SCLKOUT3,

SCLKOUT3

CLKOUT2,

CLKOUT2

VCC5_PLL1

CLKIN1/FIN,

CLKIN1/FIN

VCC2_OUT

1

Table 21. Typical Skew and Isolation vs. Distance

SOUTH

Typical

1 GHz Isolation

SOUTHWEST

Distance

Skew (ps)

Differential (dB)

90 to 100

70

Figure 47. Clock Grouping

Distant Supply Group

Closest Neighbor on

20

15

SYSREF Valid Interrupt

One of the challenges in a JESD204B system is to control and

minimize the latency from the primary system controller IC,

typically an ASIC or FPGA, to the data converters. To estimate

the correct amount of latency in the system, the designer must

know how long it takes for a master clock generator like the

HMC7044 to provide the correct output phases at each output

channel after receiving the synchronization request. Typically, a

period of time is required on the device to implement the

change requests on the outputs due to internal state machine

cycles, data transfers, and any propagation delays. The SYSREF

valid interrupt is a function to notify the user that the correct

output settings and phase relationships are established, allowing

the user to identify quickly that the desired SYSREF and device

clock states are presented at the outputs of the HMC7044.

Different Supply Group

Shared Supply

Same Clock Group

10

60

45

Output Buffer Details

Figure 47 shows the clock groups by supply pin location on the

package. With appropriate supply pin bypassing, spurious noise

of the outputs is improved. Table 20 describes how the supply

pins of each of the 14 clock channels are connected within the

seven clock groups. Clock channels that are closest to each

other have the best channel to channel skew performance, but

they also have the lowest isolation from each other. Select

critical signals that require high isolation from each other from

groups with distant supply pin locations. An example of the

expected isolation and channel to channel skew performance of

the HMC7044 at 1 GHz is provided in Table 21.

The user has the flexibility to assign the SYSREF valid interrupt

to a GPO pin or to use a software flag, set via Register 0x007D,

Bit 2, which the user can poll as necessary. The flag notifies the

user when the system is configured and operating in the desired

state, or conversely when it is not ready.

Rev. B | Page 37 of 72

HMC7044

Data Sheet

Single-Ended Operation

REFERENCE BUFFER DETAILS

The buffers support single-ended signals with a slightly reduced

input sensitivity and bandwidth. If driving these buffers single-

ended, ac couple the unused section of the buffer to ground at

the input of the die.

Input Termination Network—Common for All Input

Buffers

The four reference input buffers to PLL1, as well as the VCXO

input buffer, share similar architecture and control features. The

input termination network is configurable to 100 Ω, 200 Ω, and

2 kΩ differentially. It is typically ac-coupled on the board, and

uses the on-chip resistive divider to set the internal common-

mode voltage, V_CM, to 2.1 V.

Maximum Signal Swing Considerations

The internal supplies to these buffers are regulated from 3.3 V

to 2.8 V using on-chip regulation. With very high power

references, the signal swing can be enough to drive the signal

above the 2.8 V rail. The ESD network and parasitic diodes are

generally able to shunt the excess power, and protect the

internal circuits even above 13 dBm. Nevertheless, to protect

from latch-up concerns, the signals on reference inputs must

not exceed the 2.8 V internal supply. For a 2.1 V common-

mode, 50 Ω single-ended source, this 2.8 V limit allows

~700 mV of amplitude, or 6 dBm of maximum reference power.

By closing the 50 Ω termination switch (see Figure 48), the

network also serves as the termination system for an LVPECL

driver. Although the input termination network for the four

PLL1 reference buffers and the VCXO input buffer is identical,

the buffer behind the network is different.

2.8V

50Ω,

100Ω,

1kΩ

4kΩ

TYPICAL PROGRAMMING SEQUENCE

To initialize the HMC7044 to an operational state, use the

following programming procedure:

5kΩ

1pF

50Ω,

100Ω,

1kΩ

50Ω

1. Connect the HMC7044 to the rated power supplies. No

specific power supply sequencing is necessary.

2. Release the hardware reset by switching from Logic 1 to

Logic 0) when all supplies are stable.

3. Load the configuration updates (provided by Analog

Devices) to specific registers (see Table 74).

4. Program PLL2. Select the VCO range (high or low). Then

program the dividers (R2, N2, and reference doubler).

5. Program PLL1. Set the lock detect timer threshold based

on the PLL1 BW of the user system. Set the LCM, R1, and

N1 divider setpoints. Enable the reference and VCXO

input buffer terminations.

6. Program the SYSREF timer. Set the divide ratio (a submultiple

of the lower output channel frequency). Set the pulse

generator mode configuration, for example, selecting level

sensitive option and the number of pulses desired.

7. Program the output channels. Set the output buffer modes

(for example, LVPECL, CML, and LVDS). Set the divide

ratio, channel start-up mode, coarse/analog delays, and

performance modes.

Figure 48. On-Chip Termination Network for VCXO and Reference Buffers

PLL1 Reference Buffer Stages

The PLL1 reference buffers use a CMOS input stage, are capable

of a wide common-mode input range (0.4 V to 2.4 V), and have

hysteresis to support reliable LOS detection. These buffers are

designed to be driven reliably with an input swing of >375 mV p-p

diff (the half swing point of the LVDS standard), and support up to

800 MHz operation. For signal swings that are below 375 mV p-p

diff, the hysteresis of the buffer can engage and shut down the

signal to the internal reference paths. The exact input hysteresis

threshold varies as a function of common-mode level and input

frequency, but generally ranges from about 75 mV p-p diff to

300 mV p-p diff.

VCXO Buffer Stage

The VCXO input buffer is implemented with a bipolar input

stage to meet the stringent noise requirements of PLL2. Its

common-mode input range is tighter and, if set externally, must

be kept between 1.6 V and 2.4 V. This buffer does not have

hysteresis and is functional down to very low signal levels.

Although the buffer remains functional down to these low

signal levels, for optimal performance, keep the input power

greater than −4 dBm when driven single-ended, or −7 dBm per

side when driven differentially.

8. Wait until the VCO peak detector loop has stabilized

(~10 ms after Step 4).

9. Ensure that the references are provided to PLL1 and the

VCXO is powered.

10. Issue a software restart to reset the system and initiate

calibration. Toggle the restart dividers/FSMs bit to 1 and

then back to 0.

11. PLL1 starts to lock in parallel with PLL2 going through its

calibration and lock procedure. Wait for PLL2 to be locked

(takes ~50 μs in typical configurations).

Recommendations for Normal Use

For both styles of buffer, unless there are extenuating circum-

stances in the application, use the 100 Ω differential termination to

control reflections, use the on-chip dc bias network to set the

common-mode level, and externally ac couple the input signals.

Do not use receiver side dc termination of the LVPECL signal.

12. Confirm that PLL2 is locked by checking the PLL2 lock

detect bit.

Rev. B | Page 38 of 72

Data Sheet

HMC7044

13. Send a sync request via the SPI (set the reseed request bit)

to align the divider phases and send any initial pulse

generator stream.

14. Wait 6 SYSREF periods (6 × SYSREF Timer[11:0]) to allow

the outputs to phase appropriately (takes ~3 μs in typical

configurations).

POWER SUPPLY CONSIDERATIONS

The HMC7044 contains on-board regulators to shield some of

the more sensitive supplies from external noise and interference

as much as possible. Nevertheless, the user must still take

special care to the supply noise profile of the VCC1_VCO

supply to achieve the intended performance of the device.

15. Confirm that the outputs have all reached their phases by

checking that the clock outputs phases status bit = 1.

16. At this time, initialize any other devices in the system.

PLL1 may not be locked yet, but the small frequency offset

that can result on the output of the HMC7044 is not normally

severe enough to cause synchronization or initialization

failures. Configure slave JESD204B devices in the system to

operate with the SYSREF signal outputs from the HMC7044.

SYSREF channels from the HMC7044 can either be on

asynchronously, or dynamically, and can temporarily turn

on for a pulse generator stream.

17. Wait for PLL1 to lock. This takes ~50 ms for a 100 Hz BW

(from Step 11).

18. When all JESD204B slaves are powered and ready, send a

pulse generator request to send out a pulse generator chain

on any SYSREF channels programmed for pulse generator

mode.

In general, a flat input noise of 200 nV/Hz is an equivalent

contributor to the VCO noise and causes a 3 dB increase in the

noise profile from about 100 kHz to 10 MHz when the VCO is

the dominant contributor. This increase equates to a roughly

one-to-one conversion from dBV to dBc/Hz at a 1 MHz offset,

and f_OUT= 2.457 GHz, that is, 200 nV/Hz = −134 dBV, and the

performance of the VCO at 1 MHz offset at 2.4576 GHz is

~−134 dBc/Hz. The PSRR of the VCO follows its closed-loop

noise profile; therefore, as the offset moves in and the VCO

profile becomes higher, the 200 nV/Hz noise stays approximately

equal to the VCO. To stay suitably below the VCO, a supply

input with <50 nV/Hz is recommended on the VCC1_VCO pin

across the 100 kHz to 10 MHz frequency range.

The output buffers are also susceptible to supply noise, but to a

lesser extent. A noise tone of −60 dBV at a 40 MHz offset results

in a −90 dBc tone at the output of the buffers in CML mode and

−85 dBc in LVPECL mode. This result is a relatively flat frequency

response, and these numbers are measured differentially. Phase

noise/spurs caused by supply noise on the output buffers do not

scale with output frequency, whereas those on the VCO do.

The system is now initialized.

For power savings and the reduction of the crosscoupling of

frequencies on the HMC7044, shut down the SYSREF channels.

1. Program each JESD204B slave to ignore the SYSREF input

channel.

2. On the HMC7044, disable the individual channel enable

bits of each SYSREF channel.

Table 22 lists the supply network of the HMC7044 by pin,

showing the relevant functional blocks. Six different usage

profiles are defined for the network, not including the output

channel supplies, which are accounted for separately.

To resynchronize one or more of the JESD204B slaves, use the

following procedure:

The values listed under Profile 0 to Profile 5 in Table 22 and

Table 23 are the typical currents of that block or feature. If a

number is not listed in a profile column, a typical profile does

not exist for that block or feature, but the user can mix and

match features outside of the profile list, and can determine what

the power consumption is going to be given the current listings

per feature.

1. Set the channel enable (and SYNC enable bit) of the

SYSREF channel of interest.

2. To prevent an output channel from responding to a sync

request, disable the SYNC enable mask of each channel so

that it continues to run normally without a phase

adjustment.

3. Issue a reseed request to phase the SYSREF channel

properly with respect to the DCLK.

4. Enable the JESD204B slave sensitivity to the SYSREF

channel.

5. If the SYSREF channel is in pulse generator mode, wait at

least 20 SYSREF periods from Step 3, and issue a pulse

generator request.

Rev. B | Page 39 of 72

HMC7044

Data Sheet

Table 22. Supply Network of the HMC7044 by Pin for PLL1, PLL2, VCO, and SYSREF

Profile¹

Typical Current

(mA)

Circuit Block

Comment

0

1

2

3

4

5

VCC5_PLL1

CLKIN1/CLKIN1

CLKIN1/CLKIN1 Buffer

Used as a PLL1 reference

2

5

2

5

2

5

Extra if used as buffer for external

VCO

CLKIN0/CLKIN0

Used as a PLL1 reference

2

5

2

CLKIN0/CLKIN0 Buffer

Extra current if used as RF

synchronization buffer²

External VCO Path (f_OUT

External VCO Path

External RF Synchronization Path³

Regulator to 1.8 V, Bypassed on LDOBYP2

PLL1 Functions

PLL2 Functions

SYSREF Timer

GPO Drivers in High Speed Mode⁴

Regulator to 2.8 V, Bypassed on LDOBYP3

PLL1 PFD/CP

)

18

10

3

18

Extra current for divide by 2

N2, digital functions

LOS, R1, N1, FSMs

R2, N2, lock detect

2

10

2

10

17

1

10

17

1

17

2

7

2

7

2

7

2

PLL1 DAC Holdover Circuits

CLKIN2/CLKIN2 Buffer

2

CLKIN3/CLKIN3 Buffer

2

Subtotal for VCC5_PLL1

VCC7_PLL2

Regulator to 2.8 V, Bypassed on LDOBYP7

90

4

49

23 21

46

11

2

21

2

4

2

21

2

21

PLL2 PFD, Doubler, and R2 and N2

Outputs

21

PLL2 Charge Pump

Regulator to 2.8 V, Bypassed on LDOBYP6

VCXO Buffer

OSCOUTx/OSCOUTx Divider/Mux⁵

Subtotal for VCC7_PLL2

VCC1_VCO

VCO Distribution Network

Sync Retiming Network

VCO Regulator, Bypass to LDOBYP4 and

LDOBYP5

8

2

16

8

2

16

8

2

8

2

16

2

16 16

57

8

49

71

84

20 49

49

71

4

Minimum possible value

Minimum possible value⁶

71

8

84

0

71

84

71

VCO Core

Subtotal for VCC1_VCO

163

8

155

155 71

71

VCC3_SYSREF

SYSREF Input Network³

SYSREF Counter Base

SYSREF Counter, SYNC network

Subtotal for VCC3_SYSREF

Subtotal (Without Output Paths)

11

12

4

12

27

0

20 265 43 225 166 98

¹Profile 0 = sleep mode; Profile 1 = power-up defaults, PLL1 with four references and PLL2 locked with internal VCO, SYSREF timer running; Profile 2 = PLL1 only, one

reference; Profile 3 = PLL2 + VCO, PLL1 disabled, Profile 4 = PLL2 with external VCO, PLL1 disabled, Profile 5 = fanout mode only, SYSREF running.

2

CLKIN0

This is the incremental amount of current for the circuit when put in this mode. For example, the CLKIN0/

used as the external synchronization buffer instead, it is 2 + 5 mA.

buffer used for PLL1 reference path is 2 mA. If it is

³The transient current in PLL2 synchronization mode can be temporarily enabled when using external synchronization.

⁴The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of

~100 Ω to minimize the IR drop on the internal regulator during transitions.

⁵The function varies from 8 mA to 14 mA depending on divide ratio.

⁶A temporary current only.

Rev. B | Page 40 of 72

Data Sheet

HMC7044

Table 23. Supply Network of the HMC7044 by Pin for the Clock Output Network

Profile¹

Per Output Channel

Comment

Typical Current (mA)

0

1

2

3

4

Digital Regulator and Other Sources

2.5

0.5

2.5 2.5

2.5

Buffer

LVPECL

Including term currents

43

43 43

43

CML100

High Power

Low Power

LVDS

31

24

High Power

Low Power

CMOS

At 307 MHz

10

At 100 MHz, both sections

25

Included²

Channel Mux

Digital Delay

Off

Setpoint > 1

Analog Delay

Off

Included²

3

9

Included²

0

Minimum Setting

Maximum Setting

Divider Logic

0

Glitchless mode enabled

Not using divider path

9

Included²

0

÷1

÷2

÷3

÷4

27

31

29

32

29

30

31

32

4

÷5

÷6

÷8

÷16

÷32

31

÷2044

32

92

SYNC Logic³

Slip Logic³

Subtotal

4

2.5 48 89

13

¹Profile 0 = sleep mode; Profile 1 = fundamental mode; Profile 2 =SYSREF channel matched to fundamental mode; Profile 3 = LVDS—high power signal source from

other channel; Profile 4 = worst case configuration for power consumption of a channel.

²The base current consumption of the circuit (for example, mux) is included in the buffer typical current.

³Currents occur only temporarily during a synchronization event.

Rev. B | Page 41 of 72

HMC7044

Data Sheet

SERIAL CONTROL PORT

4. The host registers the 8-bit data on the next eight rising

edges of SCLK. The HMC7044 places 8-bit data (D7 to D0)

MSB first on the next eight falling edges of SCLK.

SERIAL PORT INTERFACE (SPI) CONTROL

The HMC7044 can be controlled via the SPI using 24-bit

registers and three pins: serial port enable (SLEN) serial data

input/output (SDATA), and serial clock (SCLK).

5. Deassertion of SLEN completes the register read cycle.

Typical Write Cycle

The 24-bit register, shown in Table 24, consists of the following:

A typical write cycle is shown in Figure 49, and occurs as

follows:

•

1-bit read/write command

2-bit multibyte field (W1, W0)

13-bit address field (A12 to A0)

8-bit data field (D7 to D0)

1. The master (host) asserts both SLEN and SDATA to

indicate a read, followed by a rising edge SCLK. The slave

(HMC7044) reads SDIO on the first rising edge of SCLK

after SLEN. Setting SDATA low initiates a write.

2. The host places the 2-bit multibyte field to be written to

low (0) on the next two falling edges of SCLK. The

HMC7044 registers the 2-bit multibyte field on the next

two rising edges of SCLK.

Table 24. SPI Bit Map

MSB

LSB

Bit 23

Bit 22

Bit 21

Bits[20:8]

Bits[7:0]

D7 to D0

R/W

W1

W0

A12 to A0

Typical Read Cycle

3. The host places the13-bit address field (A12 to A0), MSB

first on SDATA on the next 13 falling edges of SCLK. The

HMC7044 registers the 13-bit address field (MSB first) on

SDIO over the next 13 rising edges of SCLK.

4. The host places the 8-bit data (D7 to D0) MSB first on the

next eight falling edges of SCLK. The HMC7044 register

the 8-bit data (D7 to D0) MSB first on the next eight rising

edges of SCLK.

A typical read cycle is shown in Figure 48 and occurs as follows:

1. The master (host) asserts both SLEN and SDATA to

indicate a read, followed by a rising edge SCLK. The slave

(HMC7044) reads SDATA on the first rising edge of SCLK

after SLEN. Setting SDATA high initiates a read.

2. The host places the 2-bit multibyte field to be written to

low (0) on the next two falling edges of SCLK. The

HMC7044 registers the 2-bit multibyte field on the next

two rising edges of SCLK.

3. The host places the 13-bit address field (A12 to A0) MSB

first on SDATA on the next 13 falling edges of SCLK. The

HMC7044 registers the 13-bit address field (MSB first) on

SDATA over the next 13 rising edges of SCLK.

5. The final rising edge of SCLK performs the internal data

transfer into the register file, updating the configuration of

the device.

6. Deassertion of SLEN completes the register write cycle.

1

2

3

4

5

16

17

18

24

SCLK

X

READ W1

W0

A12 A11

A0

D7

D6

D0

SDATA

SLEN

Figure 49. SPI Timing Diagram, Read Operation

1

2

3

4

5

24

16

17

18

SCLK

WRITE

X

W1

W0

A12 A11

A0

D7

D6

D0

SDATA

SLEN

Figure 50. SPI Timing Diagram, Write Operation

Rev. B | Page 42 of 72

Data Sheet

HMC7044

APPLICATIONS INFORMATION

where:

Floor_FOM is the figure of merit at the floor frequency.

_PD2is the phase detector frequency of PLL2.

Calculate the total phase noise (unfiltered) as follows:

PLL1 NOISE CALCULATIONS

Use the following equations to calculate the flicker noise, noise

floor, and total unfiltered phase noise specifications for PLL1

(see Table 4).

f

PN

(

f_OUT, f_PD2, f_OFFSET=

)

Calculate the flicker noise using the following equation:

2







PN(f_OUT, f_OFFSET) = Flicker_FOM + 20 × log(f_OUT) – 10 ×

PN _ Flicker

PN _ Floor

10













(6)

+10^^







10



10×log 10^

log(f_OFFSET

where:

PN() is the phase noise.

)

(1)











where:

f

_OUTis the output frequency.

_OFFSETis the offset of noise frequency from the output carrier

PN_Flicker is the phase noise at the flicker frequency.

PN_Floor is the phase noise at the floor frequency.

frequency.

PHASE NOISE FLOOR AND JITTER

Flicker_FOM is the figure of merit at the flicker frequency.

Use the following equations to calculate the phase noise floor,

jitter density, and rms additive jitter due to floor specifications

(see Table 9).

Calculate the noise floor as follows:

PN

(

f_OUT, f_PD1

)

=

(2)













f_OUT

f_PD1

Calculate the phase noise floor using the following equation:

Floor_ FOM + 20×log

−10×log

(

f_PD1

)

PN_FLOOR= FOM_OCHAN+ 10 × log(f_OUT) + Harmonic

where:

_PD1is the phase detector frequency of PLL1.

Degradation + Power Degradation

(7)

f

where:

PN_FLOORis the phase noise floor at f_OUT

Floor_FOM is the figure of merit at the floor frequency.

.

Calculate the total phase noise (unfiltered) as follows:

FOM_OCHANis the figure of merit of the output channel.

Harmonic Degradation is the harmonics of the signal captured

in the measurement bandwidth of the receiving

instrument/circuit. The noise power of those harmonics can

fold and influence the overall noise.

Power Degradation results when the noise floor (−174 dBm/Hz)

of the measurement system approaches the noise power in the

phase noise floor of the signal. For example, a phase noise value

of−155 dBc/Hz at 0 dBm carrier level is −155 dBm/Hz and is

easily measurable. If, however, the carrier level is −20 dBm, the

phase noise of –155 dBc/Hz is −175 dBm/Hz, and is not

measurable below the other noise sources in the system.

PN

(

f_OUT, f_PD1, f_OFFSET=

)

2







PN _ Flicker

PN _ Floor













(3)

+10^^







10



10×log 10^











where:

PN_Flicker is the phase noise at the flicker frequency.

PN_Floor is the phase noise at the floor frequency.

PLL2 NOISE CALCULATIONS

Use the following equations to calculate the flicker noise, noise

floor, and total unfiltered phase noise specifications for PLL2

(see Table 5).

Calculate the jitter density at f_OUTas follows:

PN

10

floor











Calculate the flicker noise using the following equation:

f

_OUT×2π

JITTER _ DENSITY _ FLOOR = 2 ×10^

(8)

PN(f_OUT, f_OFFSET) = Flicker_FOM + 20 × log(f_OUT) – 10 ×

log(f_OFFSET

)

(4)

where JITTER_DENSITY_FLOOR is the jitter density of floor at

f_OUT

.

where:

f

_OUTis the output frequency.

Calculate the rms additive jitter due to floor using the following

equation:

f_OFFSETis the offset of noise frequency from the output carrier

frequency.

JITTER_RMS_FLOOR = JITTER_DENSITY_FLOOR ×

√Observation Bandwidth

Flicker_FOM is the figure of merit at the flicker frequency.

(9)

Calculate the noise floor as follows:

where Observation Bandwidth is the desired integration

bandwidth of the noise with a lower and upper bound offset

from the output carrier frequency.













f_OUT

f_PD2

PN

(

f_OUT, f_PD2

)

= Floor_ FOM +20×log

−10×

log

(

f_PD2

)

(5)

Rev. B | Page 43 of 72

HMC7044

Data Sheet

CONTROL REGISTERS

CONTROL REGISTER MAP

Register addresses that are not listed in Table 25 are not used, and writing to those registers has no effect. Do not change the values of

registers that are marked as reserved. When writing to registers with bits that are marked reserved, take care to always write the default

value for the reserved bits, unless listed otherwise in the other controls subsection of Table 25.

Table 25. Control Register Map

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Global Control

0x0000

Global soft

reset control

Reserved

Soft reset

0x00

0x0001

Global

request and

mode control

Reseed

request

High

Force

holdover

Mute

output

drivers

Pulse

Restart

Sleep

mode

performance performance

distribution

generator dividers/

request

PLLs/VCO

FSMs

path

0x0002

0x0003

Reserved

PLL2

autotune

trigger

Slip

request

Reserved

0x00

0x37

Global

enable

control

Reserved

RF reseeder

enable

VCO Selection[1:0]

SYSREF

timer

enable

PLL2

enable

PLL1

enable

0x0004

0x0005

Reserved

SYNC Pin Mode

Selection[1:0]

Seven Pairs of 14-Channel Outputs Enable[6:0]

CLKIN0/

PLL1 Reference Path Enable[3:0]

CLKIN0

0x7F

0x4F

Global mode

and enable

control

CLKIN1/

CLKIN1

in

in RF

external VCO

input mode

SYNC input

mode

0x0006

Global clear

alarms

Reserved

Clear

alarms

0x00

0x0007

0x0008

0x0009

Global

miscellaneous

control

Reserved

0x00

0x01

Reserved (Scratchpad)

Reserved

Disable

SYNC at

lock

PLL1

0x000A CLKIN0/

CLKIN0

Reserved

Input Buffer Mode[3:0]

Buffer

enable

0x07

0xE4

input

buffer control

0x000B

CLKIN1/

Reserved

Input Buffer Mode[3:0]

Second Priority

Buffer

enable

CLKIN1

input

buffer control

0x000C CLKIN2/

CLKIN2

Buffer

enable

input

buffer control

0x000D CLKIN3/

CLKIN3

Buffer

enable

input

buffer control

OSCIN

input buffer

control

0x000E

0x0014

Buffer

enable

OSCIN/

PLL1

Fourth Priority

CLKINx

First Priority

CLKINx

Third Priority CLKINx/

reference

priority

control

CLKINx

CLKINx/

Input[1:0]

CLKINx/

Input[1:0]

CLKINx/

Input[1:0]

0x0015

0x0016

PLL1 loss of

signal (LOS)

control

Reserved

LOS Validation Timer[2:0]

0x03

0x0C

PLL1

holdover exit

Reserved

Holdover Exit

Action[1:0]

Holdover Exit

Criteria[1:0]

control

Rev. B | Page 44 of 72

Data Sheet

HMC7044

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x0017

0x0018

PLL1

Reserved

Holdover DAC Value[6:0]

0x00

0x04

holdover

DAC/ADC

control

Reserved

ADC

tracking

disable

Force

Holdover BW

Reduction[1:0]

DAC to

holdover

in quick

mode

0x0019

PLL1 LOS

Reserved

LOS

LOS uses

0x00

mode control

bypass

input

VCXO

prescaler

0x001A PLL1 charge

pump control

Reserved

PLL1 CP Current[3:0]

0x08

0x18

0x001B

PLL1 PFD

control

Reserved

PLL1 PFD up

enable

PLL1 PFD

down

PLL1 PFD

up force

PLL1 PFD

down

PLL1 PFD

polarity

enable

force

0x001C CLKIN0/

CLKIN0

CLKIN1

CLKIN2

CLKIN3

0x04

0x01

0x04

0x01

0x04

CLKIN0/

CLKIN1/

CLKIN2/

CLKIN3/

OSCIN/

Input Prescaler[7:0]

input

prescaler

control

0x001D

0x001E

0x001F

0x0020

CLKIN1/

CLKIN1

input

prescaler

control

CLKIN2/

CLKIN2

input

prescaler

control

CLKIN3/

CLKIN3

input

prescaler

control

OSCIN

OSCIN/

OSCIN

Input

prescaler

control

0x0021

0x0022

PLL1

reference

divider

16-Bit R1 Divider[7:0] (LSB)

16-Bit R1 Divider[15:8] (MSB)

0x04

0x00

control (R1)

0x0026

0x0027

PLL1

feedback

divider

16-Bit N1 Divider[7:0] (LSB)

16-Bit N1 Divider[15:8] (MSB)

0x10

0x00

control (N1)

0x0028

0x0029

PLL1 lock

detect

control

Reserved

PLL1 lock

detect uses

slip

PLL1 Lock Detect Timer[4:0]

0x0F

0x05

PLL1

Reserved

Bypass

debouncer

Manual Mode Reference

Holdover

uses DAC

Auto-

mode

reference

switching

reference

switching

control

Switching[1:0]

revertive

reference

switching

0x002A PLL1 holdoff

time control

Holdoff Timer[7:0]

0x00

PLL2

0x0031

PLL2

miscellaneou

s control

Reserved

0x01

0x0032

PLL2

Reserved

Bypass

frequency

doubler

control

frequency

doubler

0x0033

0x0034

PLL2

reference

divider

12-Bit R2 Divider[7:0] (LSB)

0x02

0x00

Reserved

12-Bit R2 Divider[11:8] (MSB)

control (R2)

Rev. B | Page 45 of 72

HMC7044

Data Sheet

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x0035

0x0036

PLL2

feedback

divider

16-Bit N2 Divider[7:0] (LSB)

16-Bit N2 Divider[15:8] (MSB)

0x20

0x00

control (N2)

0x0037

0x0038

PLL2 charge

pump control

Reserved

PLL2 CP Current[3:0]

0x0F

0x18

PLL2 PFD

control

Reserved

PLL2 PFD up

enable

PLL2 PFD

down

PLL2 PFD

up force

PLL2 PFD

down

PLL2 PFD

polarity

enable

force

0x0039

OSCOUTx/

OSCOUTx

path control

Reserved

OSCOUTx/

OSCOUTx

path

0x00

OSCOUTx

Divider[1:0]

enable

0x003A OSCOUTx/

OSCOUTx

Reserved

OSCOUT0

Mode[1:0]

Reserved

OSCOUT0

Driver Impedance[1:0]

OSCOUT0/ 0x00

OSCOUT0

driver

OSCOUT0/

Driver

OSCOUT0/

driver control

enable

0x003B

Reserved

OSCOUT1

Mode[1:0]

OSCOUT1

Driver Impedance[1:0]

OSCOUT1/ 0x00

OSCOUT1

driver

OSCOUT1/

enable

0x003C PLL2

miscellaneous

control

Reserved

0x00

GPIO/SDATA Control

0x0046

0x0047

0x0048

0x0049

0x0050

0x0051

0x0052

0x0053

0x0054

GPI1 control

GPI2 control

GPI3 control

GPI4 control

GPO1 control

GPO2 control

GPO3 control

GPO4 control

Reserved

GPI1 Selection[3:0]

GPI2 Selection[3:0]

GPI3 Selection[3:0]

GPI4 Selection[3:0]

GPI1

enable

0x00

0x09

0x11

0x37

0x33

0x00

0x03

Reserved

GPI2

enable

GPI3

enable

GPI4

enable

GPO1 Selection[5:0]

GPO2 Selection[5:0]

GPO3 Selection[5:0]

GPO4 Selection[5:0]

Reserved

GPO1

mode

GPO1

enable

GPO2

mode

GPO2

enable

GPO3

mode

GPO3

enable

GPO4

mode

GPO4

enable

SDATA

control

SDATA

mode

SDATA

enable

SYSREF/SYNC Control

0x005A Pulse

generator

Reserved

Pulse Generator Mode Selection[2:0] 0x00

control

0x005B

SYNC control

SYNC

0x06

retime

through

PLL2

polarity

0x005C SYSREF timer

SYSREF Timer[7:0] (LSB)

Reserved

0x00

0x01

0x00

control

0x005D

Reserved

SYSREF Timer[11:8] (MSB)

0x005E

SYSREF

miscellaneous

control

Rev. B | Page 46 of 72

Data Sheet

HMC7044

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Reserved

Bit 3

Bit 2

Bit 1

Clock Distribution Network

0x0064

External VCO

control

Divide by

2 on

external

VCO

enable

Low

0x00

frequency

external

VCO path

0x0065

Analog delay

common

control

Reserved

Analog

delay low

power

mode

Alarm Masks Registers

0x0070

PLL1 alarm

mask control

PLL1 near

lock mask

PLL1 lock

acquisition

mask

PLL1 lock

detect mask

PLL1 holdover

status mask

CLKINx

0x00

0x10

PLL1 CLKINx/

LOS Mask[3:0]

0x0071

Alarm mask

control

Reserved

Sync request

mask

PLL1 and

PLL2 lock

detect

Clock

SYSREF

sync

PLL2 lock

detect

mask

outputs

phase

status

mask

status

mask

Product ID Registers

0x0078

0x0079

0x007A

Product ID

Product ID Value[7:0] (LSB)

Product ID Value[15:8] (Mid)

Product ID Value[23:16] (MSB)

0x51

0x16

0x30

Alarm Readback Status Registers

0x007B

Readback

register

Reserved

Alarm

signal

0x007C PLL1 alarm

readback

PLL1 near

lock

PLL1 lock

acquisition

PLL1 lock

detect

PLL1 holdover

status

CLKINx

CLKINx/ LOS[3:0]

0x007D Alarm

readback

Reserved

Sync request

status

PLL1 and

PLL2 lock

detect

Clock

SYSREF

sync

status

PLL2 lock

detect

outputs

phases

status

0x007E

0x007F

Latched

alarm

readback

Reserved

PLL2 lock

acquisition

latched

PLL1 lock

acquisition

latched

PLL1 holdover

latched

CLKINx

CLKINx/

LOS Latched[3:0]

Alarm

Reserved

readback

miscellaneous

PLL1 Status Registers

0x0082

PLL1 status

registers

Reserved

PLL1 Best Clock[1:0]

PLL1 Active

CLKINx

CLKINx/ [1:0]

PLL1 FSM State[2:0]

0x0083

0x0084

PLL1 Holdover DAC Averaged Value[6:0]

PLL1 Holdover DAC Current Value[6:0]

Holdover

comparator

value

0x0085

Reserved

PLL1

active

CLKINx/

CLKINx

LOS

VCXO

status

holdover

ADC

status

holdover

ADC input

range

status

0x0086

0x0087

Reserved

PLL1 Holdover Exit

Phase[1:0]

Reserved

PLL2 Status Registers

0x008C PLL2 status

PLL2 autotune value

registers

0x008D

PLL2 Autotune Signed Error[7:0] (LSB)

0x008E

PLL2

PLL2 Autotune Signed Error[13:8] (MSB)

autotune

status

autotune

error sign

0x008F

0x0090

PLL2 Autotune FSM State[3:0]

PLL2 SYNC FSM State[3:0]

Reserved

Rev. B | Page 47 of 72

HMC7044

Data Sheet

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Reserved

Bit 5

Bit 4

Channel

outputs FSM

busy

Bit 3

Bit 2

Bit 1

SYSREF Status Register

0x0091

SYSREF status

register

SYSREF FSM State[3:0]

Other Controls

0x0096

0x0097

0x0098

0x0099

Reserved

0x00

0xAA

0x55

0x56

0x97

0x03

0x00

0x1C

0x00

0x22

0x00

0x20

0x00

0x08

0x50

0x09

0x0D

0x00

Reserved

0x009A Reserved

0x009B Reserved

0x009C Reserved

0x009D

0x009E

0x009F

Reserved

Clock output driver low power setting (for optimum performance, set to 0x4D instead of default value)

0x00A0 Reserved

0x00A1 Reserved

0x00A2 Reserved

0x00A3 Reserved

0x00A4 Reserved

0x00A5 Reserved

0x00A6 Reserved

0x00A7 Reserved

0x00A8 Reserved

0x00A9 Reserved

0x00AB Reserved

0x00AC Reserved

0x00AD Reserved

0x00AE Reserved

0x00AF Reserved

Clock output driver high power setting (for optimum performance, set to 0xDF instead of default value)

Reserved

PLL1 more delay (PFD1, lock detect) (for optimum performance, set to 0x06 instead of default value)

Reserved

PLL1 holdover DAC g_msetting (for optimum performance, set to 0x06 instead of default value)

Reserved

0x00B0

0x00B1

0x00B2

0x00B3

0x00B5

0x00B6

0x00B7

0x00B8

Reserved

VTUNE preset setting (for optimum performance, set to 0x04 instead of default value)

Reserved

Clock Distribution

0x00C8 Channel

Output 0

High

performance

mode

SYNC

enable

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

0xF3

control

0x00C9

0x00CA

0x00CB

0x00CC

0x00CD

0x00CE

0x00CF

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x04

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x00D0

0x00D1

Force Mute[1:0]

Reserved

Dynamic

driver enable

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

0x00

Rev. B | Page 48 of 72

Data Sheet

HMC7044

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x00D2

Channel

Output 1

control

High

performance

mode

SYNC

enable

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

0xFD

0x00D3

0x00D4

0x00D5

0x00D6

0x00D7

0x00D8

0x00D9

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x00DA

Force Mute[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver enable

Slip enable

0x00DB

0x00

0xF3

0x00DC Channel

Output 2

High

SYNC

enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

control

mode

0x00DD

0x00DE

0x00DF

0x00E0

0x00E1

0x00E2

0x00E3

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x08

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Dynamic

Output Mux

Selection[1:0]

0x00E4

Force Mute[1:0]

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver enable

0x00E5

0x00

0xFD

0x00E6

Channel

Output 3

control

High

SYNC

enable

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

mode

0x00E7

0x00E8

0x00E9

0x00EA

0x00EB

0x00EC

0x00ED

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x00EE

Force Mute[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver enable

Slip enable

0x00EF

0x00F0

0x00

0xF3

Channel

Output 4

control

High

SYNC

enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

mode

0x00F1

0x00F2

0x00F3

0x00F4

0x00F5

0x00F6

0x00F7

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x02

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

Reserved

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x00F8

0x00F9

Force Mute[1:0]

Dynamic

driver enable

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

0x00

Rev. B | Page 49 of 72

HMC7044

Data Sheet

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x00FA Channel

Output 5

High

performance

SYNC

enable

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

0xFD

control

mode

0x00FB

0x00FC

0x00FD

0x00FE

0x00FF

0x0100

0x0101

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x0102

Force Mute[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver enable

Slip enable

0x0103

0x00

0xF3

0x0104

Channel

Output 6

control

High

SYNC

enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

mode

0x0105

0x0106

0x0107

0x0108

0x0109

0x010A

0x010B

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x02

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-bit Multislip Digital Delay[11:8] (MSB)

Reserved

Dynamic

Output Mux

Selection[1:0]

0x010C

Force Mute[1:0]

SYNC

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver enable

0x010D

0x010E

0x00

0xFD

Channel

Output 7

control

High

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

enable

mode

0x010F

0x0110

0x0111

0x0112

0x0113

0x0114

0x0115

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x0116

Force Mute[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver enable

Slip enable

0x0117

0x0118

0x00

0xF3

Channel

Output 8

control

High

SYNC

enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

mode

0x0119

0x011A

0x011B

0x011C

0x011D

0x011E

0x011F

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x02

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x0120

0x0121

Force Mute[1:0]

Dynamic

driver enable

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

0x00

Rev. B | Page 50 of 72

Data Sheet

HMC7044

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x0122

Channel

Output 9

control

High

performance

mode

SYNC

enable

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

0xFD

0x0123

0x0124

0x0125

0x0126

0x0127

0x0128

0x0129

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x012A

Force Mute[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver enable

Slip enable

0x012B

0x00

0xF3

0x012C Channel

Output 10

High

SYNC

enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

control

mode

0x012D

0x012E

0x012F

0x0130

0x0131

0x0132

0x0133

12-Bit Channel Divider[7:0] (LSB)

0x02

0x00

Reserved

12-bit channel divider[11:8] (MSB)

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Dynamic

Output mux

selection[1:0]

0x0134

Force Mute[1:0]

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver enable

0x0135

0x00

0xFD

0x0136

Channel

Output 11

control

High

SYNC

enable

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

mode

0x0137

0x0138

0x0139

0x013A

0x013B

0x013C

0x013D

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x013E

Force Mute[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver enable

Slip enable

0x013F

0x0140

0x00

0xF3

Channel

Output 12

control

High

SYNC

enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

performance

mode

0x0141

0x0142

0x0143

0x0144

0x0145

0x0146

0x0147

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x10

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x0148

0x0149

Force Mute[1:0]

Dynamic

driver enable

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

0x00

Rev. B | Page 51 of 72

HMC7044

Data Sheet

Default

Addr.

(Hex)

Register

Name

Bit 0

(LSB)

Value

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x014A Channel

Output 13

High

performance

SYNC

enable

Slip enable

Reserved

Start-Up Mode[1:0]

Multislip

enable

Channel

enable

0xFD

control

mode

0x014B

0x014C

0x014D

0x014E

0x014F

0x0150

0x0151

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux

Selection[1:0]

0x0152

0x0153

Force Mute[1:0]

Dynamic

driver enable

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

0x00

CONTROL REGISTER MAP BIT DESCRIPTIONS

Global Control (Register 0x0000 to Register 0x0009)

Table 26. Global Soft Reset Control

Address Bits Bit Name

0x0000 [7:1] Reserved

Soft reset

Settings

Description

Access

Reserved.

RW

0

Resets all registers, dividers, and FSMs to default values.

Table 27. Global Request and Mode Control

Address Bits Bit Name

Settings Description

Access

0x0001

7

Reseed request

Requests the centralized resync timer and FSM to reseed any of the

output dividers that are programmed to pay attention to sync events.

This signal is rising edge sensitive, and is only acknowledged if the

resync FSM has completed all events (has finished any previous pulse

generator and/or sync events, and is in the done state; SYSREF FSM

State[3:0] = 0010).

RW

6

High performance

distribution path

High performance distribution path select. The VCO clock distribution

path has two modes.

0

1

Power priority.

Noise priority. Provides the option for better noise floors on the

divided output signals.

5

4

High performance

PLLs/VCO

High performance PLL/VCO select. The VCO has two modes of

operation.

0

1

Power priority.

Noise priority. Reduces the phase noise around the carrier.

Force holdover

Force PLL1 into holdover mode. A holdover request from the GPI or SPI

is debounced inside the device when transferred to the PLL1 FSM

clock domain (which is nominally at the VCXO or LCM rate). With the

debouncer enabled, the delay from force holdover assertion to the

HOLDOVER state is six clock cycles. If the debouncer is bypassed, the

delay is two clock cycles. To asynchronously tristate the charge pump,

the user can disable the up and down signals from the PFD via Bits[4:3]

(PLL1 PFD up enable, PLL1 PFD down enable) in the PLL1 PFD control

register (Register 0x001B).

3

2

Mute output drivers

Mutes the output drivers (dividers still run in the background).

Pulse generator request

Asks for a pulse stream (see the Typical Programming Sequence

section).

1

0

Restart dividers/FSMs

Sleep mode

Resets all dividers and FSMs. Does not affect configuration registers.

Forces shutdown. PLL1 and PLL2, output network, and I/O buffers are

disabled.

Rev. B | Page 52 of 72

Data Sheet

HMC7044

Address Bits Bit Name

Settings Description

Access

0x0002

[7:3] Reserved

Reserved.

RW

2

PLL2 autotune trigger

Triggers an autotune if there is an error/issue when the device comes

out of reset.

1

Slip request

Reserved

Requests a slip or multislip event from all divider channels that are

sensitive to slip or multislip commands. The dividers are rising edge

sensitive and take some time to process the request, after which the

phase synchronization alarm is asserted.

0

Reserved.

Table 28. Global Enable Control

Address Bits Bit Name

Settings Description

Access

0x0003

[7:6] Reserved

Reserved

RW

5

RF reseeder enable

Enable RF reseed for SYSREF

Internal disabled/external

High

[4:3] VCO Selection[1:0]

00

01

10

Low

2

1

0

7

SYSREF timer enable

PLL2 enable

Enable internal SYSREF time reference

Master analog enable to PLL2

Master analog enable to PLL1

Reserved

PLL1 enable

0x0004

Reserved

RW

[6:0] Seven Pairs of 14

Channel Outputs

Enable[6:0]

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Enable Channel 0 and Channel 1

Enable Channel 2 and Channel 3

Enable Channel 4 and Channel 5

Enable Channel 6 and Channel 7

Enable Channel 8 and Channel 9

Enable Channel 10 and Channel 11

Enable Channel 12 and Channel 13

Table 29. Global Mode and Enable Control

Address Bits Bit Name

Settings Description

SYNC pin configuration with respect to PLL2.

Disabled.

Access

0x0005

[7:6] SYNC Pin Mode

Selection[1:0]

RW

00

01

SYNC. A rising edge is carried through PLL2. Useful for multichip

synchronization.

10

11

Pulse generator. Request a pulse generator stream from any channels

configured for dynamic startup. This behaves in the same way as a GPI

requested pulse generator.

Causes SYNC if alarm exists, otherwise causes pulse generator.

CLKIN1/CLKIN1 input is used for external VCO.

5

4

CLKIN1/CLKIN1 in

external VCO input

mode

CLKIN0/CLKIN0 in RF

SYNC input mode

CLKIN0/CLKIN0 input is used for external RF sync.

[3:0] PLL1 Reference Path

Enable[3:0]

Selects and enables the reference path for PLL1.

Enable CLKIN0/CLKIN0 input path.

Enable CLKIN1/CLKIN1 input path.

Enable CLKIN2/CLKIN2 input path.

Enable CLKIN3/CLKIN3 input path.

Bit 0

Bit 1

Bit 2

Bit 3

Rev. B | Page 53 of 72

HMC7044

Data Sheet

Table 30. Global Clear Alarms

Address Bits Bit Name

Settings Description

Access

0x0006

[7:1] Reserved

Clear alarms

Reserved

RW

0

Clear latched alarms

Table 31. Global Miscellaneous Control

Address Bits Bit Name

Settings Description

Access

0x0007

0x0008

[7:0] Reserved

Reserved.

RW

[7:0] Reserved (Scratchpad)

Reserved. The user can write/read to this register to confirm I/Os to the RW

HMC7044. This register does not affect device operation.

0x0009

[7:1] Reserved

Reserved.

RW

0

Disable SYNC at lock

0

1

PLL2 sends a sync event up N2 when lock is achieved.

This feature is disabled and SYNC is not internally generated on PLL2

lock.

PLL1 (Register 0x000A to Register 0x002A)

CLKINx

OSCIN

Table 32. CLKINx/

and OSCIN/

Input Buffer Control

Address

Bits Bit Name

Settings Description

Access

0x000A, 0x000B, 0x000C, 0x000D, 0x000E

[7:5] Reserved

Reserved

RW

[4:1] Input Buffer Mode[3:0]

Input buffer control

Bit 0

Bit 1

Bit 2

Bit 3

Enable internal 100 Ω termination

Enable ac coupling input mode

Enable LVPECL input mode

Enable high-Z input mode

Enable input buffer

0

Buffer enable

Table 33. PLL1 Reference Priority Control

Address Bits Bit Name

Settings

Description

Access

0x0014

[7:6] Fourth Priority CLKINx/CLKINx Input[1:0]

[5:4] Third Priority CLKINx/CLKINx Input[1:0]

[3:2] Second Priority CLKINx/CLKINx Input[1:0]

[1:0] First Priority CLKINx/CLKINx Input[1:0]

If third choice clock is not available, use the fourth

choice clock

RW

If second choice clock is not available, use the third

choice clock

If the first choice clock is not available, use the

second choice clock

This is the first choice clock

Table 34. PLL1 Loss of Signal (LOS) Control

Address Bits Bit Name Settings Description

Reserved.

Access

0x0015

[7:3] Reserved

RW

[2:0] LOS Validation

Timer[2:0]

LCM cycles of LOS hysteresis. This is the number of LCM cycles to wait before

exiting LOS state when the reference input becomes valid again.¹

000

001

010

011

100

101

110

111

None.

2 cycles.

4 cycles.

8 cycles.

16 cycles.

32 cycles.

64 cycles.

128 cycles.

¹The LOS revalidation takes between two and three times this number of cycles. The LOS revalidation ambiguity is dependent on whether another channel is in LOS.

Rev. B | Page 54 of 72

Data Sheet

HMC7044

Table 35. PLL1 Holdover Exit Control

Address

Bits

[7:4]

[3:2]

Bit Name

Settings

Description

Access

0x0016

Reserved

RW

Holdover Exit Action[1:0]

Action the PLL1 FSM takes as it exits holdover mode.

Reset dividers.

Do nothing.

00

01

10

11

Do nothing.

DAC assist.

[1:0]

Holdover Exit Criteria[1:0]

Criteria the PLL1 FSM uses to exit holdover mode.

Exit holdover when LOS is gone.

Exit holdover when phase error = 0.

Exit holder immediately.

X0¹

01

11

¹X means don’t care.

Table 36. PLL1 Holdover DAC/ADC Control

Address Bits Bit Name

Settings Description

Access

0x0017

7

Reserved

RW

[6:0] Holdover DAC

Value[6:0]

In holdover mode, if ADC tracking disable is set 1, the holdover DAC control

value is set to this value (regarded as an unsigned integer value); otherwise,

the holdover average DAC value is summed by this value (regarded as twos

complement coded signed integer value)

0x0018

[7:4] Reserved

Reserved

RW

3

ADC tracking

disable

Disable ADC tracking; use DAC hold word

2

Force DAC to

holdover in quick

mode

Force DAC control value from DAC current value to computed DAC holdover

value immediately, not gradually

[1:0] Holdover BW

Reduction[1:0]

Reduce tracking BW

Table 37. PLL1 LOS Mode Control

Address Bits Bit Name

Settings Description

Access

0x0019

[7:2] Reserved

Reserved

RW

1

LOS bypass input

prescaler

Bypass LCM R divider cascade; the R1 input is the selected

CLKINx/CLKINx input

0

LOS uses VCXO prescaler

For very low PFD rates; cascades VCXO LCM divider after N1

Table 38. PLL1 Charge Pump Control

Address

Bits

[7:4]

[3:0]

Bit Name

Settings

Description

Access

RW

0x001A

Reserved

PLL1 CP Current[3:0]

PLL1 charge pump current

Rev. B | Page 55 of 72

HMC7044

Data Sheet

Table 39. PLL1 PFD Control

Address Bits Bit Name

Settings Description

Access

0x001B

[7:5] Reserved

Reserved

RW

4

3

2

PLL1 PFD up enable

Enable PLL1 PFD up

Enable PLL1 PFD down

PLL1 PFD down enable

PLL1 PFD up force

Force PLL1 charge pump up; do not assert simultaneously with PLL1

PFD down force

1

0

PLL1 PFD down force

PLL1 PFD polarity

Force PLL1 charge pump down; do not assert simultaneously with PLL1

PFD up force

Select PFD polarity

Positive

Negative

0

1

CLKINx

OSCIN

Table 40. CLKINx/

and OSCIN/

Input Prescaler Control

Settings

Address

0x001C

0x001D

0x001E

0x001F

0x0020

Bits

[7:0]

Bit Name

Description

Access

RW

CLKIN0/CLKIN0 Input Prescaler[7:0]

CLKIN1/CLKIN1 Input Prescaler[7:0]

CLKIN2/CLKIN2 Input Prescaler[7:0]

CLKIN3/CLKIN3 Input Prescaler[7:0]

OSCIN/OSCIN Input Prescaler[7:0]

CLKIN0/CLKIN0 Prescaler divider setpoint

CLKIN1/CLKIN1 Prescaler divider setpoint

CLKIN2/CLKIN2 Prescaler divider setpoint

CLKIN3/CLKIN3 Prescaler divider setpoint

OSCIN/OSCIN Prescaler divider setpoint

RW

Table 41. PLL1 Reference Divider Control (R1)

Address

0x0021

0x0022

Bits

[7:0]

Bit Name

Settings

Description

Access

RW

16-Bit R1 Divider[7:0] (LSB)

16-Bit R1 Divider[15:8] (MSB)

16-bit R1 divider setpoint LSB

16-bit R1 divider setpoint MSB

Table 42. PLL1 Feedback Divider Control (N1)

Address

0x0026

0x0027

Bits

[7:0]

Bit Name

Settings

Description

Access

RW

16-Bit N1 Divider[7:0] (LSB)

16-Bit N1 Divider[15:8] (MSB)

16-bit N1 divider setpoint LSB

16-bit N1 divider setpoint MSB

Table 43. PLL1 Lock Detect Control

Address

Bits

Bit Name

Settings

Description

Access

RW

0x0028

[7:6] Reserved

Reserved

5

PLL1 lock detect uses slip

Use the slip indicator instead of ~2 ns timer for lock detect

[4:0] PLL1 Lock Detect Timer[4:0]

PLL1 lock detect center depth (LCMs); increments of

2^{PLL1 Lock Detect Timer[4:0]}cycles

00000

00001

00010

…

1 cycle

2 cycles

4 cycles

…

11110

11111

1,073,741,824 cycles

2,147,483,648 cycles

Rev. B | Page 56 of 72

Data Sheet

HMC7044

Table 44. PLL1 Reference Switching Control

Address Bits Bit Name

Settings Description

Access

0x0029

[7:6] Reserved

Reserved

RW

5

Bypass debouncer

Bypass the debouncer in manual mode and GPI clock/holdover

selection

[4:3] Manual Mode Reference

Switching[1:0]

If automode REF switching = 0, manual selection of

CLKINx/CLKINx input

2

Holdover uses DAC

In holdover, selects whether PLL1 uses the DAC or tristates the

charge pump

0

1

Tristate the charge pump

Use holdover DAC

1

0

Autorevertive reference

switching

Revert to PLL1 best clock option if it becomes available again

Automode reference switching

Clock switching is automatic based on LOS/PLL1 reference

priority control register (Register 0x0014)

Table 45. PLL1 Holdoff Time Control

Address Bits Bit Name

Settings Description

Access

0x002A

[7:0] Holdoff Timer[7:0]

PLL1 waits in holdover for 2^{Holdoff Timer[7:0]}LCM cycles to give the abandoned

reference a chance to recover before switching to the next priority clock. If

Holdoff Timer[7:0] equals to 0, holdoff functionality is disabled and switches

directly to the next priority clock.

RW

PLL2 (Register 0x0031 to Register 0x003C)

Table 46. PLL2 Miscellaneous Control

Address

0x0031

0x003C

Bits

[7:0]

Bit Name

Reserved

Settings

Description

Reserved

Access

RW

Reserved

RW

Table 47. PLL2 Frequency Doubler Control

Address

Bits

[7:1]

0

Bit Name

Settings

Description

Reserved

Access

RW

0x0032

Reserved

Bypass frequency doubler

Bypass PLL2 frequency doubler

Enable frequency doubler before R2 divider

Bypass frequency doubler

0

1

Table 48. PLL2 Reference Divider Control (R2)

Address Bits Bit Name Settings Description

Access

0x0033

[7:0] 12-Bit R2 Divider[7:0]

12-bit R2 divider setpoint LSB. Divide by 1 to divide by 4095. 00000000,

00000001 = divide by 1.

RW

(LSB)

0x0034

[7:4] Reserved

Reserved.

RW

[3:0] 12-Bit R2 Divider[11:8]

(MSB)

12-Bits R2 divider setpoint MSB.

Table 49. PLL2 Feedback Divider Control (N2)

Address Bits Bit Name

Settings Description

Access

RW

0x0035

0x0036

[7:0] 16-Bit N2 Divider[7:0] (LSB)

[7:0] 16-Bit N2 Divider[15:8] (MSB)

16-bit N2 divider setpoint LSB.

16-bit N2 divider setpoint MSB.

RW

Rev. B | Page 57 of 72

HMC7044

Data Sheet

Table 50. PLL2 Charge Pump Control

Address Bits Bit Name

Settings Description

Access

0x0037

[7:4] Reserved

Reserved.

RW

[3:0] PLL2 CP

Current[3:0]

These 4 bits set the magnitude of PLL2 charge pump current. Granularity is

~160 µA with full magnitude of ~2560 µA.

Table 51. PLL2 PFD Control

Address Bits Bit Name

Settings Description

Access

0x0038

[7:5] Reserved

Reserved

RW

4

3

PLL2 PFD up enable

Enable PLL2 PFD up

Enable PLL2 PFD down

PLL2 PFD down

enable

2

1

0

PLL2 PFD up force

Force PLL2 charge pump up; do not assert simultaneously with PLL2 PFD

down force

PLL2 PFD down

force

Force PLL2 charge pump down; do not assert simultaneously with PLL2

PFD up force

PLL2 PFD polarity

Select PFD polarity

Positive

0

1

Negative

Table 52. OSCOUTx/

Path Control

OSCOUTx

Address Bits Bit Name

0x0039 [7:3] Reserved

Settings Description

Access

Reserved

RW

[2:1] OSCOUTx/OSCOUTx

Divider[1:0]

Oscillator output divider ratio

Divided by 1

Divided by 2

Divided by 4

Divided by 8

00

01

10

11

0

OSCOUTx/OSCOUTx

path enable

Enable the oscillator output path (divider and the internal path except

driver)

Table 53. OSCOUTx/

Driver Control

OSCOUTx

Address

Bits Bit Name

Settings¹Description

Access

0x003A,

0x003B

[7:6] Reserved

Reserved

RW

[5:4] OSCOUTx/OSCOUTx Driver Mode[1:0]

Oscillator output driver mode selection

CML mode

00

01

10

11

LVPECL mode

LVDS mode

CMOS mode

[3]

Reserved

[2:1] OSCOUTx/OSCOUTx Driver

Impedance[1:0]

Oscillator output driver impedance selection for

CML mode

00

01

10

11

Internal resistor disable

Internal 100 Ω resistor enable per output pin

Reserved

Internal 50 Ω resistor enable per output pin

Enable oscillator driver

0

OSCOUTx/OSCOUTx driver enable

¹X means don’t care.

Rev. B | Page 58 of 72

Data Sheet

HMC7044

GPIO/SDATA Control (Register 0x0046 to Register 0x0054)

Table 54. GPIx Control

Address

Bits Bit Name

Settings Description

Access

0x0046, 0x0047,

0x0048, 0x0049

[7:5] Reserved

Reserved.

RW

[4:1] GPIx Selection[3:0]

Select the GPIx functionality.

Reserved.

Force PLL1 to holdover.

Select PLL1 reference manually, Bit 1.

Select PLL1 reference manually, Bit 0.

Put the chip into sleep mode.

Issue a mute.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Select the internal VCO type manually.

Select high performance mode for PLL2 and the internal VCO.

Issue a pulse generator request.

Issue a reseed request.

Issue a restart request.

Force the chip into fanout mode.

Reserved.

Issue a slip request

Reserved.

0

GPIx enable

GPIx function enable. Before changing the function of the pin,

disable it first, and then reenable it after the function change.¹

¹Note that it is possible to have a GPIOx pin configured as both an output and an input.

Table 55. GPOx Control

Address

Bits Bit Name

Settings Description

Select the GPOx functionality

Alarm signal

Access

0x0050, 0x0051, 0x0052, 0x0053 [7:2] GPOx Selection[5:0]

RW

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

SDATA from SPI communication

CLKIN3/CLKIN3 LOS for CLKIN3/CLKIN3 input

CLKIN2/CLKIN2 LOS for CLKIN2/CLKIN2input

CLKIN1/CLKIN1 LOS for CLKIN1/CLKIN1 input

CLKIN0/CLKIN0 LOS for CLKIN0/CLKIN0 input

PLL1 holdover enabled signal from PLL1

Lock detect signal from PLL1

Acquiring lock signal from PLL1

PLL1 near lock acquisition status signal from PLL1

PLL2 lock detect signal from PLL2

SYSREF sync status has not synchronized since reset

Clock outputs phase status

PLL1 and PLL2 lock detect is locked

Sync request status signal

PLL1 active CLKIN0/CLKIN0

PLL1 active CLKIN1/CLKIN1

PLL1 holdover ADC input range status

PLL1 holdover ADC input status

PLL1 VCXO status

PLL1 active CLKINx/CLKINx status

PLL1 FSM state, Bit 0

PLL1 FSM state, Bit 1

PLL1 FSM state, Bit 2

Rev. B | Page 59 of 72

HMC7044

Data Sheet

Address

Bits Bit Name

Settings Description

PLL1 holdover exit phase, Bit 0

Access

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

PLL1 holdover exit phase, Bit 1

Channel outputs FSM busy

SYSREF FSM state, Bit 0

SYSREF FSM state, Bit 1

SYSREF FSM state, Bit 2

SYSREF FSM state, Bit 3

Force Logic 1 to GPO

Force Logic 0 to GPO

Reserved

PLL1 holdover DAC averaged value, Bit 0

PLL1 holdover DAC averaged value, Bit 1

PLL1 holdover DAC averaged value, Bit 2

PLL1 holdover DAC averaged value, Bit 3

PLL1 holdover DAC current value, Bit 0

PLL1 holdover DAC current value, Bit 1

PLL1 holdover DAC current value, Bit 2

PLL1 holdover DAC current value, Bit 3

Reserved

Holdover comparator status

Pulse generator request status signal

Reserved

1

0

GPOx mode

GPOx enable

Selects the mode of GPOx driver

Open-drain mode

CMOS mode

0

1

GPOx driver enable

Table 56. SDATA Control

Address

Bits

[7:2]

1

Bit Name

Reserved

Settings

Description

Access

0x0054

Reserved

RW

SDATA mode

Selects the mode of SDATA driver

Open-drain mode

CMOS mode

0

1

0

SDATA enable

SDATA driver enable

Rev. B | Page 60 of 72

Data Sheet

HMC7044

SYSREF/SYNC Control (Register 0x005A to Register 0x005E)

Table 57. Pulse Generator Control

Address Bits Bit Name

Settings Description

Access

0x005A

[7:3] Reserved

Reserved.

RW

[2:0] Pulse Generator

Mode

SYSREF output enable with pulse generator.

000

Level sensitive. When the GPIx is configured to issue a pulse generator

Selection[2:0]

request (GPIx Selection[3:0] = 1000), or a pulse generator request is issued

through the SPI or as a SYNC pin-based pulse generator, run the pulse

generator. Otherwise, stop the pulse generator.

001

010

011

100

101

110

111

1 pulse.

2 pulses.

4 pulses.

8 pulses.

16 pulses.

Continuous mode (50% duty cycle).

Table 58. SYNC Control

Address Bits Bit Name

Settings Description

Access

0x005B

[7:3] Reserved

Reserved

RW

2

SYNC retime

0

1

Bypass the retime (if using SYNC path with on-chip VCO)

Retime the external SYNC from Reference 0

1

0

SYNC through PLL2

SYNC polarity

Allow a reseed event to be through PLL2

SYNC polarity (must be 0 if not using CLKIN0/CLKIN0 as the input)

0

1

Positive

Negative

Table 59. SYSREF Timer Control

Address Bits Bit Name

Settings Description

12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of the

Access

0x005C

[7:0] SYSREF

Timer[7:0]

RW

master timer, which controls synchronization and pulse generator events. Set the

12-bit timer to a submultiple of the lowest output SYSREF frequency, and

program it to be no faster than 4 MHz.

(LSB)

0x005D

[7:4] Reserved

Reserved.

RW

[3:0] SYSREF

Timer[11:8]

(MSB)

12-bit SYSREF timer setpoint MSB.

Table 60. SYSREF Miscellaneous Control

Address

Bits

Bit Name

Settings

Description

Access

0x005E

[7:0]

Reserved

RW

Clock Distribution Network (Register 0x0064 to Register 0x0065)

Table 61. External VCO Control

Address

Bits

[7:2]

1

Bit Name

Settings

Description

Access

0x0064

Reserved

RW

Divide by 2 on external VCO enable

Low frequency external VCO path

Use divide by 2 on external VCO path

Changes bias to Class A for low frequency VCO

0

Rev. B | Page 61 of 72

HMC7044

Data Sheet

Table 62. Analog Delay Common Control

Address Bits Bit Name

Settings Description

Access

0x0065

[7:1] Reserved

Analog delay low

power mode

Reserved.

RW

0

Analog delay is in low power mode, which can save power for low settings of

analog delay, but is not glitchless between setpoints.

Alarm Masks Registers (Register 0x0070 to Register 0x0071)

Table 63. PLL1 Alarm Mask Control

Address Bits Bit Name

Settings Description

Access

0x0070

7

6

PLL1 near lock mask

If set, allow the PLL1 near lock signal to generate alarm signal

RW

PLL1 lock acquisition mask

If set, allow the PLL1 lock acquisition signal to generate alarm

signal

5

4

PLL1 lock detect mask

If set, allow the PLL1 lock detect signal to generate alarm

signal

PLL1 holdover status mask

If set, allow the PLL1 holdover status signal to generate alarm

signal

[3:0] PLL1 CLKINx/CLKINx Status

Mask[3:0]

Bit 0

Bit 1

Bit 2

Bit 3

If set, allow CLKIN0/CLKIN0 LOS to generate alarm signal

If set, allow CLKIN1/CLKIN1 LOS to generate alarm signal

If set, allow CLKIN2/CLKIN2 LOS to generate alarm signal

If set, allow CLKIN3/CLKIN3 LOS to generate alarm signal

Table 64. Alarm Mask Control

Address Bits Bit Name

Settings Description

Access

0x0071

[7:5] Reserved

Reserved

RW

4

3

Sync request mask

If set, allow the sync request signals to generate alarm signal

PLL1 and PLL2 lock detect mask

If set, allow the PLL1 and PLL2 lock detect signals to generate

alarm signal

2

1

0

Clock outputs phases status

mask

If set, allow the clock outputs phases status signal to generate

alarm signal

SYSREF sync status mask

If set, allow the SYSREF sync status signal to generate alarm

signal

PLL2 lock detect mask

If set, allow the PLL2 lock detect signal to generate alarm

signal

Product ID Registers (Register 0x0078 to Register 0x007A)

Table 65. Product ID

Address

0x0078

0x0079

0x007A

Bits

[7:0]

Bit Name

Settings Description

24-bit product ID value low

Access

Product ID Value[7:0] (LSB)

Product ID Value[15:8] (Mid)

Product ID Value[23:16] (MSB)

R

24-bit product ID value high

24-bit product ID value very high

Alarm Readback Status Registers (Register 0x007B to Register 0x007F)

Table 66. Readback Register

Address

Bits

[7:1]

0

Bit Name

Reserved

Settings

Description

Access

0x007B

Reserved.

R

Alarm signal

Readback alarm status from SPI.

Rev. B | Page 62 of 72

Data Sheet

HMC7044

Table 67. PLL1 Alarm Readback

Address Bits Bit Name

Settings Description

PLL1 near locked. Declare near locked when the counter reaches 1/16 of

the programmable limit.

Access

0x007C

7

PLL1 near lock

R

6

5

4

PLL1 lock acquisition

PLL1 lock detect

PLL1 acquiring lock.

PLL1 locked.

PLL1 holdover status

PLL1 in holdover.

CLKIN0/CLKIN0 LOS.

CLKIN1/CLKIN1 LOS.

CLKIN2/CLKIN2 LOS.

CLKIN3/CLKIN3 LOS.

[3:0] CLKINx/CLKINx

LOS[3:0]

Bit 0

Bit 1

Bit 2

Bit 3

Table 68. Alarm Readback

Address Bits Bit Name

Settings Description

Access

0x007D

[7:5] Reserved

Reserved.

R

4

3

Sync request status

PLL2 locked (or disabled), but unsynchronized.

PLL1 and PLL2 lock detect status.

PLL1 and PLL2 lock

detect

0

1

Either PLL1 or PLL2 is not locked or both PLL1 and PLL2 are not locked.

PLL1 and PLL2 are locked.

2

1

Clock outputs phases

status

SYSREF alarm.

0

1

SYSREF of the HMC7044 is not valid; that is, its phase output is not stable.

SYSREF of the HMC7044 is valid and locked; that is, its phase output is

stable.

SYSREF sync status

PLL2 lock detect

SYSREF SYNC status alarm.

0

1

The HMC7044 has been synchronized with an external sync pulse or a

sync request from the SPI.

The HMC7044 never synchronized with an external sync pulse or a sync

request from the SPI.

0

PLL2 near locked. Declare near locked when counter reaches 1/16 of the

programmable limit.

Table 69. Latched Alarm Readback

Address Bits Bit Name

Settings Description

Access

0x007E

7

6

5

4

Reserved

Reserved.

R

PLL2 lock acquisition latched

PLL1 lock acquisition latched

PLL1 holdover latched

Readback record of PLL2 lock acquisition since the last clear event.

Readback record of PLL1 lock acquisition since the last clear event.

Readback record of PLL1 holdover since the last clear event.

[3:0] CLKINx/CLKINx LOS

Latched[3:0]

Bit 0

Bit 1

Bit 2

Bit 3

Readback record of CLKIN0/CLKIN0 LOS since the last clear event.

Readback record of CLKIN1/CLKIN1 LOS since the last clear event.

Readback record of CLKIN2/CLKIN2 LOS since the last clear event.

Readback record of CLKIN3/CLKIN3 LOS since the last clear event.

Table 70. Alarm Readback Miscellaneous

Address Bits Bit Name

Settings Description

Access

0x007F

[7:0] Reserved

Reserved.

R

Rev. B | Page 63 of 72

HMC7044

Data Sheet

PLL1 Status Registers (Register 0x0082 to Register 0x0087)

Table 71. PLL1 Status Registers

Address Bits Bit Name

Settings Description

Reserved

Access

0x0082

7

Reserved

R

[6:5] PLL1 Best Clock[1:0]

Indicates which clock the LOS/priority encoder prefers if automode

reference switching is used

[4:3] PLL1 Active CLKINx/

CLKINx[1:0]

Indicates which CLKINx/CLKINx input is currently in use

[2:0] PLL1 FSM State[2:0]

Sets the state PLL1 is in

Reset

000

001

010

011

100

101

Acquisition

Locked

Invalid

Holdover

DAC assisted holdover exit

Reserved

0x0083

0x0084

0x0085

7

Reserved

R

[6:0] Holdover DAC Averaged

Value[6:0]

Average DAC code

7

Holdover comparator value

Holdover comparator output value (DAC output vs. PLL1 V_TUNE

Current DAC code

)

[6:0] Holdover DAC Current

Value[6:0]

[7:4] Reserved

Reserved

3

2

1

PLL1 active CLKINx/CLKINx

LOS

LOS of the currently active reference

PLL1 VCXO status

Indicates whether any of the enabled references appears to run

faster than the VCXO

PLL1 holdover ADC status

0

1

0

1

ADC is acquiring

PLL1 V_TUNEis moving quickly

PLL1 V_TUNEis in range

PLL1 V_TUNEis out of range

Reserved

0

PLL1 holdover ADC input

range status

0x0086

0x0087

[7:5] Reserved

R

[4:3] PLL1 Holdover Exit

Phase[1:0]

The phase of the PLL1 holdover exit

[2:0] Reserved

[7:0] Reserved

Reserved

PLL2 Status Registers (Register 0x008C to Register 0x0090)

Table 72. PLL2 Status Registers

Address Bits Bit Name

Settings Description

Access

0x008C

0x008D

0x008E

[7:0] PLL2 autotune value

After autotune, this word is populated with the selected capacitor

bank of the VCO

R

[7:0] PLL2 Autotune Signed

Error[7:0] (LSB)

14-bit PLL2 V_TUNEerror count, LSB

R

7

PLL2 autotune status

1

0

Autotune busy

Done/not working

Sign of PLL2 autotune error

Positive

6

PLL2 autotune error sign

0

1

Negative

[5:0] PLL2 Autotune Signed

Error[13:8] (MSB)

14-bit PLL2 V_TUNEerror count, MSB

Rev. B | Page 64 of 72

Data Sheet

HMC7044

Address Bits Bit Name

Settings Description

Autotune FSM state

Idle

Access

0x008F

[7:4] PLL2 Autotune FSM

R

State[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

Startup

Reset

Measure

Wait

Update loop to state 18 times

Round

Finish

[3:0] PLL2 SYNC FSM State[3:0]

PLL2 sync carry FSM state

Idle

0000

0100

0110

0111

1110

1100

Power up Section A of the FSM

Power up Section B of the FSM

Sending to N2

Power down Section A of the FSM

Power down Section B of the FSM

Reserved

0x0090

[7:0] Reserved

R

SYSREF Status Register (Register 0x0091)

Table 73. SYSREF Status Register

Address Bits Bit Name

0x0091 [7:5] Reserved

Channel outputs

FSM busy

Settings Description

Access

Reserved.

R

4

One of clock outputs FSM requested clock, and it is running.

[3:0] SYSREF FSM

State[3:0]

Indicates the current step of the SYSREF reseed process. Note that the three

different progressions are caused by different trigger events (reseed, pulse

generator, reserved).

0000

0010

0100

0101

0110

1010

1011

1100

1101

1110

1111

Reset.

Done.

Get ready.

Running (pulse generator).

Start.

Power up.

Clear reset.

Rev. B | Page 65 of 72

HMC7044

Data Sheet

Other Controls (Register 0x0096 to Register 0x00B8)

For optimum performance of the chip, Register 0x0096 to Register 0x00B8 must be programmed to a different value than their default

value.

Table 74. Reserved Registers

Address

0x0096

0x0097

0x0098

0x0099

0x009A

0x009B

0x009C

0x009D

0x009E

0x009F

0x00A0

0x00A1

0x00A2

0x00A3

0x00A4

0x00A5

0x00A6

0x00A7

0x00A8

0x00A9

0x00AB

0x00AC

0x00AD

0x00AE

0x00AF

0x00B0

0x00B1

0x00B2

0x00B3

0x00B4

0x00B5

0x00B6

0x00B7

0x00B8

Bits

Bit Name

Settings

Description

Access

RW

[7:0] Reserved

Reserved

Clock output driver low power setting (set to 0x4D instead of default value)

Clock output driver high power setting (set to 0xDF instead of default value)

Reserved

PLL1 more delay (PFD1, lock detect) (set to 0x06 instead of default value)

Reserved

PLL1 holdover DAC g_msetting (set to 0x06 instead of default value)

Reserved

V_TUNEpreset setting (set to 0x04 instead of default value)

Reserved

Rev. B | Page 66 of 72

Data Sheet

HMC7044

Clock Distribution (Register 0x00C8 to Register 0x0153)

The bit descriptions in Table 75 apply to all 14 channels.

Table 75. Channel 0 to Channel 13 Control

Address

Bits Bit Name

Settings¹Description

Access

0x00C8, 0x00D2, 0x00DC,

0x00E6, 0x00F0, 0x00FA,

0x0104, 0x010E, 0x0118,

0x0122, 0x012C, 0x0136,

0x0140, 0x014A

7

High performance

mode

High performance mode. Adjusts the divider and buffer RW

bias to improve swing/phase noise at the expense of

power.

6

5

SYNC enable

Slip enable

Susceptible to SYNC event. The channel can process a

SYNC event to reset its phase.

Susceptible to slip event. The channel can process a slip

request from SPI or GPI. Note that if slip enable is true

but multislip is off, a channel slips by 1 VCO cycle on an

explicit slip request broadcast from the SPI/GPI.

4

Reserved

Reserved.

[3:2] Start-Up Mode[1:0]

Configures the channel to normal mode with

asynchronous startup, or to a pulse generator mode

with dynamic start-up. Note that this must be set to

asynchronous mode if the channel is unused.

00

01

10

11

Asynchronous.

Reserved.

Dynamic.

1

0

Multislip enable

Channel enable

Allow multislip operation (default = 0 for SYSREF, 1 for

DCLK).

Do not engage automatic multislip on channel startup.

Multislip events after SYNC or pulse generator request,

if slip enable, Bit = 1.

0

1

Channel enable. If this bit is 0, channel is disabled.

0x00C9, 0x00D3, 0x00DD,

0x00E7, 0x00F1, 0x00FB,

0x0105, 0x010F, 0x0119,

0x0123, 0x012D, 0x0137,

0x0141, 0x014B

[7:0] 12-Bit Channel

Divider[7:0] (LSB)

12-bit channel divider setpoint LSB. The divider

supports even divide ratios from 2 to 4094. The

supported odd divide ratios are 1, 3, and 5. All even and

odd divide ratios have 50.0% duty cycle.

RW

0x00CA, 0x00D4, 0x00DE,

0x00E8, 0x00F2, 0x00FC,

0x0106, 0x0110, 0x011A,

0x0124, 0x012E, 0x0138,

0x0142, 0x014C

[7:4] Reserved

Reserved.

[3:0] 12-Bit Channel

Divider[11:8] (MSB)

12-bit channel divider setpoint MSB.

0x00CB, 0x00D5, 0x00DF,

0x00E9, 0x00F3, 0x00FD,

0x0107, 0x0111, 0x011B,

0x0125, 0x012F, 0x0139,

0x0143, 0x014D

[7:5] Reserved

Reserved.

[4:0] Fine Analog

Delay[4:0]

24 fine delay steps. Step size = 25 ps. Values greater

than 23 have no effect on analog delay.

0x00CC, 0x00D6, 0x00E0,

0x00EA, 0x00F4, 0x00FE,

0x0108, 0x0112, 0x011C,

0x0126, 0x0130, 0x013A,

0x0144, 0x014E

[7:5] Reserved

Reserved.

[4:0] Coarse Digital

Delay[4:0]

17 coarse delay steps. Step size = ½ VCO cycle. This flip

flop (FF)-based digital delay does not increase noise

level at the expense of power. Values greater than 17

have no effect on coarse delay.

0x00CD, 0x00D7, 0x00E1,

0x00EB, 0x00F5, 0x00FF,

0x0109, 0x0113, 0x011D,

0x0127, 0x0131, 0x013B,

0x0145, 0x014F

[7:0] 12-Bit Multislip

Digital Delay[7:0]

(LSB)

12-bit multislip digital delay amount LSB.

RW

Step size = (delay amount: MSB + LSB) × VCO cycles. If

multislip enable bit = 1, any slip events (caused by GPI,

SPI, SYNC, or pulse generator events) repeat the

number of times set by 12-Bit Multislip Digital

Delay[11:0] to adjust the phase by step size.

Rev. B | Page 67 of 72

HMC7044

Data Sheet

Address

Bits Bit Name

Settings¹Description

Access

0x00CE, 0x00D8, 0x00E2,

0x00EC, 0x00F6, 0x0100,

0x010A, 0x0114, 0x011E,

0x0128, 0x0132, 0x013C,

0x0146, 0x0150

[7:4] Reserved

Reserved.

RW

[3:0] 12-Bit Multislip

Digital Delay[11:8]

(MSB)

12-bit multislip digital delay amount MSB.

0x00CF, 0x00D9, 0x00E3,

0x00ED, 0x00F7, 0x0101,

0x010B, 0x0115, 0x011F,

0x0129, 0x0133, 0x013D,

0x0147, 0x0151

[7:2] Reserved

Reserved.

RW

[1:0] Output Mux

Selection[1:0]

Channel output mux selection.

Channel divider output.

Analog delay output.

Other channel of the clock group pair.

Input VCO clock (fundamental). Fundamental can also

be generated with 12-Bit Channel Divider[11:0] = 1.

00

01

10

11

0x00D0, 0x00DA, 0x00E4,

0x00EE, 0x00F8, 0x0102,

0x010C, 0x0116, 0x0120,

0x012A, 0x0134, 0x013E,

0x0148, 0x0152

[7:6] Force Mute[1:0]

Idle at Logic 0 selection (pulse generator mode only).

RW

Force to Logic 0 or V_CM

.

00

01

10

11

Normal mode (selection for DCLK).

Reserved.

Force to Logic 0.

Reserved.

5

Dynamic driver

enable

Dynamic driver enable (pulse generator mode only).

Driver is enabled/disabled with channel enable bit

Driver is dynamically disabled with pulse generator

events.

0

1

[4:3] Driver Mode[1:0]

Output driver mode selection.

00

01

10

11

CML mode.

LVPECL mode.

LVDS mode.

CMOS mode.

[2]

[1:0] Driver

Impedance[1:0]

Reserved

Reserved.

Output driver impedance selection for CML mode.

Internal resistor disable.

Internal 100 Ω resistor enable per output pin.

Reserved.

Internal 50 Ω resistor enable per output pin.

Reserved.

00

01

10

11

0x00D1, 0x00DB, 0x00E5,

0x00EF, 0x00F9, 0x0103,

0x010D, 0x0117, 0x0121,

0x012B, 0x0135, 0x013F,

0x0149, 0x0153

[7:0] Reserved

RW

¹X means don’t care.

Rev. B | Page 68 of 72

Data Sheet

HMC7044

EVALUATION PCB SCHEMATIC

60 TO 150

SECONDS

RAMP UP

3°C/SECOND MAX

EVALUATION PCB

260 – 5°C/260 + 0°C

For the circuit board used in the application, use RF circuit

design techniques. Ensure that signal lines have 50 Ω

impedance. Connect the package ground leads and exposed pad

directly to the ground plane (see Figure 52). Use a sufficient

number of via holes to connect the top and bottom ground

planes. The evaluation circuit board is available from Analog

Devices upon request.

217°C

150°C TO 200°C

RAMP DOWN

6°C/SECOND MAX

TIME (Second)

60 TO 180

SECONDS

20 TO 40

SECONDS

480 SECONDS MAX

The typical Pb-free reflow solder profile is shown in Figure 51.

Figure 51. Pb-Free Reflow Solder Profile

Figure 52. Evaluation PCB Layout, Top Side

Rev. B | Page 69 of 72

HMC7044

Data Sheet

Figure 53. Evaluation PCB Layout, Bottom Side

Rev. B | Page 70 of 72

Data Sheet

HMC7044

OUTLINE DIMENSIONS

10.10

10.00 SQ

9.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

52

51

68

1

0.50

BSC

EXPOSED

PAD

6.40

6.30 SQ

6.20

35

34

17

18

0.60

0.50

0.40

1.20 BSC

BOTTOM VIEW

8.00 REF

TOP VIEW

0.90

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VNND-2

Figure 54. 68-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

10 mm × 10 mm Body, Very Thin Quad

(HCP-68-1)

Dimensions shown in millimeters

NOTE 1

4.10

4.00

3.90

NOTE 6

2.10

2.00

1.90

16.10

16.00

15.90

1.85

1.75

1.65

0.35

0.30

0.25

A

Ø 1.5 ~ 1.6

11.60

11.50

11.40

NOTE 6

24.30

24.00

23.70

10.30

10.40

R0.3

MAX

10.20

NOTE 4

1.20

1.10

1.00

TOP VIEW

A

Ø 1.5 MIN

10.40

10.30

DETAIL A

NOTE 5

DIRECTION OF FEED

10.20

SECTION A-A

NOTE 4

0.25

NOTES:

1. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE ± 0.20

2. CAMBER IN COMPLIANCE WITH EIA 481

3. MATERIAL: CONDUCTIVE BLACK PO LYSTYRENE

4. MEASURED ON A PLANE 0.30 mm ABOVE THE BOTTOM OF

THE POCKET

R 0.25

DETAIL A

5. MEASURED FROM A PLANE ON THE INSIDE BOTTOM OF

THE POCKET TO THE TOP SURFACE OF THE CARRIER

6. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED

AS TRUE POSITION OF POCKET, NOT POCKET HOLE

Figure 55. LFCSP Tape and Reel Outline Dimensions

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range Lead Finish

MSL Rating

Package Description Package Option Branding²

7044

XXXX

7044

HMC7044LP10BE

–40°C to +85°C 100% matte tin MSL-3

68-Lead LFCSP_VQ

Evaluation Kit

HCP-68-1

HMC7044LP10BETR –40°C to +85°C

EK1HMC7044LP10B –40°C to +85°C

100% matte tin MSL-3

HCP-68-1

XXXX

¹E = RoHS Compliant Part.

²Four-digit lot number represented by XXXX.

Rev. B | Page 71 of 72

HMC7044

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D13033-0-11/16(B)

Rev. B | Page 72 of 72


型号：	HMC7044LP10BE
厂家：	ADI
描述：	High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B / JESD204C 衰减器 PC 电信电信集成电路
文件：	总73页 (文件大小：1631K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HMC7044LP10BE [ADI]

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