HMC8073 [ADI]
0.6 GHz to 3.0 GHz, 0.5 dB LSB, 6-Bit, Silicon Digital Step Attenuator;
| 型号： | HMC8073 |
| 厂家： | 
ADI |
| 描述： | 0.6 GHz to 3.0 GHz, 0.5 dB LSB, 6-Bit, Silicon Digital Step Attenuator |
| 文件： | 总13页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.6 GHz to 3.0 GHz, 0.5 dB LSB, 6-Bit,
Silicon Digital Step Attenuator
HMC8073
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
HMC8073
Attenuation range: 0.5 dB LSB steps to 31.5 dB
Low insertion loss
1.1 dB to 1.0 GHz
1.5 dB to 2.0 GHz
Tight attenuation accuracy
1
2
3
4
12 LE
VDD
A0
LOGIC
11 GND
10 GND
CONTROL
Less than 0.25 dB (plus 3% of attenuation state)
Low phase shift error: 4° phase shift to 1.0 GHz
Bidirectional use: 30 dBm high power handling
Internal dc block on the RFIN/RFOUT pins
High linearity
GND
RFIN
6-BIT DSA
9
RFOUT
P1dB: 31 dBm typical
Input IP3: 52 dBm typical
Figure 1.
Safe state transitions
Serial interface with TTL/CMOS
Up to 8 devices on a single data bus
Single-supply operation: 3.3 V to 5.0 V
ESD sensitivity rating: Class 1C (1 kV human body model)
16-lead, 3 mm × 3 mm LFCSP package: 9 mm2
APPLICATIONS
Cellular infrastructure
Microwave radios
Very small aperture terminals
Test equipment and sensors
GENERAL DESCRIPTION
The HMC8073 is a 6-bit digital step attenuator (DSA), operating
from 0.6 GHz to 3.0 GHz, that features 31.5 dB of attenuation
range with 0.5 dB steps.
The external address feature of the HMC8073 allows users to
control up to eight DSAs using a single bus. The DSA has an
on-chip regulator that supports a wide supply operating range
from 3.3 V to 5.0 V with no performance change in electrical
characteristics. The HMC8073 incorporates a complementary
metal-oxide semiconductor (CMOS)- and transistor transitory
logic (TTL)- compatible interface that supports serial (3-wire)
control of the attenuator.
The HMC8073 is implemented in a silicon process, offering
a fast settling time, low power consumption, and high
electrostatic discharge (ESD) robustness. The device features
safe state transitions, allowing attenuation state changes without
overshooting, and is optimized for excellent step accuracy and
high power and high linearity over frequency and temperature
range. The radio frequency (RF) input and output are internally
matched to 50 Ω and do not require any external matching
components. The design is bidirectional, and the RF input and
output are interchangeable.
The HMC8073 comes in an RoHS compliant, compact,
3 mm × 3 mm LFCSP package.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
HMC8073
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Insertion Loss, Return Loss, State Error, Normalized
Attenuation, Step Error, and Relative Phase.............................7
Input Power Compression and Third-Order Intercept ..........9
Theory of Operation ...................................................................... 10
Power-Up Sequence................................................................... 10
RF Input and Output................................................................. 10
Serial Control Interface ............................................................. 10
Attenuation State at Power-Up................................................ 10
Applications Information ............................................................. 12
Evaluation PCB........................................................................... 12
Packaging and Ordering Information......................................... 13
Outline Dimensions................................................................... 13
Ordering Guide .......................................................................... 13
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Electrical Specifications............................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions ............................ 6
Interface Schematics .................................................................... 6
Typical Performance Characteristics............................................. 7
REVISION HISTORY
4/2020—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Changes to Figure 3 and Table 5.................................................... 6
Change to Figure 25....................................................................... 12
4/2018—Revision 0: Initial Version
Rev. B | Page 2 of 13
Data Sheet
HMC8073
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 5.0 V, TA = 25°C, 50 ꢀ system, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ Max
Unit
GHz
dB
dB
dB
FREQUENCY RANGE
INSERTION LOSS
0.6
3.0
0.6 GHz to 1.0 GHz
1.0 GHz to 2.0 GHz
2.0 GHz to 3.0 GHz
0.6 GHz to 3.0 GHz
Delta between minimum and maximum
attenuation states
Between any successive attenuation states
Referenced to insertion loss; all
attenuation states
1.1
1.5
2.2
ATTENUATION
Range
31.5
0.5
dB
dB
Step Size, LSB
Accuracy
−(0.25 + 3% of
attenuation state)
+(0.25 + 3% of
attenuation state)
dB
Step Error
RETURN LOSS
RFIN, RFOUT
All attenuation states
All attenuation states
0.6 GHz to 1.0 GHz
1.0 GHz to 2.0 GHz
2.0 GHz to 3.0 GHz
0.6 GHz to 1.0 GHz
1.0 GHz to 2.0 GHz
2.0 GHz to 3.0 GHz
0.ꢀ
1ꢀ
12
9
dB
dBm
dBm
dBm
RELATIVE PHASE
ꢀ
1ꢀ
38
Degrees
Degrees
Degrees
SWITCHING CHARACTERISTICS
Rise and Fall Time (tRISE, tFALL
)
10% to 90% of RF output
50% VCTL to 90% of RF output
All attenuation states
65
260
ns
ns
On and Off Time (tON, tOFF
INPUT LINEARITY
)
0.1 dB Compression (P0.1dB)
1 dB Compression (P1dB)
Input Third-Order Intercept (IP3)
28
31
52
dBm
dBm
dBm
Two-tone input power = 16 dBm/tone, ∆f =
1 MHz
SUPPLY CURRENT (IDD)
VDD = 3.3 V
VDD = 5.0 V
0.3
0.3
mA
mA
CONTROL VOLTAGE THRESHOLD,
VCTL
For CLK, LE, SI, A0, A1, A2; <1 μA typical
Low, VIL
VDD = 3.3 V
VDD = 5.0 V
VDD = 3.3 V
VDD = 5.0 V
0
0
2
2
0.8
0.8
3.3
5.0
V
V
V
V
High, VIH
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage Range (VDD)
Digital Control Voltage Range
Maximum RF Input Power
3.3
0
5.0
VDD
30
V
V
dBm
°C
For CLK, LE, SI, A0, A1, A2
Worst case at maximum attenuation
Case Temperature (TCASE
)
−ꢀ0
+85
Rev. B | Page 3 of 13
HMC8073
Data Sheet
TIMING SPECIFICATIONS
Table 2.
Parameter
Description
Min
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
tꢀ
t5
t6
t7
t8
CLK period
CLK high
CLK low
SI to CLK setup time
CLK to SI hold time
LE to CLK setup time
CLK to LE hold time
LE pulse width
2.5
2.5
1.5
1.5
1.5
1.5
2.5
Timing Diagram
A2 TO A0
X
X
A2 TO A0 EXTERNAL ADDRESS SETTING
NEW ADDRESS
SI
CLK
LE
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
X
NEW WORD
X
t4 t5
t1 t2 t3
t7 t8 t6
Figure 2. Serial Control Timing Diagram
Rev. B | Page ꢀ of 13
Data Sheet
HMC8073
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
RF Input Power (TCASE = 85°C)
Digital Control Inputs (CLK, LE, SI, A0, A1, A2)
Supply Voltage (VDD)
Continuous Power Dissipation (PDISS
Temperature
30 dBm
−0.3 V to VDD + 0.ꢀ V
5.ꢀ V
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
)
0.999 W
Table 4. Thermal Resistance
Package Type
Channel Temperature
Storage
Maximum Reflow Temperature
ESD Sensitivity
1ꢀ0°C
−65°C to +150°C
260°C (MSL3 Rating)
θJC
Unit
CP-16-38
55
°C/W
Human Body Model (HBM)
1 kV (Class 1C)
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. B | Page 5 of 13
HMC8073
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
A0
1
2
3
4
12 LE
HMC8073
11 GND
TOP VIEW
10
9
GND
RFIN
GND
(Not to Scale)
RFOUT
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
VDD
Supply Voltage Pin.
2, 15, 16
A0, A1, A2
Parallel Control Voltage Inputs. Apply VIH or VIL to attain the desired address for attenuator. See Figure ꢀ for the
interface schematic.
3, 5 to 8, 10, 11 GND
Ground. The package bottom has an exposed metal pad that must connect to the PCB RF/dc ground. See
Figure 5 for the GND interface schematic.
ꢀ
RFIN
RFOUT
LE
Attenuator Input. This pin is ac-coupled and matched to 50 Ω. No external dc blocking capacitors are
required on the RF lines. See Figure 6 for the interface schematic.
Attenuator Output. This pin is ac-coupled and matched to 50 Ω. No external dc blocking capacitors are
required on the RF lines. See Figure 6 for the interface schematic.
Serial Interface Latch Enable Input. See the Theory of Operation section for more information. See Figure 7
for the interface schematic.
Serial Interface Clock Input. See the Theory of Operation section for more information. See Figure 7 for the
interface schematic.
9
12
13
1ꢀ
CLK
SI
Serial Interface Data Input. See the Theory of Operation section for more information. See Figure 7 for the
interface schematic.
EPAD
Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
V
V
DD
DD
ESD
16kΩ
16kΩ
RFIN,
RFOUT
A0, A1, A2
Figure 4. A0 to A2 Interface Schematic
Figure 6. RFIN and RFOUT Interface Schematic
V
V
DD
DD
16kΩ
16kΩ
LE, CLK, SI
GND
Figure 5. GND Interface Schematic
Figure 7. LE, CLK, and SI Interface Schematic
Rev. B | Page 6 of 13
Data Sheet
HMC8073
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, NORMALIZED ATTENUATION, STEP ERROR, AND RELATIVE
PHASE
VDD = 5.0 V, TA = 25°C, 50 ꢀ system, unless otherwise noted.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
0
–5
+85°C
+25°C
–40°C
–10
–15
–20
–25
–30
–35
0.5dB
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Insertion Loss vs. Frequency at Various Temperatures
Figure 11. Normalized Attenuation vs. Frequency, Major States Only
–5
0
NO ATTENUATION
NO ATTENUATION
0.5dB
0.5dB
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
1.0dB
2.0dB
–5
–10
–15
–20
–25
4.0dB
8.0dB
–10
16.0dB
31.5dB
–15
–20
–25
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Input Return Loss vs. Frequency, Major States Only
Figure 12. Output Return Loss vs. Frequency, Major States Only
1.5
1.0
0.7GHz
1.0GHz
2.0GHz
0.5dB
0.8
0.6
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
1.0
0.5
3.0GHz
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
0
5
10
15
20
25
30
0.5
1.0
1.5
2.0
2.5
3.0
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 10. State Error vs. Attenuation State
Figure 13. State Error vs. Frequency, Major States Only
Rev. B | Page 7 of 13
HMC8073
Data Sheet
1.0
0.8
1.0
0.8
0.7GHz
1.0GHz
2.0GHz
3.0GHz
0.5dB
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
0
4
8
12
16
20
24
28
32
0.5
1.0
1.5
2.0
2.5
3.0
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 14. Step Error vs. Attenuation State
Figure 16. Step Error vs. Frequency, Major States Only
40
35
30
25
20
15
10
5
30
20
0.7GHz
1.0GHz
2.0GHz
3.0GHz
10
0
0.5dB
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
–10
–20
–30
0
–5
–10
0
4
8
12
16
20
24
28
32
0.5
1.0
1.5
2.0
2.5
3.0
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 15. Relative Phase vs. Attenuation State
Figure 17. Relative Phase vs. Frequency, Major States Only
Rev. B | Page 8 of 13
Data Sheet
HMC8073
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = 5.0 V, TA = 25°C, 50 ꢀ system, unless otherwise noted.
35
35
30
25
20
15
+85°C
+25°C
–40°C
30
25
20
15
NO ATTENUATION
0.5dB
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
0.5
1.0
1.5
2.0
2.5
3.0
3.0
3.0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. P0.1dB vs. Frequency at Various Temperatures,
No Attenuation State
Figure 21. P0.1dB vs. Frequency, Major States Only
40
40
35
30
25
20
15
+85°C
+25°C
–40°C
35
30
25
20
15
NO ATTENUATION
0.5dB
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. P1dB vs. Frequency at Various Temperatures,
No Attenuation State
Figure 22. P1dB vs. Frequency, Major States Only
70
65
60
55
50
45
40
70
65
60
55
50
45
40
NO ATTENUATION
0.5dB
1.0dB
2.0dB
4.0dB
8.0dB
16.0dB
31.5dB
+85°C
+25°C
–40°C
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. Input IP3 vs. Frequency at Various Temperatures,
No Attenuation State
Figure 23. Input IP3 vs. Frequency, Major States Only
Rev. B | Page 9 of 13
HMC8073
Data Sheet
THEORY OF OPERATION
A simplified circuit diagram of the HMC8073 is shown in
Figure 24. The HMC8073 incorporates a 6-bit fixed attenuator
array that offers an attenuation range of 31.5 dB in 0.5 dB steps.
An on-chip driver provides control of the attenuator from a
3-wire serial peripheral interface (SPI) and features 3-bit address
pins (A0 to A2) to enable the control of up to eight devices on a
single bus.
The serial input data bits in LSB first format are clocked into
the shift register on the rising edge of the clock signal. The latch
enable signal must be kept low during data transmission.
Otherwise, the clock signal is masked by a high latch enable
with logical OR operation. When all 16 data bits are loaded, a
high going latch enable pulse updates the attenuation state.
Figure 2 and Table 2 provide the general signal requirements
and the specific timing requirements, respectively, that must be
met for the data transfer to be accomplished properly.
POWER-UP SEQUENCE
The HMC8073 requires a single dc voltage applied to the
VDD pin. The ideal power-up sequence is as follows:
In a bit stream to serial data input, the first eight bits (D[7:0])
are designated as attenuation data, and the last eight bits (A[7:0])
are designated as address data. D[6:1] specifies the attenuation
setting, whereas D0 and D7 are don’t care bits and can be set low
or high without affecting the attenuation state (see Table 7).
Bits A[2:0] must be matched to the address setting by the A2 to
A0 pins and A[7:3] must all be low so that D[6:1] can be
latched into the attenuator bits when the latch enable signal is
pulsed.
1. Connect the GND pin to a ground reference.
2. Apply a supply voltage to the VDD pin.
3. Power up the digital control inputs. The relative order of
the digital control inputs is not important.
4. Apply an RF input signal to RFIN or RFOUT.
RF INPUT AND OUTPUT
The attenuator in the HMC8073 is bidirectional. The RFIN and
RFOUT pins are interchangeable as the RF input and output
ports. The attenuator is internally matched to 50 Ω at both the
input and the output, and no external matching components are
required. There are internal dc blocking capacitors on the RFIN
and RFOUT pins, and no external dc blocking capacitors are
required on the RF lines.
ATTENUATION STATE AT POWER-UP
The HMC8073 powers up at a maximum attenuation if the LE pin
is kept low during the initial power-up. At initial power-up or
immediately after the initial power-up, when the serial input
data is not clocked to the device, and when the LE pin is set
high while keeping the A2 to A0 pins low, the HMC8073 is
latched into an insertion loss state due to the internal pull-
down resistors at the shift register outputs. If the address set by
the A2 to A0 pins is not equal to 000, the device stays at a
maximum attenuation even with the high latch enabled.
SERIAL CONTROL INTERFACE
The HMC8073 has a 3-wire SPI that consists of the serial data
input (SI), the clock (CLK), and the latch enable (LE) pins. The
serial control inputs are both TTL- and 5 V CMOS-compatible
{fix space issue} and can easily interface to most industry-standard
field programmable gate arrays (FPGAs) and microcontrollers.
Table 6. Attenuation State at Power-Up
Address Setting
Attenuation State
31.5 dB (Maximum)
0 dB (Reference)
LE
(A2, A1, A0 Pins)
Don’t care
000
≠ 000 (001, 010, 011, 100,
101, 110, 111)
As shown in Figure 24, the driver portion contains a 16-bit serial to
parallel shift register, an 8-bit comparator, and an 8-bit latch.
Low
High
High
31.5 dB (Maximum)
Rev. B | Page 10 of 13
Data Sheet
HMC8073
FIRST 8-BIT SHIFT REGISTER FOR ADDRESS SETTING
(ALL OUTPUTS GO TO LOW AT POWER-UP)
FIRST 8-BIT SHIFT REGISTER FOR ATTENUATION SETTING
(ALL OUTPUTS GO TO LOW AT POWER-UP)
SI
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CLK
LE
FIRST IN
D0'
LAST IN
A7'
A6'
A5'
A4'
A3'
A2'
A1'
A0'
D7'
D6'
D5'
D4'
D3'
D2'
D
D1'
D
6-BIT LATCH
D
D
Q
D
Q
Q
D
Q
Q
Q
8-BIT ADDRESS COMPARATOR
OUT = 1 IF A7' – A0' = A7 – A0
OUT
(ALL OUTPUTS GO TO LOW AT POWER-UP)
A7
A6
A5
A4
A3
A2
A1
A0
A2
A1
A0
6-BIT ATTENUATOR
16dB
8dB
4dB
2dB
1dB
0.5dB
RFOUT
RFIN
Figure 24. Simplified Circuit Diagram
Table 7. Attenuation Truth Table
Attenuation Control Input1
D7
D6
D5
D4
D3
D2
D1
D0
Attenuation State (dB)
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Low
Low
Low
Low
Low
Low
High
High
Low
Low
Low
Low
Low
High
Low
High
Low
Low
Low
Low
High
Low
Low
High
Low
Low
Low
High
Low
Low
Low
High
Low
Low
High
Low
Low
Low
Low
High
Low
High
Low
Low
Low
Low
Low
High
Don’t care
0 (reference)
0.5
1.0
2.0
ꢀ.0
8.0
16.0
31.5
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
1 Any combination of the control voltage input states shown in Figure 2ꢀ provides an attenuation equal to the sum of the bits selected.
Table 8. Address Truth Table
Address Control Input
A7
A6
A5
A4
A3
A2
A1
A0
Address Setting (A2, A1, A0 Pins)
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
Low
Low
High
High
Low
Low
High
High
Low
High
Low
High
Low
High
Low
High
000
001
010
011
100
101
110
111
Rev. B | Page 11 of 13
HMC8073
Data Sheet
APPLICATIONS INFORMATION
electrical and thermal performance, as many vias as possible are
arranged around the transmission lines and under the package
exposed pad. The evaluation board layout shown in Figure 25
serves as a recommendation for optimal and stable performance as
well as for improvement of thermal efficiency.
EVALUATION PCB
The EV1HMC8073LP3D with component placement is shown
in Figure 25. The EV1HMC8073LP3D is constructed of a 4-layer
material with a copper thickness of 0.7 mil on each layer. Every
copper layer is separated with a dielectric material. The top
dielectric material is 10 mil RO4350. The middle and bottom
dielectric material is FR-4, used for mechanical strength and
overall board thickness of approximately 62 mil, which allows
SMA connectors to be slipped in at the board edges.
The EV1HMC8073LP3D is grounded from the dc test point,
TP3. The dc supply must be connected to the dc test point,
TP1, of the EV1HMC8073LP3D. The decoupling capacitors are
populated on the supply trace to filter high frequency noise.
The RF input and output ports (RFIN and RFOUT) are connected
through 50 Ω transmission lines to the SMA connectors, J1 and
J2, respectively. All the digital control pins are connected through
digital signal traces to the 2 × 6-pin header, J5. A thru calibration
transmission line can estimate the loss of PCB over the
environmental conditions being evaluated.
All RF and dc traces are routed on the top copper layer. The RF
transmission lines are designed using a coplanar waveguide
(CPWG) model, with a width of 18 mil, spacing of 13 mil, and
dielectric thickness of 10 mil, to have a characteristic impedance of
50 ꢀ. The inner and bottom layers are grounded planes that
provide a solid ground for the RF transmission lines. For optimal
J1
J5
VDD_USB
TP2
600-01513-00-2
CLK
C2
VDD
GND
USB
GND
VDD
GND
GND
GND
A2
SI
U1
TP1
R1
A1
A0
VDD
LE
A1
A0
TP3
VDD
J2
Figure 25. EV1HMC8073LP3D Evaluation PCB
Table 9. Bill of Materials for EV1HMC8073LP3D PCB
Item
J1, J2
J5
TP1 to TP3
C2
Value1
Description
Manufacturer2
PCB mount SMA connectors
Socket strip, dual-row 2 × 6
Through hole mount test points
Capacitor, 0ꢀ02 package
ꢀ70 pF
0 Ω
R1
Resistor, 0ꢀ02 package
U1
PCB3
HMC8073 digital attenuator
600-01513-00 evaluation PCB
Analog Devices, Inc.
EV1HMC8073LP3Dꢀ from Analog Devices
1 Blank cells in the value column indicate that there is no specific value recommendation for the listed component.
2 Blank cells in the manufacturer column indicate that there is no specific manufacturer recommendation for the listed component.
3 Circuit board material is Arlon 25FR.
ꢀ Reference this number when ordering the full evaluation PCB. See the Ordering Guide section.
Rev. B | Page 12 of 13
Data Sheet
HMC8073
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
0.30
0.25
0.20
3.00 SQ
PIN 1
2.90
INDICATOR
AREA
PIN 1
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
13
16
0.50
BSC
12
1
EXPOSED
PAD
1.92
1.70 SQ
1.48
9
4
5
8
*
0.35
0.30
0.25
0.20 MIN
BOTTOM VIEW
TOP VIEW
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.95
0.85
0.75
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
*
COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4
WITH THE EXCEPTION OF PACKAGE EDGE TO LEAD EDGE.
Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(CP-16-38)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
MSL Rating2
MSL3
Package Description
Package Option
CP-16-38
CP-16-38
HMC8073LP3DE
HMC8073LP3DETR
EV1HMC8073LP3D
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
MSL3
1 All models are RoHS compliant.
2 See the Absolute Maximum Ratings section.
©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14678-4/20(B)
Rev. B | Page 13 of 13
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明