HMC8108LC5 [ADI]
9 GHz to 10 GHz, X-Band, GaAs, MMIC, Low Noise Converter;
| 型号： | HMC8108LC5 |
| 厂家： | 
ADI |
| 描述： | 9 GHz to 10 GHz, X-Band, GaAs, MMIC, Low Noise Converter |
| 文件： | 总18页 (文件大小：430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9 GHz to 10 GHz,
X-Band, GaAs, MMIC, Low Noise Converter
Data Sheet
HMC8108
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Conversion gain: 13 dB typical
Image rejection: 20 dBc typical
Noise figure: 2 dB typical
Input power for 1 dB compression: −4 dBm typical
Input third-order intercept: 6 dBm typical
Output saturated power: 10 dBm typical
LO leakage at the IF port: −20 dBm typical
LO leakage at the RF port: −37 dBm typical
32-terminal, 5 mm × 5 mm, ceramic leadless chip carrier (LCC)
NIC
NIC
1
2
3
4
5
6
7
8
24 NIC
23 BUFF_VD
22 NIC
LNA_VG1
NIC
21 NIC
RFIN
20 LOIN
19 NIC
APPLICATIONS
NIC
Point to point and point to multipoint radios
Military radar
Satellite communications
VCTRL
NIC
18 NIC
HMC8108
17 NIC
EPAD
Figure 1.
GENERAL DESCRIPTION
The HMC8108 is a compact, X-band, gallium arsenide (GaAs),
monolithic microwave integrated circuit (MMIC) in-phase/
quadrature (I/Q), low noise converter in a ceramic, leadless chip
carrier, RoHS compliant package. The HMC8108 converts radio
frequency (RF) input signals ranging from 9 GHz to 10 GHz to a
typical single-ended intermediate frequency (IF) signal of 60 MHz
at its output. This device provides a small signal conversion gain
of 13 dB with a noise figure of 2 dB and image rejection of 20 dBc.
The HMC8108 uses a low noise amplifier followed by an image
reject mixer that is driven by an active LO buffer amplifier. The
image reject mixer eliminates the need for a filter following the
low noise amplifier and removes thermal noise at the image
frequency. I/Q mixer outputs are provided, and an external 90°
hybrid is needed to select the required sideband. The HMC8108
is a much smaller alternative to hybrid style, image reject mixer,
downconverter assemblies and is compatible with surface-mount
manufacturing techniques.
Rev. 0
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Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC8108
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 14
Applications Information.............................................................. 15
Biasing Sequence........................................................................ 15
Results.......................................................................................... 15
Evaluation Board Information ................................................. 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
2/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 18
Data Sheet
HMC8108
SPECIFICATIONS
TA = −25°C, IF = 60 MHz, LNA_VD1/LNA_VD2 = +3 V, BUFF_VD = +3 V, VCTRL = −1 V, MIX_VG = −1.4 V, LO power= −5 dBm,
downconverter mode with lower side selected and external 90° hybrid at the IF ports, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
OPERATING CONDITIONS
Frequency Range
Radio Frequency
Local Oscillator
Intermediate Frequency
LO Input Level
RF
LO
IF
9
9
0.02
−10
10
10
1
GHz
GHz
GHz
dBm
0
PERFORMANCE
Conversion Gain
Gain Variation Range
Noise Figure
10
10
13
15
2
dB
dB
dB
NF
2.5
Image Rejection
Input Power for 1 dB Compression
Input Third-Order Intercept
Input Second-Order Intercept
Output Saturated Power
LO Leakage at the IF Port1
LO Leakage at the RF Port
RF Leakage at the IF Port1
Amplitude Balance1
Phase Balance1
15
2
20
−4
6
12
10
−20
−37
−27
3
dBc
P1dB
IP3
IP2
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
PSAT
−25
4
Degree
Return Loss
RF Port
LO Port
IF Port1
15
9
20
dB
dB
dB
POWER SUPPLY
LNA_VD1
LNA_VD2
BUFF_VD
20
30
40
mA
mA
mA
1 Measurements performed without external 90° hybrid at the IF ports.
Rev. 0 | Page 3 of 18
HMC8108
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Drain Bias Voltage
LNA_VD1
LNA_VD2
BUFF_VD
Gate Bias Voltage
LNA_VG1
LNA_VG2
MIX_VG
BUFF_VG
5.8 V
4.8 V
4.2 V
Table 3. Thermal Resistance
Package Type
E-32-11
θJA
θJC
Unit
93
119.47
°C/W
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
20 dBm
1 See JEDEC standard JESD51-2 for additional information on optimizing the
thermal impedance (PCB with 3 × 3 vias).
VCTRL
RF Input Power
ESD CAUTION
LO Input Power
24 dBm
Maximum Peak Reflow Temperature (MSL3)1
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Field Induced Charged Device Model (FICDM)
260°C
165°C
−40°C to +85°C
−65°C to 150°C
Class 0 (150 V)
Class C3 (250 V)
1 See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 4 of 18
Data Sheet
HMC8108
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NIC 1
NIC 2
LNA_VG1 3
24 NIC
23 BUFF_VD
NIC
22
21 NIC
HMC8108
4
NIC
RFIN 5
TOP VIEW
20
19
LOIN
NIC
(Not to Scale)
6
7
8
NIC
VCTRL
NIC
18 NIC
17 NIC
EPAD
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 4, 6, 8, 9, 11, 12, NIC
14, 17 to 19, 21, 22,
24, 25, 27, 29, 31
No Internal Connection. These pins are not connected internally.
3
5
LNA_VG1
RFIN
Gate Bias Voltage for the First Low Noise Amplifier. See Figure 3 for the interface schematic.
Radio Frequency Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the interface
schematic.
7
VCTRL
Voltage Control. Gate bias attenuation control for the low noise amplifier. See Figure 5 for the interface
schematic.
10
13, 28
15
16
20
23
26
30
32
LNA_VG2
IF_I, IF_Q
MIX_VG
BUFF_VG
LOIN
BUFF_VD
GND
LNA_VD2
LNA_VD1
EPAD
Gate Bias Voltage for the Second Low Noise Amplifier. See Figure 6 for the interface schematic.
In-Phase and Quadrature Intermediate Frequency Output Pins. See Figure 7 for the interface schematic.
Gate Bias Voltage for FET Mixer. See Figure 8 for the interface schematic.
Gate Bias Voltage for the Local Oscillator Buffer. See Figure 9 for the interface schematic.
Local Oscillator Input. This pin is ac-coupled and matched to 50 Ω. See Figure 10 for the interface schematic.
Drain Bias Voltage for the Local Oscillator Buffer. See Figure 11 for the interface schematic.
Ground Connect. This pin must be connected to RF/dc ground. See Figure 12 for the interface schematic.
Drain Bias Voltage for the Second Low Noise Amplifier. See Figure 13 for the interface schematic.
Drain Bias Voltage for the First Low Noise Amplifier. See Figure 14 for the interface schematic.
Exposed Pad. Connect the exposed pad to RF/dc ground. See Figure 12 for the interface schematic.
Rev. 0 | Page 5 of 18
HMC8108
Data Sheet
INTERFACE SCHEMATICS
LNA_VG1
BUFF_VG
Figure 3. LNA_VG1 Interface Schematic
Figure 9. BUFF_VG Interface Schematic
RFIN
LOIN
Figure 4. RFIN Interface Schematic
Figure 10. LOIN Interface Schematic
BUFF_VD
VCTRL
Figure 5. VCTRL Interface Schematic
Figure 11. BUFF_VD Interface Schematic
GND
LNA_VG2
Figure 6. LNA_VG2 Interface Schematic
Figure 12. GND and EPAD Interface Schematic
LNA_VD2
IF_I, IF_Q
Figure 7. IF_I and IF_Q Interface Schematic
Figure 13. LNA_VD2 Interface
LNA_VD1
MIX_VG
Figure 8. MIX_VG Interface Schematic
Figure 14. LNA_VD1 Interface Schematic
Rev. 0 | Page 6 of 18
Data Sheet
HMC8108
TYPICAL PERFORMANCE CHARACTERISTICS
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
20
16
12
8
20
16
12
8
10GHz
9.41GHz
9GHz
+85°C
+25°C
–40°C
4
4
0
9.0
0
–16
9.2
9.4
9.6
9.8
10.0
–14
–12
–10
–8
–6
–4
–2
0
RF FREQUENCY (GHz)
LO DRIVE (dBm)
Figure 15. Conversion Gain vs. RF Frequency over Temperature
Figure 18. Conversion Gain vs. LO Drive at Various RF Frequencies
20
16
16
12
8
12
8
–1.2V
–1V
–0.8V
–0.6V
–0.4V
–0.2V
0V
4
0
9GHz
9.34GHz
4
0
9.375GHz
9.41GHz
10GHz
–4
–24
–19
–14
–9
–4
1
6
9.0
9.2
9.4
9.6
9.8
10.0
RF INPUT POWER (dBm)
RF FREQUENCY (GHz)
Figure 16. Conversion Gain vs. RF Input Power at Various RF Frequencies
Figure 19. Conversion Gain vs. RF Frequency at Various Control Voltages
16
20
16
12
8
12
8
4
20MHz
60MHz
100MHz
500MHz
750MHz
1000MHz
10GHz
9.41GHz
4
0
0
9GHz
–4
–1.2
9.0
9.2
9.4
9.6
9.8
10.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
RF FREQUENCY (GHz)
CONTROL VOLTAGE (V)
Figure 20. Conversion Gain vs. RF Frequency at Various IF Frequencies
Figure 17. Conversion Gain vs. Control Voltage at Various RF Frequencies
Rev. 0 | Page 7 of 18
HMC8108
Data Sheet
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
10GHz
9.41GHz
9GHz
+85°C
+25°C
–40°C
0
9.0
0
–16
9.2
9.4
9.6
9.8
10.0
–14
–12
–10
–8
–6
–4
–2
0
RF FREQUENCY (GHz)
LO DRIVE (dBm)
Figure 21. Image Rejection vs. RF Frequency over Temperature
Figure 24. Image Rejection vs. LO Drive at Various RF Frequencies
40
35
30
25
20
15
40
35
30
25
20
15
–1.2V
–1V
–0.8V
–0.6V
–0.4V
–0.2V
0V
9GHz
10
10
5
9.34GHz
9.375GHz
9.41GHz
5
10GHz
0
–24
0
9.0
–19
–14
–9
–4
1
6
9.2
9.4
9.6
9.8
10.0
RF INPUT POWER (dBm)
RF FREQUENCY (GHz)
Figure 22. Image Rejection vs. RF Input Power at Various RF Frequencies
Figure 25. Image Rejection vs. RF Frequency at Various Control Voltages
40
35
30
25
20
15
40
35
20MHz
60MHz
100MHz
500MHz
750MHz
1000MHz
30
25
20
15
10
5
10GHz
10
9.41GHz
9GHz
5
0
–1.2
0
9.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
9.2
9.4
9.6
9.8
10.0
CONTROL VOLTAGE (V)
RF FREQUENCY (GHz)
Figure 23. Image Rejection vs. Control Voltage at Various RF Frequencies
Figure 26. Image Rejection vs. RF Frequency at Various IF Frequencies
Rev. 0 | Page 8 of 18
Data Sheet
HMC8108
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
12
10
8
12
10
8
10GHz
9.41GHz
9GHz
6
6
4
4
+85°C
+25°C
–40°C
2
2
0
9.0
0
–16
9.2
9.4
9.6
9.8
10.0
–14
–12
–10
–8
–6
–4
–2
0
RF FREQUENCY (GHz)
LO DRIVE (dBm)
Figure 27. Input Third-Order Intercept (IP3) vs. RF Frequency over
Temperature
Figure 30. Input Third-Order Intercept (IP3) vs. LO Drive at Various
RF Frequencies
12
10
8
25
20
–1.2V
–1V
–0.8V
–0.6V
–0.4V
–0.2V
0V
15
10
5
6
4
9GHz
9.34GHz
9.375GHz
2
9.41GHz
10GHz
0
–24
0
9.0
–19
–14
–9
–4
1
6
9.2
9.4
9.6
9.8
10.0
RF INPUT POWER (dBm)
RF FREQUENCY (GHz)
Figure 28. Input Third-Order Intercept (IP3) vs. RF Input Power at Various
RF Frequencies
Figure 31. Input Third-Order Intercept (IP3) vs. RF Frequency at Various
Control Voltages
25
12
20MHz
60MHz
100MHz
500MHz
750MHz
1000MHz
10
8
10GHz
20
9.41GHz
9GHz
15
6
10
5
4
2
0
–1.2
0
9.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
9.2
9.4
9.6
9.8
10.0
CONTROL VOLTAGE (V)
RF FREQUENCY (GHz)
Figure 29. Input Third-Order Intercept (IP3) vs. Control Voltage at Various RF
Frequencies
Figure 32. Input Third-Order Intercept (IP3) vs. RF Frequency at Various IF
Frequencies
Rev. 0 | Page 9 of 18
HMC8108
Data Sheet
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
20
16
12
8
20
16
12
8
10GHz
9.41GHz
9GHz
+85°C
+25°C
–40°C
4
4
0
–16
0
9.0
–14
–12
–10
–8
–6
–4
–2
0
9.2
9.4
9.6
9.8
10.0
LO DRIVE (dBm)
RF FREQUENCY (GHz)
Figure 36. Input Second-Order Intercept (IP2) vs. LO Drive at Various
RF Frequencies
Figure 33. Input Second-Order Intercept (IP2) vs. RF Frequency over
Temperature
30
25
20
15
10
35
9GHz
30
25
20
15
10
5
9.34GHz
9.375GHz
9.41GHz
10GHz
–1.2V
–1V
–0.8V
–0.6V
–0.4V
–0.2V
0V
5
0
9.0
0
–24
9.2
9.4
9.6
9.8
10.0
–19
–14
–9
–4
1
6
RF FREQUENCY (GHz)
RF INPUT POWER (dBm)
Figure 37. Input Second-Order Intercept (IP2) vs. RF Frequency at Various
Control Voltages
Figure 34. Input Second-Order Intercept (IP2) vs. RF Input Power at Various
RF Frequencies
20
16
12
8
30
25
20
15
10
5
10GHz
9.41GHz
9GHz
20MHz
60MHz
100MHz
500MHz
750MHz
1000MHz
4
0
0
9.0
9.2
9.4
9.6
9.8
10.0
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
RF FREQUENCY (GHz)
CONTROL VOLTAGE (V)
Figure 38. Input Second-Order Intercept (IP2) vs. RF Frequency at Various
IF Frequencies
Figure 35. Input Second-Order Intercept (IP2) vs. Control Voltage at Various
RF Frequencies
Rev. 0 | Page 10 of 18
Data Sheet
HMC8108
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
0
0
–2
–2
–4
–4
–6
–6
+85°C
+25°C
–40°C
–0.5V
–1V
0V
–8
–8
–10
9.0
–10
9.0
9.2
9.4
9.6
9.8
10.0
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 39. Input Power for 1 dB Compression (P1dB) vs. RF Frequency over
Temperature
Figure 42. Input Power for 1 dB Compression (P1dB) vs. RF Frequency at
Various Control Voltages
20
15
170
160
150
140
130
120
110
100
90
5
4
3
2
+85°C
+25°C
–40°C
10
5
0
–5
+85°C
+25°C
–40°C
–10
–15
–20
1
0
–30 –26 –22 –18 –14 –10
–6
–2
2
6
10
9.0
9.2
9.4
9.6
9.8
10.0
RF INPUT POWER (dBm)
RF FREQUENCY (GHz)
Figure 40. IF Output Power and Total Drain Current vs. RF Input Power over
Temperature
Figure 43. Noise Figure vs. RF Frequency over Temperature
10
16
10GHz
8
–0.5V
–1V
0V
9.41GHz
12
8
9GHz
6
4
2
0
4
0
9.0
–16
–14
–12
–10
–8
–6
–4
–2
0
9.2
9.4
9.6
9.8
10.0
LO DRIVE (dBm)
RF FREQUENCY (GHz)
Figure 41. Noise Figure vs. LO Drive at Various RF Frequencies
Figure 44. Noise Figure vs. RF Frequency at Various Control Voltages
Rev. 0 | Page 11 of 18
HMC8108
Data Sheet
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
16
12
8
5
4
3
2
1
0
10GHz
9.41GHz
9GHz
10GHz
9.41GHz
9GHz
4
0
–1.0
–0.8
–0.6
–0.4
–0.2
0
10
20
30
40
50
60
70
80
90 100 110 120
CONTROL VOLTAGE (V)
IF FREQUENCY (MHz)
Figure 45. Noise Figure vs. Control Voltage at Various RF Frequencies
Figure 47. Noise Figure vs. IF Frequency at Various RF Frequencies
6
5
4
3
2
10MHz
20MHz
30MHz
40MHz
50MHz
60MHz
70MHz
80MHz
90MHz
100MHz
110MHz
120MHz
1
0
9.0
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
Figure 46. Noise Figure vs. RF Frequency at Various IF Frequencies
Rev. 0 | Page 12 of 18
Data Sheet
HMC8108
Measurements performed without external 90° hybrid at the IF ports and TA = −25°C, unless otherwise noted.
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–5
–5
–10
–15
–20
–25
–30
–10
–15
–20
–25
9.0
9.2
9.4
9.6
9.8
10.0
9.0
9.4
9.8
10.2
10.6
11.0
RF FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 48. RF Return Loss vs. RF Frequency over Temperature
Figure 51. LO Return Loss vs. LO Frequency over Temperature
0
0
LO TO RF
LO TO IF_I
LO TO IF_Q
RF TO IF_I
RF TO IF_Q
IF_I AT +85°C
IF_I AT +25°C
IF_I AT –40°C
IF_Q AT +85°C
IF_Q AT +25°C
IF_Q AT –40°C
–5
–10
–15
–20
–25
–30
–10
–20
–30
–40
–50
0
0.2
0.4
0.6
0.8
1.0
9.0
9.2
9.4
9.6
9.8
10.0
IF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 49. In-Phase and Quadrature IF Output Return Loss vs. IF Frequency
over Temperature
Figure 52. Leakage vs. RF Frequency
6
2
0
+85°C
4
2
+25°C
–40°C
–2
–4
–6
–8
0
+85°C
+25°C
–40°C
–2
–4
9.0
9.2
9.4
9.6
9.8
10.0
9.0
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 50. Amplitude Balance vs. RF Frequency over Temperature
Figure 53. Phase Balance vs. RF Frequency over Temperature
Rev. 0 | Page 13 of 18
HMC8108
Data Sheet
THEORY OF OPERATION
The HMC8108 is a X-band, low noise converter with integrated
LO buffers that converts RF input signals ranging from 9 GHz
to 10 GHz down to a typical single-ended IF signal of 60 MHz
at its output. See Figure 54 for a functional block diagram of the
circuit architecture of the HMC8108.
The RF input signal passes through two stages of low noise
amplification. The preamplified RF input signal then splits
through an internal hybrid to feed two singly balanced passive
mixers. A power divider followed by three LO buffer amplifiers
drives the two I and Q mixer cores to convert the amplified RF
input frequencies to a 60 MHz typical single-ended IF. A variable
attenuator allows gain control ranging from 10 dB to 30 dB.
VCTRL LNA_VD1 LNA_VD2
IF_Q
BUFF_VD
HYBRID
MIX
MIX
RFIN
LNA1
LNA2
ESD
ATTENUATOR
LOIN
BUFF3
BUFF2
BUFF1
DIV
LNA_VG1 LNA_VG2
MIX_VG IF_I
BUFF_VG
Figure 54. Functional Block Diagram of the Circuit Architecture
Rev. 0 | Page 14 of 18
Data Sheet
HMC8108
APPLICATIONS INFORMATION
A typical lower sideband application circuit is shown in Figure 57.
The IF_Q output signal of the HMC8108 is connected to the
90° port of the hybrid coupler followed by a low-pass filter to
produce a lower sideband IF output signal. The LO input signal
passes through a voltage control oscillator (VCO) followed by
an optional buffer amplifier, a 2× frequency multiplier, and an
optional band-pass filter before entering the LO port of the
device. Band-pass filter and LO buffer are optional and depend
on the VCO specification and the LO input power requirement.
External capacitors of 0.6 pF, 1 nF, 10 nF, and 100 nF, and 5.6 nH
inductors are connected to the input voltage pin of the device.
The IF_I and IF_Q pins are dc-coupled and must not source or
sink more than 3 mA of current or device malfunction or possible
device failure may result. For applications not requiring
operation to dc, use an off chip dc blocking capacitor.
To turn off the HMC8108, take the following steps:
1. Turn off the LO and RF signal source.
2. Turn off the LNA_VD1, LNA_VD2, and BUFF_VD power
supplies.
3. Turn off the LNA_VG1, LNA_VG2, BUFF_VG, MIX_VG,
and VCTRL power supplies. Refer to Figure 55 for the
HMC8108 lab bench setup.
RF INPUT
POWER
SUPPLY
POWER
SUPPLY
BIASING SEQUENCE
90° HYBRID FOR
I/Q IF OUTPUT
90°
0°
The HMC8108 uses amplifier and LO buffer stages. These active
stages use depletion mode, pseudomorphic high electron
mobility transfer (pHEMT) transistors.
To avoid transistor damage, follow these power-up bias
sequence steps:
POWER
SUPPLY
1. Set the LNA_VG1, LNA_VG2, and BUFF_VG power
supplies to −2 V and the MIX_VG power supply to +1.4 V.
Do not turn on the power supplies.
LO INPUT
SPECTRUM
ANALYZER
Figure 55. HMC8108 Lab Bench Setup
2. Set the LNA_VD1, LNA_VD2, and BUFF_VD power
supplies to 3 V. Do not turn on the power supplies.
3. Set the VCTRL power supply to −1 V. Do not turn on the
power supply.
4. Turn on the power supplies in Step 1, Step 2, and Step 3 in
order.
5. Adjust the LNA_VG1, LNA_VG2, and BUFF_VG power
supplies between −2 V and 0 V to achieve an quiescent
current LNA_ID1, LNA_ID2, and BUFF_ID = 20 mA,
30 mA, and 40 mA, respectively.
6. Connect the signal generator to the RF and LO input.
7. Connect the 90° hybrid to the IF_I and IF_Q output. Note
that IF_Q is connected to the 90° port of the hybrid. Under
this condition, the lower sideband is selected.
8. Turn on the LO and RF input to see the output on the
spectrum analyzer.
RESULTS
Figure 56 shows the expected results when testing the HMC8108
with the following operating conditions:
RF = −15 dBm at 9.44 GHz
LO = −5 dBm at 9.5 GHz
The on board IF_Q port is connected to the 90° port of the
hybrid.
The lower sideband is selected.
Note that hybrid, cable, and board loss were not deembedded.
RWB 6.25kHz
VBW 20kHz
SWT 420ms
MARKER 1 [T1]
–4.31dBm
REF 0dBm
ATT 5dB
60.00MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
CENTER 59.511MHz
1.63MHz/
SPAN 16.3MHz
Figure 56. Test Results at IF = 60 MHz
Rev. 0 | Page 15 of 18
HMC8108
Data Sheet
Figure 57. Typical Application Circuit
Rev. 0 | Page 16 of 18
Data Sheet
HMC8108
directly to the ground plane. A sufficient number of via holes
EVALUATION BOARD INFORMATION
connect the top and bottom ground planes. The full evaluation
circuit board shown in Figure 58 is available from Analog Devices,
Inc., upon request.
RF circuit design techniques were implemented for the evaluation
board PCB shown in Figure 58. Signal lines have 50 Ω impedance,
and the package ground leads and exposed pad are connected
Figure 58. EV1HMC8108LC5 Evaluation PCB Top Layer
Table 5. Bill of Material for the EV1HMC8108LC5 Evaluation PCB
Reference Designator
Quantity
Description
600-01494-00-1
J1, J2
J3, J7
J4
J5, J6
C1
C2 to C12
C13 to C16, C18 to C21
C22 to C29
C30 to C32
L1 to L3
1
2
2
1
2
1
11
8
8
3
3
3
1
Evaluation board PCB; circuit board material: Rogers 4350 or Arlon 25FR
SMA connectors, SRI
SMA connectors, Johnson
Connector header, 2 mm ,12-position vertical, SMT
Terminal strips, single row, 3-pin, SMT
Ceramic capacitor, 0.5 pF, 50 V, C0G, 0402
Ceramic capacitors, 0.6 pF, 0.1 pF, 50 V, C0G, 0402
Ceramic capacitors, 1 nF, 50 V, X7R, 0402
Ceramic capacitors, 10 nF, 50 V, 10%, X7R, 0402
Ceramic capacitors, 100 nF, 16 V, 10%, X7R, 0402
Inductors, 5.6 nH, 0402, 5%, 760 mA
TP1 to TP3
U1
Test points, PC compact, SMT
Device under test (DUT), HMC8108LC5
Rev. 0 | Page 17 of 18
HMC8108
Data Sheet
OUTLINE DIMENSIONS
5.05
4.90 SQ
4.75
0.36
0.30
0.24
PIN 1
INDICATOR
PIN 1
(0.32 × 0.32)
25
32
24
1
0.50
BSC
EXPOSED
PAD
3.50 SQ
17
8
16
9
BOTTOM VIEW
3.50 REF
TOP VIEW
SIDE VIEW
4.10 BSC
1.12 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
SECTION OF THIS DATA SHEET.
Figure 59. 32-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package Body
Material
MSL
Package
Model1
Lead Finish
Rating2 Package Description Option
Branding3
HMC8108LC5
−40°C to +85°C Alumina Ceramic Gold over Nickel MSL3
32-Terminal LCC
32-Terminal LCC
32-Terminal LCC
Evaluation Board
E-32-1
E-32-1
E-32-1
H8108
XXXX
H8108
XXXX
H8108
XXXX
HMC8108LC5TR
−40°C to +85°C Alumina Ceramic Gold over Nickel MSL3
HMC8108LC5TR-R5 −40°C to +85°C Alumina Ceramic Gold over Nickel MSL3
EV1HMC8108LC5 −40°C to +85°C Alumina Ceramic
1 The HMC8108LC5, the HMC8108LC5TR, and the HMC8108LC5TR-R5 are RoHS Compliant Parts.
2 See the Absolute Maximum Ratings section.
3 The HMC8108LC5, the HMC8108LC5TR, and the HMC8108LC5TR-R5 four-digit lot numbers are XXXX.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15133-0-2/17(0)
Rev. 0 | Page 18 of 18
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