HMC8121 [ADI]
HMC8121;
ADI 
81 GHz to 86 GHz,
E-Band Variable Gain Amplifier
Data Sheet
HMC8121
FEATURES
GENERAL DESCRIPTION
Gain: 22 dB typical
The HMC8121 is an integrated E-band, gallium arsenide (GaAs),
pseudomorphic (pHEMT), monolithic microwave integrated
circuit (MMIC), variable gain amplifier and/or driver amplifier
that operates from 81 GHz to 86 GHz. The HMC8121 provides up
to 22 dB of gain, 20 dBm output P1dB, 27.5 dBm of OIP3, and
21 dBm of PSAT while requiring only 265 mA from a 4 V power
supply. Two gain control voltages (VCTL1 and VCTL2) are provided
to allow up to 17 dB of variable gain control. The HMC8121
exhibits excellent linearity and is optimized for E-band
communications and high capacity wireless backhaul radio
systems. All data is taken with the chip in a 50 Ω test fixture
connected via a 3 mil wide × 0.5 mil thick × 7 mil long ribbon
on each port.
Wide gain control range: 17 dB typical
Output third-order intercept (OIP3): 27.5 dBm typical
Output power for 1 dB compression (P1dB): 20 dBm typical
Saturated output power (PSAT): 21 dBm typical
DC supply: 4 V at 265 mA
No external matching required
Die size: 3.599 mm × 1.369 mm × 0.05 mm
APPLICATIONS
E-band communication systems
High capacity wireless backhaul radio systems
Test and measurement
FUNCTIONAL BLOCK DIAGRAM
1
2
3
HMC8121
4
5
6
RFOUT
1.6kΩ
1.6kΩ
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
Figure 1.
Rev. B
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HMC8121
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 12
Typical Application Circuit........................................................... 13
Assembly Diagram ..................................................................... 14
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Interface Schematics..................................................................... 6
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs............................................................................................. 15
Handling Precautions ................................................................ 15
Mounting..................................................................................... 15
Wire Bonding.............................................................................. 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/2017—Rev. A to Rev. B
Updated Outline Dimensions....................................................... 16
2/2016—Revision A: Initial Version
Rev. B | Page 2 of 16
Data Sheet
HMC8121
SPECIFICATIONS
TA = 25°C, VDDx = 4 V, VCTLx = −5 V, unless otherwise noted.
Table 1.
Min
81
Typ
Max
Unit
Parameter
OPERATING CONDITIONS
RF Frequency Range
PERFORMANCE
86
GHz
Gain
19
22
dB
Gain Variation over Temperature
Gain Control Range
Output Power for 1 dB Compression (P1dB)
0.03
17
dB/°C
dB
12
16
20
dBm
dBm
dBm
dB
Saturated Output Power (PSAT
)
21
Output Third-Order Intercept (OIP3) at Maximum Gain1
27.5
12
Input Return Loss
Output Return Loss
10
dB
POWER SUPPLY
Total Supply Current (IDD)2
265
mA
1 Data taken at power input (PIN) = −10 dBm/tone, 1 MHz spacing.
2 Set VCTL1/VCTL2 = −5 V and then adjust VGG1/VGG2, VGG3, VGG4, VGG5, and VGG6 from −2 V to 0 V to achieve a total drain current (IDD) = 265 mA.
Rev. B | Page 3 of 16
HMC8121
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Table 3. Thermal Resistance
Package Type
Parameter
Rating
1
Drain Bias Voltage (VDD1 to VDD6
Gate Bias Voltage (VGG1/VGG2, VGG3 to VGG6
Gain Control Voltage (VCTL1 and VCTL2
Maximum Junction Temperature (to Maintain
1 Million Hours Mean Time to Failure (MTTF))
)
4.5 V
θJC
69.5
Unit
)
−3 V to 0 V
−6 V to 0 V
175°C
28-Pad Bare Die [CHIP]
°C/W
)
1 Based on ABLEBOND® 84-1LMIT as die attach epoxy with thermal
conductivity of 3.6 W/mK.
Storage Temperature Range
Operating Temperature Range
−65°C to +150°C
−55°C to +85°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 4 of 16
Data Sheet
HMC8121
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
GND
RFOUT
GND
HMC8121
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
Figure 2. Pad Configuration
Table 4. Pad Function Descriptions
Pad No. Mnemonic
Description
Ground Connection (See Figure 3).
1, 3, 4, 6, 10, 13, 16, GND
19, 24, 27
2
5
7
RFIN
RFOUT
VDET
RF Input. DC couple RFIN and match it to 50 Ω (see Figure 4).
RF Output. DC couple RFOUT and match it to 50 Ω (see Figure 5).
Detector Voltage for the Power Detector (See Figure 6). VDET is the dc voltage representing the RF
output power rectified by the diode, which is biased through an external resistor. Refer to the typical
application circuit for the required external components (see Figure 38).
8
VREF
Reference Voltage for the Power Detector (See Figure 6). VREF is the dc bias of the diode biased through
an external resistor used for the temperature compensation of VDET. Refer to the typical application
circuit for the required external components (see Figure 38).
9, 12, 15, 18, 25, 26 VDD6 to VDD1
Drain Bias Voltage for the Variable Gain Amplifier (See Figure 7). For the required external
components, see Figure 38.
11, 14, 17, 20, 28
21, 22
VGG6 to VGG3
,
Gate Bias Voltage for the Variable Gain Amplifier (See Figure 8). For the required external components,
see Figure 38.
Gain Control Voltage for the Variable Gain Amplifier (See Figure 9). For the required external
components, see Figure 38.
V
GG1/VGG2
VCTL2, VCTL1
23
ENVDET
GND
Envelope Detector (See Figure 10). For the required external components, see Figure 38.
Ground. Die bottom must be connected to the RF/dc ground (see Figure 3).
Die Bottom
Rev. B | Page 5 of 16
HMC8121
Data Sheet
INTERFACE SCHEMATICS
V
, V
DD5
, V ,
DD4
DD6
V
, V
, V
DD3
DD2
DD1
GND
Figure 7. VDD6 to VDD1 Interface
Figure 3. GND Interface
RFIN
1.6kΩ
V
TO V ,
GG3
GG6
V
/V
GG1 GG2
Figure 8. VGG6 to VGG3, VGG1/VGG2 Interface
Figure 4. RFIN Interface
RFOUT
1.6kΩ
V
, V
CTL1
CTL2
Figure 9. VCTL2, VCTL1 Interface
Figure 5. RFOUT Interface
V
, V
ENV
DET
DET
REF
Figure 6. VDET, VREF Interface
Figure 10. ENVDET Interface
Rev. B | Page 6 of 16
Data Sheet
HMC8121
TYPICAL PERFORMANCE CHARACTERISTICS
30
30
28
26
24
22
20
18
16
14
12
10
T
T
T
= –55°C
= +25°C
= +85°C
A
A
A
20
GAIN
INPUT RETURN LOSS
OUTPUT RETURN LOSS
10
0
–10
–20
–30
79
80
81
82
83
84
85
86
87
88
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 11. Broadband Gain and Return Loss Response vs. Frequency,
CTL1/VCTL2 = −5 V
Figure 14. Gain vs. Frequency at Various Temperatures,
V
VCTL1/VCTL2 = −5 V
30
25
20
15
10
5
30
25
20
15
10
5
RF = 81GHz
RF = 82GHz
RF = 83GHz
RF = 84GHz
RF = 85GHz
RF = 86GHz
V
V
V
V
= –5.0V
= –4.0V
= –3.5V
= –3.0V
V
= –2.6V
= –2.2V
= –2.0V
= –1.5V
V
V
V
V
= –1.2V
= –1.0V
= –0.5V
= 0V
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
V
V
V
0
0
–5.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
FREQUENCY (GHz)
CONTROL VOLTAGE (V)
Figure 12. Gain vs. Frequency at Various Control Voltages
Figure 15. Gain vs. Control Voltage at Various RF Frequencies
0
0
T
T
T
= –55°C
= +25°C
= +85°C
T
T
T
= –55°C
= +25°C
= +85°C
A
A
A
A
A
A
–4
–8
–4
–8
–12
–16
–20
–24
–12
–16
–20
–24
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5
86.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. Input Return Loss vs. Frequency at Various Temperatures,
VCTL1/VCTL2 = −5 V
Figure 16. Output Return Loss vs. Frequency at Various Temperatures,
VCTL1/VCTL2 = −5 V
Rev. B | Page 7 of 16
HMC8121
Data Sheet
0
0
–4
V
V
V
V
= –5.0V
= –4.0V
= –3.5V
= –3.0V
V
V
V
V
= –2.6V
= –2.2V
= –2.0V
= –1.5V
V
V
= –1.2V
= –1.0V
V
V
V
V
= –5.0V
= –4.0V
= –3.5V
= –3.0V
V
V
V
V
= –2.6V
= –2.2V
= –2.0V
= –1.5V
V
V
= –1.2V
= –1.0V
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
CTLx
–5
–10
–15
–20
–25
–30
–8
–12
–16
–20
–24
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. Input Return Loss vs. Frequency at Various Control Voltages
Figure 20. Output Return Loss vs. Frequency at Various Control Voltages
–40
30
29
28
27
26
25
24
23
22
T
T
T
= –55°C
= +25°C
= +85°C
A
A
A
–45
–50
–55
–60
–65
–70
T
T
T
= –55°C
= +25°C
= +85°C
A
A
A
21
20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. Output IP3 vs. Frequency at Various Temperatures,
PIN = −10 dBm/Tone, VCTL1/VCTL2 = −5 V
Figure 18. Reverse Isolation vs. Frequency at Various Temperatures,
VCTL1/VCTL2 = −5 V
25
24
23
22
21
20
19
18
17
16
15
25
T
T
T
= –55°C
= +25°C
= +85°C
T
T
T
= –55°C
= +25°C
= +85°C
A
A
A
A
A
A
24
23
22
21
20
19
18
17
16
15
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. PSAT vs. Frequency at Various Temperatures,
VCTL1/VCTL2 = −5 V
Figure 19. Output P1dB vs. Frequency at Various Temperatures,
VCTL1/VCTL2 = −5 V
Rev. B | Page 8 of 16
Data Sheet
HMC8121
25
20
32
28
24
20
16
12
8
GAIN
IIP3
GAIN
IIP3
OIP3
OIP3
15
10
5
0
–5
–10
–15
–20
4
0
–5.0
265
245
225
205
185
165
145
125
105
85
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
DRAIN CURRENT (mA)
CONTROL VOLTAGE (V)
Figure 26. Gain and Input/Output IP3 vs. Drain Current,
PIN = −5 dBm/Tone, VCTL1/VCTL2 = −1 V, RF = 81 GHz,
Drain Current = (IDD1/IDD2 Fixed at 50 mA) + (IDD3 to IDD6 Swept)
Figure 23. Gain and Input/Output IP3 vs. Control Voltage,
PIN = −10 dBm/Tone, RF = 81 GHz
32
28
24
20
16
12
8
25
GAIN
IIP3
OIP3
GAIN
IIP3
OIP3
20
15
10
5
0
–5
–10
4
–15
0
–5.0
–20
265
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
245
225
205
185
165
145
125
105
85
CONTROL VOLTAGE (V)
DRAIN CURRENT (mA)
Figure 24. Gain and Input/Output IP3 vs. Control Voltage,
PIN = −10 dBm/Tone, RF = 83.5 GHz
Figure 27. Gain and Input/Output IP3 vs. Drain Current,
PIN = −5 dBm/Tone, VCTL1/VCTL2 = −1 V, RF = 83.5 GHz,
Drain Current = (IDD1/IDD2 Fixed at 50 mA) + (IDD3 to IDD6 Swept)
25
32
28
24
20
16
12
8
GAIN
IIP3
OIP3
GAIN
IIP3
OIP3
20
15
10
5
0
–5
–10
4
–15
–20
265
0
–5.0
245
225
205
185
165
145
125
105
85
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
DRAIN CURRENT (mA)
CONTROL VOLTAGE (V)
Figure 28. Gain and Input/Output IP3 vs. Drain Current,
PIN = −5 dBm/Tone, VCTL1/VCTL2 = −1 V, RF = 86 GHz,
Figure 25. Gain and Input/Output IP3 vs. Control Voltage,
PIN = −10 dBm/Tone, RF = 86 GHz
Drain Current = (IDD1/IDD2 Fixed at 50 mA) + (IDD3 to IDD6 Swept)
Rev. B | Page 9 of 16
HMC8121
Data Sheet
24
20
16
12
8
350
330
310
290
270
250
230
10
5
P
OUT
GAIN
0
PAE
I
DD
–5
–10
I
= 265mA
= 250mA
= 225mA
= 200mA
= 175mA
= 150mA
I
I
I
I
I
I
= 140mA
= 130mA
= 120mA
= 110mA
= 100mA
= 90mA
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
I
I
4
–15
I
I
I
0
–15
–20
–13
–11
–9
–7
–5
–3
–1
1
3
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 29. Gain vs. Frequency at Various Drain Currents,
PIN = −5 dBm/Tone, VCTL1/VCTL2 = −1 V,
Figure 32. POUT, Gain, PAE, and IDD vs. Input Power,
CTL1/VCTL2 = −5 V, RF = 81 GHz
V
Drain Current = (IDD1/IDD2 fixed at 50 mA) + (IDD3 to IDD6 Swept)
24
20
16
12
8
350
330
24
20
16
12
8
350
330
310
290
270
250
230
P
P
OUT
OUT
GAIN
GAIN
310
290
270
250
230
PAE
PAE
I
I
DD
DD
4
4
0
–15
0
–15
–13
–11
–9
–7
–5
–3
–1
1
3
–13
–11
–9
–7
–5
–3
–1
1
3
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 30. POUT, Gain, PAE, and IDD vs. Input Power,
CTL1/VCTL2 = −5 V, RF = 83.5 GHz
Figure 33. POUT, Gain, PAE, and IDD vs. Input Power,
VCTL1/VCTL2 = −5 V, RF = 86 GHz
V
10
0.40
RF = 81GHz
RF = 83.5GHz
RF = 86GHz
100MHz TONE SPACING
300MHz TONE SPACING
500MHz TONE SPACING
750MHz TONE SPACING
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1
0.1
0.01
0.001
–4
0
4
8
12
16
20
–20
–18
–16
–14
–12
–10
–8
–6
–4
OUTPUT POWER (dBm)
TOTAL INPUT POWER (dBm)
Figure 31. Detector Output Voltage (VREF – VDET) vs. Output Power at
Various RF Frequencies, VCTL1/VCTL2 = −5 V
Figure 34. Envelope Detector Peak-to-Peak Output Voltage vs. Total Input
Power at Various Tone Spacings, RF = 81 GHz, VCTL1/VCTL2 = −5 V,
VDET = 4 V with 150 Ω Load Impedance at ENVDET
Rev. B | Page 10 of 16
Data Sheet
HMC8121
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.40
100MHz TONE SPACING
300MHz TONE SPACING
500MHz TONE SPACING
750MHz TONE SPACING
100MHz TONE SPACING
300MHz TONE SPACING
500MHz TONE SPACING
750MHz TONE SPACING
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–20
–18
–16
–14
–12
–10
–8
–6
–4
TOTAL INPUT POWER (dBm)
TOTAL INPUT POWER (dBm)
Figure 36. Envelope Detector Peak-to-Peak Output Voltage vs. Total Input
Power at Various Tone Spacings, RF = 86 GHz, VCTL1/VCTL2 = −5 V,
Figure 35. Envelope Detector Peak-to-Peak Output Voltage vs. Total Input
Power at Various Tone Spacings, RF = 83.5 GHz, VCTL1/VCTL2 = −5 V,
VDET = 4 V with 150 Ω Load Impedance at ENVDET
VDET = 4 V with 150 Ω Load Impedance at ENVDET
Rev. B | Page 11 of 16
HMC8121
Data Sheet
THEORY OF OPERATION
The circuit architecture of the HMC8121 variable gain amplifier
is shown in Figure 37. The HMC8121 uses multiple gain stages
and staggered voltage variable attenuation stages to form a low
noise, high linearity variable gain amplifier with a gain range of
~17 dB. The first stage is a low noise preamp, which is followed
by the first voltage variable attenuator in the signal path. A
portion of the signal is coupled away and further amplified
before driving an on-chip envelope detector. The envelope
detector provides an output that is proportional to the peak
envelope power of the incoming signal. After the first
attenuator, a second stage amplifier provides additional gain
and isolation before driving the second variable attenuator
block. Three cascaded gain stages follow the second variable
attenuator. At the output of the last stage, another coupler taps
off a small portion of the output signal. The coupled signal is
presented to an on-chip diode detector for external monitoring
of the output power. A matched reference diode is included to
help correct for detector temperature dependencies. See the
application circuit in Figure 38 for further details on biasing the
different blocks and utilizing the detector features.
RFIN
RFOUT
ENV
DET
ENV
V
V
V
V
DET
DET
CTL1
CTL2
REF
Figure 37. Variable Gain Amplifier Circuit Architecture
Rev. B | Page 12 of 16
Data Sheet
HMC8121
TYPICAL APPLICATION CIRCUIT
A typical application circuit for the HMC8121 is provided in
Figure 38. For typical operation, drive the attenuator control
pads from a single control voltage. It is important to bypass all
the supply connections and attenuator control pads with
adequate bypassing capacitors. Use single-layer chip capacitors
with very high self-resonant frequency close to the HMC8121
die, bypassing each supply or control pad. Typically, 120 pF chip
capacitors are used, followed by 0.01 µF and 4.7 µF surface-mount
capacitors. Combine supply lines as shown in the application
circuit schematic to minimize external component count and
simplify power supply routing (see Figure 38). Pad 25 and Pad 26
are internally connected. Therefore, use either pad to connect
The HMC8121 uses several amplifier, detector, and attenuator
stages. All stages use depletion mode pHEMT transistors. It is
important to follow the following power-up bias sequence to
ensure transistor damage does not occur.
1. Apply a −5 V bias to the VCTL1 and VCTL2 pads.
2. Apply a −2 V bias to the VGG3 to VGG6 and VGG1/VGG2 pads.
3. Apply 4 V to the VDD1 to VDD6 pads.
4. Adjust VGG1/VGG2 and VGG3 to VGG6 between −2 V and 0 V
to achieve a total amplifier drain current of 265 mA.
After bias is established, adjust the VCTL1 = VCTL2 bias between
−5 V and 0 V to achieve the desired gain.
the external bypass components of VDD1/VDD2
.
To power down the HMC8121, follow the reverse procedure.
For additional guidance on general bias sequencing, see the
MMIC Amplifier Biasing Procedure application note.
1
2
3
4
5
6
RFOUT
1.6kΩ
1.6kΩ
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
120pF
120pF
120pF
120pF
120pF
120pF
120pF
120pF
120pF
120pF
120pF
0.01µF
4.7µF
120pF
0.01µF
4.7µF
0.01µF
4.7µF
0.01µF
4.7µF
0.01µF
4.7µF
0.01µF
4.7µF
0.01µF
4.7µF
V
, V
V
, V
V
DD6
V
/V
V
, V
V
, V
, V
V
, V
CTL1
CTL2
GG3 GG4
GG1 GG2
DD1 DD2
DD3
DD4
DD5
GG5 GG6
V
V
DET
REF
+5V
100kΩ 100kΩ
+5V
1000pF
10kΩ
10kΩ
150Ω
3.5kΩ
+4V
ENV
DET
V
= V
– V
OUT
REF DET
10kΩ
10kΩ
–5V
SUGGESTED CIRCUIT
Figure 38. Typical Application Circuit
Rev. B | Page 13 of 16
HMC8121
Data Sheet
ASSEMBLY DIAGRAM
50Ω
TRANSMISSION
LINE
3 MIL WIDE
GOLD RIBBON
(WEDGE BOND)
3 MIL
NOMINAL
GAP
1
2
3
4
5
6
RFOUT
1.6kΩ
1.6kΩ
3 MIL WIDE
GOLD RIBBON
(WEDGE BOND)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
120pF
0.01µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
V
/V
V
, V
V
, V
V
, V
V
, V
, V
V
, V
V
DD6
GG1 GG2
DD1
DD2
CTL1
CTL2
GG3 GG4
DD3
DD4
DD5
GG5 GG6
Figure 39. Assembly Diagram
Rev. B | Page 14 of 16
Data Sheet
HMC8121
MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS
Attach the die directly to the ground plane eutectically or with
conductive epoxy.
Transients
Suppress instrument and bias supply transients while bias is
applied. To minimize inductive pickup, use shielded signal and
bias cables.
To bring RF to and from the chip, use 50 Ω microstrip trans-
mission lines on 0.127 mm (5 mil) thick alumina thin film
substrates (see Figure 40).
General Handling
Handle the chip on the edges only using a vacuum collet or with
a sharp pair of bent tweezers. Because the surface of the chip
has fragile air bridges, never touch the surface of the chip with a
vacuum collet, tweezers, or fingers.
0.05mm (0.002") THICK GaAs MMIC
RIBBON BOND
0.076mm
(0.003")
MOUNTING
The chip is back metallized and can be die mounted with gold/tin
(AuSn) eutectic preforms or with electrically conductive epoxy.
The mounting surface must be clean and flat.
RF GROUND PLANE
Eutectic Die Attach
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
It is best to use an 80% gold/20% tin preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When
hot 90% nitrogen/10% hydrogen gas is applied, maintain tool tip
temperature at 290°C. Do not expose the chip to a temperature
greater than 320°C for more than 20 sec. No more than 3 sec of
scrubbing is required for attachment.
Figure 40. Routing RF Signals
To minimize bond wire length, place microstrip substrates as
close to the die as possible. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
Epoxy Die Attach
HANDLING PRECAUTIONS
ABLEBOND 84-1LMIT is recommended for die attachment.
Apply a minimum amount of epoxy to the mounting surface so
that a thin epoxy fillet is observed around the perimeter of the
chip after placing it into position. Cure the epoxy per the
schedule provided by the manufacturer.
To avoid permanent damage, adhere to the following
precautions.
Storage
All bare die ship in either waffle or gel-based ESD protective
containers, sealed in an ESD protective bag. After opening the
sealed ESD protective bag, all die must be stored in a dry
nitrogen environment.
WIRE BONDING
RF bonds made with 0.003 in. × 0.0005 in. gold ribbon are recom-
mended for the RF ports. These bonds must be thermosonically
bonded with a force of 40 g to 60 g. DC bonds of 0.001 in.
(0.025 mm) diameter, thermosonically bonded, are recommended.
Create ball bonds with a force of 40 g to 50 g and wedge bonds
with a force of 18 g to 22 g. Create all bonds with a nominal
stage temperature of 150°C. Apply a minimum amount of
ultrasonic energy to achieve reliable bonds. Keep all bonds as
short as possible, less than 12 mil (0.31 mm).
Cleanliness
Handle the chips in a clean environment. Never use liquid
cleaning systems to clean the chip.
Static Sensitivity
Follow ESD precautions to protect against ESD strikes.
Rev. B | Page 15 of 16
HMC8121
Data Sheet
OUTLINE DIMENSIONS
3.599
0.05
0.085
0.125
0.125
0.216
TOP VIEW
(CIRCUIT SIDE)
0.225
1
2
3
4
5
6
0.125
0.125
1.200
1.369
0.682
28 27 26 25 24 23 22 21
20 19 18 17 16 15 14 13 12 11 10
9
8
7
SIDE VIEW
0.073
0.085
0.081
0.30
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15 0.15
0.15
0.15 0.15
0.15
0.15
0.15
0.15
0.15
0.15
Figure 41. 28-Pad Bare Die [CHIP]
(C-28-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC8121
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
28-Pad Bare Die [CHIP]
28-Pad Bare Die [CHIP]
Package Option2
C-28-1
HMC8121-SX
C-28-1
1 The HMC8121-SX is two pairs of the die in a gel pack for the sample orders.
2 This is a waffle pack option; contact Analog Devices, Inc., sales representatives for additional packaging options.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13154-0-4/17(B)
Rev. B | Page 16 of 16
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