HMC8325-SX [ADI]
HMC8325-SX;
| 型号： | HMC8325-SX |
| 厂家： | 
ADI |
| 描述： | HMC8325-SX 射频 微波 |
| 文件： | 总17页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
71 GHz to 86 GHz,
E-Band Low Noise Amplifier
Data Sheet
HMC8325
FEATURES
GENERAL DESCRIPTION
Gain: 21 dB typical
Noise figure: 3.6 dB typical
The HMC8325 is an integrated E-band gallium arsenide (GaAs),
monolithic microwave integrated circuit (MMIC), low noise
amplifier (LNA) chip that operates from 71 GHz to 86 GHz.
The HMC8325 provides 21 dB of gain, 13 dBm of output P1dB,
22 dBm of OIP3, and 17 dBm of PSAT while requiring only 50 mA
from a 3 V power supply. The HMC8325 exhibits excellent linearity
and is optimized for E-band communications and high capacity,
wireless backhaul radio systems. All data is taken with the chip
in a 50 Ω test fixture connected via a 3 mil wide × 0.5 mil thick ×
7 mil long ribbon on each port.
Output power for 1 dB compression: 13 dBm typical
Input third-order intercept at maximum gain: 1 dBm typical
Output third-order intercept at maximum gain: 22 dBm typical
Saturated output power: 17 dBm typical
Input return loss: 15 dB typical
Output return loss: 17 dB typical
Die size: 2.844 mm × 0.999 mm × 0.05 mm
APPLICATIONS
E-band communication systems
High capacity wireless backhauls
Test and measurement
FUNCTIONAL BLOCK DIAGRAM
V
V
V
V
V
V
V
V
D4
G1
D1
G2
D2
G3
D3
G4
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
3
2
1
RF
RF
OUT
IN
HMC8325
Figure 1.
Rev. 0
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Technical Support
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www.analog.com
HMC8325* PRODUCT PAGE QUICK LINKS
Last Content Update: 07/15/2017
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DOCUMENTATION
Data Sheet
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• HMC8325: 71 GHz to 86 GHz, E-Band Low Noise Amplifier
Data Sheet
TECHNICAL SUPPORT
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number.
DESIGN RESOURCES
• HMC8325 Material Declaration
• PCN-PDN Information
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HMC8325
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................6
Theory of Operation ...................................................................... 12
Application Information................................................................ 13
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Interface Schematics..................................................................... 5
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs......................................................................................... 14
Handling Precautions ................................................................ 14
Mounting..................................................................................... 14
Wire Bonding.............................................................................. 14
Assembly Diagram ..................................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
HMC8325
SPECIFICATIONS
TA = 25°C, VDx (VD1 and VD2 to VD3 and VD4) = 3 V, unless otherwise noted.
Table 1.
Parameter
Min
71
Typ
Max
Unit
OPERATING CONDITIONS
Radio Frequency (RF) Range
PERFORMANCE
86
GHz
Gain
19.5
21
0.02
13
17
1
dB
Gain Variation over Temperature
Output Power for 1 dB Compression (P1dB)
dB/°C
dBm
dBm
dBm
dBm
dB
Saturated Output Power (PSAT
)
Input Third-Order Intercept (IIP3) at Maximum Gain1
Output Third-Order Intercept (OIP3) at Maximum Gain1
22
3.6
Noise Figure
Return Loss
4.5
Input
Output
15
17
dB
dB
POWER SUPPLY
Total Drain Current (IDx)2
50
mA
1 Data taken at power output (POUT) = 5 dBm/tone, 1 MHz spacing.
2 Adjust VG1 and VG2 to VG3 and VG4 from −2 V to 0 V to achieve a total drain current (IDx) = 50 mA.
Rev. 0 | Page 3 of 16
HMC8325
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Drain Bias Voltage (VD1 to VD4)
Gate Bias Voltage (VG1 to VG4)
Maximum Junction Temperature (to
Maintain 1 Million Hours Mean Time to
Failure (MTTF))
Storage Temperature Range
Operating Temperature Range
4.5 V
−3 V to 0 V
175°C
Table 3. Thermal Resistance
Package Type
C-22-12
1
θJC
Unit
225
°C/W
−65°C to +150°C
−55°C to +85°C
Class 0 (150 V)
1 Based on ABLEBOND® 84-1LMIT as die attach epoxy.
2 Test Condition: Thermal impedance simulated values are based on
JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51.
ESD Sensitivity, Human Body Model (HBM)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 4 of 16
Data Sheet
HMC8325
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
16
V
GND
18
V
D4
G1
D1
G2
D2
G3
D3
G4
4
5
6
7
8
9
10
11
12
13
14
15
17
19
HMC8325
20 GND
3
2
1
GND
21
22
RF
RF
IN
OUT
GND
GND
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pad No.
Mnemonic
GND
Description
1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22
Ground Connection.
2
RFIN
RF Input. AC couple RFIN and match it to 50 Ω.
Gate Bias Voltage for the Low Noise Amplifier.
Drain Bias Voltage for the Low Noise Amplifier.
RF Output. AC couple RFOUT and match it to 50 Ω.
5, 9, 13, 17
7, 11, 15, 19
21
VG1 to VG4
VD1 to VD4
RFOUT
Die Bottom
GND
Ground. Die bottom must be connected to the RF/dc ground.
INTERFACE SCHEMATICS
GND
V
, V , V , V
D1 D2 D3 D4
Figure 6. VD1 to VD4 Interface Schematic
Figure 3. GND Interface Schematic
RF
RF
IN
OUT
Figure 7. RFOUT Interface Schematic
Figure 4. RFIN Interface Schematic
V
, V , V , V
G1 G2 G3 G4
Figure 5. VG1 to VG4 Interface Schematic
Rev. 0 | Page 5 of 16
HMC8325
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
30
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
0
–5
–10
–15
–20
GAIN
INPUT RETURN LOSS
OUTPUT RETURN LOSS
–30
–25
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 11. Noise Figure vs. Frequency over Temperature,
Figure 8. Gain and Return Loss vs. Frequency, VDx = 3 V, IDx = 57 mA
VDx = 3 V, IDx = 50 mA
20
19
18
17
16
15
14
13
12
11
10
20
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
18
16
14
12
10
8
6
4
2
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Saturated Output Power (PSAT) vs. Frequency over Temperature,
Dx = 3 V, IDx = 50 mA
Figure 9. Output P1dB vs. Frequency over Temperature,
V
VDx = 3 V, IDx = 50 mA
–40
–42
–44
–46
–48
–50
–52
–54
–56
–58
–60
–62
–64
–66
10
8
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
6
4
2
0
–2
–4
–6
–8
–10
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. Reverse Isolation vs. Frequency over Temperature,
Dx = 3 V, IDx = 57 mA
Figure 10. Input Third-Order Intercept (IP3) vs. Frequency over Temperatures,
OUT = 5 dBm/Tone, VDx = 3 V, IDx = 50 mA
V
P
Rev. 0 | Page 6 of 16
Data Sheet
HMC8325
30
30
28
26
24
22
20
18
16
14
12
10
T
T
T
= +85°C
= +25°C
= –55°C
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
A
A
A
28
26
24
22
20
18
16
14
12
10
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Gain vs. Frequency over Temperature,
Figure 17. Gain vs. Frequency over Temperature,
VDx = 3 V, IDx = 57 mA
VDx = 4 V, IDx = 57 mA
30
28
26
24
22
20
18
16
14
12
10
8
30
28
26
24
22
20
18
16
14
12
10
8
I
I
I
I
/I = 1.5mA
I
I
I
I
/I = 15.0mA
I
I
I
I
/I = 1.5mA
I
I
I
I
/I = 15.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 3.0mA
/I = 20.0mA
/I = 3.0mA
/I = 20.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 5.0mA
/I = 25.0mA
/I = 5.0mA
/I = 25.0mA
D3 D4
/I = 30.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 10.0mA
/I = 30.0mA
/I = 10.0mA
D3 D4
D3 D4
D3 D4
6
6
4
4
2
2
0
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Gain vs. Frequency over Drain Current, VDx = 3 V,
Figure 18. Gain vs. Frequency over Drain Current, VDx = 4 V,
VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
30
28
26
24
22
20
18
16
14
12
10
8
–40
–42
–44
–46
–48
–50
–52
–54
–56
–58
–60
–62
–64
–66
–68
–70
I
I
I
I
I
/I = 3.0mA
I
I
I
I
I
/I = 25.0mA
D3 D4
D3 D4
T
T
T
= +85°C
= +25°C
= –55°C
/I = 5.0mA
/I = 30.0mA
D3 D4
A
A
A
D3 D4
/I = 10.0mA
/I = 35.0mA
D3 D4
D3 D4
/I = 15.0mA
/I = 40.0mA
D3 D4
D3 D4
/I = 20.0mA
/I = 44.0mA
D3 D4
D3 D4
6
4
2
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Gain vs. Frequency over Drain Current,
Figure 19. Reverse Isolation vs. Frequency over Temperature,
Dx = 4 V, IDx = 57 mA
VD1 and VD2 = 2 V, VD3 and VD4 = 4 V
V
Rev. 0 | Page 7 of 16
HMC8325
Data Sheet
0
0
–5
–5
–10
–15
–20
–25
–30
–35
–40
–10
–15
–20
–25
–30
–35
–40
T
T
T
= +85°C
= +25°C
= –55°C
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
A
A
A
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. Input Return Loss vs. Frequency over Temperature,
Figure 23. Input Return Loss vs. Frequency over Temperature,
Dx = 4 V, IDx = 57 mA
VDx = 3 V, IDx = 57 mA
V
0
–2
0
–2
T
T
T
= +85°C
= +25°C
= –55°C
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
A
A
A
–4
–4
–6
–6
–8
–8
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. Output Return Loss vs. Frequency over Temperature,
Dx = 3 V, IDx = 57 mA
Figure 24. Output Return Loss vs. Frequency over Temperature,
Dx = 4 V, IDx = 57 mA
V
V
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
I
I
I
I
/I = 1.5mA
I
I
I
I
/I = 15.0mA
D3 D4
D3 D4
T
T
T
= +85°C
= +25°C
= –55°C
/I = 3.0mA
/I = 20.0mA
D3 D4
A
A
A
D3 D4
/I = 5.0mA
/I = 25.0mA
D3 D4
/I = 30.0mA
D3 D4
D3 D4
/I = 10.0mA
D3 D4
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. Noise Figure vs. Frequency over Temperature,
Figure 25. Noise Figure vs. Frequency over Drain Current, VDx = 3 V,
VDx = 4 V, IDx = 50 mA
VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
Rev. 0 | Page 8 of 16
Data Sheet
HMC8325
10
9
8
7
6
5
4
3
2
1
0
10
8
I
I
I
I
I
/I = 3.0mA
I
I
I
I
I
/I = 25.0mA
I
I
I
I
/I = 1.5mA
I
I
I
I
/I = 15.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 5.0mA
/I = 30.0mA
D3 D4
/I = 3.0mA
/I = 20.0mA
D3 D4
D3 D4
D3 D4
/I = 10.0mA
/I = 35.0mA
D3 D4
/I = 5.0mA
/I = 25.0mA
D3 D4
/I = 30.0mA
D3 D4
D3 D4
D3 D4
/I = 15.0mA
/I = 40.0mA
D3 D4
/I = 10.0mA
D3 D4
D3 D4
/I = 20.0mA
/I = 44.0mA
D3 D4
D3 D4
6
4
2
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Noise Figure vs. Frequency over Drain Current, VDx = 4 V,
Figure 29. Noise Figure vs. Frequency over Drain Current,
VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
VD1 and VD2 = 2 V, VD3 and VD4 = 4 V
20
18
16
14
12
10
8
20
19
18
17
16
15
14
13
12
11
10
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
6
4
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
2
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 27. Output P1dB vs. Frequency over Temperature,
Figure 30. Saturated Output Power (PSAT) vs. Frequency over Temperature,
Dx = 4 V, IDx = 50 mA
VDx = 4 V, IDx = 50 mA
V
20
18
16
14
12
10
8
20
19
18
17
16
15
14
13
12
11
10
I
I
I
I
/I = 3.0mA
I
I
I
/I = 20.0mA
I
I
I
I
/I = 3.0mA
I
I
I
/I = 20.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 5.0mA
/I = 25.0mA
/I = 5.0mA
/I = 25.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 10.0mA
/I = 30.0mA
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 15.0mA
/I = 15.0mA
D3 D4
D3 D4
6
4
2
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 28. Output P1dB vs. Frequency over Drain Current, VDx = 3 V,
Figure 31. Saturated Output Power (PSAT) vs. Frequency over Drain Current,
VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
VDx = 3 V, VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
Rev. 0 | Page 9 of 16
HMC8325
Data Sheet
20
18
16
14
12
10
8
20
19
18
17
16
15
14
13
12
11
10
I
I
I
/I = 3.0mA
I
I
I
I
/I = 15.0mA
I
I
I
I
/I = 3.0mA
I
I
I
/I = 20.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 5.0mA
/I = 20.0mA
D3 D4
/I = 5.0mA
/I = 25.0mA
D3 D4
D3 D4
D3 D4
/I = 10.0mA
/I = 25.0mA
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 30.0mA
/I = 15.0mA
D3 D4
D3 D4
6
4
2
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 32. Output P1dB vs. Frequency over Drain Current, VDx = 4 V,
Figure 35. Saturated Output Power (PSAT) vs. Frequency over Drain Current,
VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
VDx = 4 V, VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
20
18
16
14
12
10
8
20
19
18
17
16
15
14
13
12
11
10
I
I
I
I
/I = 5.0mA
I
I
I
I
I
/I = 25.0mA
I
I
I
I
/I = 5.0mA
I
I
I
I
I
/I = 25.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 10.0mA
/I = 30.0mA
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 15.0mA
/I = 35.0mA
/I = 15.0mA
/I = 35.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 20.0mA
/I = 40.0mA
/I = 20.0mA
/I = 40.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 44.0mA
/I = 44.0mA
D3 D4
D3 D4
6
4
2
0
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 33. Output P1dB vs. Frequency over Drain Current,
Figure 36. Saturated Output Power (PSAT) vs. Frequency over Drain Current,
VD1 and VD2 = 2 V, VD3 and VD4 = 4 V
VD1 and VD2 = 2 V, VD3 and VD4 = 4 V
10
8
30
28
26
24
22
20
18
16
14
12
10
T
T
T
= +85°C
= +25°C
= –55°C
T
T
T
= +85°C
= +25°C
= –55°C
A
A
A
A
A
A
6
4
2
0
–2
–4
–6
–8
–10
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 34. Input Third-Order Intercept (IP3) vs. Frequency over Temperature,
Dx = 4 V, IDx = 50 mA
Figure 37. Output Third-Order Intercept (IP3) vs. Frequency over
Temperature, VDx = 4 V, IDx = 50 mA
V
Rev. 0 | Page 10 of 16
Data Sheet
HMC8325
20
18
16
14
12
10
8
30
28
26
24
22
20
18
16
14
12
10
6
4
2
0
–2
–4
–6
–8
–10
I
I
I
I
/I = 3.0mA
I
I
I
/I = 20.0mA
I
I
I
I
/I = 3.0mA
I
I
I
/I = 20.0mA
D3 D4
D3 D4
D3 D4
D3 D4
/I = 5.0mA
/I = 25.0mA
D3 D4
/I = 5.0mA
/I = 25.0mA
D3 D4
D3 D4
D3 D4
/I = 10.0mA
/I = 30.0mA
D3 D4
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
D3 D4
/I = 15.0mA
/I = 15.0mA
D3 D4
D3 D4
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 38. Input Third-Order Intercept (IP3) vs. Frequency over Drain Current,
Figure 41. Output Third-Order Intercept (IP3) vs. Frequency over Drain
Current, VDx = 3 V, VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
VDx = 3 V, VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
20
18
16
14
12
10
8
30
28
26
24
22
20
18
16
14
I
I
I
I
/I = 3.0mA
I
I
I
/I = 20.0mA
D3 D4
D3 D4
/I = 5.0mA
/I = 25.0mA
D3 D4
D3 D4
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
/I = 15.0mA
D3 D4
6
4
2
0
–2
–4
–6
–8
–10
I
I
I
I
/I = 3.0mA
I
I
I
/I = 20.0mA
D3 D4
D3 D4
/I = 5.0mA
/I = 25.0mA
D3 D4
D3 D4
12
10
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
/I = 15.0mA
D3 D4
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 39. Input Third-Order Intercept (IP3) vs. Frequency over Drain Current,
Dx = 4 V, VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
Figure 42. Output Third-Order Intercept (IP3) vs. Frequency over Drain
Current, VDx = 4 V, VG1 and VG2 Fixed at 20 mA, VG3 and VG4 Swept
V
20
18
16
14
12
10
8
30
28
26
24
22
20
18
16
I
I
I
I
/I = 5.0mA
I
I
I
I
I
/I = 25.0mA
D3 D4
D3 D4
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
/I = 15.0mA
/I = 35.0mA
D3 D4
D3 D4
/I = 20.0mA
/I = 40.0mA
D3 D4
D3 D4
/I = 44.0mA
D3 D4
6
4
2
0
–2
–4
–6
–8
–10
I
I
I
I
/I = 5.0mA
I
I
I
I
I
/I = 25.0mA
D3 D4
D3 D4
14
12
10
/I = 10.0mA
/I = 30.0mA
D3 D4
D3 D4
/I = 15.0mA
/I = 35.0mA
D3 D4
D3 D4
/I = 20.0mA
/I = 40.0mA
D3 D4
D3 D4
/I = 44.0mA
D3 D4
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 40. Input Third-Order Intercept (IP3) vs. Frequency over Drain Current,
D1 and VD2 = 2 V, VD3 and VD4 = 4 V
Figure 43. Output Third-Order Intercept (IP3) vs. Frequency over Drain
Current, VD1 and VD2 = 2 V, VD3 and VD4 = 4 V
V
Rev. 0 | Page 11 of 16
HMC8325
Data Sheet
THEORY OF OPERATION
The circuit architecture of the HMC8325 low noise amplifier is
shown in Figure 44. The HMC8325 uses four cascaded gain
stages to form an amplifier with a combined gain of 21 dB
(typical), a noise figure of 3.6 dB (typical), and 1 dBm (typical)
input IP3 across the 71 GHz to 86 GHz frequency range. Stage 1
and Stage 2 can be biased separately from Stage 3 and Stage 4.
Operating at VD1 = VD2 = 2 V and VD3 = VD4 = 4 V improves
gain and noise figure compared to VD1 = VD2 = VD3 = VD4 = 4 V.
The input IP3 is slightly lower for the VD1 = VD2 = 2 V and VD3
D4 = 4 V case. A compromise bias voltage between the gain
noise figure vs. the input IP3 is VD1 = VD2 = VD3 = VD4 = 3 V.
Gain control can be achieved by down biasing Stage 3 and
Stage 4. By lowering the drain current of ID3 and ID4, a 12 dB
reduction in gain can be achieved with a small degradation in
=
V
the noise figure. Refer to Figure 45 for further details on biasing
arrangements for the different stages.
RF
RF
IN
OUT
Figure 44. Circuit Architecture
Rev. 0 | Page 12 of 16
Data Sheet
HMC8325
APPLICATION INFORMATION
The typical application circuit shown in Figure 45 shows the
HMC8325 chip with all of its required bypassing components.
Bypass all supply connections with adequate bypassing capacitors
is recommended. Use single-layer chip capacitors with a very
high, self-resonant frequency close to the HMC8325 chip.
Typically, 120 pF chip capacitors are recommended, followed by
0.01 µF and 4.7 µF surface-mount capacitors. Supply lines can be
combined into single drain and single gate bias sources to minimize
external component count and simplify power supply routing.
The HMC8325 uses several amplifier stages. All stages use depletion
mode, pseudomorphic high electron mobility transfer (pHEMT)
transistors. Therefore, follow the following recommended bias
sequence during power-up of the devices to ensure that damage
does not occur.
1. Apply −2 V bias to VGx (VG1 and VG2 to VG3 and VG4).
2. Apply 3 V bias to VDx (VD1 and VD2 to VD3 and VD4).
3. Adjust VG1/VG2 to VG3/VG4 between −2 V and 0 V to
achieve a total drain current (IDx) of 50 mA.
The recommended single power supply source is 3 V (VDx
VD1/VD2 and VD3/VD4 = 3 V). Alternatively, 2 V and 4 V power
supply sources can be used for VD1/VD2 and VD3/VD4, respectively.
=
4. Apply the RF input signal.
The recommended bias sequence during power-down of the
device is as follows:
1. Turn off the RF input signal.
2. Turn off the VDx (VD1 and VD2 to VD3 and VD4) voltage
supply or set it to 0 V.
3. Turn off the VGx (VG1 and VG2 to VG3 and VG4) voltage
supply.
V
V
/V
V
/V
D1 D2
G3 G4
+
+
0.01µF
0.01µF
0.01µF
120pF
4.7µF
120pF
120pF
4.7µF
4.7µF
+
/V
V
/V
G1 G2
D3 D4
+
0.01µF
120pF
4.7µF
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
3
2
1
RF
RF
OUT
IN
22
Figure 45. Typical Application Circuit (Two Power Supply Source Configuration)
Rev. 0 | Page 13 of 16
HMC8325
Data Sheet
Transients
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GAAS MMICS
Suppress instrument and bias supply transients while bias is
applied. To minimize inductive pickup, use shielded signal and
bias cables.
Attach the die directly to the ground plane eutectically or with
conductive epoxy.
General Handling
To bring RF to and from the chip, use 50 Ω microstrip transmission
lines on 0.127 mm (0.005”) thick, alumina thin film substrates
(see Figure 46).
Handle the chip on the edges only using a vacuum collet or with
a sharp pair of bent tweezers. Because the surface of the chip
has fragile air bridges, never touch the surface of the chip with
a vacuum collet, tweezers, or fingers.
0.05mm (0.002") THICK GaAs MMIC
MOUNTING
RIBBON BOND
The chip is back metallized and can be die mounted with gold/tin
(AuSn) eutectic preforms or with electrically conductive epoxy.
The mounting surface must be clean and flat.
0.076mm
(0.003")
Eutectic Die Attach
RF GROUND PLANE
It is best to use an 80% gold/20% tin preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When
hot 90% nitrogen/10% hydrogen gas is applied, maintain a tool
tip temperature of 290°C. Do not expose the chip to a temperature
greater than 320°C for more than 20 sec. No more than 3 sec of
scrubbing is required for attachment.
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
Figure 46. Routing RF Signals
To minimize bond wire length, place microstrip substrates as
close to the die as possible. Typical die to substrate spacing is
0.076 mm to 0.152 mm (0.003” to 0.006”).
Epoxy Die Attach
The ABLEBOND 84-1LMIT is recommended for die attachment.
Apply a minimum amount of epoxy to the mounting surface so
that a thin epoxy fillet is observed around the perimeter of the
chip after placing it into position. Cure the epoxy per the schedule
provided by the manufacturer.
HANDLING PRECAUTIONS
To avoid permanent damage, adhere to the following storage,
cleanliness, static sensitivity, transient, and general handling
precautions.
Storage
WIRE BONDING
All bare die ship in either waffle or gel-based ESD protective
containers, sealed in an ESD protective bag. After opening the
sealed ESD protective bag, all die must be stored in a dry nitrogen
environment.
RF bonds made with 3 mil (0.0762 mm) × 0.5 mil (0.0127 mm)
gold ribbon are recommended. Thermosonically bond these
bonds with a force of 40 grams to 60 grams. DC bonds of 1 mil
(0.0254 mm) diameter, thermosonically bonded, are recommended.
Create ball bonds with a force of 40 grams to 50 grams and
wedge bonds with a force of 18 grams to 22 grams. Create all
bonds with a nominal stage temperature of 150°C. Apply a
minimum amount of ultrasonic energy to achieve reliable bonds.
Keep all bonds as short as possible, less than 12 mil (0.31 mm).
Cleanliness
Handle the chips in a clean environment. Never use liquid
cleaning systems to clean the chip.
Static Sensitivity
Follow ESD precautions to protect against ESD strikes.
Rev. 0 | Page 14 of 16
Data Sheet
HMC8325
ASSEMBLY DIAGRAM
V
TO V
V
TO V
V
TO V
V
TO V
G1
G2
D1
D2
G3
G4
D3 D4
0.01µF
120pF
0.5mil THICK
7.0mil LONG
3mil
NOMINAL GAP
GOLD RIBBON
(WEDGE BOND)
50Ω
TRANSMISSION LINE
Figure 47. Assembly Diagram
Rev. 0 | Page 15 of 16
HMC8325
Data Sheet
OUTLINE DIMENSIONS
2.844
0.150
0.05
0.115
0.150
0.150
0.150
0.150
0.150
0.150
AIRBRIDGE
0.150
0.150
0.150
0.150
0.150
0.150
0.150
0.150 0.135
0.148
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0.466
0.999
20
21
22
3
2
1
0.130
0.130
0.130
0.130
0.179
0.196
K7801
ADI2015
0.215
SIDE VIEW
TOP VIEW
(CIRCUIT SIDE)
0.095
0.133
2.655
Figure 48. 22-Pad Bare Die [CHIP]
(C-22-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
22-Pad Bare Die [CHIP]
22-Pad Bare Die [CHIP]
Package Option2
C-22-1
HMC8325
HMC8325-SX
C-22-1
1 The HMC8325-SX is two pairs of the die in a gel pack for the sample orders.
2 This is a waffle pack option; contact Analog Devices, Inc., for additional packaging options.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14692-0-2/17(0)
Rev. 0 | Page 16 of 16
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