HMC8342LS6 [ADI]
GaAs MMIC Ã2 Active Frequency Multiplier, 22 GHz to 42 GHz Output;
| 型号： | HMC8342LS6 |
| 厂家： | 
ADI |
| 描述： | GaAs MMIC Ã2 Active Frequency Multiplier, 22 GHz to 42 GHz Output |
| 文件： | 总11页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GaAs MMIC ×2 Active Frequency
Multiplier, 22 GHz to 42 GHz Output
Data Sheet
HMC8342
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High output power: 15 dBm (typical) at RFIN = 16 GHz
Low input power drive: 5 dBm (typical)
Fundamental RF input isolation at RF output: −23 dBc at
RFOUT = 30 GHz
16-terminal, 6 mm × 6 mm LCC_HS package, 36 mm2
16
15
14
13
12
V
V
V
1
2
3
11
10
9
V
GG2
DD3
DD2
DD1
APPLICATIONS
NIC
Clock generation
Point to point and very small aperture terminal (VSAT)
radios
Test instrumentation
Military and space
HMC8342
×2
6
V
GG1
4
5
7
8
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The HMC8342 is a gallium arsenide (GaAs), monolithic
microware integrated circuit (MMIC), ×2 active broadband
frequency multiplier. When driven by a 5 dBm signal, the
multiplier provides 15 dBm typical output power. The output
frequency range is from 22 GHz to 42 GHz, and the input
fundamental and third harmonic isolations measured at the
output are −23 dBc and −20 dBc, respectively, at an output
frequency of 30 GHz. The HMC8342 is ideal for use in LO
multiplier chains for point to point and VSAT radios, resulting
in a reduced parts count vs. traditional design approaches.
Table 1. Related Devices
Device No. Description
HMC598
×2 active frequency multiplier, 22 GHz to 46 GHz
output, bare die
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC8342
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
ESD Caution ..................................................................................4
Pin Configuration and Function Descriptions .............................5
Interface Schematics .....................................................................5
Typical Performance Characteristics .............................................6
Theory of Operation .........................................................................9
Applications Information ............................................................. 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 4
Thermal Resistance...................................................................... 4
Electrostatic Discharge (ESD) Ratings...................................... 4
REVISION HISTORY
6/2021—Revision A: Initial Version
Rev. A | Page 2 of 11
Data Sheet
HMC8342
SPECIFICATIONS
VDDx = VDD1 = VDD2 = VDD3 = 5 V, VGG1 = −1.25 V, VGG2 = −0.8 V, GND = 0 V, dBm referred to 50 Ω, 5 dBm drive level, TA = TMAX to TMIN
,
unless otherwise noted.
Table 2.
Parameter
FREQUENCY RANGE
Input
Min Typ
Max Unit
Test Conditions/Comments
11
22
21
42
GHz
GHz
dBm
dBm
dBm
Output
OUTPUT POWER
4
10
2
14
15
10
RFIN = 11 GHz
RFIN = 16 GHz
RFIN = 21 GHz
ISOLATION
RFOUT = 30 GHz
Fundamental Input Frequency Isolation
Input Frequency Third Harmonic Isolation
−23
−20
dBc
dBc
With respect to output level, measured at RF output
With respect to output level, measured at RF output
RETURN LOSS
Input
Output
−10
−13
dB
dB
SUPPLY CURRENT
VDD1 Current (IDD1
VDD2 Current (IDD2
VDD3 Current (IDD3
)
)
)
17
55
97
−4.5
−2.5
mA
mA
mA
µA
VGG1 Current (IGG1
)
)
VGG2 Current (IGG2
µA
RESIDUAL PHASE NOISE
100 kHz Offset
−138
dBc/Hz RFIN = 12 GHz
Rev. A | Page 3 of 11
HMC8342
Data Sheet
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Table 3.
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Parameter
Rating
RF Input (VDDx = 5 V)
Supply Voltage (VDD1 = VDD2 = VDD3
Channel Temperature
Nominal Channel Temperature (T = 85°C)
Storage Temperature Range
10 dBm
6 V dc
175°C
175°C
−65°C to +150°C
−40°C to +85°C
)
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
ESD Ratings for HMC8342
Operating Temperature Range
Table 5. HMC8342, 16-Terminal LCC_HS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD Model
Withstand Threshold (V)
Class
0B
C0B
HBM
CDM
125
125
ESD CAUTION
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 4. Thermal Resistance
Package Type1
θJA
θJC
Unit
EH-16-1
41.9
17.1
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P test board.
Refer to JEDEC standard JESD51 for additional information.
Rev. A | Page 4 of 11
Data Sheet
HMC8342
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
15
14
13
12
V
V
V
1
2
3
11
10
9
V
GG2
DD3
DD2
DD1
HMC8342
NIC
V
GG1
4
5
6
7
8
NOTES
1. EXPOSED PAD. THE EXPOSED PAD OR GROUND PADDLE
ON THE BACKSIDE OF THE PACKAGE MUST BE TIED TO
RF OR DC GROUND FOR ELECTRICAL, MECHANICAL,
AND THERMAL REASONS.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
Power Supply Voltage. 5 V 5%. Place three parallel capacitors as close as possible to each of the VDD1
DD2, and VDD3 pins: 4.7 μF, 10 nF, and 100 pF.
1 to 3
VDD3, VDD2, VDD1
,
V
4, 8, 10, 12, 16 NIC
Not Internally Connected. These pins can be connected to RF or dc ground without affecting the
performance.
5, 7, 13, 15
GND
Ground.
6
RFIN
RF Input. The RFIN pin is ac-coupled and matched to 50 Ω.
9, 11
VGG1, VGG2
Gate Control for Active Multiplier. Place three parallel capacitors as close as possible to each of the VGG1
and VGG2 pins: 4.7 μF, 10 nF, and 100 pF. VGG1 (−1.25 V 5%) and VGG2 (−0.8 V 5%) must be applied
before application of VDD1, VDD2, and VDD3. See the Applications Information section for more information.
14
RFOUT
EP
RF Output. The RFOUT pin is ac-coupled and matched to 50 Ω.
Exposed Pad. The exposed pad or ground paddle on the backside of the package must be tied to RF or
dc ground for electrical, mechanical, and thermal reasons.
INTERFACE SCHEMATICS
GND
RFIN
Figure 3. GND Interface Schematic
Figure 6. RFIN Interface Schematic
GND
V
,
GG1
V
GG2
Figure 4. EP Interface Schematic
Figure 7. VGGx Interface Schematic
V
, V
, V
DD1 DD2 DD3
RFOUT
Figure 8. RFOUT Interface Schematic
Figure 5. VDDx Interface Schematic
Rev. A | Page 5 of 11
HMC8342
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
22
20
18
16
14
12
10
8
–40°C
20
18
16
14
12
10
8
+25°C
+85°C
6
6
4
4
0dBm
3dBm
5dBm
8dBm
10dBm
2
2
0
0
20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
Figure 9. Output Power vs. Frequency at Various Temperatures,
5 dBm Drive Level
Figure 12. Output Power vs. Frequency at Various Drive Levels
20
20
4.5V
5.0V
–40°C
+25°C
18
+85°C
10
5.5V
16
0
–10
–20
–30
–40
–50
14
12
10
8
6
4
2
0
–60
20 22 24 26 28 30 32 34 36 38 40 42 44
INPUT FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Output Power vs. Frequency at Various Supply Voltages,
5 dBm Drive Level
Figure 13. Fundamental Input Harmonic Isolation vs. Input Frequency at
Various Temperatures, 5 dBm Drive Level
0
22
20
18
16
14
12
10
8
–40°C
–10
–20
–30
–40
–50
–60
–70
+25°C
+85°C
6
4
2
0
–40°C, 22GHz
–40°C, 32GHz
–40°C, 42GHz
+25°C, 22GHz
+25°C, 32GHz
+25°C, 42GHz
+85°C, 22GHz
+85°C, 32GHz
+85°C, 42GHz
–2
–4
–6
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
INPUT FREQUENCY (GHz)
0
1
2
3
4
5
6
7
8
9
10
INPUT POWER (dBm)
Figure 14. Output Power vs. Input Power, 5 dBm Drive Level
Figure 11. Third Input Harmonic Isolation vs. Input Frequency at Various
Temperatures, 5 dBm Drive Level
Rev. A | Page 6 of 11
Data Sheet
HMC8342
0
25
23
21
19
17
15
13
11
9
–40°C
+25°C
+85°C
–5
–10
–15
–20
–25
–30
–35
–40
–40°C
+25°C
+85°C
7
5
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 40.0 42.5 45.0 47.5 50.0
202122 2324252627282930 313233343536373839 4041424344
OUTPUT FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Input Return Loss vs. Frequency at Various Temperatures
Figure 18. Supply Current (IDD1) vs. Output Frequency at Various
Temperatures, 5 dBm Drive Level
70
0
–5
–40°C
+25°C
+85°C
65
60
55
50
45
40
35
–10
–15
–20
–25
–30
–40°C
+25°C
+85°C
–35
–40 0
30
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 40.0 42.5 45.0 47.5 50.0
202122232425262728 293031323334353637 383940414243 44
OUTPUT FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Output Return Loss vs. Frequency at Various Temperatures
Figure 19. Supply Current (IDD2) vs. Output Frequency at Various
Temperatures, 5 dBm Drive Level
190
160
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
180
155
150
145
140
135
130
125
120
115
110
105
100
95
170
160
150
140
130
90
85
80
75
70
65
60
55
50
45
40
20212223242526 272829303132333435 3637383940414243 44
OUTPUT FREQUENCY (GHz)
0
1
2
3
4
5
6
7
8
9
10
INPUT POWER (dBm)
Figure 20. Supply Current (IDD3) vs. Output Frequency at Various
Temperatures, 5 dBm Drive Level
Figure 17. Total Supply Current (IDD) vs. Input Power at Various Temperatures
Rev. A | Page 7 of 11
HMC8342
Data Sheet
–50
–60
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–57.63dBc/Hz
34GHz OUTPUT SIGNAL
17GHz INPUT SIGNAL
–70
–86.81dBc/Hz
–90.13dBc/Hz
–87.30dBc/Hz
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–110.81dBc/Hz
–140.29dBc/Hz
–134.3dBc/Hz
–138.2dBc/Hz
–144.2dBc/Hz
–153.0dBc/Hz
1M 10M
–160
100
100
1k
10k
100k
1M
10M
1k
10k
100k
OFFSET FREQUENCY (dBc/Hz)
OFFSET FREQUENCY (dBc/Hz)
Figure 22. Phase Noise with ADF41513 PLL and HMC8362 VCO, 17 GHz Input,
3 dBm Drive Level
Figure 21. Residual Phase Noise, RFIN = 12 GHz, 5 dBm Drive Level
Rev. A | Page 8 of 11
Data Sheet
HMC8342
THEORY OF OPERATION
The HMC8342 is a GaAs, MMIC, ×2 active broadband
frequency multiplier. The output frequency range is from
22 GHz to 42 GHz. The input frequency range is from 11 GHz
to 21 GHz. The HMC8342 can accept input signals with a drive
level between 0 dBm and 10 dBm. The output power of the
HMC8342 is highly dependent on the input drive level. See the
Typical Performance Characteristics section for information on
the expected output power for a particular configuration.
Independent supplies of the same voltage can be used for the
drain (VDDx) pins, or they can alternatively be tied to a single
supply.
The EV1HMC8342LS6 evaluation kit can be used to test and
optimize performance for a given application.
Rev. A | Page 9 of 11
HMC8342
Data Sheet
APPLICATIONS INFORMATION
VGG1 and VGG2 are the gate controls for the HMC8342. To
prevent damage to the device, it is important to follow the
correct bias sequence and to ensure the gate supplies are set
before the drain (VDDx) supplies. −3 V is the lowest voltage that
can be applied to either of the gate supplies without damaging
the device.
A procedure to find the optimum gate bias values with minimal
risk of damage to the device follows:
1. Apply 0 V to the drain supplies, VDDx
.
2. Set both VGG1 and VGG2 to approximately −2 V to control
when the amplifier and multiplier sections can draw
current. When VGG1 and VGG2 are both set to around −2 V,
there is minimal current draw.
From Figure 1, the amplifier circuitry of the HMC8342 is
biased by a single gate voltage, VGG2. The multiplier portion of
the HMC8342 has two drain supplies, VDD2 and VDD3, which are
3. Apply an input signal to RFIN.
4. Apply 5 V to all drain supplies, VDDx
.
both biased by VGG1
.
5. Set VGG2. Increase the voltage until the total current draw
of the VDDx supplies is between 125 mA and 145 mA
(assuming a 5 dBm input signal).
6. Adjust VGG1 so that the RFOUT power and the isolation
are optimized for the application.
7. If the drain current is still low, adjust VGG2 so that there is a
current draw of approximately 160 mA. Recheck the
RFOUT power and isolation.
As per the electrical specifications, VGG1 is typically set to bias at
−1.25 V and VGG2 is typically set to bias at −0.8 V.
To ensure the performance given in the Specifications section is
met, follow this straightforward biasing procedure:
1. Set the VDDx supplies to 0 V.
2. Set VGG2 to −0.8 V and VGG1 to −1.25 V.
3. Set VDDx to 5 V.
It may be necessary to alternate between adjusting VGG1 and
This biasing procedure provides acceptable performance for
many applications. However, because the exact optimum bias
values change based on the RFIN drive level and, to a lesser
extent, frequency, it is possible to optimize output power and
isolation for a specific application by adjusting the VGG2 and
VGG1 settings.
VGG2 to achieve optimum performance.
The current values given in the preceding example assume a
15 GHz input signal at a 5 dBm drive level.
It is recommended to verify these levels for several devices
across the expected temperature range. Then, an active bias
controller can potentially be used to automatically perform the
bias sequencing.
Rev. A | Page 10 of 11
Data Sheet
HMC8342
OUTLINE DIMENSIONS
3.45
1.65
6.20
6.00 SQ
5.80
0.31
0.25
0.19
0.35
0.80
PIN 1
INDICATOR
1.05
12
16
1.00 BSC
11
9
1
3
2.06
2.00
1.94
3.46
3.40
3.34
3.55
SQ
0.56
8
4
0.50
0.44
0.90
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.63
0.57
0.51
1.21
1.15
1.444
1.317
1.190
1.09
4.70
4.65
4.60
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.44 BSC
0.05 MAX
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
Figure 23. 16-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS]
6 mm × 6 mm
(EH-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
EH-16-1
EH-16-1
HMC8342LS6
HMC8342LS6TR
EV1HMC8342LS6
−40°C to +85°C
−40°C to +85°C
16-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS]
16-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS]
Evaluation Board
1 The HMC8342LS6, HMC8342LS6TR, and EV1HMC8342LS6 are RoHS compliant parts.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D25289-6/21(A)
Rev. A | Page 11 of 11
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