HMC974LC3CTR-R5 [ADI]
10 GHz, High Speed Window Comparator;
| 型号： | HMC974LC3CTR-R5 |
| 厂家： | 
ADI |
| 描述： | 10 GHz, High Speed Window Comparator 放大器 |
| 文件： | 总13页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, 10 GHz Window Comparator
HMC974LC3C
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
HMC974LC3C
Propagation delay: 88 ps
Propagation delay at 50 mV overdrive: 20 ps
Minimum detectable pulse width: 60 ps
Differential latch control
RT
WIN
WIT
RB
1
2
3
4
ORB
12
11
10
9
Power dissipation: 240 mW
16-terminal 2.9 mm × 2.9 mm LCC package
WOUTB
URB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Clock and data restoration
V
CCO
Semiconductor test systems
Threshold detection in electronic warfare systems
PACKAGE
BASE
V
EE
Figure 1.
GENERAL DESCRIPTION
The HMC974LC3C is a silicon germanium (SiGe) monolithic,
ultra fast window comparator that features reduced swing
positive emitter-coupled logic (RSPECL) output drivers that are
level latched. Three output ports detect whether an analog input
signal is above, below, or between two reference levels supplied
at the input (see Figure 2).
The outputs are single-ended negative logic. Incorporating two
proven comparators at the input provides good dc and dynamic
matching and reduces the input capacitance. The reduced swing
output stages are designed to directly drive 400 mV into 50 Ω
terminated to a voltage (VTERM = VCCO − 2 V).
HMC974LC3C features high speed latches that can either be
enabled to latch the output data or left in the track mode to
implement a tracking window comparator.
Rev. D
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Technical Support
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HMC974* PRODUCT PAGE QUICK LINKS
Last Content Update: 07/09/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• HMC974 Material Declaration
• PCN-PDN Information
EVALUATION KITS
• HMC974LC3C Evaluation Board
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Data Sheet
DISCUSSIONS
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• HMC974LC3C: High Speed, 10 GHz Window Comparator
Data Sheet
SAMPLE AND BUY
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REFERENCE MATERIALS
Quality Documentation
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• Package/Assembly Qualification Test Report: LC3, LC3B,
LC3C (QTR: 2014-00376 REV: 01)
• Semiconductor Qualification Test Report: BiCMOS-C (QTR:
2013-00241)
DOCUMENT FEEDBACK
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HMC974LC3C
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................6
Interface Schematics .....................................................................7
Typical Performance Characteristics ..............................................8
Theory of Operation .........................................................................9
Power Sequencing .........................................................................9
Applications Information.............................................................. 10
Evaluation Board........................................................................ 10
Outline Dimensions....................................................................... 12
Ordering Guide............................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram ........................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
REVISION HISTORY
6/2017—Rev. C to Rev. D
Changes to Table 1............................................................................ 3
Added Maximum Peak Reflow Temperature Parameter,
Table 2 ................................................................................................ 5
Updated Outline Dimensions....................................................... 12
Changes to Ordering Guide .......................................................... 12
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
3/2017—v04.0616 to Rev. C
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Added Negative Supply (VEE to GND) Parameter, Table 2 ......... 5
Changes to Table 3............................................................................ 5
Added Theory of Operation Section, Power Sequencing Section,
and Table 4......................................................................................... 9
Added Applications Information Section
Changes to Evaluation Board Section and Table 5..................... 10
Updated Outline Dimensions....................................................... 12
Changes to Ordering Guide .......................................................... 12
Rev. D | Page 2 of 12
Data Sheet
HMC974LC3C
SPECIFICATIONS
TA = +25°C, VEE = −3 V, VCCI = +3.3 V, VCCO = +2 V, VTERM = 0 V, VCM = 0 V, VOD1 = 50 mV.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Offset Voltage
Bias Current
−10
−30
−2
±±
+20
+10
+30
+2
mV
μA
V
WIT pin termination open
Measured between the WIN pin voltage and
the RT pin voltage or RB pin voltage
Differential Voltage
Input Impedance
WIN Pin to WIT Pin
RT Pin to WIT Pin
RB Pin to WIT Pin
Common Mode Input Voltage Range
Input Capacitance
50
50
50
Ω
Ω
Ω
V
−1.5
2.2
+1.5
1
WIT to GND
pF
LATCH ENABLE CHARACTERISTICS
LE and LE
Input Low Voltage (VIL)
Input High Voltage (VIH)
LE and LE Impedance
1.6
V
V
kΩ
7.8
If not driven, the device is unlatched
DC OUTPUT CHARACTERISTICS
Output Voltage
High Level, VOH (50 Ω to 0 V)
Low Level, VOL (50 Ω to 0 V)
Output Voltage Swing
1.06
0.73
V
V
WOUTB
URB and ORB
300
320
360
380
±20
±±0
V
V
AC PERFORMANCE
Propagation Delay Dispersion vs. VOD
Rise Time (ORB, WOUTB, URB), tR
Fall Time (ORB, WOUTB, URB), tF
Minimum Detectable Pulse Width
Equivalent Input Bandwidth2
Input to Output Delay, tPD
Latch to Output Delay, tPD
Maximum Input Slew Rate
Noise (Referred to Input)
Random Jitter (rms)
Deterministic Jitter (Peak-to-Peak)
POWER SUPPLIES (INCLUDING LOAD)
Positive Supply Voltage Input Stage (VCCI
Positive Supply Voltage Output Stage (VCCO
Negative Power Supply (VEE)
20
25.3
21.9
60
11
88
83
5
ps
ps
ps
ps
For VOD > 50 mV
20% to 80%
80% to 20%
VCM = 0 V; ±100 mV overdrive voltage
GHz
ps
ps
V/ns
nV/ √(Hz)
ps rms
ps
6
0.2
2
At 5 Gbps with ±100 mV overdrive
At 5 Gbps with ±100 mV overdrive
)
3.135
1.8
−3.15
10
60
21
3.3
3.3
−3.0
15
70
31
3.±65
3.±65
−2.85
20
80
±1
V
V
V
mA
mA
mA
mW
)
Positive Supply Current Input Stage (ICCI)
Positive Supply Current Output Stage (ICCO
Negative Current (IEE)
Power Dissipation (PD)
)
2±0
1 VOD is the input overdrive voltage, for example, VWIN − VRT = VOD or VWIN − VRB = VOD
.
2 Equivalent input bandwidth is calculated with the following formula: BWEQ = 0.22⁄√(TRCOMP2 − TRIN2), where BWEQ is the equivalent bandwidth formula, TRIN is the 20% to
80% transition time of a quasi Gaussian signal applied to the comparator input, and TRCOMP is the effective transition time digitized by the comparator.
Rev. D | Page 3 of 12
HMC974LC3C
Data Sheet
TIMING DIAGRAM
RT
RB
WIN
LATCH
LATCH
LE, LE
TRACK
tPD (LE TO OUT)_ORB
tPD (IN TO OUT)_ORB
ORB
tPD (IN TO OUT)_WOUTB_H TO L
tPD (IN TO OUT)_WOUTB_L TO H
WOUTB
tPD (IN TO OUT)_URB_L TO H
tPD (IN TO OUT)_URB_H TO L
URB
tF
tR
Figure 2. Timing Diagram
Rev. D | Page 4 of 12
Data Sheet
HMC974LC3C
ABSOLUTE MAXIMUM RATINGS
Table 2.
ESD CAUTION
Parameter
Rating
Input Supply Voltage (VCCI to GND)
Output Supply Voltage (VCCO to GND)
Positive Supply Differential (VCCI − VCCO
Negative Supply (VEE to GND)
Input Voltage
−0.5 V to +4 V
−0.5 V to +4 V
−0.5 V to +3 V
−3.3 V to +0.5 V
−2 V to +2 V
−2 V to +2 V
40 mA
)
Differential Input Voltage
Output Current
Junction Temperature
125°C
Continuous Power Dissipation (T = 85°C;
Derate 20.4 mW/°C Above 85°C)
0.816 W
Thermal Resistance (θJC)
Maximum Peak Reflow Temperature1
MSL1 and MSL3
49°C/W
260°C
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity (HBM)
−65°C to +150°C
−40°C to +85°C
Class 1B
1 See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 5 of 12
HMC974LC3C
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RT
WIN
WIT
RB
1
2
3
4
12 ORB
11 WOUTB
10 URB
HMC974LC3C
TOP VIEW
(Not to Scale)
9
V
CCO
PACKAGE
BASE
V
EE
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST
BE CONNECTED TO V
.
EE
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5, 16
6
RT
Termination Resistor for Reference Top.
Analog Input Window.
Common Mode Window for Termination Resistors.
Termination Resistor Return for Reference Bottom.
Positive Supply Voltage Input Stage.
Inverting Latch Enable Input.
WIN
WIT
RB
VCCI
LE
7
LE
VEE
VCCO
URB
WOUTB
Noninverting Latch Enable Input.
Negative Power Supply
Positive Supply Voltage Output Stage.
Underange Output. URB is asserted low when the analog input voltage is below the RB pin voltage.
Window Output. WOUTB is asserted low when the analog input voltage is between the RB pin voltage and the
RT pin voltage.
8, 14
9, 13
10
11
12
15
ORB
RTN
Overrange output. ORB is asserted low when the analog input voltage range is above the RT pin voltage.
ESD Protection Return.
EPAD
Exposed Pad. The exposed pad must be connected to VEE.
Rev. D | Page 6 of 12
Data Sheet
HMC974LC3C
INTERFACE SCHEMATICS
RT
50Ω
WIN
50Ω
WIT
RB
50Ω
Figure 4. Interface Schematic for RT, RB, WIN, and WIT
V
CCI
LE, LE
V
EE
LE
Figure 5. Interface Schematic for LE and
V
CCO
URB,
WOUTB,
ORB
Figure 6. Interface Schematic for URB, WOUTB, and ORB
Rev. D | Page 7 of 12
HMC974LC3C
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
75
1.5
1.3
1.1
0.9
0.7
0.5
V
V
V
= +0.5V
= 0V
ORB, V
OH
CM
CM
CM
WOUT, V
OH
= –0.5V
URB, V
OH
OL
OL
60
45
30
15
0
ORB, V
WOUT, V
URB, V
OL
–15
0
10
20
30
40
50
60
70
80
90 100 110
–45 –32 –19
–6
7
20
33
46
59
72
85
OVERDRIVE VOLTAGE (mV)
TEMPERATURE (°C)
Figure 7. Dispersion vs. Overdrive Voltage
Figure 10. VOL/VOH Levels vs. Temperature
0.62
0.54
0.46
0.38
0.30
80
70
60
50
40
30
20
10
ORB SWING
WOUT SWING
URB SWING
V
V
V
CCI
CCO
EE
–45 –32 –19
–6
7
20
33
46
59
72
85
–45 –32 –19
–6
7
20
33
46
59
72
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Output Voltage Swing vs. Temperature
Figure 11. Power Supply Currents
36
34
32
30
28
26
24
22
20
ORB, RISE
WOUT, RISE
URB, RISE
ORB, FALL
WOUT, FALL
URB, FALL
–45 –32 –19
–6
7
20
33
46
59
72
85
TEMPERATURE (°C)
Figure 9. Output Rise and Fall Time
Rev. D | Page 8 of 12
Data Sheet
HMC974LC3C
THEORY OF OPERATION
The HMC974LC3C is a window comparator where the range of
the window is defined with RT as the top of the voltage window
range and RB as the bottom of the voltage window range. The
comparator has two modes of operation: track mode and latch
mode. While in track mode, the comparator determines three
things:
Table 4. Eye Diagram Details
Parameter
Value
Bit Rate
Pattern Length
Deterministic Jitter (Peak-to-Peak)
Vertical Scale
5 Gbps
215 − 1
2.15 ps
80 mV/div
33.3 ps/div
Time Scale
1. If the signal is below the window voltage value, RT, and
above the window voltage value, RB, represented by the
WOUTB output.
POWER SEQUENCING
2. If the signal is above the window voltage value RT, which is
represented by the ORB output.
3. If the signal is below the window voltage value RB, which is
represented by the URB output.
Use the following supplies sequentially to power up the device:
1. VEE
2.
3.
V
V
CCI and VCCO (if VCCO = VCCI
CCO (if different than ground)
)
A typical 5 Gbps output eye is shown in Figure 12 with specific
details outlined in Table 4.
The power-down sequence is the reverse of the previous
sequence:
1.
2.
V
V
CCO (if different than ground)
CCI and VCCO (if VCCO = VCCI
)
3. VEE
Apply power to the HMC974LC3C before applying the input
signals (WIN and WIT) and remove the input signals (WIN and
WIT) prior to powering it down.
EDGE SAMPLES
TIME (33.3ps/DIV)
Figure 12. Eye Diagram at 5 Gbps
Rev. D | Page 9 of 12
HMC974LC3C
Data Sheet
APPLICATIONS INFORMATION
EVALUATION BOARD
Table 5. Bill of Materials
The HMC974LC3C evaluation printed circuit board (PCB)
must use RF circuit design techniques. Signal lines must have
50 Ω impedance while the package ground leads must connect
directly to the ground plane of the PCB. The exposed metal
package base must connect to VEE. Ensure the top and bottom
ground planes connect together with via holes. The evaluation
PCB shown in Figure 13 is available from Analog Devices, Inc.,
upon request.
Reference Designator
Description
J1
J2 to J7
J8
JP1, JP2
C1 to C3, C5, C6, C8 to C10,
C15
C4, C7, C11
C12 to C14
TP1 to TP4
U1
Eight-position vertical header
K connector, SRI
Terminal strip, single row, 3-pin
Two position vertical header
100 pF capacitor, 0402
330 pF capacitor, 0402
4.7 μF tantalum capacitor
DC pin
Figure 14 shows the EVAL-HMC974LC3C schematic. Figure 15
shows the typical application circuit.
HMC974LC3C window comparator
PCB
EVAL-HMC974LC3C evaluation
board, circuit board material is
either Rogers 4350 or Arlon 25FR
Figure 13. Evaluation Printed Circuit Board
Rev. D | Page 10 of 12
Data Sheet
HMC974LC3C
J1
V
EE
TP4
C7
C4
C12
C6
330pF
4.7µF
100pF
J1
J1
V
V
CCO
CCI
C2
100pF
C11
330pF
C14
4.7µF
C13
4.7µF
C5
100pF
330pF
TP1
RT
J3
JP1
C8
1
2
3
4
12
ORB
100pF
J4
WOUTB
J2-WIN
11
10
9
TP2-WIT
JP2
JP3
J5
URB
C1
100pF
TP3
RB
J1
CCO
V
C9
100pF
C3
100pF
J8
GND
PACKAGE
BASE
J1
V
V
EE
CCI
V
EE
C10
100pF
J1
EE
V
J6
LE
C15
100pF
J7
LE
1
2
3
4
5
6
7
8
V
SLUG
EE
J1
JP8
V
GND
V
V
CC0
CCI
EE
Figure 14. Evaluation Board Schematic
V
= +3.3V
V
= +2.0V
CCO
CCI
OSCILLOSCOPE INPUT
ORB,
WOUTB,
50Ω
URB
V
CM_OUT
~0.9V
50Ω
HMC974 10GHz
WINDOW COMPARATOR
GND
V
= –3.0V
EE
Figure 15. Typical Application Circuit
Rev. D | Page 11 of 12
HMC974LC3C
Data Sheet
OUTLINE DIMENSIONS
3.05
2.90 SQ
2.75
0.36
0.30
0.24
PIN 1
0.08
BSC
INDICATOR
PIN 1
1.60
13
16
1
12
0.50
BSC
EXPOSED
PAD
1.50 SQ
1.40
9
4
8
5
0.32
BSC
BOTTOM VIEW
TOP VIEW
SIDE VIEW
1.50
REF
1.00
0.90
0.80
2.10 BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
SECTION OF THIS DATA SHEET.
Figure 16. 16-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC974LC3C
Temperature Range
MSL Rating2
Package Description3
Package Option
Branding
H974
−40°C to +85°C
MSL3
16-Terminal LCC
E-16-1
E-16-1
E-16-1
XXXX
H974
HMC974LC3CTR
−40°C to +85°C
−40°C to +85°C
MSL3
MSL3
16-Terminal LCC
XXXX
H974
HMC974LC3CTR-R5
16-Terminal LCC
XXXX
129538-HMC974LC3C
HMC974LC3C Evaluation Board
1 The HMC974LC3C, the HMC974LC3CTR, and the HMC974LC3CTR-R5 are RoHS Compliant Parts.
2 See the Absolute Maximum Ratings section.
3 Alumina and white package body material with a gold over nickel lead finish.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14863-0-6/17(D)
Rev. D | Page 12 of 12
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