LT3950JMSE [ADI]
60V, 1.5A LED Driver with Internal Exponential Scale Dimming;
| 型号： | LT3950JMSE |
| 厂家： | 
ADI |
| 描述： | 60V, 1.5A LED Driver with Internal Exponential Scale Dimming |
| 文件： | 总26页 (文件大小：2500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3950
60V, 1.5A LED Driver with Internal
Exponential Scale Dimming
FEATURES
DESCRIPTION
The LT®3950 is a multitopology DC/DC converter designed
specifically to drive high current LEDs. It contains a 1.5A,
60V DMOS switch and supports an external PWM dim-
ming PMOS. The LT3950 has an internal PWM generator
for dimming that maps an analog control signal to an
exponential scale used to define PWM dimming duty ratio.
Using an exponential scale to define duty ratio preserves
dimming resolution across a wide range of LED current.
In addition to operating as a constant current source, the
LT3950 also provides output voltage regulation. This can
be used to prevent damage to the part in case of open LED
events. A programmable switching frequency offers flex-
ibility in design for higher efficiency or reduced compo-
nent size. Enabling spread spectrum frequency modula-
tion reduces EMI. The switching frequency can also easily
be synchronized by driving the SYNC/SPRD pin with an
external clock. LED current is programmed with a single
external sense resistor and can be adjusted from zero to
full-scale by an analog signal at the CTRL pin.
n
Operates in Boost, SEPIC, Buck Mode and Buck-
Boost Mode
128:1 Internal Exponential Scale PWM Dimming
Wide Input Voltage Range (3V to 60V)
1.5A, 60V Internal Switch
20000:1 External PWM Dimming at 100Hz
2% LED Current and Output Voltage Regulation
PMOS Switch Driver for PWM Dimming
LED Short/Open Protection and Indication
Constant Voltage and Constant Current Regulation
Adjustable 300kHz to 2MHz Switching Frequency
Adjustable 100Hz to 1kHz PWM Generator Frequency
Internal Spread Spectrum Frequency Modulation
Easy Synchronization to External Clock
n
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Programmable V UVLO with Hysteresis
Available in 16-Lead MSOP Package
IN
APPLICATIONS
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Display Backlighting
Automotive and Avionic Lighting
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 7199560, 7321203, 7746300, 8116045. Patents pending.
n
TYPICAL APPLICATION
10W LED Driver for Automotive, 2MHz, 90% Efficient
Efficiency and Power Loss with
and without PWM Dimming
V
10µH
1Ω
IN
3V TO16V DC
TRANSIENT
TO 48V
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ.000
ꢀ.ꢁꢂ0
ꢀ.ꢁ00
ꢀ.ꢀꢁ0
ꢀ.000
ꢀ.ꢁꢂ0
ꢀ.ꢁ00
ꢀ.ꢁꢂ0
ꢀ.000
0.ꢀꢁ0
0.ꢀ00
2.2µF
2.2µF
V
SW
ISP
ISN
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ ꢆ00ꢇ ꢈꢄ
IN
EN/UVLO
1M
100k
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ ꢆꢀꢁꢁ.ꢇ ꢈꢉ
ꢊ0ꢋ ꢌꢍꢎ ꢏꢂꢎꢎꢂꢄꢐ
FAULT
FAULT
FB
10W
LED
INTV
CC
24.9k
LT3950
POWER
(DERATED
BELOW
ꢀ
ꢀ0ꢁ ꢂꢃꢄ ꢅꢆꢄꢄꢆꢇꢈ
ꢀꢁꢂꢂꢃ ꢄꢅꢅ.
1µF
CTRL
PWMTG
VC
V
= 7V)
IN
267k
ꢀ
ꢀ00ꢁ ꢂꢃ
ꢀꢁꢂꢂ
PWM
39k
220pF
SYNC/SPRD RP
RT
GND
100k
300Hz
182k
2MHz
45.3k
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀꢁꢂ
ꢀ
ꢀꢁ
3950 TA01a
ꢀꢁꢂ0 ꢃꢄ0ꢅꢆ
Rev. 0
1
Document Feedback
For more information www.analog.com
LT3950
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
V , SW, ISP, ISN, EN/UVLO, FAULT ..........................62V
IN
ꢐꢛꢊ ꢎꢈꢙꢕ
ꢀ
ꢊꢕꢖꢐꢘ
ꢉꢕ
V
– V ..................................................................2V
ꢈꢉꢊ
ꢀꢅ
ꢀꢄ
ꢀꢃ
ꢀꢂ
ISP
ISN
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈꢉꢋ
ꢌꢍ
INTV , RT, PWMTG.......................................... (Note 2)
ꢉꢕ
CC
ꢀꢆ
ꢘꢋꢔ
ꢎꢏ
ꢏꢐRꢑ
ꢎ
ꢈꢋ
VC, RP.................................................. INTV + 200mV
ꢀꢁ ꢙꢋꢓꢚꢎꢑꢛ
CC
ꢉꢒꢋꢏꢓꢉꢊRꢔ
ꢊꢕꢖ
ꢀꢀ ꢈꢋꢐꢎ
ꢏꢏ
ꢀ0 FAULT
ꢗ
Rꢐ
SYNC/SPRD, CTRL, PWM, FB .................................5.5V
Rꢊ
Operating Junction Temperature (Notes 3, 5)
ꢖꢉꢙ ꢊꢜꢏꢝꢜꢘꢙ
ꢀꢅꢞꢑꢙꢜꢔ ꢊꢑꢜꢉꢐꢈꢏ ꢖꢉꢛꢊ
LT3950E ............................................ –40°C to 125°C
LT3950J............................................. –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
θ
ꢠ ꢃ0ꢡꢏꢓꢕ
ꢟꢜ
ꢙꢢꢊꢛꢉꢙꢔ ꢊꢜꢔ ꢣꢊꢈꢋ ꢀꢆꢤ ꢈꢉ ꢘꢋꢔꢥ ꢖꢚꢉꢐ ꢍꢙ ꢉꢛꢑꢔꢙRꢙꢔ ꢐꢛ ꢊꢏꢍ
ORDER INFORMATION
LEAD FREE FINISH
LT3950EMSE#PBF
LT3950JMSE#PBF
TAPE AND REEL
PART MARKING*
3950
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3950EMSE#TRPBF
LT3950JMSE#TRPBF
16-Lead Plastic MSOP
16-Lead Plastic MSOP
–40°C to 125°C
–40°C to 150°C
3950
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
For more information www.analog.com
LT3950
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VIN = EN/UVLO = 12V, FAULT = 100kΩ to 12V,
ISP = ISN = 48V, SYNC/SPRD = 0V, CTRL = 1.5V, PWM = 3V, INTVCC = 1μF to GND, RT = 45.3kΩ to GND, RP = 100kΩ to GND, FB = 1V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
Operating Supply Range
3
60
Input (V ) Quiescent Current
V
FB
= 1.25V, Not Switching
1.8
mA
IN
Input (V ) Shutdown Current
EN/UVLO = 0V
EN/UVLO = 0.9V, CTRL = 0V
0
130
1
200
µA
µA
IN
l
EN/UVLO Shutdown Threshold (Falling)
EN/UVLO Rising Hysteresis
EN/UVLO Input Low Voltage
EN/UVLO Pin Current (Device Off)
EN/UVLO Pin Current (Device On)
Internal LDO Regulator
1.15
1.25
32
1.35
V
mV
V
EN/UVLO Rising
I
< 1µA
0.4
VIN
EN/UVLO = 1.2V
EN/UVLO = 1.35V
2
0
µA
µA
l
Internal Regulator Voltage
Line Regulation
Not Switching, 1mA External Load
2.94
20
4
3
3.06
V
%/V
Not Switching, 3.3V < V < 60V
0.025
0.05
IN
Load Regulation
Not Switching, 0.1mA < I
<10mA
%/mA
mA
LOAD
Max. Output Current
Not Switching, INTV = 2.8V
CC
Dropout Voltage
Not Switching, INTV Droop 1%, I
= 10mA
350
mV
CC
LOAD
LED Current Regulation (Note 4)
ISP Common Mode Voltage Range
l
60
V
l
l
l
Current Sense Threshold (V – V
)
ISN
CTRL = 1.5V (100%)
CTRL = 0.7V (50%)
CTRL = 0.3V (10%)
248
121
20
250
125
25
255
129
30
mV
mV
mV
ISP
Current Sense Threshold (V – V ) at GND
ISP = 0V
85
100
35
mV
mV
mV
nA
ISP
ISN
l
CTRL OFF Threshold (Falling)
85
125
CTRL OFF Hysteresis
CTRL Pin Current
–100
100
0.1
ISP, ISN Pin Current (Combined)
CTRL = 1.5V (Full Scale)
CTRL = 0V (Stopped)
450
5
µA
µA
Error Amp Transconductance
Error Amp Output Resistance
LED Voltage Regulation (Note 4)
60
20
µS
MΩ
FB Regulation Threshold (V
)
FB
1.188
1.176
1.2
1.2
1.212
1.224
V
V
l
FB Pin Current
Current Out of Pin
20
60
100
nA
V
ISP Voltage Regulation Threshold
FB Amplifier Transconductance
FB Amplifier Output Resistance
Oscillator
500
20
µS
MΩ
l
l
Programmed Switching Frequency (f
)
SW
RT = 45.3k SYNC/SPRD = 0V
RT = 402k SYNC/SPRD = 0V
1880
276
2000
300
2120
324
kHz
kHz
Spread Spectrum Modulation Depth
Minimum Off Time
SYNC/SPRD = 3V
25
55
45
%
ns
ns
l
35
75
Minimum On Time
Rev. 0
3
For more information www.analog.com
LT3950
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VIN = EN/UVLO = 12V, FAULT = 100kΩ to 12V,
ISP = ISN = 48V, SYNC/SPRD = 0V, CTRL = 1.5V, PWM = 3V, INTVCC = 1μF to GND, RT = 45.3kΩ to GND, RP = 100kΩ to GND, FB = 1V.
PARAMETER
CONDITIONS
MIN
TYP
0.85
50
MAX
UNITS
V
SYNC/SPRD Threshold (Rising)
SYNC/SPRD Hysteresis
SYNC/SPRD Internal Pull-Down Resistance
Minimum SYNC Pulse Width
Power Switch
mV
kΩ
ns
100
25
R
I
= 500mA
SW
200
mΩ
A
DS(ON)
l
Switch Current Limit
Switch Leakage Current
External PMOS Driver
1.5
6
1.65
1.8
3
V
= 60V, EN/UVLO = 0V
µA
SW
PWMTG ON (V – V
) Voltage
PWMTG
7.5
0
9
V
V
ISP
PWMTG OFF (V – V
) Voltage
PWMTG
0.3
ISP
Turn-on Time
Turn-off Time
C
C
= 470pF
= 470pF
100
100
ns
ns
LOAD
LOAD
Fault Detection and Reporting
LED Open Threshold
V
– V = 0
V
V
V
FB
V
V
ISP
ISN
FB
FB
– 37mV – 23mV – 9mV
FB Overvoltage Threshold
V
FB
V
FB
V
FB
+ 60mV + 80mV + 100mV
FB Shorted LED Threshold
300
700
330
800
mV
mV
mA
nA
Overcurrent Protection Threshold (V – V
)
ISN
V
V
V
= 60V
600
1
ISP
ISP
FAULT Pin Pull Down Current
FAULT Pin Leakage Current
Internal PWM Generator
PWM Pin Voltage for Max. Duty Ratio
PWM Pin Voltage for Min. Duty Ratio
Min. Duty Ratio
= 0.2V, V = 1.25V
FB
FAULT
FAULT
= 3V, V = 0.7V
–100
100
FB
1.2
0.2
V
V
V
V
= 0.2V
= 1.2V
0.78
100
7.8
%
PWM
PWM
Max. Duty Ratio
%
PWM Pin Voltage Step per Duty Ratio Setting
PWM Pin Current
mV
nA
Hz
%
PWM = 3V
RP = 100k
–100
100
PWM Clock Frequency
400
Fraction of INTV for 10% Duty Ratio
27.2
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
LT3950J is guaranteed over the −40°C to 150°C operating junction
temperature range. Operating lifetime is derated at junction temperatures
greater than 125°C.
Note 4: LED Amplifier parameters measured in a servo loop with VC.
Note 2: Do not apply a positive or negative voltage to INTV , PWMTG, or
RT pin, otherwise permanent damage may occur. Use these pins only as
directed in the Pin Functions and Applications Information sections.
Note 3: The LT3950E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the −40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
CC
Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Rev. 0
4
For more information www.analog.com
LT3950
TYPICAL PERFORMANCE CHARACTERISTICS
PWM Generator Duty Ratio vs
Switching Frequency vs
Temperature
PWM Pin Voltage
Switching Frequency vs RT
ꢀꢀ00
ꢀꢁꢂ0
ꢀꢁꢀ0
ꢀ0ꢁ0
ꢀ0ꢁ0
ꢀ000
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢁ0
ꢀꢁꢂ0
ꢀꢁ00
ꢀ00
ꢀ0
ꢀ0
ꢀ
ꢀ
0.ꢀ
0.ꢀ
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ ꢀ.0 ꢀ.ꢀ ꢀ.ꢁ
ꢀ0
ꢀ00
(kΩ)
ꢀ000
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇꢈꢉꢊꢋ ꢌꢅꢍ
R
ꢀ
ꢀꢁꢂ0 ꢃ0ꢀ
ꢀꢁꢂ0 ꢃ0ꢄ
ꢀꢁꢂ0 ꢃ0ꢄ
ISP–ISN Full-Scale Threshold vs
CTRL Pin Voltage
ISP–ISN Threshold (Full Scale) vs
Temperature
Internal PWM Frequency vs RP
ꢀ
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢀ
ꢀꢁ0
0
0.ꢀ
ꢀꢁ0
ꢀ0
ꢀ00
(kΩ)
ꢀ000
0
0.ꢀ
0.ꢀ
ꢀ
ꢀꢁRꢂ
ꢀ.ꢁ
ꢀꢁꢂ
ꢀ.ꢁ
ꢀ.0
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
R
ꢀ
ꢀꢁꢂ0 ꢃ0ꢄ
ꢀꢁꢂ0 ꢃ0ꢂ
ꢀꢁꢂ0 ꢃ0ꢄ
ISP–ISN Threshold (50% Scale)
vs Temperature
ISP–ISN Threshold (10% Scale)
vs Temperature
ISP–ISN Threshold (ISP = 0V) vs
Temperature
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢀꢁ
ꢀꢀꢁ
ꢀꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ0 ꢃ0ꢁ
ꢀꢁꢂ0 ꢃ0ꢄ
ꢀꢁꢂ0 ꢃ0ꢄ
Rev. 0
5
For more information www.analog.com
LT3950
TYPICAL PERFORMANCE CHARACTERISTICS
FB Regulation Voltage vs
Temperature
FB Overvoltage Threshold
(Rising) vs Temperature
FB Short LED Threshold (Falling)
vs Temperature
ꢀ.ꢁꢂ0
ꢀ.ꢁꢂꢁ
ꢀ.ꢁꢁꢂ
ꢀ.ꢁꢀꢂ
ꢀ.ꢁ0ꢂ
ꢀ.ꢁ00
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁ0
ꢀ.ꢁꢂ
ꢀ.ꢁꢀ
ꢀ.ꢁ0
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀꢀ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀ0ꢁ
ꢀ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁ0
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁ0
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ0 ꢃꢄ0
ꢀꢁꢂ0 ꢃꢄꢄ
ꢀꢁꢂ0 ꢃꢄꢅ
FB Open LED Threshold (Rising)
vs Temperature
C/10 Threshold (Falling) vs
Temperature
ISP–ISN Regulation Voltage vs
FB Pin Voltage
ꢀ.ꢁ0
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀ0
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ0
ꢀꢁꢂ ꢃ ꢀꢁꢄꢃꢅꢆꢇ
.
.
R
0
ꢀꢁ0
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁ0
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ0 ꢃꢄꢀ
ꢀꢁꢂ0 ꢃꢄꢅ
ꢀꢁꢂ0 ꢃꢄꢂ
EN/UVLO Threshold vs
Temperature
EN/UVLO Pin Current vs
Temperature
ISP Regulation Engagement Point
ꢀ.ꢁ00
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂ0
ꢀ.ꢁꢂꢂ
ꢀ.ꢁꢂ0
ꢀ.ꢁꢁꢂ
ꢀ.ꢁꢀ0
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁ0
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢀ0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ0 ꢃꢄꢅ
ꢀꢁꢂ0 ꢃꢄꢅ
ꢀꢁꢂ0 ꢃꢄꢅ
Rev. 0
6
For more information www.analog.com
LT3950
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Off Time vs
Temperature
INTVCC Voltage vs Temperature
INTVCC Dropout vs Temperature
ꢀ.ꢁ00
ꢀ.0ꢁ0
ꢀ.0ꢁ0
ꢀ.0ꢁ0
ꢀ.0ꢁ0
ꢀ.000
ꢀ.ꢁꢂ0
ꢀ.ꢁꢂ0
ꢀ.ꢁꢂ0
ꢀ.ꢁꢀ0
ꢀ.ꢁ00
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁꢀ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ0 ꢃꢄꢁ
ꢀꢁꢂ0 ꢃꢄ0
ꢀꢁꢂ0 ꢃꢄꢅ
PWMTG On-Voltage vs
Temperature
Switch RDS(ON) vs Temperature
ꢀ00
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ0 ꢃꢄꢄ
ꢀꢁꢂ0 ꢃꢄꢀ
Rev. 0
7
For more information www.analog.com
LT3950
PIN FUNCTIONS
ISP: Kelvin connect this pin to the high side of the LED
1.2V, the duty ratio of the internal PWM generator will
vary with the pin voltage. A linear ramp of voltage on the
PWM pin between 0.2V and 1.2V and lasting many PWM
dimming cycles (set by RP) will result in an exponentially
increasing PWM duty ratio. An external PWM signal can
also drive this pin directly if the ON and OFF voltages are
above 1.3V and below 100mV, respectively.
current feedback sense resistor. Current in the sense
resistor is 250mV/ R
while the CTRL pin voltage
SENSE
exceeds 1.2V. It varies as (CTRL – 200mV)/(4 • R
)
SENSE
if the voltage at the CTRL pin is between 200mV and 1.2V.
ISN: Kelvin connect this pin to the low side of the LED
current feedback sense resistor, see ISP for more details.
If the voltage difference V – V ever exceeds 700mV
SYNC/SPRD: Switch Clock Synchronize / Spread
Spectrum. Tie this pin to INTVCC to enable internal spread
spectrum frequency modulation. An external clock can
also drive this pin to synchronize switching. Choose RT
such that the LT3950 clock would be close to the external
clock, then drive this pin with that clock.
ISP
ISN
(typ.), switching stops and the part re-enters soft-start.
The PWMTG pin goes high to disconnect the load, and
the part signals an overcurrent event.
FB: Output Voltage Feedback Pin. This pin is used for
output voltage regulation and limiting. Tie this pin to a
resistive voltage divider from the output voltage. When
the voltage at FB approaches 1.2V, the control loop will
reduce switch current to regulate output voltage such that
FB remains around 1.2V. If LED current falls below 10%
(typ.) of full scale while the output voltage is in regulation,
an LED Open event is signaled. If the voltage at FB exceeds
1.3V (typ.), PWMTG is driven high, switching stops, and
the device signals an overvoltage event. If the voltage at
FB falls below 300mV (typ.) after soft-start has finished,
an LED Short event is signaled at FAULT, PWMTG is driven
high, switching stops and the part re-enters soft-start. See
the Applications section for more info on the use of the
FB pin for general applications.
INTV : Voltage Supply Used by Internal Circuitry. Tie a
CC
1µF capacitor between this pin and ground. This pin is
sometimes used as a reference voltage for other pins,
however this pin is not intended for use as a power source
for external loads, and connecting it to any external load
may interfere with operation of the system. It is not
recommended to connect INTV except as directed to
CC
LT3950.
RT: Connect a resistor between this pin and ground to set
the switching frequency. Do not connect anything other
than a resistor to this pin or the system may not function
correctly.
RP: Connect a resistor between this pin and ground to set
CTRL: Analog Alternative to PWM Dimming. Tie to INTV
to set RSENSE current to full scale. Current in RSENSE varies
as (CTRL – 200mV)/(4 • R
CTRL pin varies from 200mV to 1.2V.
CC
the PWM dimming generator frequency. Connect this pin
to INTV to synchronize the PWM dimming clock to the
CC
) when the voltage at the
SENSE
switching clock (f
= f /4096).
PWM
SW
FAULT: Open-Drain Fault Indication Pin Indicating Short
VC: An internal error amplifier node used for compensa-
tion. Stabilize the loop by connecting a capacitor or RC
network between this pin and ground.
LED, Open LED, Overvoltage and Overcurrent Faults. Tie
this pin through a 100k resistor to V or INTV , or use
IN
CC
it as an open drain signal. LT3950 pulls this pin low to
PWM: Pulse Width Modulation (PWM) Dimming Generator
Control Pin. Connect an analog signal to this pin to use
the internal exponential scale dimming PWM generator.
When the voltage at this pin remains between 0.2V and
signal all reported fault events.
EN/UVLO: Enable/Undervoltage Lockout . When the volt-
age at this pin falls below 1.25V (typ.), with approximately
Rev. 0
8
For more information www.analog.com
LT3950
PIN FUNCTIONS
32mV of hysteresis when returning over 1.25V, switching
stops and the part shuts down. Drive this pin high with
a logic level greater than 1.4V or low with a logic level
below 1V for simple ON/OFF functionality, or tie it through
a resistive voltage divider to VIN for a precise input under-
voltage shutdown threshold.
flow of residual charge from the output capacitor when
the load should be disconnected, as well as to prevent the
long transient that would result from needing to recharge
the output capacitor at the end of a long PWM off period.
Leave open if unused. The voltage at PWMTG is limited
to 7.5V (typ.) below the voltage at ISP to protect the gate
of the PMOS switch.
V : Input Supply Pin. Must be locally bypassed.
IN
SW: Switch Pin. See PCB recommendations in the
Applications section for details on reducing EMI.
PWMTG: High Side Gate Driver for External Series PMOS
Switch. This pin is used to disconnect the load for PWM
dimming as well as fault events. PWMTG drives the PMOS
GND (Exposed Pad): This is the ground connection. Must
be soldered to PCB ground for the device to work.
gate between V and V – 7.5V (typ.) to cut off the
ISP
ISP
Rev. 0
9
For more information www.analog.com
LT3950
BLOCK DIAGRAM
ꢇ
FAULT
ꢀꢃ
FAULT ꢂꢄꢗ
ꢘꢃꢌꢝꢇꢊꢐ
ꢇ
ꢔ
ꢕ
ꢔ
ꢕ
ꢀꢃ
ꢘꢃ
ꢏ.ꢖꢓꢇ
ꢏ.ꢖꢇ
ꢇ
ꢁꢐꢅꢉꢢꢁꢉꢙRꢉ
ꢙꢃꢍ
ꢀꢃ
ꢔ
ꢕ
ꢔ ꢏ.ꢖꢇ
ꢕ
ꢅꢙꢝꢊꢉ ꢊꢐꢎꢀꢈ
0.ꢖꢇ
ꢡ
ꢀꢃꢉꢇ
ꢁꢄ
ꢈꢈ
ꢊꢐꢎ
ꢙꢍꢈ
ꢁꢈꢙꢊꢘ
R
ꢁ
ꢈꢐꢝꢃꢉ
ꢐꢇRꢅꢄ
ꢣ
ꢔ
ꢕ
ꢁꢊꢐꢂꢘ ꢈꢐꢗꢂ
R
ꢁ
ꢣ
ꢂꢄꢗ
ꢇꢀꢁꢂ
ꢁꢄ
ꢅꢆ
ꢕ
ꢔ
ꢂꢄꢗꢉꢎ
ꢏ.ꢖꢇ
ꢔ
ꢕ
ꢇꢀꢁꢂ ꢕ ꢛꢇ
ꢅꢆꢐꢇ
ꢅꢆꢐꢈ
ꢏ.ꢑꢇ
0.ꢑꢇ
ꢅꢆꢐꢚ
ꢔ
ꢕ
ꢑ00ꢠꢞꢟ ꢉꢐ ꢖꢗꢞꢟ
ꢐꢁꢈꢀꢊꢊꢙꢉꢐR
ꢂꢄꢗ ꢐꢁꢈꢀꢊꢊꢙꢉꢐR
ꢑ00ꢞꢟ ꢉꢐ ꢏꢠꢞꢟ
ꢔ
ꢕ
ꢖꢓꢜꢇ
ꢏꢇ
ꢔ
ꢕ
ꢔ
ꢕ
ꢏꢇ
ꢈꢌꢏ0
ꢐꢈ
ꢔ
ꢕ
ꢛ00ꢜꢇ
ꢔ
ꢕ
ꢔ
ꢕ
ꢀꢁꢂ
ꢀꢁꢃ
R
ꢔ
ꢕ
ꢔ
ꢔ
ꢕ
ꢏ.ꢖꢇ
ꢂꢄꢗꢉꢎ
ꢤR
ꢈꢉRꢊ
ꢎꢃꢍ
ꢇꢈ
ꢁꢋꢃꢈꢌꢁꢂRꢍ
Rꢉ
Rꢂ
ꢊꢘꢍ
ꢙRRꢙꢋ
ꢑꢒꢓ0 ꢆꢍ
Rev. 0
10
For more information www.analog.com
LT3950
OPERATION
In addition to regulating load current, the LED current
sense amplifier also provides a digital indication of
whether the load current is above or below 10% of the
programmed full-scale value. If the load current drops
below 10% of full-scale while the FB pin voltage is in
regulation, the FAULT pin is asserted to indicate an Open
LED event.
LT3950 is a constant-frequency, constant-current, con-
stant voltage (CC/CV) power supply with integrated low
side NMOS switch that can be configured as a boost,
SEPIC, buck mode or buck-boost mode LED driver. The
operation of the part can be best understood by looking at
the block diagram. At the beginning of every clock cycle,
the clock signal sets an SR latch controlling the switch
driver. The switch turns on and connects the inductor
to ground. The positive voltage drop across the induc-
tor results in linearly increasing current in the inductor.
The switch will remain on until the current comparator
near the SR latch resets it. This reset will occur when the
switch current exceeds the internal demand current. This
demand current is determined by the error amplifier. The
external LED current sense resistor used to program load
current drives the error amplifier. The voltage drop across
the sense resistor multiplied by the amplifier’s transcon-
ductance establishes the demand current.
Fast overcurrent protection relies on a separate signal path
than the main current sense amplifier. If the sense resis-
tor voltage (V –V ) exceeds 700mV (typ.), switching
ISP ISN
stops and the FAULT pin is asserted to indicate an overcur-
rent event. This event, along with Short LED, also triggers
a brief interruption of switching while soft-start is reset,
followed by a soft start of the switching.
Three different methods for dimming the LED load are
provided with LT3950. First, the voltage at the CTRL pin,
which sets the sense resistor regulation threshold, pro-
vides continuous, analog dimming of the LED load. In
addition, two method of PWM dimming exist. The first,
external PWM, relies on a user-provided PWM signal. This
signal drives the PWM pin directly, causing the system
to turn off and on (meaning stop and start switching,
and also disconnect and reconnect the LED load to the
output capacitor via PWMTG) based on the duty ratio of
the PWM pin voltage. Alternatively, internal PWM dim-
ming is available.
With no induced offset, the error amplifier would regulate
the load to zero current based on the voltage across the
LED current sense resistor. To establish the positive offset
in the error amplifier needed to program the LED cur-
rent, a small current is intentionally pulled from only one
input of the amplifier through a series resistor. The CTRL
pin establishes this offset current by varying the voltage
dropped across a resistor to ground. These two resistors
are internal to the IC. Changing the CTRL pin voltage will
vary the LED current sense resistor regulation voltage
between true zero and 250mV.
Internal PWM dimming uses an internal analog-to-digital
converter to translate the voltage at the PWM pin to a
7-bit digital representation. This conversion uses a lin-
ear scale; every 7.8mV (typ.) the 7-bit value changes.
Each particular value corresponds to a unique duty ratio
that is separated exponentially from its neighbors. For
example, moving by 7.8mV (typ.) near the 10% duty ratio
region can result in a change from 9.6% to 10% duty
ratio. Moving by the same difference, 7.8mV (typ.) near
the 100% region can change the duty ratio from 96%
to 100%. A smooth ramp at the PWM pin lasting many
PWMTG dimming periods as set by RP will create an
exponentially increasing PWM duty ratio for the LED load.
This preserves dimming accuracy and resolution across
a wide range of PWM dimming duty ratios.
During constant current operation the FB pin provides
overvoltage protection. While the FB pin voltage is below
its regulation threshold, the FB amplifier has little effect
on demand current. However, as the FB pin voltage
approaches VFB, the FB amplifier has an increasingly pro-
nounced effect, until eventually it dominates the demand
current. When the FB pin voltage exceeds the regulation
threshold by 100mV (typ.) the FAULT pin is asserted to
indicate an overvoltage event. Similarly, if the voltage at
the FB pin ever falls below 300mV (typ.) (excluding start-
up) then the FAULT pin is asserted to signal a shorted
LED event.
Rev. 0
11
For more information www.analog.com
LT3950
APPLICATIONS INFORMATION
Introduction
CTRL pin voltage falls below 200mV, and will continue to
supply full-scale current after the voltage at the CTRL pin
LT3950 provides a variety of features to enable a wide
range of application options. Due to the small package
size and pin count, many pins perform more than one
function. The simplest LT3950 application is realizable in
only a few off-chip components and with very few design
choices on the part of the user. To fully utilize the capabil-
ity of the part, however, requires a good understanding
of how the individual features play together. The detailed
explanations of each feature below along with several
example application circuits will help with developing a
good understanding of the part.
exceeds 1.2V, all the way up to INTV . Total LED current
CC
(I ), taking the effects of the CTRL pin into account is
LED
then:
ꢄ
ꢇ 0.ꢈꢄ
ꢅꢆRꢁ
ꢀ
=
ꢌꢍ 0.ꢈꢄ < ꢄ
≤ ꢎ.ꢈꢄ
ꢁꢂꢃ
ꢅꢆRꢁ
ꢉR
ꢊꢂꢋꢊꢂ
Note the CTRL pin can also be used for PWM by driving it
with a digital signal whose low value is below 100mV and
whose high value is above 1.3V. This technique for PWM
dimming will not allow very high frequency PWM signals.
The frequency of PWM driving the CTRL pin should be
below 1kHz. For higher frequency PWM, use the PWM pin,
discussed later. A graphical depiction of the full range of
CTRL pin voltage appears below.
Programming the LED Current
Full-scale current through the LED string is easily pro-
grammed using a single resistor (R
) connected in
SENSE
series with the LED string. The sense resistor should be
placed on the high side of the LED string, and Kelvin con-
nected to sense pins ISP and ISN. The loop will regulate
a drop of 250mV across this sense resistor, scaled by
the voltage at the CTRL pin, discussed later. A half-Watt
resistor will usually be sufficient. Since the loop regulates
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀ0
the voltage across R
, typical full-scale load current
SENSE
(I ) is defined as
FS
0
1
I
=
A
FS
4R
ꢀꢁ0
SENSE
0
0.ꢀ
0.ꢀ
ꢀ.ꢁ
ꢀꢁꢂ
ꢀ.ꢁ
ꢀ.0
ꢀ
ꢀꢁRꢂ
ꢀꢁꢂ0 ꢃ0ꢄ
For the best performance and protection, sense at the
highest potential in the LED string, and tie the source of
the external PWM dimming PMOS to ISN. More details
on the PWM dimming PMOS will be discussed later.
Note that the loop is able to regulate LED current down
to ISP = 0V, but a ground sensing configuration is not
desirable. For more information see the Low Voltage
(SEPIC) Startup section.
Figure 1. VISP-ISN vs CTRL Pin Voltage
Setting the Output Regulation Voltage
In addition to output current regulation, LT3950 can also
provide output voltage regulation. The loop will go into
voltage regulation mode when the voltage at the FB pin
approaches 1.2V. Regulating output voltage will reduce
LED current below its programmed value. Voltage regula-
tion mode is primarily included as a safety feature, allow-
ing the part to gracefully manage Open LED and similar
events.
Adjusting LED Current with the CTRL Pin
The CTRL pin provides an analog alternative to PWM dim-
ming. The value of the voltage regulated across the sense
resistor can be adjusted with the CTRL pin. As the voltage
present at this pin varies from 200mV to 1.2V, the regu-
lated voltage drop across the sense resistor varies from
0V to 250mV. The system will supply no current if the
To set the output regulation voltage, connect a resistive
voltage divider from the output voltage to FB as shown
below. Choose R and R to set the output voltage:
FB1
FB2
Rev. 0
12
For more information www.analog.com
LT3950
APPLICATIONS INFORMATION
off the disconnect PMOS, and the device reports a fault
⎛
⎞
RFB1
RFB2
VOUT = 1+
•1.2V
at the FAULT pin.
⎜
⎟
⎝
⎠
ꢊ
ꢈꢉꢁ
Setting Switching and PWM Dimming Generator
Frequency
ꢇ
ꢈꢉꢁ
R
ꢅꢋꢌ
ꢀꢁꢂꢃꢄ0
ꢅꢋ
To program the switching frequency of LT3950, simply
connect a single resistor to ground from the RT pin. The
R
ꢅꢋꢆ
table below includes several common R resistor values
T
ꢂꢃꢄ0 ꢅ0ꢆ
and corresponding switching frequency. It is important to
connect nothing to the RT pin except this resistor.
Figure 2. Voltage Feedback Network
Table 1. Selected RT Values and Switching Frequency
It is important that the divider be Kelvin connected to the
R Value (kΩ)
T
Switching Frequency (MHz)
output capacitor. The resistors R and R should be
FB1
FB2
402
301
237
191
162
140
121
107
97.6
80.6
76.8
73.2
66.5
61.9
57.6
52.3
48.7
45.3
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
chosen such that their total value is between 1k and 1M.
For high dynamic range (>10,000:1) PWM dimming, a
total resistance of up to 10M may be appropriate. If the
part is regulating output voltage and the current drops
below 10% of full-scale, an open LED event will be sig-
naled at the FAULT pin.
In some configurations, such as buck mode, where the
load voltage is not directly referred to ground, a level
shifter may be needed to use constant voltage mode
control. An example circuit to accomplish output voltage
control for buck mode and buck-boost mode topologies
is shown below.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
⎛
⎞
⎟
⎠
R
R
ꢉꢆꢈ
ꢀ
= ꢄ ꢅ ꢀ + ꢈ.ꢄ
⎜
ꢆꢇ
ꢁꢂꢃ
⎝
ꢉꢆꢄ
R
ꢋ0ꢌ
ꢋ0ꢌ
ꢆ
ꢇꢈꢁ
ꢀꢇꢍꢎ
ꢅꢉꢋ
ꢅꢉꢊ
ꢀꢁꢂꢃꢄ0
ꢅꢉ
ꢂꢃꢄ0 ꢅ0ꢂ
During start-up, the switching frequency is reduced to
allow sufficient switch OFF time, especially for 2MHz
operation, so that inductor current can ramp below cur-
rent limit when there is minimal voltage across the induc-
tor during the OFF time. This condition is encountered
at start-up or after faults, when the output is still low.
During start-up, or when restarting after faults, switching
frequency will drop to around 40% of its nominal value,
and step up every 16 cycles. For more information about
this, see the section concerning soft-start.
R
Figure 3. Voltage Feedback Network with Level Shifter
FB Overvoltage Lockout
As part of the safety feature offered by output voltage
regulation, if the voltage at the FB pin reaches or exceeds
1.3V (typ.), switching stops, PWMTG pulls high to turn
Rev. 0
13
For more information www.analog.com
LT3950
APPLICATIONS INFORMATION
The PWM dimming generator clock offers two program-
ming options. For a separate, free-running clock with
respect to the switching frequency, connect a resistor
from the RP pin to ground. Similar to the RT pin, the RP
pin sets the frequency of PWM dimming as a function of
resistance.
For more information on power stage topologies, see the
example application circuits.
The PWM pin allows two modes of PWM dimming. The
first mode is external PWM. In this mode, a digital signal
created by some other device, such as a microprocessor,
drives the PWM pin. This PWM signal directly controls
the part: when this signal is high, the part runs, when this
signal is low, the part does not run, and disconnects the
load if an external PMOS is used. Tying the PWM pin to
INTVCC results in continuous, uninterrupted operation.
Conversely, tying the PWM pin to ground results in the
system remaining idle indefinitely. For ON time < 1µs,
Table 2. Selected RP Values and PWM Dimming Frequency
R Value (kΩ)
P
PWM Dimming Frequency (Hz)
634
274
162
107
75
100
200
300
400
500
use a low Q (<10nC) MOSFET and low or zero value for
G
R at VC pin. External PWM supports dimming dynamic
C
range up to 20,000:1.
Alternatively, the PWM dimming clock can lock to the
switching clock. To do this, simply tie the RP pin to
The second mode of PWM dimming is internal. When
using internal PWM dimming, the analog voltage at the
PWM pin controls the duty ratio of the PWMTG signal. The
voltage range for internal PWM dimming is from 0.2V to
1.2V at the PWM pin. The internal PWM generator con-
verts the voltage at the PWM pin to a 7-bit digital rep-
resentation. The analog to digital converter responsible
for this uses a linear scale, each code is around 7.8mV
wide. Each 7-bit code corresponds to a unique duty ratio
value. The values of duty ratio are separated exponentially.
Another way to phrase it is that each time the 7-bit code
increases in value by 1, the duty ratio is multiplied by a
constant scaling factor. A log-scale plot of duty ratio vs
PWM pin voltage appears below.
INTV . In this mode, the PWM clock will be the switch-
CC
ing clock divided by 4096.
Pulse Width Modulation (PWM) Dimming
Pulse width modulation (PWM) allows high dynamic
range dimming of the LED load. When using PWM dim-
ming, a pulse train with duty ratio proportional to desired
LED current controls the load. During ON periods, the
part operates normally. During OFF periods the part stops
switching. While the part is not switching, the compensa-
tion node is high impedance to minimize changes to the
compensation capacitor voltage. This reduces transient
settling time when the next ON period arrives. In addi-
tion to this, LT3950 provides an optional load disconnect.
Disconnecting the load makes turn-off much faster, as the
output capacitor does not continue to conduct current
into the load. Transient settling time is also shorter when
turning back on, as the output capacitor’s state is less
affected by the load.
ꢀ00
ꢀ0
ꢀ
To use the external load disconnect, tie a PMOS in series
with the load such that the source of the PMOS connects
to the ISN node, and the drain to the LED load. Connect
the gate of the PMOS to the PWMTG pin. The voltage at
0.ꢀ
0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ ꢀ.0 ꢀ.ꢀ ꢀ.ꢁ
the PWMTG pin will vary between V and V – 7.5V
ISP
ISP
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇꢈꢉꢊꢋ ꢌꢅꢍ
to turn the PMOS off and on. Note that this configuration
ꢀꢁꢂ0 ꢃ0ꢄ
works for any of the supported power stage topologies.
Figure 4. PWM Duty Ratio
Rev. 0
14
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LT3950
APPLICATIONS INFORMATION
Synchronizing the Switching Frequency
CISPR25 Conducted EMI Performance Current Method
ꢀ0
ꢀ0
ꢀꢁꢂꢃꢃ ꢄ ꢂꢅꢆRꢂꢇꢆ ꢁꢈꢉꢈꢊ
ꢀꢁꢂꢃꢄ0 ꢅꢅꢆꢇ ꢈꢉ
ꢀꢁꢂꢃꢄꢅꢆ
To synchronize LT3950 to an external clock, simply drive
the SYNC/SPRD pin with that clock signal. Choose the RT
resistor such that the system’s internal clock would be
within 10% of the external clock frequency. It is best to
have the RT programmed frequency as close as possible
to the external clock frequency.
ꢀ0
ꢀ0
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
Spread Spectrum Frequency Modulation
Like all switching converters, LT3950 does produce some
electromagnetic interference (EMI). Enabling spread spec-
trum frequency modulation can significantly attenuate this
interference. Conditions such as switching frequency and
printed circuit board (PCB) geometry affect the amount
of attenuation achievable with spread spectrum frequency
modulation. A variety of industry-standard tests exist to
quantify these effects.
0.ꢀ
ꢀ
ꢀ0
ꢀ0ꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
(a)
CISPR25 Conducted EMI Performance Voltage Method
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁꢂꢃꢃ ꢄ ꢂꢅꢆRꢂꢇꢆ ꢁꢈꢉꢈꢊ
ꢀꢁꢂꢃꢄ0 ꢅꢅꢆꢇ ꢈꢉ
ꢀꢁꢂꢃꢄꢅꢆ
To enable internal spread spectrum frequency modula-
tion, tie the SYNC/SPRD pin to INTV . The modulating
CC
waveform is a triangle wave with steps at the positive and
negative peaks. The modulation frequency is around 9kHz,
and the switching frequency range is from 100-125% of
the programmed value. Typical LT3950 EMI results are
shown in Figure 5.
ꢀꢁ0
ꢀꢁ0
0.ꢀ
ꢀ
ꢀ0
ꢀ0ꢁ
Maximum Duty Ratio
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
(b)
Since LT3950 uses a switch to connect an inductor from
VIN to ground, having a duty ratio of 100% would result in
zero current flowing to the load. To prevent this situation,
the part enforces a minimum off time. During this time,
irrespective of load or demand, the switch turns off and
allows the inductor current to flow into the load. The duty
ratio can, therefore, never reach 100%. The maximum
duty ratio varies with frequency. For the same minimum
off time, a higher frequency signal will have a smaller max-
imum duty ratio. At lower frequencies in boost configura-
tion and in Continuous Conduction Mode (CCM), the part
CISPR25 Radiated EMI Performance
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁ0
ꢀꢁꢂꢃꢃ ꢄ ꢂꢅꢆRꢂꢇꢆ ꢁꢈꢉꢈꢊ
ꢀꢁꢂꢃꢄ0 ꢅꢅꢆꢇ ꢈꢉ
ꢀꢁꢂꢃꢄꢅꢆ
can reach a duty ratio of 95% (that is, V /V = 60/3, the
IN
maximum range for the part). HoweverIaStPhigher frequen-
cies, such as 2MHz, the part has a maximum duty ratio
of around 90%. Maximum duty ratio at any frequency in
CCM is given by the following relationship.
ꢀꢁ0
0.ꢀ
ꢀ
ꢀ0
ꢀ00
ꢀ000
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
(c)
Figure 5. LT3950 Typical EMI (VIN = 12V, VLED = 25V, ILED
330mA, 2MHz)
=
D
= 1– f • 50ns
SW
MAX
Rev. 0
15
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LT3950
APPLICATIONS INFORMATION
Maximum Switch and Load Current
ꢆꢅ
ꢀꢁꢂꢃꢄ0
R
ꢅ
An important system parameter is the current limit. This
can prevent damage to the switch and external compo-
nents by limiting the maximum instantaneous current
conducting through the power switch. In a well-designed
system, there will be margin between the maximum switch
current to drive the LED load and the switch current limit.
The LT3950 offers a current limit that does not change
with duty ratio and also has sufficient slope compensa-
tion so that reaching the current limit during line and load
transients does not result in subharmonic oscillations.
A good rule of thumb for setting maximum LED current
for boost and buck-boost power stages appears below.
This equation assumes that the inductor selection used
limits current ripple to around 30% of average current. For
more information on inductor selection, see the External
Component Selection section.
ꢅ
ꢅ
ꢂꢃꢄ0 ꢇ0ꢈ
Figure 6. Typical Compensation
For many cases, a 1nF capacitor and 10kΩ resistor will
suffice. This is a good place to start for all applications. If
settling time is unacceptable, ringing is too large, or the
loop remains unstable, the information below can help.
First, try reducing or eliminating the compensation resis-
tor, R , especially if transient response is ringing or under-
damped. Reducing the compensation resistor will cause
longer settling time and larger deviation from load steps
such as PWM dimming.
C
Next, increase the size of the compensation capacitor, C .
C
This will reduce the frequency of the dominant (low fre-
quency) pole and thereby the unity gain frequency. It will
usually be possible to stabilize the loop given a big enough
compensation capacitor. Increasing the compensation
capacitor slows down the transient response to line and
load activity. If the compensation capacitor cannot change
by a small amount to achieve stability, consider instead
increasing the output capacitor or decreasing the inductor
to separate the load pole and right half plane zero.
V
IN
ILED,MAX(30%ripple) ≈1.4A •
V
ISP
In the boost and buck-boost mode topologies, average
switch current is related to average LED current by the
ratio of V to V . In the buck topology, average LED
IN
ISP
current approximately equals average inductor current.
For this reason the buck topology provides the highest
possible LED current capability. The peak instantaneous
switch current is thus the average LED current plus half of
the peak to peak ripple current. This leads to the following
result for buck mode current limit.
EXTERNAL COMPONENT SELECTION
Input and Output Capacitor Selection
I
= 1.4A
The input and output capacitors supply the transient cur-
rent for the power stage and should be placed and cho-
sen according to the transient current requirements. An
X7R type ceramic capacitor is usually a good choice for
both input and output capacitor. Even though X7R has
less variation with temperature and DC bias voltage than
many other materials, the effect of capacitance derating
with voltage stress must be considered. It is generally a
good rule of thumb to pick capacitors with a voltage rating
about 60% higher than the application demands.
LED,MAX(BUCK)
For more information about power stage topologies,
review the example application circuits included below.
Loop Compensation
Loop compensation normally will take the form of an RC
network connected between the VC pin and ground. A
single capacitor can fulfill stability requirements if PCB
area is extremely limited. The addition of a series resis-
tor, however, will increase response speed and can also
recover phase margin. A schematic diagram of the typical
compensation scheme is illustrated below.
The switching frequency, output current, inductor ripple
current, and tolerable input voltage ripple are key param-
eters to consider when determining the value of the input
capacitor. Typically, boost, buck-boost mode, and SEPIC
Rev. 0
16
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LT3950
APPLICATIONS INFORMATION
converters require a lower value input capacitor than buck
mode converters. Use the following equations to estimate
the value of the input capacitor. If the inductor is selected
according to the directions in the Inductor Selection sec-
the input capacitor of the buck mode case. Capacitor val-
ues will increase proportionally with decreasing switch-
ing frequency for the same ripple voltage. The equivalent
resistance presented by an LED load is typically low, so
larger capacitors may be needed to further reduce voltage
ripple. It is likely that the appropriate output capacitor
value will fall between 2.2µF and 47µF. Use the example
applications as a starting point for output capacitor selec-
tion. Sources of quality ceramic capacitors are listed in
Table 3.
tion, use the value 15% for the quantity i
/i
L(RIPPLE) L(DC)
in the following equation, otherwise use the fraction of
average inductor current representing half of the peak to
peak ripple current:
iL(RIPPLE) VLED(MAX)
i
LEDtSW
iL(DC)
ΔV
V
IN(MIN)
CIN(BOOST)
>
Table 3. Capacitor Manufacturers
IN(MAX)
MANUFACTURER
MURATA
TDK
WEBSITE
www.murata.com
www.tdk.com
www.kemet.com
www.t-yuden.com
www.avx.com
For a boost converter switching at 2MHz, a 2.2µF input
capacitor will often suffice.
KEMET
iLEDtSW
TAIYO YUDEN
AVX
CIN(BUCK)
>
ΔV
IN(MAX)
For the buck case at 2MHz, a 2.2µF input capacitor would
be appropriate to ensure less than 100mV of input volt-
Schottky Rectifier Selection
Choose a Schottky diode with reverse breakdown voltage
rating at or above 60V and with average forward current
rating greater than the programmed LED current with
some margin. It is best to find a rectifier with low equiva-
lent capacitance, around or below 350pF. Large equiva-
lent capacitance and/or poor PCB layout can negatively
interact with certain EMI mitigating features in LT3950.
Pay attention to reverse leakage current if the part is to
be used in low frequency PWM dimming (<200Hz) situa-
tions. The reverse leakage current can discharge the out-
put capacitor. This can lead to lengthy turn-on transient
effects that degrade maximum PWM dimming dynamic
range. Note that reverse leakage current increases with
temperature. For many LT3950 applications, the NXP
PMEG6020 will suffice. Table 4 has some recommend
component vendors.
age ripple with i
= 0.3A. Additional margin is recom-
LED
mended (e.g., the 1.5µF result of evaluating the above
equation may lead to selection of a 2.2µF input capacitor).
In the buck mode configuration, the input capacitor has
large pulsed currents due to the current returned through
the Schottky diode when the switch is off. In the buck con-
verter case it is important to place the capacitor as close
as possible to the Schottky diode and to the exposed pad
of the IC. It is also important to consider the ripple current
rating of the capacitor. For best reliability, this capacitor
should have low ESR and ESL and have an adequate ripple
current rating. Use the following equation to estimate the
RMS input capacitor current for the buck converter case.
⎛
⎞
VLED
VLED
iCIN(RMS) =iLED
•
1–
⎜
⎟
V
V
⎝
⎠
IN
IN
Table 4. Schottky Rectifier Manufaturers
The selection of the output capacitor depends on load and
power stage configuration. For example, a boost or buck-
boost mode converter will require a much larger output
capacitor than a buck mode converter for the same condi-
tions. The boost and buck-boost mode configurations will
also require similar low ESR and low ESL capacitors like
VENDOR
WEBSITE
ON Semiconductor
Diodes, Inc.
www.onsemi.com
www.diodes.com
www.centralsemi.com
www.nxp.com
Central Semiconductor
NXP
Rev. 0
17
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LT3950
APPLICATIONS INFORMATION
Inductor Selection
section, disconnect the load from the output capacitor.
The FAULT pin will be asserted. The part will not wait until
the end of the clock cycle to take this action. The LED
Open fault will only result in the FAULT pin being asserted;
switching will continue as normal. A summary table of
each type of fault appears at the end of this section.
Select an inductor for use with LT3950 that has a satura-
tion current rating greater than 1.7A, additional margin
is recommended. Choose the inductor value based on
desired ripple current given input and output voltage and
switching frequency. Use the equations below to select an
inductor with around 30% peak to peak ripple.
Overcurrent fault detection uses the current programming
sense resistor. If the voltage drop across the sense resis-
tor is greater than 700mV (typ.), an overcurrent event
is reported.
2
⎛
⎞
tSW
V
V
V
IN
VLED
IN
LBOOST
>
1–
⎜
⎟
0.3iLED LED
⎝
⎠
While overcurrent senses the actual current into the load,
the LED Short fault senses load voltage. This can allow
the detection of limited failures, such as one or two of the
LEDs in a string becoming shorted. LT3950 senses the
voltage at the FB pin and reports an LED Short fault if that
voltage falls below 300mV (excluding during start-up). It
is important to note that the FB resistor divider must be
in place to use the LED Short fault detection.
⎛
⎞
tSWVLED
0.3iLED
VLED
V
IN
LBUCK
>
1–
⎜
⎟
⎝
⎠
Table 5. Inductor Manufacturers
VENDOR
WEBSITE
Sumida
www.sumida.com
www.we-online.com
www.cooperet.com
www.vishay.com
Wurth Elektronik
Coiltronics
Vishay
To report an LED Open fault, the voltage at the FB pin
must approach 1.2V while the load current falls below
10% of full-scale. It is important to note that the FB resis-
tor divider must be in place to use the LED Open fault
detection.
Coilcraft
www.coilcraft.com
Power PMOS Selection
For the PMOS to be used with PWMTG, select a device
with drain-source voltage rating higher than 65V, addi-
tional margin is recommended. The gate-source voltage
rating should be higher than 10V. The drain current rating
should be sufficient to conduct the full programmed LED
current with some margin. Ensure that the PWMTG drive
voltage of 7.5V will fully enhance the PMOS device. Be
careful when selecting a PMOS to consider the effect that
The Overvoltage fault occurs when the voltage at the FB
pin exceeds 1.3V. Like the LED Open fault, the FB resis-
tor divider must be in place to take advantage of the over
voltage fault protection.
ꢆꢒꢊRꢒꢆꢍꢇꢈꢋꢊ
FAULT
ꢃꢉ Rꢊꢋꢌꢍꢈꢇꢎꢏꢋ
ꢐꢑ0
ꢓ
ꢘ
ꢕꢖꢗ
ꢍꢊ
higher current ratings have on gate charge (Q ). A high Q
(>20nC) PMOS will slow turn-on and turn-offgtime, which
g
ꢆꢒꢊRꢐꢌRRꢊꢏꢇ
ꢍꢊꢓ ꢅꢔꢆRꢇ
can reduce maximum PWM dimming dynamic range.
ꢅꢆꢃꢇ ꢅꢇꢈRꢇ
ꢀꢁꢂ0 ꢃ0ꢄ
Figure 7. Fault Logic
LED Fault Events
LT3950 provides a variety of fault detection and reporting
functions to aid larger systems in responding to failures.
While LT3950 has many self-protection features, only four
types of faults will be reported to the outside world. Of
these, three (LED Short, Overvoltage and Overcurrent) will
cause the part to stop switching and, if an external PMOS
is used according to instructions in the PWM Dimming
All four types of faults result in the FAULT pull down turn-
ing on. Since the FAULT pin has an open-drain output,
connecting a resistor from FAULT to INTV , V , or an
CC IN
external supply is required for operation. The open-drain
output allows flexibility such as the ability to wire-OR
many parts together to detect faults on an array of devices
with a single digital I/O pin.
Rev. 0
18
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LT3950
APPLICATIONS INFORMATION
Excepting LED Open, all reported faults will result in inter-
ruption of switching. The Short LED and Overcurrent
faults trigger a cooldown period, after which the system
will enter soft-start as if it had just been turned on via the
EN/UVLO pin. Upon successful completion of the soft-
start process with no faults, the FAULT signal will be de-
asserted. During soft-start, the PWM Dimming logic low
state is ignored for both internal and external PWM until
soft start is complete or current in the LED reaches 10%
of full scale value.
soft-start or observes at least 10% of full-scale current
flowing through the sense resistor, the PWM low logic
state is ignored and the part runs continuously. If any
fault condition caused the part to re-enter soft-start, the
FAULT pin will remain asserted until the part successfully
completes the soft-start process.
ꢀ
ꢀ
ꢀꢁ00ꢂꢃꢄꢅꢆꢇꢈ
Table 6.
CONDITION (TYP.)
TYPE OF FAULT
Overvoltage
Open LED
FB Pin >1.3V
1.17V < FB pin < 1.3V and V
< 25mV
ISP-ISN
ꢀ
ꢀꢁ00ꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
FB pin < 300mV
> ~700mV
Short LED
V
Overcurrent
ISP-ISN
ꢀꢁ.ꢂ ꢀ0.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀꢀ.ꢁ ꢀꢁ.ꢁ ꢀꢁ.ꢂꢀꢁ.ꢂ
ꢀꢁꢂꢃ ꢄꢅꢆꢇ
ꢀꢁꢂ0 ꢃ0ꢄ
Soft Start
Figure 8. LED Short Hiccup Mode
To prevent a surge of current at start-up, LT3950 uses
an internal soft-start. This feature affects both current
limit and switching frequency. At start-up, the system will
switch at around 40% f with near zero current limit. As
the clock runs, both coSnWstraints relax, leading to normal
Using the EN/UVLO Pin
The EN/UVLO pin offers two modes of operation. First, it
can be driven high (above 1.4V) or low (below 1V) to act
as an enable pin, turning the part on and off. In addition to
this, the pin can also be used to create an accurate exter-
nal under voltage lockout (UVLO). To use this feature,
connect the EN/UVLO pin to a resistive voltage divider
operation after ~1800 • T
. Note that this process
SW(NOM)
does not take 1800 cycles to complete, rather the above
number takes into account the reduction in clock fre-
quency enforced by the soft-start feature. In total, 1,024
from the V pin to ground. Select resistors to program
IN
cycles are spent in soft-start, with f adjustments every
SW
the desired minimum V value for operation.
IN
16 cycles.
⎛
⎜
⎝
⎞
RUV1
RUV2
The cooldown period triggered by certain faults dis-
cussed in the LED Faults Section lasts for at least
V
) =1.25V • 1+
IN FALLING
(
⎟
⎠
32,768 • T
. At the end of the cooldown period,
SW(NOM)
⎛
⎞
RUV1
RUV2
the system attempts to start again, and enters soft-start
as if it had just been powered on for the first time.
V
) =1.28V • 1+
+2µA •RUV1
IN RISING
(
⎜
⎝
⎟
⎠
Regardless of whether it is the first-time soft-start or a
soft-start resulting from a fault condition, the LT3950 will
wait until the first PWM dimming pulse arrives before
beginning to power on the system. This PWM pulse can
be from an external source or from the internal dimming
PWM generator. At the arrival of the first PWM pulse,
soft-start begins and operation continues until the system
has reached steady state. Until the system either finishes
ꢇ
ꢎꢋ
ꢀꢁꢂꢃꢄ0
R
R
ꢆꢇꢈ
ꢆꢇꢉ
ꢊꢋꢌꢆꢇꢀꢍ
ꢂꢃꢄ0 ꢅ0ꢃ
Figure 9. Programming VIN Undervoltage Setpoint
Rev. 0
19
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LT3950
APPLICATIONS INFORMATION
The EN/UVLO threshold has a hysteretic window to pre-
vent oscillating between the ON and OFF states. When
the EN/UVLO pin falls below its falling threshold (1.25V
typ.), switching stops, soft-start is reset, and if an exter-
nal PMOS is used according to instructions in the PWM
Dimming section, the load is disconnected from the out-
put capacitor.
PCB Layout Guidelines and Information
Printed Circuit Board (PCB) layout profoundly affects per-
formance of all power applications. Proper electrical and
thermal connection between the IC and outside world will
make or break any system. Do not neglect the thoughtful
and detailed layout of any application PCB.
The exposed ground pad on the bottom of the package
is the only path to ground for the IC, and it will not work
correctly unless the exposed pad has a good, high-quality
solder connection to a ground plane. The ground con-
nection for analog functions such as RT, the compensa-
tion network, and any voltage dividers for PWM or CTRL
should be Kelvin connected to the exposed pad. A sepa-
rate power ground should exist for the input and output
Low Voltage (SEPIC) Startup
Certain power stage topologies, such as the SEPIC, may
require the part to start up in the condition where ISP and
ISN are both near (or at) 0V. This condition is handled dif-
ferently than steady-state operation. Below around 2.5V at
ISN, the part does not use the programmed offset defined
by the CTRL pin, but instead uses a constant offset of
around 85mV (typ.) across ISP and ISN. This ensures
that the part starts in a reasonable amount of time. When
ISN < 2.5V (typ), LED Open and LED Short faults are
disabled. The ability of the error amplifier to tolerate an
input common mode voltage of 0V should not lead the
user to consider low-side sensing. Not only is the LED
current sense amplifier most accurate above 4V on ISN,
but also recall that ISP provides the positive rail for the
driver of the external disconnect PMOS. Therefore the use
of low side sensing of LED current is not recommended.
capacitors and LED load. If possible, the INTV bypass
CC
capacitor should have its own ground.
Proper power and ground planes provide both electrical
and thermal connections between the IC and the outside
world. It is imperative that at least one ground plane be
present in any application of LT3950. Ground planes
should not be interrupted by other traces, and should be
continuous, very wide sheets of copper. If components
connect to the ground plane by way of vias, use filled vias
if possible. Connect the exposed pad of the IC to such a
ground plane. Use as many vias as will fit in the exposed
pad area to make the connection. Use filled vias if pos-
sible. Do not copy any particular layout for the exposed
pad connection, but instead use as many vias as will fit
given the capabilities of the PCB manufacturer.
Full-scale threshold accuracy is derated when V < 4V.
ISN
Planning for Thermal Shutdown
The LT3950 will automatically shut down when the inter-
nal temperature is above 170°C. This shutdown is guar-
anteed to always be outside of the operating region of the
device. The effects of thermal shutdown are similar to that
of certain load faults: switching stops, soft-start is reset,
and if an external PMOS is used according to instructions
in the PWM Dimming section, the load is disconnected
from the output capacitor.
In addition to soldering down the exposed pad, it is critical
to provide a good, robust layout for the rest of the power
path. Use wide traces for V and to connect to the load.
IN
Keep the sense resistor very close to the IC, and ensure
that the ISP and ISN traces run as close to one another
as possible. It is strongly recommended to not allow ISP
and ISN to take different paths to the sense resistor, but
The exposed pad of LT3950 is ground, and must be sol-
dered to a good, large ground plane with many vias to aid
in thermal management. A simple electrical connection
is not sufficient for high-power operation, good thermal
conductivity is critical.
instead to keep them beside one another as much as pos
-
sible. Minimize the total area of any SW node traces; keep
the output capacitor and external catch diode as close as
possible to the IC to help this. Finally, use wide traces to
Rev. 0
20
For more information www.analog.com
LT3950
connect to the external PMOS switch, if used. Note, how-
ever, that the gate of the external PMOS should be con-
nected by a narrow trace. Except for the external PMOS
gate, avoid vias where possible in the power path. If vias
are truly unavoidable, use many (more than 10) in parallel.
the amount of capacitance that the switch sees, and thus
reduce the current spike seen during switching events.
Failing to minimize the area of the so-called hot loop will
dramatically degrade EMI performance. Keep the output
capacitor and catch diode as close as possible to the SW
pin of the IC to minimize the hot loop. For more informa-
tion about hot loops see Analog Devices Application Notes
AN136 and AN139.
Despite the techniques used in the design of LT3950 to
mitigate electromagnetic interference (EMI), proper PCB
layout is critical for suppressing radiated and conducted
noise. Minimizing the area of the SW node will decrease
TYPICAL APPLICATIONS
5W Buck-Boost Mode LED Driver with Spread Spectrum Frequency Modulation
LED ARRAY
L1
2.2µF
1µF
Efficiency and Power Loss
D1
10µH
V
500mΩ
IN
M1
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
3V TO
48V
2.2µF
500mA
1M
ꢀ
ꢀꢁꢂ ꢃ 0.ꢄꢅ
SW
ISP
ISN
PWMTG
FB
ꢀ
ꢀꢁꢂ ꢃ 0.ꢄꢅꢆ
V
IN
EN/UVLO
20k
PWM
ꢀ
ꢀꢁꢂ ꢃ 0.ꢄꢅ
LT3950
CTRL
INTV
CC
INTV
SYNC/SPRD
RP
INTV
CC
CC
ꢀ
ꢀꢁꢂ ꢃ 0.ꢄꢅꢆ
1µF
100k
VC
RT
4.7k
220pF
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0 ꢀꢀ ꢀꢁ
ꢀꢁꢂ
FAULT
FAULT
2MHz
45.3k
GND
ꢀ
ꢀꢁ
ꢀꢁꢂ0 ꢃꢄ0ꢅꢆ
3950 TA02
L1: WURTH 74437324100
D1: DIODES INC. DFLS260Q
M1: VISHAY SI7309
Rev. 0
21
For more information www.analog.com
LT3950
TYPICAL APPLICATIONS
8W Boost LED Driver with Internal 10% PWM Dimming
V
2.2µH
0.5Ω
IN
Efficiency
3.3V TO
16V
2.2µF
2.2µF
ꢀꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
V
SW
ISP
ISN
IN
ꢀ
ꢀ ꢁꢂ0ꢃꢄ
ꢀꢁꢂ
EN/UVLO
390k
10k
100k
ꢀ
ꢀ ꢁꢂꢂꢃꢄ
ꢀꢁꢂ
8W
FAULT
FAULT
INTV
CC
FB
LED
LT3950
POWER
(DERATED
BELOW
1µF
CTRL
ꢀ
ꢀ ꢁꢂ0ꢃꢄ
PWMTG
VC
ꢀꢁꢂ
V
= 6V)
IN
267k
100k
PWM
SYNC/SPRD RP
36k
220pF
RT
GND
ꢀ
ꢀ ꢁꢂꢂꢃꢄ
ꢀꢁꢂ
300Hz
180k
2MHz
45.3k
ꢀ
ꢀ0
ꢀꢁ
ꢃꢀꢄ
ꢀꢁ
ꢀꢁ
3950 TA03
ꢀ
ꢁꢂ
ꢀꢁꢂ0 ꢃꢄ0ꢀꢅ
L1: WURTH 74437321022
D1: DIODES INC. DFLS260Q
M1: VISHAY SI7309
Rev. 0
22
For more information www.analog.com
LT3950
TYPICAL APPLICATIONS
5W SEPIC LED Driver with Internal 10% PWM Dimming
L1
6.8µH
1:1
2.2µF
D1
333mA
750mΩ
V
IN
3V TO
36V
3
1
2
4
2.2µF
10µF
•
1M
Efficiency
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
0.ꢀ
0.ꢀ
0
59k
SW
FB
ISP
ISN
V
IN
EN/UVLO
CTRL
M1
PWMTG
INTV
CC
267k
100k
LT3950
GND
PWM
100k
INTV
CC
SYNC/SPRD
INTV
CC
LED
ARRAY
FAULT
FAULT
RT
RP
VC
1µF
47k
330pF
ꢀ
ꢀ
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢃꢀꢄ
2MHz
45.3k
ꢀ
ꢁꢂ
ꢀꢁꢂ0 ꢃꢄ0ꢅꢆ
3950 TA04
L1: WURTH 744 870 00
M1: VISHAY SI230
D1: DIODES INC DFLS160Q
Rev. 0
23
For more information www.analog.com
LT3950
TYPICAL APPLICATIONS
36W Buck-Mode LED Driver
4.7µF
L1
68µH
1A
LED ARRAY
D1
V
250mΩ
Efficiency
IN
M1
45V TO
58V
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
0.ꢀ
0.ꢀ
0
4.7µF
0.1µF
10k
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
1M
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
499k
V
ISP
ISN PWMTG
LT3950
IN
EN/UVLO
FB
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
15.4k
28k
PWM
CTRL
SW
ꢀ
ꢀ 0.ꢁꢂ
ꢀꢁꢂ
INTV
CC
INTV
CC
INTV
CC
100k
RP
FAULT
FAULT
RT
47k
ꢀꢁ ꢀꢁ.ꢂ ꢀꢁ ꢀꢁ.ꢂ ꢀꢁ ꢀꢁ.ꢀ ꢀꢁ ꢀꢀ.ꢀ ꢀꢁ ꢀꢁ.ꢀ ꢀ0
ꢀꢁꢂ
VC
1µF
ꢀ
ꢀꢁ
301k
400kHz
GND SYNC/SPRD
ꢀꢁꢂ0 ꢃꢄ0ꢂꢅ
220pF
3950 TA05
L1: WURTH 744 373 49680
D1: DIODES INC. DFLS260
M1: VISHAY SI7309
Rev. 0
24
For more information www.analog.com
LT3950
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0° – 6° TYP
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
25
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT3950
TYPICAL APPLICATION
2MHz, 8W and 0.8W Input Boost LED Driver
L1
2.2µH
D1
0.5Ω
m1
100%
V
IN
2.2µF
2.2µF
6V TO 16V
10%
V
SW
ISP
ISN
IN
100k
100k
EN/UVLO
390k
10k
100k
100k
FAULT
1µF
FAULT
FB
8W
INTV
VC
CTRL
RP
CC
LED POWER
(DERATED BELOW
LT3950
V
= 6V)
IN
PWMTG
RP
267k
100k
180k
300Hz
RT
45.3k
2MHz
PWM
GND GND SYNC/SPRD
36k
220pF
3950 TA06a
L1: WURTH 74437321022
D1: DIODES INC. DFLS260Q
M1: VISHAY SI7309
Startup Using Always-On Input
Startup Using 10% Dimming Input
ꢀ
ꢀꢁ ꢂꢃꢄꢅꢆꢃ
ꢀ
ꢀꢁ ꢂꢃꢄꢅꢆꢃ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ ꢂ00ꢃꢀꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀ
ꢀꢁ ꢂ00ꢃꢀꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢀ ꢅꢂꢆꢇꢈꢁꢉ
ꢀꢁꢂꢃ ꢄꢀ ꢅꢂꢆꢇꢈꢁꢉ
ꢀꢁꢂ0 ꢃꢄ0ꢅꢆ
ꢀꢁꢂ0 ꢃꢄ0ꢅꢆ
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT3517
LT3518
LT3922
LT3761
LT3952
LT3477
Full-Featured LED Driver with 1.5A Switch
Current
1.5A, 45V Internal Switch, 5000:1 True Color PWM Dimming, 100mV High-Side Current
Sense, Open LED Protection
Full-Featured LED Driver with 2.3A Switch
Current
2.3A, 45V Internal Switch, 3000:1 True Color PWM Dimming, 100mV High-Side Current
Sense, Open LED Protection
36V, 2A Synchronous Step-Up LED Driver
2% Current Regulation Accuracy, 5000:1 PWM Dimming, 128:1 Internal PWM,
Silent Switcher® Architecture for Low EMI
60V LED Controller with Internal PWM
4.5V to 60V Input, Rail-to-Rail Current Sense 0V to 80V, 3000:1 True Color PWM, 3%
Current Regulation Accuracy
IN
Generator
60V LED Driver with 4A Switch Current
4A, 60V Internal DMOS Switch, 4000:1 True Color PWM Dimming, 0V to 60V Output
Current Regulation with Monitor
3A DC/DC Converter with Dual Rail-to-Rail
Current Sense
Dual 100mV Rail-to-Rail Current Sense Amplifiers, 2.5V to 25V Input Voltage, 3A, 42V
Internal Switch
Rev. 0
10/20
www.analog.com
26
ANALOG DEVICES, INC. 2020
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