LT4356MPS-3 [ADI]
Surge Stopper with Fault Latchoff;
| 型号： | LT4356MPS-3 |
| 厂家： | 
ADI |
| 描述： | Surge Stopper with Fault Latchoff |
| 文件： | 总24页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4356-3
Surge Stopper with
Fault Latchoff
FEATURES
DESCRIPTION
The LT®4356-3 surge stopper protects loads from high
voltage transients. It regulates the output during an
overvoltage event, such as load dump in automobiles, by
controllingthegateofanexternalN-channelMOSFET.The
output is limited to a safe value thereby allowing the loads
to continue functioning. The LT4356-3 also monitors the
n
Stops High Voltage Surges
n
Adjustable Output Clamp Voltage
n
Overcurrent Protection
n
Wide Operation Range: 4V to 80V
n
Reverse Input Protection to –60V
n
Low 7µA Shutdown Current
n
Adjustable Latchoff Fault Timer
voltage drop between the V and SNS pins to protect
CC
n
Controls N-channel MOSFET
against overcurrent faults. An internal amplifier limits
the current sense voltage to 50mV. In either fault condi-
tion, a timer is started inversely proportional to MOSFET
stress. If the timer expires, the FLT pin pulls low to warn
of an impending power down. If the condition persists,
the MOSFET is turned off, until the SHDN pin pulls low
momentarily.
n
Shutdown Pin Withstands –60V to 100V
n
Fault Output Indication
n
Auxiliary Amplifier for Level Detection Comparator or
Linear Regulator Controller
Available in 12-Pin 4mm × 3mm DFN,
n
10-Pin MSOP, and 16-Pin SO Packages
The auxiliary amplifier may be used as a voltage detection
comparator or as a linear regulator controller driving an
external PNP pass transistor.
APPLICATIONS
n
Automotive/Avionic Surge Protection
n
Hot Swap/Live Insertion
Back-to-back FETs can be used in lieu of a Schottky diode
for reverse input protection, reducing voltage drop and
power loss. The SHDN input turns off the part, including
the auxiliary amplifier, and reduces the quiescent current
to less than 7µA.
n
High Side Switch for Battery Powered Systems
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
4A, 12V Overvoltage Output Regulator
Overvoltage Protector Regulates Output at
27V During Transient
10mΩ
IRLR2908
V
OUT
V
IN
12V
ꢙ
ꢇꢒꢎD
ꢛ ꢌꢜꢔꢝꢞ
ꢛ ꢋꢁꢁꢂꢎ
ꢔꢁꢆ ꢅꢐꢕꢓꢈ ꢖꢓRꢗꢘ
ꢈꢚR
ꢅ
10Ω
102k
ꢆ
ꢅꢐ
V
SNS GATE OUT
FB
ꢑꢁꢆꢄDꢅꢆ
CC
383k
V
CC
SHDN
ꢀꢑꢆ
ꢀꢑꢆ
4.99k
ꢑꢟꢆ ꢎDꢠꢓꢖꢈꢎꢡꢇꢘ ꢙꢇꢎꢚꢕ
ꢀꢁꢁꢂꢃꢄDꢅꢆ
DC-DC
+
IN
LT4356DE-3
ꢆ
ꢒꢓꢈ
CONVERTER
ꢑꢁꢆꢄDꢅꢆ
100k
EN
SHDN
GND
ꢁNDꢂꢃꢄꢅLTꢀꢆꢂ
A
FLT
FꢀꢁLT
ꢇꢈꢉꢊꢋꢌꢍꢊꢈꢎꢁꢀꢏ
OUT
GND
TMR
43563 TA01
0.1µF
Rev D
For more information www.analog.com
1
LT4356-3
(Notes 1 and 2)
ABSOLUTE MAXIMUM RATINGS
V , SHDN ................................................ –60V to 100V
LT4356H-3......................................... –40°C to 125°C
LT4356MP-3...................................... –55°C to 125°C
Storage Temperature Range
CC
SNS.............................V – 30V or –60V to V + 0.3V
CC
CC
OUT, A , FLT, EN..................................... –0.3V to 80V
OUT
GATE (Note 3) .................................–0.3V to V
+ 10V
DE12 .................................................. –65°C to 125°C
MS, SO .............................................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
OUT
+
FB, TMR, IN ................................................ –0.3V to 6V
+
A
OUT
, EN, FLT, IN .................................................. –3mA
Operating Temperature Range
MS, SO .............................................................300°C
LT4356C-3............................................... 0°C to 70°C
LT4356I-3 ............................................–40°C to 85°C
PIN CONFIGURATION
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢣ
ꢐꢎꢙ ꢗꢊꢒꢚ
ꢀꢑR
ꢟꢠ
ꢄꢡ
ꢌ
ꢐꢓR
ꢔꢕ
ꢀ
ꢁ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀꢁ ꢊꢋ
ꢀꢀ
ꢀꢂ ꢑꢋD
ꢡꢉ
ꢉꢇꢗ ꢏꢘꢌꢙ
ꢍ
ꢎꢏꢐ
ꢡꢉ
ꢈ
ꢁꢢꢀ
ꢅꢆ
ꢇꢈꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀꢑ ꢉꢖR
ꢎꢏꢐ
ꢑꢍꢐꢒ
ꢖꢋꢖ
ꢒ
ꢓ
ꢔ
ꢕ
ꢊꢎD
ꢌꢎ
ꢁꢢꢀ
ꢋꢈꢀꢅ
ꢡꢉ
ꢡꢉ
ꢀꢆ
ꢊꢋꢉꢌ
ꢍꢎꢍ
ꢃ
ꢄ
ꢅ
ꢒꢋ
ꢋꢡD
ꢅꢡ
FLT
ꢏ
SHDN
FLT
ꢐꢐ
ꢖꢍ ꢗꢋꢐꢚꢋꢊꢌ
ꢀꢑꢛꢜꢌꢋD ꢗꢜꢋꢍꢉꢘꢐ ꢖꢍꢇꢗ
ꢗ
SHDN
ꢇꢡꢇ
ꢘꢘ
FLT
ꢃ
SHDN
ꢉꢉ
ꢉ
ꢟ ꢀꢁꢄꢠꢐꢡ θ ꢟ ꢀꢕꢑꢠꢐꢢꢙ
ꢝꢋ
ꢝꢖꢋꢞ
Dꢒ ꢙꢍꢘꢛꢍꢑꢒ
ꢀꢁꢜꢝꢒꢍD ꢞꢇꢟꢟ × ꢆꢟꢟꢠ ꢙꢝꢍꢖꢐꢊꢘ Dꢔꢋ
ꢣ ꢀꢁꢈꢤꢘꢥ θ ꢣ ꢇꢆꢤꢘꢦꢚ
ꢡꢍ
ꢒꢢꢙꢎꢖꢒD ꢙꢍD ꢞꢙꢊꢋ ꢀꢆꢠ ꢙꢘꢕ ꢑꢋD ꢘꢎꢋꢋꢒꢘꢐꢊꢎꢋ ꢎꢙꢐꢊꢎꢋꢍꢝ
ꢇ ꢂꢈꢉꢊꢈꢋꢅ
ꢌꢍꢎꢏꢅꢈD ꢂꢏꢈꢇꢀꢄꢉ ꢇꢁ
ꢓ ꢌꢔꢕꢖꢉꢗ θ ꢓ ꢌꢕꢕꢖꢉꢘꢆ
ꢐ
ꢡꢓꢍꢢ
ꢀ
ꢐꢑꢈꢒ
ꢐꢈ
ORDER INFORMATION
LEAD FREE FINISH
LT4356CDE-3#PBF
LT4356IDE-3#PBF
LT4356HDE-3#PBF
LT4356CMS-3#PBF
LT4356IMS-3#PBF
LT4356HMS-3#PBF
LT4356MPMS-3#PBF
LT4356CS-3#PBF
LT4356IS-3#PBF
TAPE AND REEL
PART MARKING*
43563
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT4356CDE-3#TRPBF
LT4356IDE-3#TRPBF
LT4356HDE-3#TRPBF
LT4356CMS-3#TRPBF
LT4356IMS-3#TRPBF
LT4356HMS-3#TRPBF
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
0°C to 70°C
43563
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
43563
LTFFK
LTFFK
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
0°C to 70°C
LTFFK
10-Lead Plastic MSOP
LT4356MPMS-3#TRPBF LTGGZ
10-Lead Plastic MSOP
LT4356CS-3#TRPBF
LT4356IS-3#TRPBF
LT4356HS-3#TRPBF
LT4356MPS-3#TRPBF
LT4356S-3
16-Lead Plastic SO
LT4356S-3
16-Lead Plastic SO
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
LT4356HS-3#PBF
LT4356MPS-3#PBF
LT4356S-3
16-Lead Plastic SO
LT4356MPS-3
16-Lead Plastic SO
Rev D
2
For more information www.analog.com
LT4356-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
Operating Voltage Range
Supply Current
MIN
TYP
MAX
80
UNITS
V
l
l
V
4
CC
I
V
CC
V
V
= Float
1
1.5
mA
CC
SHDN
+
= 0V, IN = 1.3V
7
7
7
25
30
40
µA
µA
µA
SHDN
l
l
LT4356C, LT4356I
LT4356H, LT4356MP
l
l
I
Reverse Input Current
V
V
= V = –30V, SHDN Open
0.3
0.8
1
2
mA
mA
R
SNS
SNS
CC
= V = V
= –30V
CC
SHDN
l
l
ΔV
GATE Pin Output High Voltage
GATE Pin Pull-Up Current
V
= 4V; (V
– V )
OUT
4.5
10
8
16
V
V
GATE
CC
GATE
80V ≥ V ≥ 8V; (V
– V )
CC
GATE
OUT
l
l
l
I
I
V
V
V
= 12V; V = 12V; LT4356C, LT4356I, LT4356H
= 12V; V = 12V; LT4356MP
= 48V; V = 48V
–4
–4
–4.5
–23
–23
–30
–36
–38
–50
µA
µA
µA
GATE(UP)
GATE
GATE
GATE
CC
CC
CC
l
l
l
GATE Pin Pull-Down Current
FB Pin Servo Voltage
Overvoltage, V = 1.4V, V = 12V
GATE
Overcurrent, V – V
Shutdown Mode, V
75
4
1.5
150
10
5
mA
mA
mA
GATE(DN)
FB
= 120mV, V
= 12V
= 12V
CC
SNS
GATE
= 0V, V
SHDN
GATE
l
l
V
V
V
= 12V, V
= 12V, V
= 12V; LT4356C, LT4356I
= 12V; LT4356H, LT4356MP
1.225
1.215
1.25
1.25
1.275
1.275
V
V
FB
GATE
GATE
OUT
OUT
l
I
FB Pin Input Current
V
= 1.25V
FB
0.3
1
µA
FB
l
l
l
l
l
l
ΔV
SNS
Overcurrent Fault Threshold
ΔV
SNS
ΔV
SNS
ΔV
SNS
ΔV
SNS
ΔV
SNS
ΔV
SNS
= (V – V ), V = 12V; LT4356C, LT4356I
45
42.5
42.5
46
43
43
50
50
50
51
51
51
55
55
56
56
56
57
mV
mV
mV
mV
mV
mV
CC
SNS
CC
= (V – V ), V = 12V; LT4356H
CC
SNS
CC
= (V – V ), V = 12V; LT4356MP
CC
SNS
CC
= (V – V ), V = 48V; LT4356C, LT4356I
CC
SNS
CC
= (V – V ), V = 48V; LT4356H
CC
SNS
CC
= (V – V ), V = 48V; LT4356MP
CC
SNS
CC
l
l
I
I
SNS Pin Input Current
V
= V = 12V to 48V
5
10
22
µA
SNS
SNS
CC
FLT, EN Pins Leakage Current
FLT, EN = 80V
A
2.5
4.5
µA
µA
LEAK
A
OUT
Pin Leakage Current
= 80V
OUT
l
l
l
l
l
I
TMR Pin Pull-up Current
V
TMR
V
TMR
V
TMR
V
TMR
V
TMR
= 1V, V = 1.5V, (V – V ) = 0.5V
–1.5
–44
–3.5
–2.5
–195
–2.5
–50
–5.5
–4.5
–260
–4
–56
–8.5
–6.5
–325
µA
µA
µA
µA
µA
TMR
FB
CC
OUT
= 1V, V = 1.5V, (V – V ) = 75V
FB
CC
OUT
= 1.3V, V = 1.5V, (V – V ) = 75V
FB
CC
OUT
= 1V, ΔV
= 1V, ΔV
= 60mV, (V – V ) = 0.5V
SNS
SNS
CC OUT
= 60mV, (V – V ) = 80V
CC
OUT
l
l
l
l
l
TMR Pin Pull-down Current
TMR Pin Thresholds
V
= 1V, V = 1V, ΔV = 0V
SNS
1.5
1.22
80
2.2
1.25
100
1.25
0.3
2.7
1.28
120
1.28
1
µA
V
TMR
FB
V
FLT From High to Low, V = 5V to 80V
CC
TMR
ΔV
Early Warning Period
From FLT going Low to GATE Going Low, V = 5V to 80V
mV
V
TMR
+
CC
+
V
IN
IN Pin Threshold
1.22
+
+
+
I
IN
IN Pin Input Current
V
= 1.25V
µA
IN
l
l
V
OL
FLT, EN, A
Pins Output Low
I
I
= 2mA
= 0.1mA
2
300
8
800
V
mV
OUT
SINK
SINK
l
l
l
I
OUT Pin Input Current
OUT Pin High Threshold
V
V
V
= V = 12V; LT4356C, LT4356I, LT4356H
200
200
6
300
310
14
µA
µA
mA
OUT
OUT
OUT
OUT
CC
= V = 12V; LT4356MP
CC
= V = 12V, V
= 0V
CC
SHDN
l
ΔV
ΔV
= V – V ; EN From Low to High
0.25
0.5
0.7
V
OUT
OUT
CC
OUT
Rev D
For more information www.analog.com
3
LT4356-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
SHDN Pin Threshold
V
= 12V to 48V
0.6
0.4
1.7
2.1
V
V
SHDN
CC
l
l
l
V
SHDN Pin Resting Voltage
SHDN Pin Current
V
V
= 12V to 48V, Note 4
0.6
–1
2.1
–8
V
SHDN(FLT)
CC
I
t
= 0V
–4
µA
SHDN
SHDN
)
Overcurrent Turn Off Delay Time
GATE From High to Low, ΔV
LT4356I, LT4356H
LT4356MP
= 0 → 120mV; LT4356C,
OFF(OC
SNS
l
l
2
2
4
4.5
µs
µs
l
t
Overvoltage Turn Off Delay Time
GATE From High to Low, V = 0 → 1.5V
0.25
1
µs
OFF(OV)
FB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
the OUT pin. Driving this pin to voltages beyond the clamp may damage
the device.
Note 4: Resting voltage after turn-on.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
ICC vs VCC ICC (Shutdown) vs VCC
ICC (Shutdown) vs Temperature
ꢏꢄꢄꢄ
ꢋꢄꢄ
ꢊꢄꢄ
ꢉꢄꢄ
ꢈꢄꢄ
ꢄ
ꢒꢋ
ꢒꢌ
ꢐꢋ
ꢐꢌ
ꢏꢋ
ꢏꢌ
ꢋ
ꢌꢄ
ꢎꢄ
ꢋꢄ
ꢊꢄ
ꢉꢄ
ꢈꢄ
ꢄ
ꢌ
ꢄ
ꢏꢄ ꢈꢄ ꢌꢄ ꢉꢄ ꢍꢄ ꢊꢄ ꢐꢄ ꢋꢄ
ꢂꢀꢃ
ꢊꢋꢌ ꢊꢐꢋ
ꢌ
ꢐꢋ
ꢋꢌ
ꢕꢋ ꢏꢌꢌ ꢏꢐꢋ
ꢄ
ꢈꢄ ꢉꢄ ꢊꢄ ꢋꢄ ꢎꢄ ꢌꢄ ꢐꢄ ꢍꢄ
ꢂꢀꢃ
ꢀ
ꢁꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢁꢁ
ꢉꢌꢍꢊꢌ ꢎꢄꢈ
ꢑꢒꢋꢓꢒ ꢔꢌꢒ
ꢋꢊꢎꢌꢊ ꢏꢄꢈ
Rev D
4
For more information www.analog.com
LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
GATE Pull-Up Current vs
Temperature
SHDN Current vs Temperature
GATE Pull-Up Current vs VCC
ꢓ
ꢋ
ꢒ
ꢑ
ꢐ
ꢏ
ꢌ
ꢏꢄ
ꢍꢎ
ꢍꢄ
ꢌꢎ
ꢌꢄ
ꢋꢎ
ꢋꢄ
ꢎ
ꢓꢋ
ꢓꢌ
ꢑꢋ
ꢑꢌ
ꢐꢋ
ꢐꢌ
ꢋ
ꢖ
ꢗ ꢌꢖ
ꢖ
ꢗ ꢖ
ꢗ ꢐꢑꢖ
ꢘꢅꢀ
SHDN
ꢎꢄꢀꢁ
ꢄ
ꢌ
ꢊꢋꢌ ꢊꢐꢋ
ꢌ
ꢐꢋ
ꢋꢌ
ꢕꢋ ꢏꢌꢌ ꢏꢐꢋ
ꢄ
ꢋꢄ ꢌꢄ ꢍꢄ ꢏꢄ ꢎꢄ ꢐꢄ ꢒꢄ ꢑꢄ
ꢂꢀꢃ
ꢊꢋꢌ ꢊꢑꢋ
ꢌ
ꢑꢋ
ꢋꢌ
ꢕꢋ ꢐꢌꢌ ꢐꢑꢋ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢁꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢒꢑꢋꢓꢑ ꢔꢌꢒ
ꢏꢍꢎꢐꢍ ꢆꢄꢎ
ꢒꢓꢋꢔꢓ ꢎꢌꢔ
GATE Pull-Down Current vs
Temperature
GATE Pull-Down Current vs
Temperature
ΔVGATE vs IGATE
ꢔꢔꢌ
ꢔꢌꢌ
ꢍꢙꢌ
ꢍꢖꢌ
ꢍꢕꢌ
ꢍꢔꢌ
ꢍꢌꢌ
12
10
8
14
12
10
8
ꢐꢚꢁRꢚꢐꢛꢀꢄꢏꢁ ꢈꢐꢒDꢎꢀꢎꢐꢒ
ꢞ ꢍꢟꢋꢚ
OVERCURRENT CONDITION
∆V = 120mV
V
= 12V
OUT
ꢚ
ꢜꢝ
SNS
6
6
4
4
2
2
0
0
ꢊꢋꢌ ꢊꢔꢋ
ꢌ
ꢔꢋ
ꢋꢌ
ꢘꢋ ꢍꢌꢌ ꢍꢔꢋ
–50 –25
0
25
50
75 100 125
0
2
4
6
8
10 12 14 16
(µA)
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
TEMPERATURE (°C)
I
GATE
ꢕꢗꢋꢖꢗ ꢏꢌꢘ
43563 G08
43563 G09
Overvoltage TMR Current vs
(VCC – VOUT
ΔVGATE vs Temperature
ΔVGATE vs VCC
)
14
12
10
8
16
14
12
10
8
ꢑꢍ
ꢑꢈ
ꢒꢐ
ꢐꢑ
ꢎꢏ
ꢍ
I
= –1µA
ꢃꢀꢖRꢀꢃꢗꢅꢌꢔꢖ ꢁꢃꢘDꢉꢅꢉꢃꢘ
GATE
T
= 130°C
A
ꢀ
ꢀ
ꢙ ꢓꢀ
ꢙ ꢎꢀ
ꢃꢄꢅ
ꢅꢊR
V
CC
= 8V
T
= –45°C
A
T
= 25°C
A
6
6
V
CC
= 4V
4
4
2
2
I
= –1µA
CC
GATE
OUT
V
= V
0
0
ꢈ
–50 –25
0
25
50
75 100 125
0
10 20 30 40 50 60 70 80
(V)
ꢈ
ꢎꢈ ꢐꢈ ꢒꢈ ꢑꢈ ꢓꢈ ꢏꢈ ꢕꢈ ꢍꢈ
ꢂ ꢀ ꢆꢀꢇ
TEMPERATURE (°C)
V
ꢀ
ꢁꢁ
CC
ꢃꢄꢅ
43563 G10
43563 G11
ꢑꢒꢓꢏꢒ ꢔꢎꢐ
Rev D
For more information www.analog.com
5
LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
Warning Period
TMR Current vs VCC
TMR Pull-Down Current vs
Temperature
Overcurrent TMR Current vs
(VCC – VOUT
)
ꢌꢆ
ꢌꢅ
ꢌꢄ
ꢈ
ꢒꢕꢌ
ꢐꢕꢋ
ꢐꢕꢌ
ꢏꢕꢋ
ꢏꢕꢌ
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ꢐꢍꢈ
ꢐꢈꢈ
ꢏꢑꢈ
ꢏꢐꢈ
ꢎꢈ
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ꢘꢒRꢙꢎꢙꢋ ꢚꢔRꢎꢓD
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ꢀꢂR
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ꢅꢊR
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ꢏꢐR
ꢝ ꢌꢞꢊꢀ
ꢝ ꢌꢞꢉꢀ
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ꢀ
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ꢑꢒꢋꢓꢒ ꢔꢏꢋ
ꢍꢒꢓꢑꢒ ꢔꢏꢒ
Overvoltage Turn-Off Time vs
Temperature
Output Low Voltage vs Current
ꢒꢎꢉ
ꢋꢌꢌ
ꢔꢌꢌ
ꢕꢌꢌ
ꢓꢌꢌ
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ꢐꢎꢉ
ꢏꢎꢑ
ꢏꢎꢉ
ꢍꢎꢑ
ꢍꢎꢉ
ꢉꢎꢑ
ꢉ
ꢇ
ꢋꢁꢄ
FLT
ꢂꢃ
ꢉ
ꢉꢎꢑ
ꢍꢎꢉ
ꢍꢎꢑ
ꢏꢎꢉ
ꢏꢎꢑ
ꢐꢎꢉ
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ꢒꢐꢑꢓꢐ ꢔꢍꢓ
ꢔꢕꢋꢖꢕ ꢗꢍꢘ
Overcurrent Turn-Off Time vs
Temperature
Reverse Current vs Reverse
Voltage
ꢈꢑꢄ
ꢈꢉꢊ
ꢈꢉꢄ
ꢈꢊ
4.0
3.5
3.0
2.5
2.0
1.5
1.0
OVERCURRENT CONDITION
∆V = 120mV
ꢀ
ꢁꢁ
ꢒ ꢓꢔꢓ
SNS
ꢄ
ꢈꢌꢄ
–50 –25
0
25
50
75 100 125
ꢄ
ꢈꢑꢄ
ꢈꢎꢄ
ꢈꢋꢄ
TEMPERATURE (°C)
ꢀ
ꢁꢁ
ꢂꢀꢃ
43563 G18
ꢌꢍꢊꢎꢍ ꢏꢉꢐ
Rev D
6
For more information www.analog.com
LT4356-3
PIN FUNCTIONS
the fault timer current. When the OUT pin voltage reaches
A
OUT
(DFNandSOPackagesOnly):AmplifierOutput.Open
0.7V away from V , the EN pin goes high impedance.
collector output of the auxiliary amplifier. It is capable of
sinking up to 2mA from 80V. The negative input of the
amplifier is internally connected to a 1.25V reference.
CC
SHDN: Shutdown Control Input. Pulling the SHDN pin
low shuts the LTC4356-3 down to a low current mode. All
functions, including the GATE and the spare amplifier are
turned off. The SHDN input threshold is similar to a TTL
input. If the SHDN voltage goes below 2.1V, the voltage
must go below 0.4V for 100µs to properly shut down the
part. To turn the part back on, the SHDN voltage must
transitionfrombelow0.4Vtogreaterthan2.1Vwithaslew
rate faster than 10V/ms. An internal 7µA current source
is provided to pull the SHDN pin up. An external pull-up
device should be used if the leakage current to ground
might exceed 1µA. After a fault time-out which turns the
GATE off, the GATE can be restarted by shutting down and
restarting the part. The SHDN pin can be pulled up to 100V
or below GND by 60V without damage.
EN: Open-Collector Enable Output. The EN pin goes high
impedance when the voltage at the OUT pin is above (V
– 0.7V), indicating the external MOSFET is fully on. The
state of the pin is latched until the OUT pin voltage resets
at below 0.5V and goes back up above 2V. The internal
NPN is capable of sinking up to 3mA of current from 80V
to drive an LED or opto-coupler.
CC
Exposed Pad: Exposed pad may be left open or connected
to device ground (GND).
FB: Voltage Regulator Feedback Input. Connect this pin
to the center tap of the output resistive divider connected
between the OUT pin and ground. During an overvoltage
condition, the GATE pin is servoed to maintain a 1.25V
threshold at the FB pin. This pin is clamped internally to
7V. Tie to GND to disable the OV clamp.
SNS:CurrentSenseInput.Connectthispintotheoutputof
thecurrentsenseresistor.Thecurrentlimitcircuitcontrols
the GATE pin to limit the sense voltage between V and
CC
FLT: Open-Collector Fault Output. This pin pulls low
after the voltage at the TMR pin has reached the fault
threshold of 1.25V. It indicates the pass transistor is
about to turn off because either the supply voltage has
stayed at an elevated level for an extended period of
time (voltage fault) or the device is in an overcurrent
condition (current fault). The internal NPN is capable of
sinking up to 3mA of current from 80V to drive an LED or
opto-coupler.
SNS pins to 50mV. At the same time the sense amplifier
also starts a current source to charge up the TMR pin.
This pin can be pulled below GND by up to 60V, though
the voltage difference with the V pin must be limited to
CC
less than 30V. Connect to V if unused.
CC
TMR: Fault Timer Input. Connect a capacitor between this
pin and ground to set the times for early warning and fault
periods. The current charging up this pin during fault
conditions depends on the voltage difference between the
GATE: N-Channel MOSFET Gate Drive Output. The GATE
pin is pulled up by an internal charge pump current source
and clamped to 14V above the OUT pin. Both voltage and
current amplifiers control the GATE pin to regulate the
output voltage and limit the current through the MOSFET.
V
and OUT pins. When V
reaches 1.25V, the FLT pin
CC
TMR
pulls low to indicate the detection of a fault condition. If
the condition persists, the pass transistor turns off when
V
TMR
reachesthethresholdof1.35V.TheGATEpinremains
low even after the fault condition has disappeared and the
voltage at the TMR pin has reached 0.5V. A minimum of
10nF capacitor is needed to compensate the loop. A 10V
GND: Device Ground.
+
IN (DFN and SO Packages Only): Positive Input of the
rated X7R capacitor is recommended for C
.
TMR
Auxiliary Amplifier. This amplifier can be used as a level
detection comparator with external hysteresis or linear
regulator controlling an external PNP transistor. This pin
is clamped internally to 7V. Connect to ground if unused.
V : Positive Supply Voltage Input. The positive supply
CC
input ranges from 4V to 80V for normal operation. It
can also be pulled below ground potential by up to 60V
during a reverse battery condition, without damaging the
part. The supply current is reduced to 7µA with all the
OUT: Output Voltage Sense Input. This pin senses the
voltage at the source of the N-channel MOSFET and sets
functional blocks off.
Rev D
For more information www.analog.com
7
LT4356-3
BLOCK DIAGRAM
ꢂ
ꢃꢃ
ꢗꢅꢗ
ꢙꢆꢘꢎ
ꢛꢇꢘ
ꢃꢞꢆRꢙꢎ
ꢌꢇꢋꢌ
ꢟ ꢠ ꢑꢒꢓꢡꢞꢢ
ꢏꢚꢂ
ꢁ
ꢒꢓꢔꢂ
ꢑꢓꢕꢆ
ꢀ
ꢁ
ꢍꢝ
ꢁ
ꢀ
ꢀ
ꢂ
ꢃꢃ
ꢂꢆ
ꢄꢆ
ꢏꢐꢑꢒꢂ
ꢣꢕꢆ
SHDN
FLT
ꢆ
ꢛꢇꢘ
ꢛꢃ
ꢛꢇꢘ
ꢛꢂ
ꢀ
ꢏꢐꢑꢒꢂ
SHDN
ꢎꢅ
ꢃꢛꢅꢘRꢛꢉ
ꢉꢛꢙꢄꢃ
ꢆꢇꢈꢄꢉꢄꢆRꢊ
ꢆꢋꢌꢉꢄꢍꢄꢎR
ꢁ
ꢙꢆꢘꢎꢛꢍꢍ ꢍꢉꢘ
ꢁ
ꢄꢅ
ꢏꢐꢖꢒꢂ
ꢀ
ꢁ
ꢂ
ꢃꢃ
ꢁ
ꢀ
ꢓꢐꢒꢂ
ꢄ
ꢘꢋR
ꢁ
ꢀ
ꢑꢕꢆ
ꢏꢐꢑꢒꢂ
ꢘꢋR
ꢙꢅD
ꢚꢖꢒꢜꢖ ꢝD
Rev D
8
For more information www.analog.com
LT4356-3
OPERATION
Some power systems must cope with high voltage surges
of short duration such as those in automobiles. Load
circuitry must be protected from these transients, yet
high availability systems must continue operating during
these events.
the part for more than 100µs before powering it back up,
or second, pull the SHDN below 0.4V for more than 100µs
then pull SHDN high with a slew rate higher than 10V/ms.
The potential at the TMR pin starts decreasing as soon
as the output voltage is not being servoed, indicating the
overvoltage condition has disappeared, but the GATE
pin remains low even when the voltage at the TMR pin
reaches 0.5V.
The LT4356-3 is an overvoltage protection regulator that
drives an external N-channel MOSFET as the pass transis-
tor. It operates from a wide supply voltage range of 4V to
80V. It can also be pulled below ground potential by up
to 60V without damage. The low power supply require-
ment of 4V allows it to operate even during cold cranking
conditionsinautomotiveapplications. Theinternalcharge
pump turns on the N-channel MOSFET to supply current
to the loads with very little power loss. Two MOSFETs can
be connected back to back to replace an inline Schottky
diode for reverse input protection. This improves the ef-
ficiency and increases the available supply voltage level
to the load circuitry during cold crank.
The fault timer allows the load to continue functioning
duringshorttransienteventswhileprotectingtheMOSFET
from being damaged by a long period of supply overvolt-
age, such as a load dump in automobiles. The timerperiod
varieswiththevoltageacrosstheMOSFET.Ahighervoltage
corresponds to a shorter fault timer period, ensuring the
MOSFET operates within its safe operating area (SOA).
TheLT4356-3sensesanovercurrentconditionbymonitor-
ing the voltage across an optional sense resistor placed
between the V and SNS pins. An active current limit
CC
Normally, the pass transistor is fully on, powering the
loads with very little voltage drop. When the supply volt-
age surges too high, the voltage amplifier (VA) controls
the gate of the MOSFET and regulates the voltage at the
source pin to a level that is set by the external resistive
divider from the OUT pin to ground and the internal 1.25V
reference. A current source starts charging up the capaci-
tor connected at the TMR pin to ground. If the voltage at
circuit (IA) controls the GATE pin to limit the sense volt-
age to 50mV. A current is also generated to start charging
up the TMR pin. This current is about 5 times the current
generated during an overvoltage event. The FLT pin pulls
low when the voltage at the TMR pin reaches 1.25V and
the MOSFET is turned off when it reaches 1.35V.
An auxiliary amplifier is provided with the negative input
connected to an internal 1.25V reference. The output pull
down device is capable of sinking up to 2mA of current
allowing it to drive an LED or opto coupler. This amplifier
can be configured as a linear regulator controller driving
an external PNP transistor or a comparator function to
monitor voltages.
the TMR pin, V
, reaches 1.25V, the FLT pin pulls low
TMR
to indicate impending turn-off due to the overvoltage
condition. The pass transistor stays on until the TMR
pin reaches 1.35V, at which point the GATE pin pulls low
turning off the MOSFET. The GATE pin stays latched off
until it is cleared by one of two ways. First, power down
The SHDN pin turns off the pass transistor and reduces
the supply current to less than 7µA.
Rev D
For more information www.analog.com
9
LT4356-3
APPLICATIONS INFORMATION
The LT4356-3 can limit the voltage and current to the load
circuitry during supply transients or overcurrent events.
The total fault timer period should be set to ride through
short overvoltage transients while not causing damage
to the pass transistor. The selection of this N-channel
MOSFET pass transistor is critical for this application.
It must stay on and provide a low impedance path from
the input supply to the load during normal operation and
then dissipate power during overvoltage or overcurrent
conditions.
Overcurrent Fault
The LT4356-3 features an adjustable current limit that
protects against short circuits or excessive load current.
During an overcurrent event, the GATE pin is regulated to
limit the current sense voltage across the V and SNS
pins to 50mV.
CC
Anovercurrentfaultoccurswhenthecurrentlimitcircuitry
has been engaged for longer than the time-out delay set
by the timer capacitor. The GATE pin is then immediately
pulled low by a 10mA current to GND turning off the
MOSFET. The GATE pin stays low until the SHDN pin is
pulled low for at least 100µs and pulled high with a slew
rate faster than 10V/ms.
The following sections describe the overcurrent and the
overvoltage faults, and the selection of the timer capacitor
value based on the required warning time. The selection
of the N-channel MOSFET pass transistor is discussed
next. Auxiliary amplifier, reverse input, and the shutdown
functionsarecoveredaftertheMOSFETselection.External
component selection is discussed in detail in the Design
Example section.
Fault Timer
The LT4356-3 includes an adjustable fault timer pin. Con-
necting a capacitor from the TMR pin to ground sets the
delay timer period before the MOSFET is turned off. The
same capacitor also sets the cool down period before the
MOSFETisallowedtoturnbackonafterthefaultcondition
has disappeared.
Overvoltage Fault
The LT4356-3 limits the voltage at the OUT pin during an
overvoltage situation. An internal voltage amplifier regu-
lates the GATE pin voltage to maintain a 1.25V threshold at
the FB pin. During this period of time, the power MOSFET
is still on and continues to supply current to the load. This
allows uninterrupted operation during short overvoltage
transient events.
Once a fault condition, either overvoltage or overcurrent,
is detected, a current source charges up the TMR pin. The
current level varies depending on the voltage drop across
thedrainandsourceterminalsofthepowerMOSFET(V ),
which is typically from the V pin to the OUT pin. This
scheme takes better advantage of the available Safe Oper-
ating Area (SOA) of the MOSFET than would a fixed timer
current. The timer function operates down to V = 5V
across the whole temperature range.
DS
CC
When the voltage regulation loop is engaged for longer
than the time-out period, set by the timer capacitor con-
nected from the TMR pin to ground, an overvoltage fault
is detected. The GATE pin is pulled down to the OUT pin by
a 150mA current. This prevents the power MOSFET from
being damaged during a long period of overvoltage, such
as during load dump in automobiles. Pulling the SHDN
pin low for at least 100µs and pulled high with a slew rate
faster than 10V/ms will allow the GATE pin to pull back up.
CC
Rev D
10
For more information www.analog.com
LT4356-3
APPLICATIONS INFORMATION
Fault Timer Current
When the voltage at the TMR pin, V
, reaches the 1.25V
TMR
threshold, the FLT pin pulls low to indicate the detection
of a fault condition and provide warning to the load of
the impending power loss. In the case of an overvoltage
fault, the timer current then switches to a fixed 5µA. The
interval between FLT asserting low and the MOSFET turn-
ing off is given by:
The timer current starts at around 2µA with 0.5V or less
of V , increasing linearly to 50µA with 75V of V dur-
DS
DS
ing an overvoltage fault (Figure 1). During an overcurrent
fault, it starts at 4µA with 0.5V or less of V but increases
DS
to 260µA with 80V across the MOSFET (Figure 2). This
arrangement allows the pass transistor to turn off faster
duringanovercurrentevent,sincemorepowerisdissipated
during this condition. Refer to the Typical Performance
Characteristics section for the timer current at different
C
• 100mV
5µA
TMR
t
=
WARNING
V
in both overvoltage and overcurrent events.
DS
ꢛ
ꢃꢏRꢜꢛꢝ
ꢎ
ꢄ ꢆꢊꢌ
ꢎ
ꢄ ꢆꢊꢌ
ꢃꢏR
ꢃꢏR
ꢅꢙꢘꢆ
ꢅꢙꢕꢆ
ꢛ
ꢃꢏR
ꢄ ꢚꢆꢛ
ꢄ ꢆꢖꢊꢌꢝ
Dꢞ
ꢜꢎ
ꢛ
ꢃꢏR
ꢄ ꢅꢖꢛ
ꢄ ꢟꢊꢌꢝ
Dꢞ
ꢜꢎ
ꢖꢙꢆꢖ
ꢃꢎꢏꢐ
ꢀ
ꢀ
ꢒꢌRꢓꢎꢓꢔ
ꢄ ꢕꢖꢇꢈꢉꢊꢁ
ꢁꢂꢃ
ꢄ ꢅꢆꢇꢈꢉꢊꢁ
ꢀ
ꢄ ꢗꢘꢙꢚꢆꢇꢈꢉꢊꢁ
ꢀ
ꢒꢌRꢓꢎꢓꢔ
ꢄ ꢕꢖꢇꢈꢉꢊꢁ
ꢁꢂꢃ
ꢃꢋꢃꢌꢂ ꢁꢌꢍꢂꢃ ꢃꢎꢏꢐR ꢄ ꢀ ꢑ ꢀ
ꢠꢘꢆꢡꢘ ꢁꢖꢅ
ꢁꢂꢃ ꢒꢌRꢓꢎꢓꢔ
Figure 1. Overvoltage Fault Timer Current
ꢛ
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ꢖꢆꢘꢟ
ꢖꢆꢅꢟ
ꢛ
ꢃꢐR
ꢄ ꢇꢚꢛ
Dꢞ
ꢛ
ꢃꢐR
ꢄ ꢖꢚꢛ
ꢄ ꢘꢟꢋꢍꢝ
ꢜꢏ
ꢄ ꢅꢙꢚꢋꢍꢝ
Dꢞ
ꢜꢏ
ꢚꢆꢟꢚ
ꢃꢏꢐꢑ
ꢀ
ꢓꢍRꢔꢏꢔꢕ
ꢄ ꢚꢆꢘꢇꢈꢉꢊꢋꢁ
ꢀ
ꢁꢂꢃ
ꢄ ꢅꢆꢇꢇꢈꢉꢊꢋꢁ
ꢀ
ꢄ ꢅꢖꢆꢗꢘꢈꢉꢊꢋꢁ
ꢁꢂꢃ
ꢀ
ꢓꢍRꢔꢏꢔꢕ
ꢗꢘꢟꢙꢘ ꢁꢚꢅ
ꢄ ꢅꢆꢇꢙꢈꢉꢊꢋꢁ
ꢃꢌꢃꢍꢂ ꢁꢍꢎꢂꢃ ꢃꢏꢐꢑR ꢄ ꢀ ꢒ ꢀ
ꢁꢂꢃ ꢓꢍRꢔꢏꢔꢕ
Figure 2. Overcurrent Fault Timer Current
Rev D
For more information www.analog.com
11
LT4356-3
APPLICATIONS INFORMATION
The SOA of the MOSFET must encompass all fault condi-
tions. In normal operation the pass transistor is fully on,
dissipating very little power. But during either overvoltage
or overcurrent faults, the GATE pin is servoed to regu-
late either the output voltage or the current through the
MOSFET. Large current and high voltage drop across the
MOSFET can coexist in these cases. The SOA curves of
the MOSFET must be considered carefully along with the
selection of the fault timer capacitor.
This fixed early warning period allows time for the system
to perform necessary backup or house-keeping functions
before power is cut off. When V
crosses the 1.35V
TMR
threshold, the GATE pin pulls low immediately and turns
off the MOSFET. Note that during an overcurrent event the
timer current is not reduced to 5µA when V
reaches
TMR
1.25V,sinceitwouldlengthentheoverallfaulttimerperiod
and cause additional MOSFET stress. After the GATE pin
pulls low due to a fault time out, the LT4356-3 latches off.
Allow sufficient time for the TMR pin to discharge to 0.5V
(typical discharge current is 2.2µA) and for the MOSFET
to cool before attempting to reset the part. To reset, pull
the SHDN pin low for at least 100µs, then pull high with
a slew rate of at least 10V/ms.
Transient Stress in the MOSFET
During an overvoltage event, the LT4356-3 drives a series
passMOSFETtoregulatetheoutputvoltageatanacceptable
level.Theloadcircuitrymaycontinueoperatingthroughout
this interval, but only at the expense of dissipation in the
MOSFET pass device. MOSFET dissipation or stress is a
function of the input voltage waveform, regulation voltage
and load current. The MOSFET must be sized to survive
this stress.
MOSFET Selection
TheLT4356-3drivesanN-channelMOSFETtoconductthe
load current. The important features of the MOSFET are
on-resistanceR
(BR)DSS
,themaximumdrain-sourcevoltage
DS(ON)
V
, the threshold voltage, and the SOA.
Most transient event specifications use the model shown
in Figure 3. The idealized waveform comprises a linear
The maximum allowable drain-source voltage must be
higher than the supply voltage. If the output is shorted
to ground or during an overvoltage event, the full supply
voltage will appear across the MOSFET.
ramp of rise time t , reaching a peak voltage of V and
r
PK
exponentially decaying back to V with a time constant
IN
of t. A common automotive transient specification has
constants of t = 10µs, V = 80V and t = 1ms. A surge
r
PK
The gate drive for the MOSFET is guaranteed to be more
conditionknownas“loaddump”hasconstantsoft = 5ms,
r
than10Vandlessthan16VforthoseapplicationswithV
CC
V
PK
= 60V and t = 200ms.
higher than 8V. This allows the use of standard threshold
voltage N-channel MOSFETs. For systems with V less
CC
than 8V, a logic level MOSFET is required since the gate
drive can be as low as 4.5V.
ꢀ
ꢁꢂ
τ
ꢀ
ꢃꢄ
ꢋ
ꢌ
ꢅꢆꢇꢈꢆ ꢉꢊꢆ
Figure 3. Prototypical Transient Waveform
Rev D
12
For more information www.analog.com
LT4356-3
APPLICATIONS INFORMATION
ꢀ
MOSFET stress is the result of power dissipated within
the device. For long duration surges of 100ms or more,
stress is increasingly dominated by heat transfer; this is
a matter of device packaging and mounting, and heat sink
thermal mass. This is analyzed by simulation, using the
MOSFET thermal model.
ꢁꢂ
τ
ꢀ
Rꢋꢌ
ꢀ
ꢃꢄ
ꢍ
ꢎ
Forshortdurationtransientsoflessthan100ms, MOSFET
survival is increasingly a matter of safe operating area
(SOA), an intrinsic property of the MOSFET. SOA quanti-
ꢅꢆꢇꢈꢆ ꢉꢊꢅ
Figure 4. Safe Operating Area Required to Survive Prototypical
Transient Waveform
fies the time required at any given condition of V and
DS
I to raise the junction temperature of the MOSFET to its
D
Typically V
≈ V and t >> t simplifying the above to
IN r
REG
rated maximum. MOSFET SOA is expressed in units of
2
watt-squared-seconds(P t).Thisfigureisessentiallycon-
1
P2t = ILOAD2 (VPK – VREG)2 τ
(W2s)
stant for intervals of less than 100ms for any given device
type, and rises to infinity under DC operating conditions.
Destruction mechanisms other than bulk die temperature
2
For the transient conditions of V = 80V, V = 12V, V
REG
PK
IN
= 16V, t = 10µs and t = 1ms, and a load current of 3A,
distort the lines of an accurately drawn SOA graph so that
r
2
2
2
P t is 18.4W s—easily handled by a MOSFET in a D-pak
P t is not the same for all combinations of I and V .
D
DS
2
2
package.TheP tofothertransientwaveshapesisevaluated
In particular P t tends to degrade as V approaches the
DS
by integrating the square of MOSFET power versus time.
maximum rating, rendering some devices useless for
absorbing energy above a certain voltage.
Calculating Short-Circuit Stress
Calculating Transient Stress
SOAstressmustalsobecalculatedforshort-circuitcondi-
2
tions. Short-circuit P t is given by:
To select a MOSFET suitable for any given application, the
SOA stress must be calculated for each input transient
whichshallnotinterruptoperation.Itisthenasimplematter
to chose a device which has adequate SOA to survive the
maximumcalculatedstress.P tforaprototypicaltransient
waveform is calculated as follows (Figure 4).
2
2
2
P t = (V • ΔV /R ) • t
(W s)
IN
SNS SNS
TMR
where, ΔV
is the SENSE pin threshold, and t
is the
TMR
SNS
2
overcurrent timer interval.
For V = 14.7V, V
= 50mV, R
= 12mΩ and C
SNS TMR
IN
SNS
2
2
= 100nF, P t is 6.6W s—less than the transient SOA
calculated in the previous example. Nevertheless, to
accountforcircuittolerancesthisfigureshouldbedoubled
Let
a = V
– V
IN
IN
REG
b = V – V
2
PK
to 13.2W s.
(V = Nominal Input Voltage)
IN
Limiting Inrush Current and GATE Pin Compensation
Then
The LT4356-3 limits the inrush current to any load capaci-
tance by controlling the GATE pin voltage slew rate. An
external capacitor can be connected from GATE to ground
to slow down the inrush current further at the expense of
slower turn-off time. The gate capacitor is set at:
1 (b a)3
tr
2
P2t=ILOAD
+
3
b
1
2
b
2a2 ln +3a2 +b2 4ab
a
I
GATE(UP)
C1 =
•C
L
I
INRUSH
Rev D
For more information www.analog.com
13
LT4356-3
APPLICATIONS INFORMATION
R
LIM
The LT4356-3 does not need extra compensation compo-
nents at the GATE pin for stability during an overvoltage
or overcurrent event. However, with fast, high voltage
transientstepsattheinput, agatecapacitor, C1, toground
is needed to prevent turn-on of the N-channel MOSFET.
2N2905A OR
BCP53
*4.7Ω
2.5V OUTPUT
≈ 150mA MAX
INPUT
10µF
R6
100k
*OPTIONAL FOR
CURRENT LIMIT
D1*
BAV99
R4 + R5
R5
11
V
I
= 1.25
0.7
OUT
The extra gate capacitance slows down the turn off time
during fault conditions and may allow excessive current
during an output short event. An extra resistor, R1, in
series with the gate capacitor can improve the turn off
time. A diode, D1, should be placed across R1 with the
cathode connected to C1 as shown in Figure 5.
R4
A
OUT
47nF
249k
≈
LT4356DE-3
LIM
R
12
LIM
+
IN
R5
249k
43563 F06
Figure 6. Auxiliary LDO Output with Optional Current Limit
ꢎꢁ
tions. This diode causes extra power loss, generates heat,
and reduces the available supply voltage range. During
cold crank, the extra voltage drop across the diode is
particularly undesirable.
Dꢁ
ꢏꢐꢃꢁꢃꢑꢒ
Rꢂ
Rꢁ
ꢀꢁ
The LT4356-3 is designed to withstand reverse voltage
ꢋꢌꢉꢍ
without damage to itself or the load. The V , SNS, and
CC
SHDN pins can withstand up to 60V of DC voltage below
the GND potential. Back-to-back MOSFETs must be used
to eliminate the current path through their body diodes
(Figure 7). Figure 8 shows the approach with a P-Channel
MOSFET in place of Q2.
ꢈꢉꢃꢂꢄꢅꢊꢂ
ꢃꢂꢄꢅꢂ ꢆꢇꢄ
Figure 5.
Auxiliary Amplifier
An uncommitted amplifier is included in the LT4356-3 to
provide flexibility in the system design. With the negative
input connected internally to the 1.25V reference, the
amplifier can be connected as a level detect comparator
with external hysteresis. The open collector output pin,
R
M2
M1
SNS
10mΩ
IRLR2908
IRLR2908
V
V
OUT
IN
12V
12V, 3A
CLAMPED
AT 16V
D2*
SMAJ58CA
R4
10Ω
R3
R5
Q3
2N3904
10Ω
1M
R1
59k
A
, is capable of driving an opto or LED. It can also
OUT
D1
interface with the system via a pull-up resistor to a supply
voltage up to 80V.
R7
1N4148
10k
5
4
3
SNS
GATE OUT
FB
The amplifier can also be configured as a low dropout
linearregulatorcontroller.WithanexternalPNPtransistor,
such as 2N2905A, it can supply up to 100mA of current
with only a few hundred mV of dropout voltage. Current
limit can be easily included by adding two diodes and one
resistor (Figure 6). The amplifier is turned off when the
LT4356-3 is shut down.
6
2
V
CC
R2
4.99k
LT4356DE-3
7
11
12
SHDN
8
9
A
OUT
FLT
+
IN
EN
43563 F07
GND
10
TMR
1
C
TMR
0.1µF
*DIODES INC.
Reverse Input Protection
A blocking diode is commonly employed when reverse
input potential is possible, such as in automotive applica-
Figure 7. Overvoltage Regulator with N-channel MOSFET
Reverse Input Protection
Rev D
14
For more information www.analog.com
LT4356-3
APPLICATIONS INFORMATION
R
Shutdown
M2
Si4435
M1
IRLR2908
SNS
10mΩ
V
V
OUT
IN
12V
D2*
SMAJ58CA
12V, 3A
CLAMPED
AT 16V
The LT4356-3 can be shut down to a low current mode
whenthevoltageattheSHDNpingoesbelowtheshutdown
threshold of 0.4V. The quiescent current drops to 7µA. All
functions are turned off including the auxiliary amplifier.
D1
1N5245
15V
R3
R6
10k
R1
59k
10Ω
5
4
3
After the GATE pin pulls low due to a fault time out, the
LT4356-3 latches off. Allow sufficient time for the TMR
pin to discharge to 0.5V (typical discharge current is
2.2µA) and for the MOSFET to cool before attempting to
reset the part. To reset, pull the SHDN pin low for at least
100µs, then pull high with a slew rate of at least 10V/ms.
SNS
GATE OUT
6
2
V
FB
CC
R2
4.99k
LT4356DE-3
7
11
12
SHDN
8
9
A
FLT
OUT
The SHDN pin can be pulled up to V or below GND by
CC
+
IN
EN
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn
on the part while clamping the pin to 2.5V. The leakage
current at the pin should be limited to no more than 1µA
if no pull up device is used to help turn it on.
GND
10
TMR
1
43563 F08
C
TMR
0.1µF
*DIODES INC.
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
Supply Transient Protection
R
M1
SNS
The LT4356-3 is 100% tested and guaranteed to be safe
fromdamagewithsupplyvoltagesupto80V.Nevertheless,
voltagetransientsabove100Vmaycausepermanentdam-
age. During a short-circuit condition, the large change in
currentflowingthroughpowersupplytracesandassociated
wiring can cause inductive voltage transients which could
exceed100V.Tominimizethevoltagetransients,thepower
trace parasitic inductance should be minimized by using
wide traces. A small surge suppressor, D2, in Figure 9,
at the input will clamp the voltage spikes.
10mΩ
IRLR2908
V
IN
C *
L
D2
SMAJ58A
22µF
R3
10Ω
4
R1
59k
5
3
SNS GATE OUT
6
V
CC
2
FB
R4
383k
7
V
CC
SHDN
R2
4.99k
12
DC-DC
CONVERTER
+
IN
LT4356DE-3
R5
100k
9
8
EN
SHDN
GND
A total bulk capacitance of at least 22µF low ESR is re-
quired close to the source pin of MOSFET Q1. In addition,
the bulk capacitance should be at least 10 times larger
than the total ceramic bypassing capacitor on the input
of the DC/DC converter.
11
ꢁNDꢂꢃꢄꢅLTꢀꢆꢂ
A
OUT
FLT
FꢀꢁLT
GND
10
TMR
43563 F09
1
*SANYO 25CE22GA
C
47nF
TMR
Figure 9. Overvoltage Regulator with Low-Battery Detection
Rev D
For more information www.analog.com
15
LT4356-3
APPLICATIONS INFORMATION
Layout Considerations
1.25V
R2 =
= 5kΩ
To achieve accurate current sensing, Kelvin connection
to the current sense resistor (R
250µA
in Figure 9) is recom-
SNS
Choose 4.99kΩ for R2.
16V – 1.25V • R2
mended. The minimum trace width for 1oz copper foil is
0.02" per amp to ensure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530µΩ/square.Smallresistancescancauselargeerrorsin
highcurrentapplications.Noiseimmunitywillbeimproved
significantly by locating resistive dividers close to the pins
(
)
R1 =
= 58.88kΩ
1.25V
The closest standard value for R1 is 59kΩ.
Next calculate the sense resistor, R , value:
SNS
with short V and GND traces.
CC
50mV
50mV
5A
R
=
=
= 10mΩ
SNS
I
LIM
Design Example
As a design example, take an application with the follow-
C
is then chosen for 1ms of early warning time:
TMR
ing specifications: V = 8V to 14V DC with transient up
CC
1ms • 5µA
to 80V, V
≤ 16V, current limit (I ) at 5A, low battery
C
=
= 50nF
OUT
LIM
TMR
100mV
detection at 6V, and 1ms of overvoltage early warning
(Figure 9).
The closest standard value for C
is 47nF.
TMR
First, calculate the resistive divider value to limit V
16V during an overvoltage event:
to
OUT
Finally, calculate R4 and R5 for the 6V low battery thresh-
old detection:
1.25V • R1 + R2
(
)
1.25V • R4 + R5
(
)
V
=
= 16V
REG
6V =
R2
R5
Set the current through R1 and R2 during the overvoltage
condition to 250µA.
Choose 100kΩ for R5.
6V – 1.25V • R5
(
)
R4 =
= 380kΩ
1.25V
Select 383kΩ for R4.
The pass transistor, Q1, should be chosen to withstand
the output short condition with V = 14V.
CC
The total overcurrent fault time is:
47nF • 0.85V
t
=
= 0.878ms
OC
45.5µA
The power dissipation on Q1 equals to:
14V • 50mV
P =
= 70W
10mΩ
These conditions are well within the Safe Operating Area
of IRLR2908.
Rev D
16
For more information www.analog.com
LT4356-3
TYPICAL APPLICATIONS
Wide Input Range 5V to 28V Hot Swap with Undervoltage Lockout
24V Overvoltage Regulator Withstands 150V at VIN
R
M1
M1
SNS
0.02Ω
IRF640
SUD50N03-10
V
V
OUT
CLAMPED AT 32V
IN
V
V
OUT
IN
24V
R9
1k
1W
R1
118k
100µF
R6
118k
R3
10Ω
R3
10Ω
5
SNS
4
3
OUT
C1
47nF
V
SNS GATE OUT
FB
GATE
CC
6
2
SHDN
V
CC
FB
D2*
R2
4.99k
A
OUT
+
SMAT70A
IN
LT4356DE-3
LT4356DE-3
7
8
9
R7
49.9k
SHDN
FLT
FLT
EN
GND
TMR
43563 TA02
EN
GND
10
TMR
1
C
TMR
43563 TA03
1µF
C
TMR
0.1µF
*DIODES INC.
Overvoltage Regulator with Low Battery Detection and Output Keep Alive During Shutdown
1k
0.5W
R
SNS
M1
IRLR2908
V
10mΩ
OUT
V
IN
12V, 4A
12V
CLAMPED AT 16V
D2*
SMAJ58A
R3
D1
10Ω
M2
1N4746A
18V
VN2222
R4
402k
1W
5
SNS
4
3
OUT
R1
294k
GATE
6
V
2
CC
FB
R2
24.9k
V
DD
R6
LT4356DE-3
47k
12
7
11
8
+
IN
A
Lꢀꢁ
THRESHOLD = 6V
OUT
R5
105k
SHDN
FLT
9
EN
GND
10
TMR
1
*DIODES INC.
43563 TA04
C
TMR
0.1µF
Rev D
For more information www.analog.com
17
LT4356-3
TYPICAL APPLICATIONS
2.5A, 48V Hot Swap with Overvoltage Output Regulation at 72V and UV Shutdown at 35V
R
M1
FDB3632
SNS
15mΩ
V
V
OUT
IN
48V
48V
2.5A
R4
140k
R6
100k
D2*
SMAT70A
R3
10Ω
C
L
300µF
C1
6.8nF
6
5
4
3
OUT
D1
1N4714
BV = 33V
V
SNS GATE
R7
CC
1M
12
2
+
IN
7
SHDN
R5
4.02k
R8
47k
R1
226k
LT4356DE-3
FB
R2
4.02k
8
9
FLT
11
EN
A
PWRGD
OUT
GND
10
TMR
1
*DIODES INC.
43563 TA05
C
TMR
0.1µF
2.5A, 28V Hot Swap with Overvoltage Output Regulation at 36V and UV Shutdown at 15V
R
M1
FDB3632
SNS
15mΩ
V
V
OUT
IN
28V
28V
2.5A
R4
113k
R6
27k
D2*
SMAT70A
R3
10Ω
C
L
300µF
C1
6.8nF
6
5
4
3
OUT
D1
1N4700
BV = 13V
V
SNS GATE
R7
CC
1M
12
2
+
IN
7
SHDN
R5
4.02k
R8
47k
R1
110k
LT4356DE-3
FB
R2
4.02k
8
9
FLT
11
EN
A
PWRGD
OUT
GND
10
TMR
1
*DIODES INC.
43563 TA06
C
TMR
0.1µF
Rev D
18
For more information www.analog.com
LT4356-3
TYPICAL APPLICATIONS
Overvoltage Regulator with Reverse Input Protection Up to –80V
R
M2
IRLR2908
M1
IRLR2908
SNS
10mΩ
V
V
OUT
IN
12V
12V, 3A
CLAMPED
AT 16V
D2*
SMAJ58CA
R4
10Ω
R3
10Ω
R5
1M
Q1
2N3904
6
5
SNS
4
3
R1
59k
V
GATE OUT
FB
CC
D1
1N4148
2
R7
10k
R2
4.99k
D3**
1N4148
LT4356DE-3
7
SHDN
11
12
8
9
A
FLT
OUT
+
IN
EN
43563 TA07
GND
10
TMR
1
*DIODES INC.
C
TMR
**OPTIONAL COMPONENT
0.1µF
FOR REDUCED STANDBY CURRENT
250mA High Voltage Low Dropout Linear Regulator
R
M1
SNS
0.2Ω
PSMNAR8 –100BSE
V
V
OUT
16V/250mA
IN
20V
100µF
R3
10Ω
R1
59k
5
4
3
SNS
GATE
OUT
6
2
V
CC
FB
R2
4.99k
LT4356DE-3
7
8
9
SHDN
FLT
*THE OUTPUT LOAD STEP
RESPONSE IS SLOW DUE TO
THE RESPONSE TIME OF THE
INTERNAL CHARGE PUMP
EN
GND
10
TMR
1
43563 TA08
R3
7.5k
Rev D
For more information www.analog.com
19
LT4356-3
PACKAGE DESCRIPTION
DEꢀUE Package
12-Lead Plastic DFN (4mm × 3mm)
ꢄReꢫeꢬeꢭꢮe ꢚꢍꢗ Dꢐꢑ ꢯ ꢂꢡꢜꢂꢪꢜꢃꢤꢝꢡ Rev Dꢉ
ꢂꢁꢦꢂ ±ꢂꢁꢂꢡ
ꢊꢁꢊꢂ ±ꢂꢁꢂꢡ
ꢊꢁꢤꢂ ±ꢂꢁꢂꢡ
ꢅꢁꢅꢂ ±ꢂꢁꢂꢡ
ꢃꢁꢦꢂ ±ꢂꢁꢂꢡ
ꢒꢏꢗꢘꢏꢑꢈ ꢌꢙꢍꢚꢇꢋꢈ
ꢂꢁꢅꢡ ±ꢂꢁꢂꢡ
ꢂꢁꢡꢂ ꢓꢆꢗ
ꢅꢁꢡꢂ Rꢈꢕ
RꢈꢗꢌꢛꢛꢈꢋDꢈD ꢆꢌꢚDꢈR ꢒꢏD ꢒꢇꢍꢗꢟ ꢏꢋD Dꢇꢛꢈꢋꢆꢇꢌꢋꢆ
ꢏꢒꢒꢚꢣ ꢆꢌꢚDꢈR ꢛꢏꢆꢘ ꢍꢌ ꢏRꢈꢏꢆ ꢍꢟꢏꢍ ꢏRꢈ ꢋꢌꢍ ꢆꢌꢚDꢈRꢈD
ꢂꢁꢀꢂ ±ꢂꢁꢃꢂ
ꢀꢁꢂꢂ ±ꢂꢁꢃꢂ
ꢄꢅ ꢆꢇDꢈꢆꢉ
R ꢧ ꢂꢁꢃꢃꢡ
ꢍꢣꢒ
ꢦ
ꢃꢅ
R ꢧ ꢂꢁꢂꢡ
ꢍꢣꢒ
ꢊꢁꢊꢂ ±ꢂꢁꢃꢂ
ꢊꢁꢂꢂ ±ꢂꢁꢃꢂ
ꢄꢅ ꢆꢇDꢈꢆꢉ
ꢃꢁꢦꢂ ±ꢂꢁꢃꢂ
ꢒꢇꢋ ꢃ
ꢍꢌꢒ ꢛꢏRꢘ
ꢄꢋꢌꢍꢈ ꢤꢉ
ꢒꢇꢋ ꢃ ꢋꢌꢍꢗꢟ
R ꢧ ꢂꢁꢅꢂ ꢌR
ꢂꢁꢊꢡ × ꢀꢡ°
ꢗꢟꢏꢛꢕꢈR
ꢄꢙꢈꢃꢅꢩDꢈꢃꢅꢉ Dꢕꢋ ꢂꢪꢂꢤ Rꢈꢔ D
ꢤ
ꢃ
ꢂꢁꢅꢡ ±ꢂꢁꢂꢡ
ꢂꢁꢦꢡ ±ꢂꢁꢂꢡ
ꢂꢁꢅꢂꢂ Rꢈꢕ
ꢂꢁꢡꢂ ꢓꢆꢗ
ꢅꢁꢡꢂ Rꢈꢕ
ꢓꢌꢍꢍꢌꢛ ꢔꢇꢈꢐꢥꢈꢞꢒꢌꢆꢈD ꢒꢏD
ꢂꢁꢂꢂ ꢨ ꢂꢁꢂꢡ
ꢋꢌꢍꢈꢎ
ꢃꢁ DRꢏꢐꢇꢋꢑ ꢒRꢌꢒꢌꢆꢈD ꢍꢌ ꢓꢈ ꢏ ꢔꢏRꢇꢏꢍꢇꢌꢋ ꢌꢕ ꢔꢈRꢆꢇꢌꢋ
ꢄꢐꢑꢈDꢉ ꢇꢋ ꢖꢈDꢈꢗ ꢒꢏꢗꢘꢏꢑꢈ ꢌꢙꢍꢚꢇꢋꢈ ꢛꢂꢜꢅꢅꢝ
ꢅꢁ DRꢏꢐꢇꢋꢑ ꢋꢌꢍ ꢍꢌ ꢆꢗꢏꢚꢈ
ꢊꢁ ꢏꢚꢚ Dꢇꢛꢈꢋꢆꢇꢌꢋꢆ ꢏRꢈ ꢇꢋ ꢛꢇꢚꢚꢇꢛꢈꢍꢈRꢆ
Rev D
20
For more information www.analog.com
LT4356-3
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1ꢀꢀ1 Rev F)
0.889 0.127
(.035 .005)
5.10
(.201)
MIN
3.20 – 3.45
(.12ꢀ – .13ꢀ)
3.00 0.102
(.118 .004)
(NOTE 3)
(.0197)
0.497 0.07ꢀ
(.019ꢀ .003)
REF
0.50
0.305 0.038
(.0120 .0015)
TYP
10 9
8
7 ꢀ
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .00ꢀ)
DETAIL “A”
0.254
(.010)
0° – ꢀ° TYP
GAUGE PLANE
1
2
3
4 5
0.53 0.152
(.021 .00ꢀ)
0.8ꢀ
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.101ꢀ 0.0508
(.004 .002)
0.50
(.0197)
BSC
MSOP (MS) 0213 REV F
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Rev D
For more information www.analog.com
21
LT4356-3
PACKAGE DESCRIPTION
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
ꢆReꢧeꢨeꢩꢪe ꢝꢍꢚ Dꢢꢘ ꢫ ꢁꢅꢬꢁꢋꢬꢂꢃꢂꢁ Rev ꢘꢊ
ꢀꢐꢋꢃ ꢄ ꢀꢐꢓꢇ
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ꢂꢃ
ꢑ
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ꢂꢇ
ꢂꢐ
ꢂꢈ
ꢂꢂ
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ꢓ
ꢑ
ꢂ
ꢀꢈꢇꢅ
ꢛꢜꢑ
ꢀꢂꢃꢁ ꢀꢁꢁꢅ
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ꢆꢐꢀꢋꢂꢁ ꢄ ꢐꢀꢓꢋꢋꢊ
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ꢆꢅꢀꢉꢓꢂ ꢄ ꢃꢀꢂꢓꢉꢊ
ꢈ
ꢐ
ꢑꢒꢈ
ꢑꢒꢈ
ꢋ
ꢀꢁꢐꢁ ꢀꢁꢁꢅ
ꢍꢎꢏ
RꢕꢚꢔꢛꢛꢕꢑDꢕD ꢖꢔꢝDꢕR ꢏꢞD ꢝꢞꢎꢔꢟꢍ
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ꢐ
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ꢉ
ꢂ
ꢇ
ꢀꢁꢂꢁ ꢄ ꢀꢁꢈꢁ
ꢆꢁꢀꢈꢅꢇ ꢄ ꢁꢀꢅꢁꢋꢊ
× ꢇꢅ°
ꢀꢁꢅꢐ ꢄ ꢀꢁꢃꢓ
ꢆꢂꢀꢐꢇꢃ ꢄ ꢂꢀꢉꢅꢈꢊ
ꢀꢁꢁꢇ ꢄ ꢀꢁꢂꢁ
ꢆꢁꢀꢂꢁꢂ ꢄ ꢁꢀꢈꢅꢇꢊ
ꢀꢁꢁꢋ ꢄ ꢀꢁꢂꢁ
ꢆꢁꢀꢈꢁꢐ ꢄ ꢁꢀꢈꢅꢇꢊ
ꢁꢌ ꢄ ꢋꢌ ꢍꢎꢏ
ꢀꢁꢅꢁ
ꢆꢂꢀꢈꢉꢁꢊ
ꢙꢖꢚ
ꢀꢁꢂꢇ ꢄ ꢀꢁꢂꢓ
ꢆꢁꢀꢐꢅꢅ ꢄ ꢁꢀꢇꢋꢐꢊ
ꢍꢎꢏ
ꢀꢁꢂꢃ ꢄ ꢀꢁꢅꢁ
ꢆꢁꢀꢇꢁꢃ ꢄ ꢂꢀꢈꢉꢁꢊ
ꢖꢂꢃ Rꢕꢗ ꢘ ꢁꢈꢂꢈ
ꢑꢔꢍꢕꢡ
ꢂꢀ Dꢜꢛꢕꢑꢖꢜꢔꢑꢖ ꢜꢑ
ꢜꢑꢚꢠꢕꢖ
ꢆꢛꢜꢝꢝꢜꢛꢕꢍꢕRꢖꢊ
ꢈꢀ DRꢞꢢꢜꢑꢘ ꢑꢔꢍ ꢍꢔ ꢖꢚꢞꢝꢕ
ꢐꢀ ꢍꢠꢕꢖꢕ Dꢜꢛꢕꢑꢖꢜꢔꢑꢖ Dꢔ ꢑꢔꢍ ꢜꢑꢚꢝꢟDꢕ ꢛꢔꢝD ꢣꢝꢞꢖꢠ ꢔR ꢏRꢔꢍRꢟꢖꢜꢔꢑꢖꢀ
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ꢇꢀ ꢏꢜꢑ ꢂ ꢚꢞꢑ ꢙꢕ ꢙꢕꢗꢕꢝ ꢕDꢘꢕ ꢔR ꢞ Dꢜꢛꢏꢝꢕ
Rev D
22
For more information www.analog.com
LT4356-3
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
12/09 Revise Features and Description
1
Update Absolute Maximum Ratings, Pin Configuration, Order Information and Electrical Characteristics to Include
H-grade
2-4
Revise Pin Functions
7
8
Revise Block Diagram
Minor Text Edits to Operation Section
Text Added to Applications Information
Update Typical Applications
9
12, 15
18, 19
2, 3, 4
7
B
C
D
8/12
9/17
4/19
Added MP-Grade
Updated TMR pin function with minimum recommended capacitance
Updated: SHDN Pin Function; Block Diagram; Operation section
7, 8, 9
Rev D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
23
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT4356-3
TYPICAL APPLICATION
Overvoltage Regulator with Linear Regulator Up to 100mA
Q1
2N2905A
2.5V, 100mA
C5
10µF
R
M1
IRLR2908
SNS
10mΩ
V
V
OUT
12V, 3A
CLAMPED AT 16V
IN
12V
D2*
SMAJ58A
R3
R1
10Ω
59k
5
4
3
SNS
GATE
OUT
R6
100k
6
2
V
A
FB
CC
R2
4.99k
R4
249k
C3
47nF
LT4356DE-3
11
7
12
8
+
IN
OUT
R5
249k
SHDN
FLT
9
EN
GND
10
TMR
*DIODES INC.
43563 TA09
1
C
TMR
0.1µF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1696
Overvoltage Protection Controller
ThinSOT™ Package, 2.7V to 28V
LTC1735
High Efficiency Synchronous Step-Down
Switching Regulator
Output Fault Protection, 16-Pin SSOP
LTC1778
No R
™ Wide Input Range Synchronous
Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
≤ (0.9)(V ),
OUT IN
SENSE
IN
Step-Down Controller
I
Up to 20A
OUT
LTC2909
Triple/Dual Inputs UV/OV Negative Monitor
Single/Dual UV/OV Voltage Monitor
Quad UV/OV Monitor
Pin Selectable Input Polarity Allows Negative and OV Monitoring
Ads UV and OV Trip Values, 1.5% Threshold Accuracy
For Positive and Negative Supplies
LTC2912/LTC2913
LTC2914
LTC3727/LTC3727-1 2-Phase, Dual, Synchronous Controller
LTC3827/LTC3827-1 Low I , Dual, Synchronous Controller
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 14V
IN
OUT
OUT
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V, 80µA Quiescent Current
Q
IN
LTC3835/LTC3835-1 Low I , Synchronous Step-Down Controller
Single Channel LTC3827/LTC3827-1
4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, 120µA Quiescent Current
Q
LT3845
Low I , Synchronous Step-Down Controller
Q
IN
OUT
LTC3850
Dual, 550kHz, 2-Phase Synchronous Step-Down Dual 180° Phased Controllers, V 4V to 24V, 97% Duty Cycle, 4mm × 4mm
IN
Controller
QFN-28, SSOP-28 Packages
LT4256-1/LT4256-2 Positive 48V Hot Swap Controller with
Open-Circuit Detect
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to
80V Supply
LTC4260
Positive High Voltage Hot Swap Controller with
ADC and I C
Wide Operating Range 8.5V to 80V
2
LTC4352
LTC4354
LTC4355
LTC4380
Ideal MOSFET ORing Diode
External N-channel MOSFETs Replace ORing Diodes, 0V to 18V
Controls Two N-channel MOSFETs, 1µs Turn-Off, 80V Operation
Controls Two N-channel MOSFETs, 0.5µs Turn-Off, 80V Operation
Negative Voltage Diode-OR Controller
Positive Voltage Diode-OR Controller
Low Quiescent Current Surge Stopper
8µA I ; 4V to 72V Operation; –60V Reverse Input Protection
Q
Rev D
04/19
www.analog.com
ANALOG DEVICES, INC. 2009-2019
24
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