LT6556CGN#TR_技术文档

LT6556

750MHz Gain of 1 Triple

2:1Video Multiplexer

U

DESCRIPTIO

FEATURES

®

■

750MHz –3dB Small Signal Bandwidth

The LT 6556 is a high speed triple 2:1 video multiplexer

■

450MHz –3dB 2V Large-Signal Bandwidth

with an internally ﬁxed gain of 1. The individual buffers

are optimized for performance with a 1k load and feature a

P-P

■

120MHz 0ꢀ1dB Bandwidth

High Slew Rate: 2100V/µs

2V –3dB bandwidth of 450MHz, making them ideal for

P-P

Fixed Gain of 1; No External Resistors Required

72dB Channel Separation at 10MHz

52dB Channel Separation at 100MHz

drivingveryhighresolutionvideosignals. Separatepower

supply pins for each ampliﬁer boost channel separation

to 72dB, allowing the LT6556 to excel in many high speed

applications.

–84dBc 2nd Harmonic Distortion at 10MHz, 2V

P-P

–87dBc 3rd Harmonic Distortion at 10MHz, 2V

Low Supply Current: 9.5mA per Ampliﬁer

6.5ns 0.1% Settling Time for 2V Step

While the performance of the LT6556 is optimized for dual

supplyoperation, itcanalsobeoperatedwithasinglesup-

ply as low as 4.5V. Using dual 5V supplies, each ampliﬁer

draws only 9.5mA. When disabled, the ampliﬁers draw

less than 330µA and the outputs become high impedance.

For applications requiring a ﬁxed gain of 2, refer to the

LT6555 datasheet.

I

SS

≤ 330µA per Ampliﬁer When Disabled

Differential Gain of 0.033%, Differential Phase of 0.022°

Wide Supply Range: 2.25V ꢀ4.5Vꢁ to 6V ꢀ12Vꢁ

Available in 24-Lead SSOP and 24-Lead QFN Packages

U

TheLT6556isavailablein24-leadSSOPandultra-compact

24-lead QFN packages.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

APPLICATIO S

■

RGB Buffers

■

UXGA Video Multiplexing

■

LCD Projectors

U

TYPICAL APPLICATIO

RGB Multiplexer and Line Driver

Large-Signal Transient Response

+

V

R

G

B

LT6556

INA

1.5

75Ω

V

= 2V

P-P

IN

S

L

= ±5V

= 1k

×1

R

G

OUT

1.0

0.5

R

1k

T

= 25°C

A

75Ω

0

AGND

75Ω

×1

OUT

–0.5

–1.0

–1.5

R

INB

G

INB

B

INB

75Ω

0

2

4

6

8

10 12 14 16 18 20

TIME (ns)

×1

B

OUT

75Ω

6556 TA02

SELECT A/B

V

REF

75Ω

ENABLE

DGND

–

6556 TA01

V

6556f

1

LT6556

W W U W

ABSOLUTE AXI U RATI GS _{(Note 1)}

+

–

Total Supply Voltage ꢀV to V ꢁ .............................12.6V

Input Current ꢀNote 2ꢁ ......................................... 10mA

Output Current ꢀContinuousꢁ .............................. 70mA

EN to DGND Voltage ꢀNote 2ꢁ ..................................5.5V

SEL to DGND Voltage ꢀNote 2ꢁ....................................8V

Output Short-Circuit Duration ꢀNote 3ꢁ ............ Indeﬁnite

Operating Temperature Range ꢀNote 4ꢁ ... –40°C to 85°C

Speciﬁed Temperature Range ꢀNote 5ꢁ .... –40°C to 85°C

Junction Temperature

SSOP ................................................................ 150°C

QFN................................................................... 125°C

Storage Temperature Range

SSOP ................................................. –65°C to 150°C

QFN.................................................... –65°C to 125°C

Soldering Temperature ꢀ10 secꢁ............................ 300°C

U

W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

+

1

2

V

24

23

22

21

20

19

18

17

16

15

14

13

IN1A

DGND

IN2A

EN

24 23 22 21 20 19

+

3

SEL A/B

+

V

1

2

3

4

5

6

18

17

16

V

REF

4

V

REF

IN3A

OUT1

G=+1

5

OUT1

–

IN3A

AGND1

IN1B

AGND1

V

25

–

6

V

15 OUT2

+

7

OUT2

+

IN1B

14

V

8

V

AGND2

IN2B

AGND2

13 OUT3

9

OUT3

–

7

8

9 10 11 12

10

11

12

V

AGND3

IN3B

+

V

+

–

V

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

V

GN PACKAGE

T

= 125°C, θ = 37°C/W, θ = 2.6°C/W

JA JC

JMAX

24-LEAD PLASTIC SSOP

–

EXPOSED PAD ꢀPIN 25ꢁ IS V

MUST BE SOLDERED TO PCB

T

= 150°C, θ = 90°C/W

JA

JMAX

ORDER PART NUMBER

GN PART MARKING

ORDER PART NUMBER

UF PART MARKING*

6556

LT6556CGN

LT6556IGN

LT6556CGN

LT6556IGN

LT6556CUF

LT6556IUF

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

ELECTRICAL CHARACTERISTICS ^{The denotes the speciﬁcations which apply over the full operating}

temperature range, otherwise speciﬁcations are at T_A= 25°Cꢀ V_S= 5V, R_L= 1k, C_L= 1ꢀ5pF, V_EN= 0ꢀ4V, V_AGND, V_DGND, V_VREF= 0Vꢀ

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

18

mV

V

Offset Voltage

V

= 0V, V = V

OUT

67

75

OS

IN

OS

●

µA

I

IN

Input Current

–12

500

1

45

100

51

R

Input Resistance

V

=

1V

kΩ

IN

pF

C

IN

Input Capacitance

Power Supply Rejection Ratio

f = 100kHz

V = 2.25V to 6V (Note 6)

PSRR

62

dB

S

6556f

2

LT6556

ELECTRICAL CHARACTERISTICS ^{The denotes the speciﬁcations which apply over the full operating}

temperature range, otherwise speciﬁcations are at T_A= 25°Cꢀ V_S= 5V, R_L= 1k, C_L= 1ꢀ5pF, V_EN= 0ꢀ4V, V_AGND, V_DGND, V_VREF= 0Vꢀ

SYMBOL

PARAMETER

CONDITIONS

V = 2.25V to 6V (Note 6)

MIN

–2.8

3.65

TYP

MAX

UNITS

µA/V

%

●

1

I

Input Current Power Supply Rejection

Gain Error

3

PSRR

S

A ERR

V

= V =

REF

2V, Nominal Gain 1V/V

–1.15

0.05

3.85

9.5

0

OUT

%

A MATCH

V

Gain Matching

Any One Channel to Another

(Note 7)

●

V

OUT

Output Voltage Swing

Supply Current, Per Ampliﬁer

13

14.5

mA

I

S

R = ∞

L

●

47

42

330

µA

Supply Current, Disabled, Per Ampliﬁer

Enable Pin Current

V

= 4V, R = ∞

EN

L

= Open, R = ∞

L

●

I

V

= 0.4V

= 4V

–200

–75

–95

–21

EN

●

µA

mA

Select Pin Current

V

= 0.4V

= 4V

–50

50

–5

–1

105

2100

750

SEL

SC

SEL

●

Output Short-Circuit Current

Slew Rate

R = 0Ω, V

=

2V, V =

1V

L

IN

REF

1200

SR

1V on 2.2V Output Step (Note 8)

V/µs

MHz

–3dB BW

0.1dB BW

FPBW

Small-Signal –3dB Bandwidth

Gain Flatness 0.1dB Bandwidth

V

= 200mV

OUT

P-P

120

190

335

175

MHz

dB

Full Power Bandwidth 2V

Full Power Bandwidth 4V

All-Hostile Crosstalk

V

= 2V (Note 9)

P-P

OUT

= 4V (Note 9)

P-P

f = 10MHz, V = 2V

f = 100MHz, V = 2V

–72

–52

IN

P-P

dB

Selected Channel to Unselected

Channel Crosstalk

f = 10MHz, V = 2V

–85

–64

IN

P-P

f = 100MHz, V = 2V

IN

200

Channel Select Output Transient

Channel-to-Channel Select Time

INA = INB = 0V

mV

P-P

8

ns

INA = –1V, INB = 1V

from 50% SEL to V

= 0V

OUT

6.5

ns

ps

%

t

Settling Time

0.1% of V

, V = 2V

S

FINAL STEP

500

t , t

R

Small-Signal Rise and Fall Time

Differential Gain

10% to 90%, V

(Note 10)

= 200mV

P-P

F

OUT

dG

dP

0.056

0.028

Deg

dBc

Differential Phase

(Note 10)

HD2

HD3

2nd Harmonic Distortion

3rd Harmonic Distortion

f = 10MHz, V

= 2V

–84

–87

OUT

P-P

= 2V

OUT

–

Note 1: Absolute Maximum Ratings are those values beyond which the life

to V + 0.4V, and the SEL pin is set to either V + 0.4V or V + 4V. At 6V

and all other cases, DGND is set to ground and the EN and SEL pins are

referenced from it.

of a device may be impaired.

Note 2: This parameter is guaranteed to meet speciﬁed performance

through design and characterization. It is not production tested.

Note 3: As long as output current and junction temperature are kept

below the Absolute Maximum Ratings, no damage to the part will occur.

Depending on the supply voltage, a heat sink may be required.

Note 4: The LT6556C is guaranteed functional over the operating

temperature range of –40°C to 85°C.

Note 5: The LT6556C is guaranteed to meet speciﬁed performance from

0°C to 70°C. The LT6556C is designed, characterized and expected to

meet speciﬁed performance from –40°C and 85°C but is not tested or

QA sampled at these temperatures. The LT6556I is guaranteed to meet

speciﬁed performance from –40°C to 85°C.

Note 7: The V pin is set to 3V when testing positive swing and –3V

REF

when testing negative swing to ensure that the internal input clamps do

not limit the output swing.

Note 8: Slew rate is 100% production tested using both inputs of

channel 2. Slew rates of channels 1 and 3 are guaranteed through

design and characterization.

Note 9: Full power bandwidth is calculated from the slew rate:

FPBW = SR/ꢀπ • V

ꢁ

P-P

Note 10: Differential gain and phase are measured using a Tektronix

TSG120YC/NTSC signal generator and a Tektronix 1780R video

measurement set. The resolution of this equipment is better than 0.05%

and 0.05°. Nine identical ampliﬁer stages were cascaded giving an

effective resolution of better than 0.0056% and 0.0056°.

Note 6: In order to follow the constraints for 4.5V operation for PSRR

–

and I

testing at 2.25V, the DGND pin is set to V , the EN pin is set

PSRR

6556f

3

LT6556

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current per Ampliﬁer

vs Temperature

Supply Current per Ampliﬁer

vs Supply Voltage

Supply Current per Ampliﬁer

vs EN Pin Voltage

12

10

8

12

10

8

12

10

8

V

T

= ±5V

EN IN DGND SEL

= 25°C

V

R

V

= ±5V

= ∞

L

V

S

= ±5V

= ∞

= 0V

S

, V , V

, V

= 0V

R

IN

L

V

= 0V

EN

= 0V

IN

V

A

V

= 0.4V

EN

T

= –55°C

A

T

= 25°C

A

6

T

= 125°C

A

4

2

V

EN

= 4V

0

1

2

3

4

5

6

7

8

9

10 11 12

0

2.0

3.0 3.5

0.5 1.0 1.5

2.5

4.0

–55 –35 –15

5

25 45 65 85 105 125

EN PIN VOLTAGE (V)

TOTAL SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

6556 G02

6556 G03

6556 G01

Input Bias Current

vs Temperature

EN Pin Current vs EN Pin Voltage

Offset Voltage vs Temperature

25

20

0

–5

0

–20

V

= ±5V

IN

V

= ±5V

S

V

= ±5V

DGND

S

= 0V

V

= 1.5V

IN

–10

–15

–20

–25

–30

–35

–40

15

T

= 125°C

A

–60

V

= 0V

IN

T

= –55°C

A

V

= –1.5V

IN

–80

10

5

T

= 25°C

A

–100

–120

–140

0

25 45

TEMPERATURE (°C)

–55 –35 –15

5

25 45 65

85 105

125

–55 –35 –15

5

65 85 105 125

0

3

4

5

1

2

TEMPERATURE (°C)

EN PIN VOLTAGE (V)

6556 G05

6556 G04

6556 G06

Maximum Output Voltage Swing

vs V_REFPin Voltage

Output Voltage Swing

vs I_LOAD(Output High)

Output Voltage Swing

vs I_LOAD(Output Low)

5

4

5

4

3

0

–1

–2

V

= ±5V

= 1k

V

= ±5V

V

= ±5V

S

L

S

R

= 4V

= –4V

IN

T

= 125°C

T

= –55°C

A

= 3V

= –3V

VREF

3

HIGH SWING

T

= –55°C

2

A

T

= 125°C

A

T

= –55°C

A

1

T

= 25°C

A

T

= 125°C

A

0

T

= 25°C

T

= 125°C

A

T

= 25°C

–1

–2

–3

–4

–5

A

2

1

0

–3

–4

–5

T

= 25°C

A

T

= –55°C

A

LOW SWING

0

0.5

–2 –1.5 –1 –0.5

1

1.5

2

0

10 20 30 40 50 60 70 80 90 100

SOURCE CURRENT (mA)

6556 G08

10 20 30 40 50 60 70 80 90 100

0

V

PIN VOLTAGE (V)

SINK CURRENT (mA)

REF

6556 G07

6556 G09

6556f

4

LT6556

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Input Noise Spectral Density

Input Impedance vs Frequency

PSRR vs Frequency

70

60

50

40

30

20

10

0

1000

100

10

1000

100

10

V

A

= ±5V

V

T

= ±5V

= 25°C

S

A

V

= ±5V

S

A

±PSRR

= 0V

IN

= 25°C

T

= 25°C

T

–PSRR

+PSRR

e

n

i

1

0.1

1

0.001

0.01

0.1

1

10

100

0.01

0.1

1

10

100

1000

0.001

0.01

0.1

1

10

100

FREQUENCY (MHz)

FREQUENCY (kHz)

6556 G12

6556 G11

6556 G10

Frequency Response

vs Output Amplitude

Frequency Response with

Capacitive Loads

Gain Flatness vs Frequency

9

6

0.15

3

V

= ±5V

S

V

= ±5V

= 1k

= 25°C

S

L

V

= ±5V

S

= 200mV

C

= 10pF

OUT

P-P

L

R

2

1

= 200mV

OUT

P-P

R

L

= 1k

0.10

0.05

T

A

R

= 1k

L

T

= 25°C

A

C

= 15pF

L

T

A

= 25°C

IN2B

0

IN3B

IN1A

3

C

= 6.8pF

L

–1

–2

–3

–4

–5

–6

V

= 200mV

OUT

P-P

0

V

= 2V

OUT

P-P

–0.05

C

= 3.3pF

L

V

= 4V

P-P

OUT

–3

–6

IN3A

IN1B

–0.10

–0.15

IN2A

1

C

= 0pF

100

L

0.1

1

10

1000

0.1

10

FREQUENCY (MHz)

100

1000

0.1

1

10

100

1000

FREQUENCY (MHz)

6555 G15

6556 G14

6556 G13

Crosstalk vs Frequency

Harmonic Distortion vs Frequency

0

–10

V

R

T

= ±5V

V

R

T

= ±5V

V

R

T

= ±5V

S

= 2V

OUT

P-P

OUT

P-P

OUT

P-P

–20

= 1k

–20

–40

= 1k

–20

–40

L

= 25°C

A

–30

–40

–50

–60

–80

–60

–80

WORST

ADJACENT

DRIVE IN A;

SELECT IN B

–70

ALL CHANNELS

DRIVEN

–80

HD2

HD3

–90

DRIVE IN B;

SELECT IN A

–100

–110

–120

–100

–120

–100

–120

0.1

1

10

FREQUENCY (MHz)

100

1000

0.01

0.1

1

10

100

0.1

1

10

FREQUENCY (MHz)

100

1000

FREQUENCY (MHz)

6556 G16

6556 G18

6556 G17

6556f

5

LT6556

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Capacitive Load vs

Output Series Resistor

Output Impedance vs Frequency

Small-Signal Transient Response

0.20

0.15

0.10

0.05

0

1000000

100000

10000

1000

100

35

30

25

20

15

10

5

V

= 2V

P–P

OUT

S

= ±5V

= 1k

R

L

DISABLED

EN

T

= 25°C

A

V

= 4V

AC PEAKING

>3dB

–0.05

–0.10

–0.15

–0.20

10

V

= 200mV

= ±5V

IN

S

L

P-P

ENABLED

= O.4V

V

EN

1

V

= ±5V

S

A

R

= 1k

T

= 25°C

T

= 25°C

A

0.1

0

2

4

6

8

10 12 14 16 18 20

0.01

0.1

1

10

100

1000

1

10

100

1000

FREQUENCY (MHz)

TIME (ns)

CAPACITIVE LOAD (pF)

6556 G19

6556 G21

6556 G20

Video Amplitude Transient

Response

Large-Signal Transient Response

Gain Error Distribution

35

30

25

20

15

10

5

2.5

2.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V

= 700mV

V

= 4V

V

= ±5V

S

IN

S

L

P-P

IN

S

L

P-P

= ±5V

= 1k

= ±5V

= 1k

V

= ±2V

OUT

R

= 1k

L

1.5

T

= 25°C

T

A

= 25°C

T

= 25°C

A

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.1

–0.2

0

–1.05

–1.3 –1.25 –1.2 –1.15 –1.1

–1.0 –.95 –.90

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

TIME (ns)

GAIN ERROR—INDIVIDUAL CHANNEL (%)

TIME (ns)

6556 G24

6556 G22

6556 G23

Gain Error Matching Distribution

Channel Switching Transient

40

35

30

25

20

15

10

5

0.15

0.10

0.05

0

1.5

1.0

0.5

0

V

= ±5V

S

= ±2V

OUT

R

L

= 1k

T

= 25°C

A

–0.05

–0.10

–0.5

–1.0

–1.5

V

= ±5V INA = INB = 0V

S

L

R

= 1k

T = 25°C

V

= ±5V INB = 300MHz, 2V SINE

P-P

A

S

L

R

= 1k

T = 25°C INA = 0V

A

5

4

3

2

1

0

5

4

3

2

1

0

0.025

–0.1 –0.075 –0.05 –0.025

0

0.05 0.075 0.1

0

10 20 30 40 50 60 70 80 90 100

TIME (ns)

0

10 20 30 40 50 60 70 80 90 100

TIME (ns)

GAIN ERROR—BETWEEN CHANNELS (%)

6556 G25

6556 G26

6556 G27

6556f

6

LT6556

U

PI FU CTIO S

(GN24 Package)

IN1A (Pin 1): Channel 1 Input A. This pin has a nominal

impedance of 500kΩ and does not have any internal

termination resistor.

be connected externally. Proper supply bypassing is

necessary for best performance. See the Applications

Information section.

DGND (Pin 2): Digital Ground Reference for Enable Pin.

V–(Pin15):NegativeSupplyVoltageforChannel3Output

Stage.V^–pinsarenotinternallyconnectedtoeachotherand

mustallbeconnectedexternally. Propersupplybypassing

is necessary for best performance. See the Applications

Information section.

This pin is normally connected to ground.

IN2A (Pin 3): Channel 2 Input A. This pin has a nominal

impedance of 500kΩ and does not have any internal

termination resistor.

OUT3 (Pin 16): Channel 3 Output. It is the buffered output

of the selected Channel 3 input.

VREF (Pin 4): Voltage Reference for Input Clamping. This

is the tap to an internal voltage divider that deﬁnes mid-

supply. It is normally connected to ground in dual supply,

DC coupled applications.

V+ (Pin 17): Positive Supply Voltage for Channels 2 and

+

3 Output Stages. V pins are not internally connected to

each other and must all be connected externally. Proper

supply bypassing is necessary for best performance. See

the Applications Information section.

IN3A (Pin 5): Channel 3 Input A. This pin has a nominal

impedance of 500kΩ and does not have any internal

termination resistor.

OUT2 (Pin 18): Channel 2 Output. It is the buffered output

of the selected Channel 2 input.

AGND (Pin 6): Analog Ground for Isolation between IN3A

andIN1B.AGNDpinshaveESDprotectionandshouldnotbe

connected to potentials outside the power supply range.

V– (Pin 19): Negative Supply Voltage for Channels 1 and

2 Output Stages. V^–pins are not internally connected to

each other and must all be connected externally. Proper

supply bypassing is necessary for best performance. See

the Applications Information section.

IN1B (Pin 7): Channel 1 Input B. This pin has a nominal

impedance of 500kΩ and does not have any internal

termination resistor.

AGND (Pin 8): Analog Ground for Isolation between IN1B

andIN2B.AGNDpinshaveESDprotectionandshouldnotbe

connected to potentials outside the power supply range.

OUT1 (Pin 20): Channel 1 Output. It is the buffered output

of the selected Channel 1 input.

V+ (Pin 21): Positive Supply Voltage for Channel 1 Output

IN2B (Pin 9): Channel 2 Input B. This pin has a nominal

impedance of 500kΩ and does not have any internal

termination resistor.

+

Stage.V pinsarenotinternallyconnectedtoeachotherand

mustallbeconnectedexternally. Propersupplybypassing

is necessary for best performance. See the Applications

Information section.

AGND (Pin 10): Analog Ground for Isolation between

IN2B and IN3B. AGND pins have ESD protection and

should not be connected to potentials outside the power

supply range.

SEL A/B (Pin 22): Select Pin. This high impedance pin

selects which set of inputs are sent to the output pins.

Whenthepinispulledlow, theAinputsareselected. When

the pin is pulled high, the B inputs are selected.

IN3B (Pin 11): Channel 3 Input B. This pin has a nominal

impedance of 500kΩ and does not have any internal

termination resistor.

V– (Pin 12): Negative Supply Voltage. V^–pins are not in-

ternally connected to each other and must all be connected

externally. Proper supply bypassing is necessary for best

performance. See the Applications Information section.

EN(Pin23):EnableControlPin.Aninternalpull-upresistor

of 46k deﬁnes the pin’s impedance and will turn the part

off if the pin is unconnected. When the pin is pulled low,

the ampliﬁers are enabled.

Exposed Pad (Pin 25, QFN Only): The Exposed Pad is

–

V and must be soldered to the PCB. It is internally con-

+

–

V+ (Pins 13, 14, 24): Positive Supply Voltage. V pins

nected to the QFN Pin 4, V .

are not internally connected to each other and must all

6556f

7

LT6556

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APPLICATIO S I FOR ATIO

Power Supplies

The enable/disable times of the LT6556 are fast when

driven with a logic input. Turn on ꢀfrom 50% EN input to

50% outputꢁ typically occurs in less than 50ns. Turn off

is slower, but is typically below 500ns.

The LT6556 is optimized for 5V supplies but can be op-

erated on as little as 2.25V or a single 4.5V supply and

as much as 6V or a single 12V supply. Internally, each

supply is independent to improve channel isolation. Do

not leave any supply pins disconnected or the part may

not function correctly!

Channel Select

The SEL pin uses the same internal threshold as the EN

pin and is also referenced to DGND. When the pin is logic

low, the channel A inputs are passed to the output. When

the pin is logic high, the channel B inputs are passed to

the output. The pin should not be ﬂoated but can be tied

to DGND to force the outputs to always be channel A or

Enable/Shutdown

The LT6556 has a shutdown mode controlled by the EN

pinandreferencedtotheDGNDpin. Iftheampliﬁerwillbe

enabled at all times, the EN pin can be connected directly

to DGND. If the enable function is desired, either driving

the pin above 2V or allowing the internal 46k pull-up

resistor to pull the EN pin to the top rail will disable the

ampliﬁer. When disabled, the output will become very

high impedance. Supply current into the ampliﬁer in the

disabled state will be:

+

to V ꢀwhen less than 8Vꢁ to force the outputs to always

be channel B.

Truth Table

SEL A/B

EN

0

OUT

IN A

IN B

OFF

0

1

X

0

1

V⁺– V_EN

46k

V⁺– V^–

80k

I_S=

+

Input Considerations

It is important that the following constraints on the DGND,

EN and SEL pins are always followed:

The LT6556 uses input clamps referenced to the V pin

REF

to prevent damage to the input stage on the unselected

+

channel.Threetransistorsinserieslimittheinputvoltageto

V – V

≥ 4ꢀ5V

DGND

within three diode drops ꢀ ꢁ from V . V

is nominally

REF REF

-0ꢀ5V ≤ V – V

SEL

≤ 5ꢀ5V

EN

DGND

set to half of the sum of the supplies by the 40k resistors.

A simpliﬁed schematic is shown in Figure 1.

V

– V

≤ 8V

DGND

+

In dual supply cases where V is less than 4.5V, DGND

should be connected to a potential below ground, such as

+

V

–

V . Since the EN and SEL pins are referenced to DGND, they

40k

mayneedtobepulledbelowgroundinthosecases.However,

in order to protect the internal enable circuitry, the EN pin

should not be forced more than 0.5V below DGND.

In single supply applications above 5.5V, an additional

resistor may be needed from the EN pin to DGND if the

pin is ever allowed to ﬂoat. For example, on a 12V single

supply, a 33k resistor would protect the pin from ﬂoating

too high while still allowing the internal pull-up resistor

to disable the part.

IN

V

REF

40k

–

6556 F01

V

–

Ondual 2.25Vsupplies, connectingtheDGNDpintoV is

Figure 1ꢀ Simpliﬁed Schematic of V_REFPin and Input Clamping

+

the only way of ensuring that V – V

≥ 4.5V.

DGND

6556f

8

LT6556

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APPLICATIO S I FOR ATIO

To improve clamping, the pin’s DC impedance should be

minimized by connecting the V pin directly to ground

Layout and Grounding

REF

It is imperative that care is taken in PCB layout in order to

beneﬁt from the very high speed and very low crosstalk of

the LT6556. Separate power and ground planes are highly

recommended and trace lengths should be kept as short

as possible. If input traces must be run over a distance of

several centimeters, they should use a controlled imped-

ance with either series or shunt terminations ꢀnominally

50Ω or 75Ωꢁ to maintain signal ﬁdelity.

in the symmetric dual supply case with a common mode

voltage of 0V. If the common mode voltage is not centered

at ground or the input voltage exceeds plus or minus three

diodes from ground, an external resistor to either supply

can be added to shift the V voltage to the desired level.

REF

–

The only way to cover the full input voltage range of V +

+

1V to V – 1V is to shift V up or down.

REF

The V pin can also be directly driven with a DC source.

REF

Care should be taken to minimize capacitance on the

LT6556’s output traces by increasing spacing between

traces and adjacent metal and by eliminating metal planes

in underlying layers. To drive cable or traces longer than

several centimeters, using the LT6555 with its ﬁxed gain

of+2inconjunctionwithseriesandloadterminationresis-

tors may provide better results.

Figure 2 shows the effect of the clamp on input current

when sweeping input voltage with various V

pin volt-

REF

ages. Bypassing the V pin is not necessary.

REF

250

V

= –2V

= –1V

= 0V

= 1V

= 2V

REF

200

150

100

50

A plot of AC performance driving a 1k load with various

tracelengthsisshowninFigure3. Alldataisfroma4-layer

board with 2oz copper, 18mil of board layer thickness to

the ground plane, a trace width of 12mils and spacing to

adjacent metal of 18mils. The 0.2cm output trace places

the 1k resistor as close to the part as possible, while the

other curves show the load resistor consecutively further

away. The worst case, 4cm, trace has almost 10pF of

parasitic capacitance.

0

–50

–100

–150

–200

–250

T

= 25°C

= ±5V

A

S

V

0

1

–4 –3 –2 –1

2

3

4

INPUT VOLTAGE (V)

6556 F02

Figure 2ꢀ Input Current vs Input Voltage

at Different V_REFVoltages

6

V

= ±5V

S

= 200mV

OUT

P-P

4

2

R

= 1k

L

4cm TRACE

T

A

= 25°C

The inputs can be driven beyond the point at which the

output clips so long as input currents are limited to less

than 10mA. Continuing to drive the input beyond the

output limit can result in increased current drive and

slightly increased swing, but will also increase supply

current and may result in delays in transient response

at larger levels of overdrive.

2cm TRACE

0.2cm TRACE

0

–2

–4

–6

0.1

10

FREQUENCY (MHz)

100

1000

1

6556 F03

Figure 3ꢀ Response vs Output Trace Length

6556f

9

LT6556

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APPLICATIO S I FOR ATIO

In order to counteract any peaking in the frequency re-

sponse from driving a capacitive load, a series resistance

can be inserted in the line at the output of the part to ﬂat-

ten the response. Figure 4 shows the frequency response

with the same 4cm trace from Figure 3, now with a 10Ω

series resistor inserted near the output pin of the ampli-

ﬁer. Note that using a 10Ω series resistor with a 1k load

only decreases the output amplitude by 0.1dB or 1% and

has a minimal effect on the bandwidth of the system. See

the graph labeled “Maximum Capacitive Load vs Output

SeriesResistor”intheTypicalPerformanceCharacteristics

section for more information.

To maintain the LT6556’s channel isolation, it is beneﬁcial

to shield parallel input and parallel output traces using a

ground plane or power supply traces. Vias between top-

side and backside metal may be required to maintain a

low inductance ground near the part where numerous

traces converge. See Figures 7 and 8 for photos of an

optimized layout.

Single Supply Operation

Figure 5 illustrates how to use the LT6556 with a single

supplyrangingfrom4.5Vto12V. Sincetheoutputrangeis

comparabletotheinputrange,theDCbiaspointattheinput

canbesetanywherebetweenthesuppliesthatwillprevent

the AC-coupled signal from running into the output range

limits. As shown, the DC input level is mid-supply.

6

V

= ±5V

S

= 200mV

OUT

P-P

4

2

R

= 1k

L

4cm TRACE

T

= 25°C

A

The only additional power dissipation in the single supply

conﬁgurationisthroughtheresistorbiasstringattheinput

and through any load resistance at the output. In many

cases, the output can be used to directly drive other single

supply devices without additional coupling and without

any resistive load.

0

4cm TRACE

S, OUT

R

= 10Ω

–2

–4

–6

4.5V TO 12V

0.1

10

FREQUENCY (MHz)

100

1000

1

6556 F04

5k

22μF

Figure 4ꢀ Response vs Series Output Resistance

+

V

IN

V

IN

OUT

1/3

LT6556

While the AGND pins on the LT6556 are not connected to

the ampliﬁer circuitry, tying them to ground or another

“quiet” node signiﬁcantly increases channel isolation

and is always recommended. The AGND pins do have

ESD protection and therefore should not be connected to

potentials outside the power supply range.

AGND

5k

–

V

6556 F05

Figure 5ꢀ Single Supply Conﬁguration, One Channel Shown

LowESL/ESRbypasscapacitorsshouldbeplacedasclose

to the positive and negative supply pins as possible. One

Input Expansion

+

4700pF ceramic capacitor is recommended for both V

In applications with more than two inputs per channel,

multipleLT6556scanbeconnecteddirectlytogetheratthe

outputs. Logic circuitry can be used to drive the EN pins

of each LT6556 to ensure that only one set of channels is

buffered at a time. See Figure 9 for a schematic.

–

andV supplybusses.Additional470pFceramiccapacitors

with minimal trace length on each supply pin will further

improve AC and transient response as well as channel

isolation. For high current drive and large-signal transient

applications, additional 1µF to 10µF tantalums should

be added on each supply. The smallest value capacitors

should be placed closest to the package.

Since the output impedance of a disabled LT6556 is high,

adding additional channels will not resistively load an

6556f

10

LT6556

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APPLICATIO S I FOR ATIO

enabledoutput.However,sincethedisabledLT6556andits

traces have around 6pF of capacitance, it may be desirable

toresistivelyisolatetheoutputsofeachchanneltomaintain

ﬂat frequency response as shown in the graph labeled

“Maximum Capacitive Load vs Output Series Resistor” in

the Typical Performance Characteristics section.

ESD Protection

TheLT6556hasreverse-biasedESDprotectiondiodesonall

pins. If any pins are forced a diode drop above the positive

supply or a diode drop below the negative supply, large

currents may ﬂow through these diodes. If the current is

kept below 10mA, no damage to the devices will occur.

U

TYPICAL APPLICATIO

RGB Multiplexer Demo Board

traces and isolate the part from any capacitive loading in

those traces, they also contribute to gain error if the out-

put is not terminated with high impedance. For example,

if the output is terminated with a 1k load, the 75Ω back

termination will cause a 7% gain error. Decreasing the

value of the back termination resistors will decrease the

signal attenuation but may compromise the AC response.

However, connecting the LT6556 output pins to the output

tracesontheDC892Aboardwithoutsomeseriesresistance

is not recommended; 10Ω to 20Ω is generally sufﬁcient.

Figures7and8showthetopandbottomsideboardlayout

and placement.

The DC892A Demo Board illustrates optimal routing,

bypassing and termination using the LT6556 as an

RGBvideomultiplexer.TheschematicisshowninFigure 6.

All inputs and outputs are routed to have a characteristic

impedance of 75Ω and 75Ω input shunt and output series

terminations are connected as close to the part as pos-

sible. The board is fabricated with four layers with internal

ground and power planes.

While the 75Ω back termination resistors at the outputs

of the LT6556 minimize signal reﬂections in the output

E1

EN

E4

SEL A/B

J8

J1

50Ω BNC

Z = 50

1

R7

20k

JP1

2

EN

SEL A/B

E2

DGND

R8

50Ω

OPT

R9

50Ω

OPT

CONTROL

A

B

1

3

1

3

V

CC

2

JP4

SEL

EXT ENABLE

5

4 3 2

DGND

5

4

3

2

DGND

JP2

DGND

3

1

2

FLOAT AGND

E5

REF

V

J2

BANANA JACK

JP5

REF

V

3

1

V

CC

3.3V TO 5V

2

C1

C2

C3

C10

C4

C7

0.33μF

10V

BNC × 6

EXT GND

4700pF

470pF

4700pF

10μF

16V

1206

5

JP12

U1 LT6556CUF

IN1A

V

CC

1

L1 Z = 75

22

23

24

1

21

4

3

2

+

V

IN1A

DGND

20 EN

DGND

IN2A

EN

5

4

3

2

5

4

3

2

5

4

3

2

5

4

3

2

JP13

JP14

JP5

1

SEL

19

18

17

16

15

14

13

12

IN2A

IN3A

IN1B

IN2B

IN3B

SEL A/B

V

BNC × 3

REF

+

V

R1

75Ω

REF

J9

5

4

3

2

5

4

3

2

5

4

3

2

Z = 75

L2

1

2

IN3A

OUT1

OUT2

OUT3

3

–

AGND1

IN1B

V

R2

75Ω

J10

J11

L2

5

OUT2

6

+

AGND2

IN2B

V

R3

75Ω

JP6

7

OUT3

8

–

AGND3

IN3B

V

5

4

3

2

JP7

9

4

11

10

+

V

R10

75Ω

R11

75Ω

R12

75Ω

R4

R5

75Ω

R6

–

+

J4

–

V

75Ω

BANANA JACK

25

V

EE

E3

AGND

–3.3V TO –5V

C5

4700pF

C6

470pF

C9

C8

0.33μF

10V

10μF

16V

1206

J3

BANANA JACK

SINGLE DUAL

2

V

EE

6556 F06

AGND

NOTE:

1

3

JP3

SUPPLY

470pF BYPASS CAPACITORS LOCATED

AS CLOSE TO PINS AS POSSIBLE

Figure 6ꢀ Demo Board Schematic

6556f

11

LT6556

U

TYPICAL APPLICATIO

Figure 7ꢀ Demo Board Topside

(IC Removed for Clarity)

Figure 8ꢀ Demo Board Bottom Side

6556f

12

LT6556

W

SI PLIFIED SCHE ATIC

(One channel shown)

6556f

13

LT6556

U

PACKAGE DESCRIPTIO

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.337 – .344*

(8.560 – 8.738)

.033

(0.838)

REF

24 23 22 21 20 19 18 17 16 15 14 13

.045 ±.005

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.254 MIN

.150 – .165

1

2

3

4

5

6

7

8

9 10 11 12

.0165 ±.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

.015 ± .004

(0.38 ± 0.10)

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN24 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

6556f

14

LT6556

U

PACKAGE DESCRIPTIO

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

0.70 ±0.05

4.50 ± 0.05

3.10 ± 0.05

2.45 ± 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

R = 0.115

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 × 45° CHAMFER

0.75 ± 0.05

4.00 ± 0.10

(4 SIDES)

TYP

23 24

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

1

2

2.45 ± 0.10

(4-SIDES)

(UF24) QFN 0105

0.200 REF

0.25 ± 0.05

0.00 – 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

6556f

InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,

no responsibility is assumed for its use. Linear Technology Corporation makes no representation that

the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LT6556

U

TYPICAL APPLICATIO

RED 1

GREEN 1

BLUE 1

+

LT6556 #1

×1

V

5V

75Ω

IN1A

IN1B

OUT1

OUT2

OUT3

IN2A

IN2B

×1

RED 2

GREEN 2

BLUE 2

IN3A

IN3B

AGND

DGND

SEL

EN

V

R

G

REF

OUT

–

V

–2V

5V

OUT

RED 3

GREEN 3

BLUE 3

+

LT6556 #2

V

75Ω

IN1A

IN1B

OUT1

OUT2

OUT3

B

OUT

×1

IN2A

IN2B

RED 4

GREEN 4

BLUE 4

IN3A

IN3B

AGND

DGND

SEL1 SEL0 OUTPUT

SEL

EN

0

1

0

1

0

1

2

3

4

V

REF

–

SEL0

SEL1

V

NC7SZ14

6556 F09

–2V

Figure 9ꢀ 4:1 RGB Multiplexer

RELATED PARTS

PART NUMBER

LT1203

DESCRIPTION

COMMENTS

Single SPDT Video Switch

0.1dB Gain Flatness to 150MHz, Shutdown

150MHz Single 2:1 Multiplexer

LT1399

300MHz Triple Current Feedback Ampliﬁer

250MHz Triple RGB Multiplexer

LT1675

100MHz Pixel Switching, 1100V/µs Slew Rate, 16-Lead SSOP

110MHz Gain of 2 Buffers in MS Package

LT6550/LT6551

LT6553

3.3V Triple and Quad Video Buffers

650MHz Gain of 2 Triple Video Ampliﬁer

650MHz Gain of 1 Triple Video Ampliﬁer

650MHz Gain of 2 Triple Video Multiplexer

Same Pinout as the LT6554 but Optimized for Driving 75Ω Cables

Performance Similar to the LT6556 with One Set of Inputs, 16-Lead SSOP

Same Pinout as the LT6556 but Optimized for Driving 75Ω Cables

LT6554

LT6555

6556f

LT/TP 0805 500 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT6556CGN#TR
厂家：	ADI
描述：	LT6556 - 750MHz Gain of 1 Triple 2:1Video Multiplexer; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C 光电二极管
文件：	总16页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT6556CGN#TR [ADI]

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